Cypress STK14C88-3 User's Manual
Contents
1. V Quantum Trap e Sap 512 X 512 L he POWER STORE CONTROL 6 a A As STATIC RAM RECALL STORE Ag 9 RECALL lt gt HSB A A ARRAY lt CONTROL 512 X 512 A A12 5 i A13 x SOFTWARE DETECT DQ COLUMN I O PO 2 COLUMN DEC ne Lu 17 DQ 3 Lo oo HS EN H T Ao At A A4 Ato DQ rtte Z lt DQ gt H lt p OE D e CE Cypress Semiconductor Corporation Document Number 001 50592 Rev 198 Champion Court San Jose CA 95134 1709 Revised January 29 2009 408 943 2600 Feedback n Q zo gt gt CYPRESS PERFORM Pin Configurations STK14C88 3 Figure 1 Pin Diagram 32 Pin SOIC 32 Pin PDIP Vas 1 Neu 32 1 Ves 2 RS8 L 3 30 WE A 14 Ars As 5 28 As 16 27 777 A A 7 26 8 25 NC 19 View 7 2 10 Not Scale 3 22 CE A n n oo DQ 13 20 po 14 19 DQ 15 18 DQ Vss 16 7 Table 1 Pin Definitions 32 Pin SOIC 32 Pin PDIP Pin Name Alt IO Type Description Ag A14 Input Address2. Parameter 35 ns 45 ns Cypress Description gt Unit Paraieten Alt Min Max Min Max tACE teL QV Chip Enable Access Time 35 45 ns thc 19 tavav tELEH Read Cycle Time 35 45 ns tAA tavav Address Access Time 35 45 ns tpoE teLav Output Enable to Data Valid 15 20 ns loHA 10 taxax Output Hold After Address Change 5 5 ns tizcE m Chip Enable to Output Active 5 5 ns tuzcE tEHoz Chip Disable to Output Inactive 13 15 ns tizoE m teLax Output Enable to Output Active 0 0 ns tuzoE 17 Output Disable to Output Inactive 13 15 ns tPU 8 tELICCH Chip Enable to Power Active 0 0 ns tpp 8 tEHICCL Chip Disable to Power Standby 35 45 ns Switching Waveforms Figure 7 SRAM Read Cycle 1 Address Controlled 10 lt trc gt ADDRESS lt lt tona gt DQ DATA OUT DATA VALID gt lt Figure 8 SRAM Read Cycle 2 CE and OE Controlled 91 lt tac ADDRESS mE K tace gt lt tpo gt CE bu tizce gt lt tuzce gt i too tuzoe gt DQ DATA OUT lt gt lt DATA VALID lt tpu ACTIVE STANDBY Notes a 9 WE and HSB must be HIGH during SRAM Read Cycles 10 I O state assumes CE and OE lt Vi and WE gt V p device is continuously selected 11 Measured 200 mV from steady state output voltage Page 9 of 17 Document Number 001 50592 Rev Feedback CYPRESS STK14C88 3 PERFORM Table 3 SRAM Write Cycle
3. Parameter 35 ns 45 ns Be dicis Alt Serer hien Min Max Min Max Unit twe tavav Write Cycle Time 35 45 ns tpwe twi wH Write Pulse Width 25 30 ns tscE tei wH teLEH Chip Enable To End of Write 25 30 ns tsp tpvwH tpvEH Data Setup to End of Write 12 15 ns tup twHDX tEHDX Data Hold After End of Write 0 0 ns tAW tavwH tAVEH Address Setup to End of Write 25 30 ns tsa tavwL tAVEL Address Setup to Start of Write 0 0 ns tHa twHax tEHAX Address Hold After End of Write 0 0 ns tuzwE 17 12 twLaz Write Enable to Output Disable 13 15 ns tizwe ll twHax Output Active After End of Write 5 5 ns Switching Waveforms Figure 9 SRAM Write Cycle 1 WE Controlled 14 I lt twe ADDRESS gt dec tra l lt tsce CE taw gt lt tsa lt tewe gt WE lt tsp gt lt tup gt DATA IN DATA VALID Ituzwe p NS gt HIGH IMPEDANCE DATA OUT PREVIOUS DATA Figure 10 SRAM Write Cycle 2 CE Controlled 3 14 twe gt ADDRESS tsa gt tsce gt lt tha CE lt taw gt WE K tewe j tsp gt lt tap DATAIN DATA VALID DATA OUT HIGH IMPEDANCE Notes 12 If WE is Low when CE goes Low the outputs remain in the high impedance state 13 CE or WE must be greater than Viy during address transitions 14 HSB must be H
4. Feedback Ei NE z 2 CYPRESS STK14C88 3 PERFORM Software Controlled STORE RECALL Cycle The software controlled STORE RECALL cycle follows 18 191 n 35 ns 45 ns Parameter Alt Description Unit Min Max Min Max tac 91 tavav STORE RECALL Initiation Cycle Time 35 45 ns tsal 19 Address Setup Time 0 0 ns to 12 19 ELEH Clock Pulse Width 25 30 ns tyacel 19 tELAX Address Hold Time 20 20 ns tRECALL RECALL Duration 20 20 us Switching Waveforms ADDRESS Figure 12 CE Controlled Software STORE RECALL Cycle 19 gt tac tac ADDRESS 1 ADDRESS 6 wan 4m tstore treca DATA VALID sons Notes HIGH IMPEDANCE 18 The software sequence is clocked on the falling edge of CE without involving OE double clocking will abort the sequence 19 The six consecutive addresses must be read in the order listed in the Mode Selection table WE must be HIGH during all six consecutive cycles Document Number 001 50592 Rev Page 12 of 17 Feedback STK14C88 3 gt CYPRESS PERFORM Hardware STORE Cycle STK14C88 3 Parameter Alt Description Unit Min Max tpHsB tuLHx Hardware STORE Pulse Width 15 ns tonse 9 207 trecover Hardware STORE High to Inhibit Off 700 ns tui p
5. 22 4 E 229 LI 25 X CYPRESS STK14C88 3 PERFORM Document History Page Document Title STK14C88 3 256 Kbit 32K x 8 AutoStore nvSRAM Document Number 001 50592 Orig of Submission inti Rev ECN No Change Date Description of Change T 2625096 GVCH PYRS 12 19 08 New data sheet Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com lcd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2008 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety
6. M 2 CYPRESS PERFORM 3 Features m 35 ns and 45 ns access times m Automatic nonvolatile STORE on power loss m Nonvolatile STORE under Hardware or Software control m Automatic RECALL to SRAM on power up m Unlimited Read Write endurance m Unlimited RECALL cycles m 1 000 000 STORE cycles m 100 year data retention m Single 3 3V 0 3V power supply m Commercial and Industrial Temperatures m 32 pin 300mil SOIC and 32 pin 600 mil PDIP packages m RoHS compliance STK14C88 3 256 Kbit 32K x 8 AutoStore nvSRAM Functional Description The Cypress STK14C88 3 is a 256 Kb fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down On power up data is restored to the SRAM the RECALL operation from the nonvolatile memory Both the STORE and RECALL opera tions are also available under software control Logic Block Diagram
7. 9 mA at tac 200 ns 5V Dependent on output loading and cycle rate Values obtained without 25 C Typical output loads loca Average Vcap Current All Inputs Do Not Care Vcc Max 2 mA during AutoStore Average current for duration tsToRE Cycle Average Voc Current tac 35ns CE gt Vi Commercial 18 mA Standby Cycling TTL tac245ns CE gt Viu 16 Input Levels Industrial 19 mA 17 15 2 7 Voc Standby Current CE gt Vec 0 2 All others Vix lt 0 2V or gt Voc 0 2 1 mA Standby Stable CMOS Input Levels lix Input Leakage Current Voc Max Vss lt ViN lt Vcc 1 1 loz Off State Output Voc Max Vss lt Vin lt CE or OE gt Viu or WE lt Vi 1 1 pA Leakage Current ViH Input HIGH Voltage 2 2 Voct V 0 5 ViL Input LOW Voltage Vss 0 8 V 0 5 Vou Output HIGH Voltage lour 4 mA except HSB 2 4 V VoL Output LOW Voltage loyr 8 mA except HSB 0 4 V VBL Logic 0 Voltage lour 2 0 4 V HSB output VcAP Storage Capacitor Between Vcap pin and Vss 68 to 220uF 20 4 7V rated 54 264 uF Notes 6 Voc reference levels throughout this data sheet refer to Vcc if that is where the power supply connection is made or Vcap if Voc is connected to ground 7 CE gt will not produce standby current levels until any nonvolatile cycle in progress has timed out Document Number 001 50592 Rev Page 7 of 17 Feedback CYPRESS STK14C88 3 Data Retentio
8. An optional pull up resistor is shown connected to HSB The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress If the power supply drops faster than 20 us volt before Vcc reaches Vswlircn then 1 ohm resistor should be connected between Vcc and the system supply to avoid momentary excess of current between Vcc and AutoStore Inhibit Mode If an automatic STORE on power loss is not required then Vcc is tied to ground and 3 3V is applied to Vcap Figure 3 This is the AutoStore Inhibit mode where the AutoStore function is disabled If the STK14C88 3 is operated in this configuration references to Vcc are changed to Vcap throughout this data sheet In this mode STORE operations are triggered through software control It is not permissible to change between these options On the fly Page 3 of 17 Feedback SS I Ed CYPRESS STK14C88 3 PERFORM Figure 3 AutoStore Inhibit Mode Vor WE Vcc HSB o WF Bypass 10k Ohm 10k Ohm WE Vss Hardware STORE HSB Operation The STK14C88 3 provides the HSB pin for controlling and acknowledging the STORE operations The HSB pin is used to request a hardware STORE cycle When the HSB pin is driven LOW the STK14C88 3 conditionally initiates a STORE operation after Ay An actual STORE cycle only begins if a WRITE to the SRAM takes place since the last S
9. AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 50592 Rev Revised January 29 2009 Page 17 of 17 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
10. applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY
11. 14C88 3 only the lower 14 are used to control software modes Page 6 of 17 Feedback PERFORM Maximum Ratings Voltage on DQo 7 or HSB 0 5V to Vcc 0 5V Power Dissipation 1 0W Exceeding maximum ratings may shorten the useful life of the 9 g M DC output Current 1 output at a time 1s duration 15 mA device These user guidelines are not tested Storage Temperature 659 to 150 G Operating Range Temperature under 55 C to 125 C Range Ambient Temperature Vcc Supply Voltage on Vcc Relative to GND 0 5V to 7 0V Commercial 0 C to 70 C 3 0V to 3 6V Voltage on Input Relative to Vss 0 6V to Vec 0 5V Industrial 40 C to 85 C 3 0V to 3 6V DC Electrical Characteristics Over the operating range Vcc 3 0V to 3 6V 6 Parameter Description Test Conditions Min Max Unit loct Average Vcc Current tac 35 ns Commercial 50 mA tac 45 ns 42 mA Dependent on output loading and cycle rate Values industrial 52 mA obtained without output loads 44 mA louT 0 mA loce Average Vcc Current All Inputs Do Not Care Vcc Max 3 mA during STORE Average current for duration tsToRE loos Average Voc Current WE gt Vec 0 2V All other inputs cycling
12. IC STK14C88 3WFABI 51 85018 32 pin PDIP All parts are Pb free The above table contains Final information Please contact your local Cypress sales representative for availability of these parts Document Number 001 50592 Rev Page 14 of 17 Feedback STK14C88 3 CYPRESS PERFORM Package Diagrams Figure 14 32 Pin 300 Mil SOIC 51 85127 PIN 1 ID 16 1 i g DIMENSIONS IN INCHES MM MIN 0 299 7 594 MAX 0405110287 REFERENCE JEDEC MO 119 0 419 10 642 PART STANDARD PKG LEAD FREE PKG TAARAAANAAAAAAAA 1 SEATING PLANE 0 810 20 574 0 822 20 878 I fr 0 090 2 286 AAA j senso Id T H H H H H H a G Ee y 0 004 0 101 i 0 050 1 270 0 026 0 660 L 0 006 0 152 TYP 003200812 SN 0 012 0 304 0 004 0 101 041 1 0 014 0 355 0 0100 0 254 51 85127 A 0 020 0 508 Page 15 of 17 Feedback Document Number 001 50592 Rev Figure 15 32 Pin 600 Mil PDIP 51 85018 CYPRESS PERFORM Package Diagrams continued PLANE DIMENSIONS IN STK14C88 3 MIN MAX 2 009 012 625 670 Document Number 001 50592 Rev 600 625 3 MIN 51 85018 A Page 16 of 17 Feedback 204
13. IGH during SRAM WRITE cycles Document Number 001 50592 Rev Page 10 of 17 Feedback AutoStore or Power Up RECALL STK14C88 3 Parameter Alt Description Sr 50885 Unit Min Max tuRECALL 15 tRESTORE Power up RECALL Duration 550 us tsTORE 16 7 tur uz STORE Cycle Duration 10 ms tvsBL Low Voltage Trigger Vswircr to HSB low 300 ns VRESET Low Voltage Reset Level 2 4 V VswitcH Low Voltage Trigger Level 2 7 2 95 V tpELAY tBioz Time Allowed to Complete SRAM Cycle 1 us Switching Waveforms Voc Veeset Figure 11 AutoStore Power Up RECALL AutoStore POWER UP RECALL trecanu tvss lt terore HSB to ELAY Notes POWER UP RECALL du BROWN OUT BROWN OUT NO STORE AutoStore NO SRAM WRITES NO RECALL NO RECALL Vcc DID NOT GO Vcc DID NOT GO BELOW Vneser BELOW Vneser 15 tupEcALL Starts from the time Vcc rises above Vgwitcn 16 CE and OE low and WE high for output behavior 17 HSB is asserted low for 1us when Vcap drops through Vswrircr If an SRAM WRITE has not taken place since the last nonvolatile cycle HSB will be released and no store will take place Document Number 001 50592 Rev lt M BROWN OUT AutoStore RECALL WHEN Vcc RETURNS ABOVE VSWITCH Page 11 of 17
14. Inputs Used to select one of the 32 768 bytes of the nvSRAM DQo DQ Input or Bidirectional Data IO lines Used as input or output lines depending on operation Output WE W Input Write Enable Input Active LOW When the chip is enabled and WE is LOW data on the IO pins is written to the specific address location CE E Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state Vss Ground Ground for the Device The device is connected to ground of the system Vec Power Supply Power Supply Inputs to the Device HSB Input or Hardware Store Busy HSB When LOW this output indicates a Hardware Store is in Output progress When pulled low external to the chip it initiates a nonvolatile STORE operation A weak internal pull up resistor keeps this pin high if not connected connection optional VcAP Power Supply AutoStore Capacitor Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements Document Number 001 50592 Rev Page 2 of 17 Feedback SS I _ E CYPRESS PERFORM Device Operation The STK14C88 3 nvSRAM is made up of two functional compo nents paired in the same physical cell These are an SRAM memory cell and a nonvolatile QuantumTrap cell The SRAM memor
15. L Hardware STORE Low to STORE Busy 300 ns Figure 13 Hardware STORE Cycle Switching Waveforms HSB IN E tensa gt tstore tup HIGH IMPEDANCE HSB OUT lt lt HIGH IMPEDANCE lt DATA VALID DQ DATA OUT Note 20 tpusgp is only applicable after tsronE is complete Document Number 001 50592 Rev ANA VALID Page 13 of 17 Feedback EP CYPRESS STK14C88 3 Part Numbering Nomenclature STK14C88 3N F 45 I TR Packaging Option TR Tape and Reel Blank Tube Temperature Range Blank Commercial 0 to 70 Industrial 40 to 85 C Speed 35 35 ns 45 45 ns Lead Finish F 10096 Sn Matte Tin Package N Plastic 32 pin 300 mil SOIC W Plastic 32 pin 600 mil DIP Ordering Information gen Ordering Code Package Diagram Package Type idc 35 STK14C88 3NF35TR 51 85127 32 pin SOIC Commercial STK14C88 3NF35 51 85127 32 pin SOIC STK14C88 3WF35 51 85018 32 pin PDIP STK14C88 3NF35ITR 51 85127 32 pin SOIC Industrial STK14C88 3NF35I 51 85127 32 pin SOIC STK14C88 3WF35I 51 85018 32 pin PDIP 45 STK14C88 3NF45TR 51 85127 32 pin SOIC Commercial STK14C88 3NF45 51 85127 32 pin SOIC STK14C88 3WF45 51 85018 32 pin PDIP STK14C88 3NF45ITR 51 85127 32 pin SOIC Industrial STK14C88 3NFA5I 51 85127 32 pin SO
16. TORE or RECALL cycle The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition while the STORE initiated by any means is in progress Pull up this pin with an external 10K ohm resistor to if HSB is used as a driver SRAM READ and WRITE operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated After HSB goes LOW the STK14C88 3 continues SRAM operations for tDELAY During multiple SRAM READ operations take place If a WRITE is in progress when HSB is pulled LOW it allows a time Ay to complete However any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH The HSB pin is used to synchronize multiple STK14C88 3 while using a single larger capacitor To operate in this mode the HSB pin is connected together to the HSB pins from the other STK14C88 3 An external pull up resistor to Vcap is required since HSB acts as an open drain pull down The Vcap pins from the other STK14C88 3 parts are tied together Document Number 001 50592 Rev and share a single capacitor The capacitor size is scaled by the number of devices connected to it When any one of the STK14C88 3 detects a power loss and asserts HSB the common HSB pin causes all parts to request a STORE cycle A STORE takes place in those STK14C88 3 that are written since the last nonvolatile cycl
17. a two step procedure First the SRAM data is cleared and then the nonvolatile information is transferred into the SRAM cells After the taEcALL cycle time the SRAM is once again ready for READ and WRITE operations The RECALL operation does not alter the data in the nonvolatile elements The nonvolatile data can be recalled an unlimited number of times Preventing STORE The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30 mA at a Vor of at least 2 2V because it has to overpower the internal pull down device This device drives HSB LOW for 20 us at the onset of a STORE When the STK14C88 3 is connected for AutoStore operation system Vcc connected to Vcc and a 68 uF capacitor on and Vcc crosses Vewitcy on the way down the STK14C88 3 attempts to pull HSB LOW If HSB does not actually get below Vi the part stops trying to pull HSB LOW and aborts the STORE attempt Hardware Protect The STK14C88 3 offers hardware protection against inadvertent STORE operation SRAM WRITEs during low voltage condi tions When lt all externally initiated STORE operations and SRAM WRITES are inhibited Noise Considerations The STK14C88 3 is a high speed memory It must have a high frequency bypass capacitor of approximately 0 1 uF connected between Vcc and using leads and traces that are as short as possible As with all high speed CMOS ICs careful routing of po
18. e During any STORE operation regardless of how it is initiated the STK14C88 3 continues to drive the HSB pin LOW releasing it only when the STORE is complete After completing the STORE operation the STK14C88 3 remains disabled until the HSB pin returns HIGH If HSB is not used it is left unconnected Hardware RECALL Power Up During power up or after any low power condition Vcc lt an internal RECALL request is latched When Vec once again exceeds the sense voltage of Vewitcy a RECALL cycle is automatically initiated and takes tjjggcA to complete If the STK14C88 3 is in a WRITE state at the end of power up RECALL the SRAM data is corrupted To help avoid this situation a 10 Kohm resistor is connected either between WE and system Voc or between CE and system Vcc Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence The STK14C88 3 software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order During the STORE cycle an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements When a STORE cycle is initiated input and output are disabled until the cycle is completed Because a sequence of READs from specific addresses is used for STORE initiation it is important that no other READ or WRITE accesses intervene in the sequence If t
19. hey intervene the sequence is aborted and no STORE or RECALL takes place To initiate the software STORE cycle the following READ sequence is performed 1 Read address 0x0E38 Valid READ 2 Read address 0 31 7 Valid READ 3 Read address 0x03E0 Valid READ 4 Read address 0x3C1F Valid READ 5 Read address 0x303F Valid READ 6 Read address OxOFCO Initiate STORE cycle The software sequence is clocked with CE controlled READs When the sixth address in the sequence is entered the STORE cycle commences and the chip is disabled It is important that READ cycles and not WRITE cycles are used in the sequence It is not necessary that OE is LOW for a valid sequence After the cycle time is fulfilled the SRAM is again activated for READ and WRITE operation Page 4 of 17 Feedback SS I Ed SES CYPRESS PERFORM Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation To initiate the RECALL cycle the following sequence of CE controlled READ operations is performed 1 Read address 0x0E38 Valid READ 2 Read address 0x31C7 Valid READ 3 Read address 0x03E0 Valid READ 4 Read address 0x3C1F Valid READ 5 Read address 0x303F Valid READ 6 Read address 0x0C63 Initiate RECALL cycle Internally RECALL is
20. n and Endurance Parameter Description Min Unit DATAR Data Retention 100 Years NVc Nonvolatile STORE Operations 1 000 K Capacitance In the following table the capacitance parameters are listed 8 Parameter Description Test Conditions Max Unit CIN Input Capacitance Ta 25 f 1 MHz 5 pF Cour Output Capacitance Vcc 0 to 30 V 7 pF Thermal Resistance In the following table the thermal resistance parameters are listed Parameter Description Test Conditions 32 SOIC 32 PDIP Unit Thermal Resistance Test conditions follow standard test methods and TBD TBD C W Junction to Ambient procedures for measuring thermal impedance per Thermal Resistance EIA JESD51 TBD TBD C W Junction to Case Figure 6 AC Test Loads R1 3170 3 3V Output 30 pF PA 3510 AC Test Conditions Input Pulse OVto3V Input Rise and Fall Times 10 90 lt 5 ns Input and Output Timing Reference Levels 1 5 V Note 8 These parameters are guaranteed by design and are not tested Page 8 of 17 Document Number 001 50592 Rev Feedback CYPRESS STK14C88 3 PERFORM AC Switching Characteristics SRAM Read Cycle
21. on IO pins DQy are written into the memory if it has valid tsp before the end of a WE controlled WRITE or before the end of an CE controlled WRITE Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines If OE is left LOW internal circuitry turns off the output buffers after WE goes LOW AutoStore Operation The STK14C88 3 can be powered in one of three storage opera tions During normal operation the device draws current from Vcc to charge a capacitor connected to the Vcap pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vswircn the part automatically disconnects the pin from Voc A STORE operation is initiated with power provided by the capacitor Figure 2 shows the proper connection of the storage capacitor Vcap for automatic store operation A charge storage capacitor having a capacity of between 68 uF and 220 uF 20 rated at 4 7V should be provided To reduce unnecessary nonvolatile stores AutoStore and Hardware Store operations are ignored unless at least one Document Number 001 50592 Rev STK14C88 3 Figure 2 AutoStore Mode Wi 1 0 68yF 6v 12 0 1uf Bypass WRITE operation has taken place since the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place
22. oot status should always program a of a tRECALL period unique NV pattern for example a complex 4 byte pattern of 46 E6 49 53 hex or more random bytes as part of the final Table 2 Hardware Mode Selection CE WE SB A45 Ag Mode Io Power H X H X Not Selected Output High Z Standby L H H X Read SRAM Output Data Activell L L H X Write SRAM Input Data Active X X L X Nonvolatile Store Output High Z local L H H 0x0E38 Read SRAM Output Data Activell 3 4 5 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output Data 0x3C1F Read SRAM Output Data 0x303F Read SRAM Output Data 0x0FC0 Nonvolatile STORE Output Data L H H 0x0E38 Read SRAM Output Data Activel 3 4 5 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output Data 0x3C1F Read SRAM Output Data 0x303F Read SRAM Output Data 0x0C63 Nonvolatile RECALL Output Data Notes 1 into standby mode inhibiting all operations until HSB rises 3 CE and OE LOW and WE HIGH for output behavior Document Number 001 50592 Rev state assumes lt Vj Activation of nonvolatile cycles does not depend on state of OE 2 HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle After the STORE if any completes the part will go 4 The six consecutive addresses must be in the order listed WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle 5 While there are 15 addresses on the STK
23. tions has resulted in the following suggestions as best STK14C88 3 system manufacturing test to ensure these system routines work consistently Power up boot firmware routines should rewrite the nvSRAM into the desired state While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently program bugs or incoming inspection routines m The value specified in this data sheet includes minimum and a maximum value size Best practice is to meet this requirement and not exceed the max value because the higher inrush currents may reduce the reliability of the internal pass transistor Customers who want to use a larger value to ensure there is extra store charge should discuss their VcAp size selection with Cypress to understand any impact on the Vcap voltage level at the end m The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance Incoming inspection routines at customer or contract manufacturer s sites sometimes reprogram these values Final NV patterns are typically repeating patterns of AA 55 00 FF A5 or 5A End product s firmware should not assume an NV array is in a set programmed state Routines that check memory content values to determine first time system configuration and cold or warm b
24. wer ground and signals reduce circuit noise Document Number 001 50592 Rev STK14C88 3 Low Average Active Power CMOS technology provides the STK14C88 3 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns Figure 4 and Figure 5 show the relationship between and READ or WRITE cycle time Worst case current consumption is shown for both CMOS and TTL input levels commercial temperature range VCC 3 6V 100 duty cycle on chip enable Only standby current is drawn when the chip is disabled The overall average current drawn by the STK14C88 3 depends on the following items 1 The duty cycle of chip enable 2 The overall cycle rate for accesses 3 The ratio of READs to WRITEs 4 CMOS versus TTL input levels 5 The operating temperature 6 The Voc level 7 IO loading Figure 4 Current Versus Cycle Time READ 100 o o lt 5 60 lt 40 TTL amp 20 CMOS 0 50 100 150 200 Cycle Time ns Figure 5 Current Versus Cycle Time WRITE 100 o o o o CMOS Average Active Current mA N o 50 100 150 200 Cycle Time ns Page 5 of 17 Feedback CYPRESS practices f 4 Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values experience gained working with hundreds of applica
25. y cell operates as a standard fast static RAM Data in the SRAM is transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to SRAM the RECALL operation This unique architecture enables the storage and recall of all cells in parallel During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited The STK14C88 3 supports unlimited reads and writes similar to atypical SRAM In addition it provides unlimited RECALL opera tions from the nonvolatile cells and up to one million STORE operations SRAM Read The STK14C88 3 performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH The address specified on pins Ap 4 determines the 32 768 data bytes accessed When the READ is initiated by an address transition the outputs are valid after a delay of taa READ cycle 1 If the READ is initiated by CE OE the outputs are valid at tace or at tpog whichever is later READ cycle 2 The data outputs repeatedly respond to address changes within the t44 access time without the need for transitions on any control input pins and remains valid until another address change or until CE or OE is brought HIGH or WE or HSB is brought LOW SRAM Write A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle The data on the comm
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