Cypress Perform STK12C68 User's Manual
Contents
1. Logic Block Diagram V V Quantum Trap e cor A 128 X 512 7 ae s D POWER A STORE CONTROL S x A a 7 z RECALL le STORE ie p EEN lt RECALL lt gt HSB a lt __ __ CONTROL Ag pl 128 X 512 S Ay gt amp SOFTWARE Ar _ gt DETECT lt Ao A12 AA DQo __ COLUMN I O Paii 1 2 COLUMN DEC DQ DQ L Da Hh Ja DQ5 Te T Ao A1 Ag A3 A4 A10 i DQ r 6 a u DQ Bal HL lt H a p OE CE Oo b WE Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 408 943 2600 Document Number 001 51027 Rev Revised January 30 2009 Feedback m o zo _ N Eou gt Ean 7 CYPRESS I STK12C68 PERFORM Pin Configurations Figure 1 28 Pin SOIC DIP and LLC x 8 ww 4 gt Z YIMMI N d 3 2 28 27 Forc Mi oE e As 4 26C HSB 2 C 2 __ WE C A C As 5 25 As 7 C 26 __ HSB S As E4 3 C Ay Aa 6 24 Ae She a j As As 7 23C Arn 7 cs 2 An aay TOP 205E Ee Top View 2 OE Al An ge a 7 Ap Ph 21C Aro A Cols Not To Scale ao2. Page 2 of 20 Feedback Device Operation The STK12C68 nvSRAM is made up of two functional compo nents paired in the same physical cell These are an SRAM memory cell and a nonvolatile QuantumTrap cell The SRAM memory cell operates as a standard fast static RAM Data in the SRAM is transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to SRAM the RECALL operation This unique architecture enables the storage and recall of all cells in parallel During the STORE and RECALL operations SRAM Read and Write operations are inhibited The STK12C68 supports unlimited reads and writes similar to a typical SRAM In addition it provides unlimited RECALL opera tions from the nonvolatile cells and up to one million STORE operations SRAM Read The STK12C68 performs a Read cycle whenever CE and OE are LOW while WE and HSB are HIGH The address specified on pins Ap_ 2 determines the 8 192 data bytes accessed When the Read is initiated by an address transition the outputs are valid after a delay of ta Read cycle 1 If the Read is initiated by CE or OE the outputs are valid at tace or at tpog whichever is later Read cycle 2 The data outputs repeatedly respond to address changes within the ta access time without the need for transi tions on any control input pins and remains valid until another address change or until CE or OE is brought HIGH or WE or HSB is brought LOW SRAM Write A Wr
3. Feedback _ o gt _ F CYPRESS PERFORM Package Diagrams continued Figure 18 28 Pad 350 Mil LCC 001 51696 1 ALL DIMENSION ARE IN INCHES AND MILLIMETERS MIN MAX 2 JEDEC 95 OUTLINE MO 041 3 PACKAGE WEIGHT TBD Document Number 001 51027 Rev STK12C68 001 51696 Page 19 of 20 Feedback o r A SE CYPRESS STK12C68 PERFORM Document History Page Document Title STK12C68 64 Kbit 8K x 8 AutoStore nvSRAM Document Number 001 51027 Orig of Submission inti Rev ECN No Change Date Description of Change i 2606744 GVCH 01 30 2009 New data sheet Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com cd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypr
4. IMPEDANCE gt lt Dama VALID Page 13 of 20 Feedback CYPRESS STK12C68 Part Numbering nomenclature STK12C68 SF 45 1TR Packaging Option TR Tape and Reel Blank Tube Temperature Range C Commercial 0 to 70 C Industrial 40 to 85 C 7 Speed 25 25 ns 35 35 ns Lead Finish 45 45 ns F 100 Sn Matte Tin Package S Plastic 28 pin 330 mil SOIC P Plastic 28 pin 300 mil DIP W Plastic 28 pin 600 mil DIP C Ceramic 28 pin 300 mil DIP L Ceramic 28 pin LLC Ordering Information Speed ns Ordering Code Package Diagram Package Type Operating Range 25 STK12C68 SF25TR 001 85058 28 pin SOIC 330 mil Commercial STK12C68 SF25 001 85058 28 pin SOIC 330 mil STK12C68 PF25 001 85014 28 pin PDIP 300 mil STK12C68 WF25 001 85017 28 pin PDIP 600 mil STK12C68 SF25ITR 001 85058 28 pin SOIC 330 mil Industrial STK12C68 SF25 001 85058 28 pin SOIC 330 mil STK12C68 PF25l 001 85014 28 pin PDIP 300 mil STK12C68 WF25l 001 85017 28 pin PDIP 600 mil 35 STK12C68 C35 001 51695 28 pin CDIP 300 mil Commercial STK12C68 L35 001 51696 28 pin LCC 350 mil STK12C68 C35l 001 51695 28 pin CDIP 300 mil Industrial STK12C68 L351 001 51696 28 pin LCC 350 mil Document Number 001 51027 Rev Page 14 of 20 Feedback f CYPRESS STK12C6
5. Output Data Ox1FFF Read SRAM Output Data 0x10FO Read SRAM Output Data OxOFOF Nonvolatile STORE Output High Z L H H 0x0000 Read SRAM Output Data Activel 3 0x1555 Read SRAM Output Data Ox0AAA Read SRAM Output Data Ox1FFF Read SRAM Output Data 0x10F0 Read SRAM Output Data OxOFOE Nonvolatile RECALL Output High Z Notes 1 HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle After the STORE If any completes the part goes into standby mode inhibiting all operations until HSB rises 2 The six consecutive addresses must be in the order listed WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle 3 I O state assumes OE lt Vi Activation of nonvolatile cycles does not depend on state of OE Document Number 001 51027 Rev Page 6 of 20 Feedback CYPRESS STK12C68 Voltage on DQo 7 OF HSB eee 0 5V to Vcc 0 5V Power DiSSipatiOn ceseeeeeseeeeseneeeeeneeeteneeeesnneereaees 1 0W DC output Current 1 output at a time 1s duration 15 mA Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device These user guidelines are not tested Storage Temperature ccccceeseseteeeeeees 65 C to 150 C Operating Range 7 eres nas e a Jasari 55 F ae Range Ambient Temperature Voc pone on ie
6. ae to f a to 7 y Sominercial 0 C to 470 C 45V to 55V oltage on Input Relative to Vss 0 6V to Vcc 0 5 Industrial 40 C to 485 C 45V to55V DC Electrical Characteristics Over the operating range Vcc 4 5V to 5 5V M Parameter Description Test Conditions Min Max Unit loci Average Vcc Current taco 25 ns 85 mA tro 35ns 75 mA tac 45 ns 65 mA Dependent on output loading and cycle rate Values obtained without output loads lout 0 mA loce Average Vcc Current All Inputs Do Not Care Voc Max 3 mA during STORE Average current for duration tstore loos Average Vcc Current at WE gt Vcc 0 2V All other inputs cycling 10 mA trc 200 ns 5V 25 C Dependent on output loading and cycle rate Values obtained Typical without output loads loca Average Vcap Current All Inputs Do Not Care Vgc Max 2 mA during AutoStore Cycle Average current for duration tstore Isai Vcc Standby Current tac 25 ns CE gt Viy 27 mA Standby Cycling TTL tpRe 35 ns CE gt Viy 24 mA Input Levels trc 45 ns CE gt Vin 20 mA lope P Voc Standby Current CE gt Vcc 0 2V All others Viy lt 0 2V or gt Commercial 1 5 mA Vcc 0 2V Standby current level after nonvolatile cycle is complete Inputs are static f 0 MHZ neue tie g mA lix Input Leakage Current Voc Max Vss lt Vin lt Voc 1 1 pA lix Input Leakage Current Vcc Max Vss lt Vin lt Voc 1 1 uA loz Off State Output Vec Max Vss lt V
7. 0 uF 20 rated at 6V should be provided The voltage on the Vcap pin is driven to 5V by a charge pump internal to the chip A pull up is placed on WE to hold it inactive during power up Figure 2 AutoStore Mode 10k Ohm NM 10k Ohm Vow we Vcc WE HSB 68 UF 6v 20 gt 0 1n F Bypass 1 Vss In system power mode both Vcc and Vcap are connected to the 5V power supply without the 68 uF capacitor In this mode the AutoStore function of the STK12C68 operates on the stored system charge as power goes down The user must however guarantee that Vcc does not drop below 3 6V during the 10 ms STORE cycle To reduce unnecessary nonvolatile stores AutoStore and Hardware Store operations are ignored unless at least one Write operation has taken place since the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a Write operation has taken place An optional pull up resistor is shown connected to HSB The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress Page 3 of 20 Feedback 2 CYPRESS PERFORM Figure 3 AutoStore Inhibit Mode T n set a Q T E og 5 I JFl Veap Vec t WE 2 HSB A Vss V If the power supply dr
8. 50 100 150 200 Cycle Time ns Figure 5 Current Versus Cycle Time Write 100 80 g 5 60 oO v z TTL g lt 40 amp CMOS v Z 20 0 50 100 150 200 Cycle Time ns Preventing Store The STORE function is disabled by holding HSB high with a driver capable of sourcing 30 mA at a Voy of at least 2 2V because it must_overpower the internal pull down device This device drives HSB LOW for 20 us at the onset of a STORE When the STK12C68 is connected for AutoStore operation system Vcc connected to Vcc and a 68 uF capacitor on Vcap and Vcc crosses Vswitcy on_the way down the STK12C68 attempts to pull HSB LOW If HSB does not actually get below Vi_ the part stops trying to pull HSB LOW and abort the STORE attempt Page 5 of 20 Feedback Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values experience gained working with hundreds of applications has resulted in the following suggestions as best practices m The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance Incoming inspection routines at customer or contract manufacturer s sites sometimes reprograms these values Final NV patterns are typically repeating patterns of AA 55 00 FF A5 or 5A The end product s firmware should not assume that an NV array is in a set programmed state Routine
9. 5058 A Figure 15 28 Pin 300 Mil PDIP 51 85014 SEE LEAD END ea OTN i la LA DIMENSIONS IN INCHESCMM MIN SS T MAX 0 26006 60 REFERENCE JEDEC MO 095 0 295L7 49 PACKAGE WEIGHT 2 15gms PART P28 3 STANDARD PKG PZ28 3 LEAD FREE PKG 0 29067 36 T 0 325 8 25 SEATING PLANE 4 1 385 35 18 0 11502 92 7 0 009 0 23 3 MIN 0 160 4 06 0 012 0 30 i To 0 06001 52 0 09012 281 0 065 1 65 0 385 9 78 0 110 2 79 0 015 0 381 0 020 0 503 SEE LEAD END OPTION 51 penig ep LEAD END OPTION LEAD 1 14 15 amp 28 Document Number 001 51027 Rev Page 16 of 20 Feedback F CYPRESS STK12C68 PERFORM Package Diagrams continued Figure 16 28 Pin 600 Mil PDIP 51 85017 DIMENSIONS IN INCHES MIN MAX 14 1 REFERENCE JEDEC Ms 020 0 530 PART P28 6 STANDARD PKG 0 55 PZ28 6 LEAD FREE PKG SEATING PLANE 0 600 0 625 0 009 E 0012 3 MIN 0 610 0 700 51 85017 B Document Number 001 51027 Rev Page 17 of 20 Feedback Package Diagrams continued Figure 17 28 Pin 300 Mil Side Braze DIL 001 51695 a p A me tl nat 1 4 E tod ha E ALL DIMENSIONS ARE IN MILLIMETEI AND INCHS MIN MAX ACKAGE WEIGHT TI 5 EDEC REFERENCE N Document Number 001 51027 Rev 8 STK12C68 001 51695 Page 18 of 20
10. 6 55 45 16 55 84 46 1 95 31 C W tance standard test methods and Junction to procedures for measuring Ambient thermal impedance per EIA Ojo Thermal Resis _ YESD51 27 95 31 62 25 74 5 01 9 01 C W tance Junction to Case Figure 6 AC Test Loads R1 9639 R1 9639 For Tri state Specs 5 0V 5 0V Output Output 30 pF R2 5 pF R2 5120 5120 AC Test Conditions Input Pulse Levels ce eeeeeeeeeeeneeeeeeneeeeeneeereneees OVto3V Input Rise and Fall Times 10 to 90 nesen lt 5 ns Input and Output Timing Reference Levels 06 1 5 Note 6 These parameters are guaranteed by design and are not tested Document Number 001 51027 Rev Page 8 of 20 Feedback Da F f CYPRESS STK12C68 PERFORM AC Switching Characteristics SRAM Read Cycle Parameter 25 ns 35 ns 45 ns Cypress Description p Unit Parametar Alt Min Max Min Max Min Max tACE teLav Chip Enable Access Time 25 35 45 ns tac 1 tavav tELEH Read Cycle Time 25 35 45 ns taa 8 tavav Address Access Time 25 35 45 ns tpoE teLav Output Enable to Data Valid 10 15 20 ns TOHA 8 taxax Output Hold After Address Change 5 5 5 ns tLzcE BI tELQX Chip Enable to Output Active 5 5 5 ns tuzcE BI teHQz Chip Disable to Output Inactive 10 10 12 ns tLZ0E DI teLax Output Enable to Output Active 0 0 0 ns tuz0E DI teHaz Output Disable to Output Inactive 10 10 12 ns tpu e tELICCH Chip Enable to Powe
11. 8 Ordering Information continued Speed ns Ordering Code Package Diagram Package Type Operating Range 45 STK12C68 SF45TR 001 85058 28 pin SOIC 330 mil Commercial STK12C68 SF45 001 85058 28 pin SOIC 330 mil STK12C68 PF45 001 85014 28 pin PDIP 300 mil STK12C68 WF45 001 85017 28 pin PDIP 600 mil STK12C68 C45 001 51695 28 pin CDIP 300 mil STK12C68 L45 001 51696 28 pin LCC 350 mil STK12C68 SF45ITR 001 85058 28 pin SOIC 330 mil Industrial STK12C68 SF451 001 85058 28 pin SOIC 330 mil STK12C68 PF451 001 85014 28 pin PDIP 300 mil STK12C68 WF45l 001 85017 28 pin PDIP 600 mil STK12C68 C45 001 51695 28 pin CDIP 300 mil STK12C68 L451 001 51696 28 pin LCC 350 mil All parts are Pb free The above table contains Final information Contact your local Cypress sales representative for availability of these parts Docu ment Number 001 51027 Rev Page 15 of 20 Feedback SF CYPRESS STK12C68 PERFORM Package Diagrams Figure 14 28 Pin 330 Mil SOIC 51 85058 PIN 1 1D DIMENSIONS IN INCHESEMM MIN MAX PACKAGE WEIGHT 0 79gms 0 460 11 684 narerasesy 0480021921 SART F 0 346 8 788 28 33 STANDARD PKG SEATING PLANE 2 0 72018 288 0 728018 4911 ae 0 094 2 3871 l IAAAAARAAA 4 ostote 7943 I 00040102 4 L uen 00501 2701 0 01400 355 nonero so1 9 03000 762 0 012 0 304 TYP O 020C 508 n onaro tso 0 050 1 2701 51 8
12. Level 3 9 V VCCRISE Vcc Rise Time 150 us tvsBL Low Voltage Trigger Vswitcy to HSB Low 300 ns Switching Waveform Figure 11 AutoStore Power Up RECALL Vec Veeset AutoStore POWER UP RECALL treca tvse s je TeroRz HSB toevav DE WE DQ DATA OUT lt gt POWER UP BROWN OUT BROWN OUT BROWN OUT RECALL NO STORE AutoStore AutoStore NO SRAM WRITES NO RECALL NO RECALL RECALL WHEN Vcc DID NOT GO Vcc DID NOT GO Vcc RETURNS ABOVE VSWITCH BELOW Veeser BELOW Vreser Notes 13 tuRecaLt Starts from the time Vcc rises above Vgwitcn 14 CE and OE low for output behavior 15 CE and OE low and WE high for output behavior EES 16 HSB is asserted low for 1us when Vcap drops through Vewitcn If an SRAM Write has not taken place since the last nonvolatile cycle HSB is released and no store takes place Document Number 001 51027 Rev Page 11 of 20 Feedback gt Da A SS Fp f CYPRESS STK12C68 PEK ORM Software Controlled STORE RECALL Cycle The software controlled STORE RECALL cycle follows l8 ae 25 ns 35 ns 45 ns p Parameter Alt Description Unit Min Max Min Max Min Max trel tavav STORE RECALL Initiation Cycle Time 25 35 45 ns tsal tAVEL Address Setup Time 0 0 0 ns tew ELEH Clock Puls
13. OS ICs careful routing of power ground and signals reduce circuit noise Hardware Protect The STK12C68 offers hardware protection against inadvertent STORE operation and SRAM Writes during low voltage condi tions When Vcap lt Vswitcu all externally initiated STORE operations and SRAM Writes are inhibited AutoStore can be completely disabled by tying VCC to ground and applying 5V to Vcap This is the AutoStore Inhibit mode in this mode STOREs are only initiated by explicit request using either the software sequence or the HSB pin Low Average Active Power CMOS technology provides the STK12C68 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns Figure 4 shows the relationship between Icc and Read or Write cycle time Worst case current consumption is shown for both CMOS and TTL input levels commercial temper ature range VCC 5 5V 100 duty cycle on chip enable Only standby current is drawn when the chip is disabled The overall average current drawn by the STK12C68 depends on the following items m The duty cycle of chip enable m The overall cycle rate for accesses m The ratio of Reads to Writes m CMOS versus TTL input levels m The operating temperature Document Number 001 51027 Rev STK12C68 m The Vcc level m O loading Figure 4 Current Versus Cycle Time Read 100 80 T Z 5 60 oO o gt lt 40 k D ko D TTL Z 20 CMOS 0
14. an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements When a STORE cycle is initiated input and output are disabled until the cycle is completed Because a sequence of Reads from specific addresses is used for STORE initiation it is important that no other Read or Write accesses intervene in the sequence If they intervene the sequence is aborted and no STORE or RECALL takes place To initiate the software STORE cycle the following Read sequence is performed Read address 0x0000 Valid READ Read address 0x1555 Valid READ Read address Ox0AAA Valid READ Read address Ox1FFF Valid READ Read address 0x10F0 Valid READ Read address OxOFOF Initiate STORE cycle The software sequence is clocked with CE controlled Reads or OE controlled Reads When the sixth address in the sequence is entered the STORE cycle commences and the chip is disabled It is important that Read cycles and not Write cycles are used in the sequence It is not necessary that OE is LOW for a valid sequence After the tstore cycle time is fulfilled the SRAM is again activated for Read and Write operation Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence A software RECALL cycle is initiated with a sequence of Read operations in a manner similar to the software STORE initiation To initiate the RECALL cycle the following sequence of CE
15. aw tavwu tavEH Address Setup to End of Write 20 25 30 ns tsa tavw_ taveL Address Setup to Start of Write 0 0 0 ns tua twHax teHAx Address Hold After End of Write 0 0 0 ns tuzwe 2 twLaz Write Enable to Output Disable 10 13 14 ns tLzwe twHax Output Active After End of Write 5 5 5 ns Switching Waveforms Figure 9 SRAM Write Cycle 1 WE Controlled 121 I lt twe ADDRESS X me tsce gt CE lt taw gt K tsa lt tewe gt WE lt tsp gt lt tho gt DATA IN DATA VALID gt lt tizwe gt l lt tone j DATA OUT PREVIOUS DATA MIGHIMFEPANGE Figure 10 SRAM Write Cycle 2 CE Controlled l 1 121 lt twc ADDRESS lt tsa tsce lt tha CE lt taw WE X N towe tsp lt tuo DATA IN DATA VALID DATA OUT HIGH IMPEDANCE Notes 10 If WE is Low when CE goes Low the outputs remain in the high impedance state 11 HSB must be high during SRAM Write cycles 12 CE or WE must be greater than Vj during address transitions Document Number 001 51027 Rev Page 10 of 20 Feedback gt F f CYPRESS STK12C68 PERFORM AutoStore or Power Up RECALL Parameter Alt Description SIKILE Unit Min Max HRECALL 73 tRESTORE Power up RECALL Duration 550 us tsrore 4 1 gt TT lt ys STORE Cycle Duration 10 ms tperay 17 thLaz tBLaz Time Allowed to Complete SRAM Cycle 1 uS VswitcH Low Voltage Trigger Level 4 0 4 5 V VRESET Low Voltage Reset
16. controlled Read operations is performed 1 Read address 0x0000 Valid READ 2 Read address 0x1555 Valid READ oar WDM Page 4 of 20 Feedback ama __ wr F CYPRESS PERFORM 3 Read address 0x0AAA Valid READ 4 Read address 0x1FFF Valid READ 5 Read address 0x10F0 Valid READ 6 Read address OxOFOE Initiate RECALL cycle Internally RECALL is a two step procedure First the SRAM data is cleared then the nonvolatile information is transferred into the SRAM cells After the trecatt cycle time the SRAM is again ready for Read and Write operations The RECALL operation does not alter the data in the nonvolatile elements The nonvol atile data can be recalled an unlimited number of times Data Protection The STK12C68 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and Write operations The low voltage condition is detected when Vcc is less than Vswitcu If the STK12C68 is in a Write mode both CE and WE are low at power up after a RECALL or after a STORE the Write is inhibited until a negative transition on CE or WE is detected This protects against inadvertent writes during power up or brown out conditions Noise Considerations The STK12C68 is a high speed memory It must have a high frequency bypass capacitor of approximately 0 1 uF connected between Vcc and Vss using leads and traces that are as short as possible As with all high speed CM
17. e Width 20 25 30 ns tHacel Address Hold Time 20 20 20 ns RECALL RECALL Duration 20 20 20 us Switching Waveform ADDRESS Figure 12 CE Controlled Software STORE RECALL Cycle l8 gt tre tre ADDRESS 1 CL ADDRESS 6 i gt T e tstore t RECALL gt Notes a 17 The software sequence is clocked on the falling edge of CE without involving OE double clocking aborts the sequence 18 The six consecutive addresses must be read in the order listed in Table 1 on page 6 WE must be HIGH during all six consecutive cycles Document Number 001 51027 Rev HIGH IMPEDANCE DATA VALID j Page 12 of 20 Feedback STK12C68 gt FH F CYPRESS PERFORM Hardware STORE Cycle STK12C68 Parameter Alt Description Unit Min Max tsTORE 9 14 tuLyz STORE Cycle Duration 10 ms tpHsB 14 19 tRecover tHHax Hardware STORE High to Inhibit Off 700 ns tpHsB tHLHx Hardware STORE Pulse Width 15 ns tHLBL Hardware STORE Low to STORE Busy 300 ns Switching Waveform lt tense Figure 13 Hardware STORE Cycle buss i HSB IN lt tstore lt thue gt HSB OUT HIGH IMPEDANCE toeLay gt DQ DATA OUT DATA VALID Note 19 tousg is only applicable after tstore is complete Document Number 001 51027 Rev HIGH
18. ess Semiconductor Corporation 2006 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conj
19. i W 2 CYPRESS Features m 25 ns 35 ns and 45 ns access times STK12C68 64 Kbit 8K x 8 AutoStore nvSRAM m Hands off automatic STORE on power down with external 68 uF capacitor m STORE to QuantumTrap nonvolatile elements is initiated by software hardware or AutoStore on power down m RECALL to SRAM initiated by software or power up m Unlimited Read Write and Recall cycles m 1 000 000 STORE cycles to QuantumTrap m 100 year data retention to QuantumTrap m Single 5V 10 operation m Commercial and industrial temperatures m 228 pin 330mil SOIC 28 pin 300mil PDIP 28 pin 600mil PDIP packages m 28 pin 300 mil CDIP and 28 pad 350 mil LCC packages m RoHS compliance Functional Description The Cypress STK12C68 is a fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down On power up data is restored to the SRAM the RECALL operation from the nonvolatile memory Both the STORE and RECALL operations are also available under software control A hardware STORE is initiated with the HSB pin
20. in lt Vcc CE or OE gt Vin or WE lt ViL 5 5 uA Leakage Current Vin Input HIGH Voltage 2 2 Vec V 0 5 Vit Input LOW Voltage Vss 0 5 0 8 V VoH Output HIGH Voltage loyt 4 mA 2 4 V VoL Output LOW Voltage lour 8 mA 0 4 V VBL Logic 0 Voltage on lout 3 mA 0 4 V HSB Output Voap Storage Capacitor Between Vcap pin and Vss 6V rated 68 uF 20 nom 54 260 uF Notes 4 Voc reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made or Vcap if VCC is connected to ground 5 CE gt Viy does not produce standby current levels until any nonvolatile cycle in progress has timed out Document Number 001 51027 Rev Page 7 of 20 _ gt _ wr SSS f CYPRESS STK12C68 PERFORM Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention 100 Years NVc Nonvolatile STORE Operations 1 000 K Capacitance In the following table the capacitance parameters are listed 6 Parameter Description Test Conditions Max Unit Cin Input Capacitance Ty 25 C f 1 MHz 8 pF Cout Output Capacitance Vcc 0 to 3 0 V 7 pF Thermal Resistance In the following table the thermal resistance parameters are listed Parameter Description Test Conditions 28 SOIC 300 malt coo mall 28 CDIP 28 LCC Unit Oya Thermal Resis Test conditions follow 4
21. ite cycle is performed whenever CE and WE are LOW and HSB is HIGH The address inputs must be stable prior to entering the Write cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle The data on the common IO pins DQo_7 are written into the memory if it has valid tgp before the end of a WE controlled Write or before the end of an CE controlled Write Keep OE HIGH during the entire Write cycle to avoid data bus contention on common IO lines If OE is left LOW internal circuitry turns off the output buffers tyzw_ after WE goes LOW AutoStore Operation The STK12C68 stores data to nvSRAM using one of three storage operations 1 Hardware store activated by HSB 2 Software store activated by an address sequence 3 AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the STK12C68 Document Number 001 51027 Rev STK12C68 During normal operation the device draws current from Vcc to charge a capacitor connected to the Vcap pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vsgwitcu the part automatically disconnects the Vca p pin from Voc A STORE operation is initiated with power provided by the Vcap capacitor Figure 2 shows the proper connection of the storage capacitor Vcap for automatic store operation A charge storage capacitor between 68 UF and 22
22. ops faster than 20 us volt before Vcc reaches Vsw tcp then a 2 2 ohm resistor should be connected between Vcc and the system supply to avoid momentary excess of current between Vcc and Vecar AutoStore Inhibit Mode lf an automatic STORE on power loss is not required then Voc is tied to ground and 5V is applied to Vcap Figure 3 This is the AutoStore Inhibit mode where the AutoStore function is disabled If the STK12C68 is operated in this configuration refer ences to Vcc are changed to Vcap throughout this data sheet In this mode STORE operations are triggered through software control or the HSB pin To enable or disable Autostore using an I O port pin see Preventing Store on page 5 It is not permissible to change between these three options on the fly Hardware STORE HSB Operation The STK12C68 provides the HSB pin for controlling and acknowledging the STORE operations The HSB pin is used to request a hardware STORE cycle When the HSB pin is driven LOW the STK12C68 conditionally initiates a STORE operation after tpe_ay An actual STORE cycle only begins if a Write to the SRAM takes place since the last STORE or RECALL cycle The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition while the STORE initiated by any means is in progress SRAM Read and Write operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE o
23. peration is initiated After HSB goes LOW the STK12C68 continues SRAM operations for tpe_ay During tpeLay Multiple SRAM Read operations take place If a Write is in progress when HSB is pulled LOW it allows a time tpe ay to complete However any SRAM Write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH Document Number 001 51027 Rev STK12C68 During any STORE operation regardless of how it is initiated the STK12C68 continues to drive the HSB pin LOW releasing it only when the STORE is complete After completing the STORE operation the STK12C68 remains disabled until the HSB pin returns HIGH If HSB is not used it is left unconnected Hardware RECALL Power Up During power up or after any low power condition Vcc lt Vreset an internal RECALL request is latched When Vcc once again exceeds the sense voltage of VswitcH a RECALL cycle is automatically initiated and takes tyrecat to complete If the STK12C68 is in a Write state at the end of power up RECALL the SRAM data is corrupted To help avoid this situation a 10 Kohm resistor is connected either between WE and system Vcc or between CE and system Vcc Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence The STK12C68 software STORE cycle is initiated by executing sequential CE controlled Read cycles from six specific address locations in exact order During the STORE cycle
24. r Active 0 0 0 ns tpp e tEHICCL Chip Disable to Power Standby 25 35 45 ns Switching Waveforms Figure 7 SRAM Read Cycle 1 Address Controlled 81 l lt tre ADDRESS DQ DATA OUT ADDRESS DQ DATA OUT ICC Notes lt Tia I tona DATA VALID gt lt Figure 8 SRAM Read Cycle 2 CE and OE Controlled 7 tre tace gt k teo gt tizce gt lt thzce gt K tuzoe gt tooe gt t zoe gt gt _ lt DATA VALID lt tay ACTIVE STANDBY 7 WE and HSB must be High during SRAM Read cycles 8 Device is continuously selected with CE and OE both Low 9 Measured 200 mV from steady state output voltage Document Number 001 51027 Rev Page 9 of 20 Feedback f CYPRESS STK12C68 PERFORM SRAM Write Cycle Parameter 25 ns 35 ns 45 ns Description Unit PE Alt i Min Max Min Max Min Max twe tavav Write Cycle Time 25 35 45 ns tpwe twewu tWLEH Write Pulse Width 20 25 30 ns tsce teLwu tELEH Chip Enable To End of Write 20 25 30 ns tsp tpvwH DVEH Data Setup to End of Write 10 12 15 ns tub twupx teHpx Data Hold After End of Write 0 0 0 ns t
25. s that check memory content values to determine first time system configuration cold or warm boot status and so on must always program a STK12C68 manufacturing test to ensure these system routines work consistently m Power up boot firmware routines should rewrite the nvSRAM into the desired state While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently program bugs incoming inspection routines and so on m The Vcap value specified in this data sheet includes a minimum and a maximum value size The best practice is to meet this requirement and not exceed the maximum Vcap value because the higher inrush currents may reduce the reliability of the internal pass transistor Customers who want to use a larger Vcap value to make sure there is extra store charge should discuss their Vcap size selection with Cypress unique NV pattern for example complex 4 byte pattern of 46 E6 49 53 hex or more random bytes as part of the final system Table 1 Hardware Mode Selection CE WE SB A12 A0 Mode 10 Power H X H X Not Selected Output High Z Standby L H H X Read SRAM Output Data Active L L H X Write SRAM Input Data Active x xX L x Nonvolatile STORE Output High Z local L H H 0x0000 Read SRAM Output Data Active lcc l 0x1555 Read SRAM Output Data Ox0AAA Read SRAM
26. t E Ao D10 20C cE Ao 10 19 _ va7 Dau i 196 DQ pao C Jn 18 DQ6 DQ pat _ 12 47 bas 1212 180 DQes 2 J 13 DQ4 Koa 3 ff R Ie Z J ss 14 DQ3 N Y 9 o8g8gogagog D gt ASA Pin Definitions Pin Name Alt 10 Type Description Ag A12 Input Address Inputs Used to select one of the 8 192 bytes of the nvSRAM DQ DQ Input or Output Bidirectional Data IO Lines Used as input or output lines depending on operation WE W Input Write Enable Input Active LOW When the chip is enabled and WE is LOW data on the IO pins is written to the specific address location CE E Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state Vss Ground Ground for the Device The device is connected to ground of the system Voc Power Supply Power Supply Inputs to the Device HSB Input or Output Hardware Store Busy HSB When LOW this output indicates a Hardware Store is in progress When pulled low external to the chip it initiates a nonvolatile STORE operation A weak internal pull up resistor keeps this pin high if not connected connection optional Voap Power Supply AutoStore Capacitor Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements Document Number 001 51027 Rev
27. unction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 51027 Rev Revised January 30 2009 Page 20 of 20 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
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