Cypress Perform CY7C1576V18 User's Manual
Contents
1. _ gt cmm 3 CYPRESS PERFORM AC Electrical Characteristics Over the Operating Range 14 Parameter Description Test Conditions Min Typ Max Unit Vin Input HIGH Voltage VREF 0 2 VDDQ 0 24 V Vit Input LOW Voltage 0 24 Vrer 0 2 V Capacitance Tested initially and after any design or process change that may affect these parameters Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHZ Vpp 1 8V Vppo 1 5V 5 pF Celk Clock Input Capacitance 6 pF Co Output Capacitance 7 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters 165 FBGA 1 Parameter Description Test Conditions Package Unit OJA Thermal Resistance Test conditions follow standard test methods and 11 82 C W Junction to Ambient procedures for measuring thermal impedance in jc Thermal Resistance accordance with EIA JESD51 2 33 C W Junction to Case Figure 4 AC Test Loads and Waveforms Vner 0 75V Vner o 0 75V OUTPUT VREF e 0 75V R 500 23 ALL INPUT PULSES Device OUTPUT 1 25V Under Devi fw NN Test To 5 pF 0 25V 28 Veer 0 75V Jest ZQ a I Slew Rate 2 V ns RQ 5 2500 2500 a INCLUDING JIG AND b SCOPE Notes 23 Unless otherwise noted test conditions assume signal transition time of 2V ns timing reference2. TDO 2 NC 144M and NC 288M are not connected to the die and can be tied to any voltage level J uz zr jcromimjogoj uyu Note Document Number 001 05384 Rev F CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 10 11 CQ CYPRESS 1 2 NC Pin Configuration continued 144M 5 BWS K K 165 Ball FBGA 15 x 17 x 1 4 mm Pinout 7 RPS NC Q7 D7 CY7C1563V18 4M x 18 6 D9 Vss BWS NC NC NC 288M A NC NC Q6 NC NC NC Vppo PERFORM The pin configuration for CY7C1561V18 CY7C1576V18 CY7C1563V18 and CY7C1565V18 follow 2 8 A NC D8 NC Q5 D5 ZQ VREF Q4 D4 Q3 D3 Q Q9 D10 NC NC Q10 NC D11 Q11 NC 2 D2 D1 Qo NC D12 NC TDI Q12 Q13 TMS Vss NC D13 Vppa DOFF VREF NC D14 Q14 10 11 NC NC NC Q15 D15 D16 9 NC 144M Q17 NC NC Q16 A 7 D17 Q7 NC D17 Q17 A D16 D15 N C NC A CY7C1565V18 2M x 36 6 5 K BWS BWS Q16 D6 NC TCK BWS A Q15 Q14 J v Zi zir z A ciroimimiogo uo TDO 4 D14 D13 BWS Q13 VR CQ 2 A A Q8 D8 D7 Q6 Q5 D5 EF ZQ D4 VDDQ D12 Q4 Q12 D3 Q3 D11 Q11 Q2 D10 Q1 D2 D9 D1 Qo 1 CQ NC 288M Q27 Q18 D18 D27 Q28 D19 D20 Q19 Q20 D
3. 1 1 ER CY7C1561V18 CY7C1576V18 T CYPRESS CY7C1563V18 CY7C1565V18 PERFORM Boundary Scan Order Bit Bump ID Bit 4 Bump ID Bit Bump ID Bit Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 1F 58 5A 86 3K 3 7P 31 11G 59 4A 3J 4 7N 32 9F 60 5C 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 4 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 Hc 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 OK 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document Number 001 05384 Rev F Page 18 of 28 Feedback CY7C1561V18 CY7C1576V18 E cu E CYPRESS CY7C1563V18 CY7C1565V18 PERFORM Power Up Sequence in QDR II SRAM DLL Constraints aer m DLL uses K clock as its synchronizing input The input must QDR Il SRAMs must be powered up and initialized in a have low phase jitter which is specified as tkc yar predefined manner to prevent undefined operations During Power Up when the DOFF is tied
4. Reg Reg gt Reg Reg Address Register A 20 0 Address A 20 0 i ad keny 6 X WZ keny 6 X WZ Aeuy 6 X WZ Keny 6 X WZ Control Write Add Decode Read Add Decode gt Read Data Reg Document Number 001 05384 Rev F Page 2 of 28 Feedback ge 7 CYPRESS PERFORM CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 Logic Block Diagram CY7C1563V18 Di17 0 z E Write Write Reg gt Reg Write Reg Write Reg Address Aug Register pe Address A 19 0 s jou keny 8L X WL FE Keny 9L XNE NT Keny 9L X WL ER Keny 9L X WL Read Add Decode Control Write Add Decode Read Data Reg VREF WPS BWSrr gj Control Logic Logic Block Diagram CY7C1565V18 Dt5 9 t t t Write Write Write Reg gt Reg gt Reg Write Address Register A 18 0 Address D D A 18 0 e gt ibd spay aye ages SIR RIRIS JS a x x x x a z 8 8 8 8 S9 K d lt i gt gt gt 345 o E S 9 Control EN 3 8 3 23 8 DOFF VREF WPS BWS I Control Logic Read Data Reg Document Number 001 053
5. Accesses for both ports are initiated on the positive input clock K All synchronous input and output timing are referenced from the rising edge of the input clocks K and K All synchronous data inputs Dix o inputs pass through input registers controlled by the input clocks K and K All synchronous data outputs Qk 0 outputs pass through output registers controlled by the rising edge of the input clocks K and K as well All synchronous control RPS WPS NWSp o BWSjgj inputs pass through input registers controlled by he rising adus of the input clocks K and K CY7C1563V18 is described in the following sections The same basic descriptions apply to CY7C1561V18 CY7C1576V18 and CY7C1565V18 Read Operations The CY7C1563V18 is organized internally as four arrays of 1M X 18 Accesses are completed in a burst of four sequential 18 bit data words Read operations are initiated by asserting RPS active at the rising edge of the positive input clock K The address presented to address inputs are stored in the read address register Following the next two K clock rise the corre sponding lowest order 18 bit word of data is driven onto the Qr 7 9 using K as the output timing reference On the subse quent rising edge of K the next 18 bit data word is driven onto the Q 17 9 This process continues until all four 18 bit data words have been driven out onto Qr 7 9 The requested data is ics 0 45 ns from the rising Fue o
6. 565V18 Ordering Code Package Diagram Package Type Operating Range CY7C1561V18 400BZC CY7C1576V18 400BZC CY7C1563V18 400BZC CY7C1565V18 400BZC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1561V18 400BZXC CY7C1576V18 400BZXC CY7C1563V18 400BZXC CY7C1565V18 400BZXC CY7C1561V18 400BZI CY7C1576V18 400BZI CY7C1563V18 400BZI CY7C1565V18 400BZI 51 85195 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1561V18 400BZXI CY7C1576V18 400BZXI CY7C1563V18 400BZXI CY7C1565V18 400BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free Commercial Industrial 375 CY7C1561V18 375BZC CY7C1576V18 375BZC CY7C1563V18 375BZC CY7C1565V18 375BZC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Commercial CY7C1561V18 375BZXC CY7C1576V18 375BZXC CY7C1563V18 375BZXC CY7C1565V18 375BZXC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1561V18 375BZI CY7C1576V18 375BZl CY7C1563V18 375BZI CY7C1565V18 375BZI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1561V18 375BZXI CY7C1576V18 375BZXI CY7C1563V18 375BZXI CY7C1565V18 375BZXI 51 85195 165 Ba
7. NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 05384 Rev F Revised March 6 2008 Page 28 of 28 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress IDT NEC Renesas and Samsung All product and company names mentioned in this document are the trademarks of their respective holders Feedback
8. TON ult Circuitry p 31 30 29 2 1 0 gt Identification Register 108 i 2 1 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range lS 14 15 Parameter Description Test Conditions Min Max Unit VonHi Output HIGH Voltage lon 2 0 mA 1 4 V Von2 Output HIGH Voltage lou 100 pA 1 6 V Vout Output LOW Voltage lo 2 0 mA 0 4 V Voi Output LOW Voltage lo 100 pA 0 2 V Vin Input HIGH Voltage 0 65Vpp Vpp 0 3 V Vi Input LOW Voltage 0 3 0 35Vpp V lx Input and Output Load Current GND lt Vi x Vpp 5 5 uA Notes 13 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels are specified in the Electrical Characteristics Table 14 Overshoot Viy AC lt Vppg 0 35V Pulse width less than toyc 2 Undershoot Vi AC gt 0 3V Pulse width less than toyc 2 15 All Voltage referenced to Ground Document Number 001 05384 Rev F Page 15 of 28 Feedback YPRESS PERFORM TAP AC Switching Characteristics Over the Operating Range 6 17 CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 Parameter Description Min Max Unit trcvc TCK Clock Cycle Time 50 ns tte TCK Clock Frequency 20 MHz ty TCK Clock HIGH 20 ns tn TCK Clock LOW 20 ns Setup Times truss TMS Setup to TCK Clock Rise 5 ns troi
9. data during a read operation Valid data is Synchronous driven out on the rising edge of both the K and K clocks during read operations On deselecting the read port Qi o are automatically tri stated CY7C1561V18 Qr CY7C1576V18 Gg CY7C1563V18 Qj17 0 CY7C1565V18 Qi35 0 RPS Input Read Port Select Active LOW Sampled on the rising edge of positive input clock K When active a Synchronous read operation is initiated Deasserting deselects the read port When deselected the pending access is allowed to complete and the output drivers are automatically tri stated following the next rising edge of the K clock Each read access consists of a burst of four sequential transfers QVLD Valid output Valid Output Indicator The Q Valid indicates valid output data QVLD is edge aligned with CQ and CQ indicator K Input Positive Input Clock Input The rising edge of K is used to capture synchronous inputs to the device Clock and to drive out data through Q 9 All accesses are initiated on the rising edge of K K Input Negative Input Clock Input K is used to capture synchronous inputs being presented to the device and Clock to drive out data through Qro CQ Echo Clock Synchronous Echo Clock Outputs This is a free running clock and is synchronized to the input clock K of the QDR II The timings for the echo clocks are shown in the Switching Characteristics on page 23 CQ Echo Clock Synchronous Echo Clock Outputs This is a free runn
10. for 2 5 Cycle Read Latency NOP READ WRITE READ WRITE NOP 1 2 3 4 5 6 7 8 Kk j ott ee LJ NY X4 X IKH tkL tcvc KHKH gt lt K CN FNS NS NEN ws DULL ST X 8 NOOK EN D Wf lll lll A pjo pit D 2 wi W LEA i WITT SS MUT tavLD f QVLD QVLD I f E DOH 4 pL co re tie CQDOH ke ANG top icuz gt je aa Q de aot a02 a0 a20 ca a et t Read Latency 2 5 Cycles t CCQO i ia EM cQ i _ N kt l i CCQO teon CaHGOH T zer d l t e y iL eF Lo NI DON T CARE R UNDEFINED Notes 31 Q00 refers to output from address AO Q01 refers to output from the next internal burst address following AO i e A0 1 32 Outputs are disabled High Z one clock cycle after a NOP 33 In this example if address A2 A1 then data Q20 D10 Q21 D11 Q22 D12 and Q23 D13 Write data is forwarded immediately as read results This note applies to the whole diagram Document Number 001 05384 Rev F Page 24 of 28 Feedback P CYPRESS PERFORM Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered CY7C1561V18 CY7C1 CY7C1563V18 CY7C1 576V18
11. it is possible that during the Capture DR state an input or output undergoes a transition The TAP may then try to capture a signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that is captured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold times tcs and to The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins Document Number 001 05384 Rev F CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is the data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instructio
12. levels of 0 75V Vref 0 75V RQ 2500 Vppq 1 5V input pulse levels of 0 25V to 1 25V and output loading of the specified lo Io and load capacitance shown in a of AC Test Loads and Waveforms Page 22 of 28 Document Number 001 05384 Rev F Feedback CY7C1561V18 CY7C1576V18 Ss J CYPRESS CY7C1563V18 CY7C1565V18 PERFORM T Switching Characteristics Over the Operating Range 23 241 i v 400 MHz 375 MHz 333 MHz 300 MHz Perameter Parameter Deacon Min Max Min Max Min Max Min Max Unit tpoWER Vpp Typical to the First Access 25 1 1 1 1 ms tcvc tkHkH K Clock Cycle Time 2 50 8 40 2 66 8 40 3 0 8 40 3 3 8 40 ns tkH tkKHKL Input Clock K K HIGH 04 04 04 pu T tee tk tkt KH Input Clock K K LOW 04 04 04 0 4 Tiyo tKHKH tkHKH K Clock Rise to K Clock Rise 1 06 1 13 128 1 40 ns rising edge to rising edge Setup Times tsa tAVKH Address Setup to K Clock Rise 04 104 104 04 ns tsc tivkH Control Setup to K Clock Rise RPS WPS 04 104 104 04 ns tecppR tivkH Double Data Rate Control Setup to Clock K K 0 28 0 28 028 028 ns Rise BWSg BWS BWSs BWS3 tsp tpvKH Dpco Setup to Clock K K Rise 0 28 0 28 0 28 0 28 ns Hold Times tua tkKHAX Ad
13. selected at a time through the instruction registers Data is serially loaded into the TDI pin on the rising edge of TCK Data is output on the TDO pin on the falling edge of TCK Document Number 001 05384 Rev F CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 15 Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between TDI and TDO pins This enables shifting of data through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM Several No Connect NC pins are also included in the scan register to reserve pins for
14. sequence CY7C1561V18 only the lower nibble Dj3 9 is written into the device Dr 4j remains unaltered CY7C1563V18 only the lower byte Djg o Is written into the device Dr 7 9j remains unaltered H L L H During the data portion of a write sequence CY7C1561V18 only the upper nibble Djz 4 is written into the device Drs 9j remains unaltered CY7C1563V18 only the upper byte Gara is written into the device Drs oj remains unaltered H L L H During the data portion of a write sequence CY7C1561V18 only the upper nibble Djz 4 is written into the device Dj3 9 remains unaltered CY7C1563V18 only the upper byte Gn is written into the device Drs oj remains unaltered K K Comments H H L H No data is written into the devices during this portion of a write operation H H L H No data is written into the devices during this portion of a write operation Notes 3 X Don t Care H Logic HIGH L Logic LOW T represents rising edge 4 Device powers up deselected with the outputs in a tri state condition 5 A represents address location latched by the devices when transaction was initiated A 1 A 2 and A 3 represents the address sequence in the burst 6 t represents the cycle at which a read write operation is started t 1 t 2 andt 3 are the first second and third clock cycles respectively succeeding the t clock cycle 7 Data inputs a
15. 28 Q29 D29 Q30 Q21 D21 D30 D22 Q22 DOFF Vngr VDDQ D31 Q31 D23 Q32 D32 Q23 Q33 Q24 D24 D33 Q34 D25 D34 D26 Q25 D35 Q26 A A A A Q10 Q9 DO TMS TDI Page 5 of 28 Q35 TCK TDO J uz zir jcrommoojuyu Document Number 001 05384 Rev F Feedback Pin Definitions YPRESS PERFORM CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 Pin Name IO Pin Description Dix 0 Input Data Input Signals Sampled on the rising edge of K and K clocks when valid write operations are active Synchronous CY7C1561V18 Drz CY7C1576V18 Dig CY7C1563V18 D 17 0 CY7C1565V18 Dias WPS Input Write Port Select Active LOW Sampled on the rising edge of the K clock When asserted active a Synchronous write operation is initiated Deasserting deselects the Write Port Deselecting the write port ignores Djx 9 NWSp Input Nibble Write Select 0 1 Active LOW CY7C1561V18 Only Sampled on the rising edge of the K and NWS Synchronous K clocks when write operations are active Used to select which nibble is written into the device during the current portion of the write operations NWSy controls Dra oj and NWS controls Dy 4j All the Nibble Write Selects are sampled on the same edge as the data Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written i
16. 300BZXC CY7C1565V18 300BZXC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1561V18 300BZI CY7C1576V18 300BZI CY7C1563V18 300BZI CY7C1565V18 300BZI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1561V18 300BZXI CY7C1576V18 300BZXI CY7C1563V18 300BZXI CY7C1565V18 300BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free Document Number 001 05384 Rev F Page 26 of 28 Feedback CYPRESS PERFORM Package Diagram CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 Figure 6 165 ball FBGA 15 x 17 x 1 4 mm 51 85195 TOP VIEW PIN 1 CORNER 1 2 3 4 5 7 8 9 10 11 A B D E F G J K L M N P R a ol g ri E 8 oN m A U S 2 F n X 3 s L r3 i I SEATING PLANE tf c m Document Number 001 05384 Rev F 1 40 MAX BOTTOM VIEW A 20 05 M C PIN 1 CORNER T go25 MCA 0 14 0 50 0 06 165X 170 9 8 7 6 5 4 3 2 1 E i A 0000g00 00 0 60000 O0000 B T 2 00000 0 6 0 069 c 8 eo0000000000 D eoo000oOec00 000 E 00000 O0000 F Oo O0 0 6 00000 6 o o 2 8 3 M j 8 O
17. 6 Functional Description The CY7C1561V18 CY7C1576V18 CY7C1563V18 and CY7C1565V18 are 1 8V Synchronous Pipelined SRAMs equipped with QDR II architecture Similar to QDR II archi tecture QDR II SRAMs consists of two separate ports the read port and the write port to access the memory array The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations QDR Il architecture has separate data inputs and data outputs to completely eliminate the need to turn around the data bus that exists with common IO devices Each port is accessed through a common address bus Addresses for read and write addresses are latched on alternate rising edges of the input K clock Accesses to the QDR Il read and write ports are completely independent of one another To maximize data throughput both read and write ports are equipped with DDR interfaces Each address location is associated with four 8 bit words CY7C1561V18 9 bit words CY7C1576V18 18 bit words CY7C1563V18 or 36 bit words CY7C1565V18 that burst sequentially into or out of the device Because data is trans ferred into and out of the device on every rising edge of both input clocks K and K memory bandwidth is maximized while simpli fying system design by eliminating bus turn arounds Depth expansion is accomplished with port selects which enables each port to operate independently All synchrono
18. 84 Rev F Page 3 of 28 Feedback CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 11 CQ Q3 D3 2 CYPRESS Pin Configuration 1 A NC 165 Ball FBGA 15 x 17 x 1 4 mm Pinout CY7C1561V18 8M x 8 6 7 NC 144M 5 NWS K NC 288M NWS PERFORM The pin configuration for CY7C1561V18 CY7C1576V18 CY7C1563V18 and CY7C1565V18 follow P 8 S NC NC NC NC NC NC VDDQ NC NC Q2 NC NC ZQ D1 NC Qo NC NC NC DO NC NC N C NC D4 Q4 NC NC NC NC NC TDI NC Q5 NC TMS VDDQ NC NC D6 NC D5 VREF NC NC Q6 11 CQ Q4 D4 DOFF NC NC NC NC NC Q7 7 NC NC D7 NC NC NC CY7C1576V18 8M x 9 6 5 K BWS NC 144M 0 NC NC TCK NC A NC TDO Divi Zi s r xAl e z o nim o o wv gt NC N C 288M NC NC Q3 NC NC ZQ NC Vppa NC CQ NC NC NC NC NC NC Q 5 NC N C NC D5 NC NC NC NC D2 Q1 D1 NC QO TDI NC NC Q6 NC TMS NC D6 Vppa NC VREF NC DOFF NC NC D 7 NC NC NC Q7 NC Page 4 of 28 NC NC 8 NC Q8 Feedback N C D NC NC NC TCK
19. DO During this state instructions are shifted through the instruction register through the TDI and TDO pins To execute the instruction after it is shifted in the TAP controller must be moved into the Update IR state Page 12 of 28 Feedback YPRESS PERFORM The IDCODE instruction loads a vendor specific 32 bit code into the instruction register It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test Logic Reset state SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is supplied during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the input and output pins is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies
20. HIGH the DLL gets locked m The DLL functions at frequencies down to 120 MHz after 2048 cycles of stable clock m If the input clock is unstable and the DLL is enabled then the Power Up Seq uence DLL may lock onto an incorrect frequency causing unstable SRAM behavior To avoid this provide 2048 cycles stable clock m Apply power with DOFF tied HIGH All other inputs can be to relock to the desired clock frequency HIGH or LOW 3 Apply Vpp before Vppa 3 Apply Vppq before Vref or at the same time as VREF m Provide stable power and clock K K for 2048 cycles to lock the DLL Figure 3 Power Up Waveforms l tt aud VM N NINJA NI NI PES l I K e Na o aoa Eer Clock ja gt 2048 Stable Clock i Start Normal Operation Clock Start Clock Starts after Vpp Vppq is Stable VT nn a a a a a Vpp Vppo NE SENE Vpp Vppg Stable lt 0 1V DC per 50 ns DOFF f Fix HIGH tie to Vppq Document Number 001 05384 Rev F Page 19 of 28 Feedback Maximum Ratings CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 Current into Outputs LOW Static Discharge Voltage MIL STD 883 M 3015 gt 2001V See Pees USER scene ae Bl ti EM Mo Latch up Current sss 2200 mA Storage Temperature susse 65 C to 150 C Op
21. PERFORM CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 72 Mbit QDR I SRAM 4 Word Burst Architecture 2 5 Cycle Read Latency Features m Separate independent read and write data ports Supports concurrent transactions m 400 MHz clock for high bandwidth m 4 word burst for reducing address bus frequency m Double Data Rate DDR interfaces on both read and write ports data transferred at 800 MHz at 400 MHz m Available in 2 5 clock cycle latency m Two input clocks K and K for precise DDR timing a SRAM uses rising edges only m Echo clocks CQ and CQ simplify data capture in high speed systems m Data valid pin QVLD to indicate valid data on the output m Single multiplexed address input bus latches address inputs for both read and write ports m Separate port selects for depth expansion m Synchronous internally self timed writes m Available in x8 x9 x18 and x36 configurations m Full data coherency providing most current data m Core Vpp 1 8V 0 1V IO Vppo 1 4V to Vpp 11 m HSTL inputs and variable drive HSTL output buffers m Available in 165 Ball FBGA package 15 x 17 x 1 4 mm m Offered in both Pb free and non Pb free packages m JTAG 1149 1 compatible test access port m Delay Lock Loop DLL for accurate data placement Selection Guide Configurations With Read Cycle Latency of 2 5 cycles CY7C1561V18 8M x 8 CY7C1576V18 8M x 9 CY7C1563V18 4M x 18 CY7C1565V18 2M x 3
22. atings for DC Input Voltage from Vppq to Vpp Changed the Pin Definition of lx from Input Load current to Input Leakage current on page 18 D 497567 See ECN NXR Changed the Vppq operating voltage to 1 4V to Vpp in the Features section in Operating Range table and in the DC Electrical Characteristics table Added foot note in page 1 Changed the Maximum rating of Ambient Temperature with Power Applied from 10 C to 85 C to 55 C to 4125 C Changed Vper Max spec from 0 85V to 0 95V in the DC Electrical Characteristics table and in the note below the table Updated footnote 21 to specify Overshoot and Undershoot Spec Updated Ipp and lag values Updated Oj and O c values Removed x9 part and its related information Updated footnote 25 E 1351243 See ECN VKN FSU Converted from preliminary to final Added x8 and x9 parts Changed toya max spec to 8 4 ns for all speed bins Updated footnote 23 Updated Ordering Information table F 2181046 See ECN VKN AESA Added footnote 22 related to Ipp Cypress Semiconductor Corporation 2005 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medica
23. bit is preset HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Page 13 of 28 Feedback YPRESS PERFORM CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 The state diagram for the TAP controller follows 12 TAP Controller State Diagram i TEST LOGIC RESET E 1 TEST LOGIC SELECT 1 SELECT py IDLE DR SCAN IR SCAN vy vy 1 1 CAPTURE DR CAPTURE IR 0 Y oy P SHIFT DR P SHIFT IR p ty ty 1 E EXIT1 DR Pp EXIT1 IR y y PAUSE DR p PAUSE IR ty Y 0 0 EXIT2 DR EXIT2 IR EN NM ty UPDATE IR UPDATE DR 4 Note y 1 Document Number 001 05384 Rev F 12 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Page 14 of 28 Feedback CY7C1561V18 CY7C1576V18 2P CYPRESS CY7C1563V18 CY7C1565V18 PERFORM TAP Controller Block Diagram 0 Bypass Register 2 1 0 r Selection TDI a Instruction Register Selection L TDO Circuitry VEU in
24. dress Hold after K Clock Rise 04 104 04 04 ns tuc tiuix Control Hold after K Clock Rise RPS WPS 04 04 04 04 ns tucppR ltkHix Double Data Rate Control Hold after Clock K K 0 28 028 028 028 ns Rise BWSo BWS BWS3 BWS3 tup tkHDXx Do Hold after Clock K K Rise 0 28 028 028 028 ns Output Times tco tcHav K K Clock Rise to Data Valid 045 0 45 0 45 10 45 ns tDoH tcHax Data Output Hold after Output K K Clock Rise 0 45 0 45 0 45 0 45 ns Active to Active tccoo tcHcav K K Clock Rise to Echo Clock Valid 0 45 0 45 045 0 45 ns cooH tcHcax Echo Clock Hold after K K Clock Rise 0 45 0 45 0 45 0 45 ns tcap tcaHav Echo Clock High to Data Valid 0 2 0 2 0 2 0 2 ns tcopoH tcaqHuax Echo Clock High to Data Invalid 0 2 02 02 0 2 ns tcoH tcoucaL Output Clock CQ CQ HIGH 26 0 81 0 88 m 1 03 1 15 a ns lcoHcGH coucanH CQ Clock Rise to CQ Clock Rise P6l 0 81 0 88 103 1 15 ns rising edge to rising edge tcHz tcHaz Clock K K Rise 19 high Z 0 45 045 045 0 45 ns eve to Pigh Z tciz tcuoxt Clock K K Rise to Low z 9 27 0 45 0 45 045 045 ns tavip tcaHavip Echo Clock High to QVLD Valid 29 0 20 0 20 0 20 0 20 0 20 0 20 0 20 0 20 ns DLL Timing tke Var tkc Var Clock Phase Jitter 020 0 20 020 0 20
25. erating Range Ambient Temperature with Power Applied 55 C to 125 C Ambient Supply Voltage on Vpp Relative to GND 0 5V to 2 9V Range Temperature Ta Voo vppg 8l Supply Voltage on Vppo Relative to GND 0 5V to Vpp Commercial 0 C to 70 C 1 8 0 1V 1 4V to DC Applied to Outputs in High Z 0 5V to Vppq 0 3V Industrial 40 C to 85 C VoD DC Input Voltage 14 0 5V to Vpp 0 3V Electrical Characteristics DC Electrical Characteristics Over the Operating Range 19 Parameter Description Test Conditions Min Typ Max Unit Vpp Power Supply Voltage 1 7 1 8 1 9 V VDDQ IO Supply Voltage 1 4 1 5 Vpp V Vou Output HIGH Voltage Note 19 Vppo 2 0 12 Vppo 2 0 12 V VoL Output LOW Voltage Note 20 Vppo 2 0 12 Vppo 2 0 12 V VoH Low Output HIGH Voltage lou 0 1 mA Nominal Impedance Vppq 0 2 VDDQ V Vor ow Output LOW Voltage lo 0 1mA Nominal Impedance Vss 0 2 V Vin Input HIGH Voltage 7 Vngr 0 1 Vppg 0 15 V ViL Input LOW Voltage T 0 15 Vner 0 1 V Ix Input Leakage Current GND lt Vi lt Vppa 2 2 pA loz Output Leakage Current GND lt V lt Vppq Output Disabled 2 2 pA VREF Input Reference Voltage ETI Typical Value 0 75V 0 68 0 75 0 95 V Ipp 22 Vpp Operating Supply Vpp Max 400 MHz x8 1400 mA pu P ae x9 1400 x18 1400 x36 1400 375 MHz x8 1300 mA x9 1300 x18 1300 x36 1300 Notes 18 Power up Assumes a linear ramp from OV to Vpp min with
26. f the input clock K or K T maintain the internal logic each read access must be allowed t complete Each read access consists of four 18 bit data words and takes two clock cycles to complete Therefore read accesses to the device cannot be initiated on two consecutive K clock rises The internal logic of the device ignores the second read request Read accesses can be initiated on every other K clock rise Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the input clocks K and K When the read port is deselected the CY7C1563V18 first completes the pending read transactions Synchronous internal circuitry automatically tri states the outputs following the next rising edge of the negative input clock K This enables for a Document Number 001 05384 Rev F CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock K On the following K clock rise the data presented to Dj47 9 is latched and stored into the lower 18 bit write data register provided BWS 1 0 are both asserted active On the subsequent rising edge of the negative input clock K the information presented to D 17 9 is also stored into the write data register provided BWS 9 are both asserted ac
27. he rising edge of TCK This pin may be left unconnected if the TAP is not used The pin is pulled up inter nally resulting in a logic HIGH level Test Data In TDI The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see the The state diagram for the TAP controller follows IM on page 14 TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB on any register Test Data Out TDO The TDO output pin is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine see Instruction Codes on page 17 The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register Performing a TAP Reset A Reset is performed by forcing TMS HIGH Vpp for five rising edges of TCK This Reset does not affect the operation of the SRAM and can be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a high Z state TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry Only one register can be
28. higher density devices The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the input and output ring Boundary Scan Order on page 18 shows the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the Identification Register Definitions on page 17 TAP Instruction Set Eight different instructions are possible with the three bit instruction register All combinations are listed in the Instruction Codes on page 17 Three of these instructions are listed as RESERVED and must not be used The other five instructions are described in this section in detail Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and T
29. in 200 ms During this time Vi lt Vpp and Vppq lt Vpp 19 Output are impedance controlled lo Vppq 2 RQ 5 for values of 175 ohms lt RQ lt 350 ohms 20 Output are impedance controlled Io Vppo 2 RQ 5 for values of 175 ohms lt RQ lt 350 ohms 21 Vggr min 0 68V or 0 46Vppq whichever is larger Vage max 0 95V or 0 54Vppq whichever is smaller 22 The operation current is calculated with 50 read cycle and 50 write cycle Document Number 001 05384 Rev F Page 20 of 28 Feedback em CY7C1561V18 CY7C1576V18 Z CYPRESS CY7C1563V18 CY7C1565V18 PERFORM Electrical Characteristics continued DC Electrical Characteristics Over the Operating Range 15 Parameter Description Test Conditions Min Typ Max Unit Ipp 22 Vpp Operating Supply Vpp Max 333 MHz x8 1200 mA lour 0 mA x9 1200 P x18 1200 x36 1200 300 MHz x8 1100 mA x9 1100 x18 1100 x36 1100 Ispi Automatic Power down Max Vpp 400 MHz x8 550 mA Current Both Ports Deselected x 550 Vin 2 Vin OF Vin lt Vit f fmax 1 tcyc Inputs x18 550 Static x36 550 375 MHz x8 525 mA x9 525 x18 525 x36 525 333 MHz x8 500 mA x9 500 x18 500 x36 500 300 MHz x8 450 mA x9 450 x18 450 x36 450 Document Number 001 05384 Rev F Page 21 of 28 Feedback CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18
30. ing clock and is synchronized to the input clock K of the QDR II The timings for the echo clocks are shown in the Switching Characteristics on page 23 Document Number 001 05384 Rev F Page 6 of 28 Feedback CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 Pin Description Output Impedance Matching Input This input is used to tune the device outputs to the system data bus impedance CQ CQ and Q 9 output impedance are set to 0 2 x RQ where RQ is a resistor connected between ZQ and ground Alternately this pin can be connected directly to Vppq which enables the E P PERFORM Pin Definitions continued Pin Name IO ZQ Input minimum impedance mode This pin cannot be connected directly to GND or left unconnected DOFF Input DLL Turn Off Active LOW Connecting this pin to ground turns off the DLL inside the device The timings in the DLL turned off operation are different from those listed in this data sheet For normal operation this pin can be connected to a pull up through a 10 KO or less pull up resistor The device behaves in QDR I mode when the DLL is turned off In this mode the device can be operated at a frequency of up to 167 MHz with QDR I timing TDO Output TDO for JTAG TCK Input TCK Pin for JTAG TDI Input TDI Pin for JTAG TMS Input TMS Pin for JTAG NC N A Not Connected to the Die Can be tied to any voltage level NC 144M N A Not Con
31. l life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT
32. ll Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free Document Number 001 05384 Rev F Page 25 of 28 Feedback P CYPRESS Ordering Information continued Not all of the speed package and temperature ranges are available Please contact your local sales representative or PERFORM visit www cypress com for actual products offered CY7C1561V18 CY7C1 CY7C1563V18 CY7C1 576V18 565V18 Ordering Code Package Diagram Package Type Operating Range CY7C1561V18 333BZC CY7C1576V18 333BZC CY7C1563V18 333BZC CY7C1565V18 333BZC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1561V18 333BZXC CY7C1576V18 333BZXC CY7C1563V18 333BZXC CY7C1565V18 333BZXC CY7C1561V18 333BZl CY7C1576V18 333BZl CY7C1563V18 333BZl CY7C1565V18 333BZl 51 85195 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Commercial Industrial CY7C1561V18 333BZXI CY7C1576V18 333BZXI CY7C1563V18 333BZXI CY7C1565V18 333BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free 300 CY7C1561V18 300BZC CY7C1576V18 300BZC CY7C1563V18 300BZC CY7C1565V18 300BZC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Commercial CY7C1561V18 300BZXC CY7C1576V18 300BZXC CY7C1563V18
33. n is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST The EXTEST instruction drives the preloaded data out through the system output pins This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift DR controller state EXTEST OUTPUT BUS TRI STATE IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a tri state mode The boundary scan register has a special bit located at bit 108 When this scan cell called the extest output bus tri state is latched into the preload register during the Update DR state in the TAP controller it directly controls the state of the output Q bus pins when the EXTEST is entered as the current instruction When HIGH it enables the output buffers to drive the output bus When LOW this bit places the output bus into a High Z condition This bit can be set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell latches into the preload register When the EXTEST instruction is entered this bit directly controls the output Q bus pins Note that this
34. nected to the Die Can be tied to any voltage level NC 288M N A Not Connected to the Die Can be tied to any voltage level VREF Input Reference Voltage Input Static input used to set the reference level for HSTL inputs and Outputs as Reference well as AC measurement points Vpp Power Supply Power Supply Inputs to the Core of the Device Vss Ground Ground for the Device VDDQ Power Supply Power Supply Inputs for the Outputs of the Device Page 7 of 28 Feedback Document Number 001 05384 Rev F D 2s a SES Cypress PERFORM Functional Overview The CY7C1561V18 CY7C1576V18 CY7C1563V18 and CY7C1565V18 are synchronous pipelined Burst SRAMs equipped with a read port and a write port The read port is dedicated to read operations and the write port is dedicated to write operations Data flows into the SRAM through the write port and out through the read port These devices multiplex the address inputs to minimize the number of address pins required By having separate read and write ports the QDR II completely eliminates the need to turn around the data bus and avoids any possible data contention thereby simplifying system design Each access consists of four 8 bit data transfers in the case of CY7C1561V18 four 9 bit data transfers in the case of CY7C1576V18 four 18 bit data transfers in the case of CY7C1563V18 and four 36 bit data transfers in the case of CY7C1565V18 in two clock cycles
35. ns tke lock tkc lock DLL Lock Time K 2048 2048 2048 2048 cycles tkc Reset tkc Reset K Static to DLL Reset 30 30 30 30 30 ns Notes 24 When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range 25 This part has a voltage regulator internally tpowgg is the time that the power is supplied above VDD minimum initially before a read or write operation can be initiated 26 These parameters are extrapolated from the input timing parameters tk WK 250ps where 250ps is the internal jitter An input jitter of 200ps t cyAg is already included in the tkyKH These parameters are only guaranteed by design and are not tested in production 27 tore telz are specified with a load capacitance of 5 pF as in part b of AC Test Loads and Waveforms on page 22 Transition is measured 100 mV from steady state voltage 28 At any given voltage and temperature toyz is less than tc 7 and toyz less than tco m tavi p spec is app icabl for both rising and falling edges of QVLD signal 0 Hol dio gt Viy or Vj Document Number 001 05384 Rev F Page 23 of 28 Feedback AE CY7C1561V18 CY7C1576V18 Te CYPRESS CY7C1563V18 CY7C1565V18 PERFORM Switching Waveforms Read Write Deselect Sequence 31 32 33 Figure 5 Waveform
36. nto the device BWSg Input Byte Write Select 0 1 2 and 3 Active LOW Sampled on the rising edge of the K and K clocks when BWS Synchronous write operations are active Used to select which byte is written into the device during the current portion BWS of the write operations Bytes not written remain unaltered BWS3 CY7C1576V18 BWSp controls Dyg o CY7C1563V18 BWSp controls Drs oj and BWS controls Dr 7 9 CY7C1565V18 BWSp controls Drs g BWS controls Dri 7 9 BWS controls Djog 19 and BWS3 controls Drss 27 All the Byte Write Selects are sampled on the same edge as the data Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device A Input Address Inputs Sampled on the rising edge of the K clock during active read and write operations These Synchronous address inputs are multiplexed for both read and write operations Internally the device is organized as 8M x 8 4 arrays each of 2M x 8 for CY7C1561V18 8M x 9 4 arrays each of 2M x 9 for CY7C1576V18 4M x 18 4 arrays each of 1M x 18 for CY7C1563V18 and 2M x 36 4 arrays each of 512K x 36 for CY7C1565V18 Therefore only 21 address inputs are needed to access the entire memory array of CY7C1561V18 and CY7C1576V18 20 address inputs for CY7C1563V18 and 19 address inputs for CY7C1565V18 These inputs are ignored when the appropriate port is deselected Qix 0 Outputs Data Output Signals These pins drive out the requested
37. ocooo ocoooo J o0Ooooooooooo K 3 eo0000dg00000 L 8 i 00000 00000 M oo0o000000000 N 900000000 O00 P 60000 o0oooeoe R A 1 00 5 00 10 00 B tM 15 00 0 10 A 0 15 4X NOTES SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0 65g JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE CODE BBOAD 51 85195 A Page 27 of 28 Feedback a CY7C1561V18 CY7C1576V18 EP CYPRESS CY7C1563V18 CY7C1565V18 PERFORM Document History Page Document Title CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 72 Mbit QDR II SRAM 4 Word Burst Archi tecture 2 5 Cycle Read Latency Document Number 001 05384 ISSUE ORIG OF REV ECN NO DATE CHANGE DESCRIPTION OF CHANGE ee 402911 See ECN VEE New Data Sheet A 425251 See ECN VEE Updated the switching waveform Corrected the typos in DC parameters Updated the DLL section Added additional notes in the AC parameter section Updated the Power up sequence Added additional parameters in the AC timing B 437000 See ECN IGS ECN for Show on web C 461934 See ECN NXR Moved the Selection Guide table from page 3 to page 1 Modified Application Diagram Changed try and t from 40 ns to 20 ns changed truss trois tcs trMSH trDiH tcu from 10 ns to 5 ns and changed trpoy from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power Up waveform Included Maximum ratings for Supply Voltage on Vppq Relative to GND Changed the Maximum R
38. of any data pin This signal is asserted half a cycle before valid data arrives DLL These chips use a Delay Lock Loop DLL that is designed to function between 120 MHz and the specified maximum clock frequency The DLL may be disabled by applying ground to the DOFF pin When the DLL is turned off the device behaves in QDR I mode with 1 0 cycle latency and a longer access time For more information refer to the application note DLL Consid erations in QDRIIDDRII QDRII DDRII The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30ns However it is not necessary to reset the DLL to lock to the desired frequency During Power up when the DOFF is tied HIGH the DLL is locked after 2048 cycles of stable clock Figure 1 Application Example Vt SRAM 1 RQ 250ohms RQ 250ohms DATA IN DATA OUT Address zQ CO CQ Q RPS WPS BWS K K AA SRAM 4 BUS MASTER RPS CPU or ASIC BWS CLKIN CLKIN Source K e Source K Document Number 001 05384 Rev F R 50ohms Vt Vppo 2 Page 9 of 28 Feedback ER x CY7C1561V18 CY7C1576V18 2P CYPRESS CY7C1563V18 CY7C1565V18 PERFORM The truth table for CY7C1561V18 CY7C1576V18 CY7C1563V18 and CY7C1565V18 follows I 5 6 7 8 Truth Table Operation K RPS WPS DQ DQ DQ DQ Write Cycle L H HI LI 0 D A a
39. oj remains unaltered H H L L H During the Data portion of a write sequence only the byte Di35 27 is written into the device Drog oj remains unaltered L H No data is written into the device during this portion of a write operation L H No data is written into the device during this portion of a write operation Document Number 001 05384 Rev F Page 11 of 28 Feedback CYPRESS PERFORM IEEE 1149 1 Serial Boundary Scan JTAG These SRAMs incorporate a serial boundary scan Test Access Port TAP in the FBGA package This part is fully compliant with IEEE Standard 1149 1 2001 The TAP operates using JEDEC standard 1 8V IO logic levels Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternatively be connected to Vpp through a pull up resistor TDO must be left unconnected Upon power up the device comes up in a reset state which does not interfere with the operation of the device Test Access Port Test Clock The test clock is used only with the TAP controller All inouts are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select TMS The TMS input is used to give commands to the TAP controller and is sampled on t
40. pletely independently of one another As each port latches the address inputs on different clock edges the user can read or write to any location regardless of the transaction on the other port If the ports access the same location when a read follows a write in successive clock cycles the SRAM delivers the most recent information associated with the specified address location This includes forwarding data from a write cycle that was initiated on the previous K clock rise Read access and write access must be scheduled such that one transaction is initiated on any clock cycle If both ports are selected on the same K clock rise the arbitration depends on the previous state of the SRAM If both ports are deselected the read port takes priority If a read was initiated on the previous cycle the write port takes priority as read operations cannot be initiated on consecutive cycles If a write was initiated on the previous cycle the read port takes priority since write operations cannot be initiated on consecutive cycles Therefore asserting both port selects active from a deselected state results in alter nating read or write operations being initiated with the first access being a read Page 8 of 28 Feedback Depth Expansion The CY7C1563V18 has a port select input for each port This enables for easy depth expansion Both port selects are sampled on the rising edge of the positive input clock only K Each port selec
41. re registered at K and K rising edges Data outputs are delivered on K and K rising edges also 8 Itis recommended that K K HIGH when clock is stopped This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically 9 If this signal was LOW to initiate the previous cycle this signal becomes a Don t Care for this operation 10 This signal was HIGH on previous K clock rise Initiating consecutive read or write operations on consecutive K clock rises is not permitted The device ignores the second read or write request 11 Is based on a write cycle was initiated per the The write cycle description table for CY7C1561V18 and CY7C1563V18 follows 11 table NWSp NWS BWSo BWS BWS and BWS can be altered on different portions of a write cycle as long as the setup and hold requirements are achieved Document Number 001 05384 Rev F Page 10 of 28 Feedback CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 as P E P ER F o RM The write cycle description table for CY7C1576V18 follows I9 11 Write Cycle Descriptions BWS K K L L H During the Data portion of a write sequence the single byte Djg o is written into the device L L H During the Data portion of a write sequence the single byte Drg gj is written into the device H L H No data is written into the device during thi
42. s TDI Setup to TCK Clock Rise 5 ns tes Capture Setup to TCK Rise 5 ns Hold Times trusH TMS Hold after TCK Clock Rise 5 ns trpiH TDI Hold after Clock Rise 5 ns tcu Capture Hold after Clock Rise 5 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions 17 Figure 2 TAP Timing and Test Conditions 0 9V ALL INPUT PULSES 500 1 8V mm TDO ov gee LG 20pF a GND trn tL ahi ji igi e Test Clock N TEK trcvc trusH H8 P truss I Test Mode Select TMS C LX XU X trpis TTDIH et Test Data In TDI XN MB REN Test Data Out TDO A Notes trpov trpoxl 16 tcs and toy refer to the setup and hold time requirements of latching data from the boundary scan register 17 Test conditions are specified using the load in TAP AC Test Conditions tp te 1 ns Document Number 001 05384 Rev F Page 16 of 28 Feedback d PI CYPRESS PER FORM CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 Identification Register Definitions Value Instruction Field Description CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 b Revision Number 000 000 000 000 Version number 31 29 Cypre
43. s portion of a write operation H L H No data is written into the device during this portion of a write operation The write cycle description table for CY7C1565V18 follows 9 11 Write Cycle Descriptions BWSg BWS BWS BWS3 K K Comments L L L L L H During the Data portion of a write sequence all four bytes Djs5 o are written into the device L L H During the Data portion of a write sequence all four bytes D 35 0 are written into the device L H H L H During the Data portion of a write sequence only the lower byte Djg o is written into the device Djss 9j remains unaltered L H H H L H During the Data portion of a write sequence only the lower byte Djg o is written into the device Drs gj remains unaltered H L L H During the Data portion of a write sequence only the byte Dr7 gj is written into the device Drg gj and Drss 1gj remains unaltered H H L H During the Data portion of a write sequence only the byte Dr7 9 is written into the device Drg oj and Di35 1g remains unaltered H H L H L H jDuring the Data portion of a write sequence only the byte Dja 1g is written into the device Dr 7 9j and Dj35 27 remains unaltered H H L H L H During the Data portion of a write sequence only the byte Droe 18 is written into the device Dr 7 oj and Djas 7 remains unaltered H L L H During the Data portion of a write sequence only the byte Dras 27 is written into the device Drog
44. ss Device ID 11010010001000100 11010010001001100 11010010001010100 11010010001100100 Defines the type of 28 12 SRAM Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique 11 1 identification of SRAM vendor ID Register 1 1 1 1 Indicates the Presence 0 presence of an ID register Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 109 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the input and output ring contents Places the boundary scan register between TDI and TDO Does not affect the SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operation Document Number 001 05384 Rev F Page 17 of 28 Feedback 1
45. t K t 1 T D A 1 at K t 1 T D A 2 at K t 2 T D A 3 at K t 2 T Load address on the rising edge of K input write data on two consecutive K and K rising edges Read Cycle L H LUO x iQ A at K t 2 Q A 1 at K t 3 1 Q A 2 at K t 3 1 Q A 3 at K t 4 T 2 5 cycle Latency Load address on the rising edge of K wait two and a half cycles read data on two consecutive K and K rising edges NOP No Operation L H H H D X D X D X D X Q High Z Q High Z Q High Z Q High Z Standby Clock Stopped Stopped X X Previous State Previous State Previous State Previous State The write cycle description table for CY7C1561V18 and CY7C1563V18 follows P 11 Write Cycle Descriptions BWSy BWS NWS NWS L L L H During the data portion of a write sequence CY7C1561V18 both nibbles Dr oj are written into the device CY7C1563V18 both bytes acai are written into the device L L L H During the data portion of a write sequence CY7C1561V18 both nibbles Dr 9j are written into the device CY7C1563V18 both bytes Dr 7 9j are written into the device L H L H During the data portion of a write sequence CY7C1561V18 only the lower nibble Dj3 9 is written into the device Dr7 4j remains unaltered CY7C1563V18 only the lower byte Digo Is written into the device Dji7 9 remains unaltered L H L H During the data portion of a write
46. t input can deselect the specified port Deselecting a port does not affect the other port All pending transactions read and write are completed prior to the device being deselected Programmable Impedance An external resistor RQ must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output driver impedance The value of RQ must be 5X the value of the intended line impedance driven by the SRAM the allowable range of RQ to guarantee impedance matching with a tolerance of 15 is between 1750 and 350Q with Vppq 1 5V The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature Echo Clocks Echo clocks are provided on the QDR II to simplify data capture on high speed systems Two echo clocks are generated by the QDR II CQ is referenced with respect to K and CQ is refer enced with respect to K These are free running clocks and are synchronized to the input clock of the QDR II The timing for the echo clocks are shown in Switching Characteristics on page 23 Application Example Figure 1 shows four QDR II used in an application CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 Valid Data Indicator QVLD QVLD is provided on the QDR II to simplify data capture on high speed systems The QVLD is generated by the QDR II device along with data output This signal is also edge aligned with the echo clock and follows the timing
47. tive This process continues for one more cycle until four 18 bit words a total of 72 bits of data are stored in the SRAM The 72 bits of data are then written into the memory array at the specified location Therefore write accesses to the device cannot be initiated on two consecutive K clock rises The internal logic of the device ignores the second write request Write accesses can be initiated on every other rising edge of the positive input clock K Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks K and K When deselected the write port ignores all inputs after the pending write operations have been completed Byte Write Operations Byte write operations are supported by the CY7C1563V18 A write operation is initiated as described in the Write Operations section The bytes that are written are determined by BWS and BWS which are sampled with each set of 18 bit data words Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered This feature can be used to simplify read modify or write operations to a Byte write operation Concurrent Transactions The read and write ports on the CY7C1563V18 operates com
48. us inputs pass through input registers controlled by the K or K input clocks All data outputs pass through output registers controlled by the K or K input clocks Writes are conducted with on chip synchronous self timed write circuitry Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Maximum Operating Frequency 400 375 333 300 MHz Maximum Operating Current x8 1400 1300 1200 1100 mA x9 1400 1300 1200 1100 x18 1400 1300 1200 1100 x36 1400 1300 1200 1100 Note 1 The QDR consortium specification for Vppq is 1 5V 0 1V The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting Vppo 1 4V to Vpp Cypress Semiconductor Corporation Document Number 001 05384 Rev F 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 6 2008 Feedback Mu CY7C1561V18 CY7C1576V18 CYPRESS CY7C1563V18 CY7C1565V18 PERFORM Logic Block Diagram CY7C1561V18 Dir Ide Write Write Write Write Reg gt Reg gt Reg Reg Address ud on A 20 0 Register Address 20 0 TE gt o keny 9 x NG Control Keny 9 X NZ Kelly 9 X NZ Write Add Decode Keny 9 x NG Read Add Decode Read Data Reg Control Logic Logic Block Diagram CY7C1576V18 Piso IX Write Write Write Write
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