Cypress NoBL CY7C1470V33 User's Manual
Contents
1. is controlled by BW DQPy is controlled by BW is controlled by BW DQP is controlled by is controlled by BWs DOP is controlled BW is controlled by BWg DOP is controlled by BW MODE Input Strap Pin Mode Input Selects the burst order of the device Tied HIGH selects the interleaved burst order Pulled LOW selects the linear burst order MODE should not change states during operation When left floating MODE will default HIGH to an interleaved burst order TDO JTAG Serial Serial data out to the JTAG circuit Delivers data on the negative edge of TCK Output Synchronous TDI JTAG Serial Input Serial data In to the JTAG circuit Sampled on the rising edge of TCK Synchronous Document 38 05289 Rev I Page 6 of 29 Feedback CY7C1470V33 Z CY7C1472V33 CYPRESS CY7C1474V33 PERFORM Pin Definitions continued Pin Name Type Pin Description TMS Test Mode Select This pin controls the Test Access Port state machine Sampled on the rising edge of TCK Synchronous TCK JTAG Clock Clock input to the JTAG circuitry Vpp Power Supply Power supply inputs to the core of the device VDDQ Power Supply Power supply for the I O circuitry Vss Ground Ground for the device Should be connected to ground of the system NC _ No connects This pin is not connected to the die NC 144M These pins are not connected They wi2. L s N 00000 R 5 00 10 00 B 15 00 0 10 A 0 15 4 51 85165 A Page 26 of 29 Feedback CY7C1470V33 CY7C1472V33 CYPRESS CY7C1474V33 PERFORM M Package Diagrams continued 209 ball FBGA 14 x 22 x 1 76 mm 51 85167 51 85167 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation ZBT is a trademark of Integrated Device Technology All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05289 Rev I Page 27 of 29 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application impl
3. 3 4 5 on ae a 1 N VEN _ p UL DA LU LE 27 AZ UEM _ MUM UT Z7 w LL mA _ 77 mas DOA NA XC e ILC 2 Z E A Z _ A ps beeJeeelk 94 Bp 2 rLR LUu ADV D Z l Data VX DAD 08 Qa DER Q A3 am 0 Q ous 0 T T T In Out DQ WRITE READ STALL READ WRITE STALL NOP READ DESELECT CONTINUE D A1 Q A2 Q A3 D A4 Q A5 DESELECT V Z DON T CARE UNDEFINED ZZ Mode 26 27 H HY AA H t ZZREC z tz suppLy i Ht DDZZ tma except ZZ DON T CARE Notes 25 The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrated CEN being used to create a pause A Write is not performed during this cycle 26 Device must be deselected when entering ZZ mode See cycle description table for all possible signal conditions to deselect the device 27 Os are in High Z when exiting ZZ sleep mode Document 38 05289 Rev I Page 22 of 29 Feedback i Z CYPRESS PERFORM Ordering Information CY7C1470V33 CY7C1472V33 CY7C1474V33 Not all of the speed package and temperature ranges are available Please contact your local sales re
4. ADV D 0 BWa WRITE REGISTRY EN AND DATA COHERENCY WRI s B DQs BW CONTROL LOGIC DRIVERS i E DQPa BWa 5 E DQP BWe E R H BW R N DQPs BWo G DQPe BWh E E DQPr EM DQPh WE DE READ LOGIC CE2 CE3 22 Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Access Time 3 0 3 0 3 4 ns Maximum Operating Current 500 500 450 mA Maximum CMOS Standby Current 120 120 120 mA Document 38 05289 Rev I Page 2 of 29 Feedback M lt CYPRESS PERFORM CY7C1470V33 CY7C1472V33 CY7C1474V33 100 pin TQFP Packages Pin Configurations QS IS S S o o ox 2 gt lt HH P sopes Q SS2ESVSsSKsSSSsSBssas DQPcH 1 80 DQPb DQc 2 79 DQb DQcH 3 78 DQb 4 77 H Vona Vss O 5 76 3 Vss DQcH 6 75 DQb DQc 7 74 DQb DQc 8 73 DQb DQc 9 72 DQb Vss r 10 71 O Vss Vopor 11 70 H Vppa DQc 12 69 DQb DQc 13 68 DQb NG H 14 67 H Vss CY7C1470V33 FING Vss 17 2M x 36 64 F1 ZZ DQdq 18 63 L1 DQa DQdH 19 62 DQa Vppad 20 61 H Vppo Vss 21 60 L1 Vss DQdrj 22 59 DQa DQdq 23 58 DQa DQdrj 24 57 DQa
5. 21 60 1 Vss 22 59 DQa 23 58 DQa 24 57 O NC 25 56 NC 26 55 H Vss 27 54 28 53 ANC 29 52 NC 30 51 NC N CO LO O0 A x 10 QD lt CO CO CO CO CO CO s LO LI LI LT UU LI Ww lt lt lt lt T Qo DO lt lt lt lt lt lt lt lt 9 ae gt 28 Page 3 of 29 Feedback CY7C1470V33 CY7C1472V33 F CYPRESS CY7C1474V33 PERFORM Pin Configurations continued 165 ball FBGA 15 x 17 x 1 4 mm Pinout CY7C1470V33 2M x 36 1 2 3 4 5 6 7 8 9 10 11 576 BW BW CEN ADV LD A A NC B NC 1G A CE2 BW BW CLK WE OE A A NC C DQP NC Vppo Vss Vss Vss Vss Vss VDDQ NC DQP D DQ DQ Vpp Vss Vss Vss Vpp DQ DQp E DQ DQ Vppo Vpp Vss Vss Vss Vpp DQp F DQ DQ Vppo VDD Vss Vss Vss VDD DQp G DQ DQ VDD Vss Vss Vss Vpp Vppa DQ DQp H NC NC NC Vss Vss Vss VoD 72 J DQg DQg Vppo Vpp Vss Vss Vss Vpp DQ DQ K DQg DQg Vppo Vpp Vss Vss Vss VDD Vppo DQ DQ L DQg Vpp Vss Vss Vss Vpp DQ DQ M Vpp Vss Vss Vss Vpp DQ DQ N NC Vooo Vss NC NC NC Vss Vba NC DOP P NC 144M A
6. SEATING PLANE A f N STAND OFF q 025 L 0 05 MIN NOTE ne 0 15 MAX GAUGE PLANE I HN 1 JEDEC STD REF MS 026 TOR co 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH Y RGOEMIN MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 0 7 0 20 MAX BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 e 020 MIN 51 85050 B 1 00 REF DETAIL Document 38 05289 Rev I Page 25 of 29 Feedback Package Diagrams continued 165 ball FBGA 15 x 17 x 1 4 mm 51 85165 CY7C1470V33 CY7C1472V33 CY7C1474V33 gt j 1700 0 10 TOP VIEW s PIN 1 CORNER 1 2 1 4 5 7 8 10 11 A B D E G H J K L M N P R 8 82 3 8 7 3 N 8 5 X 3 1 I POT SEATING PLANE g H 3 Document 38 05289 Rev I 1 40 MAX BOTTOM VIEW PIN 1 CORNER g NE 0 25 MEAIB 0 45 0 05 165X 9 7 6 5 4 3 2 1 x L 4 e oooo ooood T 90000 c 8 D 00000 E F 00000 e o O J 00000 00000 K
7. P c r Lm e ss SM ra SSE 00 207 Fsx sx YPRESS CY7C1470V33 CY7C1472V33 CY7C1474V33 PERFOR Features Pin compatible and functionally equivalent to ZBT Supports 250 MHz bus operations with zero wait states Available speed grades are 250 200 and 167 MHz Internally self timed output buffer control to eliminate the need to use asynchronous OE Fully registered inputs and outputs for pipelined operation Byte Write capability Single 3 3V power supply 3 3V 2 5V I O power supply Fast clock to output time 3 0 ns for 250 MHz device Clock Enable CEN pin to suspend operation Synchronous self timed writes CY7C1470V33 CY7C1472V33 available in JEDEC standard lead free 100 pin TQFP lead free and non lead free 165 ball FBGA package CY7C1474V33 available in lead free and non lead free 209 ball FBGA package IEEE 1149 1 JTAG Boundary Scan compatible Burst capability linear or interleaved burst order ZZ Sleep Mode option and Stop Clock option 72 Mbit 2M x 36 4M x 18 1M x 72 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1470V33 CY7C1472V33 and CY7C1474V33 are 3 3V 2M x 36 4M x 18 1 x 72 Synchronous pipelined burst SRAMs with No Bus Latency NoBL logic respectively They are designed to support unlimited true back to back Read Write operations with wait states
8. 0 3 0 8 V Vppo 2 5V 0 3 0 7 V lx Input Load Current GND lt Vin lt VDDQ 5 5 uA Note 11 All voltages referenced to Vss GND Document 38 05289 Rev I Page 14 of 29 Feedback CY7C1470V33 e CY7C1472V33 CYPRESS CY7C1474V33 sd PERFORM Identification Register Definitions CY7C1470V33 CY7C1472V33 CY7C1474V33 Instruction Field 2M x 36 4M x 18 1M x 72 Description Revision Number 31 29 000 000 000 Describes the version number Device Depth 28 24 172 01011 01011 01011 Reserved for internal use Architecture Memory 001000 001000 001000 Defines memory type and archi Type 23 18 tecture Bus Width Density 17 12 100100 010100 110100 Defines width and density Cypress JEDEC ID Code 00000110100 00000110100 00000110100 Allows unique identification of 11 1 SRAM vendor ID Register Presence 1 1 1 Indicates the presence of an ID Indicator 0 register Scan Register Sizes Register Name Bit Size x36 Bit Size x18 Bit Size x72 Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order 165 FBGA 71 52 Boundary Scan Order 209 FBGA 110 Identification Codes Instruction Code Description EXTEST 000 Captures I O ring contents Places the boundary scan register between TDI and TDO Forces all SRAM outputs to High Z state This instruction is not 1149 1 compliant IDCODE 001 Load
9. 11 10 01 00 f DQ p ca DOP ap og for 470 DQ DQP for Linear Burst Address Table MODE GND CY701472V33 are automatically tri stated during the data First 5 d Third Fourth ortion of a Write cycle regardless of the state of OE Irs econ Ir our P 3 Address Address Address Address Burst Write Accesses A1 A0 A1 A0 A1 A0 A1 A0 The CY7C1470V33 CY7C1472V33 and CY7C1474V33 has 00 01 10 11 an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Write opera 01 10 11 00 tions without reasserting the address inputs ADV LD must be 10 11 00 01 driven LOW in order to load the initial address as described 11 00 01 10 in the Single Write Access section above When ADV LD is driven HIGH subsequent clock rise the Chip Enables CE CEs and CE3 and WE inputs are ignored and the burst counter is incremented The correct BW BWa b c d e t g h for ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ gt Vpp 0 2V 120 mA 1775 Device operation to ZZ ZZ Vpp 0 2V 2tcvc ns tzznEC ZZ recovery time ZZ lt 0 2V 2tcvc ns tzzi ZZ active to sleep current This parameter is sampled 2tcyc ns trzzI ZZ Inactive to exit sleep current This parameter is sampled 0 ns Document 38 05289 Rev I Page 8 of 29 T
10. 51 71 B 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M 34 RH 54 A 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10 a7 e 3 EH 5 Boo 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R 40 KH 6 A Boundary Scan Exit Order 4M x 18 Bit 165 Ball ID Bit 4 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID 1 D2 14 R4 27 L10 40 B10 2 E2 15 P6 28 K10 41 A8 3 F2 16 R6 29 J10 42 B8 4 G2 17 R8 30 H11 43 A7 5 Ji 18 P3 31 G11 44 B7 6 K1 19 P4 32 F11 45 B6 7 L1 20 P8 33 E11 46 A6 8 M1 21 P9 34 D11 47 B5 9 1 22 10 35 11 48 A4 10 R1 23 R9 36 A11 49 B3 11 R2 24 R10 37 A9 50 A3 12 R3 25 R11 38 B9 51 A2 13 P2 26 M10 39 A10 52 B2 Document 38 05289 Rev I Page 16 of 29 Feedback CY7C1470V33 CY7C1472V33 CYPRESS CY7C1474V33 PERFORM Boundary Scan Exit Order 1M x 72 Bit 209 Ball ID Bit 209 Ball ID Bit 209 Ball ID Bit 209 Ball ID 1 Al 29 T1 57 U10 85 11 2 2 30 T2 58 T11 86 B10 3 B1 31 U1 59 T10 87 A11 4 B2 32 U2 60 R11 88 A10 5 C1 33 V1 61 R10 89 A7 6 C2 34 V2 62 P11 90 A5 7 D1 35 W1 63 P10 91 A9 8 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99 B4 16 H2 44 V5 72 J10 100 B3 17 J1 45 U5 73
11. CY7C1474V33 PERFORM Switching Waveforms Read Write Timing 2 23 24 1 78 4 5 6 7 8 9 10 CIUS Bua B c D ID tCES tCEH eh EA NEA MD EN E E we A 2 BW 2 A D ADDRESS VIKAS BS XX AS X XU 7 Ds DH tco 45 tAH s 2 I DOH tCHZ Data A oan y pia2 WYA Daz Q A3 ba Q A4 1 pias QY ouo In Out toEHZz EN lge _ DEM tOELZ WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D A1 D A2 WRITE Q A3 Q A4 READ D A5 Q A6 D A7 D A2 1 Q A4 H DON T Q UNDEFINED Notes 22 For this waveform ZZ is tied LOW 23 When CE is LOW CE is LOW CE is HIGH and CE is LOW When CE is HIGH CE is HIGH or is LOW or CE is HIGH 24 Order of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Document 38 05289 Rev I Page 21 of 29 Feedback m CY7C1470V33 CY7C1472V33 CYPRESS CY7C1474V33 Switching Waveforms continued NOP STALL and DESELECT Cycles 22 23 25 10 f 7 8
12. DQdr 25 56 L1 DQa Vss o 26 55 L3 Vss Vopor 27 54 O DQdrj 28 53 DQa DQdr 29 52 L3 DGPdr 30 51 E1 DQPa ANOMOTNORDADOrVYNTNOONADAD SO CO CO CO CO CO CO CO sb s sb Sb sb sb SE Sb ob Sb O10 9 3 lt lt lt lt lt lt lt lt lt gt gt NC 288 NC 144 Document 38 05289 Rev I NC NC NC Vppo Vss NC NC DQb DQb Vss Vppo DQb DQb NG Vpp NC Vss DQb DQb Vppo Vss DQb DQb DQPb NC V Vong NC NC NC oo T 2S ong ox f gt u uoo uu w ju ju E 99 2 esas lt lt lt wa ES aa ao SE c OL nan sa as wa a sa S CO LO F QW O O O LO st CO GN O O O O O O O O CO CO 1 80 2 79 3 78 NC 4 77 LH Vppa 5 76 O Vss 6 75 NC 7 74 DQPa 8 73 DQa 9 72 DQa 10 71 H Vss 11 H 12 69 DQa 13 eg O 14 67 H Vss 15 CY7C1472V33 66 i 16 65 DD 17 4M X 18 64 O 22 18 63 DQa 19 62 DQa 20 61 Fl
13. _ Function CY7C1474V33 Read Write No Bytes Written Write Byte X DQ and Write All Bytes WE H L L L All BW L Note 8 Table only lists a partial listing of the Byte Write combinations Any combination of is valid Appropriate Write will be done based on which Byte Write is active Document 38 05289 Rev I Page 10 of 29 Feedback CYPRESS CYPRESS PERFORM IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1470V33 CY7C1472V33 and CY7C1474V33 incorporates a serial boundary scan test access port TAP This port operates in accordance with IEEE Standard 1149 1 1990 but does not have the set of functions required for full 1149 1 compliance These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149 1 fully compliant TAPs The TAP operates using JEDEC standard 3 3V or 2 5V I O logic levels The CY7C1470V33 CY7C1472V33 and CY7C1474V33 contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clo
14. AND a a scope 0 2 5V I O Test Load R 16670 OUTPUT OUTPUT 500 5 pF R 15380 1 25V INCLUDING JIG AND 0 Note 15 Tested initially and after any design or process changes that may affect these parameters Document 38 05289 Rev I Page 19 of 29 Feedback CY7C1470V33 CY7C1472V33 CYPRESS CY7C1474V33 PERFORM Switching Characteristics Over the Operating Range 116 17 250 200 167 Parameter Description Min Max Min Max Min Max Unit tPower 51 Vcc typical to the First Access Read or Write 1 1 1 ms Clock Clock Cycle Time 4 0 5 0 6 0 ns FMAX Maximum Operating Frequency 250 200 167 MHz tcu Clock HIGH 2 0 2 0 2 2 ns teL Clock LOW 2 0 2 0 2 2 ns Output Times tco Data Output Valid After CLK Rise 3 0 3 0 3 4 ns toEv OE LOW to Output Valid 3 0 3 0 3 4 ns Data Output Hold After CLK Rise 1 3 1 3 1 5 ns tcHz Clock to High Z 9 20 21 3 0 3 0 3 4 ns tcLz Clock to Low Z 9 20 21 1 3 1 3 1 5 ns tEOHZ OE HIGH to Output 2119 20 21 3 0 3 0 34 ns tEOLZ OE LOW to Output Low Z 9 20 21 0 0 0 ns Set up Times tas Address Set up Before CLK Rise 1 4 1 4 1 5 ns tps Data Input Set up Before CLK Rise 1 4 1 4 1 5 ns tcENS CEN Set up Before CLK Rise 1 4 1 4 1 5 ns twes WE BW Set up Before C
15. CEN inserts wait states Device will power up deselected and the I Os in a tri state condition regardless of OE n OE is asynchronous and is not sampled with the clock rise It is masked internally during Write cycles During a Read cycle DQ and DQPra tri state when OE is inactive or when the device is deselected and DQ data when OE is active Document 38 05289 Rev I Page 9 of 29 Feedback ae CYPRESS PERFORM j Partial Write Cycle Description 2 3 8 CY7C1470V33 CY7C1472V33 CY7C1474V33 Function CY7C1470V33 Qa Read Write No bytes written Write Byte a DQ and DQP Write Byte b DQ DQP Write Bytes b a Write Byte c DQ and DQP Write Bytes c a Write Bytes c b Write Bytes c b a Write Byte d DQg and DQPy Write Bytes d a Write Bytes d b Write Bytes d b a Write Bytes d c Write Bytes d c a Write Bytes d c b Write All Bytes z zz rz z rx 2 ri rr rir IT T T T lt X f x z z z z z z z x r r r irriimir mi irimrr T r T r T lt Function CY7C1472V33 m Read Write No Bytes Written Write Byte a DQ and DQP Write Byte b DQ and DQP Write Both Bytes Al rr yr yoy m _ 18 w
16. CY7C1470V33 CY7C1472V33 and CY7C1474V33 are equipped with the advanced NoBL logic required to enable consecutive Read Write operations with data being trans ferred on every clock cycle This feature dramatically improves the throughput of data in systems that require frequent Write Read transitions The CY7C1470V33 CY7C1472V33 and CY7C1474V33 are pin compatible and functionally equiv alent to ZBT devices All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock The clock input is qualified by the Clock Enable CEN signal which when deasserted suspends operation and extends the previous clock cycle Write operations are controlled_by the Byte Write Selects BW BW for CY7C1474V33 BW BW for CY7C1470V33 and BW BW for CY7C1472V33 a Write Enable WE input All writes are conducted with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE4 CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri state control In order to avoid bus contention the output drivers are synchronously tri stated during the data portion of a write sequence Logic Block Diagram CY7C1470V33 2M x 36 ADDRESS 1 REGISTER 0 Al MODE c ADV D CEN WRITE ADDRESS REGISTER 1
17. WRITE ADDRESS REGISTER 2 ADV D WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWa BW BW BWa WE CEL 2 READ LOGIC SLEEP rae po BURST Go AO LOGIC MEMORY DQs dud anw DQPa TMnpman amx ACCO 21 PHPO INPUT REGISTER 1 INPUT REGISTER 0 CONTROL Cypress Semiconductor Corporation Document 38 05289 Rev I 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised June 20 2006 Feedback CY7C1470V33 CY7C1472V33 7 CYPRESS CY7C1474V33 PERFORM Logic Block Diagram CY7C1472V33 4M x 18 ADDRESS REGISTER 0 A1 A ADV LD WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV LD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC MEMORY ARRAY WRITE DRIVERS DQs DQPa DQP wroE muzmun wzmancw cvo4co QZz zmmduw PA gt O m uzm u Gm Acv4CO m OE CEl CE2 READ LOGIC Logic Block Diagram CY7C1474V33 1M x 72 AO A1 A ADDRESS REGISTER 0 At fou po BURST LOGIC A MODE ao ADV LD c CEN WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2
18. is not fully compliant to the 1149 1 convention because some of the mandatory 1149 1 instructions are not fully implemented The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I O buffers The SRAM does not implement the 1149 1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE PRELOAD rather it performs a capture of the I O ring when these instructions are executed Document 38 05289 Rev I CY7C1470V33 CY7C1472V33 CY7C1474V33 Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state EXTEST EXTEST is a mandatory 1149 1 instruction which is to be executed whenever the instruction register is loaded with all Os EXTEST is not implemented in this SRAM TAP controller and therefore this device is not compliant to 1149 1 The TAP controller does recognize an all O instruction When an EXTEST instruction is loaded into the instruction register the SRAM responds as if a SAMPLE PRELOAD instruction has been loaded There is one difference between the two instructions Unlike the SAMPLE PRELOAD instruction EXTEST places the SRAM outputs in a High Z state IDCODE The ID
19. 1472V33 250AXC CY7C1470V33 250BZC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1472V33 250BZC CY7C1470V33 250BZXC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Lead Free CY7C1472V33 250BZXC CY7C1474V33 250BGC 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1474V33 250BGXC 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Lead Free CY7C1470V33 250AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1472V33 250AXI CY7C1470V33 250BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1472V33 250BZI CY7C1470V33 250BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Lead Free CY7C1472V33 250BZXI CY7C1474V33 250BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1474V33 250BGXI 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Lead Free Document 38 05289 Rev I Page 24 of 29 Feedback CY7C1470V33 he CY7C1472V33 WEEZCYPRESS 1 CY7Ci474V33 j PERFORM Package Diagrams 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 14 00 0 10 1 40 0 05 100 81 RRRRRRRERRRERRRRRRR c i o 80 0 30 0 08 e I a e e a S N N 0 65 SEE DETAIL A Y 30 51 0 20 MAX 1 60 MAX R 0 08 MIN 0 20 MAX p gt 0 MIN E
20. 3V Input pulse levels sse Vgg to 2 5V Input rise and fall times u a 1ns Input rise and fall time a 1ns Input timing reference 1 5V Input timing reference 1 25V Output reference levels a 1 5V Output reference levels 1 25V Test load termination supply voltage 1 5V Test load termination supply voltage 1 25V 3 3V TAP AC Output Load Equivalent 2 5V TAP AC Output Load Equivalent 15V 1 25V 500 500 TDO TDO Zo 500 20pF Zo 500 20pF TAP DC Electrical Characteristics And Operating Conditions 0 C lt TA lt 70 C Vpp 3 135V to 3 6V unless otherwise noted Parameter Description Test Conditions Min Max Unit Vout Output HIGH Voltage loy 4 0 MA Vppq 3 3V 2 4 V lou 1 0 mA Vppq 2 5V 2 0 V Output HIGH Voltage lop 100 HA Vppo 3 3V 2 9 V Vppo 2 5V 2 1 V Vout Output LOW Voltage loj 8 0 mA Vppo 3 3V 0 4 V lot 1 0mA VDDQ 2 5V 0 4 V Vor Output LOW Voltage Io 100 HA Vppo 3 3V 0 2 V Vppo 2 5V 0 2 V Vin Input HIGH Voltage VDDQ 3 3V 2 0 0 3 V VDDQ 2 5V 1 7 Vpp 4 0 3 V Vy Input LOW Voltage Vppo 3 3V
21. A A TDI A1 TDO A A A NC 288M R MODE A A A TMS TCK A A A A CY7C1472V33 4M x 18 1 2 3 4 5 6 7 8 9 10 11 A NC 576M A CE BW NC CEN ADV LD A A A B NC 1G 2 BW CLK WE OE A A NC C NC NC Vss Vss Vss Vss Vss VDDQ NC D NC DQ Vpp Vss Vss Vss Vpp VDDQ NC DQa E NC DQ Vppo Vpp Vss Vss Vss Vpp Vppo NC DQ F NC DQp Vpp Vss Vss Vss Vpp Vppo NC DQ G NC DQ VDD Vss Vss Vss Vpp Vppo NC DQ H NC NC NC Vss Vss Vss 77 J DQ NC VDDQ Vpp Vss Vss Vss Vpp DQ NC K DQ NC Vppo Vpp Vss Vss Vss Vpp Vppo DQ NC L DQy NC VDDQ Vpp Vss Vss Vss Vpp DQ NC M DQp NC VDDQ Vpp Vss Vss Vss Vpp DQ NC N pap NC Vbo Ves NC NC NC Vas Vppo NC NC P NC 144M A A A TDI A1 TDO A A A NC 288M R MODE A A A TMS TCK A A A A Document 38 05289 Rev I Page 4 of 29 Feedback CY7C1470V33 CY7C1472V33 CYPRESS CY7C1474V33 PERFORM Pin Configurations continued 209 ball FBGA 14 x 22 x 1 76 mm Pinout CY7C1474V33 1M x 72 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A CE A ADV LD A DQb B DQg DQg BWS BWS NG WE A BWS BWS DQb DQb C BWS BWS NC 576M CE NC BWS BWS DQb DQb D DQg DQg Vss NC NCAG OE NC NC Vss DQb DQb E DaPg DOPc Vp
22. CODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state It also places all SRAM outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction The PRELOAD portion of this instruction is not implemented so the device TAP controller is not fully 1149 1 compliant When the SAMPLE PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This wil
23. H11 101 C3 18 J2 46 U6 74 H10 102 C4 19 L1 47 W7 75 G11 103 C8 20 L2 48 V7 76 G10 104 C9 21 M1 49 U7 77 F11 105 B9 22 M2 50 V8 78 F10 106 B8 23 N1 51 V9 79 E10 107 A4 24 N2 52 W11 80 E11 108 C6 25 P1 53 W10 81 D11 109 B7 26 P2 54 V11 82 D10 110 A3 27 R2 55 V10 83 C11 28 R1 56 U11 84 C10 Document 38 05289 Rev I Page 17 of 29 Feedback CY7C1470V33 CY7C1472V33 Z CYPRESS CY7C1474V33 PERFORM Maximum Ratings Current into Outputs LOW 20 mA Above which the useful life may be impaired For user guide MODUS SOMME EPUM lines not tested Storage aa _65 C to 150 Latch up Current n sn aaa gt 200 mA Ambient Temperature with Operating Range Power 55 C to 125 Ambient Supply Voltage on Vpp Relative to GND 0 5V to 4 6V Range Temperature Vpp Vppo Supply Voltage on Vppq Relative to GND 0 5V to Vpp Commercial 0 C to 70 C 3 3V 2 5V 5 DC to Outputs in 0 5V to Vppg 0 5V Industrial 40 Cto 85 C S 10 to Vpp DC Input 0 5V to Vpp 0 5V Electrical Characteristic
24. HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see the TAP Controller State Diagram TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB of any register See Tap Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register See Tap Controller State Diagram TAP Controller Block Diagram y Bypass Register 2 1 0 Selection e Instruction Register Circuitry Selection 33029 2 1 0 Circuitry Identification Register beL eh Boundary Scan Register Ciri TDI TDO o TMS TAP CONTROLLER Performing a TAP Reset A RESET is performed by forcing TMS HIGH Vpp for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At p
25. LK Rise 1 4 1 4 1 5 ns tats ADV LD Set up Before CLK Rise 1 4 1 4 1 5 ns tcEs Chip Select Set up 1 4 1 4 1 5 ns Hold Times Address Hold After CLK Rise 0 4 0 4 0 5 ns toy Data Input Hold After CLK Rise 0 4 0 4 0 5 ns tcENH CEN Hold After CLK Rise 0 4 0 4 0 5 ns twEH WE BW Hold After CLK Rise 0 4 0 4 0 5 ns tALH ADV LD Hold after CLK Rise 0 4 0 4 0 5 ns icEH Chip Select Hold After CLK Rise 0 4 0 4 0 5 ns Notes 16 Timing reference is 1 5V when Vppq 3 3V and is 1 25V when 2 5V 17 Test conditions shown in a of AC Test Loads unless otherwise noted 18 This part has a voltage regulator internally tpower is the time power needs to be supplied above Vpp minimum initially before a Read or Write operation can be initiated 19 toyz tcLz teoLz and tgopz are specified with AC test conditions shown in b of AC Test Loads Transition is measured 200 mV from steady state voltage 20 At any given voltage and temperature t orz is less than tgo and is less than tc to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 21 This parameter is sampled and not 100 tested Document 38 05289 Rev I Page 20 of 29 Feedback m CY7C1470V33 CY7C1472V33 amp CYPRESS _ _ _ _
26. Orig of REV No Issue Date Change Description of Change H 416221 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Changed Three state to Tri state Changed the description of lx from Input Load Current to Input Leakage Current on page 18 Changed the current values of MODE on page 18 from 5 pA and 30 pA to 30 pA and 5 uA Changed the ly current values of ZZ on page 18 from 30 uA and 5 pA to 5 pA and 30 uA Changed VDDQ lt VDD to Vppa lt Vpp in page 18 Replaced Package Name column with Package Diagram in the Ordering Information table Updated the Ordering Information Table 7 472335 See ECN VKN Corrected the typo in the pin configuration for 209 Ball FBGA pinout Corrected the ball name for H9 to Vss from Vggq Added the Maximum Rating for Supply Voltage on Vppo Relative to GND Changed try tr from 25 ns to 20 ns and trpoy from 5 ns to 10 ns TAP AC Switching Characteristics table Updated the Ordering Information table Document 38 05289 Rev I Page 29 of 29 Feedback
27. PASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan register is loaded with the contents of the RAM I O ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I O ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the ldentification Register Definitions table TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are listed in the Instruction Codes table Three of these instructions are listed as RESERVED and should not be used The other five instruc tions are described in detail below The TAP controller used in this SRAM
28. ch Ball Grid Array 15 x 17 x 1 4mm Lead Free CY7C1472V33 167BZXI CY7C1474V33 167BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1474V33 167BGXI 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Lead Free 200 CY7C1470V33 200AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1472V33 200AXC CY7C1470V33 200BZC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4mm CY7C1472V33 200BZC CY7C1470V33 200BZXC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4mm Lead Free CY7C1472V33 200BZXC CY7C1474V33 200BGC 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1474V33 200BGXC 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Lead Free CY7C1470V33 200AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial Document 38 05289 Rev I Page 23 of 29 Feedback Z CYPRESS PERFORM Ordering Information continued CY7C1470V33 CY7C1472V33 CY7C1474V33 Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Part and Package Type Range 250 CY7C1470V33 250AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C
29. cking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO should be left unconnected Upon power up the device will come up in a reset state which will not interfere with the operation of the device TAP Controller State Diagram TEST LOGIC RESET 0 Ld 1 RUN TEST i SELECT 1 SELECT 1 IDLE i DR SCAN IR SCAN 0 0 1 1 CAPTURE DR CAPTURE IR 0 0 Y Y SHIFDR 0 SHIFT IR D 202 1 1 1 1 EXITL DR EXITLIR 0 0 T PAUSEDR 05 PAUSE IR D 0D 1 1 0 0 EXIT2 DR EXIT2 IR 1 1 Y Y UPDATEDR UPDATER 1 0 1 0 Y The 0 1 next to each state represents the value of TMS at the rising edge of TCK Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Document 38 05289 Rev I CY7C1470V33 CY7C1472V33 CY7C1474V33 Test MODE SELECT TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this ball unconnected if the TAP is not used The ball is pulled up internally resulting in a logic
30. e reduced to simple Byte Write operations Because the CY7C1470V33 CY7C1472V33 and CY7C1474V33 common I O devices data should not be driven into the device while the outputs are active The Output Enable OE can be deasserted HIGH before presenting data to the DQ and DQP DQ b c d e f p DQPabcdef h for CY7C1474V33 DQ bc g DOP4 p 5 for CY7C1470V38 and DQ y DQP b for 47233 inputs Doing so will tri state the output drivers As a safety precaution DQ and DOP DQa bc d e tg h DOP abcde for CY7C1474V33 CY7C1470V33 CY7C1472V33 CY7C1474V33 CY7C1474V33 BWabcg for CY7C1470V33 and BW for CY7C1472V33 inputs must be driven in each cycle of the burst write in order to write the correct bytes of data Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE and must remain inactive for the duration of tzzngc after the ZZ input returns LOW Interleaved Burst Address Table MODE Floating or Vpp First Second Third Fourth Address Address Address Address A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 01 00 11 10 10 11 00 01
31. ed grades 135 mA Power down Vin gt Vj or Vin lt Vj f 0 Current TTL Inputs Notes 13 Overshoot VIH AC lt Vpp 1 5V Pulse width less than tcyc 2 undershoot Vy AC gt 2 14 Tpower up Assumes a linear ramp from OV to Vpp min within 200 ms During this time V Document 38 05289 Rev I V Pulse width less than 1 2 lt and lt Page 18 of 29 Feedback Jj a eed 7 CYPRESS PERF ORM Capacitance CY7C1470V33 CY7C1472V33 CY7C1474V33 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Max Max Max Unit CADDRESS Address Input Capacitance TA 25 C f 1 MHz 6 6 6 pF CDATA Data Input Capacitance M DD 5 5 5 pF CcTRL Control Input Capacitance s es 8 8 8 pF Clock Input Capacitance 6 6 6 pF Cio Input Output Capacitance 5 5 5 pF Thermal Resistance 100 TQFP 165 FBGA 209 FBGA Parameters Description Test Conditions Package Package Package Unit OJA Thermal Resistance Test conditions follow standard 24 63 16 3 15 2 C W Junction to Ambient test methods and procedures for ing thermal impedance o Thermal Resistance measuring 2 28 2 1 1 7 C W Junction to Case per EIA JESD51 AC Test Loads and Waveforms 3 3V I O Test Load R 3170 uU 3 3V ALL INPUT PULSES OUTPUT 500 5 pF 3510 1 5V INCLUDING JIG
32. ged ball C11 D11 E11 F11 G11 from DQPb DQb DQb DQb DQb to DQPa DQa DQa DQa DQa in page 4 Modified capacitance values in page 20 299511 SYT Removed 225 MHz offering and included 250 MHz speed bin Changed from 4 4 ns to 4 0 ns for 250 MHz Speed Bin Changed from 16 8 to 24 63 C W and from 3 3 to 2 28 C W for 100 TQFP Package on Page 20 Added lead free information for 100 Pin TQFP and 165 FBGA Packages Added comment of Lead free BG packages availability below the Ordering Information VBL Add Industrial part numbers in Ordering Info section F 323039 See ECN PCI Unshaded 250 MHz speed bin in the AC DC Table and Selection Guide Address expansion pins balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Modified VoL Vou Test Conditions Changed package name from 209 ball PBGA to 209 ball FBGA on 5 Removed comment of Lead free BG packages availability below the Ordering Information Updated Ordering Information Table Changed from Preliminary to Final G 351937 See ECN PCI Updated Ordering Information Table Document 38 05289 Rev I Page 28 of 29 Feedback CY7C1470V33 CY7C1472V33 CYPRESS C147 4033 PERFORM i i Document Title CY7C1470V33 CY7C1472V33 CY7C1474V33 72 Mbit 2M x 36 4M x 18 1M x 72 Pipelined SRAM with NoBL Architecture Document Number 38 05289
33. i stated regardless of the state of the OE input signal This allows the external logic to present the data on DQ and DQP Oac e a DOPa b c d e f for CY7C1474V33 Qo ea DG b c a for CV7CTA70V33 and DQ DQP p for cB iov In addition the address for the subsequent access Read Write Deselect is latched into the Address Register provided the appropriate control signals are asserted Page 7 of 29 Feedback 74 CYPRESS PERFORM On the next clock rise the data presented to DQ and DQP DQa bc de tgh DOPab cdetg for CY7C1474V33 DQ 299806 og for CYIE1470V33 amp DQ DQP s for CY7C1472V33 or a subset for byte write operations see Write Cycle Description table for details inputs is latched into the device and the write is complete The data written during the Write operation is controlled by BW BW y for CY7C1474V33 BW 5 bod for CY761470V33 and BW p for CY7C1472V33 signals The CY7C1470V33 CY7C1472V33 and CY7C1474V33 provides Byte Write capability that is described in the Write Cycle Description table Asserting the Write Enable input WE with the selected Byte Write Select BW input will selectively write to only the desired bytes Bytes not selected during a Byte Write operation will remain unaltered synchronous self timed Write mechanism has been provided to simplify the Write operations Byte Write capability has been included in order to greatly simplify Read Modify Write sequences which can b
34. ies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback y es JN m SS CYPRESS PERFORM Document History Page CY7C1470V33 CY7C1472V33 CY7C1474V33 Document Title CY7C1470V33 CY7C1472V33 CY7C1474V33 72 Mbit 2M x 36 4M x 18 1M x 72 Pipelined SRAM with NoBL Architecture Document Number 38 05289 Orig of REV ECN No Issue Date Change Description of Change P 114676 08 06 02 PKS New Data Sheet A 121520 01 27 03 CJM Updated features for package offering Removed 300 MHz offering Changed tCO tEOV tCHZ tEOHZ from 2 4 ns to 2 6 ns 250 MHz tDOH tCLZ from 0 8 ns to 1 0 ns 250 MHz tDOH tCLZ from 1 0 ns to 1 3 ns 200 MHz Updated ordering information Changed Advanced Information to Preliminary B 223721 See ECN NJY Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified Functional Overview section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Included IDD and ISB values Removed 250 MHz offering and included 225 MHz speed bin Changed package outline for 165FBGA package and 209 ball BGA package Removed 119 BGA package offering C 235012 See ECN RYQ Minor Change The data sheets do not match on the spec system and external web D 243572 See ECN NJY Chan
35. l not harm the device but there is no guarantee as to the value that will be captured Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture set up plus hold time tcs plus tcp The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still Page 12 of 29 Feedback a 4 7 CYPRESS i PERFORM possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO balls Note that since the PRELOAD part of the command is not implemented putting the TAP to the Update DR state while performing a SAMPLE PRELOAD instruction will have the same effect as the Pause DR command TAP Timing Test Clock TCK CY7C1470V33 CY7C1472V33 CY7C1474V33 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO balls The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are con
36. ll Writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE CE3 and an asynchronous Output Enable OE simplify depth expansion All operations Reads Writes and Deselects are pipelined ADV LD should be driven LOW once the device has been deselected in order to load a new address for the next operation Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 and CE are ALL asserted active 3 the Write Enable input signal WE is deasserted HIGH and 4 ADV LD is asserted LOW The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3 0 ns Document 38 05289 Rev I 250 MHz device provided OE is active LOW After the first clock of the Read access the output buffers are controlled by OE and the internal control logic OE must be driven LOW in order for the device to drive out the requested data During the second clock a subsequent operation Read Write Deselect can be initiated Deselecting the device is also pipelined The
37. ll be used for expansion to the 144M 288M 576M 288M 1G densities 576M 1G ZZ Input ZZ sleep Input This active HIGH input places the device in non time critical sleep condition Asynchronous with data integrity preserved During normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down Functional Overview The CY7C1470V33 CY7C1472V33 and CY7C1474V33 are synchronous pipelined Burst NoBL SRAMs designed specifi Cally to eliminate wait states during Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock signal is qualified with the Clock Enable input signal CEN If CEN is HIGH the clock signal is not recognized and all internal states are maintained All synchronous operations are qualified with CEN All data outputs pass through output registers controlled by the rising edge of the clock Maximum access delay from the clock rise tco is 3 0 ns 250 MHz device Accesses can be initiated by asserting all three Chip Enables CE CEs CE3 active at the rising edge of the clock If Clock Enable CEN is active LOW and ADV LD is asserted LOW the address presented to the device will be latched The access can either be a Read or Write operation depending on the status of the Write Enable WE BW can be used to conduct Byte Write operations Write operations are qualified by the Write Enable WE A
38. nected together on a board Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Test Mode Select TMS Test Data In TDI trpov DOX Test Data Out TDO QC 9C 9C OC DON T UNDEFINED AC Switching Characteristics Over the Operating Rangel 10 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns 1 TCK Clock Frequency 20 MHz tty TCK Clock HIGH time 20 ns tr TCK Clock LOW time 20 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns ttpox TCK Clock LOW to TDO Invalid 0 ns Set up Times truss TMS Set up to TCK Clock Rise 5 ns trois TDI Set up to TCK Clock Rise 5 ns lcs Capture Set up to TCK Rise 5 ns Hold Times trusH TMS Hold after TCK Clock Rise 5 ns TDIH TDI Hold after Clock Rise 5 ns icu Capture Hold after Clock Rise 5 ns Notes 9 tcs and toy refer to the set up and hold time requirements of latching data from the boundary scan register 10 Test conditions are specified using the load in AC Test Conditions tp tp 1 ns Document 38 05289 Rev I Page 13 of 29 Feedback 3 3V AC Test Conditions CY7C1470V33 CY7C1472V33 CY7C1474V33 2 5V TAP AC Test Conditions Input pulse levels Vgg to 3
39. ontrols DQ and BW controls DQ and DQP BW BW controls DQ DQP BW controls DQg and DQP BW controls DQ and BW BWg controls DQ and BW controls DQ DQPg BW controls DQ and DQP BW BW BW BW WE Input Write Enable Input active LOW Sampled on the rising edge of CLK if CEN is active LOW This Synchronous signal must be asserted LOW to initiate a write sequence ADV LD Input Advance Load Input used to advance the on chip address counter or load a new address Synchronous When HIGH and CEN is asserted LOW the internal burst counter is advanced When LOW new address can be loaded into the device for an access After being deselected ADV LD should be driven LOW in order to load a new address CLK Input Clock Input Used to capture all synchronous inputs to the device CLK is qualified with CEN Clock CLK is only recognized if CEN is active LOW Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CEs to select deselect the device CE3 Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous and to select deselect the device OE Input Output Enable active LOW Combined with the synchron
40. ous logic block inside the device to Asynchronous control the direction of the I O pins When LOW the I O pins are allowed to behave as outputs When deasserted HIGH I O pins are tri stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device has been deselected CEN Input Clock Enable Input active LOW When asserted LOW the clock signal is recognized by the Synchronous SRAM When deasserted HIGH the clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required Bidirectional Data I O lines As inputs they feed into an on chip data register that is triggered Synchronous by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by during the previous clock rise of the read cycle The direction of the pins is controlled by OE and the internal control logic When OE is asserted LOW the pins can behave as outputs When HIGH DQ4 DQy are placed in a tri state condition The outputs are automat ically tri stated during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE DQPy I O Bidirectional Data Parity I O lines Functionally these signals are identical to DQx During write Synchronous
41. ower up the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Page 11 of 29 Feedback Z CYPRESS CYPRESS PERFORM Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BY
42. po Vpp Voo Voo DQPf DaPb F DQc Vss Vss Vss NC Vss Vss Vss Daf Daf G DQc Vpp NC Voo Vppo Daf Daf H DQc Vss Vss Vss NC Vss Vss Vss por J DQc DQc Vppq Vppa NC Vppa Daf K NC NC CLK NC Vss CEN Vss L DQh DQh NC Voo Vppa DQa M DQh DQh Vss Vss Vss NC Vss Vss Vss DQa DQa N NC Yooa Daa DQa P DQh DQh Vss Vss Vss ZZ Vss Vss Vss DQa DQa R DQPd DQPh Vpp Vpp DQPa T DQd Vss NC NC MODE NC NC Vss U DQd NC i44M A A A NC 288M DQe V DQd DQd A1 A A Dae w DQd DQd TMS TDI AO TDO TCK pae Document 38 05289 Rev I Page 5 of 29 Feedback nh i vas 7 CYPRESS PERFORM Pin Definitions CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Name Type Pin Description Input Address Inputs used to select one of the address locations Sampled at the rising edge of Al Synchronous the CLK A BW Input Byte Write Select Inputs active LOW Qualified with WE to conduct writes to the SRAM BW Synchronous Sampled on the rising edge of CLK BW c
43. presentative or visit www cypress com for actual products offered CY7C1472V33 200AXI CY7C1470V33 200BZI CY7C1472N33 200BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4mm CY7C1470V33 200BZXI CY7C1472N33 200BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4mm Lead Free CY7C1474V33 200BGI CY7C1474V33 200BGXI 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Lead Free Speed Package Operating MHz Ordering Code Diagram Part and Package Type Range 167 CY7C1470V33 167AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1472V33 167AXC CY7C1470V33 167BZC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4mm CY7C1472V33 167BZC CY7C1470V33 167BZXC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4mm Lead Free CY7C1472V33 167BZXC CY7C1474V33 167BGC 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1474V33 167BGXC 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Lead Free CY7C1470V33 167AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1472V33 167AXI CY7C1470V33 167BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4mm CY7C1472V33 167BZI CY7C1470V33 167BZXI 51 85165 165 ball Fine Pit
44. refore when the SRAM is deselected at clock rise by one of the chip enable signals its output will tri state following the next clock rise Burst Read Accesses The CY7C1470V33 CY7C1472V33 and CY7C1474V33 have an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must be driven LOW in order to load a new address into the SRAM as described in the Single Read Access section above The sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an interleaved burst sequence Both burst counters use AO and A1 in the burst sequence and will wrap around when incremented sufficiently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of chip enables inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or Write is maintained throughout the burst sequence Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 CE and CE are ALL asserted active and 3 the Write signal WE is asserted LOW The address presented to the address inputs is loaded into the Address Register The write signals are latched into the Control Logic block On the subsequent clock rise the data lines are automatically tr
45. ruth Table 2 3 4 5 6 7 CY7C1470V33 CY7C1472V33 CY7C1474V33 Operation Address Used CE ZZ ADV LD WE BW OE CEN CLK DQ Deselect Cycle None H L X X X L L H Tri State Continue None X H X X X L L H Tri State Deselect Cycle Read Cycle External L L L H X L L L H Data Out Q Begin Burst Read Cycle Next X L H X X L L L H Data Out Q Continue Burst NOP Dummy Read External L L L H X H L L H Tri State Begin Burst Dummy Read Next X L H X X H L L H Tri State Continue Burst Write Cycle External L L L L L X L L H Data In D Begin Burst Write Cycle Next X L H X L X L L H Data In D Continue Burst NOP Write Abort None L L L L H X L L H Tri State Begin Burst Write Abort Next X L H X H X L L H Tri State Continue Burst Ignore Clock Edge Current X L X X X X H L H Stall Sleep Mode None X H X X X X X X Tri State Notes 1 X Don t Care H Logic HIGH L Logic LOW CE stands for ALL Chip Enables active BWx 0 signifies at least one Byte Write Select is active BWx Valid signifies that the desired byte write selects are asserted see Write Cycle Description table for details NOORWD Write is defined by WE and BW 4 See Write Cycle Description table for details When a Write cycle is detected all I Os are tri stated even during Byte Writes The DQ and pins are controlled by the current cycle and the OE signal
46. s Over the Operating Rangel 14 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ I O Supply Voltage for 3 3V I O 3 135 Vpp V for 2 5V I O 2 375 2 625 V Output HIGH Voltage for 3 3V I O 4 0 mA 2 4 V for 2 5V I O 1 0 mA 2 0 V VoL Output LOW Voltage for 3 3V I O loj 8 0 mA 0 4 V for 2 5V I O 1 0 mA 0 4 V Vin Input HIGH Voltagel 3 for 3 3V 2 0 Vpp 0 3V V for 2 5V 1 7 Vpp 0 3V V Vi Input LOW Voltage 3 3 3V 0 3 0 8 V for 2 5V 0 3 0 7 V lx Input Leakage Current GND lt x Vppo 5 5 uA except ZZ and MODE Input Current of MODE Input Vss 30 uA Input Vpp 5 uA Input Current of ZZ Input Vss 5 uA Input Vpp 30 loz Output Leakage Current GND x V lt Vppq Output Disabled 5 5 uA Ipp Vpp Operating Supply Vpp Max lour 0 mA 4 0 ns cycle 250 MHz 500 mA f fmax 1 lcyc 5 0 ns cycle 200 MHz 500 mA 6 0 ns cycle 167 MHz 450 mA Automatic Max Vpp Device Deselected 4 0 ns cycle 250 MHz 245 mA 6 0 ns cycle 167 MHz 245 mA Automatic Vpp Device Deselected All speed grades 120 mA Power down Vin 0 3V or Vin gt Vppo 0 3V Current CMOS Inputs f 0 Automatic CE Max Vpp Device Deselected 4 0 ns cycle 250 MHz 245 mA Cure Inputs i Nye ene POS 200 Me 6 0 ns cycle 167 MHz 245 mA Automatic Vpp Device Deselected All spe
47. s the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures I O ring contents Places the boundary scan register between TDI Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures I O ring contents Places the boundary scan register between TDI Does not affect SRAM operation This instruction does not implement 1149 1 preload function and is therefore not 1149 1 compliant RESERVED 101 Do Not Use This instruction is reserved for future use Note 12 Bit 424 is 1 in the ID Register Definitions for both 2 5V and 3 3V versions of this device Document 38 05289 Rev I Page 15 of 29 Feedback CY7C1470V33 CY7C1472V33 F CYPRESS CY7C1474V33 PERFORM _ Boundary Scan Exit Order 2M x 36 Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID 1 1 21 R3 41 J11 61 B7 2 D1 22 P2 42 K10 62 B6 3 E1 23 R4 43 J10 63 A6 4 D2 24 P6 44 H11 64 B5 5 E2 25 R6 45 G11 65 A5 6 F1 26 R8 46 F11 66 A4 7 G1 27 P3 47 E11 67 B4 8 F2 28 P4 48 D10 68 B3 9 G2 29 P8 49 D11 69 A3 10 Ji 30 P9 50 C11 70 A2 n Ki Pro
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