Cypress MoBL CY62128E User's Manual
Contents
1. 1 PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2004 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in li2. M NJ CYPRESS Features m Very high speed 45 ns m Temperature ranges Industrial 40 C to 85 C Automotive A 40 C to 85 C Automotive E 40 to 125 C Voltage range 4 5V to 5 5V m Pin compatible with CY62128B m Ultra low standby power Typical standby current 1 pA Maximum standby current 4 uA Industrial m Ultra low active power Typical active current 1 3 mA at f 1 MHz m Easy memory expansion with CE4 and OE features m Automatic power down when deselected m CMOS for optimum speed and power m Offered in standard Pb free 32 pin STSOP 32 pin SOIC and 32 pin TSOP packages MoBL CY62128E 1 Mbit 128K x 8 Static RAM Functional Description CY62128El is a high performance CMOS static RAM organized as 128K words by 8 bits This device features advanced circuit design to provide ultra low active current This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling Placing the device into standby mode reduces power consumption by more than 99 percent when deselected CE HIGH or CE LOW The eight input and output pins IOo through IO are placed in a high impedance state when the device is deselected CE HIGH or CE LOW the outputs_are disabled OE HIGH write operat
3. 0 5V Electrical Characteristics Over the Operating Range i m 45 ns Ind l Auto A 55 ns Auto E 3 Parameter Description Test Conditions 3 3 Unit Min Typ 1 Output HIGH 1 mA 24 24 V Voltage VoL Output LOW lo 2 1 mA 0 4 0 4 V Voltage Input HIGH Voltage Vcc 4 5V to 5 5V 2 2 0 5 22 0 5 V Vi Input LOW voltage Vcc 4 5V to 5 5V 0 5 0 8 0 5 0 8 V lix Input Leakage GND lt V lt Vee 1 1 4 4 Current loz Output Leakage GND lt Vo x Vcc Output Disabled 1 1 4 4 uA Current lec Vcc Operating f fax titre Vcc 11 16 11 35 Supply Current m lout 0 mA f 1 MHz CMOS levels 1 3 1 3 4 legal Automatic CE CE gt Vcc 0 2V or CE lt 0 2V 1 4 1 30 uA Power down Vin gt Voc 0 2V or Vin lt 0 2V Current CMOS f 0 Vcc Vcc max Inputs Capacitance For all Packages 91 Parameter Description Test Conditions Max Unit Input Capacitance TA 25 C f 1 MHz 10 pF Cour Output Capacitance Voc Vcc yp 10 pF Notes 5 Vit min 2 0V for pulse durations less than 20 ns Voc 0 75V for pulse durations less than 20 ns 7 Full device AC operation assumes a 100 us ramp time from 0 to Vcc min and 200 us wait time after stabilization 8 Only chip enables CE CE2 must be at CMOS level to meet the 5 2 spec Other inputs can be left floating 9 Tested initially and a
4. V CE3 Vi 17 WE is HIGH for read cycle m 18 Address valid before or similar to CE transition LOW and CE transition HIGH 19 Data IO is high impedance if OE Vj 20 If CE goes HIGH or goes LOW simultaneously with WE HIGH the output remains in high impedance state 21 During this period the IOs are in output state and input signals must not be applied Page 6 of 12 Document 38 05485 Rev F Feedback mE CYPRESS MoBL 62128 PERFORM Switching Waveforms continued Figure 4 Write Cycle No 2 or CE2 Controlled 17 15 19 20 twc tsA taw tHA tpwE NN E QAR tsp Figure 5 Write Cycle No 3 WE Controlled OE LOW 11 201 twc N NN n E taw tHA tsA tpwE WE N NN LX gt XX ea XX gt paravano 0 22 luzwE tLZwe Truth Table CE CE WE OE Inputs Outputs Mode Power H X X X High Z Deselect Power down Standby Isp X L X X High Z Deselect Power down Standby Isp L H H L Data Out Read Active lec L H L X Data In Write Active lcc L H H H High Z Selected Outputs Disabled Active lcc Document 38 05485 Rev F Page 7 of 12 Feedback MoBL 62128 PERFORM Ordering Information yen Ordering Code 45 CY62128ELL 45SXI 51 85081 32 450 Mil SOIC Pb free Industrial CY62128ELL 45ZAXI 51 85094 32 S
5. ns in footnote 11 Changed max of 2 and Iccpr from 1 0 uA to 1 5 uA B 461631 See ECN Converted from Preliminary to Final Included Automotive Range and 55 ns speed bin Removed 35 ns speed bin Removed L version of CY62128E Removed Reverse TSOP I package from Product offering Changed lec Typ from 8 mA to 11 mA and lec max from 12 mA to 16 mA for f max Changed lcc max from 1 5 mA to 2 0 mA for f 1 MHz Removed 15 DC Specs from Electrical characteristics table Changed Isg2 max from 1 5 uA to 4 pA Changed Isp from 0 5 pA to 1 pA Changed max from 1 5 pA to 4 pA Changed the AC Test load Capacitance value from 100 pF to 30 pF Changed t zog from 3 to 5 ns Changed t from 6 to 10 ns Changed from 22 to 18 ns Changed tpwe_ from 30 to 35 ns Changed tsp from 22 to 25 ns Changed t zug from 6 to 10 ns Updated the Ordering Information Table C 464721 See ECN Updated the Block Diagram on page 1 D 563144 See ECN AJU Added footnote 4 on page 2 E 1024520 See ECN Added Automotive A information Converted Automotive E specs to final Added footnote 9 related to lag Iccpr Updated Ordering Information table F 2548575 08 05 08 NXR Corrected typo error in Ordering Information table Document 38 05485 Rev F Page 11 of 12 Feedback CYPRESS MoBL 62128
6. py TA 25 2 NC pins are not connected on the die 3 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Voc Vcc 4 When used with a 100 pF capacitive load and resistive loads as shown on page 4 access times of 55 ns taa tace and 25 ns tpog are guaranteed Document 38 05485 Rev F Page 2 of 12 Feedback PERFORM MoBL 62128 Maximum Ratings Output Current into Outputs LOW 20 mA Static Discharge Voltage gt 2001V Exceeding maximum ratings may impair the useful life of the MIL STD 883 Method 3015 device These user guidelines are not tested i Latch up Current aa 200 mA Storage Temperature 65 C to 150 C Ambient Temperature with Operating Range Power Applied eese 55 C to 125 C Supply Voltage to Ground Device Range Tempe tin Potential u u u u uuu 0 5V to 6 0V 0 5V CY62128ELL Ind l Auto A 40 C to 85 4 5 to 5 5V DC Voltage air to Outputs _ in High Z State 81 0 5V to 6 0V Vcc max 0 5V Auto E 40 C to 125 C DC Input Voltage 1 0 5 to 6 0V Vcc max
7. TSOP Pb free CY62128ELL 45ZXI 51 85056 32 TSOP Type I Pb free 45 CY62128ELL 45SXA 51 85081 32 450 Mil SOIC Pb free Automotive A CY62128ELL 45ZXA 51 85056 32 pin TSOP Type Pb free 51 85081 32 450 Mil SOIC Pb free Automotive E 55 CY62128ELL 55SXE CY62128ELL 55ZAXE 51 85094 Contact your local Cypress sales representative for availability of these parts 32 pin STSOP Pb free Package Diagrams Figure 6 32 pin 450 Mil Molded SOIC 51 85081 AARRAARARAARAARE 7 0548413868 0 566 14 376 0 440 11 176 0 450 1 1 430 es ee H 7 32 0 793 20 142 0 817 20 751 0 006 0 152 0 012 0 304 N 01010 55 a 011829971 m MAX Fn L L1 J L rj 000401021 0047 13 L 0004010 a G63 1 62 0 A j 0063 1 600 00140355 0 020 0 508 SEATINGPLANE Page 8 of 12 Document 38 05485 Rev F Feedback CYPRESS PERFORM MoBL 62128 Figure 7 32 pin Shrunk Thin Small Outline Package 8 x 13 4 mm 51 85094 DIMENSIDN IN MM SEATING PLANE 13 20 MIN 13 60 MAX 1 70 Vise 11 90 0 50 ID 017 023 0 21 0 95 SEATING PLANE MAX 105 y f St L 11 CX 010MM 04 57 0 25 0 675 MIN GAUGE PLANE 0 30 0 70 7 Document 38 05485 Re
8. eters other than tri state parameters assume signal transition time of 3ns 1V ns or less timing reference levels of 1 5V input pulse levels of 0 to 3V and output loading of the specified lo as shown in the on page 4 13 At any given temperature and voltage condition is less than tj is less than tj zog and tyzwe_ is less than tj for any given device 14 tuzog tyzce and tyzwe transitions are measured when the outputs enter a high impedance state 15 The internal Write time of the memory is defined by the overlap of WE CE Vi All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE The data input setup and hold timing must be referenced to the edge of the signal that terminates the write Document 38 05485 Rev F Page 5 of 12 Feedback MoBL 62128 PERFORM Switching Waveforms 16 17 Figure 1 Read Cycle 1 Address Transition Controlled tRC ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Figure 2 Read Cycle No 2 OE Controlled 11 17 18 ADDRESS CE OE O tLZ0E HIGH HIGH IMPEDANCE 1 7772 IMPEDANCE Vcc loc SUPPLY CURRENT Isp Figure 3 Write Cycle No 1 WE Controlled 117 15 19 20 two NI NN Z BE NA NN ZA taw tHa tsa iPwE WE WX Qs E tup DATA IO lt norz DATA VALID tHZ0E Notes 16 The device is continuously selected OE CE4
9. fe support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical compone
10. fter any design or process changes that may affect these parameters Page 3 of 12 Document 38 05485 Rev F Feedback MoBL 62128 PERFORM Thermal Resistance SOIC STSOP TSOP Parameter Description Test Conditions Package Package Package Unit Thermal Resistance Still Air soldered on a 3 x 4 5 inch 48 67 32 56 33 01 C W Junction to Ambient two layer printed circuit board Ojc Thermal Resistance 25 86 3 59 3 42 C W Junction to Case AC Test Loads and Waveform R1 Vcc ALL INPUT PULSES OUTPUT 30 pF R2 GND 1 Rise Time 1 V ns Fall Time 1 V ns INCLUDING 7 JIG AND Equivalent to THEVENIN EQUIVALENT OUTPUT o wo Parameters Value Unit R1 1800 R2 990 639 Viu 1 77 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ Max Unit VDR Vcc for Data Retention 2 V 9 Data Retention Current Vcc Vpg CE1 gt Vcc 0 2V or CE2 lt 0 2 Ind l Auto A 4 pA VIN gt Vcc 0 2V or VIN lt 0 2V Auto E 30 uA tcpR 9 Chip Deselect to Data 0 ns Retention Time tr 10 Operation Recovery tac ns Time Data Retention Waveform 1 DATA RETENTION MODE gt 2 0V Vocc min tR Notes 10 Full device AC operation requires linear Vcc ramp fro
11. ion is in progress CE LOW and HIGH and WE LOW To write to the device take Chip Enable CE LOW and CE HIGH and Write Enable WE inputs LOW Data on the eight IO pins IOo through 107 is then written into the location specified on the address pins Ag through A46 To read from the device take Chip Enable CE LOW and CE HIGH and Output Enable OE LOW while forcing Write Enable WE HIGH Under these conditions the contents of the memory location specified by the address pins appear on the IO pins Logic Block Diagram SUUS E Note 1 For best practice recommendations refer to the Cypress application note System Design Guidelines at http www cypress com Cypress Semiconductor Corporation Document 38 05485 Rev F 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised August 4 2008 Feedback MoBL 62128 PERFORM Pin Configuration 32 Pin SOIC Top View TSOPI Top View not to scale 1 2 3 4 5 6 8 STSOP Top View not to scale Product Portfolio Power Dissipation Product Ran Sese i ge Vcc Range V ns Operating mA Standby 2 f 1MHz UE es Min Typ Max Typ Max 31 CY62128ELL Ind Auto A 4 5 5 0 5 5 4541 13 2 11 16 1 4 CY62128ELL Auto E 4 5 5 0 5 5 55 1 3 4 11 35 1 30 Notes
12. m Vpg to Vcc min gt 100 us or stable at Vcc min gt 100 us 11 CE is the logical combination of CE and CE When CE is LOW and CE is HIGH CE is LOW when CE is HIGH or CE is LOW is HIGH Page 4 of 12 Document 38 05485 Rev F Feedback CYPRESS MoBL CY62128E PERFORM Switching Characteristics Over the Operating Range 45 ns Ind l Auto A 55 ns Auto E Parameter Description Unit Min Max Min Max Read Cycle tac Read Cycle Time 45 55 ns tAA Address to Data Valid 45 55 ns toHA Data Hold from Address Change 10 10 ns tACE LOW and HIGH to Data Valid 45 55 ns OE LOW to Data Valid 22 25 ns tLzOE OE LOW to 1 21131 5 5 ns tuzoE OE HIGH to High Z 3 14 18 20 ns lizcE CE LOW and CE HIGH to 1 21131 10 10 ns tuzcE CE HIGH or LOW to High Z 14 18 20 ns tpu CE LOW and HIGH to Power Up 0 0 ns tpp CE HIGH LOW to Power Down 45 55 ns Write Cyclel 5l twc Write Cycle Time 45 55 ns tscE CE LOW and CE HIGH to Write End 35 40 ns taw Address Setup to Write End 35 40 ns tha Address Hold from Write End 0 0 ns tsa Address Setup to Write Start 0 0 ns tpwe WE Pulse Width 35 40 ns tsp Data Setup to Write End 25 25 ns tup Data Hold from Write End 0 0 ns luzwE WE LOW to High ZU 141 18 20 ns tizwE WE HIGH to 1 21131 10 10 ns Notes 12 Test conditions for all param
13. nts in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 05485 Rev F Revised August 4 2008 Page 12 of 12 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document are the trademarks of their respective holders All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
14. v F ge Ul 790 8 10 51 85094 D Page 9 of 12 Feedback MoBL 62128 PERFORM Figure 8 32 pin Thin Small Outline Package Type 8 x 20 mm 51 85056 DIMENSION IN HH 1 5 HILL Zu Ay Z IT HE ORIENTATION TD 3 120 50 017 51 85U56 U Document 38 05485 Rev F Page 10 of 12 Feedback SEE CYPRESS MoBL CY62128E PERFORM Document History Page Document Title CY62128E MoBL 1 Mbit 128K x 8 Static RAM Document Number 38 05485 Submission Orig of Revision ECN Date Change Description of Change 203120 AJU New data sheet 299472 SYT Converted from Advance Information to Preliminary Changed tora from 6 ns to 10 ns for both 35 ns and 45 ns respectively Changed tpog from 15 ns to 18 ns for 35 ns speed bin Changed tuzwg from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns speed bins respectively Changed from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed bins respectively Changed from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed bins respectively Changed tgp from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed bins respectively Added Pb free package information Added footnote 9 Changed operating range for SOIC package from Commercial to Industrial Modified signal transition time from 5 ns to 3
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