Cypress CYS25G0101DX-ATC User's Manual
Contents
1. 26 Figure 19 Parallel Input Block Schematic Diagram 27 Figure 20 Signals Block Schematic Diagram 11 28 Figure 21 Power Supply Block Schematic Diagram 29 Figure 22 Control Block Schematic Diagram 30 2 Feedback 4 E CYS25G0101DX ATC Evaluation Board User s Guide CYPRESS List of Figures continued Figure 23 Reference Clock Block Schematic Diagram 31 Figure 24 CYS25G0101DX Evaluation Board PCB Mechanical Drawing 33 Figure 25 CYS25G0101DX Evaluation Board Layer Silk Screen 34 Figure 26 CYS25G0101DX Evaluation Board PCB Top Layer Layout 35 Figure 27 CYS25G0101DX Evaluation Board Top Layer Solder Mask 36 Figure 28 CYS25G0101DX Evaluation Board PCB Power Plane Layout 37 Figure 29 CYS25G0101DX Evaluation Board PCB Ground Plane Layout 38 Figure 30 CYS25G0101DX Evaluation Board PCB Bottom Silk Screen2. 39 Figure 31 CYS25G0101DX Evaluation Board PCB Bottom Layer Layout 40 Figure 32 CYS25G0101DX Evaluation Board PCB Bottom Solder Mask 41 List of Tables Table 1 Functional Description of the Connectors 6 Table 2 Pin Assignment of J1 Header and Description of J10 Header 7 Table 3 Pin Assignment of J2 Header and Description of J9 Header 8 Table 4 Functional Description of Switch 1 SW1 9 Table 5 Functional Description of Connector sanant 10 Table 6 Description of LED Indicators 2 0 22 4480 nenene nnne 10 Table 7 Operation Specification of CYS25G0101DX Evaluation Board 23 Table 8 CYS25G0101DX Evaluation Board LVPECL BOM Page 1 of 4 43 Table 9 CYS25G0101DX Evaluation Board LVPECL BOM Page 2 of 4 44 Table 10 CYS25G0101DX Evaluation Board LVPECL BOM Page 3 of 4 45 Table 11 CYS25G0101DX Evaluation Board LVPECL BOM Page 4 of 4 46 Table 12 CYS25G0101DX Evaluation Board HSTL BOM
3. _ n Y E ned CYPRESS CYS25G0101DX ATC Evaluation Board User s Guide RXDt5 H 6 CYPRESS SEMICONDUCTOR CYS25GB101DX CYS25G01020X 0 TRANSCEIVER EVAL BOARD Cypress Semiconductor Corporation 3901 North First Street SanJose 95134 408 943 2600 March 19 2002 Feedback CYS25G0101DX ATC Evaluation Board User s Guide 2 Table of Contents 1 E 4 BIUpIlsSeee 5 4 It 4 4 TERR 4 5 DIAGHOSTIC MOUOS BEY AURA RE 12 5 1 Diagnostic Loopback Mode ii icc doen mr E S Cu eR B Nn a UR pue e Eb Rx 12 5 2 Line LOOpDack imc PEE 13 5 3 Analog Eine Rae aut Ra EAR 14 5 4 Parallel Line Loopback TESTO Mode 44 10500000 15 5 4 1 Test the Internal RX CDR PLL Only 15 5 4 2 Test the Internal RX CDR PLL and TX PLL 15 6 Testing HOOKUP rien rias nin eo ia ocn re Rd Y ru FE du YI TO a aia e Ela 16 6 1 Set up for BERT Test 16 6 2 Set up for Eye Diagram Test 17 6 3 SONET Jitter Tr
4. 8 2558 x e ci T 4 xm x 2 x 4 ex 2 x A X eu CHE E onNU es x x 4 s pae 5 LAYER iim BOARD Figure 27 CYS25G0101DX Evaluation Board PCB Top Layer Solder Mask 36 Feedback CYS25G0101DX ATC Evaluation Board User s Guide CX X X NX X X X X X X X X X LAYER PLANE2 LAYER BOARD Figure 28 CYS25G0101DX Evaluation Board Power Plane Layout 37 Feedback CYS25G0101DX ATC Evaluation Board User s Guide W X X X X X X X X X X X X X X CK CK GND LAYER BOARD Figure 29 CYS25G0101DX Evaluation Board PCB Ground Plane Layout 38 Feedback CYS25G0101DX ATC Evaluation Board User s Guide mi agora m x x ie uv x 5 gt
5. 12 Figure 5 Line Loopback Mode Data Path 13 Figure 6 Analog Line Loopback Mode Data Path 14 Figure 7 Parallel Loopback TESTO Mode Data Path 15 Figure 8 Equipment Set up for BERT Test 16 Figure 9 Equipment Set up For Eye Diagram Test 17 Figure 10 Equipment Set up For Jitter Test 18 Figure 11 Equipment Set up For Testing the TX PLL in Parallel Line Loopback Mode 19 Figure 12 CYS25G0101DX Evaluation Board Eye Diagram 20 Figure 13 CYS25G0101DX Evaluation Board GR 253 Jitter Transfer Testing Result 21 Figure 14 CYS25G0101DX Evaluation Board 6958 Jitter Transfer Testing Result 21 Figure 15 CYS25G0101DX Evaluation Board GR 253 JitterTolerance Testing Result 22 Figure 16 CYS25G0101DX Evaluation Board 6825 Jitter Tolerance Testing Result 22 Figure 17 Level of CYS25G0101DX Evaluation Board Schematic Diagram 25 Figure 18 Parallel Output Block Schematic Diagram
6. e TEE x 7 2140 0 3 5 z m DU x 5 e TSA x 5 08 SL e OSEO c 55 8898 om EET 1 sa 5 ez x x 2 8 5550 asa e x E aso ILLE ene x x d 55555 x x sra 33383 418 m SIDE E rs Sx ex m B 51555 T eu e em we E ew e eu M 53 8 A o 6 ero e ex x B mmi ex 3 e ED x e F E am es 2 d EX z etm T m m 2 3 m x 22V LAYER Bi BOTTOM SILK LAYER BOARD Figure 30 CYS25G0101DX Evaluation Board PCB Bottom Silk Screen 39 CYS25G0101DX ATC Evaluation Board User s Guide x x x x x
7. Appendix C CYS25G0101DX Evaluation Board LVPECL BOM Bill of Material Feedback 25842 2842 3 zia 8012 019 019 019 019 AL 1NdOd LON Od doysedes diya arue487 Ja Kenyn 2090 LON Od Oooo oo co 4oy3edez 316187 2090 1012697 9003970132090 diyg Wea aaen 2090 Jn LOO 0079 FRED PLEO ELEO LEO OLED amp DE2 anes 0223 anea 9022 FOES 2022 2022 5 Ro EZ2 INOST LOLS OLIN dya 1 2090 34000 ez 120 022 OFED GEES PEED ered LEES ZED 97 ZED GZED GZED FCEO ZED 9020 2022 1020 95 282 9092770132090 Joysedes diyo 2nue18 5090 INL Oo 792 140 089 siayaedez ESI HLLIABZFPDBIA2OIA diu 2810449815 ese2 792 192 050 2 nsi Hid J381njog amp jnueqpy uonduasag 1 3 uonenpe 3 XGLOLODSZSAD CYS25G0101DX ATC Evaluation Board User s Guide Table 8 CYS25G0101DX Evaluation Board LVPECL BOM Page 1 of 4 Feedback 43 CYS25G0101DX ATC Evaluation Board User s Guide Table 9 CYS25G0101DX Evaluat
8. 4 Error Detector Tektronix D3286 Error Detector Allequipmentinthe listisfor reference only Pulse Generator HP 8133A Pulse Generator Power Supply HP E3631A DC Power Supply 5 k divided by 16 Tektronix D3286 HP 8133A Pulse Generator configure to Output Input ATTEN sn lt 4 Pattern Analyzer 66555668 mE wee BB External Tektronix 03186 Pattern Generator Input QV Q J HP E3631A Power Supply 1 Disconnect 2 Remove the OSC 3 Place C400 on C402 and C401 on C403 positions Cypress CYS25G0101DX Figure 11 Equipment Set up For Testing the TX PLL in Parallel Line Loopback Mode Evaluation Board Feedback 19 CYS25G0101DX ATC Evaluation Board User s Guide CYPRESS 7 Eye Diagram Testing Result Figure 12isthe Eye Diagram measurement from CYS25G0101DX Evaluation Board by using the test set up as in Figure 9 In this measurement the evaluation board is configured to parallel loop back mode Figure 7 and with SONET filter atthe oscilloscope Ae a anne eem md pa d PICO a E br RR Figure 12 CYS25G0101DX Evaluation Board Eye Diagram 20 Feedback 4 eE E 5 CYS25G0101DX ATC Evaluation Board User s Guide CYPRESS 8 Jitter Transfer Testing Resul
9. 10151584 2090 M DEOSDAAD H2 Nid 181njyegnueqg 1LSH Nid 0511 25 GLY 55 YGLH ES LS BSrid zr ri Gr Frid Cri LF riH 85H SSH ESH 299 188 OSH Ur GrH FRY tr 1015159 2090 wyo 0 zr 17 peog XaL0L0DSCSAO 50 Feedback CYS25G0101DX ATC Evaluation Board User s Guide Table 15 CYS25G0101DX Evaluation Board HSTL BOM Page 4 of 4 Disti P N 1225 CKNS007 ND Disti Manufacturer CYS2560101D ATC 3431 155 5200 105 01 5 0 m 5 gt o RN d Description o t I T di 5 9 3 55 e gt Lu gt x o 0 gt 2 with Ejector Clips and Keying Transceiver EHT 105 01 5 D CYS25GD0101DX Cypress 120TGFP 1450 SONET OC 48 155 5200MHz Clock Oscillator 4PIN OSC SKT DIP Osc BANANA DIP Switch Reference J3 J6 JZ J8 IHDRTX2 J10 P1 P2 P3 P4 F5 J10 J11 J12 J17 413 J15 15 18 Cypre
10. 46 Feedback CYS25G0101DX ATC Evaluation Board User s Guide Appendix D CYS25G0101DX Evaluation Board HSTL BOM Bill of Material Feedback CYS25G0101DX ATC Evaluation Board User s Guide Table 12 CYS25G0101DX Evaluation Board HSTL BOM Page 1 of 4 Nd sid 31411909 LON Od WOOOSHEOLYZEOSO 90 HLASE AWM Hid 115 peog ye 1022427 dyg 3146187 aken 2090 10128087 di JAAR INA 6090 Jn LO O 10128082 dya 2146187 2080 49001 10128082 dyg 218187 2090 Jn LO 947 210212813 g 8883 p 100912580 0 096505 92 9079 FORD EOFS 200 102 DDF2 GPED PRED FLED ELEO TLES LLES OLED 60 5 8060 069 9023 9062 POE 2023 ZOE 1062 OED EZ TH Wi 020 BEEN 8 0 986 GEES PEED BEES ZEEJ LEES 2 EZES SZEJ OCES 9022 9020 YOZA 2023 002 1022 022 782 290 82 182 092 90 ESI 299 182 092 ES EM way 48 Feedback CYS25G0101DX ATC Evaluation Board User s Guide Page 2 of 4 Table 13 CYS25G0101DX Evaluation Board HSTL BOM M d 0810 0001 090 Hid 181njyejnue gy
11. MA11 E 5 f Mw 226 5 TXb10 2 ze HG SMA10 c Dee 5 TXDTS H J2 5 x 2 REF NO 74 03005 P1 F cypress Cp 5 E EAT Figure 2 The CYS25G0101DX Evaluation Board Table 1 Functional Description of the Connectors Jumpers and Connectors Name Description J1 RxDBUS 16 bit RxD Data Bus interface header see Table 2fordetails Figure 3showsthe orienta tionofthis header J2 TxDBUS 16 bit TxD Data Bus interface header see Table 3for details Figure 3shows the orienta tionofthis header J3 TxCLKO H Header for CYS25G0101DX s TXCLKO pin 79 and GND Figure 3showsthe orientation ofthis jumper 94 OPTIC POWER Powersupply for external optical module see Table 5for details 6 Feedback 4 Q 9 2 MN CYS25G0101DX ATC Evaluation Board User s Guide Table 1 Functional Description of the Connectors continued Jumpers and Connectors Name Description J5 SD Thisjumperis usedtosetthe SD signal When open default SD signal will driven bythe optical module When 1 2 are shorted SD is forced to HIGH When 2 3 are shorted SD is forcedto LOW Figure 3shows the orientation of this jumper J6 TESTO This jumper when shorted is to enable the Parallel Line Loopback mode J7 LFI Test Tap for CYS25G0101DX sLFI pin
12. 1 Figure shows the orientation ofthis jumper J8 FIFO_ERR Test Tap for CYS25G0101DX s LIFO pin 51 Figure 3showsthe orientation of this jumper SMA10 TXCLKI Optional SMA connector for CYS25G0101DX s TXCLKI pin57 R37 need to popu lated if this connector is used SMA11 RXCLK Optional SMA connector for CYS25G0101DX s RXCLK pin 24 C118 R118 R138 and R158 need to be populated and C116 R116 and R136 need to be unpopulated if this connector is used SMA12 TXCLKO Optional SMAconnectorfor CYS25G0101DX s TXCLKO pin 79 C119 R119 R139 R159 need to be populated and C117 R117 and R137 need to be unpopulated if this connector is used SMA13 IN SMA connector for CYS25G0101DX s IN pin 109 This connector is also forthe optional optical module interface SMA14 IN SMA connector for CYS25G0101DX s IN pin 108 This connector is also forthe optional optical module interface SMA15 OUT SMAconnectorfor CYS25G0101DX sOUT pin 104 Thisconnectoris also forthe option aloptical module interface SMA16 OUT SMAconnectorfor CYS25G0101DX s OUT pin 103 Thisconnectoris also forthe option al optical module interface SMA17 REFCLKP Optional SMAconnectorfor CYS25G0101DX s REFCLK 87 Thisconnectorisforus ing the external reference clock instead of using the on board oscillator 155 52 MHz To use the external reference clock C400 and C401 0 01 4F cap have to be removed and placed on C402 and C403 positions A
13. 1LSH 40151584 E090 wo LON 5 c dyg 31048487 aken 2090 uonduasaqg XQLOLO0DSCSA2 El SELH ZELH 8014 2214 aci POLY EZLH COH 1214 OLY ALLY SLEH FEE ELLY ELE 8014 Z0LH 9014 9014 POLY EOLH COL LOY 70019 SEH 204 OLY SLY ELM LE OLY GH UH SH rH EH ZH 14 04 8119 GELS FELD ELL L2 OLEG 8012 8010 128012 SOLD COLD ZOLI 012 0010 49 Feedback CYS25G0101DX ATC Evaluation Board User s Guide Table 14 CYS25G0101DX Evaluation Board HSTL BOM Page 3 of 4 3200 po SBE Eu SOO 090 po Ifldod LON 09 Bl d 2024 8029 2024 902 40151584 2090 WYOHOL EDZH E 1015158 2090 dN 0 10151584 2090 uos gg COPY E 1015158 E090 zc 0 l 8124 ELZH 2128 10151584 2090 WYO 0029 10481534 2090 00 0028 ii
14. Page 1 of 4 48 Table 13 CYS25G0101DX Evaluation Board HSTL BOM Page 2 of 4 49 Table 14 CYS25G0101DX Evaluation Board HSTL BOM Page of 4 50 Table 15 CYS25G0101DX Evaluation Board HSTL BOM Page 4 of 4 51 3 Feedback 4 m CYS25G0101DX ATC Evaluation Board User s Guide 2 CYPRESS oo 1 Introduction Cypress s CYS25G0101DX SONET OC 48 Transceiverisacommunications building block for high speed SONET datacommunica tions It provides complete parallel to serial and serial to parallel conversions clock generation and clock and data recovery opera tionsinasingle chip optimized for full SONET SDH compliance The CYS25G0101 DX Evaluation Boardis designed for evaluating as well as understanding the characteristics of the CYS25G0101DX SONET SDH Transceiver The CYS25G0101DX SONET SDH Transceiver Evaluation Board provides the following advantages 2 Features Flexible and easy to operate On board Cypress 120 pin TQFP CYS25G0101DX SONET SDH Transceiver Supports LVPECL and HSTL interfaces Dip switch for selecting different diagnostic modes Four diagnostic modes Diagnostic Loopback mode Line Loopback mode Analog Line Loopback mode and factory TESTO Parallel Line Loopback mode LFlandFIFO_ERRLEDs Onboard oscillator forthe REFCLK Supports external cl
15. even whenLFlis toggling Insuch acase observe LFl using a scope on J7 OFF Indicates the selected receive data stream has been detected an invalid either LOW input on SD or by the receive VCO being oper ated outside its specified limits 10 Feedback CYS25G0101DX ATC Evaluation Board User s Guide 5A 1A 1B 5B ae __ 95 3 LFI GND FIFO_ERR GND J8 RXCLK TXCLKO GND GND 92 1 i E Da gt GND 288 f lt Pin 1 Vs rende 9116 2002 CYPRESS SEMICONDUCTOR 525001610 MEE 48 TRANSCEIVER EVAL BOARD Figure 3 The Jumper Orientations of the CYS25G0101DX 11 Feedback E CYS25G0101DX ATC Evaluation Board User s Guide CYPRESS 5 Diagnostic Modes The CYS25G0101DX Evaluation Board provides four different diagnostic modes Diagnostic Loopback mode Line Loopback mode Analog Loopback mode and Parallel Line Loopback mode Figure 4to Figure 7 illustrate these diagnostic modes and Figure 8to Figure 10illustrate the testing equipment set up for testing the characteristics ofthe CYS25G0101 DX 5 1 Diagnostic Loopback Mode Inthe Diagnostic Loopback mode parallel data willloopthrough the inputbuffer serializer block deserializer andthe outputbuff er Figure 4shows the data path bold line of the Diagnostic Loopback mode To s
16. x 99V X 9 466 NS i in Ea ajaaa Pere ererere Q coma 07070 x 9 e e x x 9 8 LAYER 6 BOTTOM GND LAYER BOTTOM SILK LAYER BOARD Figure 31 CYS25G0101DX Evaluation Board PCB Bottom Layer Layout 40 Feedback CYS25G0101DX ATC Evaluation Board User s Guide x E x x x x x d a e x e x x e 1 x x Di Ex e x u E ert tam sx 921 ps pp eee ea n 7 HIE se i oci au ai W g zo EN we m ux EUN 1 m a LAYER BOARD Figure 32 CYS25G0101DX Evaluation Board PCB Bottom Solder Mask 41 Feedback CYS25G0101DX ATC Evaluation Board User s Guide
17. 1A Cypress CYS25G0101DX Power Supply Evaluation Board 3333339333333 Figure 9 Equipment Set up Eye Diagram Test 17 Feedback CYS25G0101DX ATC Evaluation Board User s Guide gt CYPRESS 6 3 SONET Jitter Transfer and Jitter Tolerance Test Figure 10illustrates the set upfortestingthe jitter The equipmentlist 1 Evaluation Board Cypress CYS25G0101 DX Evaluation Board 2 SONETTester Agilent HP OmniBER 718 Communication Performance Analyzer 3 Optical Converters Agilent HP 83446A Receiver and 83430A Transmitter 4 PowerSupply HP E3631A DC Power Supply Allequipmentinthe listisfor reference only HP OmniBER 718 Communications Performance Analyzer Optical to Analog Converter i e HP s 83446A Analog to Optical Converter i e HP s 83430A EJ E93 C9 Cypress CYS25G0101DX Evaluation Board eooe 9 19 4333343333333434 HP E3631A Power Supply Figure 10 Equipment Set up For Jitter Test 18 Feedback CYS25G0101DX ATC Evaluation Board User s Guide Im M m CYPRESS 6 4 Set up for Testing the TX PLL in Parallel Line Loopback Mode Figure 11 illustrates the set up for testing the TX in Parallel Line Loopback Mode The equipmentlist Evaluation Board Cypress CYS25G0101 DX Evaluation Board Pattern Generator Tektronix 03186 Pattern Generator 1 2 3
18. 1DX Evaluation Board Feedback CYS25G0101DX ATC Evaluation Board User s Guide A e h 20 1 SUBAYI 81 53903 CHOG 30 S3HONI 99 NIHLIM SI 434309 ON Lt SIMUL YOLONONOD SY 1H9 3H 3MYS 1S0 ONY NO 50 4 91 5 009 281 LON 10005 SI SSTINN HONOWHL 5270 8 TV NO 30 720 1 L i098 38 TIVHS NO MOINIM 9 3Nndhils KINO 3403 SS3NDIOIHL 043130 34084 3004 5 101 38 ASN NO 20093730 291 55 Cuvod 72009 24 1 S3HONI NI SUNN 03419345 3SWAGHLO 55374 S310N Figure 24 CYS25G0101DX Evaluation Board Mechanical Drawing 33 Feedback CYS25G0101DX ATC Evaluation Board User s Guide S uli a ogogo lada 8 5 13 s SMA15 ogogo ol 4 2 i x m w 61 Swi x x c51 r
19. 25G0101DX ATC Evaluation Board User s Guide CYPRESS en gt o c C 5 Clock Block 2 5 A Om Figure 17 Top Level of CYS25G0101DX Evaluation Board Schematic Diagram 25 Feedback CYS25G0101DX ATC Evaluation Board User s Guide 1 sry HDR1X2 EJ HDRIX2 Figure 18 Parallel Output Block Schematic Diagram 26 WWW 46 AW Feedback CYS25G0101DX ATC Evaluation Board User s Guide HOR1X2 ANN i ANN ANN NWA ANN bo ANN WW ANN ANN WW AW Figure 19 Parallel Input Block Schematic Diagram 27 Feedback a 0 B9 m CYS25G0101DX ATC Evaluation Board User s Guide MJ O PRESS Y E 2 5 LIN O HB i iE i E 2 5 Z 5 Hi lt 2 Figure 20 Signals Block Schematic Diagram 28 Feedback POWER CONNECTI
20. 4 LOOPA mustbe ON position and SW1 3 LINELOOP mustbe in OFF position All other dip switches mustbe in their default positions as statedin Table 4 TESTO jumper J6 mustbe opened Applythe Testing Hookupillustrated in Figure 8to Figure 10 LINELOOP SW1 3 OFF LOOPA SW1 4 ON OUT Figure 6 Analog Line Loopback Mode Data Path 14 Feedback 55 CYS25G0101DX ATC Evaluation Board User s Guide 5 4 Parallel Line Loopback TESTO Mode In Parallel Line Loopback mode the parallel output buffers are internally linked to the parallel input buffers Figure 7 shows the data path bold line ofthe Parallel Line Loopback mode In this test mode the internal CDR PLL and TX PLL can be tested by different configurations 5 4 1 Test the Internal RX CDR PLL Only 1 2 3 4 TESTO jumper J6 mustbe shorted SW1 5 LOOPTIME mustbe in ON position All other dip switches mustbe in their default positions see Table 4 Applythe Testing Hookupillustratedin Figure 8to Figure 10forthe measurement 5 4 2 Test the Internal RX CDR PLL and TX PLL TESTO jumper J6 mustbe shorted All switches mustbe in their default positions see Table 4 Disconnect CLKVCC P2 remove the 155 52 MHz oscillator place C400 on C402 and C401 on C403 positions see Table 1 jumpers J17 and J18 for details Applythe Testing Hookupillustrated in Figure 11forthe measurement JUMPER J6 TESTO C
21. Functional Description of DIP Switch 1 SW1 continued Position Name State Description 5 LOOPTIME ON The transmission will be using the extracted receive bit clockforthe transmitted bit clock OFF Thetransmissionwillbeusingthe REFCLKinput 155 52 MHz which is multiplied by 16 to generate the transmitted bit clock 6 LOCKREF ON The receive PLL locks to serial data stream OFF The receive PLL locks to the REFCLK 7 PWRDN ON Disable Power Down Normal Operation OFF Enable Device Power Down mode All the logic and drivers are dis abledandplacedinto astandby conditionwhere only minimalpoweris dissipated 8 FIFO_RST ON Disable FIFO reset Normal Operation OFF Resetthe transmit FIFO pointers The in and out pointers of the trans mit FIFO are reset to the maximum separation Table 5 Functional Description of J4 Connector Pin Name Description 1B Power supply for optical module 2A 2B 4A 4B GND Power ground 5A NC No Connection 5B SD SD signal from optical module Table 6 Description of LED Indicators LED Name LED Status Description D1 FIFO_ERR ON The transmit FIFO has either under or overflowed The FIFO mustbe resetto clear the error by switching the DIP switch SW1 8to OFF and then ON See Table 4 for details OFF Indicates the FIFO has neither under or overflowed D2 LFI ON Indicates Line Fault Itwillappearto be ON
22. HE 10131584 2090 440028 10151584 2090 wwe 006 40151884 2090 dh 10181594 2090 WYO LE 193dA1 00993540 OL er Or abcd 9124 ZIEH OLEH bled S074 074 anc 024 gory rd OOF 0029 8514 9918 9514 915 915 ari Mis ari a3ualajaH 45 Feedback CYS25G0101DX ATC Evaluation Board User s Guide CYS25G0101DX Evaluation Board LVPECL BOM Page 4 of 4 Table 11 OLEND EE dama did 71710 05 10810207071 TS gir Fir EL air Zt LLP OUP 09 WOOES S51 Ww 1925 SMUD YES 230 did 118 050 101811930 993 ZHIADDZS S51 JI O LOLODSCS A2 20 801 5588457 uasuyor 97 00 L3NOS 9401051 5881449 0101099549 0 5 10 901 231495 pue 5915 10128 3 yya Bd Ed ld v Nd 9510 Nid 181njoegnue 18njaenueqy uonduasag 1934dA1 peog XaL0HIOSCSAO
23. LOSED A OUT Figure 7 Parallel Loopback TESTO Mode Data Path 15 Feedback CYS25G0101DX ATC Evaluation Board User s Guide EZ CYPRESS 6 Testing Hookup 6 1 Set up for BERT Test Figure 8illustratesthe set up forthe BERT test The equipmentlist Evaluation Cypress CYS25G0101 DX Evaluation Board Pattern Tektronix 03186 Pattern Generator 1 2 3 Error Detector Tektronix D3286 Error Detector Allequipmentinthe listisfor reference only Power Supply HP E3631A DC Power Supply 4 Tektronix D3286 Pattern Analyzer Tektronix D3186 Pattern Generator 500 Terminator Cypress CYS25G0101DX Evaluation Board Figure 8 Equipment Set up for BERT Test Feedback CYS25G0101DX ATC Evaluation Board User s Guide CYPRESS 6 2 Set up for Eye Diagram Test Figure 9illustratesthe set upfortestingthe Eye Diagram The 51 Evaluation Board Cypress CYS25G0101 DX Evaluation Board 1 2 Pattern Generator Tektronix D3186 Pattern Generator 3 Oscilloscope Agilent Infiniium DCA 86100A with 83484A Dual Channel 50GHz Module 4 PowerSupply HP E3631A DC Power Supply Allequipmentinthe listisfor reference only Agilent Infinium DAC 86100 Oscilloscope with 8348A Dual Channel 50GHz Module Tektronix D3186 Pattern Generator 22266 Trigger Out HP E363
24. ONS CYS25G0101DX ATC Evaluation Board User s Guide L3 3 2 Rm 3 L 12 LigePr La a 3 E LS peu EM 309 c sak EON eset H I mus p EM RN Figure 21 Power Supply Block Schematic Diagram 29 Feedback BOARD LED S FOR LFI AND FIFO ERR CYS25G0101DX ATC Evaluation Board User s Guide 15 3 PIN HEADER 858 714 515 i 5 2 2715 5 ANN 2 I 1 3 sll 8 58 5 fo 85 z A EA 6 124 gt 24 AAA 105 2 amn Figure 22 Control Block Schematic Diagram 30 Feedback 7 CYPRESS CYS25G0101DX ATC Evaluation Board User s Guide SEL3431AA 155 5200M CLOCKOSCILLATOR ANN 4 ANN ANN ANN CLOCK OSCILLATOR CIRCUIT Figure 23 Reference Clock Block Schematic Diagram 31 CYS25G0101DX ATC Evaluation Board User s Guide Appendix B PCB Layout Diagrams of the CYS25G010
25. REF 74 03005 P1 JOBNO 1258REV 0 c52 CYPRESS x SEMICONDUCTOR CYS25G0101DX CYS25G0102DX 48 TRANSCEIVER EVAL BOARD VC LAYER TOP SILK LAYER BOARD Figure 25 CYS25G0101DX Evaluation Board PCB Top Layer Silk Screen 34 Feedback CYS25G0101DX ATC Evaluation Board User s Guide OPTIC 5 5 0 5 N Q 2 __ IS DAR Ji x e o z SEMICONDUCTOR CYS25G0101DX 525691020 d TRANSCEIVER EVAL BOARD LAYER TOP SILK LAYER BOARD LAYER 1 TOP GND Figure 26 CYS25G0101DX Evaluation Board PCB Top Layer Layout 35 Feedback CYS25G0101DX ATC Evaluation Board User s Guide MIN FE TI e x x s 0 D e MON 2e a an e XO un c Md 8 oa 7
26. YS25G0101DX Evaluation Board 6825 Jitter Tolerance Testing Result 22 Feedback 4 CYPRESS CYS25G0101DX ATC Evaluation Board User s Guide 10 Schematic Diagram Layout of Material Figure 1710 Figure 23inAppendix Ashowsthe schematic diagram ofthe CYS25G0101 DX evaluation board Figure 17isthetoplevel diagramforthe schematicdiagramsfor Figure 18to Figure 23 Figure 24to Figure 32in Appendix Bshowthe PCBlayoutofeachlayer ofthe CYS25G0101 DX evaluation board The Bill of Material BOM ofthe evaluation 15 listed in Appendix C for LVPECL Table 8to Table 11 and Appendix D for HSTL Table 12to Table 15 respectively Table 7 Operation Specification of CYS25G0101DX Evaluation Board Description Min Max Unit Notes PowerSupply 3 135 3 465 V Current 280 320 mA Clock Power Supply CLKVCC 3 135 3 465 V Currentlci 75 90 mA Notes 1 The operation voltage VCC for the device at the power supply nodes 2 The operation current drawn by supply VCC at room temperature 3 Assumes onboard clock option If external clock SMA option is used the current drawn will depend on the termination resistors required for the external clock 23 Feedback CYS25G0101DX ATC Evaluation Board User s Guide Appendix A Schematic Diagrams of the CYS25G0101DX Evaluation Board Feedback se CYS
27. ae x 1 71 gt o DIAGLOOP x LINELOOP x 5 x O o LOOPA res O o LOOPTIME x Bog VCC _ OPTIC ws o TOCKREF x 5 17 x NN 52299 2 REFCLKP P2 mes o L re sa 58 T uc 2 C54 je emo C64 Testa 0 5 zt greed 212 OJE n SES 5 R218 032 EE ms s 5 a aC CLKVCC 10301 ars m 81474 x 9 1050 5 P3 REFCLKN m R200 2 x D SMA18 c50 5 ias Ga 2 R137 em 5 Ei O RXD2 H 8718 TXD1 HO 8 E x O RXD3 H ue De now diis 8 Q En d VDDQ 59 6 2 x B TXCLKO RXD7 H i 8 ne E R159 E x BO RXD H TXD9 HO 8 2 6 02 x TXD11 H O 8 O RXD12 H TXCLKI all gO B O RXD14 H GND TXbi4 HO m 5 1 V PAR 26 E 2 8 O RXD15 H 15 9 Q x S Ji 5 dius X C62 x x
28. ansfer and Jitter Tolerance Test 18 6 4 Set up for Testing the TX PLL in Parallel Line Loopback Mode 19 7 Eye Diagram Testing Result i i eae Face 20 8 Jitter Transfer Testing FUA RARE ANS 21 9 Jitter Tolerance Testing Result 22 10 Schematic Diagram PCB Layout and BOM of Material 23 Appendix A Schematic Diagrams of the CYS25G0101DX Evaluation Board 24 Appendix PCB Layout Diagrams of the CYS25G0101DX Evaluation Board 32 Appendix C CYS25G0101DX Evaluation Board LVPECL BOM Bill of Material 42 Appendix D CYS25G0101DX Evaluation Board HSTL BOM of Material 47 List of Figures Figure 1 The Block Diagram of the CYS25G0101DX 5 Figure 2 The CYS25G0101DX Evaluation Board 6 Figure 3 The Jumper Orientations of the CYS25G0101DX 11 Figure 4 Diagnostic Loopback Mode Data Path
29. eceive data output RXD13 The outputs change following RXCLKY 7 RXD12 HSTL output Parallel receive data output RXD12 The outputs change following RXCLKY 9 RXD11 HSTLoutput Parallel receive data output RXD11 The outputs change following RXCLKY 11 RXD10 HSTL output Parallel receive data output The outputs change following RXCLKY 13 RXD9 HSTLoutput Parallel receive data output RXD9 The outputs change following RX CLKY 15 RXD8 HSTLoutput Parallel receive data output RXD8 The outputs change following RX CLKY 17 RXD7 HSTLoutput Parallel receive data output RXD7 The outputs change following RX CLKY 19 RXD6 HSTLoutput Parallel receive data output RXD6 The outputs change following RX CLKY 21 RXD5 HSTLoutput Parallel receive data output RXD5 The outputs change following RX CLKY 23 RXD4 HSTL output Parallel receive data output RXD4 The outputs change following RX CLKY 25 RXD3 HSTL output Parallel receive data output RXD3 The outputs change following RX CLKY 27 RXD2 HSTL output Parallel receive data output RXD2 The outputs change following RX CLKY 29 RXD1 HSTL output Parallelreceive data output RXD1 Theoutputs changefollowing RX CLKY 31 RXDO HSTL output Parallel receive data output RXDO The outputs change following RX CLKY 2 4 6 8 10 GND Ground Ground 12 14 16 18 20 22 24 26 28 30 32 J10 RXCLK HSTL output Receive clock output This clock is divided by 16 ofthe bit rate clock extracted from
30. elect the Diagnostic Loopback mode 1 SW1 2 DIAGLOOP mustbein ON position SW1 3 LINELOOP Allother dip switches mustbe in their default positions as statedin Table 4 TESTO jumper J6 mustbe opened Applythe Testing Hookupillustrated in Figure 8to Figure 10 DIAGLOOP SW1 2 ON Figure 4 Diagnostic Loopback Mode Data Path 12 Feedback CYS25G0101DX ATC Evaluation Board User s Guide CYPRESS 5 2 Line Loopback In the Line Loopback mode serial data from IN will loop through the serial input buffer and CDR block to the serial output buffer OUT Figure 5shows the data path bold line ofthe Line Loopback mode selectthe Line Loopback mode 1 SW1 3 LINELOOP mustbe in ON position Allother dip switch settings mustbe in their default positions as statedin Table 4 TESTO jumper J6 mustbe opened Applythe Testing Hookupillustrated in Figure 8to Figure 10 SW1 3 ON LOOPA SW1 4 OFF OUT IN Figure 5 Line Loopback Mode Data Path 13 Feedback CYS25G0101DX ATC Evaluation Board User s Guide CYPRESS 5 3 Analog Line Loopback In the Analog Line Loopback mode serial data from IN will loop through directly from serial input buffer to the serial output buffer OUT Figure 6 shows the data path bold line of the Analog Line Loopback mode To selectthe Analog Line Loopback mode 1 SW1
31. input TXD5 The input datais sampled by TX CLKIT 24 TXD4 HSTL input Paralleltransmitdatainput TXD4 Theinputdatais sampled by TX CLKIT 26 TXD3 input Paralleltransmitdatainput TXD3 Theinputdatais sampled by CLKIT 28 TXD2 input Paralleltransmitdatainput TXD2 Theinputdatais sampled by TX CLKIT 30 TXD1 input Paralleltransmitdatainput TXD1 Theinputdatais sampled by TX CLKIT 32 TXDO input Paralleltransmitdatainput TXDO Theinputdatais sampled by TX CLKIT J9 TXCLKI HSTL input Paralleltransmitdata input clock Table 4 Functional Description of DIP Switch 1 SW1 Position Name State Description 1 RESET ON Disable Reset Normal operation OFF Resetforalllogicfunctions exceptthetransmit FIFO 2 DIAGLOOP ON Transmit data from TXD 15 0 is routed through the receive clock and data recovery and presented at RXD 15 0 output OFF Receivedserialdata fromIN isroutedthroughthereceiveclockand datarecovery and presented at RXD 15 0 output 3 4 LINELOOP ON ON Invalid setting SOORA ON OFF Received serialdata is looped back from receive input IN to trans mit output OUT after being reclocked by the recovered clock OFF ON Received serial data is looped back from receive input IN to trans mit output OUT but is not routed through the clock and data recovery PLL OFF OFF Disable serial dataloop back Feedback 4 CYS25G0101DX ATC Evaluation Board User s Guide Table 4
32. ion Board LVPECL BOM Page 2 of 4 SSHOREOSO OHS 101818854 2090 uuo Lr 10151584 2090 wyog 08 10 LE cr EJE Lr rr 00 N d Ist NODEDSO 242 4002 3008 10451584 2090 wyo 0 40451534 E090 1015158 2080 uonduasaq 193dA 1 Pog XALOLOSSZSAD 99 PSH 158 LEH po 919 ESH za 054 tH FRY JEH SEY DEH 324 ETH SLY Fly I LLY OLY SH FH EH 24 18 44 Feedback CYS25G0101DX ATC Evaluation Board User s Guide Table 10 CYS25G0101DX Evaluation Board LVPECL BOM Page 3 of 4 SLOOLEOSOA JHI 520015 JHE 30 215 300286 000 31911904 LON 00 sig Nid 181m3ejnue py ul 200 ho d y 40151384 2090 WYO 10151584 2090 WOO 10151834 2090 dh 1015158 2090 10151584 2090 4405728 10151584 2090 Wytse 40181890 2090 WYT
33. lso The CLKVCC P2 has to be discon nected from the power supply SMA18 REFCLKN Optional SMAconnectorfor CYS25G0101DX s REFCLK pin87 Thisconnectorisforus ing the external reference clockinstead of using the on board oscillator 155 52 MHz To use the external reference clock C400 and C401 0 01 4F cap have to be removed and placed on C402 and C403 positions Also The CLKVCC P2 has to be discon nected from the power supply P1 GND Power Ground For external power supply P2 CLKVCC Power supply 3 3V forthe clock oscillator VDDQ Power supply 3 3V for LVPECL output 1 5V for HSTL outputs P4 VCC OPTIC Power supply 3 3V forthe optional optical module P5 VCC Power supply 3 3V for digital and low speed I O function P6 V_Par Power supply 3 3V for L VPECL output 1 5V for HSTL outputs Table 2 Pin Assignment of J1 Header and Description of J10 Header Pin Number Name Characteristics Description 1 RXD15 HSTL output Parallel receive data output RXD15 The outputs change following RXCLKL 3 RXD14 HSTL output Parallel receive data output RXD14 The outputs change following RXCLKL 7 Feedback CYS25G0101DX ATC Evaluation Board User s Guide CYPRESS Table 2 Pin Assignment of J1 Header and Description of J10 Header continued Pin Number Name Characteristics Description 5 RXD13 HSTL output Parallel r
34. ock source for the REFCLK 16 bit RxD 16 bit TxD bus RXCLK TXCLKI TXCLKO interface SMA connectors for CML input and output buffers Separate Banana Jacks for all voltage sources for measuring current individually 3 Kit Contents CYS25G0101DX Evaluation Board Certificate of Compliance e CYS25G0101DX Evaluation Kit CD UsersGuide Application Notes DataSheet 4 Functional Description This board can be used to test the CYS25G0101DX in various modes such as TESTO parallel line loopback mode LINELOOP LOOPA and LOOPTIME REFCLK of the CYS25G0101DX is connected to the onboard 155 52 MHz oscillator The on board REFCLK can be replaced by connecting the external reference clock source to J17 and J18 To use the external reference clock source the C400 and C401 0 01 uF cap have tobe removed and placed on C402 and C403 positions Also the P2 CLKVCC has to be disconnected from the power supply or power down The CYS25G0101DX Evaluation Board provides an optional optical module interface for connecting to an optical module daughter card The block diagram of the CYS25G0101DX is shown in Figure 1 The detailed functional description can be found in the CYS25G0101DX data sheet Figure 2 shows the picture of the CYS25G0101DX Evaluation Board and the location of the jumpers Table 1isthe description of alljumpers and connectors The bus connectors J1 and J2 areusedto connecttothe 16 bit RxD and TxD busesfortransfer
35. ring andreceivingthe parallel data Table 2and Table 3are the pin definitions of J1 and J2 A multi function eight po sition Dip switch provides the selection of the different diagnostic modes as well as the control functions Table 4 is the functional de scription of the Dip switch SW1 The TESTO jumper J6 when closed is usedto enable the factory TESTO Parallel Line Loop Back mode Inthe Parallel Line Loop Back mode parallel outputbuffers are internally jumpedto the parallelinput buffers There is no need touse external jumpers forthe headers J13 J14 J15 J16andJ4 are Differential CMLinputandoutputandpowersupplyforthe option al optical module daughter card Table 5idescribes the optical module interface and Table 6idescribes the LED Figure 3shows the jumper orientations of the CYS25G0101DX Evaluation Board Feedback CYS25G0101DX ATC Evaluation Board User s Guide CYPRESS 155 52MHz 155 52MHz 155 52MHz FIFO ERR FIFO RST TXCLKI S TXCLKO REFCLK RXCLKOUT 8 Ny Output gt Register Recovered Bit Clock SHIFTER mE PLL Retimed Data X Input Lock to Data Clock Control Logic OUT PWRDN LOCKREFSD LFI RESET M Figure 1 The Block Diagram of the CYS25G0101DX Feedback CYS25G0101DX ATC Evaluation Board User s Guide SMA13 SMA14 SMA16 SMA15 J4 P4 SW1 J5 SMA17 J6 J7 P2 D2 D1 SMA18 P3 J8 J3 SMA12
36. ss Semiconductor Corporation 2002 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product Nor does it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges Feedback
37. t Figure 13and Figure 14showthe Jitter Transfer measurementby usingthetestset up asin Figure 10 Figure 13isthe measurement resultofthe GR 253 Bellcore standard and Figure 14isthemeasurementresultofthe G958 ITU standard Inthis measurement the CYS25G0101DX evaluation board is configured to parallel loopback mode Figure 7 GR 253 Mask 2 5 5 Gain dB 60 Freq Hz 10 100 1K 10K 100K 1M 10M Figure 13 CYS25G0101DX Evaluation Board GR 253 Jitter Transfer Testing Result 6958 Mask 2 5Gb s Type Gain dB 60 i Freq Hz 10 100 1 10K 100K 1M 10M Figure 14 CYS25G0101DX Evaluation Board G958 Jitter Transfer Testing Result 21 Feedback CYS25G0101DX ATC Evaluation Board User s Guide 9 Jitter Tolerance Testing Result Figure 15and Figure 16showthe Jitter Tolerance measurementby usingthetestset up asin Figure 10 Figure 15isthemeasurement resultofthe GR 253 Bellcore standard and Figure 16isthemeasurementresultofthe G825 ITU standard Inthis measurement the CYS25G0101DX evaluation board is configured to parallel loopback mode Figure 7 GR 253 Mask 2 5Gb s Amplitude UI 0 1 Freq Hz 0 1 1 10 100 1K 10K 100K iM Figure 15 CYS25G0101DX Evaluation Board GR 253 JitterTolerance Testing Result 6825 Mask 2 56b s Amplitude UI 0 1 i Freq Hz 0 1 1 10 100 1K 10K 100K iM TON Figure 16 C
38. the received serial stream Table 3 Pin Assignment of J2 Header and Description of J9 Header Pin Number Name Characteristics Description 1 3 5 7 9 11 GND Ground Ground 13 15 17 19 21 23 25 27 29 31 2 TXD15 HSTL output Paralleltransmitdatainput TXD15 The input datais sampled by TX CLKIT 4 TXD14 input Paralleltransmitdatainput TXD14 The input datais sampled by TX CLKIT 6 TXD13 HSTL input 3 Theinputdatais sampled by TX CLKI Feedback CYS25G0101DX ATC Evaluation Board User s Guide 7 CYPRESS Table 3 Pin Assignment of J2 Header and Description of J9 Header continued Pin Number Name Characteristics Description 8 TXD12 HSTL input Paralleltransmitdata input TXD12 The inputdatais sampled by TX CLKIT 10 TXD11 HSTL input Paralleltransmitdata input TXD10 The input datais sampled by TX CLKIT 12 TXD10 input Paralleltransmitdatainput TXD9 Theinputdatais sampled by CLKIT 14 TXD9 HSTL input Paralleltransmitdatainput TXD8 Theinputdatais sampled by TX CLKIT 16 TXD8 input Paralleltransmitdatainput TXD8 Theinputdatais sampled by CLKIT 18 TXD7 input Paralleltransmitdatainput TXD7 Theinputdatais sampled by CLKIT 20 TXD6 input Paralleltransmitdatainput TXD6 Theinputdatais sampled by TX CLKIT 22 TXD5 input Paralleltransmitdata
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