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Cypress CY7C1350G User's Manual

1. write mechanism has been provided to simplify the write Second Third Fourth operations Byte write capability has been included in order to aie w ae c A greatly simplify Read Modify Write sequences which can be d gt reduced to simple byte write operations 00 01 10 11 Because the CY7C1350G is a common I O device data 01 00 11 10 should not be driven into the device while the outputs are 10 11 00 01 active The Output Enable OE can be deasserted HIGH T 10 01 00 before presenting data to the DQs and DQPy p inputs Doing so will tri state the output drivers As a safety precaution DQs Linear Burst Address Table MODE GND and are automatically tri stated during the data portion of a write cycle regardless of the state of OE Second Third Fourth Burst Write Accesses won ras AM B The CY7C1350G has an on chip burst counter that allows the 00 01 10 1 user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs 01 10 11 00 ADV LD must be driven LOW in order to load the initial 10 11 00 01 address as described in the Single Write Access section 11 00 01 10 above When ADV LD is driven HIGH on the subsequent clock rise the chip enables CE4 CEs and CE3 and WE inputs are Truth Table 3 4 5 6 7 8 Operation Address Used CE ZZ ADV LD WE BW OE CEN CLK DQ Deselect Cycle None H L L X X X L L H Tri State Continue Deselect Cycle None X L
2. L 4 20 61 Vss 21 60 Vss DQp 22 59 DQ 23 BYTE D BYTE A 24 57 DQA DQp 25 56 DQ Vss 26 55 J Vss 27 54 Vona DQp 28 53 DQp 29 52 DQA DQPp 30 51 DOP _ s CU OOO U D c0 c0 c0 co c0 co st cst cs cs cS GS GS B GG GS B GT u lt lt lt lt lt lt 8 85 5 5 S gt lt lt lt lt lt lt lt gt a gt o Oo zz 22 Document 38 05524 Rev F Page 2 of 15 Feedback a 4 CYPRESS P ERF ORM CY7C1350G Pin Configurations continued 119 Ball BGA Pinout 1 2 3 4 5 6 7 A Vppa A A NC 18M A A Vppa B NC 576M ADV LD A CEs NC C NCAG A A Vpp A A NC D Vss NC Vss DOP Vss BE Vss DQg DQg F VDDQ DQc Vss OE Vss VDDQ G DQc DQc BWc
3. Oooo oooc K L L M OOOQOOO M N N P P R R T U f J f T U M H 1 27 0 70 REF A 381 12 00 7 62 in B t 14 00 0 20 e 9 30 TYP A 0 15 4X lt 2 40 o S 1 1 51 85115 B T SEATING PLANE i a o Z 025c 0415C 50 0 10 ZBT is a trademark of Integrated Device Technology Inc NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation All product and company names mentioned in this document may be the trademarks of their respective holders Document 38 05524 Rev F Page 14 of 15 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant in
4. P 0 r a sw s s gt r ra SSE 00 207 EN T I SM Features CEN d D YPRESS PERFORM CY7C1350G Pin compatible and functionally equivalent to ZBT devices Internally self timed output buffer control to eliminate the need to use OE Byte Write capability 128K 36 common I O architecture 3 3V power supply Vpp 2 5V 3 3V I O power supply Vppq Fast clock to output times 2 6 ns for 250 MHz device Clock Enable CEN pin to suspend operation Synchronous self timed writes Asynchronous output enable OE Available in lead free 100 Pin TQFP package lead free and non lead free 119 Ball BGA package Burst Capability linear or interleaved burst order ZZ Sleep mode option Logic Block Diagram ADDRESS 1 REGISTER Al Di MODE b ADV LD WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 po BURST Qol A1 1 9 AO LOGIC 4 Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1350G is a 3 3V 128K x 36 synchronous pipelined Burst SRAM designed specifically to support unlimited true back to back Read Write operations without the insertion of wait states The CY7C1350G is equipped with the advanced No Bus Latency NoBL logic required to enable
5. Feedback A ry CYPRESS CY7C1350G PERFORM Truth Table 3 4 5 6 7 8 continued Operation Address Used CE ZZ ADV LD WE BW OE CEN CLK DQ NOP WRITE ABORT Begin Burst None L L L L H X L L H Tri State WRITE ABORT Continue Burst Next X L H X H X L L H Tri State IGNORE CLOCK EDGE Stall Current X L X X X X H L H SNOCZE MODE None X H X X X X X X Tri State Partial Truth Table for Read Write 3 9 Function WE BWp BWc BWg BW Read H X X X X Write No bytes written L H H H H Write Byte A DQ DQPA L H H H L Write Byte B DQg and L H H L H Write Bytes A B L H H L L Write Byte C DQc and L H L H H Write Bytes C A L H L H L Write Bytes C B L H L L H Write Bytes C B A L H L L L Write Byte D DQp and DQPp L L H H H Write Bytes D A L L H H L Write Bytes D B L L H L H Write Bytes D B A L L H L L Write Bytes D C L L L H H Write Bytes D C A L L L H L Write Bytes D C B L L L L H Write All Bytes L L L L L ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Snooze mode standby current ZZ gt Vpp 0 2V 40 mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tzzREC ZZ recovery time ZZ 0 2N 2tcyc ns tzzi ZZ active to snooze current This parameter is sampled 2
6. S 5 gt E N E gt G V INPUT INPUT N REGISTER 1 REGISTER O K READ LOGIC SLEEP CONTROL Note 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com Cypress Semiconductor Corporation Document 38 05524 Rev F 198 Champion Court San Jose CA 95134 1709 e 408 943 2600 Revised July 5 2006 Feedback e lt IR m nd LI PERFORM Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit Maximum Access Time 2 6 2 8 3 5 4 0 4 5 ns Maximum Operating Current 325 265 240 225 205 mA Maximum CMOS Standby Current 40 40 40 40 40 mA Pin Configurations 100 Pin TQFP Pinout 88 gt a 1 0 020 X F 5 ui lt E 3 lz E lo 2 2 91582 Z lt lt oc r Qd i0 st CO F lt qo DO sk CO QN e O O O O O O O O O O WO DQPc 1 80 DOP DQc 2 79 DQg 3 78 Vppo 4 77 Vppo Vss 5 76 Vss BYTEC DQc 75 7 DQ BYTE B 7 74 DQg DQc 8 73 DQg DQc 9 72 DQg Vss 10 71 Vss Vppa 11 70 DQg 12 69 poc CY7C1350G Bn Das 14 67 Vss 15 66 NC NC 16 65 Vpp Vss 17 64 zz DQp 18 63 7 DQ 7 19 62 DQA
7. 51 85050 16 00 0 20 14 00 0 10 1 40 0 05 80 s 0 30 0 08 22 00 0 20 20 00 0 10 L 0 65 TYP SEE DETAIL A 51 1 30 m 0 20 MAX 1 60 MAX R 0 08 MIN 0 20 MAX e 0 MIN 2 SEATING PLANE STAND OFF q 0 05 MIN NOTE n 0 15 MAX GAUGE PLANE n J 1 JEDEC STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH R0 08 MIN MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 0 7 0 20 BODY LENGTH DIMENSIONS ARE PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 FT 0 20 MIN 51 85050 B 1 00 REF DETAIL Document 38 05524 Rev F Page 13 of 15 Feedback I ned CYPRESS CY7C1350G PERFORM Package Diagrams continued 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 90 05 ME Y 025 A1 CORNER 0 75 0 15 119X 61 00 3 REF 123456 7 j 7654321 A y 00 009 A B 0 m 9000000 D 5 D E F ooooooc F G G H o E a E ET OD e amp J K 7 8
8. H X X X L L H Tri State Read Cycle Begin Burst External L L L H x L L L H Data Out Q Read Cycle Continue Burst Next X L H X X L L L H Data Out Q NOP Dummy Read Begin Burst External L L L H X H L L H Tri State Dummy Read Continue Burst Next X L H X X H L L H Tri State Write Cycle Begin Burst External L L L L L X L L H Data In D Write Cycle Continue Burst Next X L H X L X L L H Data In D Notes X Don t Care H Logic HIGH L Logic LOW CE stands for ALL Chip Enables active BW L signifies at least one Byte Write Select is active BW Valid signifies that the desired byte write selects are asserted see Write Cycle Description table for details Write is defined by BWy and WE See Write Cycle Descriptions table 2 3 4 When a write cycle is detected all DQs are tri stated even during byte writes _ 5 The DQ and pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock 6 7 8 CEN H inserts wait states Device will power up deselected and the DQs in a tri state condition regardless of OE OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle DQs and DQPr p tri state when OE is inactive or when the device is deselected and DQs and data when OE is active Document 38 05524 Rev F Page 5 of 15
9. NC 9M BWg DQg H Vss WE Vss DQg DQg J Vss Vpp Vss Vpp Vppo K DQp DQp Vss CLK Vss DQ DQA L DQp DQp BWp NC BWA DQA DQA M Vppo DQp Vss CEN Vss DQA Vppo N DQp DQp Vss A1 Vss DQA DQA P DQp Vas AO Vss DOP DQ R NC 144M A MODE Vpp NC A NC 288M T NC NC 72M A A A NC 36M ZZ U Vppo NC NC NC NC NC Vppo Pin Definitions Name 1 0 Description AO A1 A Input Address Inputs used to select one of the 128K address locations Sampled at the rising edge Synchronous of the CLK Aj are fed to the two bit burst counter BWia p Input Byte Write Inputs active LOW Qualified with WE to conduct writes to the SRAM Sampled on Synchronous he rising edge of CLK WE Input Write Enable Input active LOW Sampled on the rising edge of CLK if CEN is active LOW This Synchronous signal must be asserted LOW to initiate a write sequence ADV LD Input Advance Load Input Used to advance the on chip address counter or load anew address When Synchronous HIGH and CEN is asserted LOW the internal burst counter is advanced When LOW a new address can be loaded into the device for an access After being deselected ADV LD should be driven LOW in order to load a new address CLK Input Clock Clock Input Used to capture all synchronous inputs to the device CLK is qualified with CEN CLK is only recognized if CEN is active LOW CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Sy
10. of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Document 38 05524 Rev F Page 10 of 15 Feedback gt CYPRESS CY7C1350G Switching Waveforms continued NOP STALL and DESELECT Cycles 9 20 22 ax A FX FF FAT 1 2 3 4 5 6 7 8 J VE D 7 Q Q 0 0 REI M I A A we MT m Woo D ADDRESS 7 TK YO i Z ZI AS EXIIT 77 tcHZ Data man X 003 In Out DQ READ STALL NOP Q A3 DONTCARE Z UNDEFINED CONTINUE DESELECT READ Q A5 WRITE DESELECT D A4 WRITE STALL D A1 READ Q A2 ZZ Mode Timing 24 DAT S RE CA CI TATATA z j except ZZ DON T CARE Notes 22 The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrates CEN being used to create a pause A write is not performed during this cycle 23 Device must be deselected when entering ZZ mode See cycle description table for all possible signal conditions to deselect the device 24 DGs are in high Z when exiting ZZ sleep mode Document 38 05524 Rev F Page 11 of 15 CYPRESS PERFORM Ordering Information CY7C1350G Not all of the speed p
11. to GND selects linear burst Strap pin sequence When tied to VDD or left floating selects interleaved burst sequence Vpp Power Supply Power supply inputs to the core of the device VDDQ Power Supply Power supply for the I O circuitry Vss Ground Ground for the device NC No Connects Not internally connected to the die 9M 18M 36M 72M 144M and 288M are address expansion pins in this device and will be used as address pins in their respective densities and control logic The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus provided OE is active LOW After the first clock of the read access the output buffers are controlled by OE and the internal control logic OE must be driven LOW in order for the device to drive out the requested data During the second clock a subsequent operation Read Write Deselect can be initiated Deselecting the device is also pipelined Therefore when the SRAM is deselected at clock rise by one of the chip enable signals its output will tri state following the next clock rise Burst Read Accesses The CY7C1350G has an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must be dr
12. 0 0 ns toEHz QE HIGH to Output 211 15 2 6 2 8 3 5 4 0 45 ns Set up Times tas Address Set up Before CLK Rise 1 2 1 2 1 5 1 5 1 5 ns tats ADV LD Set up Before CLK Rise 1 2 1 2 1 5 1 5 1 5 ns twes GW BWy Set Up Before CLK Rise 1 2 1 2 1 5 1 5 1 5 ns CEN Set up Before CLK Rise 1 2 1 2 1 5 1 5 1 5 ns tps Data Input Set up Before CLK Rise 1 2 1 2 1 5 1 5 1 5 ns tcEs Chip Enable Set Up Before CLK 1 2 1 2 1 5 1 5 1 5 ns Rise Hold Times tAH Address Hold After CLK Rise 0 3 0 5 0 5 0 5 0 5 ns tALH ADV LD Hold after CLK Rise 0 3 0 5 0 5 0 5 0 5 ns twEH GW BWy Hold After CLK Rise 0 3 0 5 0 5 0 5 0 5 ns tcENH CEN Hold After CLK Rise 0 3 0 5 0 5 0 5 0 5 ns toy Data Input Hold After CLK Rise 0 3 0 5 0 5 0 5 0 5 ns Chip Enable Hold After CLK Rise 0 3 0 5 0 5 0 5 0 5 ns Notes 13 This part has a voltage regulator internally tpowERn is the time that the power needs to be supplied above Vpop minimum initially before a Read or Write operation can be initiated 14 tonz tcrz togrz and togpz are specified with AC test conditions shown in part b of AC Test Loads Transition is measured 200 mV from steady state voltage 15 At any given voltage and temperature togpz is less than tog and toyz is less than 7 to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designe
13. 1 ns trzzI ZZ inactive to exit snooze current This parameter is sampled 0 ns Note 9 Table only lists a partial listing of the byte write combinations Any combination of BW is valid Appropriate write will be done on which byte write is active Document 38 05524 Rev F Page 6 of 15 Feedback a sg CYPRESS CY7C1350G PERFORM Maximum Ratings DC Input Voltage 0 5V to Vpp 0 5V Abavaswiich dmpsired For aserauides Current into Outputs LOW 20 mA lines not tested Static Discharge Voltage gt 2001V Storage Temperature 65 C to 150 C per MIL STD 883 Method 3015 Ambient Temperature with Latch up Current essen gt 200 Power 55 C to 125 C Operating Range Supply Voltage on Vpp Relative to 0 5V to 4 6V Ambient Supply Voltage on Vppq Relative to GND 0 5V to Vpp Range Temperature TA Vpp VDDQ DC Voltage Applied to Outputs Commercial 0 C to 70 C 3 3V 5 2 5V 596 eere eerte e 0 5V to Vppo 0 5V Industrial 40 to 85 10 to Vpp Electrical Characteristics Over the Op
14. 3V I O Test Load R 3170 OUTPUT 3 3V ALL INPUT PULSES OUTPUT Vppo 90 500 10 10 5 pF GND 3510 lt 1ns gt gt lt ins Vr 1 5 INCLUDING JIG AND c 8 scope 0 2 5 I O Test Load R 16670 OUTPUT 2 5V 9 ALL INPUT PULSES OUTPUT PRS E 90 10 10 215380 lt ins gt lt ins INCLUDING JIG AND c a scope 0 Note 12 Tested initially and after any design or process changes that may affect these parameters Document 38 05524 Rev F Page 8 of 15 Feedback os CE CYPRESS CY7C1350G PERFORM Switching Characteristics Over the Operating Rangel 18 250 200 166 133 100 Parameter Description Min Max Min Max Min Max Min Max Min Max Unit tPOWER Vpp typical to the first Accessl 3 1 1 1 1 1 ms Clock Clock Cycle Time 4 0 5 0 6 0 7 5 10 ns tcu Clock HIGH 1 7 2 0 2 5 3 0 3 5 ns teL Clock LOW 1 7 2 0 2 5 3 0 3 5 ns Output Times tco Data Output Valid After CLK Rise 2 6 2 8 3 5 4 0 4 5 ns Data Output Hold After CLK Rise 1 0 1 0 1 5 1 5 1 5 ns telz Clock to 2114 15 16 0 0 0 0 0 ns tcHz Clock to 211 15 16 2 6 2 8 3 5 4 0 45 ns toev OE LOW to Output Valid 2 6 2 8 3 5 4 0 45 ns toELz OE LOW to Output Low Z 4 15 16 0 0 0
15. 4 mm CY7C1350G 166BGXC 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1350G 166AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1350G 166BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1350G 166BGXI 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free 200 CY7C1350G 200AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1350G 200BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1350G 200BGXC 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1350G 200AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1350G 200BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1350G 200BGXI 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free 250 CY7C1350G 250AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1350G 250BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1350G 250BGXC 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1350G 250AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1350G 250BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1350G 250BGXI 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free Document 38 05524 Rev F Page 12 of 15 Feedback IE LIC we SS IER Z CYPRESS CY7C1350G PERFORM Package Diagrams 100 Pin TQFP 14 x 20 x 1 4 mm
16. ackage and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Package Type Range 100 CY7C1350G 100AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1350G 100BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1350G 100BGXC 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1350G 100AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1350G 100BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1350G 100BGXI 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free 133 CY7C1350G 183AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 Lead Free Commercial CY7C1350G 133BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1350G 133BGXC 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1350G 133AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1350G 133BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1350G 133BGXI 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free 166 CY7C1350G 166AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1350G 166BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2
17. active 3 the Write Enable input signal WE is deasserted HIGH and 4 ADV LD is asserted LOW The address presented to the address inputs is latched into the Address Register and presented to the memory core Document 38 05524 Rev F Name 1 0 Description ZZ Input ZZ sleep Input This active HIGH input places the device in a non time critical sleep condition Asynchronous with data integrity preserved During normal operation this pin has to be low or left floating ZZ pin has an internal pull down DQs I O Bidirectional Data I O Lines As inputs they feed into an on chip data register that is triggered Synchronous by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by the address during the clock rise of the read cycle The direction of the pins is controlled by OE and the internal control logic When OE is asserted LOW the pins can behave as outputs When HIGH DQ and DQPy are placed in a tri state condition The outputs are automati cally tri stated during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE I O Bidirectional Data Parity I O Lines Functionally these signals are identical to DQ During write Synchronous sequences DQP a p is controlled by BW a p correspondingly MODE Input Mode Input Selects the burst order of the device When tied
18. consec utive Read Write operations with data being transferred on every clock cycle This feature dramatically improves the throughput of the SRAM especially in systems that require frequent Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock The clock input is qualified by the Clock Enable CEN signal which when deasserted suspends operation and extends the previous clock cycle Maximum access delay from the clock rise is 2 6 ns 250 MHz device Write operations are controlled by the four Byte Write Select BWra p and a Write Enable WE input All writes are conducted with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE4 CE CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri state control In order to avoid bus contention the output drivers are synchronously tri stated during the data portion of a write sequence ADV LD e BWa BWe BWc BWo WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC 2 U D P A T N U T P T A u E R MEMORY WRITE E S B gt DQs DRIVERS ARRAY A U DQPa M 5 E E DQPs P T E E DQPc S R R
19. d to achieve tri state prior to Low Z under the same system conditions 16 This parameter is sampled and not 100 tested 17 Timing reference level is 1 5V when Vppq 3 3V and is 1 25V when Vppq 2 5V 18 Test conditions shown in a of AC Test Loads unless otherwise noted Document 38 05524 Rev F Page 9 of 15 Feedback Ie CYPRESS CY7C1350G PERFORM Switching Waveforms Read Write Timing 9 20 21 1 2 tc 3 4 5 6 7 8 9 10 gt gt tCENS tCENH cx Wah MD LAE MD m Md m m T T T T T T T T T T tces tCEH a MUU Wd Wd HI ADV LD we A EE O O FA _ 10 BWao 7k 2 2 ML TY AT WL ADDRESS A1 Dias H oae I A2 A3 A4 4 tCLZ ii cree tas gt 1 Dara A pan pia2 W X Da2 tps tDH In Out DQ OE i i i i i i i i i WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D A1 D A2 WRITE Q A3 Q A4 READ D A5 Q A6 D A7 D A2 1 Q A4 1 CARE Q UNDEFINED Notes 19 For this waveform ZZ is tied LOW A NN 20 When CE is LOW is LOW CE is HIGH and is LOW When CE is HIGH CE is HIGH or is LOW CE3 is HIGH 21 Order
20. erating Rangel 11 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ I O Supply Voltage 2 375 Vpp V VoH Output HIGH Voltage for 3 3V I O lop 4 0 mA 2 4 V for 2 5V I O 1 0 mA 2 0 V VoL Output LOW Voltage for 3 3V I O Io 8 0 mA 0 4 V for 2 5V I O loj 21 0 mA 0 4 V Input HIGH Voltage 3 3V 20 Vpp 03V V Vppo 2 5V 1 7 Vpp 03V V Vi Input LOW Voltage 0 Vppo 3 3V 0 3 0 8 V Vppo 2 5V 0 3 0 7 V Ix Input Leakage Current GND x lt Vppq 5 5 HA except ZZ and MODE Input Current of MODE Input Vsg 30 Input Vpp 5 HA Input Current of ZZ Input Vss 5 Input Vpp 30 HA loz Output Leakage GND lt V lt Vppo Output Disabled 5 5 uA Current Ipp Vpp Operating Supply Vpp Max lour 0 mA 4 ns cycle 250 MHz 325 mA Current f fmax l tevc 5 ns cycle 200 MHz 265 mA 6 ns cycle 166 MHz 240 mA 7 5 ns cycle 133 MHz 225 mA 10 ns cycle 100MHz 205 mA Ispy Automatic CE Vpp Max Device Deselected 4 ns cycle 250 MHz 120 mA 6 ns cycle 166 MHz 100 mA 7 5 ns cycle 133 MHz 90 mA 10 ns cycle 100 MHz 80 mA Automatic CE Vpp Max Device Deselected All speeds 40 mA Power down Vin 0 3V or Vin gt Vppq 0 3V f 0 Current CMOS Inputs Notes 10 Overshoot lt Vpp 1 5V Pulse width less than 2 undershoot Vi gt 2V Pulse width less than tcyc 2 11 Tpower up Assumes a linear ramp fr
21. est condition from VDDQ lt Vpp to VDDQ lt Vpp Modified test condition from Vin lt Vpp to lt Vpp Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51 85050 from A to B Updated the Ordering Information E 419705 See RXU Added 100 MHz speed grade F 480368 See VKN Added the Maximum Rating for Supply Voltage on Vppo Relative to GND Updated the Ordering Information table Document 38 05524 Rev F Page 15 of 15 Feedback
22. iven LOW in order to load a new address into the SRAM as described in the Single Read Access section above The sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an interleaved burst sequence Both burst counters use AO and A1 in the burst sequence and will wrap around when incremented sufficiently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of chip enables inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or Write is maintained throughout the burst sequence Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 CE and CE are ALL asserted active and 3 the Write signal WE is asserted LOW The address presented to the address inputs is loaded into the Address Register The write signals are latched into the Control Logic block Page 4 of 15 Feedback CYPRESS PERFORM j i On the subsequent clock rise the data lines are automatically tri stated regardless of the state of the OE input signal This allows the external logic to present the data on DQs and DQPry p In addition the address for the subsequent access Read Write Deselect is latched into the Address Register provided the appropriate control signals are asserted On the nex
23. jury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback i a a G CYPRESS PERFORM Document History Page CY7C1350G Document Title CY7C1350G 4 Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Document Number 38 05524 Issue Orig of REV ECN NO Date Change Description of Change 25 224380 See ECN RKF New data sheet A 276690 See ECN Changed TQFP pkg to lead free TQFP in Ordering Info section Added comment of BG lead free package availability B 332895 See ECN SYT Converted from Preliminary to Final Removed 225 MHz and 100 MHz speed grades Address Expansion balls in the pinouts for 119 BGA Package was modified as per JEDEC standards Modified VoL Voy test conditions Replaced TBDs for and jc to their respective values on the Thermal Resistance table Changed the package name for 100 TQFP from A100RA to A101 Removed comment on the availability of BG lead free package Updated Ordering Information by removing Shaded Parts C 351194 See PCI Updated Ordering Information Table D 419264 See RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Modified t
24. nchronous CE and to select deselect the device CE gt Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction with Synchronous and CE to select deselect the device CE3 Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous and CE to select deselect the device OE Input Output Enable asynchronous input active LOW Combined with the synchronous logic block Asynchronous inside the device to control the direction of the I O pins When LOW the I O pins are allowed to behave as outputs When deasserted HIGH I O pins are tri stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state when the device has been deselected CEN Input Clock Enable Input active LOW When asserted LOW the Clock signal is recognized by the Synchronous SRAM When deasserted HIGH the Clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required Document 38 05524 Rev F Page 3 of 15 Feedback a CYPRESS PERFORM CY7C1350G Pin Definitions continued Functional Overview The CY7C1350G is a synchronous pipelined Burst SRAM designed specifically to eliminate wait states during Write Read transitions All synchr
25. om OV to Vpp min within 200 ms During this time lt Vpp and Vppo lt Vpp Document 38 05524 Rev F Page 7 of 15 Feedback a n IKK CYPRESS CY7C1350G PERFORM Electrical Characteristics Over the Operating Rangel 11 continued Parameter Description Test Conditions Min Max Unit Isp3 Automatic CE Vpp Max Device Deselected 4 ns cycle 250 MHz 105 mA Power Down Vin lt 0 3V or Vin gt VDDQ 0 3 5 ns cycle 200 MHz 95 mA Current CMOS f fmax l tevc Inputs 6 ns cycle 166 MHz 85 mA 7 5 ns cycle 133 MHz 75 mA 10 ns cycle 100 MHz 65 mA Automatic CE Vpp Max Device Deselected All speeds 45 mA Power Down Vin 2 Vin or Vin lt Vit f 0 Current TTL Inputs Capacitance 100 TQFP 119 BGA Parameter Description Test Conditions Max Max Unit Cin Input Capacitance 25 f 1 MHz 5 5 pF Clock Input Capacitance Vpp 3 3V 3 3V 5 5 pF Cio Input Output Capacitance 5 7 pF Thermal Resistance 100 TQFP 119 BGA Parameter Description Test Conditions Package Package Unit OJA Thermal Resistance Junction to Test conditions follow standard 30 32 34 1 C W Ambient test methods and procedures for measuring thermal impedance Thermal Resistance Junction to per EIA JESD51 6 85 14 0 C W Case AC Test Loads and Waveforms 3
26. onous inputs pass through input registers controlled by the rising edge of the clock The clock signal is qualified with the Clock Enable input signal CEN If CEN is HIGH the clock signal is not recognized and all internal states are maintained All synchronous operations are qualified with CEN All data outputs pass through output registers controlled by the rising edge of the clock Maximum access delay from the clock rise tco is 2 6 ns 250 MHz device Accesses can be initiated by asserting all three Chip Enables CE CEs CE3 active at the rising edge of the clock If Clock Enable CEN is active LOW and ADV LD is asserted LOW the address presented to the device will be latched The access can either be a read or write operation depending on the status of the Write Enable WE BWr4 p can be used to conduct Byte Write operations Write operations are qualified by the Write Enable WE All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE CE CE3 and asynchronous Output Enable OE simplify depth expansion All operations Reads Writes and Deselects are pipelined ADV LD should be driven LOW once the device has been deselected in order to load a new address for the next operation Single Read Accesses A read access is initiated_when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 and are ALL asserted
27. t clock rise the data presented to DQs or a subset for Byte Write operations see Write Cycle Description table for details inputs is latched into the device and the write is complete The data written during the Write operation is controlled by BWia p _ signals The CY7C1350G provides byte write capability that is described in the Write Cycle Description table Asserting the Write Enable input WE with the selected Byte Write Select BW p input will selectively write to only the desired bytes Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed CY7C1350G ignored and the burst counter is incremented The correct inputs must be driven in each cycle of the burst write in order to write the correct bytes of data Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE CEs and CE3 must remain inactive for the duration of tzzagc after the ZZ input returns LOW Interleaved Burst Address Table MODE Floating or Vpp

Cypress CY7C1350G User's Manual

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