Cypress CY7C1302DV25 User's Manual
Contents
1. tions can be used to capture the contents of the Input and Output ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the Identification Register Definitions table TAP Instruction Set Eight different instructions are possible with the three bit instruction register All combinations are listed in the Instruction Code table Three of these instructions are listed as RESERVED and should not be used The other five instruc tions are described in detail below Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO pins To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instructio2. Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture set up plus hold times tcs and tcp The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preloaded data can be shifted in Document 38 05625 Rev A CY7C1302DV25 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTES
3. V Vic input LOW Voltage S T fT a YP Ver 0 1 y lx Input Load Current GND lt Vi lt VDDQ 5 5 LA loz Output Leakage Current GND lt V lt Vppq Output Disabled 5 5 pA VREF Input Reference Voltage Typical value 0 75V 0 68 0 75 0 95 V Ipp Vpp Operating Supply Vpp Max lour 0 mA 500 mA f fmax t tcyc Ispi Automatic Max Vpp Both Ports Deselected 240 mA Power Down Vin 2 Vin or Vin lt Vit f fmax Current 1 tcyc Inputs Static AC Input Requirements Over the Operating Range Parameter Description Test Conditions Min Typ Max Unit Vin Input HIGH Voltage Vrer 0 2 V Vit Input LOW Voltage Veer 0 2 V Notes 13 Overshoot ViH AC lt Vppq 0 85V Pulse width less than tcyc 2 Undershoot Vi AC gt 1 5V Pulse width less than tcyc 2 14 Power up Assumes a linear ramp from OV to Vpp min within 200 ms During this time Viy lt Vpp and Vppa lt Vpp 15 All voltage referenced to Ground 16 Output are impedance controlled lo Vppq 2 RQ 5 for values of 175Q lt RQ lt 3500 17 Output are impedance controlled lo Vppaq 2 RQ 5 for values of 175Q lt RQ lt 3500 18 This spec is for all inputs except C and C Clock For C and C Clock Vj Max Vger 0 2V 19 Vref Min 0 68V or 0 46Vppq whichever is larger Vaer Max 0 95V or 0 54Vppq whichever is smaller Document 38 05625 Rev A Page 13 of 18 Feedback CYPRESS PE
4. 51 85180 A Samsung All product and company names mentioned in this document are trademarks of their respective holders Document 38 05625 Rev A Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Page 17 of 18 Feedback CYPRESS PERFORM Document History Page CY7C1302DV25 Document Title CY7C1302DV25 9 Mb Burst of 2 Pipelined SRAM with QDR Architecture Document Number 38 05625 Document 38 05625 Rev A Orig of REV ECN NO Issue Date Change Description of Change E 253010 See ECN SYT New Data Sheet A 436864 See ECN NXR Conve
5. CYPRESS CY7C1302DV25 PERFORM SSS Maximum Ratings Static Discharge Voltage ccccscscssscsesssesseeseeees gt 2001V per MIL STD 883 Method 3015 Above which the useful life may be impaired Latch Up CuUrrent cecceeeceeeeeeeneeseeeeeeeteneeeeeeeeetaes gt 200 mA Storage Temperature ceeeeeeeeeeeeeetees 65 C to 150 C Ambient Temperature with Operating Range Power Applied 2 c ccceeeeeeeceeeeeeeeeeneeees 55 C to 125 C Ambient Supply Voltage on Vpp Relative to GND 0 5V to 3 6V Range Temperature Ta Vool Vopa Supply Voltage on Vppo Relative to GND 0 5V to Vpp Com l 0 C to 70 C 2 5 0 1V 1 4V to 1 9V DC Applied to Outputs in High Z 0 5V to Vppg 0 5V P9 40 C to 85 C DC Input Voltage ooo esecsscesseesseenees 0 5V to Vpp 0 5V Current into Outputs LOW ceeeeeeeeeeceeeeeneeeneeee 20 mA Electrical Characteristics Over the Operating Rangel DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Typ Max Unit Vpp Power Supply Voltage 2 4 2 5 2 6 V VDDQ I O Supply Voltage 1 4 1 5 1 9 V VoH Output HIGH Voltage Note 16 Vppg 2 0 12 Vppd 2 0 12 V VoL Output LOW Voltage Note 17 VDpo 2 0 12 Vppd 2 0 12 V VoH Low Output HIGH Voltage lop 0 1 mA Nominal Impedance Vppo 0 2 VDDQ V Vot Low Output LOW Voltage loL 0 1 mA Nominal Impedance Vss 0 2 V Vin Input HIGH Voltage Vper 0 1 Vopo 0 3
6. NC Q17 A A C A A NC DO Qo R TDO TCK A A A C A A A TMS TDI Pin Definitions Name VO Description Di17 0 Input Data input signals sampled on the rising edge of K and K clocks during valid Write opera Synchronous tions WPS Input Write Port Select active LOW Sampled on the rising edge of the K clock When asserted active Synchronous a Write operation is initiated Deasserting will deselect the Write port Deselecting the Write port will cause Dj17 9 to be ignored BWSo Input Byte Write Select 0 1 active LOW Sampled on the rising edge of the K and K clocks during BWS Synchronous Write operations Used to select which byte is written into the device during the current portion of the Write operations Bytes not written remain unaltered BWSp controls Djg 9 and BWS controls Di47 9 All the Byte Write Selects are sampled on the same edge as the data Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device A Input Address Inputs Sampled on the rising edge of the K read address and K write address clocks Synchronous for active Read and Write operations These address inputs are multiplexed for both Read and Write operations Internally the device is organized as 512K x 18 2 arrays each of 256K x 18 These inputs are ignored when the appropriate port is deselected QH7 0 Outputs Data Output signals These pins drive out the requested data during a Read operation Valid dat
7. mA 1 7 V VoH2 Output HIGH Voltage lop 100 pA 2 1 V Vou Output LOW Voltage lo 2 0 mA 0 7 V VoL2 Output LOW Voltage loL 100 pA 0 2 V Vin Input HIGH Voltage 1 7 Vpp 0 3 V Vit Input LOW Voltage 0 3 0 7 V lx Input and Output Load Current GND lt Vi lt VDDQ 5 5 pA TAP AC Switching Characteristics Over the Operating Range 121 Parameter Description Min Max Unit ttcyc TCK Clock Cycle Time 50 ns tte TCK Clock Frequency 20 MHz tty TCK Clock HIGH 20 ns tr TCK Clock LOW 20 ns Set up Times ttuss TMS Set up to TCK Clock Rise 10 ns trois TDI Set up to TCK Clock Rise 10 ns tes Capture Set up to TCK Rise 10 ns Hold Times ttMsH TMS Hold after TCK Clock Rise 10 ns TDIH TDI Hold after Clock Rise 10 ns tou Capture Hold after Clock Rise 10 ns Notes 10 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels are specified in the Electrical Characteristics table 11 Teg and Toy refer to the set up and hold time requirements of latching data from the boundary scan register 12 Test conditions are specified using the load in TAP AC test conditions Tr Tf 1 ns Document 38 05625 Rev A Page 9 of 18 Feedback CY PREDO CY7C1302DV25 PERFORM TAP AC Switching Characteristics Over the Operating Range continued 1 121 Parameter Description Min Max Unit Output Times ttpov TCK Clock LOW to TDO Valid 20 ns ttpox TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Te
8. ns Set up Times tsa tsa Address Set up to Clock K and K Rise 0 7 ns tsc tsc Control Set up to Clock K and K Rise RPS WPS BWSp BWS4 0 7 ns tsp tsp Dj17 0 Set up to Clock K and K Rise 0 7 ns Hold Times tHa tHa Address Hold after Clock K and K Rise 0 7 ns tuc tuc Control Signals Hold after Clock K and K Rise 0 7 ns RPS WPS BWS BWS tup tup Dj17 0 Hold after Clock K and K Rise 0 7 ns Notes 20 Tested initially and after any design or process change that may affect these parameters 21 Unless otherwise noted test conditions assume signal transition time of 2V ns timing reference levels of 0 75V Vref 0 75V RQ 250W Vppq 1 5V input pulse levels of 0 25V to 1 25V and output loading of the specified Io Ioy and load capacitance shown in a of AC test loads 22 This part has a voltage regulator that steps down the voltage internally tpower is the time power needs to be supplied above Vpp minimum initially before a read or write operation can be initiated Document 38 05625 Rev A Page 14 of 18 Feedback CYPRESS CY7C1302DV25 PERFORM Switching Characteristics Over the Operating Range continued 1 Cypress Consortium 1O ies Parameter Parameter Description Min Max Unit Output Times tco tcHav C C Clock Rise or K K in single clock mode to Data Valid 2 5 ns tpou tcHax Data Output Hold after Output C C Clock Rise Active to Active 1 2 ns tcuz tou
9. BWS can be altered on different portions of a Write cycle as long as the set up and hold requirements are achieved 38 05625 Document 38 05625 Rev A Page 5 of 18 Feedback CYPRESS PERFORM IEEE 1149 1 Serial Boundary Scan JTAG These SRAMs incorporate a serial boundary scan test access port TAP in the FBGA package This part is fully compliant with IEEE Standard 1149 1 1900 The TAP operates using JEDEC standard 2 5V I O logic levels Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO should be left unconnected Upon power up the device will come up in a reset state which will not interfere with the operation of the device Test Access Pori Test Clock The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this pin unconnected if the TAP is not used The pin is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI pin is used to serially input information int
10. RFORM CY7C1302DV25 Thermal Resistance Parameter Description Test Conditions 165 FBGA Package Unit OJA Thermal Resistance Junction to Ambient Test conditions follow standard test 16 7 C W F methods and procedures for measuring o Oje Thermal Resistance Junction to Case thermal impedance per EIA JESD51 2 5 C W Capacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHz 5 pF Cok Clock Input Capacitance L DD me 6 pF Co Output Capacitance eo 7 pF AC Test Loads and Waveforms Vper 0 75V Vaer o 0 75V OUTPUT VREF j 0 0 75V R 500 21 ALL INPUT PULSES Device OUTPUT 1 25V Under Device 0 75V Test Under 5 pF 0 25V Veer 0 75V ast ZQ ll Slew Rate 2 Vins RQ RQ 2500 oun a b Switching Characteristics Over the Operating Range P1 Cypress Consortium oie Parameter Parameter Description Min Max Unit tpower Vcc typical to the First Access Read or Write 10 us Cycle Time teyc tkKHKH K Clock and C Clock Cycle Time 6 0 ns tki tKHKL Input Clock K K and C C HIGH 2 4 ns tk tKLKH Input Clock K K and C C LOW 2 4 ns tKHKH tKHKH K K Clock Rise to K K Clock Rise and C C to C C Rise rising edge 2 7 3 3 ns to rising edge tKHCH tKHCH K K Clock Rise to C C Clock Rise rising edge to rising edge 0 0 2 0
11. T The EXTEST instruction enables the preloaded data to be driven out through the system output pins This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift DR controller state EXTEST Output Bus Three state IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a three state mode The boundary scan register has a special bit located at bit 47 When this scan cell called the extest output bus three state is latched into the preload register during the Update DR state in the TAP controller it will directly control the state of the output Q bus pins when the EXTEST is entered as the current instruction When HIGH it will enable the output buffers to drive the output bus When LOW this bit will place the output bus into a High Z condition This bit can be set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell will latch into the preload register When the EXTEST instruction is entered this bit will directly control the output Q bus pins Note that this bit is pre set HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved f
12. a Synchronous is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode When the Read port is deselected Qi 7 9 are automatically three stated RPS Input Read Port Select active LOW Sampled on the rising edge of positive input clock K When Synchronous active a Read operation is initiated Deasserting will cause the Read port to be deselected When deselected the pending access is allowed to complete and the output drivers are automatically three stated following the next rising edge of the C clock Each read access consists of a burst of two sequential transfers Document 38 05625 Rev A Page 2 of 18 Feedback CYPRESS PERFORM CY7C1302DV25 Pin Definitions continued Name VO Description C Input Positive Input Clock for Output Data C is used in conjunction with C to clock out the Read data Clock from the device C and C can be used together to deskew the flight times of various devices on the board back to the controller See application example for further details C Input Clock Negative Input Clock for Output Data C is used in conjunction with C to clock out the Read data from the device C and C can be used together to deskew the flight times of various devices on the board cack to the controller See application example for further details K Input Clock Positive Inpu
13. a aege _ _ Seas F _ S SS i S YPREDO PERFORM Features Separate independent Read and Write data ports Supports concurrent transactions 167 MHz clock for high bandwidth 2 5 ns Clock to Valid access time 2 word burst on all accesses Double Data Rate DDR interfaces on both Read and Write ports data transferred at 333 MHz 167 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C and to minimize clock skew and flight time mismatches Single multiplexed address input bus latches address inputs for both Read and Write ports Separate Port Selects for depth expansion Synchronous internally self timed writes 2 5V core power supply with HSTL Inputs and Outputs Available in 165 ball FBGA package 13 x 15 x 1 4 mm Variable drive HSTL output buffers Expanded HSTL output voltage 1 4V 1 9V JTAG Interface Configurations CY7C1302DV25 512K x 18 Cypress Semiconductor Corporation Logic Block Diagram CY7C1302DV25 CY7C1302DV25 9 Mbit Burst of Two Pipelined SRAMs with QDR Architecture Functional Description The CY7C1302DV25 is a 2 5V Synchronous Pipelined SRAM equipped with QDR architecture QDR architecture consists of two separate ports to access the memory array The Read port has dedicated data outputs to support Read operations and the Write Port has dedic
14. ated data inputs to support Write operations Access to each port is accomplished through a common address bus The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock QDR has separate data inputs and data outputs to completely eliminate the need to turn around the data bus required with common I O devices Accesses to the CY7C1302DV25 Read and Write ports are completely independent of one another All accesses are initiated synchronously on the rising edge of the positive input clock K In order to maximize data throughput both Read and Write ports are equipped with DDR interfaces Therefore data can be transferred into the device on every rising edge of both input clocks K and K and out_of the device on every rising edge of the output clock C and C or K and K in a single clock domain thereby maximizing performance while simplifying system design Each address location is associated with two 18 bit words that burst sequentially into or out of the device Depth expansion is accomplished with a Port Select input for each port Each Port Select allows each port to operate independently All synchronous inputs pass through input registers controlled by the K or K input clocks All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks Writes are conducted with on chip synchronous self timed write circuit
15. mation presented to_Dj17 9 is stored into the Write Data register provided BWS 1 o are both asserted active The 36 bits of data are then written into the memory array at the specified location When deselected the Write port will ignore all inputs after the pending Write operations have been completed Byte Write Operations Byte Write operations are supported by the CY7C1302DV25 A Write operation is initiated as described in the Write Operation section above The bytes that are written are deter mined by BWS and BWS which are sampled with each set of 18 bit data word Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered This feature can be used to simplify Read Modify Write operations to a Byte Write operation 38 05625 Single Clock Mode The CY7C1302DV25 can be used with a single clock mode In this mode the_device will recognize only the pair of input clocks K and K that control both the input and output Application Example SRAM 1 eno D DATA IN DATA OUT Address CY7C1302DV25 registers This operation is identical to the operation if the device had zero skew between the K K and C C clocks All timing parameters remain the same in this mode _To use
16. n register It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction Page 6 of 18 Feedback CYPRESS PERFORM is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is given during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and output pins is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This will not harm the device but there is no guarantee as to the value that will be captured
17. o the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see the TAP Controller State Diagram TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB on any register Test Data Out TDO The TDO output pin is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine see Instruction codes The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register Performing a TAP Reset A Reset is performed by forcing TMS HIGH Vpp for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a high Z state TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction registers Data is serially loaded into the TDI pin on the rising edge of TCK Data is output on the TDO pin on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into
18. ode Diagram Package Type Range 167 CY7C1302DV25 167BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1302DV25 167BZXC 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead free CY7C1302DV25 167BZI 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial Package Diagram 165 ball FBGA 13 x 15 x 1 4 mm 51 85180 TOP VIEW aiid 1 2 3 4 5 6 z 8 9 10 11 A B Cc D E F G e i a s J 5 K E M N P R LAJ B 13 00 0 10 U 3 a g 2 fgl 2 2 fo q T SEATINGPLANE j j o c 3 Quad Data Rate SRAM and QDR SRAM comprise a new family of products developed by Cypress IDT NEC Renesas and 0 35 0 06 BOTTOM VIEW 0 05M PIN 1 CORNER 0 25 MEAIB 0 50 6 165X 0 14 m 10 9 8 F 6 5 4 3 2 1 if eo0000d00000d o0000gv00000 1 lal ocooo0ogpgpoo0oo0oo00 s COo00COoO00000 CO00OOO00000 OoOOo0oo0oO gd OO 00 0 COCO OoOv00000 e je g s oee 0 6 6 Go 8 eoo0000o00000 COoO0C0Ov00000 o ooo Ooo oO OO OO 8 s x COoO00OOoO00000 C0000 000000 CO0COv 00000 0000 P00008 A ai 5 00 10 00 B 13 00 0 10 A 0 15 4X NOTES SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0 475g JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE CODE BBOAC
19. or future use Do not use these instructions Page 7 of 18 TAP Controller State Diagram CYPRESo PERFORM TEST LOGIC RESET CY7C1302DV25 y TEST LOGIC IDLE Note A SELECT oy 1 A DR SCAN 1 a gt CAPTURE DR SELECT IR SCAN oy 0 SHIFT DR y y EXIT1 DR EXIT2 DR y PAUSE DR CAPTURE DR 0 pe SHIFT IR t L EXIT1 IR A PAUSE IR UPDATE DR Vy 0 EXIT2 IR Y UPDATE IR Ty 7 9 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Document 38 05625 Rev A Page 8 of 18 Feedback CYPRESS CY7C1302DV25 PERFORM TAP Controller Block Diagram pe 0 B Bypass Register TDI Selection gt 211 0 m Selection TDO Circuitry f l Circuitry Instruction Register m 31 30 29 1 121110 m Identification Register Lpeli06 ete h 2b er Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range 13 15 Parameter Description Test Conditions Min Max Unit Von Output HIGH Voltage lon 2 0
20. r Supply Power supply inputs to the core of the device Vss Ground Ground for the device VDDQ Power Supply Power supply inputs for the outputs of the device Introduction synchronous data outputs Qi17 9 pass through output Functional Overview registers controlled by the rising edge of the output clocks C and C or K and K when in single clock mode The CY7C1302DV25 is a synchronous pipelined Burst SRAM equipped with both a Read port and a Write port The Read port is dedicated to Read operations and the Write port is dedicated to Write operations Data flows into the SRAM through the Write port and out through the Read port These devices multiplex the address inputs in order to minimize the number of address pins required By having separate Read and Write ports the QDR I completely eliminates the need to turn around the data bus and avoids any possible data contention thereby simplifying system design 38 05625 Accesses for both ports are initiated on the rising edge of the Positive Input Clock K All synchronous input timing is refer enced from the rising edge of the input clocks K and K and all output timing is referenced to the output clocks C and C or K and K when in single clock mode All synchronous data inputs D 17 9 pass through_input registers controlled by the input clocks K and K All Document 38 05625 Rev A All synchronous control RPS WPS BWSj1 inputs pass through input registe
21. remains unaltered L H L H_ During the Data portion of a Write sequence only the lower byte Djg o is written into the device Di17 9 remains unaltered H L L H oy the Data portion of a Write sequence only the byte D 17 9 is written into the device Dig o remains unaltered H L L H_ During the Data portion of a Write sequence only the byte Dj47 9 is written into the device Drg o remains unaltered H H L H No data is written into the device during this portion of a Write operation H H L H No data is written into the device during this portion of a Write operation Notes X Don t Care H Logic HIGH L Logic LOW t represents rising edge Device will power up deselected and the outputs in a three state condition A represents address location latched by the devices when transaction was initiated A 0 A 1 represent the addresses sequence in the burst symmetrically 38 05625 NOORwWD t represents the cycle at which a Read Write operation is started t 1 is the first clock cycle succeeding the t clock cycle Data inputs are registered at K and K rising edges Data outputs are delivered on C and C rising edges except when in single clock mode It is recommended that K K and C C when clock is stopped This is not essential but permits most rapid restart by overcoming transmission line charging Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table BWS
22. rs controlled by the rising ledge of input clocks K and K Read Operations The CY7C1302DV25 is organized internally as 2 arrays of 256K x 18 Accesses are completed in a burst of two sequential 18 bit data words Read operations are initiated by asserting RPS active at the rising edge of the positive input clock K The address is latched on the rising edge of the K clock Following the next K clock rise the corresponding lower order 18 bit word of data is driven onto the Qh7 o using Cas the output timing reference On the euibsequent rising edge of C the higher order data word is driven onto the QiH17 0 The requested data will be valid 2 5 ns from the rising edge of the output clock C and C or K and K when in single clock mode 167 MHz device Page 3 of 18 Feedback y 9 CYPRESS PERFORM Synchronous internal circuitry will automatically three state the outputs following the next rising edge of the positive output clock C This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock K On the same K clock rise the data presented to Dj17 9 is latched into the lower 18 bit Write Data register provided BWS 1 9 are both asserted active On the subsequent rising adie F the negative input clock K the address is latched and the infor
23. rted from Preliminary to Final Removed 133 MHz amp 100 MHZ from product offering Included the Industrial Operating Range Changed C C Description in the Features Section amp Pin Description Table Changed trcyc from 100 ns to 50 ns changed trp from 10 MHz to 20 MHz and changed ty and tr from 40 ns to 20 ns in TAP AC Switching Characteristics table Modified the ZQ pin definition as follows Alternately this pin can be connected directly to Vppq which enables the minimum impedance mode Included Maximum Ratings for Supply Voltage on Vppq Relative to GND Changed the Maximum Ratings for DC Input Voltage from Vppq to Vpp Modified the Description of lx from Input Load current to Input Leakage Current on page 13 Modified test condition in note 14 from VDDQ lt Vpp to VDDQ lt Vpp Updated the Ordering Information table and replaced the Package Name Column with Package Diagram Page 18 of 18 Feedback
24. ry 7 Di17 0 e 18 Address Register Memory Array Write Add Decode Write Write gt Data Reg gt Data Reg 256Kx18 256Kx18 gt Read Data Reg Address Register Memory o gt Array Control Read Add Decode Vref WPS BWS BWS Document 38 05625 Rev A 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 23 2006 Feedback pe CYPRESS CY7C1302DV25 PERFORM Selection Guide CY7C1302DV25 167 Unit Maximum Operating Frequency 167 MHz Maximum Operating Current 500 mA Pin Configuration 165 ball FBGA 13 x 15 x 1 4 mm Pinout CY7C1302DV25 512K x 18 1 2 3 4 5 6 7 8 9 10 11 A NC Gnd 144M NC 36M WPS BWS K NC RPS NC 18M Gnd 72M NC B NC a9 D9 A NC K BWS A NC NC Q8 c NC NC D10 VSS A A A VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS A A A VSS NC NC D1 P NC
25. st Conditions 2 1 25V 50Q TDO ALL INPUT PULSES 2 5V a GND i trh TL D E a S a Test Clock o TCK a t TCYC ttuss m tTMsH gt Test Mode Select _ TMS Test Data In TDI Test Data Out TDO LAN BCEA trois aa t TDIH r G OU ttpox trpov Identification Register Definitions Value Instruction Field CY7C1302DV25 Description Revision Number 31 29 000 Version number Cypress Device ID 28 12 01011010010010110 Defines the type of SRAM Cypress JEDEC ID 11 1 00000110100 Allows unique identification of SRAM vendor ID Register Presence 0 1 Indicate the presence of an ID register Document 38 05625 Rev A Page 10 of 18 Feedback CY PRESO CY7C1302DV25 PERFORM Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input Output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the Input Output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the Inp
26. t Clock Input The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q 17 9 when in single clock mode All accesses are initiated on the rising edge of K K Input Clock Negative Input Clock Input K is used to capture synchronous inputs being presented to the device and to drive out data through Q 17 9 when in single clock mode ZQ Input Output Impedance Matching Input This input is used to tune the device outputs to the system data bus impedance Qj17 0 output impedance is set to 0 2 x RQ where RQ is a resistor connected between ZQ and ground Alternately this pin can be connected directly to Vppo which enables the minimum impedance mode This pin cannot be connected directly to GND or left unconnected TDO Output TDO for JTAG TCK Input TCK pin for JTAG TDI Input TDI pin for JTAG TMS Input TMS pin for JTAG NC 18M N A Address expansion for 18M This is not connected to the die and so can be tied to any voltage level NC 36M N A Address expansion for 36M This is not connected to the die and so can be tied to any voltage level GND 72M Input Address expansion for 72M This must be tied LOW GND 144M Input Address expansion for 144M This must be tied LOW NC N A Not connected to the die Can be tied to any voltage level VREF Input Reference Voltage Input Static input used to set the reference level for HSTL inputs and Outputs Reference as well as AC measurement points Vop Powe
27. the instruction register This register is loaded when it is placed between the Document 38 05625 Rev A CY7C1302DV25 TDI and TDO pins as shown in TAP Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between TDI and TDO pins This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM Several no connect NC pins are also included in the scan register to reserve pins for higher density devices The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instruc
28. this mode of operation the user must tie C and C HIGH at power up This function is a strap option and not alterable during device operation Concurrent Transactions The Read and Write ports on the CY7C1302DV25 operate completely independently of one another Since each port latches the address inputs on different clock edges the user can Read or Write to any location regardless of the trans action on the other port Also reads and writes can be started in the same clock cycle If the ports access the same location at the same time the SRAM will deliver the most recent infor mation associated with the specified address location This includes forwarding data from a Write cycle that was initiated on the previous K clock rise Depth Expansion The CY7C1302DV25 has a Port Select input for each port This allows for easy depth expansion Both Port Selects are sampled on the rising edge of the Positive Input Clock only K Each port select input can deselect the specified port Deselecting a port will not affect the other port All pending transactions Read and Write will be completed prior to the device being deselected Programmable Impedance An external resistor RQ must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output driver impedance The value of RQ must be 5X the value of the intended line impedance driven by the SRAM The allowable range of RQ to guarantee impedance matching with a
29. tolerance of 15 is between 175Q and 3509 with Vppq 1 5V The output impedance is adjusted every 1024 cycles to account for drifts in supply voltage and temperature Nn RPS BUS WPS MASTER CPU or BWs Source K ASIC source ke LAA Delayed K AVV Delayed K MVV R R 50ohms vt Vddq 2 Note 1 The above application shows 4 QDR I being used Document 38 05625 Rev A Page 4 of 18 ee 9 wee CYPREDSo PERFORM Truth Table 3 4 5 6 7 RY CY7C1302DV25 Operation K RPS WPS DQ DQ Write Cycle L H X L D A 0 at K t T D A 1 at K t t Load address on the rising edge of K clock input write data on K and K rising edges Read Cycle L H L X Q A 0 at C t 1 Q A 1 at C t 1 7 Load address on the rising edge of K clock wait one cycle read data on 2 consecutive C and C rising edges NOP No Operation L H H H D X D X Q High Z Q High Z Standby Clock Stopped Stopped X X Previous State Previous State Write Cycle Descriptions BWS BWS K K Comments L L L H During the Data portion of a Write sequence both bytes D 17 9 are written into the device L L L H __ During the Data portion of a Write sequence both bytes Dj47 0 are written into the device H L H During the Data portion of a Write sequence only the lower byte Djg o is written into the device Di17 9
30. ut Output ring contents Places the boundary scan register between TDI and TDO Does not affect the SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operation Document 38 05625 Rev A Page 11 of 18 Feedback CYPRESS CY7C1302DV25 PERFORM Boundary Scan Order Bit Bump ID Bit Bump ID Bit Bump ID Bit Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95 1N 15 9M 42 11B 69 3D 96 2M 16 9N 43 11C 70 3C 97 3P 17 11L 44 9B 71 1D 98 2N 18 11M 45 10B 72 2C 99 2P 19 9L 46 11A 73 3E 100 1P 20 10L 47 Internal 74 2D 101 3R 21 11K 48 9A 75 2E 102 4R 22 10K 49 8B 76 1E 103 4P 23 9J 50 7C 77 2F 104 5P 24 9K 51 6C 78 3F 105 5N 25 10J 52 8A 79 1G 106 5R 26 11J 53 7A 80 1F Document 38 05625 Rev A Page 12 of 18 Feedback
31. z Clock C and C Rise to High Z Active to High Z 3 24 2 5 ns terz telz Clock C and C Rise to Low z 3 4 1 2 ns Notes 23 tchz telz are specified with a load capacitance of 5 pF as in b of AC Test Loads Transition is measured 100 mV from steady state voltage 24 At any given voltage and temperature toyz is less than tcz and toyz less than tco Document 38 05625 Rev A Page 15 of 18 Feedback S CYPRESS CY7C1302DV25 PERFORM Switching Waveforms 26 27 I READ WRITE READ WRITE READ WRE NOP WRITE NOP DONT cARE XM UNDEFINED 25 Q00 refers to output from address AO Q01 refers to output from the next internal burst address following AO i e AO 1 26 Outputs are disabled High Z one clock cycle after a NOP 27 In this example if address A2 A1 then data Q20 D10 and Q21 D11 Write data is forwarded immediately as read results This note applies to the whole diagram Document 38 05625 Rev A Page 16 of 18 Feedback CYPRESS PERFORM Ordering Information CY7C1302DV25 Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered CY7C1302DV25 167BZXI 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead free Speed Package Operating MHz Ordering C
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