Cypress CY7B9911V User's Manual
Contents
1. PERFORM Features m All output pair skew lt 100 ps typical 250 max m 3 75 to 110 MHz output operation m User selectable output functions a Selectable skew to 18 ns o Inverted and non inverted a Operation at 1 and 1 4 input frequency a Operation at 2x and 4x input frequency input as low as 3 75 MHz m Zero input to output delay m 50 duty cycle outputs m LVTTL outputs drive 50Q terminated lines m Operates from a single 3 3V supply m Low operating current m 32 pin PLCC package m Jitter 100 ps typical CY7B9911V 3 3V RoboClock High Speed Low Voltage Programmable Skew Clock Buffer Functional Description The CY7B9911V 3 3V RoboClock High Speed Low Voltage Programmable Skew Clock Buffer LVPSCB offers user selectable control over system clock functions These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high perfor mance computer systems Each of the eight individual drivers arranged in four pairs of user controllable outputs can drive terminated transmission lines with impedances as low as 5002 They deliver minimal and specified output skews and full swing logic levels LVTTL Each output is hardwired to one of nine delay or function configurations Delay increments of 0 7 to 1 5 ns are deter mined by the operating frequency with outputs that can skew up to 6 time units from their nominal zero skew position The comp2. 3Q outputs are also skewed to compensate for varying trace delays independent of inversion on 4Q Figure 5 Frequency Multiplier with Skew Connections Document Number 38 07408 Rev D CY7B9911V 3 3V RoboClock Figure 5shows the LVPSCB configured as a clock multiplier The 3Q0 output is programmed to divide by four and is sent back to FB This causes the PLL to increase its frequency until the 3Q0 and 3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx outputs run at 80 MHz The 4Q0 and 4Q1 outputs are programmed to divide by two that results in a 40 MHz waveform at these outputs Note that the 20 and 40 MHz clocks fall simul taneously and are out of phase on their rising edge This enables the designer to use the rising edges of the frequency and 14 frequency outputs without concern for rising edge skew The 2Q0 2Q1 1Q0 and 1Q1 outputs run at 80 MHz and are skewed by programming their select inputs accordingly Note that the FS pin is wired for 80 MHz operation because that is the frequency of the fastest output Figure 6 Frequency Divider Connections Figure 6 shows the LVPSCB in a clock divider application 2Q0 is sent back to the FB input and programmed for zero skew 3Qx is programmed to divide by four 4Qx is programmed to divide by two Note that the falling edges of the 4Qx and 3Qx outputs are aligned This enables use of the rising edges of the 1 frequency and t frequency without concern for skew mismat
3. Voc LOW indicates a connection to GND and MID indicates an open connection Internal termination circuitry holds an unconnected input to Vcc 2 2 The level to be set on FS is determined by the normal operating frequency fjom of the Vco and Time Unit Generator see Nominal frequency fom always appears at 1Q0 and the other outputs when they are operated in their undivided modes see lable 2 The frequency appearing at the REF and FB inputs is fNom when the output connected to FB is undivided The frequency of the REF and FB inputs is fNoM 2 orfNoM4 when the part is configured for a frequency multiplication using a divided output as the FB input 3 When the FS pin is selected HIGH the REF input must not transition upon power up until Vcc has reached 2 8V Document Number 38 07408 Rev D Page 3 of 14 Feedback 2 CYPRESS PERFORM CY7B9911V 3 3V RoboClock Figure 1 shows the typical outputs with FB connected to a zero skew output Figure 1 The Typical Outputs with FB Connected to a Zero Skew Output FB Input REFInput 1Fx 3Fx 2Fx 4Fx N A LM 6tu am LL LH 4ty LM N A 3ty SU Ue Le ume ELLE ae io MH N A 1ty HL MH 2ty HM N A 3ty HH HL 4ty N A HM 6ty N A LL HH DIVIDED N A HH INVERT Test Mode The TEST input is a three level input In normal system operation this pin is connected to ground allowing the CY7B9911V to operate as described in Block Di
4. mA lcca Operating Current Used by Internal Circuitry Vccn Vcco Max All Com 95 mA Input Selects Open Mil Ind 100 Icon Output Buffer Current per Output Pair l Vocn Vaca Max 19 mA lout 0 mA Input Selects Open fmax PD Power Dissipation per Output Pair Vocn VccaQ Max 104 mW lout 0 mA Input Selects Open fmax Notes 5 For more information see Group A subgroup testing information 6 These inputs are normally wired to VCC GND or left unconnected actual threshold voltages vary as a percentage of VCC Internal termination resistors hold unconnected inputs at VCC 2 If these inputs are switched the function and timing of the outputs glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved Woe ICCN 4 0 11F 835 3F Z 0022FC N x 1 1 ere F frequency in MHz C capacitive load in pF Z line impedance in ohms N number of loaded outputs 0 1 or 2 FC F lt load circuit PD 22 0 61F 1550 2 7F Z 0125FC N x 1 1 See note 8 fo Document Number 38 07408 Rev D r variable definition CY7B9911V must be tested one output at a time output shorted for less than one second less than 10 duty cycle Room temperature only Total output current per output pair is approximated by the following expression that includes device current plus load current Total power dissipation per output pair is approximated by the following expressi
5. the feedback A wider range of delays is possible if the output connected to FB is also skewed Since Zero Skew tU and tU are defined relative to output Page 5 of 14 Feedback groups and the PLL aligns the rising edges of REF and FB you can create wider output skews by proper selection of the xFn inputs For example a 10 tU between REF and 3Qx is achieved by connecting 1Q0 to FB and setting 1FO 1F1 GND 3F0 MID and 3F1 High Since FB aligns at 4 tU and 3Qx skews to 6 tU a total of 10 tU skew is realized Many other configu rations are realized by skewing both the outputs used as the FB input and skewing the other outputs Figure 4 Inverted Output Connections REF Figure 4 shows an example of the invert function of the LVPSCB In this example the 4Q0 output used as the FB input is programmed for invert 4F0 4F1 HIGH while the other three pairs of outputs are programmed for zero skew When 4F0 and 4F1 are tied HIGH 4Q0 and 4Q1 become inverted zero phase outputs The PLL aligns the rising edge of the FB input with the rising edge of the REF This causes the 1Q 2Q and 3Q outputs to become the inverted outputs with respect to the REF input By selecting the output connected to FB you can have two inverted and six non inverted outputs or six inverted and two non inverted outputs The correct configuration is determined by the need for more or fewer inverted outputs 1Q 2Q and
6. Reel and Pb free Devices in the Ordering Information table Added 100 ps typical value for jitter peak B 404630 See ECN RGL Minor Change Added a note in ordering table that Pb free is in Pure Sn C 1199925 See ECN KVM AESA Added Note 23 Parts not recommended for the new design in Ordering Information table D 1286064 See ECN AESA __ Change status to final Cypress Semiconductor Corporation 2002 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection Un
7. Rise Fall Fall Different Class Outputs Ta 0 5 0 7 ns tskEWw4 Output Skew Rise Fall Nominal Divided Divided Inverted T3 171 0 5 1 0 ns tpEv Device to Device Skew 78 1 25 ns tpp Propagation Delay REF Rise to FB Rise 0 5 0 0 0 5 ns topcv Output Duty Cycle Variation 1 0 0 0 1 0 ns tpwH Output HIGH Time Deviation from 50 2 5 ns tpwe Output LOW Time Deviation from 50 3 ns toRISE Output Rise Time 27 0 15 1 0 1 5 ns tOEAIT Output Fall Time 27 0 15 1 0 1 5 ns tock PLL Lock Time 0 5 ms tR Cycle to Cycle Output RMS A 25 ps Jitter Peak to Peak 7 200 ps Document Number 38 07408 Rev D Page 9 of 14 Feedback CY7B9911V SSS CYPRESS 3 3V RoboClock Switching Characteristics 7 Option Over the Operating Rangel 1 CY7B9911V 7 Parameter Description Unit Min Typ Max fNoM Operating Clock FS LOW A 15 30 MHz Frequency in MHz FS MDU 2 25 50 FS HIGH 2 40 10 tiRPWH REF Pulse Width HIGH 5 0 ns tRPWL REF Pulse Width LOW 5 0 ns ty Programmable Skew Unit See Table 1 tsKEWPR Zero Output Matched Pair Skew XQ0 XQ1 I73 14 0 1 0 25 ns tsKEWwo Zero Output Skew All Outputs 15 0 3 0 75 ns tskEw1 Output Skew Rise Rise Fall Fall Same Class Outputs 11 0 6 1 0 ns tskEw2 Output Skew Rise Fall Nominal Inverted Divided Divided TFT3 17 1 0 1 5 ns SKEW3 Output Skew Rise Rise Fall Fall Differen
8. able 7 1F0 1F1 Three level function select inputs for output pair 1 1Q0 1Q1 See Table 2 2F0 2F1 Three level function select inputs for output pair 2 2Q0 2Q1 See Table 2 3F0 3F1 Three level function select inputs for output pair 3 3Q0 3Q1 See Table 2 4FO 4F1 Three level function select inputs for output pair 4 4Q0 4Q1 See Table 2 TEST Three level select See Test Mode on page 4 under the Block Diagram Description on page 3 1Q0 1Q1 O Output pair 1 See Table 2 2Q0 2Q1 O Output pair 2 See Table 2 3Q0 3Q1 O Output pair 3 See Table 2 4Q0 4Q1 O Output pair 4 See Table 2 VccN PWR Power supply for output drivers Veca PWR Power supply for internal circuitry GND PWR Ground Document Number 38 07408 Rev D Page 2 of 14 Feedback F CYPRESS PERFORM Block Diagram Description Phase Frequency Detector and Filter The Phase Frequency Detector and Filter blocks accept inputs from the Reference Frequency REF input and the Feedback FB input They generate correction information to control the frequency of the Voltage Controlled Oscillator VCO These blocks along with the VCO form a Phase Locked Loop PLL that tracks the incoming REF signal VCO and Time Unit Generator The VCO accepts analog control inputs from the PLL filter block It generates a frequency used by the time unit generator to create discrete time units that are selected in the skew
9. agram Description on page 3 For testing purposes any of the three level inputs can have a removable jumper to ground or be tied LOW through a 100W resistor This enables an external tester to change the state of these pins Note 4 FB connected to an output selected for zero skew that is xF1 xFO MID Document Number 38 07408 Rev D If the TEST input is forced to its MID or HIGH state the device operates with its internal phase locked loop disconnected and input levels supplied to REF directly control all outputs Relative output to output functions are the same as in normal mode In contrast with normal operation TEST tied LOW all outputs function based only on the connection of their own function select inputs xFO and xF1 and the waveform characteristics of the REF input Page 4 of 14 Feedback AA 2 PERFORM Operational Mode Descriptions CY7B9911V 3 3V RoboClock Figure 2 Zero Skew and Zero Delay Clock Driver REF SYSTEM CLOCK LENGTH L1 L2 ee Figure 2 shows the LVPSCB configured as a zero skew clock buffer In this mode the CY7B9911V is used as the basis for a low skew clock distribution tree When all the function select inputs xFO xF1 are left open each of the outputs are aligned and drive a terminated transmission line to an independent load The FB input is tied to any output in this configuration and the operating frequency ra
10. arges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 38 07408 Rev D Revised June 20 2007 Page 14 of 14 PSoC Designer Programmable System on Chip and PSoC Express are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp All other trademarks or registered trademarks referenced herein are property of the respective corporations Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an 12C system provided that the system conforms to the I C Standard Specification as defined by Philips RoboClock is a trademark of Cypress Semiconductor Corporation All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
11. ch The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs In this example the FS input is grounded to configure the device in the 15 to 30 MHz range since the highest frequency output is running at 20 MHz Figure 7 shows some of the functions that are selectable on the 3Qx and 4Qx outputs These include inverted outputs and outputs that offer divide by 2 and divide by 4 timing An inverted output enables the system designer to clock different subsystems on opposite edges without suffering from the pulse asymmetry typical of non ideal loading This function enables each of the two subsystems to clock 180 degrees out of phase but still is aligned within the skew specification The divided outputs offer a zero delay divider for portions of the system that divide the clock by either two or four and still remain within a narrow skew of the 1X clock Without this feature an external divider is added and the propagation delay of the divider adds to the skew between the different clock signals These divided outputs coupled with the Phase Locked Loop allow the LVPSCB to multiply the clock rate at the REF input by either two or four This mode enables the designer to distribute a low frequency clock between various portions of the system and then locally multiply the clock rate to a more suitable Page 6 of 14 Feedback CY7B9911V 3 FF CYPRESS 3 3V RoboClock PERFORM j frequen
12. classes of outputs Nominal multiple of tU delay Inverted 4Q0 and 4Q1 only with 4FO 4F1 HIGH and Divided 3Qx and 4Qx only in Divide by 2 or Divide by 4 mode 18 tDEV is the output to output skew between any two devices operating under the same conditions VCC ambient temperature air flow and so on 19 tODCV is the deviation of the output from a 50 duty cycle Output pulse width variations are included in tSKEW2 and tSKEW4 specifications 20 Specified with outputs loaded with 30 pF for the CY7B9911V 5 and 7 devices Devices are terminated through 50Q to VCC 2 tPWH is measured at 2 0V tPWL is measured at 0 8V 21 tORISE and tOFALL measured between 0 8V and 2 0V 22 tLOCK is the time that is required before synchronization is achieved This specification is valid only after VCC is stable and within normal operating limits This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits Document Number 38 07408 Rev D Page 10 of 14 Feedback AC Timing Diagrams REF FB Q SKEWPR tSKEWO 1 OTHERQ INVERTED Q tskEWs 4 REF DIVIDED BY 2 SKEW1 3 4 REF DIVIDED BY 4 Document Number 38 07408 Rev D SKEWPR lt tsKEWo 1 CY7B9911V 3 3V RoboClock tskEWs 4 tSKEW2 4 Page 11 of 14 Feedback CY7B9911V x f Cypress 3 3V RoboClock PERFORM Ordering Informa
13. cy while still maintaining the low skew characteristics of and four or divide by two and four at the same time This shifts the clock driver The LVPSCB performs all of the functions its outputs over a wide range or maintain zero skew between described in this section at the same time It can multiply by two selected outputs Figure 7 Multi Function Clock Driver 110 MHz 27 5 MHz DISTRIBUTION INVERTED CLOCK 27 5 MHz 110 MHz ZERO SKEW 110 MHz LOAD SKEWED 2 273 ns 4ty Zo Figure 8 Board to Board Clock Distribution Figure 8 shows the CY7B9911V connected in series to construct a zero skew clock distribution tree between boards Delays of the downstream clock buffers are programmed to compensate for the wire length that is select negative skew equal to the wire delay necessary to connect them to the master clock source approximating a zero delay clock tree Cascaded clock buffers accumulates low frequency jitter because of the non ideal filtering characteristics of the PLL filter Do not connect more than two clock buffers in a series Document Number 38 07408 Rev D Page 7 of 14 Feedback CY7 B9911V 3 3V RoboClock Maximum Ratings Output Current into Outputs LOW pp 64 mA f Static Discharge Voltage pp gt 2001V Operating outside these boundaries may affect the pe
14. ited States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all ch
15. letely integrated PLL allows external load and cancels the transmission line delay effects When this zero delay capability of the LVPSCB is combined with the selectable output skew functions you can create output to output delays of up to 12 time units Divide by two and divide by four output functions are provided for additional flexibility in designing complex clock systems When combined with the internal PLL these divide functions allow distribution of a low frequency clock that are multiplied by two or four at the clock destination This facility minimizes clock distribution difficulty enabling maximum system clock speed and flexibility Logic Block Diagram VCO AND TIME UNIT GENERATOR 4Q0 4Q1 SKEW 3Q0 3Q1 SELECT 2Q0 2F1 be MATRIX 2Q1 1F0 190 1F1 1Q1 Cypress Semiconductor Corporation Document Number 38 07408 Rev D 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised June 20 2007 Feedback Pin Configuration Pin Definitions CY7B9911V 2F0 GND 1F1 1F0 VccN 1Q0 1Q1 GND GND CY7B9911V 3 3V RoboClock Signal Name IO Description REF Reference frequency input This input supplies the frequency and timing against which all functional variations are measured FB PLL feedback input typically connected to one of the eight outputs FS Three level frequency range select See T
16. nge is selected with the FS pin The low skew specification along with the ability to drive terminated transmission lines with impedances as low as 509 enables efficient printed circuit board design Figure 3 Programmable Skew Clock Driver REF SYSTEM CLOCK LENGTH L1 L2 ee ee oe L3 lt L2 by 6 inches L4 gt L2 by 6 inches Figure 3 shows a configuration to equalize skew between metal traces of different lengths In addition to low skew between outputs the LVPSCB is programmed to stagger the timing of its outputs Each of the four groups of output pairs is programmed to different output timing Skew timing is adjusted over a wide range in small increments with the appropriate strapping of the function select pins In this configuration the 4Q0 output is sent back to FB and configured for zero skew The other three pairs of outputs are programmed to yield different skews relative to the feedback By advancing the clock signal on the longer traces or Document Number 38 07408 Rev D retarding the clock signal on shorter traces all loads receive the clock pulse at the same time In Figure 3 the FB input is connected to an output with 0 ns skew xF1 xFO MID selected The internal PLL synchronizes the FB and REF inputs and aligns their rising edges to make certain that all outputs have precise phase alignment Clock skews are advanced by 6 time units tU when using an output selected for zero skew as
17. on that includes device power dissipation plus power dissipation due to the Page 8 of 14 Feedback CY7B9911V SS CYPRESS 3 3V RoboClock PERFORM Capacitance Tested initially and after any design or process changes that may affect these parameters 9 Parameter Description Test Conditions Max Unit Cin Input Capacitance Ty 25 C f 1 MHz Vec 3 3V 10 pF Note 10 Applies to REF and FB inputs only AC Test Loads and Waveforms Figure 9 AC Test Loads and Waveforms Voc 3 0V R1 R1 100 2 0V 2 0V R2 100 Vin 1 5V Vin 1 5V CL 30 pF 0 8V 0 8V CL T Ro Includes fixture and probe capacitance 0 0V lt 1ns lt 1ns TTL ACTest Load TTL Input Test Waveform Switching Characteristics 5 Option Over the Operating Range 2 1 B CY7B9911V 5 f Parameter Description Unit Min Typ Max fNoM Operating Clock FS LOWI A 15 30 MHz Frequency in MHz FS MIDI 25 50 FS HIGHI 2 3 40 110 tRpwhH REF Pulse Width HIGH 5 0 ns tRpwWL REF Pulse Width LOW 5 0 ns ty Programmable Skew Unit See Table 1 tsKEWPR Zero Output Matched Pair Skew XQ0 XQ1 TF3 14 0 1 0 25 ns tsKEWwo Zero Output Skew All Outputs S 75 0 25 0 5 ns tskew1 Output Skew Rise Rise Fall Fall Same Class Outputs 77 0 6 0 7 ns SKEW2 Output Skew Rise Fall Nominal Inverted Divided Divided TF3 171 0 5 1 0 ns tsSKEW3 Output Skew Rise
18. rformance MIL STD 883 Method 3015 and life of the device These user guidelines are not tested Latch up Current pp gt 200 mA Storage Temperature pp 65 C to 150 C Ambient Temperature with Operating Range Power Applied pp 55 C to 125 C Range Ambient Temperature Vec Supply Voltage to Ground Potential 0 5V to 7 0V Commercial 0 to 70 3 3V 10 DC Input Voltage ppp 0 5V to 7 0V Electrical Characteristics Over the Operating Rangel ae a CY7B9911V Parameter Description Test Conditions Unit Min Max VoH Output HIGH Voltage Voc Min lop 18 mA 2 4 V VoL Output LOW Voltage Voc Min lo 35 mA 0 45 V Vin Input HIGH Voltage REF and FB inputs only 2 0 Vec V Vi Input LOW Voltage REF and FB inputs only 0 5 0 8 V VIHH Three Level Input HIGH Voltage Test FS Min lt Vcc lt Max 0 87 Vec Vcc V XFn VIMM mea Level Input MID Voltage Test FS Min lt Voc lt Max 0 47 Voc 0 53 Veco V xFn Vil Three Level Input LOW Voltage Test FS Min lt Voc lt Max 0 0 0 13 Voc V xFn lH Input HIGH Leakage Current REF and FB Vcc Max Viy Max 20 LA inputs only lit Input LOW Leakage Current REF and FB Voc Max Vy 0 4V 20 LA inputs only 1HH Input HIGH Current Test FS xFn Vin Vee 200 pA liv Input MID Current Test FS xFn Vin Vec 2 50 50 HA lite Input LOW Current Test FS xFn Vin GND 200 LA los Short Circuit Current Vec MAX Vout GND 25 only 200
19. select matrix The operational range of the VCO is determined by the FS control pin The time unit ty is determined by the operating frequency of the device and the level of the FS pin as shown in Table 1 Table 1 Frequency Range Select and ty Calculation from MHz a Approximate FSI2 j U fyom N Frequency MHz At Min Max where N Which ty 1 0 ns LOW 15 30 44 22 7 MID 25 50 26 38 5 HIGH 40 110 16 62 5 Notes CY7B9911V 3 3V RoboClock Skew Select Matrix The skew select matrix is comprised of four independent sections Each section has two low skew high fanout drivers xQ0 xQ1 and two corresponding three level function select xFO xF1 inputs Table 2 shows the nine possible output functions for each section as determined by the function select inputs All times are measured with respect to the REF input assuming that the output connected to the FB input has Oty selected Table 2 Programmable Skew Configurations Function Selects Output Functions SFT AFT SFO 4F0 200 207 300 301 400 401 LOW LOW 4ty Divide by 2 Divide by 2 LOW MID 3ty 6ty 6tu LOW HIGH 2tu 4ty 4ty MID LOW ity 2ty 2ty MID MID Oty Oty Oty MID HIGH Tty 2ty 2ty HIGH LOW 2ty 4ty 4ty HIGH MID 3ty 6ty 6ty HIGH HIGH 4ty Divide by 4 Inverted 1 For all three state inputs HIGH indicates a connection to
20. t Class Outputs TT3 77 0 7 1 2 ns tsSKEW4 Output Skew Rise Fall Nominal Divided Divided Inverted 3 17 1 2 1 7 ns tpEv Device to Device Skew 78 1 65 ns tpp Propagation Delay REF Rise to FB Rise 0 7 0 0 0 7 ns topcv Output Duty Cycle Variation 1 2 0 0 1 2 ns tpPWH Output HIGH Time Deviation from 50 3 ns tpwL Output LOW Time Deviation from 50 P0 3 5 ns toRISE Output Rise Time 27 0 15 1 5 2 5 ns TOFALL Output Fall Time 27 0 15 1 5 2 5 ns tLocK PLL Lock Time 0 5 ms tur Cycle to Cycle Output RMSTIT3 25 ps Jitter Peak 100 200 ps Notes 11 Test measurement levels for the CY7B9911V are TTL levels 1 5V to 1 5V Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified 12 Guaranteed by statistical correlation Tested initially and after any design or process changes that may affect these parameters 13 SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay is selected when all are loaded with 30 pF and terminated with 50Q to VCC 2 CY7B9911V 14 tSKEWPR is defined as the skew between a pair of outputs XQ0 and XQ1 when all eight outputs are selected for OtU 15 tSKEWO is defined as the skew between outputs when they are selected for OtU Other outputs are divided or inverted but not shifted 16 CL 0 pF For CL 30 pF tSKEWO 0 35 ns 17 There are three
21. tion Accuracy ps Ordering Code Package Type ae 500 CY7B9911V 5JC 32 Pb Plastic Leaded Chip Carrier Commercial 500 CY7B9911V 5JCT 32 Pb Plastic Leaded Chip Carrier Tape and Reel Commercial 700 CY7B9911V 7JC2 32 Pb Plastic Leaded Chip Carrier Commercial 700 CY7B9911V 7JCT23I 32 Pb Plastic Leaded Chip Carrier Tape and Reel Commercial Pb Free 500 CY7B9911V 5JXC 32 Pb Plastic Leaded Chip Carrier Commercial 500 CY7B9911V 5JXCT 32 Pb Plastic Leaded Chip Carrier Tape and Reel Commercial 700 CY7B9911V 7JXCF3 32 Pb Plastic Leaded Chip Carrier Commercial 700 CY7B9911V 7UXCT I 32 Pb Plastic Leaded Chip Carrier Tape and Reel Commercial Note 23 Parts not recommended for the new design Document Number 38 07408 Rev D Page 12 of 14 Feedback Sa CYPRESS Package Diagram CY7B9911V 3 3V RoboClock CHES MIN MAX Figure 10 32 Pin Plastic Leaded Chip Carrier J65 DIMENSIONS IN IN Document Number 38 07408 Rev D 51 85002 B Page 13 of 14 Feedback 5 CY7B9911V 7 CYPRESS 3 3V RoboClock PERFORM Document History Page Document Title CY7B9911V 3 3V RoboClock High Speed Low Voltage Programmable Skew Clock Buffer Document Number 38 07408 Orig of ae REV ECN NO Issue Date Change Description of Change ge 114350 3 20 02 DSG Change from Specification number 38 00765 to 38 07408 A 299713 See ECN RGL Added Tape and
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