Cypress CY62167EV30 User's Manual
Contents
1. i RAI NNNSN B WE XDOO tHZ0E C ITI N OE m DATA I O Notes E 22 Data IO is high impedance if OE Vj 23 If CE goes HIGH and CE goes LOW simultaneously with WE Vu the output remains in a high impedance state 24 During this period the l Os are in output state Do not apply input signals Document 38 05446 Rev E Page 7 of 14 Feedback y E CYPRESS CY62167EV30 MoBL Switching Waveforms continued Figure 8 shows CE or CE controlled write cycle waveforms 8 22 23 Figure 8 Write Cycle No 2 BHE BLE x ZZ XX som DATA I O NOTE 24 ESO VALID DATA tazoe Figure 9 shows WE controlled OE LOW write cycle waveforms 3 Figure 9 Write Cycle No 3 twe CE SS LL WLLL LLL K gt BHE BLE Qe SN I IT tewe m m tsa SS XD IAS tw E tuzwE Page 8 of 14 Document 38 05446 Rev E Feedback VypnEss CY62167EV30 MoBL PERFORM Switching Waveforms continued Figure 10 shows BHE BLE controlled OE LOW write cycle waveforms 291 Figure 10 Write Cycle No 4 twe mores OK CE SX A PZA IIA tha gt Annn tsa wmo ZEE XXX XXXD Truth Table CE CE WE OE BHE BLE Inputs Outputs Mode Power H X X X X X High Z Deselect Power Down Standby lag X L X X X X High Z Deselect Power Down Standby lag X X X X H H Hoh Z2. 3 8 m S Ss 3 S EE E TE X X i SEATING PLANE Fog a c S 3 51 85150 D Document 38 05446 Rev E Page 11 of 14 Feedback LL E CY62167EV30 MoBL PERFORM Package Diagrams continued Figure 13 48 Pin TSOP I 12 mm x 18 4 mm x 1 0 mm 51 85183 DIMENSIONS IN INCHES MM MIN MAX JEDEC MO 142 0 037 0 95 0 041 1 05 0 020 0 50 Y TP i 0 007 0 17 0 011 0 27 0 472 12 00 0 002 0 05 MEN 0724 1840 O 0006015 004 120 aech MAX 0 787 20 00 SE S EP Els 30 0 004 0 10 10 010 0 25 0 008 0 21 A N E S 0 GAUGE PLANE 0 020 0 50 0 028 0 70 51 85183 A KN Page 12 of 14 Document 38 05446 Rev E Feedback PERFORM Document History Page CY62167EV30 MoBL Document Title CY62167EV30 MoBL 16 Mbit 1M x 16 2M x 8 Static RAM Document Number 38 05446 REV ECN NO Orig of Change Submission Date Description of Change 202600 AJU 01 23 2004 New Data Sheet 463674 NXR See ECN Converted from Advance Information to Preliminary Removed L bin and 35 ns speed bin from product offering Modified Data sheet to include x8 configurability Changed ball E3 in FBGA pinout from DNU to NC Changed the Isg2 ryp value from 1 3 yA to 1 5 pA Changed the Icc max value from 40 mA to 25 mA Changed Vcc Stabilization time in footnote 9 from 100 u
3. Device AC operation assumes a 100 us ramp time from 0 to Vcc min and 200 us wait time after Vcc stabilization 9 Under DC conditions the device meets a Vu of 0 8V However in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0 7V This is applicable to TSOP package only 10 Only chip enables CE and CE3 byte enables BHE and BLE and BYTE must be tied to CMOS levels to meet the lg lccpg spec Other inputs can be left floating Document 38 05446 Rev E Page 3 of 14 Feedback CY62167EV30 MoBL PERFORM Thermal Resistance Tested initially and after any design or process changes that may affect these parameters Parameter Description Test Conditions 6 E E RIS 6 y R m TSOP Unit Still Air soldered on a 3 x 4 5 inch 27 74 55 60 C W Thermal Resistance OJA Junction to Ambient two layer printed circuit board Oe Thermal Resistance 9 84 16 4 3 C W Junction to Case Shaded areas contain preliminary information Figure 3 AC Test Loads and Waveforms ALL INPUT PULSES R1 Voc Veo 3 S 90 OUTPUT GND 10 90 10 lt x Fall Time 1 V ns R2 Rise Time 1 V ns 30 pF md JIG AND Equivalent to TH VENIN a OUTPUTe V Parameters 2 2V to 2 7V 2 7V to 3 6V Unit R1 16667 1103 Q R2 15385 1554 Q Ryu 8000 645 Q VTH 1 20 1 75 V Data Re
4. and Byte Low Enable are disabled BHE BLE HIGH or a write operation is in progress CE4 LOW CE HIGH and WE LOW To write to the device take Chip Enables CE LOW and CE HIGH and Write Enable WE input LOW If Byte Low Enable BLE is LOW then data from I O pins l Og through 1 07 is written into the location specified on the address pins Ag through A49 If Byte High Enable BHE is LOW then data from the I O pins 1 Og through l O45 is written into the location specified on the address pins Ag through A49 To read from the device take Chip Enables CE LOW and CE gt HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH If Byte Low Enable BLE is LOW then data from the memory location specified by the address pins appears on 1 Oy to 1 07 If Byte High Enable BHE is LOW then data from memory appears on l Og to l O45 See the Truth Table on page 9 for a complete description of read and write modes For best practice recommendations refer to the Cypress application note AN1064 SRAM System Guidelines Logic Block Diagram DATA IN DRIVERS A Aun i lt TE A g gt A 8 A 7 Ae A 5 A 4 Aa A 2 gt A 1 a ROW DECODER 1M x 16 2M x 8 RAM Array ml O 107 SENSE AMPS a gt Og lO 45 A q COLUMN DECODER ZS
5. CE LOW and CE HIGH to Data Valid 45 ns tpoE OE LOW to Data Valid 22 ns tizoE OE LOW to LOW 219 5 ns luzoE OE HIGH to High zl16 17 18 ns lizcE CE LOW and CE HIGH to Low Z 16l 10 ns thzce CE HIGH and CE LOW to High ZU 17 18 ns tru CE LOW and CE HIGH to Power Up 0 ns tpp CE HIGH and CE LOW to Power Down 45 ns tpgE BLE BHE LOW to Data Valid 45 ns tizBE BLE BHE LOW to Low Z 6l 10 ns tuzpE BLE BHE HIGH to HIGH ZU 17 18 ns WRITE CYCLE twc Write Cycle Time 45 ns tsce CE LOW and CE HIGH to Write End 35 ns taw Address Setup to Write End 35 ns tha Address Hold from Write End 0 ns tsa Address Setup to Write Start 0 ns towe WE Pulse Width 35 ns tew BLE BHE LOW to Write End 35 ns tsp Data Setup to Write End 25 ns tup Data Hold from Write End 0 ns thawe WE LOW to High z 17 18 ns tLZWE WE HIGH to Low Z 16l 10 ns Notes 14 Test conditions for all parameters other than tri state parameters assume signal transition time of 1 V ns timing reference levels of Vcc typ 2 input pulse levels of 0 to Vcc typ and output loading of the specified lo Tou as shown in AC Test Loads and Waveforms on page 4 15 AC timing parameters are subject to byte enable signals BHE or BLE not switching when chip is disabled See application note AN13842 for further clarification 16 At any temperature and voltage condition tyzcg is less than tj zcg tuzpg is less than t zgg tuzog is less than tj zog and tyzwe is less than tj zyyg for an
6. Deselect Power Down Standby lag L H H L L L Data Out l Og l O 5 Read Active lcc L H H L H L Data Out l Og 1 O Read Active Icc High Z l Og 1 O45 L H H L L H High Z l Og 1I O7 Read Active lcc Data Out l Og 1 O45 L H H H L H JHighZ Output Disabled Active loc L H H H H L HighZ Output Disabled Active loc L H H H L L HighZ Output Disabled Active loc L H L X L L Data In 1 O 1 045 Write Active Icc L H L X H L Data In l Og l Oz Write Active lcc High Z 1 Og 1 045 L H L X L H High Z l Og 1 O Write Active lcc Data In l Og 1 O45 Document 38 05446 Rev E Page 9 of 14 Feedback F CYPRESS CY62167EV30 MoBL PERFORM Ordering Information Speed Package Operating ns Ordering Code Diagram Package Type Range 45 CY62167EV30LL 45BAXI 001 13297 48 ball VFBGA 6 x 7 x 1 mm Pb free Industrial CY62167EV30LL 45BVI 51 85150 48 ball VFBGA 6 x 8 x 1 mm CY62167EV30LL 45BVXI 51 85150 48 ball VFBGA 6 x 8 x 1 mm Pb free CY62167EV30LL 45ZXI 51 85183 48 pin TSOP Pb free CY62167EV30LL 45ZXA 51 85183 48 pin TSOP Pb free Automotive A Shaded areas contain preliminary information Please contact your local Cypress sales representative for availability of t
7. E we CYPRESS PERFORM Features m TSOP Package Configurable as 1M x 16 or 2M x 8 SRAM m Very High Speed 45 ns m Temperature Ranges a Industrial 40 C to 85 C a Automotive A 40 C to 85 C m Wide Voltage Range 2 20V to 3 60V m Ultra Low Standby Power a Typical standby current 1 5 pA a Maximum standby current 12 uA Ultra Low Active Power a Typical active current 2 2 mA f 1 MHz m Easy Memory Expansion with CE4 CE and OE Features m Automatic Power Down when Deselected m CMOS for Optimum Speed and Power m Offered in Pb free 48 Ball VFBGA and 48 Pin TSOP I Packages Functional Description The CY62167EV30 is a high performance CMOS static RAM organized as 1M words by 16 bits or 2M words by 8 bits This device features an advanced circuit design that provides an ultra CY62167EV30 MoBL 16 Mbit 1M x 16 2M x 8 Static RAM low active current Ultra low active current is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling Place the device into standby mode when deselected CE HIGH or CE LOW or both BHE and BLE are HIGH The input and output pins Oe through l O45 are placed in a high impedance state when the device is deselected CE HIGH or CE LOW outputs are disabled OE HIGH both Byte High Enable
8. EI lt lt A44 gt CE MHIL BHE I BLE PowerDown d Circuit 2S lt lt BYTE b BHE CLER WE CE ae Li Ec qa OE BLE ii lt lt Cypress Semiconductor Corporation Document 38 05446 Rev E 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 23 2009 Feedback ES CYPRESS CY62167EV30 MoBL PERFORM Pin Configuration Figure 1 48 Ball VFBGA 6 x 7 x 1mm 6 x 8 x 1mm Top View 3 DELAS a GHC EQ CACHE 8 0 2 Cer toe 8 te o Ce iege y E C9 COA As URES DEA 1 SCOSOOJ Figure 2 48 Pin TSOP I Top View O 1 2 3 4 5 6 7 8 9 Product Portfolio Power Dissipation Product Range Vcc Range V opns Operating Icc mA Standby Isp2 f21MHz f fax Min Typ Max Typ Max Typ Max Typ Max CY62167EV30LL Industrial Auto A 2 2 3 0 3 6 45 2 2 4 0 25 30 1 5 12 Notes 1 The information related to 6 x 7 x 1 mm VFBGA package is preliminary 2 Ball H6 for the VFBGA package can be used to upgrade to a 32M density 3 NC pins are not connected on the die 4 The BYTE pin in the 48 TSOPI package has to be tied to Vcc to use the device as a 1M X 16 SRAM The 48 TSOPI package can also be used as a 2M X 8 SRA
9. M by tying the BYTE signal to Vas In the 2M x 8 configuration Pin 45 is A20 while BHE BLE and lOg to 1044 pins are not used 5 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Voc Vcc typ Ta 25 C Document 38 05446 Rev E Page 2 of 14 Feedback 2 CYPRESS CY62167EV30 MoBL PERFORM Maximum Ratings DC Input Voltagel 7 0 3V to 3 9V Vcc max 0 3V F Output Current into Outputs LOW 20 mA Exceeding the maximum ratings may impair the useful life of the MN device These user guidelines are not tested Static Discharge Voltage 22001V MIL STD 883 Method 3015 Storage Temperature 65 C to 150 C Latch up Current 2200 mA Ambient Temperature with Power Applied sss 55 C to 125 C Operating Range Supply Voltage to Ground Ambient Potential 1111111121 0 3V to 3 9V Vec may 0 3V Device Range temperature Vcc DC Voltage Applied to Outputs CY62167EV30LL Industrial 40 Cto 85 C 2 2V to 3 6V in High Z Statel 7 0 3V to 3 9V Vcc max 0 3V Auto A Electrical Characteristics Over the Operating Range RE 45 ns Industrial Auto A Parameter Description Test Conditions 5 Unit Min
10. Typ Max Vou Output HIGH Voltage 2 2 lt Voc 2 7 lop 0 1 mA 2 0 V 2 7 lt Voc 3 6 lop 1 0 mA 2 4 V VoL Output LOW Voltage 2 2 lt Vec 2 7 loy 0 1 mA 0 4 V 2 7 lt Voc 3 6 lo 2 1mA 0 4 V Vin Input HIGH Voltage 2 2 lt Vcc 2 7 1 8 Vec 0 3V V 2 7 lt Voc lt 3 6 2 2 Vcec 0 3V V Vu Input LOW Voltage 2 2 Vec 2 7 0 3 0 6 V 2 7 lt Voc 3 6 For VFBGA package 0 3 0 8 V For TSOP I package 0 3 0 7191 V lix Input Leakage Current GND lt Vj lt Vee 1 1 HA loz Output Leakage Current GND lt Vo lt Vcc Output Disabled 1 1 HA lec Vec Operating Supply f fmax 1 tre Vec Vcc max 25 30 mA Current z lour 0 mA f 1 MHz CMOS levels 2 2 4 0 mA Isp4 Automatic CE Power Down CE gt Vcc 0 2V or CE 0 2V 1 5 12 HA Current CMOS Inputs Vin 2 Vcc 0 2V Vin lt 0 2V f fuax Address and Data Only f 0 OE WE BHE and BLE Vcc 3 60V Ispol l Automatic CE Power Down CE gt Vcc 0 2V or CE lt 0 2V 1 5 12 uA Current CMOS Inputs Vin gt Voc 0 2V or Vin lt 0 2V f 0 Vec 3 60V Capacitance Tested initially and after any design or process changes that may affect these parameters Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHz 10 pF Cour Output Capacitance Vcc Vecityp 10 pF Notes 6 Vi min 2 0V for pulse durations less than 20 ns 7 Vin max Vcc 0 75V for pulse durations less than 20 ns 8 Full
11. e a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 05446 Rev E Revised March 23 2009 Page 14 of 14 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document are the trademarks of their respective holders Feedback
12. hese parts Package Diagrams Figure 11 48 Ball VFBGA 6 x 7 x 1 mm 001 13297 0 20 C A1 CORNER 053 x 0 47 8 H8 0 24 0 75 B 0 16 1234556 r A bood e Y D A 000 SS T B D B OOOUO000 1 C D c 000000 A NES 7 10 p D 000000 E E 6 90 D E 000000 F D F 000000 G D G 000000 D po H l H O O OO 6 6 432 1 0575 117 JW 0 775 0 93 0 50 A 48X 6 10 0 40 REF E 5 90 2 55 REF 050 90 150 c A 8 i s 0 08W C 1 17 A 0 12 C REF Po CO Ud po 0 24 C er 028 cH NOTES 1 ALL DIMENSION ARE IN MM MAX MIN 2 JEDEC REFERENCE MO 216 001 13297 A 3 PACKAGE WEIGHT 0 03g Document 38 05446 Rev E Page 10 of 14 Feedback CES PRESS CY62167EV30 MoBL PERFORM Package Diagrams continued Figure 12 48 Ball VFBGA 6 x 8 x 1 mm 51 85150 OPEN BOTTOM VIEW A1 CORNER goosm A1 CORNER pass ED 0 30 0 05 48X 12 3 4 5 6 6 5 4 3 2 n XI A i i 06 OOIO0O A B TY 00000 B 000000 c 2 D e s 000000 D Bot SE H 600090 le H F 8 000000 F G A 000000 G H 4o oi y 000 T T H n A 1875 B m 600 0 0 075 375 B 4 6004030 4 z E A 0 15 4X
13. implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems wher
14. les Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com lcd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb O Cypress Semiconductor Corporation 2004 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application
15. s to 200 us Changed the AC Test Load Capacitance value from 50 pF to 30 pF Corrected typo in Data Retention Characteristics tr from 100 us to tRC ns Changed top tj zcg han and t zy from 6 ns to 10 ns Changed tj zog from 3 ns to 5 ns Changed tuzoE tuzce tuzBe gt and tuzwE from 15 ns to 18 ns Changed tsce taw and tgw from 40 ns to 35 ns Changed tpg from 30 ns to 35 ns Changed tgp from 20 ns to 25 ns Updated 48 ball FBGA Package Information Updated the Ordering Information table B 469169 NSI See ECN Minor Change Moved to external web C 1130323 VKN See ECN Converted from preliminary to final Changed Icc max spec from 2 8 mA to 4 0 mA for f 1MHz Changed Icc typ spec from 22 mA to 25 mA for f fmax Changed Icc max spec from 25 mA to 30 mA for f fmax Added Vu spec for TSOP package and footnote 9 Added footnote 10 related to Isgo and Iccpr Changed Isp and lgg gt spec from 8 5 uA to 12 pA Changed Iccpr spec from 8 yA to 10 pA Added footnote 15 related to AC timing parameters D 1323984 VKN AESA See ECN Modified Iccpr spec for TSOP package Added 48 Ball VFBGA 6 x 7 x 1mm package Added footnote 1 related to VFBGA 6 x 7 x 1mm package Updated Ordering Information table E 2678799 VKN PYRS 03 25 2009 Added Automotive A information Document 38 05446 Rev E Page 13 of 14 Feedback CY62167EV30 MoBL PERFORM Sa
16. tention Characteristics Over the Operating Range Parameter Description Conditions Min Typ Max Unit VDR Vcc for Data Retention 1 5 V Iccpr 0 Data Retention Current Vcc 7 1 5V to 3 0V CE4 gt Vcc 0 2V CE Industrial 45ZXI 8 uA lt 0 2V Vin gt Vcc 0 2V or Vin 0 2V Auto A TSOP I Vec 1 5V CE gt Mee 0 2V CE lt 0 2V Industrial 45BAXI 10 pA Vin Voc 0 2V or Vy 0 2V Sr VFBGA teor Chip Deselect to Data 0 ns Retention Time tal 2 Operation Recovery Time tre ns Figure 4 Data Retention Waveform DATA RETENTION MODE Vor gt 1 5 V Vec min tr Voc o tcor gt CE or BHE BLE 13 or CE Notes 11 Tested initially and after any design or process changes that may affect these parameters 12 Full device operation requires linear Vgc ramp from Vpg to Vcc min gt 100 us or stable at Vcc min gt 100 us 13 BHE BLE is the AND of both BHE and BLE Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE Page 4 of 14 Document Z 38 05446 Rev E Feedback PERFORM Switching Characteristics Over the Operating Rangel 15 45 ns Industrial Auto A Parameter Description Unit Min Max READ CYCLE tre Read Cycle Time 45 ns taa Address to Data Valid 45 ns toHa Data Hold from Address Change 10 ns tace
17. y device 17 tuzoe cp hepp and tyzwe transitions are measured when the outputs enter a high impedance state 18 The internal write time of the memory is defined by the overlap of WE CE Mu BHE or BLE or both Vj and CE Vj All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE The data input setup and hold timing must refer to the edge of the signal that terminates the write Document 38 05446 Rev E Page 5 of 14 Feedback VpnEss CY62167EV30 MoBL PERFORM Switching Waveforms Figure 5 shows address transition controlled read cycle waveforms 19 20 Figure 5 Read Cycle No 1 tec ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Figure 6 shows OE controlled read cycle waveforms 9 21 Figure 6 Read Cycle No 2 ADDRESS CE CE BHE BLE A OE DATA OUT HIGH IMPEDANCE mu SESS DATA VALID Vec SUPPLY CURRENT Notes 19 The device is continuously selected OE CE Vu BHE BLE or both Vj and CE gt Vj 20 WE is HIGH for read cycle 21 Address valid before or similar to CE4 BHE BLE transition LOW and CE transition HIGH Document 38 05446 Rev E Page 6 of 14 Feedback CYPRESS CY62167EV30 MoBL PERFORM Switching Waveforms continued Figure 7 shows WE controlled write cycle waveforms 19 22 23 Figure 7 Write Cycle No 1 twe ee taw tha tsa tewe
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