Cypress CY62146EV30 User's Manual
Contents
1. 45 ns Parameter Description Min Max Unit Read Cycle tre Read Cycle Time 45 ns taa Address to Data Valid 45 ns toHA Data Hold from Address Change 10 ns tace CE LOW to Data Valid 45 ns LOW to Data Valid 22 ns tizoE OE LOW to Low Z 131 5 ns tuzoE OE HIGH to High Z 14 18 ns tizcE CE LOW to Low Z 10 ns tuzcE CE HIGH to High Z 13 141 18 ns tpu CE LOW to Power Up 0 ns tpp CE HIGH to Power Down 45 ns BLE LOW to Data Valid 22 ns tizgE BLE LOW to Low Z 113 5 ns tuzgE BLE HIGH to High Z 14 18 ns Write Cycle 15 twe Write Cycle Time 45 ns tsce CE LOW to Write End 35 ns taw Address Setup to Write End 35 ns tua Address Hold from Write End ns tsa Address Setup to Write Start 0 ns tPwE WE Pulse Width 35 ns tBw BLE BHE LOW to Write End 35 ns tsp Data Setup to Write End 25 ns tup Data Hold from Write End 0 ns tuzwE WE LOW to High z 13 141 18 ns ti zw WE HIGH to Low Z 10 ns Notes 11 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns 1V ns or less timing reference levels of 2 input pulse levels of 0 to and output loading of the specified lo as shown in the AC Test Loads and Waveforms on page 4 12 AC timing parameters are subject to byte enable signals BHE or BLE not switching when chip is disabled Please see application not2. fF G G H 1 1 875 B m 6 00 010 0 75 3 75 B 4 6 00 0 10 R CN 0 15 4 3 8 9 S X 5 q SEATING PLANE 4 2 lt gt s 51 85150 D o Document 38 05567 Rev C Page 10 of 12 CYPRESS __CY62446EV30 MOBL PERFORM Package Diagrams continued Figure 2 44 pin TSOP 51 85087 DIMENSION IN MM CINCH MIN PIN 1 LD 11938 0470 __ 10262 0404 4 EJECTOR PIN TOP VIEW BOTTOM VIEW 10 262 0 404 10058 0 356 BASE PLANE 60 396 p 5 0 210 0 0083 0120 0 00475 10 004 0 03155 9 400 0 0162 0 800 EN i 0 300 0 012 gt 18517 0 7295 0 597 0 02355 18 313 0 72D 0406 0 01605 0 0395 51 85087 1194 0 047 gt 0 99 0 150 0 0059 gt is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05567 Rev C Page 11 of 12 Cypress Semiconductor Corporation 2006 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress prod
3. P 0 r R M M W SSE 00 207 T YPRESS CY62146EV30 MoBL PERFORM Features Very high speed 45 ns Wide voltage range 2 20V 3 60V Pin compatible with CY62146DV30 Ultra low standby power Typical standby current 1 Maximum standby current 7 pA Ultra low active power Typical active current 2 mA f 1 MHz Easy memory expansion with CE and OE features Automatic power down when deselected CMOS for optimum speed and power Available in a Pb free 48 ball VFBGA and 44 pin TSOP II packages Functional Description 1 The CY62146EV30 is a high performance CMOS static RAM organized as 256K words by 16 bits This device features advanced circuit design to provide ultra low active current This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that significantly Product Portfolio 4 Mbit 256K x 16 Static RAM reduces power consumption by 80 when addresses are not toggling The device can also be put into standby mode reducing power consumption by more than 99 when deselected CE HIGH The input and output pins IOg through 1045 are placed in a high impedance state when Deselected CE HIGH Outputs are disabled OE HIGH Both Byte High Enable and Byte Low Enable are disabled BHE BLE H
4. Read Active loc L H L H L Data Out 100 10 Read Active loc lOg IO45 in High Z L H L L H Data Out lOg 1O45 Read Active lec lOg 1O in High Z L H H L L High Z Output Disabled Active loc L H H H L High Z Output Disabled Active loc L H H L H High Z Output Disabled Active loc L L X L L Data In IOg 1O45 Write Active lec L L X H L Data In 10 10 Write Active loc lOg lO4s in High Z L X L H Data In IOg lO45 Write Active lcc IO9 lO7 in High Z Ordering Information Speed Package Operating ns Ordering Code Diagram Package Type Range 45 CY62146EV30LL 45BVXI 51 85150 48 ball VFBGA Pb free Industrial CY62146EV30LL 45ZSXI 51 85087 44 pin TSOP II Pb free Please contact your local Cypress sales representa Document 38 05567 Rev C ive for availability of other parts Page 9 of 12 YPRESS CY62146EV30 MoBL PERFORM Uns Package Diagrams Figure 1 48 ball VFBGA 6 x 8 x 1 mm 51 85150 EE BOTTOM VIEW A1 CORNER 20 05 M C EGER 2025MC B 1 0 30 0 05 48X 12 345 6 6 5 4 3 2 1 1 i O OJO n B moe B c E 2 D e a 18 D 4 i le gt 8 i F g
5. continued Write Cycle No 1 WE Controlled 15 13 20 two ADDRESS tw tsi F we 3 E ASS REE 1212122 omo IKK lt luzoE gt Write Cycle No 2 CE Controlled 15 13 20 ADDRESS lt Notes 19 Data IO is high impedance if OE Vj 20 If CE goes HIGH simultaneously with WE the output remains in a high impedance state 21 During this period the IOs are in output state and input signals must not be applied Document 38 05567 Rev C Page 7 of 12 gt CYPRESS CY62146EV30 MoBL PERFORM 4 Switching Waveforms continued Write Cycle No 3 WE Controlled OE LOW 201 A tiw lt lt lt tewe _ gt tsa 3 ASK pee ud L 3 lt gt t tuzwE LZWE Write Cycle No 4 BHE BLE Controlled OE LOW 120 lt BEBE WE tHzwe tup C tsp DATAIO XX NOTE 21 XQ OOO 0 00 tLzwe Document 38 05567 Rev C Page 8 of 12 2 CYPRESS 1 CY62146EV30 MoBL PERFORM Truth Table CE WE OE BHE BLE Inputs Outputs Mode Power H X X X X High Z Deselect Power down Standby lag L X X H H High Z Output Disabled Active loc L H L L L Data Out lOg 1O45
6. 3 0 8 V lix Input Leakage Current GND lt Vi lt Vee 1 1 loz Output Leakage Current GND lt Vo lt Vcc Output Disabled 1 1 lec Vec Operating Supply Current f fmax 1 Voc Vecimax 15 20 mA Penang ze Isp1 Automatic CE Power down gt Vcc 0 2V 1 7 Current CMOS Inputs Vin gt Vcc 0 2V or Vin lt 0 2V f fmax Address and Data Only f 0 OE BLE and WE 3 60V 1 Automatic Power down CE gt Vec 0 2V 1 7 Current CMOS Inputs Vin gt Vcc 0 2V or Vin lt 0 2V f 0 Vec 3 60V Notes 5 Vit min 2 0V for pulse durations less than 20 ns 6 Vcc 0 75V for pulse durations less than 20 ns 7 Full device AC operation assumes a minimum of 100 us ramp time from 0 to V min and 200 us wait time after V stabilization 8 Only chip enable CE and byte enables and BLE need to be tied to CMOS levels to meet the 1 lt 2 spec Other inputs can be left floating Document 38 05567 Rev C Page 3 of 12 1 us 2 CYPRESS CY62146EV30 MoBL PERFORM Capacitance For All Packages 9 Parameter Description Test Conditions Max Unit Input Capacitance Ta 25 f 1 MHz 10 pF Output Capacitance Vecityp 10 pF Thermal Resistance 9 VFBGA TSOP Il Parameter
7. Description Test Conditions Package Package Unit OJA Thermal Resistance Still Air soldered on a x 4 5 inch 75 TT C W Junction to Ambient two layer printed circuit board Thermal Resistance 10 13 C W Junction to Case AC Test Loads and Waveforms R1 Vcc ALL INPUT PULSES OUTPUT 90 GND 10 30 pF T RE Rise Time 1 V ns Fall Time 1 Vins INCLUDING JIGAND 7 SCOPE Equivalent to THEVENIN EQUIVALENT RTH OUTPUT o w o V Parameters 2 50V 3 0V Unit R1 16667 1103 Q R2 15385 1554 Q RTH 8000 645 Q VTH 1 20 1 75 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ 2 Unit VDR Vcc for Data Retention 1 5 V lecpr 1 Data Retention Current Vec 1 5V CE gt 02V 0 8 7 uA VIN 2 Vcc 0 2V or ViN lt 0 2V 9 Chip Deselect to Data Retention Time 0 ns tr 10 Operation Recovery Time tre ns Data Retention Waveform DATA RETENTION MODE gt 1 5V tR Notes 9 Tested initially and after any design or process changes that may affect these parameters 10 Full device operation requires linear Vcc ramp from Vpr to Vcc min gt 100 us or stable at Vcc min gt 100 us Document 38 05567 Rev Page 4 of 12 YPRESS CY62146EV30 MoBL PERFORM Switching Characteristics Over the Operating Range 1 12
8. 5567 Rev C 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 26 2007 YPRESS CY62146EV30 MoBL PERFORM Logic Block Diagram DATA IN DRIVERS o pon 256K x 16 RAM Array lt gt 00107 Y SENSE AMPS lt gt lOg 1045 COLUMN DECODER BHE AGEE gt a ROW DECODER CE OE A44 5 A12 M A43 A44 15 A46 A47 Pin Configurations 5 4 44 pin TSOP II 48 ball VFBGA Top View Top View 4 O 44 O As 02 43 O Tm 13 42 O Az GOODS mos 410 Oe 15 40 O aE sep 7 38 1015 101 08 37 A o5 103 110 35 1042 Cs 69 Ge Ves V 12 V Ge e9 e eG BUS REDE 105 114 34 O 1049 lOs 115 O 10g 1O14 k 107 16 29 1 5 Rca e Me 19 26 Ag f 15 120 25 O Ne Ag Ag A10 A11 NC H ne 21 24 Aq 13 Notes 3 NC pins are not c
9. IGH Write operation is active CE LOW and WE LOW Write to the device by taking Chip Enable CE and Write Enable WE inputs LOW If Byte Low Enable BLE is LOW then data from IO pins through 107 is written into the location specified on the address pins Ag through A47 If Byte High Enable is LOW then data from IO pins lO through 10 5 is written into the location specified on the address pins Ag through A47 Read from the device by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH If Byte Low Enable BLE is LOW then data from the memory location specified by the address pins appear on to IO If Byte High Enable BHE is LOW then data from memory appears on lOg to 1045 See the Truth Table page 9 for a complete description of read and write modes Power Dissipation Speed Product Vcc Range V Operating mA x ns Standby Isg2 uA f 1 MHz f fmax Min Typ 2 Max Typ 2 Max Typ 2 Max Typ 2 Max CY62146EV30LL 2 2 3 0 3 6 45 ns 2 2 5 15 20 1 7 Notes 1 For best practice recommendations please refer to the Cypress application note System Design Guidelines on http www cypress com 2 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Ta 25 Cypress Semiconductor Corporation Document 38 0
10. d the package diagram 48 ball VFBGA from B to D Updated the ordering information table and replaced the Package Name column with Package Diagram Added footnote 8 related to Isp and Iccpr Added footnote 12 related AC timing parameters Page 12 of 12
11. e AN13842 for further clarification 13 At any given temperature and voltage condition tizcg is less than tj tyzpe is less than tj tyzoe is less than tj zog and tyzwe is less than tj for any given device 14 tuzoe and tyzwe transitions are measured when the outputs enter a high impedence state 15 The internal write time of the memory is defined by the overlap of WE CE Vi and or BLE All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE The data input setup and hold timing must be referenced to the edge of the signal that terminates the write Document 38 05567 Rev C Page 5 of 12 E CYPRESS CY62146EV30 MoBL PERFORM Switching Waveforms Read Cycle 1 Address Transition Controlled 16 17 ADDRESS DATA VALID PREVIOUS DATA VALID DATA OUT Read Cycle No 2 OE Controlled 17 18 ADDRESS CE teo gt tHzcE gt E tACE HIGHMPEDANCE KEK DATA VALID IMPEDANCE DATA OUT lizcE MEN tpu gt Vcc 50 50 SUPPLY lsg CURRENT Notes 16 The device is continuously selected OE CE Vi BHE and or BLE Vj 17 WE is HIGH for read cycle 18 Address valid before or similar to CE and HE BLE transition LOW Document 38 05567 Rev C Page 6 of 12 ye CYPRESS CY62146EV30 MoBL PERFORM Switching Waveforms
12. ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tyzcg from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tsp from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed from 15 to 18 ns for 35 ns Speed Bin Changed tpge from 15 to 18 ns for 35 ns Speed Bin Changed Ordering Information to include Pb Free Packages 414807 925501 Document 38 05567 Rev ZSD VKN Changed from Preliminary information to Final Changed the address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Removed 35ns Speed Bin Removed L version of CY62146EV30 Changed ball E3 from DNU to NC Removed the redundant foot note on DNU Changed Max value from 2 mA to 2 5 mA and Typ value from 1 5 mA to 2 mA at f 1 MHz Changed Typ value from 12 mA to 15 mA at f fmax Changed Isg1 and 2 Typ values from 0 7 uA to 1 uA and Max values from 2 5 to 7 pA Changed the AC test load capacitance from 50pF to 30pF on Page 4 Changed from 2 5 uA to 7 pA Added typical value Changed t zog from 3 ns to 5 ns Changed t and tj zyg from 6 ns to 10 ns Changed t from 6 ns to 5 ns Changed tyzce from 22 ns to 18 ns Changed tpyg from 30 ns to 35 ns Changed tgp from 22 ns to 25 ns Update
13. onnected on the die 4 Pins H1 G2 and H6 in the BGA package are address expansion pins for 8 Mb 16 Mb and 32 Mb respectively Document 38 05567 Rev C Page 2 of 12 CYPRESS CY62146EV30 MoBL PERFORM Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device These user guidelines are not tested Static Discharge Voltage 22001V Storage Temperature 65 to 150 C MIL STD 883 Method 3012 Ambient Temperature with Latch up Current 2200 mA Power Appli amp d ettet 55 C to 125 C Operating Range Supply Voltage to Ground Ambient uen Device Range Temperature in High Z State 5 6 0 3V to 3 9V 0 3V CY62146EV30 Industrial 40 C to 85 2 2V to 3 6V Electrical Characteristics Over the Operating Range 45 ns Parameter Description Test Conditions Min Typ 2 Unit Output HIGH Voltage 0 1 mA 2 0 V 1 0 mA gt 2 70V 2 4 V VoL Output LOW Voltage lo 0 1 mA 0 4 V lo 2 1 mA Vcc gt 2 70V 0 4 V Input HIGH Voltage Voc 2 2V to 2 7V 1 8 Vcc 0 3 V Vec 2 7V to 3 6V 2 2 0 3 V VIL Input LOW Voltage Voc 2 2V to 2 7V 0 3 0 6 V Vec 2 7V to 3 6V 0
14. ucts are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Wag YPRESS CY62146EV30 MoBL PERFORM Document History Page Document Title CY62146EV30 MoBL 4 Mbit 256K x 16 Static RAM Document Number 38 05567 REV ECN NO Issue Date Orig of Change Description of Change 223225 AJU New Data Sheet 247373 SYT Changed Advance Information to Preliminary Moved Product Portfolio to Page 2 Changed Vec stabilization time in footnote 8 from 100 us to 200 us Removed Footnote 14 4 zgg from Previous revision Changed from 2 0 uA to 2 5 uA Changed typo in Data Retention Characteristics tp from 100 us to ns Changed topa from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tuzog tuzwe from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tsce tgw from 25 to 30
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