Cypress AutoStore STK17TA8 User's Manual
Contents
1. Document 001 52039 Rev Real Time Clock Years 1FFFF ee D7 D6 D5 D4 D3 D2 D1 DO 10s Years Years Contains the lower two BCD digits of the year Lower nibble contains the value for years upper nibble contains the value for 10s of years Each nibble operates from 0 to 9 The range for the register is 0 99 Real Time Clock Months UXIEREE D7 D6 D5 D4 D3 D2 D1 DO 0 0 0 10s Month Months Contains the BCD digits of the month Lower nibble contains the lower digit and operates from 0 to 9 upper nibble one bit contains the upper digit and operates from 0 to 1 The range for the register is 1 12 Real Time Clock Date 1FFFD e D7 D6 D5 D4 D3 D2 D1 DO 0 0 10s Day of month Day of month Contains the BCD digits for the date of the month Lower nibble contains the lower digit and operates from 0 to 9 upper nibble contains the upper digit and operates from 0 to 3 The range for the register is 1 31 Leap years are automatically adjusted for Real Time Clock Day 1FFF of E D7 D6 D5 D4 D3 D2 D1 DO 0 0 0 0 0 Day of week Lower nibble contains a value that correlates to day of the week Day of the week is a ring counter that counts from 1 to 7 then returns to 1 The user must assign meaning to the day value as the day is not integrated with the date Real Time Clock Hours 1FFFB e D7 D6 D5 D4 D3 D2 D1 DO 0 0 10s Hours Hours Contain2. EZ CYPRESS STK17TA8 7 PERFORM MODE Selection E w G A16 A0 Mode y o Power Notes H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x04E38 Read SRAM Output Data 0x0B1C7 Read SRAM Output Data 0x083E0 Read SRAM Output Data Active 17 18 19 0x07C1F Read SRAM Output Data 0x0703F Read SRAM Output Data Ox08FCO Nonvolatile Store Output High Z lcc2 L H L 0x04E38 Read SRAM Output Data Active 0x0B1C7 Read SRAM Output Data 0x083E0 Read SRAM Output Data 17 18 19 0x07C1F Read SRAM Output Data 0x0703F Read SRAM Output Data 0x04C63 Nonvolatile Recall Output High Z Notes 17 The six consecutive addresses must be in the order listed W must be high during all six consecutive cycles to enable a nonvolatile cycle 18 While there are 17 addresses on the STK17TA68 only the lower 16 are used to control software modes 19 I O state depends on the state of G The I O table shown assumes G low Document 001 52039 Rev Page 11 of 23 Feedback PERFORM nvSRAM Operation The STK17TA8 nvSRAM is made up of two functional compo nents paired in the same physical cell These are the SRAM memory cell and a nonvolatile QuantumTrap cell The SRAM memory cell operates like a standard fast static RAM Data in the SRAM can be transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to SRAM the RECALL
3. STK17TA8 RFASITR Ordering Code Description ns Temperature STK17TA8 RF25 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 25 Commercial STK17TA8 RF45 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 45 Commercial STK17TA8 RF25TR 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 25 Commercial STK17TA8 RF45TR 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 45 Commercial STK17TA8 RF25l 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 25 Industrial STK17TA8 RF45l 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 45 Industrial STK17TA8 RF25ITR 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 25 Industrial 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 45 Industrial Document 001 52039 Rev Page 21 of 23 Feedback STK17TA8 a CYPRESS Package Diagrams Figure 17 48 Pin SSOP 51 85061 x Eis LUUD ILI DIMENSIHNS IN INCHES MIN MAX ON 0 620 0 630 j li SEATING PLANE 0 005 0 088 SSS et 0095 10 s 0 010 Doge 0410 r L1 iy GAUGE PLANE Pf LL B AJ 0 004 0 094 EE 0 025 cx E 0 040 BSC L 0 008 Loog o g 9 0135 0 016 51 85061 C Page 22 of 23 Document 001 52039 Rev Feedback STK17TA8 PERFORM Document History Page Document Title STK17TA8 128k X 8 AutoStore n
4. The number of time pulses are added or substracted depends upon the value loaded into the five calibration bits found in Calibration register at Ox1FFF8 Adding counts speeds the clock up subtracting counts slows the clock down The Calibration bits occupy the five lower order bits of the register These bits can be set to represent any value between 0 and 31 in binary form Bit D5 is a Sign bit where a 1 indicates positive calibration and a 0 indicates negative calibration Calibration occurs during a 64 minute period The first 62 minutes in the cycle may once per minute have one second either shortened by 128 or lengthened by 256 oscillator cycles If a binary 1 is loaded into the register only the first 2 minutes of the 64 minute cycle is modified if a binary 6 is loaded the first 12 will be affected and so on Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125 829 120 actual oscillator cycles That is 4 068 or 2 034 ppm of adjustment per calibration step in the calibration register The calibration register value is determined during system test by setting the CAL bit in the Flags register at OXTFFFO to 1 This causes the INT pin to toggle at a nominal 512 Hz This frequency can be measured with a frequency counter Any deviation measured from the 512 Hz will indicate the degree and direction of the required correction For example a reading of 512
5. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 001 52039 Rev Revised March 02 2009 Page 23 of 23 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation All products and company names mentioned in this document are the trademarks of their respective holders Feedback
6. 01024 Hz would indicate a 20 ppm error requiring a 10 001010 to be loaded into the Calibration register Note that setting or changing the calibration register does not affect the frequency test output frequency To set or clear CAL set the write bit W in the Flags register at Ox1FFFO to a 1 to enable writes to the Flag register Write a value to CAL and then reset the write bit to 0 to disable writes The default Calibration register value from the factory is 00h The user calibration value loaded is retained during a power loss Alarm The alarm function compares a user programmable alarm time date stored in registers Ox1FFF 1 5 with the real time clock time of day date values When a match occurs the alarm flag AF is set and an interrupt is generated if the alarm interrupt is enabled The alarm flag is automatically reset when the Flags register is read Each of the alarm registers has a match bit as its MSB Setting the match bit to a 1 disables this alarm register from the alarm comparison When the match bit is 0 the alarm register is compared with the equivalent real time clock register Using the match bits the alarm can occur as specifically as one particular second on one day of the month or as frequently as once per minute Note The product requires the match bit for seconds 1x1FFF2 D7 be set to 0 for proper operation of the Alarm Flag and Interrupt Document 001 52039 Rev STK17TA8 Th
7. End of Write 0 0 ns 17 taywu tAVEH tAW Address Set up to End of Write 20 30 ns 18 taywL tAVEL tas Address Set up to Start of Write 0 0 ns 19 twuax tEHAX twr Address Hold after End of Write 0 0 ns 20 Itwoz twz Write Enable to Output Disable 10 15 ns 21 twHex tow Output Active after End of Write 3 3 ns Figure 7 SRAM WRITE Cycle 1 W Controlled 9l 11 r tavav ADDRESS 19 t B el twHax ELWH E ssi MELLEL EEE BED EEE EE EEE EEE 17 n tavwH g tavwe 13 W twLwH DATA IN DATA OUT PREVIOUS DATA HIGH IMPEDANCE I tavav ADDRESS E Ww toveH met teHDx DATA IN C ATAVALID 0007 DATA OUT HIGH IMPEDANCE Notes _ 7 If W is low when E goes low the outputs remain in the high impedance state 8 E or W must be 2 V during address transitions Document 001 52039 Rev Page 7 of 23 Feedback STK17TA8 PERFORM AutoStore Power Up Recall Symbols STK17TA8 z NO Parameter Units Notes Standard Alternate Min Max 22 HRECALL Power up RECALL Duration 40 ms 9 23 STORE tui uz STORE Cycle Duration 12 5 ms 10 11 24 VswirCH Low Voltage Trigger Level 2 65 V 25 VCcCRISE Vec Rise Time 150 uS Figure 9 AutoStore Power Up RECALL STORE occurs only if a No STORE occurs SRAM write has without at least one happened SRAM write Vswrrca AutoStore POWER UP RECALL 5 i hem E THRECALL Read amp Write Inhibited DL E POWER UP BROWN OUT POWER
8. Time 25 45 ns 4 tiov toe Output Enable to Data Valid 12 20 ns 5 taxax taxax tog Output Hold after Address Change 3 3 ns 6 ter ox ttz Address Change or Chip Enable to Output Active 3 3 ns 7 tehaz thz Address Change or Chip Disable to Output 10 15 ns Inactive 8 teLax to_z Output Enable to Output Active 0 0 ns 9 tenaz toyz Output Disable to Output Inactive 10 15 ns 10 tg icc 4 tpa Chip Enable to Power Active 0 0 ns 11 teHiccH tps Chip Disable to Power Standby 25 45 ns Figure 5 SRAM READ Cycle 1 Address Controlled 4 6l ADDRESS DQ DATA OUT ADDRESS mt ol DQ DATA OUT Notes 3 W must be high during SRAM READ cycles 4 Device is continuously selected with E and G both low 5 Measured 200mV from steady state output voltage 6 HSB must remain high during READ and WRITE cycles Document 001 52039 Rev Page 6 of 23 Feedback PERFORM STK17TA8 SRAM WRITE Cycles 1 and 2 Symbols STK17TA8 25 STK17TA8 45 NO Parameter Units 1 2 Alt Min Max Min Max 11 tAVAV tAVAV twc Write Cycle Time 25 45 ns 13 twLwH tWLEH twp Write Pulse Width 20 30 ns 14 Jterwu tELEH tew Chip Enable to End of Write 20 30 ns 15 tpywH tpvEH tpw Data Set up to End of Write 10 15 ns 16 twupx tEHDX toy Data Hold after
9. high accuracy oscillator The Alarm function is programmable for one time alarms or periodic minutes hours or days alarms There is also a programmable watchdog timer for processor control Logic Block Diagram ROW DECODER g Es J il INPUT BUFFERS STATIC RAM ARRAY 1024 X 1024 1L 1I COLUMN I O COLUMN DEC LN ZN ZN ZN ZN ZN ZN Ao At Az As Ag A10 A11 Voc Vcap Quantum Trap 1024 X 1024 POWER CONTROL Vatcbat Vatccap STORE RECALL zl CONTROL HSB SOFTWARE Ki Ass A DETECT MERE Cypress Semiconductor Corporation Document 001 52039 Rev 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 02 2009 Feedback PERFORM Pinouts _ m Figure 1 Pin Diagram 48 PIn SSOP Relative PCB Area Usage Iw Voe O 1 48 O Vec Awl 2 47100 Ais Au 3 46 D ASB Q ja 4 40 w Q 7 5 44 Ais V9 Ae 6 43 As AsO 7 42 As INT 8 41 NC Ag 9 40 An NC 0 39 NC NC 1 TOP 38 NC NC 2 3700 NC Vss 3 36 0O Vss NC 4 35 NC Vatcbat 5 34 Vatccap DQo 6 330 DQ A3 7 320 G A2 8 3100 Aio Ay 9 30 E Ao O 20 290 DO DQ 21
10. the watch dog timer set a new value into the load register by writing a 0 to the watchdog write bit WDW of the watchdog register at 01x1FFF7 Then load a new value into the load register Once the new value is loaded the watchdog write bit is then set to 1 to disable watchdog writes The watchdog strobe bit WDS is then set to 1 to load this value into the watchdog timer Note Setting the load register to zero disables the watchdog timer function The system software should initialize the watchdog load register on power up to the desired value since the register is not nonvol atile Power Monitor The STK17TA8 provides a power monitor function The power monitor is based on an internal band gap reference circuit that compares the Vcc voltage to VswircH When the power supply drops below Vewitcu the real time clock circuit is switched to the backup supply battery or capacitor When operating from the backup source no data may be read or written to the nvSRAM and the clock functions are not available to the user The clock continues to operate in the background Updated clock data is available to the user turecaLL delay after VCC has been restored to the device When power is lost the PF flag in the Flags Register is set to indicate the power failure and an interrupt is generated if the power fail interrupt is enabled interrupt register 20h This line would normally be tied to the processor master reset input for pe
11. 28 DO DO 22 27 DQ Xi Q 23 26 DO XL 24 25 O Vec Pin Descriptions Pin Name IO Type Description A46 Ao Input Address The 17 address inputs select one of 131 072 bytes in the nvSRAM array or one of 16 bytes in the clock register map DQ DQgo I O Data Bi directional 8 bit data bus for accessing the nvSRAM and RTC E Input Chip Enable The active low E input selects the device W Input Write Enable The active low W enables data on the DQ pins to be written to the address location selected on the falling edge of E G Input Output Enable The active low G input enables the data output buffers during read cycles De asserting G high caused the DQ pins to tri state X Output Crystal Connection drives crystal on startup X Input Crystal Connection for 32 768 kHz crystal Vnrccap Power Supply Capacitor supplied backup RTC supply voltage Left unconnected if Vatcbat is used Vnrcbat Power Supply Battery supplied backup RTC supply voltage Left unconnected if VRTCcap is used Vcc Power Supply Power 3 0V 20 10 HSB VO Hardware Store Busy When low this output indicates a Store is in progress When pulled low external to the chip it will initiate a nonvolatile STORE operation A weak pull up resistor keeps this pin high if not connected Connection Optional INT Output Interrupt Control Can be programmed to respond to the clock alarm the watchdog timer and the power monitor Programmable to either active high push p
12. A Note The HSB pin has loy1 10uA for Voy of 2 4V this parameter is characterized but not tested Note The INT is open drain and does not source or sink high current when interrupt Register bit D3 is below Document 001 52039 Rev Page 3 of 23 Feedback EZ CYPRESS STK17TA8 7 PERFORM DC Electrical Characteristics continued Vcc 2 7V 3 6V Commercial Industrial Units Notes Symbol Parameter Min Max Min Max TA Operating Temperature 0 70 40 85 C Vec Operating Voltage 2 7 3 6 2 7 3 6 V 3 0V 20 10 VcAP Storage Capacitance 17 57 17 57 uF Between Vcap pin and Vss 5V rated NVc Nonvolatile STORE operations 200 200 K DATAg Data Retention 20 20 Years At 55 C AC Test Conditions Input Pulse Levels cene OV to 3V Input Rise and Fall Times eeeeeeeeeesee lt 5 ns Input and Output Timing Reference Levels 1 5V Output Load See Figure 2 and Figure 3 Capacitance TA 25 C f 1 0MHz 4 Symbol Parameter Max Units Conditions Cin Input Capacitance 7 pF AV 0 to 3V Cour Output Capacitance 7 pF AV 0 to 3V Figure 2 AC Output Loading 3 0V S 577 Ohms OUTPUT gt 30 pF 789 enis lt INCLUDING SCOPE AND FIXTURE Figure 3 AC Output Loading for Tristate Specs tpz ti 7 twi o7 twHaz ter ox tenaz 3 0V 577 Ohms OUTPUT gt 5pF ZESHORIE INCLUDIN
13. A M CYPRESS Features m nvSRAM Combined with Integrated Real Time Clock Functions RTC Watchdog Timer Clock Alarm Power Monitor m Capacitor or Battery Backup for RTC m 25 45 ns Read Access and Read Write Cycle Time m Unlimited Read Write Endurance m Automatic nonvolatile STORE on Power Loss m Nonvolatile STORE Under Hardware or Software Control m Automatic RECALL to SRAM on Power Up m Unlimited RECALL Cycles m 200K STORE Cycles m 20 Year nonvolatile Data Retention m Single 3 V 20 10 Power Supply m Commercial and Industrial Temperatures m 48 pin 300 mil SSOP Package RoHS Compliant STK17TA8 128k X 8 AutoStore nvSRAM with Real Time Clock Description The Cypress STK17TA8 combines a 1 Mb nonvolatile static RAM nvSRAM with a full featured real time clock in a reliable monolithic integrated circuit The 1 Mb nvSRAM is a fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell The SRAM provides the fast access and cycle times ease of use and unlimited read and write endurance of a normal SRAM Data transfers automatically to the nonvolatile storage cells when power loss is detected the STORE operation On power up data is automatically restored to the SRAM the RECALL operation Both STORE and RECALL operations are also available under software control The real time clock function provides an accurate clock with leap year tracking and a programmable
14. ADs 13 The six consecutive addresses must be read in the order listed in the Software STORE RECALL Mode Selection Table W must be high during all six consecutive cycles Document 001 52039 Rev Page 9 of 23 Feedback EE STK17TA8 PERFORM Hardware STORE Cycle Symbols STK17TA8 NO Parameter Units Notes Standard Alternate Min Max 31 tpELAv tHLaz Hardware STORE to SRAM Disabled 1 70 us 14 32 ty Hx Hardware STORE Pulse Width 15 ns Figure 12 Hardware STORE Cycle 32 thuHx Hea N J HSB OUT DQ DATA OUT SRAM Enabled SRAM Enabled Soft Sequence Commands NO Symbols Parameter STK17TA8 Units Notes Standard Min Max 33 tss Soft Sequence Processing Time 70 us 15 16 Figure 13 Soft Sequence Commands Soft Sequence Command ADDRESS 1 ADDRESS 6 ADDRESS 5 ADDRESS 1 ADDRESS Vec Notes 14 On a hardware STORE initiation SRAM operation continues to be enabled for time tDELAY to allow READ WRITE cycles to compete 15 This is the amount of time that it takes to take action on a soft sequence command Vcc power must remain high to effectively register command 16 Commands like Store and Recall lock out I O until operation is complete which further increases this time See specific command Document 001 52039 Rev Page 10 of 23 Feedback
15. D5 D4 D3 D2 D1 DO WDS WDW WDT WDS Watchdog Strobe Setting this bit to 1 reloads and restarts the watchdog timer The bit is cleared automatically once the watchdog timer is reset The WDS bit is write only Reading it always will return a 0 WDW Watchdog Write Enable Set this bit to 1 to disable writing of the watchdog time out value WDT5 WDTO This allows the user to strobe the watchdog stobe bit without disturbing the time out value Set this bit to 0 to allow bits 5 0 to be written WDT Watchdog time out selection The watchdog timer interval is selected by the 6 bit value in this register It represents a multiplier of the 32 Hz count 31 25 ms The range of time out values is 31 25 ms a setting of 1 to 2 seconds setting of 3Fh Setting the watchdog timer register to 0 disables the timer These bits can be written only if the WDW bit was cleared to 0 on a previous cycle Interrupt 1FFF i D7 D6 D5 D4 D3 D2 D1 DO WIE AIE PFIE ABE H L P L 0 0 WIE Watchdog Interrupt Enable When set to 1 and a watchdog time out occurs the watchdog timer drives the INT pin as well as setting the WDF flag When set to 0 the watchdog time out only sets the WDF flag AIE Alarm Interrupt Enable When set to 1 the alarm match drives the INT pin as well as setting the AF flag When set to 0 the alarm match only affects the AF flag PFIE Power Fail Enable When set to 1 a power failure drives the INT pin as well as setting the PF flag When set to 0 the power fail
16. G SCOPE AND FIXTURE Notes 7 2 These parameters are guaranteed but not tested Document 001 52039 Rev Page 4 of 23 Feedback PERFORM RTC DC Characteristics STK17TA8 Commercial Industrial Symbol Parameter Min Max Min Max Units Notes lsak RTC Backup Current 300 350 nA From either Vetccap OF VRTCbat VRTCbat RTC Battery Pin Voltage 1 8 3 3 1 8 3 3 V Typical 7 3 0 Volts during normal operation VRTCcap RTC Capacitor Pin Voltage 1 2 2 7 1 2 2 7 V Typical 7 2 4 Volts during normal operation toscs RTC Oscillator time to start 10 10 sec At MIN Temperature from Power up or Enable 5 5 sec At 25 C from Power up or Enable Figure 4 RTC Recommended Component Configuration Document 001 52039 Rev O AU Xi NE Recommended Values Y 32 768 KHz RF 10M Ohm C 0 install cap footprint but leave unloaded Cz 56 pF 10 do not vary from this value Page 5 of 23 Feedback PERFORM SRAM READ Cycles 1 and 2 Symbols STK17TA8 25 STK17TA8 45 NO Parameter Units 1 2 Alt Min Max Min Max 1 tei av tacs Chip Enable Access Time 25 45 ns 2 taval te gu tre Read Cycle Time 25 45 ns 3 tav ov tav ov taa Address Access
17. UP POWER DOWN RECALL AutoStore RECALL AutoStore NOTE Read and Write cycles will be ignored during STORE RECALL and while Vcc is below Vswrrcu Notes 9 tunEcALL Starts from the time Vcc rises above Vswircu 10 If an SRAM WRITE has not taken place since the last nonvolatile cycle no STORE will take place 11 Industrial Grade Devices require 15 ms MAX Page 8 of 23 Document 001 52039 Rev Feedback J CYPRESS STK17TA8 PERFORM Software Controlled STORE RECALL Cycle In the following table the software controlled STORE and RECALL cycle parameters are listed 12 15 Symbols STK17TA8 35 STK17TA8 45 NO Parameter Units Notes E Cont G Cont Alternate Min Max Min Max 26 tavav toca tre STORE RECALL Initiation Cycle 25 45 ns 13 Time 27 taveL taveL tAS Address Set up Time 0 0 ns 28 tELEH t6LGH tCW Clock Pulse Width 20 30 ns 29 tEnAx teHax Address Hold Time 1 1 ns 30 tRECALL tRECALL RECALL Duration 100 100 us Figure 10 Software STOREIRECALL Cycle E CONTROLLED 26 26 tavav tavav ADDRESS aes T 27 28 taver teen j 29 tenax i 23 30 tstore treca DQ DATA aue Figure 11 Software STORE RECALL Cycle G Controlled 26 26 tavay MM VAV ADDRESS E Ka 23 30 tstore tRecaLL DQ DATA HIGH IMPEDENC Notes 12 The software sequence is clocked on the falling edge of E controlled READs or G controlled RE
18. a software address sequence A Software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the Software STORE initiation To initiate the RECALL cycle the following sequence of E or G controlled or READ operations must be performed 1 Read Address Ox4E38 Valid READ Read Address 0xB1C7 Valid READ Read Address 0x83E0 Valid READ Read Address Ox7C1F Valid READ Read Address Ox703F Valid READ 6 Read Address 0x4C63 Initiate RECALL Cycle Internally RECALL is a two step procedure First the SRAM data is cleared and second the nonvolatile information is trans ferred into the SRAM cells After the t amp gcA cycle time the SRAM is once again be ready for READ or WRITE operations The RECALL operation in no way alters the data in the nonvol atile storage elements Data Protection The STK17TA8 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations The low voltage condition is detected when Vcc VswrrcH If the STK17TA8 is in a WRITE mode both E and W low at power up after a RECALL or after a STORE the WRITE will be inhibited until a negative transition on E or W is detected This protects against inadvertent writes during power up or brown out conditions Noise Considerations The STK17TA8 is a high speed memory and so must have a high frequency bypass capacitor of 0 1 uF connected between both Vec pins and Vss ground pl
19. ane with no plane break to chip Vss Use leads and traces that are as short as possible As with all high speed CMOS ICs careful routing of power ground and signals reduces circuit noise oR WD o aR 0 N Document 001 52039 Rev STK17TA8 Preventing AutoStore Because of the use of nvSRAM to store critical RTC data the AutoStore function cannot be disabled on the STK17TA8 Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values experience gained working with hundreds of applications has resulted in the following suggestions as best practices m The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance Incoming inspection routines at customer or contract manufacturer s sites sometimes reprogram these values Final NV patterns are typically repeating patterns of AA 55 00 FF A5 or 5A End product s firmware should not assume an NV array is in a set programmed state Routines that check memory content values to determine first time system configuration cold or warm boot status should always program a unique NV pattern for example complex 4 byte pattern of 46 E6 49 53 hex or more random bytes as part of the final system manufacturing test to ensure these system routines work consistently m Power up boot firmware routines should rewrite the nvSRAM into the desired state autost
20. ap Detail continued STK17TA8 Document 001 52039 Rev Alarm Seconds 1FFF2 ax D7 D6 D5 D4 D3 D2 D1 DO M 10s Alarm Seconds Alarm Seconds Contains the alarm value for the seconds and the mask bit to select or deselect the seconds value M Match Setting this bit to O causes the seconds value to be used in the alarm match Setting this bit to 1 causes the match circuit to ignore the seconds value Ox1FFF1 Real Time Clock Centuries D7 D6 D5 D4 D3 D2 D1 DO 10s Centuries Centuries Contains the BCD value of centuries Lower nibble contains the lower digit and operates from 0 to 9 upper nibble contains the upper digit and operates from 0 to 9 The range for the register is 0 99 centuries Flags 1FFF 5 j D7 D6 D5 D4 D3 D2 D1 DO WDF AF PF OSCF 0 CAL W R WDF Watchdog Timer Flag This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user It is cleared to 0 when the Flags register is read or on power up AF Alarm Flag This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits 0 It is cleared when the Flags register is read or on power up PF Power fail Flag This read only bit is set to 1 when power falls below the power fail threshold Vswitcu It is cleared to 0 when the Flags register is read or on power up OSCF Oscillator Fail Flag S
21. as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein
22. e alarm value should be initialized on power up by software since the alarm registers are not nonvolatile To set or clear Alarm registers set the write bit W in the Flags register at Ox1FFFO to a 1 to enable writes to the Alarm registers Write an alarm value to the alarm registers and then reset the write bit to 0 to disable writes Watchdog Timer The watchdog timer is designed to interrupt or reset the processor should the program get hung in a loop and not respond in a timely manner The software must reload the watchdog timer before it counts down to zero to prevent this interrupt or reset The watchdog timer is a free running down counter that uses the 32 Hz clock 31 25 ms derived from the crystal oscillator The watchdog timer function does no operate unless the oscillator is running The watchdog counter is loaded with a starting value from the load register and then counts down to zero setting the watchdog flag WDF and generating an interrupt if the watchdog interrupt is enabled The watchdog flag bit is reset when the flag register is read The operating software would normally reload the counter by setting the watchdog strobe bit WDS to 1 within the timing interval programmed into the load register To use the watchdog timer to reset the processor on timeout the INT is tied to processor master reset and Interrupt register is programmed to 24h to enable interrupts to pulse the reset pin on timeout To load
23. ed Exposure to absolute maximum rating conditions for extended periods may affect reliablity Commercial Industrial Units Notes Symbol Parameter Min Max Min Max loc Average Vcc Current 65 70 mA tayay 25 ns 50 55 mA tAVAV 45ns Dependent on output loading and cycle rate Values obtained without output loads lcc2 Average Vcc Current during 3 3 mA All Inputs Don t Care Vcc max STORE Average current for duration of STORE cycle tstore Icca Average Vcc Current at tayay 10 10 mA W gt Vcc 0 2V 200ns All Other Inputs Cycling at CMOS 3V 25 C Typical Levels Dependent on output loading and cycle rate Values obtained without output loads loca Average Vcap Current during 3 3 mA All Inputs Don t Care lt Emphasis gt AutoStore Cycle Average current for duration of STORE cycle tsroRE Isp Vec Standby Current 3 3 mA E 2 Vec 0 2V Standby Stable CMOS Levels All Others Viy lt 0 2V or gt Vec 0 2V Standby current level after nonvolatile cycle complete lick Input Leakage Current 1 1 mA Vcc max Vin Vss to Voc loik Off State Output Leakage Current 1 1 mA Vcc max TUM ViN Vss to Veco EorGz Vin Vin Input Logic 1 Voltage 2 0 Vec 0 5 20 Vec 0 5 V All Inputs ViL Input Logic 0 Voltage Vss 0 5 0 8 Vss 0 5 0 8 V Al Inputs Vou Output Logic 1 Voltage 24 24 V lour 2 mA except HSB VoL Output Logic 0 Voltage 0 4 0 4 V floyt 4 m
24. etto 1 on power up only if the oscillator is enabled and not running in the first 5ms of operation This indicates that RTC backup power failed and clock value is no longer valid The user must reset this bit to 0 to clear this condition CAL Calibration Mode When set to 1 a 512Hz square wave is output on the INT pin When set to 0 the INT pin resumes normal operation This bit defaults to O disabled on power up WwW Write Enable Setting the W bit to 1 freezes updates of the RTC registers and enables writes to RTC registers Alarm registers Calibration register Interrupt register and Flags register Setting the W bit to O causes the contents of the RTC registers to be transferred to the timekeeping counters if the time has been changed a new base time is loaded This bit defaults to O on power up R Read Time Set R to 1 to captures the current time in holding registers so that clock updates are not seen during the reading process Set R to 0 to enable the holding register to resume clock updates This bit defaults to 0 on power up Page 20 of 23 Feedback PERFORM Ordering Information STK17TA8 R F 45 ITR Packing Option Blank Tube TR Tape and Reel Temperature Range Blank Commercial 0 to 70 C l Industrial 45 to 85 C Access Time 25 25 ns 45 45 ns Lead Finish F 100 Sn Matte Tin ROHS Compliant Package R Plastic 48 pin 300 mil SSOP 25 mil pitch Ordering Codes STK17TA8 Access Times
25. low power condition Vec lt VswitcH an internal RECALL request is latched When Vcc once again exceeds the sense voltage of Vswitcu a RECALL cycle is automatically initiated and takes tyrecaty to complete Software STORE Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence The STK17TA8 software STORE cycle is initiated by executing sequential E controlled or G controlled READ cycles from six specific address locations in exact order During the STORE cycle previous data is erased and then the new data is programmed into the nonvol Page 12 of 23 Feedback CYPRESS PERFORM atile elements Once a STORE cycle is initiated further memory inputs and outputs are disabled until the cycle is completed To initiate the Software STORE cycle the following read sequence must be performed Read Address 0x4E38 Valid READ Read Address 0xB1C7 Valid READ Read Address 0x83E0 Valid READ Read Address 0x7C1F Valid READ Read Address 0x703F Valid READ Read Address Ox8FCO Initiate STORE Cycle Once the sixth address in the sequence has been entered the STORE cycle starts and the chip is disabled It is important that READ cycles and not WRITE cycles be used in the sequence and that G is active After the tstore cycle time has been fulfilled the SRAM is again activated for READ and WRITE operation Software RECALL Data is transferred from nonvolatile memory to the SRAM by
26. nds on the following items 1 The duty cycle of chip enable 2 The overall cycle rate for accesses 3 The ration of READs to WRITEs 4 The operating temperature 5 The VCC level 6 I O loading Page 13 of 23 Feedback PERFORM Figure 15 Current versus Cycle Time A a o A o Ww o Writes 4 o Average Active Current mA N o o 50 100 150 200 300 Cycle Time ns RTC Operations Real Time Clock The clock registers maintain time up to 9 999 years in one second increments The user can set the time to any calendar time and the clock automatically keeps track of days of the week and month leap years and century transitions There are eight registers dedicated to the clock functions which are used to set time with a write cycle and to read time during a read cycle These registers contain the Time of Day in BCD format Bits defined as 0 are currently not used and are reserved for future use by Cypress Reading The Clock The user should halt internal updates to the real time clock registers before reading clock data to prevent the reading of data in transition Stopping the internal register updates does not affect clock accuracy Write a 1 to the read bit R in the Flags register at 0x1FFFO captures the current time in holding registers Clock updates will not restart until a 0 is written to the read bit The RTC registers can then be read while the internal clock c
27. not a BCD value 0 Not implemented reserved for future use Default Settings of nonvolatile Calibration and Interrupt registers from factory Calibration Register 00h Interrupt Register 00h BCD Format Data A Register Function Range D7 D6 D5 D4 D3 D2 D1 DO Ox1FFFF 10s Years Years Years 00 99 Ox1FFFE 0 0 0 10s Months Months 01 12 Months Ox1FFFD 0 0 10s Day of Day of Month Day of Month 01 31 Month Ox1FFFC 0 0 0 0 0 Day of Week Day of week 01 07 Ox1FFFB 0 10s Hours Hours Hours 00 23 Ox1FFFA 0 10s Minutes Minutes Minutes 00 59 Ox1FFF9 0 10s Seconds Seconds Seconds 00 59 Ox1FFF8 OSCEN 0 Cal Calibration 00000 Calibration values 0 Sign Ox1FFF7 WDS WDW WDT Watchdog Ox1FFF6 WIE 0 AIE 0 PFE 0 H L P L 0 0 0 Interrupts 0 1 Ox1FFF5 M 0 10s Alarm Date Alarm Day Alarm Day of Month 01 31 Ox1FFF4 M 0 10s Alarm Hours Alarm Hours Alarm hours 00 23 Ox1FFF3 M 10 Alarm Minutes Alarm Minutes Alarm minutes 00 59 Ox1FFF2 M 10 Alarm Seconds Alarm Seconds Alarm seconds 00 59 Ox1FFF1 10s Centuries Centuries Centuries 00 99 Ox1FFFO WDF AF WI 0 R 0 Flags The User should configure to desired value at startup or during operation and the value is then retained during a power failure designates values shipped from the factory See Stopping And Starting The RTC Oscillator on page 14 Document 001 52039 Rev Page 17 of 23 Feedback STK17TA8 PERFORM Register Map Detail
28. olled WRITE It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I O lines If G is left low internal circuitry turns off the output buffers tw o7 after W goes low AutoStore Operation The STK17TA8 stores data to nvSRAM using one of three storage operations These three operations are Hardware Store Document 001 52039 Rev STK17TA8 activated by HSB Software Store activated by an address sequence and AutoStore on power down AutoStore operation a unique feature of Cypress QuanumTrap technology is a standard feature on the STK17TA8 During normal operation the device draws current from Vcc to charge a capacitor connected to the Vcap pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vswitcu the part automatically disconnects the Vcap pin from Vcc A STORE operation is initiated with power provided by the VcAp capacitor Figure 14 shows the proper connection of the storage capacitor Vcap for automatic store operation Refer to the DC Electrical Characteristics on page 3 for the size of the capacitor The voltage on the Vcap pin is driven to 5V by a charge pump internal to the chip A pull up should be placed on W to hold it inactive during power up To reduce unneeded nonvolatile stores AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken
29. ontinues to run Within 20ms after a O is written to the read bit all real time clock registers are simultaneously updated Setting The Clock Set the write bit W in the Flags register at OXTFFFO to a 1 to enable the time to be set The correct day date and time can then be written into the real time clock registers in 24 hour BCD format The time written is referred to as the Base Time This value is stored in nonvolatile registers and used in calculation of the current time Reset the write bit to 0 to transfer the time to the actual clock counters The clock starts counting at the new base time Backup Power The RTC in intended to keep time even when system power is lost When primary power Vcc drops below Vswitcu the real time clock switches to the backup power supply connected to either the Vetccap OF Vrtcbat pin The clock oscillator uses a maximum of 300 nanoamps at 2 volts to maximize the backup time available from the backup source Document 001 52039 Rev STK17TA8 You can power the real time clock with either a capacitor or a battery Factors to be considered when choosing a backup power source include the expected duration of power outages and the cost and reliability trade off of using a battery versus a capacitor If you select a capacitor power source connect the capacitor to the VRTCcap pin and leave the Vetcbat pin unconnected Capacitor backup time values based on maximum curren
30. operation This unique architecture enables all cells to be stored and recalled in parallel During the STORE and RECALL opera tions SRAM READ and WRITE operations are inhibited The STK17TA8 supports unlimited read and writes like a typical SRAM In addition it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations SRAM READ The STK17TA8 performs a READ cycle whenever E and G are low while W and HSB are high The address specified on pins Ao 1g determine which of the 131 072 data bytes are accessed When the READ is initiated by an address transition the outputs are valid after a delay of tayay READ cycle 1 If the READ is initiated by E and G the outputs are valid at te_qy or at tai ay whichever is later READ cycle 2 The data outputs repeatedly respond to address changes within the tayoy access time without the need for transitions on any control input pins and remain valid until another address change or until E or G is brought high or W and HSB is brought low Figure 14 AutoStore Mode Vcap 0 1uF SRAM WRITE A WRITE cycle is performed whenever E and W are low and HSB is high The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle The data on the common l O pins DQO 7 is written into memory if it is valid tpyyg before the end of a W controlled WRITE or tpyey before the end of an E contr
31. orded by the OSCF Oscillator Failed bit of the Flags register at address 0x1FFFO When the device is powered on Vcc goes above Vswitcu the OSCEN bit is checked for enabled status If the OSCEN bit is enabled and the oscillator is not active within the first 5 ms the OSCF bit is set The user should check for this condition and then write a 0 to clear the flag When the OSCF flag bit is set the real time clock registers are reset to the Base Time see the section Setting the Clock the value last written to the real time clock registers The value of OSCF should be reset to 0 when the real time clock registers are written for the first time This initializes the state of this bit which may have become set when the system was first powered on To reset OSCF set the write bit W in the Flags register at Ox1FFFO to a 1 to enable writes to the Flag register Write a 0 to the OSCF bit and thenreset the write bit to 0 to disable writes Page 14 of 23 Feedback PERFORM Calibrating The Clock The RTC is driven by a quartz controlled oscillator with a nominal frequency of 32 768 KHz Clock accuracy will depend on the quality of the crystal specified usually 35 ppm at 25 C This error could equate to 1 53 minutes gain or loss per month The STK17TA8 employs a calibration circuit that can improve the accuracy to 1 2 ppm at 25 C The calibration circuit adds or subtracts counts from the oscillator divider circuit
32. ore enabled and so on While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently program bugs incoming inspection routines and so on m The OSCEN bit in the Calibration register at Ox1FFF8 should be setto 1 to preserve battery life when the system is in storage see Stopping And Starting The RTC Oscillator on page 14 m The Vcap value specified in this data sheet includes a minimum and a maximum value size Best practice is to meet this requirement and not exceed the max Va value because the nvSRAM internal algorithm calculates Vc charge time based on this max Vcap value Customers that want to use a larger Vcap Value to make sure there is extra store charge and store time should discuss their Voca size selection with Cypress to understand any impact on the Veap voltage level at the end of a tRECALL period Low Average Active Power CMOS technology provides the STK17TA8 with the benefit of power supply current that scales with cycle time Less current is drawn as the memory cycle time becomes longer than 50 ns Figure 15 shows the relationship between Ico and READ WRITE cycle time Worst case current consumption is shown for commercial temperature range Vcc 3 6V and chip enable at maximum frequency Only standby current is drawn when the chip is disabled The overall average current drawn by the STK17TA8 depe
33. place since the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress Hardware STORE HSB Operation The STK17TA8 provides the HSB pin for controlling and acknowledging the STORE operations The HSB pin can be used to request a hardware STORE cycle When the HSB pin is driven low the STK17TA8 conditionally initiates a STORE operation after tpg Ay An actual STORE cycle only begins if a WRITE to the SRAM took place since the last STORE or RECALL cycle The HSB pin has a very resistive pullup and is internally driven low to indicate a busy condition while the STORE initiated by any means is in progress This pin should be externally pulled up if it is used to drive other inputs SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated After HSB goes low the STK17TA8 continues to allow SRAM operations for tpg Ay During tpg Ay multiple SRAM READ operations may take place If a WRITE is in progress when HSB is pulled low it is allowed a time tpg Ay to complete However any SRAM WRITE cycles requested after HSB goes low is inhibited until HSB returns high If HSB is not used it should be left unconnected Hardware RECALL POWER UP During power up or after any
34. rform power off reset Page 15 of 23 Feedback Interrupts The STK17TA8 has a Flags register Interrupt Register and interrupt logic that can interrupt a microcontroller or generate a power up master reset signal There are three potential interrupt sources the watchdog timer the power monitor and the clock alarm Each can be individually enabled to drive the INT pin by setting the appropriate bit in the Interrupt register In addition each has an associated flag bit in the Flags register that the host processor can read to determine the interrupt source Two bits in the Interrupt register determine the operation of the INT pin driver A functional diagram of the interrupt logic is shown below Figure 16 Interrupt Block Diagram Watchdog Timer Power Monitor INT VINT Clock Alarm Interrupt Register Watchdog Interrupt Enable WIE When set to 1 the watchdog timer drives the INT pin when a watchdog time out occurs When WIE is set to 0 the watchdog time out only sets the WDF flag bit Alarm Interrupt Enable AIE When set to 1 the INT pin is driven when an alarm match occurs When set to 0 the alarm match only sets the AF flag bit Document 001 52039 Rev STK17TA8 Power Fail Interrupt Enable PFE When set to 1 the INT pin is driven by a power fail signal from the power monitor circuit When set to 0 onl
35. s the BCD value of hours in 24 hour format Lower nibble contains the lower digit and operates from 0 to 9 upper nibble two bits contains the upper digit and operates from 0 to 2 The range for the register is 0 23 Real Time Clock Minutes 1FFFA D7 D6 D5 D4 D3 D2 D1 DO 0 10s Minutes Minutes Contains the BCD value of minutes Lower nibble contains the lower digit and operates from 0 to 9 upper nibble contains the upper minutes digit and operates from 0 to 5 The range for the register is 0 59 Real Time Clock Seconds STEERS D7 D6 D5 D4 D3 D2 D1 DO 0 10s Seconds Seconds Contains the BCD value of seconds Lower nibble contains the lower digit and operates from 0 to 9 upper nibble contains the upper digit and operates from 0 to 5 The range for the register is 0 59 Calibration BEES D7 D6 D5 D4 D3 D2 D1 DO OSCEN 0 Calibration Calibration Sign OSCEN Oscillator Enable When set to 1 the oscillator is disabled When set to 0 the oscillator is enabled Disabling the oscillator saves battery capacitor power during storage Calibration Determines if the calibration adjustment is applied as an addition 1 to or as a subtraction 0 from the time base Sign Calibration These five bits control the calibration of the clock Page 18 of 23 Feedback STK17TA8 PERFORM Register Map Detail continued Watchdog Timer 1FFF7 a D7 D6
36. t specs are shown below Nominal times are approximately three times longer Capacitor Value Backup Time 0 1 F 72 hours 0 47 F 14 days 1 0F 30 days A capacitor has the obvious advantage of being more reliable and not containing hazardous materials The capacitor is recharged every time the power is turned on so that real time clock continues to have the same backup time over years of operation If you select a battery power source connect the battery to the VRTCpat Pin and leave the VRTCcap pin unconnected A 3V lithium battery is recommended for this application The battery capacity should be chosen for the total anticipated cumulative down time required over the life of the system The real time clock is designed with a diode internally connected to the Vetcbat pin This prevents the battery from ever being charged by the circuit Stopping And Starting The RTC Oscillator The OSCEN bit in Calibration register at OX1FFF8 enables RTC oscillator operation This bit is nonvolatile and shipped to customers in the enabled state set to 0 OSCEN should be set to a 1 to preserve battery life while the system is in storage This turns off the oscillator circuit extending the battery life If the OSCEN bit goes from disabled to enabled it typically takes 5 seconds 10 seconds max for the oscillator to start The STK17TA8 has the ability to detect oscillator failure due to loss of backup power The failure is rec
37. ull or active low open drain VcAP Power Supply Autostore Capacitor Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements Vss Power Supply Ground NC No Connect Unlabeled pins have no internal connections Note 1 For detailed package size specifications See Package Diagrams on page 22 Document 001 52039 Rev Page 2 of 23 Feedback PERFORM Absolute Maximum Ratings Voltage on Input Relative to Ground 0 1V to 4 1V Voltage on Input Relative to Vas 0 5V to Vec 0 5V Voltage on DQy or HSB 0 5V to Vcg 0 5V Temperature under Bias 55 C to 125 C Junction Temperature esses 55 C to 140 C Storage Temperature sssssss 65 C to 150 C Power Dissipation se 1W DC Output Current 1 output at a time 1s duration 15mA DC Electrical Characteristics Vec 2 7V 3 6V STK17TA8 RF SSOP 48 Package Thermal Characteristics Ojo 6 2 C W Oja 51 1 Ofpm 44 7 200fpm 41 8 C W 500fpm Note Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at conditions above those indicated in the operational sections of this specification is not impli
38. ure only sets the PF flag 0 Reserved For Future Used H L High Low When set to a 1 the INT pin is driven active high When set to 0 the INT pin is open drain active low P L Pulse Level When set to a 1 the INT pin is driven active determined by H L by an interrupt source for approxi mately 200 ms When set to a 0 the INT pin is driven to an active level as set by H L until the Flags register is read Al D Ox1FFF5 es oT C M 10s Alarm Date Alarm Date Contains the alarm for the date of the month and the mask bit to select or deselect the date value M Match Setting this bit to O causes the date value to be used in the alarm match Setting this bit to 1 causes the match circuit to ignore the date value Alarm Hours 1FFF4 px D7 D6 D5 D4 D3 D2 D1 DO M 0 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value M Match Setting this bit to O causes the hours value to be used in the alarm match Setting this bit to 1 causes the match circuit to ignore the hours value Ox1FFFA4 Alarm Hours M 10s Alarm Hours Alarm Hours Contains the alarm for the hours and the mask bit to select or deselect the hours value M Match Setting this bit to O causes the hours value to be used in the alarm match Setting this bit to 1 causes the match circuit to ignore the hours value Document 001 52039 Rev Page 19 of 23 Feedback CYPRESS PERFORM Register M
39. vSRAM with Real Time Clock Document Number 001 52039 Orig of Submission a ge ECN No Change Date Description of Change 2668660 GVCH PYRS 03 04 2009 New Data Sheet Rev Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com cd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use
40. y the PF flag is set High Low H L When set to a 1 the INT pin is active high and the driver mode is push pull The INT pin can drive high only when Vcec gt Vswitcu When set to a 0 the INT pin is active low and the drive mode is open drain The active low open drain output is maintained even when power is lost Pulse Level P L When set to a 1 the INT pin is driven for approximately 200 ms when an interrupt occurs The pulse is reset when the Flags register is read When P L is set to a 0 the INT pin is driven high or low determined by H L until the Flags register is read The Interrupt register is loaded with the default value 00h at the factory The user should configure the Interrupt register to the value desired for their desired mode of operation Once configured the value is retained during power failures Flags Register The Flags register has three flag bits WDF AF and PF These flags are set by the watchdog time out alarm match or power fail monitor respectively The processor can either poll this register or enable interrupts to be informed when a flag is set The flags are automatically reset once the register is read The Flags register is automatically loaded with the value 00h on power up with the exception of the OSCF bit Page 16 of 23 Feedback CYPRESS PERFORM RTC Register STK17TA8 A binary value
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