Cypress AutoStore STK17T88 User's Manual
Contents
1. Commercial Industrial Symbol Parameter Units Notes Min Max Min Max Vou Output Logic 1 2 4 2 4 V our 2 mA Voltage VoL Output Logic 0 0 4 0 4 V four z4mA Voltage Ta Operating Temper 0 70 40 85 C ature Voc Operating Voltage 2 7 3 6 2 7 3 6 V 3 0V 20 10 Vcap Storage Capacitance 17 57 17 57 uF Between Vcap pin and Vss 5V rated NVo Nonvolatile STORE 200 200 K operations DATAR Data Retention 20 20 Years At 55 C AC Test Conditions Input Pulse Levels oe eeceeeeseeeeeeeeeeeneeeeeneeereeees OV to 3V Input Rise and Fall Times 0 eee cceeeeceeeeeeeeeseeseeeeaee lt 5ns Input and Output Timing Reference Levels 1 5V Output LOA eee eeeeeeeeeeeeeeeees See Figure 2 and Figure 3 Capacitance Symbol Parameter Max Units Conditions Cin Input Capacitance 7 pF AV 0 to 3V Court Output Capacitance 7 pF AV 0to 3V Figure 2 AC Output Loading Figure 3 AC Output Loading for Tristate Specs Tpz t 7 twLaz twHaz teLax teHaz 3 0V 3 0v 577 Ohms 577 Ohms OUTPUT gt OUTPUT gt 30 pF 5 pF 789 Ohms ikan ior INCLUDING SCOPE AND SCOPE AND FIXTURE FIXTURE Note 2 These parameters are guaranteed but not tested Document Number 001 52040 Rev A Page 4 of 22 Feedback awe oS ao CYPRESS PERFORM RTC DC Characteristics STK17T88 Commercial Industrial Sy2. ja tavav gt ADDRESS 19 ea eT Wa E Zo N ECU 17 tavwH gt 18 taw FR W twiwH DATA IN HIGH IMPEDANCE DATA OUT PREVIOUS DATA ADDRESS mi W 15 16 toveH PI EHDX ai DATA IN DATA OUT HIGH IMPEDANCE Notes _ 7 If Wis low when E goes low the outputs remain in the high impedance state 8 E or W must be gt V p during address transitions Document Number 001 52040 Rev A Page 7 of 22 Feedback J CYPRESS STK17T88 PERFORM AutoStore Power Up RECALL Symbols STK17T88 NO Parameter Units Notes Standard Alternate Min Max 22 tuRECALL Power up RECALL Duration 40 ms 9 23 tsTORE HLHZ STORE Cycle Duration 12 5 ms 10 11 24 VswitcH Low Voltage Trigger Level 2 65 V 25 VCCRISE Vec Rise Time 150 uS Figure 9 AutoStore Power Up RECALL No STORE occurs without at least one SRAM write STORE occurs only if a SRAM write has happened VswrrcH AutoStore POWER UP RECALL ee gt 22 22 e tuRECALL THRECALL Read amp Write Inhibited fof POWER UP BROWN OUT POWER UP POWER DOWN RECALL AutoStore RECALL AutoStore NOTE Read and Write cycles will be ignored during STORE RECALL and while Vcc is below Vswitcu Notes 9 tuRECALL Starts from the time Vcc rises above VgwitcH 10 If an SRAM WRITE has not taken place since the last n
3. PERFORM Features m nvSRAM Combined With Integrated Real Time Clock Functions RTC Watchdog Timer Clock Alarm Power Monitor m Capacitor or Battery Backup for RTC m 25 45 ns Read Access and R W Cycle Time m Unlimited Read Write Endurance m Automatic Nonvolatile STORE on Power Loss m Nonvolatile STORE Under Hardware or Software Control m Automatic RECALL to SRAM on Power Up m Unlimited RECALL Cycles m 200K STORE Cycles m 20 Year Nonvolatile Data Retention m Single 3V 20 10 Power Supply m Commercial and Industrial Temperatures m 48 pin 300 mil SSOP Package RoHS Compliant STK17T88 32K x 8 AutoStore nvSRAM with Real Time Clock Description The Cypress STK17T88 combines a 256 Kb nonvolatile static RAM nvSRAM with a full featured real time clock in a reliable monolithic integrated circuit The 256 Kb nvSRAM is a fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell The SRAM provides the fast access and cycle times ease of use and unlimited read and write endurance of a normal SRAM Data transfers automatically to the nonvolatile storage cells when power loss is detected the STORE operation On power up data is automatically restored to the SRAM the RECALL operation Both STORE and RECALL operations are also available under software control The real time clock function provides an accurate clock with leap year tracking and a programmable high accur
4. 3 Read address 0x03E0 Valid READ 4 Read address 0x3C1F Valid READ 5 Read address 0x303F Valid READ 6 Read address 0x0C63 Initiate RECALL cycle Internally RECALL is a two step procedure First the SRAM data is cleared and second the nonvolatile information is trans ferred into the SRAM cells After the trecart cycle time the SRAM is again ready for READ or WRITE operations The RECALL operation in no way alters the data in the nonvolatile storage elements Data Protection The STK17T88 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations The low voltage condition is detected when Voc lt VswitcH Document Number 001 52040 Rev A STK17T88 If the STK17T88 is in a WRITE mode both E and W low at power up after a RECALL or after a STORE the WRITE is inhibited until a negative transition on E or W is detected This protects against inadvertent writes during power up or brown out conditions Noise Considerations The STK17T88 is a high speed memory and so must have a high frequency bypass capacitor of 0 1 uF connected between both Vcc pins and Vgg ground plane with no plane break to chip Vss Use leads and traces that are as short as possible As with all high speed CMOS ICs careful routing of power ground and signals reduce circuit noise Preventing AutoStore Because of the use of nvSRAM to store critical RTC data the AutoStore
5. Industrial 40 to 85 C Lead Finish F 100 Sn Matte Tin ROHS Compliant Ordering Codes Package R Plastic 48 pin 330 mil SSOP Ordering Code Description Access Times ns Temperature STK17T88 RF25 3 3V 32Kx8 AutoStore nvSRAM RTC SSOP48 300 25 Commercial STK17T88 RF45 3 3V 32Kx8 AutoStore nvSRAM RTC SSOP48 300 45 Commercial STK17T88 RF25TR 3 3V 32Kx8 AutoStore nvSRAM RTC SSOP48 300 25 Commercial STK17T88 RF45TR 3 3V 32Kx8 AutoStore nyvSRAM RTC SSOP48 300 45 Commercial STK17T88 RF251 3 3V 32Kx8 AutoStore nvSRAM RTC SSOP48 300 25 Industrial STK17T88 RF451 3 3V 32Kx8 AutoStore nvSRAM RTC SSOP48 300 45 Industrial STK17T88 RF25ITR 3 3V 32Kx8 AutoStore nvSRAM RTC SSOP48 300 25 Industrial STK17T88 RF45ITR 3 3V 32Kx8 AutoStore nvSRAM RTC SSOP48 300 45 Industrial Document Number 001 52040 Rev A Page 20 of 22 Feedback STK17T88 F CYPRESS PERFORM Package Diagram Figure 16 48 Pin SSOP 51 85061 AN a U0 pp Lt asero 7 pa w i Jala Halal H GAUGE Hh a Ni 51 85061 C Page 21 of 22 Document Number 001 52040 Rev A Feedback CYPRESS STK17T88 PERFORM Document History Page Docume
6. Connect Unlabeled pins have no internal connections Note 1 For detailed package size specifications see Package Diagram on page 21 Document Number 001 52040 Rev A Page 2 of 22 Feedback CYPRESS STK17T88 PERFORM Absolute Maximum Ratings Note Stresses greater than those listed under Absolute Voltage on Input Relative to Ground 0 5V to 4 1V Maximum Ratings may cause permanent damage to the device Voltage on Input Relative to Vg 0 5V to Vcc 0 5V This is a stress rating only and functional operation of the device Hep at conditions above those indicated in the operational sections Voltage on DQ or HSB eee 0 5V to Vec 0 5V of this specification is not implied Exposure to absolute Temperature under Bias eeeeeeeeeeeeeees 55 C to 125 C maximum rating conditions for extended periods may affect Junction Temperature nasaan 55 C to 140 C reliability Storage Temperature eeeeeeeeeeeeteeeneeeeees 65 C to 150 C Power Dissipation eesceeseeeeseeeeeeneeeteneeeeeneeeeeeneeeesaeees 1W DC Output Current 1 output at a time 1s duration 15 mA RF SSOP 48 Package Thermal Characteristics Bj 6 2 C W Oja 51 1 Ofpm 44 7 200fpm 41 8 C W 500fpm DC Characteristics Vcc 2 7V 3 6V Commercial Industrial Symbol Parameter Units Notes Min Max Min Max lec Average Vcc Current 65 70 MA tavay 25 ns 50 55 mA t
7. capacitor power source connect the capacitor to the Vatccap Pin and leave the Vprcbat pin unconnected Capacitor backup time values based on maximum current specs are shown below Nominal times are approximately 3 times longer Capacitor Value Backup Time 0 1F 72 hours 0 47 F 14 days 1 0F 30 days Document Number 001 52040 Rev A STK17T88 A capacitor has the obvious advantage of being more reliable and not containing hazardous materials The capacitor is recharged every time the power is turned on so that the real time clock continues to have the same backup time over years of operation If you select a battery power source connect the battery to the Vrtcbat pin and leave the Vatccap pin unconnected A 3V lithium is recommended for this application The battery capacity should be chosen for the total anticipated cumulative down time required over the life of the system The real time clock is designed with a diode internally connected to the Vatcbat pin This prevents the battery from ever being charged by the circuit Stopping and Starting the RTC Oscillator The OSCEN bit in Calibration register at Ox7FF8 enables RTC oscillator operation This bit is nonvolatile and shipped to customers in the enabled state set to 0 OSCEN should be set to a 1 to preserve battery life while the system is in storage This turns off the oscillator circuit extending the battery life If the OSCEN bit goes from disab
8. is then retained during a power failure designates values shipped from the factory See Stopping and Starting the RTC Oscillator on page 14 Document Number 001 52040 Rev A Page 17 of 22 Feedback PERFORM STK17T88 Register Map Detail Real Time Clock Years FEE D7 D6 D5 D4 D3 D2 Di DO 10s Years Years Contains the lower two BCD digits of the year Lower nibble contains the value for years upper nibble contains the value for 10s of years Each nibble operates from 0 to 9 The range for the register is 0 99 Real Time Clock Months ORFE D7 D6 D5 D4 D3 D2 Di DO 0 Months Contains the BCD digits of the month Lower nibble contains the lower digit and operates from 0 to 9 upper nibble one bit contains the upper digit and operates from 0 to 1 The range for the register is 1 12 eal Time Clock Date Ox FED D7 D6 D5 D4 D3 D2 D1 DO 0 0 10s Day of mont ay of mont Contains the BCD digits for the date of the month Lower nibble contains the lower digit and operates from 0 to 9 upper nibble contains the upper digit and operates from 0 to 3 The range for the register is 1 31 Leap years are automatically adjusted for eal Time Clock Day Ene D7 D6 D5 D4 D3 D2 D1 DO 0 0 0 0 0 ay of wee Lower nibble contains a value that correlates to day of the week Day of the week is a ring coun
9. pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PA
10. value to be used in the alarm match Setting this bit to 1 causes the match circuit to ignore the minutes value Alarm Seconds M 10s Alarm Seconds Alarm Seconds Contains the alarm value for the seconds and the mask bit to select or deselect the seconds value Match Setting this bit to O causes the seconds value to be used in the alarm match Setting this bit to 1 causes the match circuit to ignore the seconds value eal Time Clock Centuries 10s Centuries Ceniuries Document Number 001 52040 Rev A Contains the BCD value of Centuries Lower nibble contains the lower digit and operates from 0 to 9 upper nibble contains the upper centuries digit and operates from O to 9 The range for the register is 0 99 centuries Page 19 of 22 Feedback PERFORM Register Map Detail continued STK17T88 0x7FFO Flags D7 D6 D5 D4 D3 D2 D1 DO WDF AF PF OSCF 0 CAL WwW R WDF Watchdog Timer Flag This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user It is cleared to 0 when the Flags register is read or on power up Alarm Flag This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits 0 It is cleared when the Flags register is read or on power up Power fail Flag This read only bit is set to 1 when power falls below the power fail thres
11. 3 D2 Di DO WDS WDW WDT WDS Watchdog Strobe Setting this bit to 1 reloads and restarts the watchdog timer The bit is cleared automat ically once the watchdog timer is reset The WDS bit is write only Reading it always will return a 0 Document Number 001 52040 Rev A Page 18 of 22 Feedback Register Map Detail continued STK17T88 0x7FF6 WDW Watchdog Write Enable Set this bit to 1 to disable writing of the watchdog time out value WDT5 WDTO This allows the user to strobe the watchdog without disturbing the time out value Setting this bit to O allows bits 5 0 to be written WDT Watchdog time out selection The watchdog timer interval is selected by the 6 bit value in this register It represents a multiplier of the 32 Hz count 31 25 ms The range or time out values is 31 25 ms a setting of 1 to 2 seconds setting of 3Fh Setting the watchdog timer register to 0 disables the timer These bits can be written only if the WDW bit was cleared to 0 on a previous cycle a ep L L Fa ea aa ee ee aay a GE Saga ma Sa ee E 0x7FF5 M WIE Watchdog Interrupt Enable When set to 1 and a watchdog time out occurs the watchdog timer Ties the INT pin and sets the WDF flag When set to 0 the watchdog time out only sets the WDF flag AlE Alarm Interrupt Enable When set to 1 the alarm match drives the INT pin and sets the AF flag When set to O the alarm match only sets the AF flag PFIE Power Fail
12. Data 17 18 19 Ox3C1F Read SRAM Output Data 0x303F Read SRAM Output Data 0x0C63 Nonvolatile Recall Output High Z Notes 17 The six consecutive addresses must be in the order listed W must be high during all six consecutive cycles to enable a nonvolatile cycle 18 While there are 15 addresses on the STK17T88 only the lower 13 are used to control software modes 19 I O state depends on the state of G The I O table shown assumes G low Document Number 001 52040 Rev A Page 11 of 22 Feedback PERFORM nvSRAM Operation The STK17T88 nvSRAM is made up of two functional compo nents paired in the same physical cell These are the SRAM memory cell and a nonvolatile QuantumTrap cell The SRAM memory cell operates like a standard fast static RAM Data in the SRAM can be transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to SRAM the RECALL operation This unique architecture allows all cells to be stored and recalled in parallel During the STORE and RECALL opera tions SRAM READ and WRITE operations are inhibited The STK17T88 supports unlimited read and writes like a typical SRAM In addition it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations SRAM READ The STK17T88 performs a READ cycle whenever E and G are low while W and HSB are high The address specified on pins Ao 14 determine which of the 32 768 data bytes are accessed When the
13. Enable When set to 1 a power failure drives the INT pin and sets the PF flag When set to 0 a power failure only sets the PF flag 0 Reserved for Future Use H L High Low When set to a 1 the INT pin is driven active high When set to O the INT pin is open drain active low P L Pulse Level When set to a 1 the INT pin is driven active determined by H L by an interrupt source for approximately 200 ms When set to a O the INT pin is driven to an active level as set by H L until the Flags register is read Alarm Day D7 D6 D5 D4 D3 D2 D1 DO MO 0 0sAamDae ATarm Dare Contains the alarm value for the date of the month and the mask bit to select or deselect the date value Match Setting this bit to O causes the date value to be used in the alarm match Setting this bit to 1 causes the match circuit to ignore the date value Alarm o Hours 0x7FF2 0x7 ox4FFs D7 D6 D5 D4 D3 D2 Di DO 0 10s Alarm Hours arm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value M Match Setting this bit to O causes the hours value to be used in the alarm match Setting this bit to 1 causes the match circuit to ignore the hours value Alarm Minutes Ox7FES D7 D6 D5 D4 D3 D2 Di DO M 10s Alarm Minutes Alarm Minutes Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value M Match Setting this bit to O causes the minutes
14. READ is initiated by an address transition the outputs are valid after a delay of tayoy READ cycle 1 If the READ is initiated by E and G the outputs are valid at te_qy or at teray whichever is later READ cycle 2 The data outputs repeatedly respond to address changes within the tayoy access time without the need for transitions on any control input pins and remain valid until another address change or until E or G is brought high or W and HSB is brought low Figure 13 AutoStore Mode SRAM WRITE A WRITE cycle is performed whenever E and W are low and HSB is high The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle The data on the common O pins DQ0 7 are written into memory if it is valid tpywp before the end of a W controlled WRITE or tpyey before the end of an E controlled WRITE It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I O lines If G is left low internal circuitry turns off the output buffers tw 07 after W goes low AutoStore Operation The STK17T88 stores data to nvSRAM using one of three storage operations These three operations are Hardware Store Document Number 001 52040 Rev A STK17T88 activated by HSB Software Store activated by an address sequence and AutoStore on power down AutoStore operation a unique feature of Cypress Quanum
15. RTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 52040 Rev A Revised March 17 2009 Page 22 of 22 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
16. SRAM array or one of 16 bytes in the clock register map DQ7 DQg 1 0 Data Bi directional 8 bit data bus for accessing the nvSRAM and RTC E Input Chip Enable The active low E input selects the device W Input Write Enable The active low W enables data on the DQ pins to be written to the address location selected on the falling edge of E G Input Output Enable The active low G input enables the data output buffers during read cycles De asserting G high caused the DQ pins to tri state X Output Crystal Connection drives crystal on startup Xo Input Crystal Connection for 32 768 kHz crystal VRTCcap Power Supply Capacitor supplied backup RTC supply voltage Left unconnected if Vprcbat is used VRTCbat Power Supply Battery supplied backup RTC supply voltage Left unconnected if VRTCcap IS used Vec Power Supply Power 3 0V 20 10 HSB 1 0 Hardware Store Busy When low this output indicates a Store is in progress When pulled low external to the chip it initiates a nonvolatile STORE operation A weak pull up resistor keeps this pin high if not connected Connection Optional INT Output Interrupt Control Can be programmed to respond to the clock alarm the watchdog timer and the power monitor Programmable to either active high push pull or active low open drain Vcap Power Supply Autostore Capacitor Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements Vss Power Supply Ground NC No
17. Trap technology that is a standard feature on the STK17T88 During normal operation the device draws current from Vcc to charge a capacitor connected to the Vcap pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vswitcu the part automatically disconnects the Vca p pin from Voc A STORE operation is initiated with power provided by the Vcap capacitor Figure 5 shows the proper connection of the storage capacitor Vcap for automatic store operation Refer to the DC Character istics table for the size of the capacitor The voltage on the Vcap pin is driven to 5V by a charge pump internal to the chip A pull up should be placed on W to hold it inactive during power up To reduce unneeded nonvolatile stores AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress Hardware STORE HSB Operation The STK17T88 provides the HSB pin for controlling and acknowledging the STORE operations The HSB pin can be used to request a hardware STORE cycle When the HSB pin is driven low the STK17T88 conditionally initiates a STORE operation after tpeLay An actual STORE cycle only begins if a WRITE to th
18. When set to O the alarm match only sets the AF flag bit Power Fail Interrupt Enable PFE When set to 1 the INT pin is driven by a power fail signal from the power monitor When set to O only the PF flag is set Document Number 001 52040 Rev A STK17T88 High Low H L When set to a 1 the INT pin is active high and the driver mode is push pull The INT pin can drive high only when VeesVswitcH When set to a 0 the INT pin is active low and the drive mode is open drain The active low open drain output is maintained even when power is lost Pulse Level P L When set to a 1 the INT pin is driven for approximately 200 ms when the interrupt occurs The pulse is reset when the Flags register is read When P L is set to a O the INT pin is driven high or low determined by H L until the Flags register is read The Interrupt register is loaded with the default value 00h at the factory The user should configure the Interrupt register to the value desired for their desired mode of operation Once configured the value is retained during power failures Flags Register The Flags register has three flag bits WDF AF and PF These flags are set by the watchdog time out alarm match or power fail monitor respectively The processor can either poll this register or enable the interrupts to be informed when a flag is set The flags are automatically reset once the register is read The Flags register is automatically loaded
19. acy oscillator The Alarm function is programmable for one time alarms or periodic minutes hours or days alarms There is also a programmable watchdog timer for processor control Logic Block Diagram STATIC RAM ARRAY 512X512 ROW DECODER INPUT BUFFERS Quantum Trap 512 X 512 STORE RECALL CONTROL SOFTWARE DETECT Cypress Semiconductor Corporation 198 Champion Court Document Number 001 52040 Rev A San Jose CA 95134 1709 408 943 2600 Revised March 17 2009 Feedback PERFORM Pin Configurations STK17T88 Figure 1 48 Pin SSOP Relative PCB Area Usage wy Vear 1 48 O Vec NC 2 47 NC Awl 3 46 D ASB An 4 450 W a AO 5 44 Ais O Ag 6 43 Ag 2 As 7 42 Ag NTO 8 41 NC AsO 9 40 An NC 10 39 NC nco 1 TOP 38H nc NC 12 37 NC Vss 13 36 U Vss NC 14 35 NC V RTCbat 15 34 Varccap DQO 16 33 DQ As O 17 20G A2 18 31 Ato Ai 19 30 E Ao 20 29 DQ DQ 21 28 DQs DQO 22 27 DQ Xj 23 26 DQ X2 24 250 Vec Pin Descriptions Pin Name 10 Type Description A 4 Ag Input Address The 15 address inputs select one of 32 768 bytes in the nv
20. al 512 Hz This frequency can be measured with a frequency counter Any deviation measured from the 512 Hz indicates the degree and direction of the required correction For example a reading of 512 01024 Hz would indicate a 20 ppm error requiring a 10 001010 to be loaded into the Calibration register Note that setting or changing the calibration register does not affect the frequency test output frequency To set or clear CAL set the write bit W in the Flags register at 0x7FF0 to a 1 to enable writes to the Flags register Write a value to CAL and then reset the write bit to O to disable writes The default Calibration register value from the factory is 00h The user calibration value loaded is retained during a power loss Alarm The alarm function compares a user programmed alarm time date stored in registers Ox7FF1 5 with the real time clock time of day date values When a match occurs the alarm flag AF is set and an interrupt is generated if the alarm interrupt is enabled The alarm flag is automatically reset when the Flags register is read Each of the alarm registers has a match bit as its MSB Setting the match bit to a 1 disables this alarm register from the alarm comparison When the match bit is 0 the alarm register is compared with the equivalent real time clock register Using the match bits an alarm can occur as specifically as one particular second on one day of the month or as frequently as
21. avav 45ns Dependent on output loading and cycle rate Values obtained without output loads loco Average Voc Current 3 3 mA All Inputs Don t Care Vcc max during STORE Average current for duration of STORE cycle tstore locg Average Voc Current 10 10 mA W gt Vcc 0 2V at tayay 200ns All Other Inputs Cycling at CMOS Levels 3V 25 C Typical Dependent on output loading and cycle rate Values obtained without output loads loca Average Vcap 3 3 mA All Inputs Don t Care Current during Average current for duration of STORE cycle AutoStore Cycle t5TORE Isp Voc Standby Current 3 3 mA E gt Vec 0 2V Standby Stable All Others Vjys 0 2V or 2 Vec 0 2V CMOS Levels Standby current level after nonvolatile cycle complete litK Input Leakage 1 1 LA Vcc max Current Vin Vss to Vcc loLK Off State Output 1 1 pA Vcoc max Leakage Current Vin Vss to Vcc E or G2 Vjy Vin Input Logic 1 2 0 Voc 0 5 2 0 Vcc 0 5 V All Inputs Voltage Vit Input Logic O Vss 0 5 0 8 Vss 0 5 0 8 V All Inputs Voltage Note The HSB pin has l 7 10UuA for Voy of 2 4V this parameter is characterized but not tested Note The INT is open drain and does not source or sink high current when interrupt Register bit D3 is below Document Number 001 52040 Rev A Page 3 of 22 Feedback PERFORM DC Characteristics continued Voc 2 7V 3 6V STK17T88
22. ble to Output Active 0 0 ns 9 tcHoz touz Output Disable to Output Inactive 10 15 ns 10 texicci h tPA Chip Enable to Power Active 0 0 ns 11 tenIccH tps Chip Disable to Power Standby 25 45 ns Figure 5 SRAM READ Cycle 1 Address Controlled 4 8 ADDRESS DQ DATA OUT ADDRESS z vm z DQ DATA OUT Notes 3 W must be high during SRAM READ cycles _ 4 Device is continuously selected with E and G both low 5 Measured 200mV from steady state output voltage 6 HSB must remain high during READ and WRITE cycles Document Number 001 52040 Rev A Page 6 of 22 Feedback es See a 7 Cypress STK17T88 PERFORM SRAM WRITE Cycles 1 and 2 Symbols STK17T88 25 STK17T88 45 NO Parameter Units 1 2 Alt Min Max Min Max 12 tayav tavav two Write Cycle Time 25 45 ns 13 liwwH tWLEH twp Write Pulse Width 20 30 ns 14 teLwH tFLEH tew Chip Enable to End of Write 20 30 ns 15 lipvwH tDVEH tow _ Data Set up to End of Write 10 15 ns 16 twupx teHpx toy Data Hold after End of Write 0 0 ns 17 Jtaywu tAVEH taw _ Address Set up to End of Write 20 30 ns 18 taywL tAVEL tas Address Set up to Start of Write 0 0 ns 19 twHax tFHAX twp _ Address Hold after End of Write 0 0 ns 20 iwaz twz Write Enable to Output Disable 10 15 ns 21 twHax tow Output Active after End of Write 3 3 ns Figure 7 SRAM WRITE Cycle 1 W Controlled 3 12
23. e SRAM took place since the last STORE or RECALL cycle The HSB pin has a very resistive pull up and is internally driven low to indicate a busy condition while the STORE initiated by any means is in progress This pin should be externally pulled up if it is used to drive other inputs SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated After HSB goes low the STK17T88 continues to allow SRAM operations for tpej ay During tpe ay Multiple SRAM READ operations may take place If a WRITE is in progress when HSB is pulled low it is allowed a time tpeLay to complete However any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high During any STORE operation regardless of how it was initiated the STK17T88 will continue to drive the HSB pin low releasing it only when the STORE is complete Upon completion of the STORE operation the STK17T88 will remain disabled until the HSB pin returns high If HSB is not used it should be left unconnected Hardware Recall POWER UP During power up or after any low power condition Vec lt VswitcH an internal RECALL request will be latched When Vcc once again exceeds the sense voltage of VewrcH a RECALL cycle is automatically initiated and takes turecat to complete Page 12 of 22 Feedback PERFORM Software STORE Data can be transferred fr
24. egister To use the watchdog timer to reset the processor on timeout the INT is tied to processor master reset and Interrupt register is programmed to 24h to enable interrupts to pulse the reset pin on timeout To load the watchdog timer set a new value into the load register by writing a O to the watchdog write bit WDW of the watchdog register at Ox7FF7 Then load a new value into the load register Once the new value is loaded the watchdog write bit is then set to 1 to disable watchdog writes The watchdog strobe bit WDS is set to 1 to load this value into the watchdog timer Note Setting the load register to zero disables the watchdog timer function The system software should initialize the watchdog load register on power up to the desired value since the register is not nonvol atile Power Monitor The STK17T88 provides a power monitor function The power monitor is based on an internal band gap reference circuit that compares the Vcc voltage to Vswitcu When the power supply drops below Vswitcu the real time clock circuit is switched to the backup supply battery or capacitor When operating from the backup source no data may be read or written and the clock functions are not available to the user The clock continues to operate in the background Updated clock data is available to the user tyurecat delay after Vee has been restored to the device When the power is lost the PF flag in the Flags register is se
25. function can not be disabled on the STK17T88 Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values experience gained working with hundreds of applications has resulted in the following suggestions as best practices m The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance Incoming inspection routines at customer or contract manufacturer s sites sometimes reprograms these values Final NV patterns are typically repeating patterns of AA 55 00 FF A5 or 5A End product s firmware should not assume an NV array is ina set programmed state Routines that check memory content values to determine first time system configuration cold or warm boot status etc should always program a unique NV pattern e g complex 4 byte pattern of 46 E6 49 53 hex or more random bytes as part of the final system manufacturing test to ensure these system routines work consistently m Power up boot firmware routines should rewrite the nvSRAM into the desired state autostore enabled etc While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently program bugs incoming inspection routines etc m The OSCEN bit in the Calibration register at Ox7FF8 should be set to 1 to preserve battery life whe
26. hold Vswitcu It is cleared to 0 when the Flags register is read or on power up OSCF Oscillator Fail Flag Set to 1 on power up only if the oscillator is enabled and not running in the first 5ms of operation This indicates that the RTC backup power failed and the clock value is no longer valid The user must reset this bit to 0 to clear this condition CAL Calibration Mode When set to 1 a 512Hz square wave is output on the INT pin When set to 0 the INT pin resumes normal operation This bit defaults to O disabled on power up Write Time Setting the W bit to 1 freezes updates of the RTC registers The user can then write to the RTC registers Alarm registers Calibration register Interrupt register and Flags register Setting the W bit to 0 disables writes to the registers and causes the contents of the real time clock registers to be transferred to the timekeeping counters if the time has changed a new base time is loaded The bit defaults to 0 on power up Read Time Setting the R bit to 1 captures the current time in holding registers so that clock updates are not during the reading process Set the R bit to 0 to enable the holding register to resume clock updates The bit defaults to 0 on power up Commercial and Industrial Ordering Information STK17T88 R F 451TR Packaging Option TR Tape and Reel Blank Tube Temperature Range C Commercial 0 to 70 C
27. idth 15 ns Figure 11 Hardware STORE Cycle 32 tex RB N SO es HSB OUT DQ DATA OUT SRAM Enabled SRAM Enabled Soft Sequence Commands NO Symbols Parameter STK17T88 Units Notes l Standard Min Max 33 tss Soft Sequence Processing Time 70 us 15 16 Figure 12 Soft Sequence Command 33 33 Soft Sequence Command Soft Sequence Command ADDRESS Vee Notes 14 On a hardware STORE initiation SRAM operation continues to be enabled for time tDELAY to allow read write cycles to complete 15 This is the amount of time that it takes to take action on a soft sequence command Vcc power must remain high to effectively register command 16 Commands like Store and Recall lock out I O until operation is complete which further increases this time See specific command Document Number 001 52040 Rev A Page 10 of 22 Feedback STK17T88 MODE Selection E W G A14 Ag Mode 1 O Power Notes H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L Ox0E38 Read SRAM Output Data 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output Data Active 17 18 19 Ox3C1F Read SRAM Output Data 0x303F Read SRAM Output Data Ox0FCO Nonvolatile Store Output High Z loce L H L Ox0E38 Read SRAM Output Data Active 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output
28. led to enabled it typically takes 5 seconds 10 seconds max for the oscillator to start The STK17T88 has the ability to detect oscillator failure due to loss of backup power The failure is recorded by the OSCF Oscillator Failed bit of the Flags register at address 0x7FFO When the device is powered on Vcc goes above VswircH the OSCEN bit is checked for enabled status If the OSCEN bit is enabled and the oscillator is not active within 5 ms the OSCF bit is set The user should check for this condition and then write a 0 to clear the flag When the OSCF flag bit the real time clock registers are reset to the Base Time see the section Setting the Clock on page 14 the value last written to the real time clock registers The value of OSCF should be reset to 0 when the real time clock registers are written for the first time This initializes the state of this bit since it may have become set when the system was first powered on To reset OSCF set the write bit W in the Flags register at 0x7FFO to a 1 to enable writes to the Flags register Write a O to the OSCF bit and then reset the write bit to O to disable writes Calibrating The Clock The RTC is driven by a quartz controlled oscillator with a nominal frequency of 32 768 KHz Clock accuracy depends on the quality of the crystal specified usually 35 ppm at 25 C This error could equate to 1 53 minutes gain or loss per month The STK17T88 e
29. mbol Parameter Units Notes Min Max Min Max IBAK RTC Backup Current 300 350 nA From either VRTCcap or VRTCbat VRTCbat RTC Battery Pin 1 8 3 3 1 8 3 3 V Typical 3 0 Volts during normal operation Voltage VRTCcap RTC Capacitor Pin 1 2 2 7 1 2 2 7 V Typical 2 4 Volts during normal operation Voltage tOSCS RTC Oscillator time to 10 10 sec At Minimum Temperature from Power up or start Enable 5 5 sec At 25 C from Power up or Enable Figure 4 RTC Component Configuration ys O LL r a O pa Jl O oqo E X C X2 Recommended Values Y 32 768 KHz RF 10M Ohm C 0 install cap footprint but leave unloaded Co 56 pF 10 do not vary from this value Document Number 001 52040 Rev A Page 5 of 22 Feedback es SP CYPRESS STK17T88 O PERFORM SRAM READ Cycles 1 and 2 Symbols STK17T88 25 STK17T88 45 NO Parameter Units 1 2 Alt Min Max Min Max 1 teLav tacs Chip Enable Access Time 25 45 ns 2 tavay teten tRC Read Cycle Time 25 45 ns 3 tanaw ltavav ltna fAddress Access Time 25 45 ns 4 teLav tog Output Enable to Data Valid 12 20 ns 5 taxax 4l taxax toH Output Hold after Address Change 3 3 ns 6 teLax t7 Address Change or Chip Enable to 3 3 ns Output Active 7 teHQz tuz Address Change or Chip Disable to 10 15 ns Output Inactive 8 teLax to17 Output Ena
30. mploys a calibration circuit that can improve the accuracy to 1 2 ppm at 25 C The calibration circuit adds or subtracts counts from the oscillator divider circuit The number of time pulses added or subtracted depends upon the value loaded into the five calibration bits found in Calibration register at Ox7FF8 Adding counts speeds the clock up subtracting counts slows the clock down The Calibration bits occupy the five lower order bits of the register These bits can be set to represent any value between 0 and 31 in binary form Bit D5 is a Sign bit where a 1 indicates positive calibration and a 0 indicates negative calibration Calibration occurs during a 64 minute period The first 62 minutes in the cycle may once per Page 14 of 22 Feedback PERFORM minute have one second either shortened by 128 or lengthened by 256 oscillator cycles If a binary 1 is loaded into the register only the first 2 minutes of the 64 minute cycle is modified if a binary 6 is loaded the first 12 are affected and so on Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125 829 120 actual oscillator cycles That is 4 068 or 2 034 ppm of adjustment per calibration step in the Calibration register The calibration register value is determined during system test by setting the CAL bit in the Flags register at Ox7FFO to 1 This causes the INT pin to toggle at a nomin
31. n the system is in storage see Stopping and Starting the RTC Oscillator on page 14 m The Vcap value specified in this datasheet includes a minimum and a maximum value size Best practice is to meet this requirement and not exceed the max Vcap value because the nvSRAM internal algorithm calculates Vcap charge time based on this max Vcap value Customers that want to use a larger Veap value to make sure there is extra store charge and store time should discuss their Voa size selection with Cypress to understand any impact on the Vcapvoltage level at the end of a tRECALL period Page 13 of 22 Feedback PERFORM Real Time Clock The clock registers maintain time up to 9 999 years in one second increments The user can set the time to any calendar time and the clock automatically keeps track of days of the week and month leap years and century transitions There are eight registers dedicated to the clock functions which are used to set time with a write cycle and to read time during a read cycle These registers contain the Time of Day in BCD format Bits defined as O are currently not used and are reserved for future use by Cypress Reading the Clock The user should halt internal updates to the real time clock registers before reading clock data to prevent reading of data in transition Stopping the internal register updates does not affect clock accuracy Write a 1 to the read bit R in the Flags registe
32. nt Title STK17T88 32K x 8 AutoStore nvSRAM with Real Time Clock Document Number 001 52040 Rev ECN No org HA Submission Date Description of change ka 2668660 GVCH PYRS 03 04 2009 New data sheet A 2675319 GVCH 03 17 2009 Corrected typo on page 1 in Description section changed 256KB to 256Kb Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless
33. om the SRAM to the nonvolatile memory by a software address sequence The STK17T88 software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations in exact order During the STORE cycle previous data is erased and then the new data is programmed into the nonvolatile elements Once a STORE cycle is initiated further memory inputs and outputs are disabled until the cycle is completed To initiate the software STORE cycle the following READ sequence must be performed 1 Read address 0x0E38 Valid READ 2 Read address 0x31C7 Valid READ 3 Read address 0x03E0 Valid READ 4 Read address 0x3C1F Valid READ 5 Read address 0x303F Valid READ 6 Read address Ox0FCO Initiate STORE cycle Once the sixth address in the sequence has been entered the STORE cycle commences and the chip is disabled It is important that READ cycles and not WRITE cycles be used in the sequence After the tstore cycle time has been fulfilled the SRAM is again activated for READ and WRITE operation Software RECALL Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence A software RECALL cycle is initiated with a sequence of READ operations in a man ner similar to the software STORE initiation To initiate the RECALL cycle the following sequence of E controlled READ operations must be performed 1 Read address 0x0E38 Valid READ 2 Read address 0x31C7 Valid READ
34. once per minute Note The product requires the match bit for seconds Ox7FF2 bit D7 be set to O for proper operation of the Alarm Flag and Interrupt The alarm value should be initialized on power up by software since the alarm registers are not nonvolatile To set or clear the Alarm registers set the write bit W in the Flags register at Ox7FFO to a 1 to enable writes to the Alarm registers Write an alarmvalue to the alarm registers and then reset the write bit to O to disable writes Watchdog Timer The watchdog timer is designed to interrupt or reset the processor should its program get hung in a loop and not respond in a timely manner The software must reload the watchdog timer before it counts down to zero to prevent this interrupt or reset Document Number 001 52040 Rev A STK17T88 The watchdog timer is a free running down counter that uses the 32Hz clock 31 25 ms derived from the crystal oscillator The watchdog timer function does not operate unless the oscillator is running The watchdog counter is loaded with a starting value from the load register and then counts down to zero setting the watchdog flag WDF and generating an interrupt if the watchdog interrupt is enabled The watchdog flag bit is reset when the Flags register is read The operating software would normally reload the counter by setting the watchdog strobe bit WDS to 1 within the timing interval programmed into the load r
35. onvolatile cycle no STORE will take place 11 Industrial Grade Devices require 15 ms Max Document Number 001 52040 Rev A Page 8 of 22 Feedback SS 2 mm F CYPRESS STK17T88 3539 PERFORM Software Controlled STORE RECALL Cycle In the following table the software controlled STORE and RECALL cycle parameters are listed 12 19 Symbols STK17T88 35 STK17T88 45 NO Parameter Units Notes ECont Alternate Min Max Min Max 26 tayav tro STORE RECALL Initiation Cycle Time 25 45 ns 13 27 tave tas Address Set up Time 0 0 ns 28 teren tcw Clock Pulse Width 20 30 ns 29 tEHAX Address Hold Time 1 1 ns 30 tRECALL RECALL Duration 100 100 ms Figure 10 Software Store Recall Cycle E CONTROLLED 3 26 26 ADDRESS E s s a Gs 23 store trecaLL R COREE HIGH IMPEDENCE Notes 12 The software sequence is clocked on the falling edge of E controlled READs 13 The six consecutive addresses must be read in the order listed in the Software STORE RECALL Mode Selection Table W must be high during all six consecutive cycles Document Number 001 52040 Rev A Page 9 of 22 Feedback CYPRESS STK17T88 PERFORM Hardware STORE Cycle Symbols STK17T88 NO Parameter Units Notes Standard Alternate Min Max 31 DELAY tuLaz Hardware STORE to SRAM Disabled 1 70 us 14 32 HLHX Hardware STORE Pulse W
36. r at Ox7FFO to capture the current time in holding registers Clock updates do not restart until a O is written to the read bit The RTC registers can now be read while the internal clock continues to run Within 20ms after a O is written to the read bit all real time clock registers are simultaneously updated Setting the Clock Set the write bit W in the Flags register at Ox7FFO to a 1 enable the time to be set The correct day date and time can then be written into the real time clock registers in 24 hour BCD format The time written is referred to as the Base Time This value is stored in nonvolatile registers and used in calculation of the current time Reset the write bit to O to transfer the time to the actual clock counters The clock starts counting at the new base time Backup Power The RTC is intended to keep time even when system power is lost When primary power Vcc drops below Vswircu the real time clock switches to the backup power supply connected to either the VRTCcap Or VRTCbat pin The clock oscillator uses a maximum of 300 nanoamps at 2 volts to maximize the backup time available from the backup source You can power the real time clock with either a capacitor or a battery Factors to be considered when choosing a backup power source include the expected duration of power outages and the cost and reliability trade off of using a battery versus a capacitor If you select a
37. t to indicate the power failure and an interrupt is generated if the power fail interrupt is enabled interrupt register 20h The INT line would normally be tied to the processor master reset input to perform power off reset Interrupts The STK17T88 has a Flags register Interrupt register and interrupt logic that can interrupt the microcontroller or general a power up master reset signal There are three potential interrupt sources the watchdog timer the power monitor and the clock alarm Each can be individually enabled to drive the INT pin by setting the appropriate bit in the Interrupt register In addition each has an associated flag bit in the Flags register that the host processor can read to determine the interrupt source Two bits in the interrupt register determine the operation of the INT pin driver Page 15 of 22 Feedback PERFORM Figure 15 is a functional diagram of the interrupt logic Figure 15 Interrupt Block Diagram WDF Watchdog Timer Je Pe Power Monitor YO INT 5 VINT Vss Interrupt Register Watchdog Interrupt Enable WIE When set to 1 the watchdog timer drives the INT pin when a watchdog time out occurs When WIE is set to 0 the watchdog time out only sets the WDF flag bit Alarm Interrupt Enable AlE When set to 1 the INT pin is driven when an alarm match occurs
38. ter that counts from 1 to 7 then returns to 1 The user must assign meaning to the day value as the day is not integrated with the date Real Time Clock Hours OERE D7 D6 D5 D4 D3 D2 Di DO 0 0 10s Hours Hours Contains the BCD value of hours in 24 hour format Lower nibble contains the lower digit and operates from 0 to 9 upper nibble two bits contains the upper digit and operates from 0 to 2 The range for the register is 0 23 Real Time Clock Minutes OxZEEA D7 D6 D5 D4 D3 D2 D1 DO 0 10s Minutes inutes Contains the BCD value of minutes Lower nibble contains the lower digit and operates from 0 to 9 upper nibble contains the upper minutes digit and operates from O to 5 The range for the register is 0 59 Real Time Clock Seconds Dx7FF9 D7 D6 D5 D4 D3 D2 D1 DO 0 10s Seconds Seconds Contains the BCD value of seconds Lower nibble contains the lower digit and operates from 0 to 9 upper nibble contains the upper digit and operates from 0 to 5 The range for the register is 0 59 Sess Cal bration asa a al Ox7FF8 alibration alibration OSCEN Oscillator Enable When set to 1 the oscillator is disabled When set to 0 the oscillator is enabled Disabling the oscillator saves battery capacitor power during storage Calibration Sign Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time base Calibration These five bits control the calibration of the clock Watchdog Timer OxX7FEY D7 D6 D5 D4 D
39. with the value 00h on power up with the exception of the OSCF bit Page 16 of 22 Feedback awe oS ao 2 CYPRESS STK17T88 PERFORM RTC Register Map BCD Format Data Register D7 DE D5 D4 D3 DZ Di DO Function Range Ox7FFF TOs Years Years Years 00 99 Ox7FFE 0 0 0 10s Months Months 01 12 Months Ox7FFD 0 0 10s Day of Month Day of Month Day of Month 01 31 Ox7FFC 0 0 0 0 0 Day of Week Day of week 01 07 Ox7FFB 0 0 10s Hours Hours Hours 00 23 Ox7FFA 0 10s Minutes Minutes Minutes 00 59 Ox7FF9 0 10s Seconds Seconds Seconds 00 59 Ox7FF8 OSCEN 0 Cal Calibration 00000 Calibration values 0 Sign Ox7FF7 WDS WDW WDT Watchdog Ox7FF6 WIE 0 AlE 0 PFE O 0 H L 1 P L 0 0 0 Interrupts Ox7FF5 M 0 10s Alarm Date Alarm Day Alarm Day of Month 01 31 Ox7FF4 M 0 10s Alarm Hours Alarm Hours Alarm hours 00 23 Ox7FF3 M 10 Alarm Minutes Alarm Minutes Alarm minutes 00 59 Ox7FF2 M 10 Alarm Seconds Alarm Seconds Alarm seconds 00 59 Ox7FF1 10s Centuries Centuries Centuries 00 99 Ox7FFO WDF AF PF OSCF 0 CAL 0 W 0 R 0 Flags A binary value not a BCD value 0 Not implemented reserved for future use Default Settings of nonvolatile Calibration and Interrupt registers from factory Calibration Register 00h Interrupt Register 00h The User should configure to the desired value at startup or during operation and the value
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