CH Tech Pulse Generator User's Manual
Contents
1. Device Class Device Clas Register Based binary 11 Ares Space gt Address Space A16 Only inary IL Manuf Manufacture Menication Engines o VRIDEVICE TIPE wa Net ied Mad Cae Model Cade gt code Model VX4628 hex FFD Wa Rai Uae TTT gt Reset a sets th card MODID Module ID Status 0 P2 MODID line i selected active high Ray gt Ready 1 ready Pass Sees pass indicator passed Figure 5 VXI Configuration Registers 10 3 52 Pulse Configuration Registers Pulse Repetition Interval Register 08 This read write register controls the pulse repetition interval and the state of the output relay See Figure 6 for details PRT Register PO REI E ite OEN Range Norte PRI Mulan DEN Range Not Use PRI Malipier gt Output Relay Enable 1 enbledoutpt en Range PRIA Delay Range Dit 14 13 000 25m ty 0 100 101 Im invalid PRI gt PRI Multiple period PRI Muliplie Range NOTES 9 The Range fields used for both the PRI and Delay tne stings 2 The minimum programmable is 100 asec Therefore the minimum PRI in ih 25 nsec range and 2 fr lle ranges 3 The maximum PRI Mulpir i 1023 therefore the maximum programmable period is 1 023 we 4 Forhighos accuaey use the smallest a2. 016 Address Space LA 64 CO00h For example VME DI6 address space FF0000h and the VX462B Logical Address 8 Address FR0000h 8 64 COOOh FEC200h 42 PROGRAMMING SEQUENCE The RUN bit in the Pulse Control Register is the basic On Off control for pulse generation A separate output relay connects disconnects the generated pulse to from the connector The output relay is controlled by the OEN bit in the PRI Register Before enabling the RUN control bit or output relay be sure to program all of the timing and voltage level registers as prescribed in this manual Special care should be taken to check the registers for timing over runs and output voltage levels To prevent damage to the users circuitry the following steps should be followed when programming 1 Disable the output relay and reset RUN 2 Program Voltage References 3 Setup Timing registers and control functions 4 Enable the output relay 5 Enable RUN 43 NORMAL MODES OF OPERATION The three normal modes of operation are single pulse delayed pulse and double pulse three modes of operation and their relationship to trigger out are described below The Trigger Output signal indicates the beginning of a pulse cycle It occurs 50 7515 after the RUN bit is set or the trigger input signal goes high The width of trigger out is equal to the pulse width range selected 25ns 100 etc 431 Single Pulse
3. ofthe programmed value Pulse Width Range 251s to Lee in 6 ranges Resolution 25ns min 10 bits Accuracy 191508 ofthe programmed value Timing rom Trigger Out Range 2505 to 1 sec range slaved to Pulse Repetition Interval range Resolution 25ns min 10 bits Accuracy 191508 of the programmed value 250 75ns synchronization time Pulse Output Impedance 2 5 max load 50 ohms 50 ohms selectable 10 no load lt 10 MHz low impedance into 50 ohms 50 Ohm impedance Accuracy 346 ofthe programmed value plus offset erro lad Resolution 12bi1 49mV no load Transition Time Fixed rate Sns at SV Trigger Output TIL 10 gate drive capability Trigger Gate In TIL Figure 1 Electrical Timing and Output Characteristics 124 Environmental The environmental specifications of the module are Operating Temperature OPC to 450 C Storage Temperature 40 C to 465 C Humidity 5954 without condensation 12 5 Bus Compliance The module complies with the VXIbus Specification Revision 1 4 for B size register based modules and with VMEbus Specification STD 1014 1987 and IEC 821 Manufacturer ID Model Code Access Type Addressing Data Transfer Bus Arbitration Local Bus FCI hex FED hex Register Based 16 not supported not supported IACKIN tied t
4. Pulse Configuration Registers 4 0 OPERATING INSTRUCTIONS 4 1 LOGICAL ADDRESS 4 2 PROGRAMMING SEQUENCE 4 3 NORMAL MODES OF OPERATION 43 1 Single Pulse Mode 43 2 Delayed Pulse Mode 433 Double Pulse Mode 4 4 TRIGGERED MODES OF OPERATION 441 Free 44 2 Triggered Mode 443 Gated Mode 4 5 SPECIAL MODES OF OPERATION 4 6 OUTPUT VOLTAGE LEVEL PROGRAMMING 5 0 TROUBLE ANALYSIS 5 1 BUILT IN TEST AND DIAGNOSTICS 5 2 TROUBLE ANALYSIS GUIDE APPENDIX BOARD LAYOUT APPENDIX CONNECTORS LIST OF FIGURES Figure 1 Electrical Timing and Output Characteristics Figure 2 Simplified Block Diagram Figure 3 Hardware Configurable Controls Figure 4 Front Panel Figure 5 VXI Configuration Registers Figure 6 PRI Register Figure 7 Delay Register Figure 8 Pulse Width Register Figure 9 Control Register Figure 10 Low High Level Reference Registers Figure 11 Functional Block Diagram Figure 1 Pin Configuration Figure B 2 P2 Pin Configuration Figure B 3 Front Panel Connector LIST OF TABLES Table I VXI Register Address 10 GENERAL DESCRIPTION The VX462B is a B size VXIbus compatible programmable 20 MHz pulse generator with an additional 40 MHz square wave function The module can output single or double pulse patterns that can be continuous streams or externally triggered or gated The pulse repetition interval and pulse width are programmable and a delay time may be programmed in the delayed or d
5. Mode Single pulse mode produces the desired pulse immediately approximately 25ns after trigger out and is selected when neither delayed or double pulse are selected 432 Delayed Pulse Mode When delayed pulse mode is selected the pulse occurs the programmed delay time after the trigger out plus Approximately 25ns To prevent a pulse overrun ensure that the delay time and the pulse width do not extend into the next cycle The pulse generation logic takes about 75 nsec to start therefore ensure that the delay time the pulse width is less than the pulse repetition interval 75 nsec 43 3 Double Pulse Mode The double pulse mode combines the functions of the single pulse mode and the delayed pulse mode The primary pulse occurs immediately after the trigger out and the secondary pulse occurs the programmed delay time after trigger out The width of both pulses are equal to the pulse width clock range times the pulse width multiplier value To prevent a pulse overrun ensure that the delay time and the pulse width do not extend into the next cycle The pulse generation logic takes about 75 nsec to start therefore ensure that the delay time the pulse width is less than the pulse repetition interval 75 nsec 16 44 TRIGGERED MODES OF OPERATION The pulse stream can be programmed to run continuously output a single function when triggered or output continuously as long as the gate trigger in is high free run trigg
6. USER S MANUAL VXI PULSE GENERATOR MODULE MODEL VX462B Manual Part No 110263390 COPYRIGHT Technologies Inc provides this manual as is without warranty of any kind either expressed or implied including but not limited to the implied warranties of merchantability and fitness for a particular purpose may make improvements and or changes in the product s and or program s described in this manual at any time and without notice This publication could contain technical inaccuracies or typographical errors Changes are periodically made to the information herein these changes will be incorporated in new editions of this publication Copyright 1993 1995 2005 Technologies Inc The information and or drawings set forth in this document and all rights in and to inventions disclosed herein which might be granted thereon disclosing or employing the materials methods techniques or apparatus described herein are the exclusive property Technologies Inc Readers Comment Form is provided at the back of this publication If this form has been removed address comments to Engineering Inc Technical Publications 445 West Round Rock Drive Round Rock Texas 78681 5012 may use or distribute any of the information you supply in any way that it believes appropriate without incurring any obligations whatever AMENDMENT NOTICE Technologies Inc makes e
7. arately it should be enclosed in a suitable water and vapor proof static bag Heat seal or tape the bag to insure a moisture proof closure When sealing the bag keep trapped air volume to a minimum The shipping container should be a rigid box of sulicient size and strength to protect the equipment from damage If the module was received separately from a C amp H system then the original module shipping container and packing material may be re used if is still in good condition 6 30 FUNCTIONAL DESCRIPTION 31 GENERAL The VX462B is configured controlled and statused through on board registers access through the VXI backplane These registers control the mode of operation pulse repetition interval pulse width delay time output amplitude and an output relay simplified block diagram of the module is shown in Figure 2 Figure 2 Simplified Block Diagram 3 2 SWITCHES AND JUMPERS 7 The following switches are used to configure the VX462B Refer to Figure 3 for the switch and jumper 3 locations LOGICAL ADDRESS An 8 bit 1 logical address switch is provided to uniquely identify the module in the system Refer to Section 4 for switch definition OUTPUT IMPEDANCE VX462B can be configured with a 50 Ohm or a 2 Ohm output impedance Install a jumper in 15 only for 2 Ohms and J6 only for 50 Ohm series output impe
8. dance Je Figure 3 Hardware Configurable Controls 34 INDICATORS Two LED indicators are provided on the front panel One indicates the status and the other indicates the board status MODID This front panel LED illuminates whenever the host processor applies the MODID signal to the slot the module is occupying RUN This front panel LED illuminates when the modules is actively outputting pulses CONNECTORS Front Panel Connectors Three BNC type connectors are provided for the pulse output trigger output and trigger input as shown in Figure 4 Their functions are as follows TRI This TTL level Trigger Input signal initiates the pulse eycles when Free Running Mode bit FRE in the Pulse Control Figure 4 Front Panel Register is set to zero If the Trigger Mode bit TMD is zero the rising edge of this signal starts one pulse cycle single or double pulse Ifthe bit is set to one the TRIG IN signal acts as a gate This gate allows the pulse cycle to repeat continuously while the gate is high When the gate is lowered the current pulse cycle completes and the pulse output stops TRIG OUT This TTL level Trigger Output signal indicates the beginning of a pulse cycle It occurs 50 75ns after the RUN bit is set or the trigger input TRIG IN signal goes high In single or double pulse mode the output pulse PULSE OUT will start approxima
9. e control The registers are briefly described below and are detailed in Figure 5 VXI Identification ID Register Base 00h A read of this register provides manufacturer identification device classification Le register based and the addressing mode A16 A write to this register has no effect VXI Device Type Register Base 02h A read of this register provides the model code identifier A write to this register has no effect VXI Status Control Register Base 04h read of this register provides the state P2 MODID line and the Ready and self test Passed status write to bit 0 of this register provides a reset of the module SYSEAIL is not implemented on this module Table 1 VXI Register Address Map Wee Register Description Read Register Descnpiin High Reference Register High Reference Register Base Low Reference Register Low Reference Register Pulse Control Register Pulse Control Registr Pulse Width Register Pulse Widih Register Base 04 Delay Registr Delay Register ERA PRI Resist Resist Base 0 Unused Register VA Unused Register ERAN VAT Control Register VAT Stats Register Base WRI Read Only Register YX Device Type Register Base O VXI Read Only Register VALID Repite Dis Doo Dis DoD Nate Nata Doris space Manufacturer ID
10. er or gated repetition three trigger modes are described below The RUN control bit must be set for any mode of operation to produce a pulse stream 44 1 Free When the FRE and RUN bits are programmed high a continuous stream of pulses are generated at the output driver Both normal and special modes of operation function in the free run mode The triggered modes operate only with the FRE bit set to 0 Each pulse cycle will be accompanied with a Trigger Out to indicate the beginning of the cycle 44 2 Triggered Mode When the FRE bit is reset low and the RUN bit is set high the output pulse stream function is dependent on the TMD control bit TMD is reset low for triggered mode an output pulse or a double pulse is generated on each rising edge of the trigger pulse Any triggers occurring prior the end of the pulse repetition interval are ignored even if the pulse has finished This allows the pulse repetition interval to be used to hold off retriggering 443 Gated Mode When the FRE bit is reset low and the RUN bit is set high the output pulse stream function is dependent on the TMD control bit If TMD is set high for gated mode the output pulse stream performs like free run as long as the input gate trigger in is high When the gate goes low the current pulse stream completes then stops For square wave modes the level remains at the current level 45 SPECIAL MODES OF OPERATION Along with the nor
11. l Reference Registers 40 OPERATING INSTRUCTIONS The VX462B provides three normal modes three triggered modes and three special modes of operation along with voltage level programming output disconnect and pulse enable controls A functional block diagram is show in Figure 11 These operational modes are configured controlled and statused through on board registers accessible through the VXI backplane Refer to paragraph 3 5 2 for register bit definitions Figure 11 Functional Block Diagram 4 1 LOGICAL ADDRESS Addressing the VX462B is a function of the logical address switch see paragraph 3 2 and the VXI host address modifier code The logical address has a range of 0 to 255 Any value within this range is valid but care should be taken not to set the logical address the same as another module in the system Position 1 on the switch is the most significant bit and has a weighted value of 128 when the switch is in the off position Position 8 on the switch is the least significant bit and has weighted value of 1 when the switch is in the off position The sum of the weighted values of all the switches in the off position is the module address The VXI secondary address is the Logical Address divided by 8 For VME users the board may be accessed in A32 24 16 address space although the VX462B decodes only 16 address The VME address is Address
12. logies Inc may use and distribute any of the information that you supply in any way that it believes to be appropriate without incurring any obligation whatsoever You may of course continue to use the information which you supply Please refrain from using this form for technical questions or for requests for additional publications this will only delay the response Instead please direct your technical questions to your authorized C amp H representative COMMENTS Thank you for helping to deliver the best possible product Your support is appreciated Sincerely FR Harrison President and CEO INSTRUCTIONS In its continuing effort to improve documentation Technologies Inc provides this form for use in submitting any comments or suggestions that the user may have This form may be detached folded along the lines indicated taped along the loose edge DO NOT STAPLE and railed Please try to be as specific as possible and reference applicable sections of the manual drawings if appropriate Also indicate if you would like an acknowledgment mailed to you stating whether or not your comments were being incorporated NOTE This form may not be used to request copies of documents or to request waivers deviations or clarification of specification requirements on current contracts Comments submitted on this form do not constitute or imply authorization to waive any portion of the refere
13. mal modes of operation three special free running square wave modes are provided These include a frequency programmable square wave and fixed frequency 20 MHz and 40 MHz square waves These modes provide a rapid method of producing a square wave output The square wave generation logic produces an output level change on each pulse repetition interval Note that this results in a square wave with a period equal to twice the programmed PRI The pulse width and delay time registers are disabled in this mode In the 20 and 40 MHz modes the PRI Pulse Width and Delay time registers are disabled Additionally at these high frequencies the output has limited output voltage capability however 45 can still be sustained 46 OUTPUT VOLTAGE LEVEL PROGRAMMING Two 12 bit digital to analog converters provide the output switch reference voltages The have built in safety features to prevent damage if the positive reference is programmed below the negative voltage however the user should try to prevent this situation The output logie switches the high and low reference voltages into a power op amp output stage The pulse string from the pulse generation logic provides the control to the switch while the reference voltages provide the voltage levels The op amp power stage has 2 3 ohms output impedance A jumper selectable resistor between the op amp output and the BNC provides isolation and back termination The resulting ou
14. nced document s or to amend contractual requirements Fold along this line Fold along this line Engineering Inc Technical Publications 445 West Round Rock Drive Round Rock Texas 78681 5012 Place Stamp Here
15. nge with aa Delay Register 0A This read write register controls delay of the primary pulse from the trigger oF the delay of the second pulse of a double pulse from the trigger out See Figure 7 for details al Delay Restor Fa E A Nata Delay Re Nat Use Delay Delay Multiplier Delay Malte period Delay Multiplier PRI Range NOTES 1 The Range programmable inthe PRI 2 The minimum delay multiplier is 1 therefore the minimum programmable delay is 25 3 The maximum delay multiple is 1023 however do not st the Delay Pulse Width eater than the PRI Period accuracy use the smallest PRL range with larger multiple Figure 7 Delay Register Pulse Width Register 0 This read write register controls the pulse width of the output pulse See Figure 8 for details False Width Register na RE EIA CI Wei RUT Range Not Used PW Super NAT Range PW Maliplier Nat Used Range gt PWRange bit 14 000 001 1 100 101 Im invalid gt PW Multiple width PW Multiple Range NOTES 1 The minimum programmable pulse width period is 25 nse 2 The pulse rypicaly requires 75 sa tigger ou or the delay time out 3 The maximum pulse width muliplir is 1023 however do not pr
16. o LACKOUT BRx tied to BGx not used 2 0 INSTALLATION 21 UNPACKING AND INSPECTION In most cases the VX462B is individually sealed and packaged for shipment Verify that there has been no damage to the shipping container If damage exists the container should be retained as it will provide evidence of carrier caused problems Such problems should be reported to the carrier immediately as well as to If there is no damage to the shipping container carefully remove the module from its box and anti static bag and inspect for any signs of physical damage If damage exists report immediately to 22 HANDLING PRECAUTIONS The VX462B contains components that are sensitive to electrostatic discharge When handling the module for any reason do so at a static controlled workstation whenever possible At a minimum avoid work areas that are potential static sources such as carpeted areas Avoid unnecessary contact with the components on the module 23 INSTALLATION CAUTION Read the entire User s Manual before proceeding with the installation and application of power Set or verify the module s logical address Insert the module into the appropriate slot according the desired priority Apply power If no obvious problems exist proceed to communicate with the module as outlined in Section 4 0 Operating Instructions 24 PREPARATION FOR RESHIPMENT Ifthe module is to be shipped sep
17. ogram the Delay Pulse Widh ree than PRI period 75 nse 4 Forhighest accuracy us the smallest ang with larger multiple Figure 8 Pulse Width Register 12 Pulse Control Register QE This read write register configures the operating mode of the pulse See Figure 9 for detail Pulse Control Register PO RE O O 7 SC wi Na et RUN FD PRE el Nat Use EAN 50 OU gt Double Pulse 0 single pus RUN gt Run EnableDisable 1 enabled TMD Tigger Mode 0 wiggered 1 gated DEL gt Delay Mode 0 immediate no delay 1 delayed FRE Free Running Mode 0 wiggered I runing Mode gt Wavefoom Mode bit 10 double pulse 0 0 Normal 021 Square Wave 1 0 2 Square Wave 11 AO MHZ Square Wave NOTES 1 With double pulse enabled the primary pulse will start 75 nse after tigger The second pulse wll stat the programmed delay time afer tigger out Double pulse enable has peecedence over delayed pulse 2 Pulse ae generated when RUN is high however the ouput relay must be enabled oat panel 3 With the tiger mode gate he output pulse steam vil continue as long as TRIG IN is high When he TRIG IN goes low he pulse sequence started will nich then sup 9 With delayed pulse enabled the primary pulse will sir programmed dela
18. ouble pulse modes The output amplitude is also programmable 11 PURPOSE OF EQUIPMENT This module is well suited for applications within automated test equipment and hardware in the loop simulation systems as well as development laboratory environments 12 SPECIFICATIONS OF EQUIPMENT 121 Key Specifications Single and double pulse modes Continuous triggered gated and delayed modes Programmable pulse repetition interval and pulse width Programmable delay time 10Vpp output amplitude with low impedance output 5Vpp output amplitude with 50 Ohm impedance output selected Read back capability on all registers 122 Electrical The module requires the 5V and 12V power from the VXI backplane The peak module current 1 for the 5 volt supply is 3 0 amps and for the 12 volts it is 04 amps The pulse timing and output characteristics are shown in Figure 1 123 Mechanical The mechanical dimensions of the module are in conformance with the VXIbus specification Rev 1 4 for single slot size modules The nominal dimensions are 233 35 9 187 high x 160 mm 6 299 in deep The module is designed for a mainframe with 20 32 mm 0 8 in spacing between slots As required by the VXI bus specification these dimensions are in accordance with those given in the VME bus specification Rev Pulse Repetition Interval Range to 1 sec in 6 ranges Resolution 25ns min 10 bits Accuracy
19. tely 25ns after trigger out In delayed pulse mode the output pulse will start the programmed time after trigger out approximately 2515 The width of trigger out is equal to the pulse width range selected Le 25ns 100ns 15 etc When in running mode a trigger output signal will occur atthe beginning of every PULSE OUT The amplified pulse cycles are available at this connector The output impedance of this signal in jumper selectable between 2 or 50 Ohms see figure 3 The output amplitude cycle period pulse width and other pulse and trigger characteristics are register programmable 342 Rear Connectors The and connectors are configured in accordance with the VXI specification See Appendix B 35 CONFIGURATION REGISTERS There are several types of registers used to configure and control the VX462B The VXI configuration registers provide for control and status as required by the VXIbus specification The other register provides board level control and status of the pulse repetition interval pulse width trigger modes and delay times and output amplitude An address map of the registers is shown in Table I 3 5 1 VXI Configuration Registers The VXI configuration registers contain basic information needed to configure a VXIbus system The configuration information includes manufacturer identification product model code device type memory requirements device status and devic
20. ternal loads by removing the connector 20 1 4 APPENDIX CON PI 1 Dos 007 2 009 Dot 3 010 002 4 003 5 012 BGOOUT 004 5 013 BGN 005 7 014 006 015 BGN 007 9 GND GND 10 m BOSOUT 12 SYSRESET 13 14 AMS WRITE 16 na 16 AmO TACK 7 E 18 2 19 aig ANS 20 18 2 TACKING 2 lACKOUT 2 GND 24 Aa 07 25 Ras 06 26 Ras 205 2 IRs 28 03 2 02 30 08 Ino El 12 V 12V 32 SV 15V Figure 1 PI Pin Configuration PR ry 1 357 2 GND 3 4 GND 5 6 7 8 9 10 GND GND 12 13 14 15 16 GND GND 17 18 19 20 22 GND 2 24 25 25 2 2 2 GND CHD GND 32 Figure B 2 P2 Pin Configuration BNO TRIGGERIGATE INPUT TRIG IN TRIGGER OUTPUT OUT PULSE PULSE OUT FRONT VIEW Figure B 3 Front Panel Connector NOTES READER S COMMENT FORM Your comments assist us in improving the usefulness of publications they are an important part of the inputs used for revision Techno
21. tput impedance is about 5 ohms with jumper 15 installed and 50 ohms with Jumper 16 installed load of 50 ohms or more is recommended 18 50 TROUBLE ANALYSIS 5 1 BUILT IN TEST AND DIAGNOSTICS Built in test functions are provided for the VX462B in the form of read back registers The VXIbus registers perform as defined in the VXIbus specification and the timing and control registers have read back capability for data verification and test 52 TROUBLE ANALYSIS GUIDE The first approach to troubleshooting is to attempt 16 VXIbus access successful access read or write will not produce a bus error If a bus error occurs a probable cause is an improperly set logical address Check this setting and verify the program for proper addressing If no bus error occurs read the first two VXIbus registers The expected device type is FFFD and the expected ID is refer to the paragraph 3 5 1 for the Device Type and ID bit locations check the register write capability write a value to the Pulse Width Register then read it back The returned value should match the data written with the exception of the unused bits If the module is responding as expected program a pulse stream and monitor the Pulse Out with an oscilloscope If no signal is seen or is not as expected utilize the modules read back capability to verify that all registers are correctly set When diagnosing output problems isolate the module from ex
22. very attempt to provide up to date manuals with the associated equipment Occasionally changes are made to the equipment wherein itis necessary to provide amendments to the manual If any amendments are provided for this manual they are printed on colored paper and will be found at the rear of this manual NOTE The contents of any amendment may affect operation maintenance calibration of the equipment INTRODUCTION This manual describes the functional operation of the Model VX462B VXI Pulse Generator Part No 11026335 This module is one of a number of test and data acquisition control modules in the and VXI format provided by Contained within this manual is information on the physical and electrical specifications installation and startup procedures operating procedures functional analysis and figures and diagrams required to adequately support this product TABLE OF CONTENTS 1 0 GENERAL DESCRIPTION 1 1 PURPOSE OF EQUIPMENT 1 2 SPECIFICATIONS OF EQUIPMENT 1 2 1 Key Specifications 122 Electrical 123 Mechanical 124 Environmental 12 5 Bus Compliance 2 0 INSTALLATION 2 1 UNPACKING AND INSPECTION 2 2 HANDLING PRECAUTIONS 2 3 INSTALLATION 2 4 PREPARATION FOR RESHIPMENT 3 0 FUNCTIONAL DESCRIPTION 3 1 GENERAL 3 2 SWITCHES AND JUMPERS 3 3 INDICATORS 3 4 CONNECTORS 3 4 1 Front Panel Connectors 34 2 Rear Connectors 3 5 CONFIGURATION REGISTERS 3 51 VXI Configuration Registers 3 52
23. y time er igge ut Double pulse enable has precedence delayed pale 5 Fes run disables al inpats and produces continuo pulse seam 6 Inte square wave mode the square Wave period is equal o timos the PRI period programmed 7 The special modes provide the output a 20 ce 40 MHz square wave by Programming aly the waveform mae Figure 9 Control Register Low High Level Reference Register 10 amp 12 Two 12 bit Digital to Analog Converters DAC are used to create the low and high level references to the output logic These registers are write only See Figure 10 for details so Taw Level Reference Registers E RES A O Ts E wre Reference Volage O E A IS Ref 2 Ohm Output 50 Ohm Outpt lap 0 Y 0 0V FFF FFF 10 0 Y bit esla igh Level Reference Registers ees Pee Po wre Nor Wied Reference Red CI IC O CI O O CO CI A IA A Ref gt 2 Ohm Output 50 Ohm Outpt lap 10 0 V 008 0 0 Y FFFR 10 0 bit solution 4 884 mV 0 V FFFA 45 0 V bit resolution 2 442 mV NOTE The Low Level Reference should no be pogrammed more positive than the High Level Reference Likewise the High Level Reference should not be programmed less negative than the Low Level Reference Figure 10 Low High Leve
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