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AMD CS5535 User's Manual

1. Procedure IF lt PCI graphics card exists gt THEN Jump to PCI graphics BIOS for initialization ELSEIF lt ISA graphics card exists gt THEN Jump to ISA graphics BIOS for initialization ELSE lt SoftVGA required by setup gt THEN Initialize SoftVGA during VSA initialization Jump to integrated graphics BIOS for initialization ENDIF 4 5 1 1 Monochrome Support GeodeROM includes the appropriate INT 10h support for monochrome video adapters SoftVG needs an extra hole at BO000h B7FFh when a mono card is present 4 5 1 2 Dual Monitor Support GeodeROM provides dual monitor support GeodeROM assumes that the external card is the primary graphics card and that the XpressGRAPHICS system is secondary AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 25 AMD d 32430C Initialization 26 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Implementation 324300 AMD Implementation 5 1 Implementation The following is a collection of implementation details to consider in the GeodeROM implementation phase 5 1 1 Clocking There are two clock inputs to the GX processor the system PCI clock SYSREF used to derive the Core clock and the GeodeLink clock used for the memory clock The Dot clock is used for video display control The Core and GeodeLink clocks can be programmed and restarted by reseting the GX processor 5 1 2 Scratchpad Initialization The scratch
2. 0 7FFFFh 80000h 9FFFFh Conventional Memory Figure 7 2 CPU Core Cache Descriptors AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 31 AMDA 32430C Memory Map RCONF_DEFAULT ROMRC RCONF_DEFAULT ROMBASE RCONF_DEFAULT DEVRG RCONF_SMM RCONF_DEFAULT SYSTOP RCONF_DEFAULT SYSRC RCONF_A0_BF RCONF_EO_FF RCONF_DEFAULT SYSRC RCONF_BYPASS RCONF RCONF7 ROM FFFCO0000h PCI Memory Mapped PCI PCI PCI Memory Mapped Frame Buffer 50000000h Memory Mapped Video Registers Memory Mapped VSA PCI Frame Buffer VSA 40400000h subtracted from Extended Memory Top of DRAM VSA and Frame Buffer PCI Extended Memory Top of System OS RAM System and Option ROMs Conventional Memory SMM and DMM header and table walk properties Not Used Figure 7 3 CPU Core Cache Region Configurations 32 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Memory Map 324300 AMD CPU ID Uses CPU ID instruction a A orrect CMOS NVRAM Valid and Checksum Ok Failed to Failed boots need a POR Load CMOS Boot J NVRAM Defaults 3 Times reset and will always take this path Early CS5535 Initialization PLL Flag ae Y indicates 2nd Pass N J Continue POST Jumper settings correspond PLL R
3. KB data cache The cache is enabled through register CRO and both caches can be disabled through MSRs regardless of the CRO state 4 1 5 4 Region Configuration Region Configuration MSRs are used to describe the caching properties of each memory region Unlike descriptors RConfs are designed to overlap The Default Region Configuration Properties register CPU Core MSR Address 00001808h contains the base settings and RConfs for the shadow area and other special regions supersede its setting Example Default Region Configuration Properties 128 MB memory in the system 8 MB is used for frame buffer and 256 KB is used for VSA technology 0x1808 0x25FFFCO2 0x1077DF00 The Default Region Configuration Properties register shown in Table 4 1 is the main register for GX processor cache set tings Table 4 1 Default Region Configuration Properties Bit Descriptions Bit Name Note Description 63 56 ROMRP ROM Region Properties Region properties for addresses greater than ROMBASE bits 55 36 55 36 ROMBASE ROM Base Address Base address for boot ROM This field represents A 32 12 of the memory address space for 4 KB granularity 35 28 DEVRP SYSTOP to ROMBASE Region Properties Region properties for addresses less than ROMBASE bits 55 36 and addresses greater than or equal to SYSTOP bits 27 8 27 8 SYSTOP Top of System Memory Top of system memory that is available for general processor use The frame buffer and other
4. MM an XPIC and two Legacy 8259 compat ible PICs LPIC Initialization At reset the PIC subsystem comes up in legacy mode VSA initializes the XPIC to generate ASMI from GPIOs Devices on the XPIC are hard wired to Interrupt Groups IG in the MM and XPIC The XPIC is hooked to the LPIC on interrupts 0 1 3 15 The rest 16 64 are hooked to ASMI The XPIC has several incoming sources They are IRQ LPC Y and Z sources The Y sources include software USB RTC alarm audio power management NAND Flash SMB KEL and UARTs The Z sources include eight MFGPTs and eight GPIOs During PCI scan GeodeROM allocates memory I O and interrupts to the PCI devices This includes the virtual devices emulated by VSA VSA is responsible for the setup of the XPIC mapper for the devices it is virtualizing 4 2 4 2 Keyboard Emulation Logic KEL 1 2 Location NA Description Used for A20 support as well as USB keyboard emulation Initialization VSA technology 4 2 4 3 System Management Bus SMBus Location 6000h Description SMBus is an industry standard two wire serial interface The SMBus is essentially an ACCESS bus and is the interface used to read the DRAM SPD Initialization GeodeROM sets the LBAR with the desired location and the GPIOs for SMBus The recommended address SMBADDR is OEFh 4 2 4 4 GPIO and ICF Location 6100h Description There are 23 GPIOs in Working mode and 5 in Standby mode The GPIO registers are suc
5. Reset Register GLCP_SYS_RSTPLL GX GLCP MSR Address 4C000014h The GX processor has separate clocks for the CPU core and GeodeLink interface These clocks are derived from the sys tem PLL which is driven by the PCI clock At power on these clocks default to a safe value Setting the clock registers and doing a reset will re clock the GX processor The clocks are controlled by three divisors as shown in Figure 4 1 The Feed back Divisor FbDIV in the PLL sets sppl_raw_clk Sppl_raw_clk is divided by the GeodeLink Divisor MDIV and the CPU Divisor VDIV to derive GeodeLink clock and CPU clock Sppl_raw_clk must be between 300 MHz and 800 MHz The GeodeLink clock is used to clock the memory Therefore the GeodeLink clock should never be greater than the speed and type of the system memory All the divisor bits software bits memory type bit and reset bits are located in the GLCP_SYS_RSTPLL register Once the divisors and memory type DDR SDR are set the BIOS sets a reset flag and resets the CPU to continue initialization at the desired CPU speed GeodeROM sets the clocks based on jumper settings that are interpreted to match SKUs defined for that version of the CPU SKUs are defined by PCI speed memory type SDR or DDR and the jumper setting GeodeROM can also use FbDIV MDIV and VDIV values set by the user in CMOS for debugging If there is an incorrect setting in CMOS setup and the system cannot boot three times in a row GeodeROM rese
6. port address is further parsed into six 3 bit channel address fields Each 3 bit field represents from the perspective of the source module the GLIU channels that are used to get to the destination module starting from the closest GLIU to the source left most 3 bit field to the farthest GLIU right most 3 bit field When the GLIU gets the cycle it reads the three MSBs of the address register shifts those three bits of the 18 MSBs of the address register off and passes the transaction to the port indicated by the next three bits MSR addresses that are outside the module address spaces are invalid meaning RDMSR WRMSR instructions attempting to use the address within the CPU core will cause a General Protection Fault Unimplemented MSR accesses not in periph eral modules go to the bit bucket 3 1 1 Addressing Example GX Processor GeodeLink Modules Addresses Source CPU Core gt Destination GeodeLink Control Processor GLCP 2 3 0 0 0 0 gt 4C00xxxxh CS5535 Companion Device GeodeLink Module Addresses Source CPU Core gt Destination SB_GLCP 2 4 2 7 0 0 gt 5170xxxxh GLPCI acts like another GLIU 3 2 Descriptors Descriptors are used to route memory or I O resources through GLIUs to a GX processor module Memory and UO addresses that do not have descriptors are subtractively decoded through the GLIUs and out to the PCI It is important that no descriptors overlap each other The result is indeterminate 3 2 1 Memory Descrip
7. private memory areas are located above SYSTOP 7 0 SYSRP System Memory Region Properties Region properties for addresses less than SYS TOP bits 27 8 Note that Region Configuration 000A0000h 000FFFFFh takes prece dence over SYSRP Note Region Properties 7 6 Reserved 5 Write Serialize 4 Write Combine 3 Write through 2 Write Protect 1 Write Allocate O Cache Disable 18 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Initialization 32430C AMDA Registers CRO RCONF MSRs CPU Core MSR Address 00001808h 00001817h Instruction Memory Configuration Register CPU Core MSR Address 00001700h Data Memory Configuration Register CPU Core MSR Address 00001800h Entry Conditions None Procedure IF lt L1 cache requested gt Setup the Default Region Configuration Properties and any other RCONFs required Write Cache Disable and Not Write Through bits bits 30 29 in the CRO register WBINVD ENDIF Note See Figure 7 2 on page 31 for a pictorial presentation GLPCI Regions The GLPCI has similar MSRs to the CPU Core Region Configuration registers for inbound transactions These memory regions control the memory hole from 6460 KB to 1 MB Six flexible region MRSs are assigned Memory Region 0 Configu ration RO through Memory Region 5 Configuration R5 Descriptor Allocation Register PHY_CAP MSR Address GLIUO 10000086h GLIU1 40000086h Each GLIU descriptor allocat
8. the processor can use the RDMSR and WRMSR instructions and modules within the processor can use the GeodeLink MSR transactions The second method allows debug modules such as the System Navigator from FS First Silicon Solutions to program MSRs All MSRs are 64 bits wide The MSR addresses are 32 bits where each unique address refers to a 64 bit data quantity To communicate with modules on the GeodeLink interface the address of that module must be known Addresses are obtained by either scanning the GeodeLink interface or having prior knowledge of the chip topology This is discussed in detail in Section 3 0 GeodeLink Architecture on page 13 RDMSR Input ECX Address to read Output EDX EAX WRMSR Input 64 bits data returned ECX Address to write EDX EAX Output None 64 bits data written 2 1 Example MSR Transaction Read and write extended CPUID registers This example will change the CPUID RDMSR Load MSR specified by ECX into EDX EAX WRMSR Write the value in EDX EAX to MSR specified by ECX MSR_CPUIDO MSR_CPUID1 mov ecx RDMSR mov edx WRMSR mov ecx RDMSR mov edx WRMSR Done EQU 00003000h EQU 00003001h MSR_CPUIDO get values cdeR write edx eax to MSR in ecx No change to eax MSR_CPUID1 duol No change to eax AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 11 AMD 32430C Model Specif
9. 0018h MC_CF8F_DATA MSR Address 200001 9h MC_CFCLK_DBUG MSR Address 200001 Dh The memory controller in the GX processor supports SDRAM and DDR memory The memory controller and the RAM are programmed via settings read from the SPD The SPD is required for detection of PC66 PC100 PC133 and DDR RAM In the case of a closed system where the RAM is soldered to the motherboard and there is no SPD memory settings can be stored in CMOS for initialization The SDRAM clock is set up prior to reset by the clock initialization e Address bank registered unbuffered and other values read from the SPD Size memory in DIMM socket s Program Memory Controller Set default refresh to an appropriate value 16 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Initialization 32430C AMD d 4 1 3 1 Size Memory Entry Conditions 4 GB descriptor in FS Core register Procedure For each DIMM e Set the following in the MC_CFO7_DATA register MSR Address 20000018h Module Banks per DIMM SPD byte 5 Number of DIMM Banks Banks per SDRAM device SPD byte 17 Number of Banks on SDRAM device DIMM size Size Density Banks SPD byte 5 Number of DIMM Banks SPD byte 31 Module Bank Density Page size Page size 24 Column Addresses SPD byte 4 Number of Column Addresses Set CAS Latency in MC_CF8F_DATA register MSR Address 20000019h SPD byte 18 CAS Laten
10. AMD Geode AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide April 2006 Publication ID 32430C AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide O 2006 Advanced Micro Devices Inc All rights reserved The contents of this document are provided in connection with Advanced Micro Devices Inc AMD products AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice No license whether express implied arising by estoppel or otherwise to any intellectual property rights is granted by this publication Except as set forth in AMD s Standard Terms and Conditions of Sale AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to its products including but not limited to the implied warranty of mer chantability fitness for a particular purpose or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in systems intended for surgical implant into the body or in other applications intended to support or sustain life or in any other application in which the failure of AMD s product could create a situation where personal injury death or severe property or environmental damage may occu
11. as needed 4 2 4 8 Flash Interface Location 4 LBARs for 4 Flash devices Description NA Initialization The default values for the LBARs are located in BDCFG INC in the platform directory but can be changed at Boot via setup The Flash interface is configured in the code at ChipsetFlashSetup in CHIPSET ASM based on the corresponding NVRAM values 4 2 4 9 Other Legacy DD Initialization Location Default legacy definitions Description Initialize COM ports LPT ports RTC Initialization These devices are initialized in the same fashion as with a normal Superl O and CS5535 Any MSR reg ister settings will be done in chipset individualization GeodeROM can handle multiple devices and loca tions by design 22 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Initialization 32430C AMD d 4 2 4 10 DD I O Locations Table 4 2 Diverse Device I O Locations Location Device 0020h PIC Master Command and Status 0021h PIC Master Command and Status 0060h USB Keyboard and Mouse Data 0064h USB Keyboard and Mouse Command and Status KEL 0070h RTC Address 0071h RTC Data 00AOh PIC Slave Command and Status 00A1h PIC Slave Command and Status 02E8h UART IR COM4 02F8h UART IR COM2 03E8h UART IR COM3 03F8h UART IR COM1 04D0h PCI Level Edge IRQO 7 04D1h PCI Level Edge IRQ8 15 6000h SMBus 6100h GPIO and ICF 6200h General Purpose T
12. cy Turn on the memory interface in MC_CFCLK_DBUG bit MASK_CKE 1 0 MSR Address 2000001Dh 9 8 Do 12 refreshes CFO7_PROG_DRAM for the Memory Controller to synchronize Set the refresh rate of the DIMM SPD byte 12 Refresh Rate Type Load RDSYNC counter with sync value Note See the AMD Geode GX Processors Data Book publication ID 31505 for bit descriptions and allocation 4 1 4 Test Extended DRAM Entry Conditions 4 GB descriptor in FS Core register All memory configured Procedure Set GLIU descriptor to allow writes to memory e Make sure interface is turned on in MC_CFCLK_DBUG bit MASK_CKE 1 0 MSR Address 2000001 Dh 9 8 e Determine total amount of memory by doing a read write test For each 1 MB block of memory 1 Walk a 1 through data bus at first location of block 2 Walk a O through data bus at first location of block 3 Check for stuck address line in the block e Continue test if no memory present for debug purposes 4 1 5 GeodeLink Modules Initialization Descriptors routing memory and l O for GX processor modules are initialized by GeodeROM and Virtual System Architec ture VSA technology GeodeLink modules that are virtualized by VSA technology and use PCI memory or PCI I O report that resource in the virtual PCI header The GLIU is configured with MSRs like all GX processor modules AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 17 AMD d 32430C I
13. eode GX Processor CS5535 Companion Device GeodeROM Porting Guide 29 AMD 32430C 30 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Memory Map 324300 AMD Memory Map Figures 7 1 7 2 and 7 3 show the system memory Figure 7 1 is the GLIU Descriptor Map Figure 7 2 shows the Core Cache descriptors and Figure 7 3 on page 32 shows the Core cache region configurations Figure 7 4 on page 33 shows the flow of GeodeROM in the GX processor CS5535 system Memory Descriptors BM Base Mask BMO Base Mask Offset R Range RO Range Offset SC Swiss Cheese No Swiss Cheese Offset Figure 7 1 GLIU Descriptor Map FFFFFFFFh 4 GB ROM FFFC0000h Subtractive to PCI Subtractive to PCI Subtractive to PCI Subtractive to PCI Frame Buffer Offset 7 Memory Mapped Frame Buffer Video Descriptors A 50000000h RO VP GP DC Memory Mapped Video Registers VSA Offset Memory Mapped VSA 40400000h subtracted from Extended Memory Subtractive to PCI Frame Buffer Descriptors 5 BH Top of DRAM RO GLMC rame butter SMM Descriptor RO GLMC VSA m VSA and Video Memory Subtractive to PCI SysTop Descriptor R GLMC ics ES SE Two Shadow Descriptor SC GLMC Extended Memory A0000h DFFFFh E0000h 11FFFh Two Conv Desc BM MC system and Option ROMs A0000h 100000h 640 KB 1 MB
14. eodeROM Porting Guide Overview 32430C AMD d Overview 1 1 Introduction This document describes the changes needed for GeodeROM and other BIOSs to support the AMD Geode GX proces sor and the AMD Geode CS5535 companion device GeodeROM requires modifications for hardware initialization and specific implementations Each section targets the GeodeROM changes needed to support the GX processor CS5535 device system Where appro priate the changes list the Entry Conditions that briefly describe the machine state required to execute that function as well as some pseudo code for implementing the changes For more information on GeodeROM see the AMD Geode GeodeROM Functional Specification publication ID 32087 1 2 Assumption The following assumption must be made clear during the design phase GeodeROM expects all memory has a serial presence detect SPD to determine characteristics for memory controller ini tialization If a SPD is not present GeodeROM outputs a POST code and halts unless customizations have been made for the platform AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 9 AMD 32430C Assumption 10 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Model Specific Registers 32430C AMDA Model Specific Registers There are two ways to read or write Model Specific Registers MSRs in a Geode GX processor system Software run ning on
15. er and other critical graphics information stored in this area The memory is claimed in the Virtual PCI header 4 4 PCI Bus Initialization The GX processor does not incorporate a standard PCI bus controller The GX processor and CS5535 devices do not have PCI headers VSA emulates all the PCI headers and the GeodeLink is configured to route memory and I O for those mod ules This requires VSA to be initialized before PCI scan For Virtual PCI headers VSA sets GeodeLink descriptors and the Region Control Registers as requested by the modules during PCI scans PCI scan supports interrupt mapping and PCI Bridge support There is no plan for ISA PnP support at this time The PCI controller configuration registers are accessed through PCI type one configuration access mechanism using Ports CF8h and CFCh 24 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Initialization 32430C AMD d 4 5 Miscellaneous Initializations In addition to the previous processor initializations the graphics card s must also be initialized 4 5 1 Initialize Graphics Subsystem There are two different modes CRT and TFT Graphics initialization needs to identify which kind of support is required by reading an MSR in the Video Processor Entry Conditions 4 GB descriptor in FS core register GeodeLink descriptors initialized VSA initialized First MB of DRAM functional Interrupts enabled DMA initialized PCI bus functional
16. eset completed to a table of SKUs for each Get Core and GLIU revision of the CPU gt Settings from Jumper PLL settings can be set Settings or CMOS manually for debug Set All Clocks GLCP_SYS_RSTPPL CP Speed o MSR Addr 4C00014h PCI Clock Set PLL Flag DRAM Clock Setting from SPD C 3 Internal PLL Reset Figure 7 4 GeodeROM Flow GX Processor CS5535 Device AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 33 AMD 32430C Finish Post Setup Stack Enable Interrupts Shadow ROM Initialize and Enable Cache VSA Initialization System ROM Initialization Northbridge Initialization and CPU Bug Fixes PCI and Video Option ROM Initialization CS5535 descriptor set here after shadow Chipset Initialization Superl O Initialization Keyboard F1 Pressed Flag Reset Reboot INT 19 Setup Flag Reset Reboot Figure 7 4 GeodeROM Flow GX Processor CS5535 Device Continued 34 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Appendix A Support Documentation 32430C AM DA Support Documentation A 1 Document Revision History This section reports the revision creation process of the porting guide Any revis
17. h that there is no need to do read modify writes GPIO registers associated with bit settings are 32 bits Thus 16 GPIO may be changed at once These are organized into Low and High banks The Low bank deals with GPIOs 0 through 15 while the High bank deals with GPIOs 16 through 31 Be aware of specification update issue 113 in certain silicon revisions as of this writing see AMD Geode CS5535 Companion Device Specification Update Silicon Revision A3 publication ID 31534 After a suspend writing the register can not be done atomically Initialization VSA technology will set and use GPIOs connected with SMIs Many GPIOs are muxed with other signals and must be set up appropriately There is a GPIO INT and Power Management Event PME Mapper that maps GPIOs to the PIC and power management sub system 4 2 4 5 Multi Function General Purpose Timers MFGPTs Location 6200h Description Timers are used by VSA mostly The timers can set and be set by GPIOs The timers can output to non maskable interrupts and cause an ASMI through the XPIC with interrupts Initialization VSA technology AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 21 AMD d 32430C Initialization 4 2 4 6 ACPI Location 9C00h or other normal ACPI location Description NA Initialization ACPI VSM 4 2 4 7 Power Management Logic Location 9D00h put on the end of ACPI Description NA Initialization VSA technology and ACPI VSM
18. ialized by VSA technology GeodeLink modules can be scanned for their identification Non legacy GeodeLink modules that must be visi ble on the PCI bus will have PCI headers virtualized by VSA technology The GLIU is configured with MSRs like all GX pro cessor and CS5535 device modules VSA technology is also responsible for the Geode CS5535 descriptor allocation 4 2 4 Diverse Device Initialization The Diverse Device DD is a collection of new and legacy devices that are located in I O space and connected by the Local bus It is also the subtractive decode port of the CS5535 Any memory or I O not claimed by the DD is passed on to the Low Pin Count LPC bus The CS5535 has provided complete flexibility to put non legacy Local bus devices at any I O location by implementing Local BARs LBARs The following subsections show recommended locations in I O space to set the LBARs Devices that may be used before VSA is initialized will be set by GeodeROM 20 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Initialization 32430C AMD d 4 2 4 1 IRQ Mapper Location I O 20 21 master Programmable Interrupt Controller PIC MO AO A1 slave PIC I O 400 edge level PIC shadow register at MSR Address 51400034h The use of the IRQ Mapper LBAR is optional since it is always accessible via MSRs The LBAR is for the Mask and Mapper MM and the extended PIC XPIC Description The IRQ Mapper is a combination of a Mapper and Mask
19. ic Registers 12 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide GeodeLink Architecture 32430C AMD d GeodeLink Architecture GeodeLink architecture connects the internal modules of the AMD Geode GX processor using the data channels pro vided by GeodeLink Interface Units GLIUs GeodeLink modules are connected to GLIU ports 1 7 as shown in Figure 3 1 Port 0 is always the GLIU itself GLIUs can be chained together and up to a maximum of six GLIUs can be connected allowing for 32 modules CPU Core 3 Not Used VP 2 GP GLIUO GLIU1 AMD Geode ACC GX Processor 1 Not Used l 2 0 7 3 Not Used GLIU1 GLCP 1 GLCP l 5 6 Not Used 4 GIO AMD Geode j USBC2 5 Companion GLPCI Device GLPCI PCI Bus Figure 3 1 GeodeLink Architecture Topology AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 13 AMD d 32430C GeodeLink Architecture 3 1 GeodeLink MSR Addressing The GX processor s MSRs are addressed from the source module to the port of the target module The topology of the GX processor must be understood to derive the address An MSR address is parsed into two fields the port address 18 bits and the index 14 bits The
20. imers 6400h Flash BAR 6500h Flash BAR 6600h Flash BAR 6700h Flash BAR 9C00h ACPI Subdivide to support GX processor and CS5535 companion device 9D00h Power Management Logic Placed at the end of ACPI 4 2 5 ATA 5 Hard Drive Initialization Hard drive initialization is handled by a system ROM that is loaded by GeodeROM The hard drive ROM contains the hard drive initialization the PIO modes support and the interrupt support New to the hard drive ROM is the UDMA setup so that default drivers may be used in some operating systems The UDMA setup includes detecting the 80 conductor IDE cable for UDMA 66 support 4 2 6 Universal Serial Bus USB There are two Universal Serial Bus Controllers USBCs each containing a GeodeLink Adapter PCI Adapter and USB Core blocks The GeodeLink Adapter GLA translates GeodeLink transactions to from Local bus transactions The GLA interfaces to a 64 bit GLIU GeodeLink Interface Unit and a 32 bit Local bus The GLA supports in bound memory and I O requests which are converted by the PCI Adapter PA into PCI memory and I O requests that target the USBC It also sup ports in bound MSR transactions to the MSRs 4 2 7 AC97 Audio Controller Initialization The audio codec is initialized by the native audio driver The virtual PCI header contains the IRQ line The IRQ is set through the regular PCI initialization and IRQ mapping AMD Geode GX Processor CS5535 Companion Device Ge
21. ion is defined in the PHY_CAP register Descriptor MSR Address GLIUO GLIU1 P2D_BM 10000020h 00000000h 00007FFFh 00000000h 00007FFFh 10000021h 00080000h 0009FFFFh 00080000h 0009FFFFh 10000022h 4FFFCO00h 4FFFFFFFh 4FFFCO00h 4FFFFFFFh 10000023h 000A0000h 000BFFFFh 000A0000h 000BFFFFh 10000024h Not used by GeodeROM Not used by GeodeROM 10000025h Not used by GeodeROM Not used by GeodeROM P2D_BMO 10000026h 40400000h 4043FFFFh 40400000h 4043FFFFh 10000027h Not used by GeodeROM Not used by GeodeROM P2D_R 10000028h 00100000h 0E7BFFFFh 00100000h 0E7BFFFFh P2D_RO 10000029h 50000000h 517FFFFFh 50000000h 517FFFFFh 1000002Ah 4FFF8000h 4FFFBFFFh 4FFF8000h 4FFFBFFFh 1000002Bh Not used by GeodeROM Not used by GeodeROM P2D_SC 1000002Ch C000C7FFh EQOOFFFFh C000C7FFh EQOOFFFFh AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 19 AMD 324300 Initialization 4 2 AMD GeoderM CS5535 Companion Device Initialization The Geode CS5535 is a complete companion device to the GX processor The Geode 055535 incorporates the GeodeLink technology developed in the GX processor to make a transparent GeodeLink through the PCI to the CS5535 device The CS5535 companion device contains many of the components normally found on the Superl O chip GeodeROM and VSA2 technology initialize these components including the hard disk controller USB controllers GPIOs RTC SMBus Local bus and o
22. ions e additions deletions parameter corrections etc are recorded in the table s below Table A 1 Revision History Revision A PDF Date Revisions Comments A 30 Jun 2005 Initial release B 22 Mar 2006 The goal was to remove Confidential to make this an non NDA document Also incorporated other minor corrections See revision B for details 6 25 Apr 2006 e Section 4 0 Initialization on page 15 Several sub sections had incorrect MSR Addresses Most were 7 digits long instead of 8 missing a 0 Corrected these Section 4 2 4 8 Flash Interface on page 22 Changed 5535 ASM to CHIPSET ASM AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 35 AMD www amd com One AMD Place P O Box 3453 Sunnyvale CA 94088 3453 USA Tel 408 749 4000 or 800 538 8450 e TWX 910 339 9280 TELEX 34 6306
23. nitialization 4 1 5 1 GLIU Descriptors Initialization Register P2D_BM P2D_BMO P2D_R P2D_RO P2D_SC GLIUO MSR Address 10000020h 1000003Fh GLIU1 MSR Address 40000020h 1000003Fh DM IO_SC GLIUO MSR Address 100000E0h 100000FFh GLIU1 MSR Address 400000E0h 400000F Fh Set up system memory map with GeodeLink Descriptors and Region Control Registers RConfs Descriptors and RConfs must match each other These register maps will look like the memory map from INT 15h AX E820 The responsibility of setting Descriptors and RConfs is split between GeodeROM and VSA technology GeodeROM han dles settings for system memory and VSA memory Then the responsibility is handed off to VSA technology once it is loaded to handle all other memory and I O routing This is most notable in the frame buffer initialization See Memory Map Figure 7 2 on page 31 for a pictorial representation 4 1 5 2 GLIU Priority Initialization Each GeodeLink module has standard MSRs GLD_MSR_CONFIG is one of the standard registers located at address 2001h in the GX processor and 0001h in the CS5535 companion device Two fields in some of the GLD_MSR_CONFIG registers can affect the module priority Priority Level PRIO and Priority Domain PID These values default to zero In the case of data starvation or saturation on the GLIU GeodeROM can adjust these values as recommended by AMD 4 1 5 3 Cache Setup The GX processor has a 16 KB instruction cache and a 16
24. odeROM Porting Guide 23 AMD d 32430C Initialization 4 2 8 GeodeLink Control Processor Initialization The Geode CS5535 GLCP contains the diagnostic bus the JTAG interface clock south bridge control and power manage ment 4 3 Virtual System Architecture Initialization Virtual System Architecture VSA is the System Management Mode SMM software VSA virtualizes PCI BARs and head ers for GeodeLink modules as well as its normal functions described in the AMD Geode GeodeROM Functional Specifi cation publication ID 32087 4 3 1 Allocate Processor Frame Buffer and VSA2 Memory The GX processor employs a Unified Memory Architecture UMA meaning the frame buffer is allocated from the total sys tem memory The GeodeROM code programs the amount of system memory initially needed for VSA memory VSA can adjust the descriptors once it is loaded When internal video is enabled VSA allocates the frame buffer and graphics descriptors The amount of memory currently allowed for frame buffer use ranges from 4 to 16 MB To inhibit operating system DRAM detection code from reporting the frame buffer as part of system memory a GLIU offset descriptor is set to send transactions to the PCI bus and program Region Configuration Registers to set the region non cacheable This means that DOS Windows OS 2 and UNIX are never aware of the graphics memory portion of system memory This mapping prevents unwanted access to the graphics frame buff
25. pad is no longer needed either for BLT buffers or by the audio code for variable storage The scratchpad is not supported in the GX processor CPU Core 5 1 3 Post Codes Post codes are sent out to port 80 throughout GeodeROM A Post codes list is available in the AMD Geode GeodeROM Functional Specification publication ID 32087 to help users debug their problems AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 27 AMD 32430C Implementation 28 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Setup Options 324300 AMD Setup Options Initial configuration is set in the configurator at build time Based on those settings there are some setup options at runtime that are platform specific Check your platform specification for more details Desired Setup Options e Clock configuration complete control of system PLLs Default Use strap setting for core GeodeLink interface frequency is calculated based on DIMM type PM settings Default Off e Audio enable disable Default Enabled Video Primary Secondary Disabled Default Secondary Video Memory Size Default 24 MB Cache enable disable Default Write Back e MTest enable disable Default disabled e LPT enable disable Default 378 Note If a setting is incorrect and the system cannot boot three times CMOS is reset to the default setup options AMD G
26. plementation A dng nee e eer de ie dee ae apa e Se e E 27 27 6 0 Setup Options tia a A AR EE EE 29 7 0 Memory Mabe AAA a 31 Appendix A Support Documentation 35 AA Document Revision History 35 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 3 AMD d 32430C Contents 4 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide List of Figures 324300 AMD List of Figures Figure 3 1 GeodeLink Architecture Topology Y Y FIR 13 Figure 4 1 Clock Control eM rr daa a 15 Figure 7 1 GEIU Descriptor Map is zue EMS a AE Y 31 Figure 7 2 CPU Core Cache Descriptors o ooooccccococo ee 31 Figure 7 3 CPU Core Cache Region Configurations YF YF RE 32 Figure 7 4 GeodeROM Flow GX Processor CS5535 Device 2020 33 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 5 AMD 32430C List of Figures 6 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide List of Tables 32430C AMD List of Tables Table 4 1 Default Region Configuration Properties Bit Descriptions 18 Table 4 2 Diverse Device I O Locations F Y Y FI FI FF RF ua 23 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 7 AMD 324300 List of Tables 8 AMD Geode GX Processor CS5535 Companion Device G
27. r AMD reserves the right to discontinue or make changes to its products at any time without notice Trademarks AMD the AMD Arrow logo and combinations thereof and Geode GeodeLink Virtual System Architecture and XpressGRAPHICS are trademarks of Advanced Micro Devices Inc Windows is a registered trademark of Microsoft Corporation in the United States and or other jurisdictions Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies 2 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Contents 32430C AMD d Contents List of Figures eer gd ALA A et A AAA AS AA Y ele 5 Listof Tables ege Re oe EE cand REE eS 7 1 0 VOVENnVIEW Sa dina NG ad 9 TA Mntroduction ceu ae e a AAA A Ee od 9 1 2 ASSUMPTION voii ae ae Cae alos SA TRE ade aa 9 2 0 Model Specific Registers 11 2 1 Example MSR Transaction SEET eee p Peele eos Aa 11 3 0 GeodeLink Architecture seca ma aa ae cies YW EEN EINEN i ra OE ct n lt 13 3 1 GeodeLink MSR Addressing 14 KSE ul TC 14 4 0 InitialiZauony ida ARA EA 15 41 Processor Initialization Y FF FFF FFF Yu 15 4 2 AMD Geode CS5535 Companion Device Initialization 20 4 3 Virtual System Architecture Initialization 24 4 4 PCIBusinitialization 24 4 5 Miscellaneous InitializationS 25 5 07 Im
28. ther legacy components This chapter contains descriptions as well as some pseudo code for GX processor specific code sequences in GeodeROM The GX processor and CS5535 device do not implement com plete PCI bus controllers so GeodeLink modules that must be identified and configured by an operating system have their PCI configuration spaces virtualized by VSA 4 2 1 Chipset ID Hardware PCI Header ID 002A100Bh Virtual PCI Header ID 002B100bh 4 2 2 Set ID Select IDSEL The CS5535 companion device number is changeable by a 32 bit write once register located in I O space 0 By default the CS5535 is located at device 15 IDSEL AD25 To insure that it is not accidentally moved it must be programmed very early in post The External MSR Access Configuration Register GX GLPCI MSR Address 50000201Eh must match the device number to route MSR transactions across the PCI bus Example set IDSEL mov eax 02000000h A mov eax 04000000h s out 0000h eax H DSEL AD25 device 15 DSEL AD30 device 20 H set EXtMSR mov eax OFOFOFOFh device 15 mov edx 000FOFOFh device 15 mov eax 14141414h device 20 mov edx 00141414h device 20 mov ecx extMSR WRMSR 4 2 3 GLIU Initialization The CS5535 companion device contains one GLIU that connects up to six peripheral modules The GLIU routes memory and I O for the attached modules Descriptors controlling memory and UO for the attached modules are init
29. tor Types e Range Covers a memory range in 4 KB granularity Range Offset Covers a memory range in 4 KB granularity with the destination address translated by an offset Base Mask Covers a memory range that is a power of 2 in size Base Mask Offset Covers a memory range that is a power of 2 in size with the destination address translated by an offset Swiss Cheese Covers a 256 KB region split into 16 KB pieces to a module or the subtractive port 3 22 W O Descriptor Types Base Mask Covers an I O range that is a power of 2 in size Swiss Cheese Covers an 8 byte region split into 1 byte pieces to a module or the subtractive port 14 AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide Initialization 32430C AMD d Initialization 4 1 Processor Initialization The AMD Geode GX processor contains many of the components normally found in system support chipsets GeodeROM must set up these components including the DRAM controller L1 cache controller clock control and PCI con troller as well as some proprietary systems like GeodeLink architecture This chapter contains descriptions and some pseudo code for GX processor specific code sequences in GeodeROM The modifications are grouped into CPU core initialization DRAM controller initialization GeodeLink interface initialization PCI bus initialization and miscellaneous other initializations changes 4 1 1 Set Clocks and
30. ts CMOS to the defaults See Figure 7 4 on page 33 for example reset and system clock logic GLIU Clock MDIV SYSREF PCI Clock System PLL spil_raw clk 300 800 MHz 0 66 MHz Sep Clock CPU Core Clock gt vov Figure 4 1 Clock Control AMD Geode GX Processor CS5535 Companion Device GeodeROM Porting Guide 15 AMD d 32430C Initialization 4 1 2 Calculating Processor Speed Entry Conditions Stack and No Stack versions required 8254 timer available port 61 Procedure e Utilize the Real Time Stamp Counter RTSC e Disable the L1 cache Set up a channel of the 8254 Timer chip to count for a predetermined amount of time Read the CPU RTSC and save the initial count value Poll counter and wait for it to roll over Read the CPU RTSC and save as the final count e Subtract the initial value of the RTSC from the final value e EDX EAX now contains the number of clock ticks in the predetermined amount of time To get the value in MHz divide the number of clocks by the time represented in microseconds i e 5 ms 5000 4 1 2 1 CPU Identification The CPUID check should be done as soon as possible Use the CPUID instruction Check the Major and Minor Revision fields located in the GLCP_CHIP_REVID register MSR Address 4C000017h 7 0 for the silicon revision 4 1 3 Memory Controller Initialization Registers MC_CFO7_DATA MSR Address 200

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