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AMD ATHLON 8 User's Manual

1. Pin Name Description L P R Pin Name Description L P 619 NC Pin page 78 J5 NC Pin page 78 G21 NC Pin page 78 J7 VID 4 page79 O O G23 Key Pin page 78 J31 NC Pin page 78 G25 Key Pin page 78 J33 SDATA 19 G27 NC Pin page 78 J35 SDATAINCLK 1 P G29 NCPin page 78 J37 SDATA 29 HF G31 NC Pin page 78 K2 VSS G33 SDATA 20 P B K4 VSS G35 SDATA 23 B K6 VSS 657 SDATA 21 P B K8 NC Pin page 78 H2 Vcc_coRE K30 NC Pin page 78 H4 K32 H6 NC Pin page 78 K34 8 NC Pin page 78 K36 Vcc coRE H10 NCPin page 78 L1 VID 0 79 O O H12 L5 VID 1 79 O O H14 VSS L5 VID 2 page 79 010 H16 coRE L7 VID 5 79 O O H18 VSS L31 NC Pin page 78 H20 Vec coRE 133 SDATA 26 P B H22 VSS L35 NC Pin page 78 H24 Vcc coRE 137 SDATA 28 P B H26 VSS M2 Vcc H28 NC Pin page 78 M4 H30 NC Pin page 78 M6 H32 NC Pin page 78 M8 Vcc_coRE H34 VSS M30 H36 55 M32 VSS JI SADDOUT 0 page 79 P O M34 VSS 15 SADDOUT 1 page 79 P O Ms36 VSS 68 Pin Descriptions Chapter 11 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Table 25 Cross Reference by Pin Location continu
2. Pin Name Description L P R Pin Name Description L P R D10 VSS E33 NC Pin page 78 D12 Vcc coRE E35 SDATA 31 55 E37 SDATA D22 016 Vcc core F2 VSS 018 VSS F4 VSS D20 Vcc F6 VSS 022 55 F8 NC Pin page 78 D24 Vcc VSS D26 VSS F12 Vcc core D28 Vcc F14 VSS D30 VSS F16 coRE 032 Vcc F18 VSS D34 55 F20 Vcc conE 036 VSS F22 55 El SADDOUT 11 amp P O P F4 Vcc core ES SADDOUTCLK P O G F26 VSS E5 SADDOUTI4 P O P P Vcc core E7 SADDOUT 6 P O G 1750 NC Pin page 78 E9 SDATA 52 P B P F2 Vcc con EM SDATA 50 P B P 254 Vcc core E13 SDATA 49 P B G F36 Vc core E15 SDATAINCLK 3 SADDOUT 10 P O E17 SDATA 48 P B P G SADDOUI M s P O E19 SDATA 58 B GIIG SADDOUT 13 P O E21 SDATA 36 P B P G7 Key Pin page 78 E23 SDATA 46 B G9 Key Pin page 78 E25 NC Pin page 78 G11 NC Pin page 78 E27 SDATAINCLK 2 P 1 G 613 NCPin page 78 E29 SDATA 33 P B 15 KeyPin page 78 E31 SDATA 32 P B P GU Key Pin page 78 Chapter 11 Pin Descriptions 67 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet Table 25 Cross Reference by Pin Location continued 25175H March 2005
3. Abbreviation Full Name Pin Abbreviation Full Name Pin VCC Vcc_coRE AK34 VSS D22 VCC Vcc AK36 VSS D26 VCC Vcc AJ5 VSS D30 VCC Vcc 15 VSS D34 VCC Vcc AM2 VSS 056 VCC Vcc AM10 VSS F2 VCC Vcc AM14 VSS H VCC Vcc 18 VSS F6 VCC Vcc_coRE AM22 VSS F10 VCC Vcc_coRE AM26 VSS F14 VCC Vcc_coRE AM22 VSS F18 VCC Vcc_coRE AM26 VSS F22 VCC Vcc AM30 VSS F26 VCC Vcc AM34 VSS H14 VCCA AJ23 VSS H18 VID 0 L1 VSS H22 VID 1 13 VSS H26 VID 2 L5 VSS H34 VID 3 L7 VSS H36 VID 4 VSS K2 VREF S VREF SYS W5 VSS 4 VSS B2 VSS K6 VSS B6 VSS M30 VSS B10 VSS M32 VSS 14 VSS M34 VSS B18 VSS M36 VSS B22 VSS P2 VSS B26 VSS P4 VSS B30 VSS P6 VSS B34 VSS P8 VSS D6 VSS R30 VSS D10 VSS R32 VSS D14 VSS R34 VSS D18 VSS R36 Chapter 11 Pin Descriptions 63 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Table 24 Pin Name Abbreviations continued Table 24 Pin Name Abbreviations continued Abbreviation Full Name Pin Abbreviation Full Name Pin VSS T2 NS VSS T4 VSS AK2 VSS T6 VSS AK4 VSS T8 VSS AK12 VSS V30 VSS AK16 VSS V32 VSS AK20 VSS V34 VSS AK24 VSS V36 VSS AK28 VSS X2 VSS AK32 VSS X4 VSS AMA VSS X6 VSS AM6 VSS X8 VSS AM12 VSS 230 VSS AM16 VSS 232 VSS AM2
4. 2 w w ov av av av ov sv ve z A X M n 1 S 3 4 3 q s v 5 LE ons Lays 6 05 105 105 105 3 90 91805 81005 gards 6080 145 140005 LE Q 9t SSA SSA SSA DA SSA SSA DA SSA IDA SSA SSA SSA DA 9t 29 S cus INS LAYS 0 2005 vis 0 Ers WOS vits 140 3 1905 ETHOS 5 0 SE 4 o 13 SSA SSA DA SSA SSA DA SSA SSA SSA DA SSA SSA vt o DIS UNS sns 0465 8105 3 0015 sins 1805 VUOS STROS 92105 61805 0085 THEOS woos EE 5 43 SSA SSA SSA IN SSA DA SSA SSA DA SSA DA SSA DA DA 43 A 6 LE runs 1005 nns 0851 3 IN N N 3 3 3 3 IN N 0t 195 IN N SSA SSA DA SSA SSA N N N SSA SSA 0t a 66 uns Laws 085 M N 6 82 SSA SSA SSA N N DA 90 6 ow N IN NJ N 205 d 46 S 92 SSA SSA SSA SSA 9 SZ w N HMM N NJ IN D sei 60 C SSA SSA SSA SSA DA DA DA EZ DND N NJ 95 0 60 lt 44 DA DA A IDA SSA SSA SSA SSA 44 12 0 OLY um N N 9 05 95805 1 M 3IA apisuiojog 0 SSA SSA SSA SSA A DA DA 0 6L D N N 8 89005 69805 61 81 yA vA vA vA d dX Ww SSA SSA SSA SSA 81 30559201 ADD N NJ NJ 80005 08405 zoos 91 SSA SSA SSA SSA IDA DA DA 91 SI DM N NJ NJ EDIS 16805 esas Gl tl
5. AK30 Vcc AJ9 NC Pin page 78 AK32 VSS NC Pin page 78 AK34 Vcc core AJ Analog page 74 AK36 Vcc AJ15 NC Pin page 78 INTR page 77 P NC Pin page 78 FLUSH page 77 9 NC Pin page 78 7 core 21 CLKFWDRST page 74 P P 7 NC Pin page 78 29 115 25 VCCA page 79 AL9 NC Pin page 78 25 PLLBYPASS page 78 P I NCPin page 78 AJ27 NCPin page 78 PLLMON2 page78 O O AJ29 SADDIN 0J page79 P ALI5 PLLBYPASSCLK 78 AJ31 SFILLVALID P G CLKIN page 74 P AJ53 SADDINCLK P l G AL19 RSTCLK page 74 P AJ35 SADDIN 6 P P AL21 K7CLKOUT page 78 P O AJ37 SADDIN 3 P G AL23 CONNECT page 75 P 72 Pin Descriptions Chapter 11 Preliminary Information 25175H March 2003 Table 25 Cross Reference Pin Location AMD Athlon XP Processor Model 8 Data Sheet Table 25 Cross Reference by Pin Location Pin Name Description L P R Pin Name Description L P R 125 NC Pin page 78 NC Pin page 78 AL27 NC Pin page 78 PLLMONI page78 0
6. 50 10 3 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 0815 ette EXE e ERR ES 51 10 4 Part Number 27648 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID OOST eve exce RU EUR ENS EE EROS E 53 11 Pin Descriptions 55 11 1 Pin Diagram and Pin Name Abbreviations 55 11 27 OP ari PASisz 7 nae u h ak wau ERA am saki REI MM AR 65 11 3 Detailed Pin Descriptions 74 AZO MEF IT 74 AMD Pant 2555 Pe eal aa en Wie RAN ha dels 74 AMD Athlon System Bus Pins 74 Analog Pin vidi eed E Rs 74 APIC Pins PICCLK PICD 1 0 74 CLKEWDRSTIPin 9k Se ele BAe 74 4 Table of Contents Preliminary Information 25175H March 2005 AMD Athlon XP Processor Model 8 Data Sheet CLKIN RSTCLK SYSCLK Pins 74 CONNECT c pana au ERU T 75 COREFB 75 CPU 75 DBRDY 5 75 ata 75 FID S OT PINS 75 FSB 1 0 77 FEUSHE 5525 5226 EES 77 IGNNE sse q Aux ua s ku
7. 129 SADDIN 1 page79 P ANIS PLLBYPASSCLK page78 P I AL31 SDATAOUTVALID P O P CLKIN page 74 AL33 SADDIN 8 P 1 P 9 RSTCLK page 74 AL35 SADDIN 4 1 AN21 K7CLKOUT page78 0 AL37 SADDIN 10 P 1 G 25 PROCRDY AM2 Vcc AN25 NC Pin page78 AM4 VSS AN27 NC Pin page 78 AM6 VSS AN29 SADDIN 12 P l G AM8 NCPin page 78 s SADDIN 14 P l G AMIO SDATAINVALID P I P AM12 VSS AN35 SADDIN 13 P l G AM14 AN37 SADDIN 9 PIIIG 16 VSS 18 20 VSS 1 AM22 Bl Be 24 VSS 26 Vcc aj AM28 VSS S AM30 Vcc_coRE ed oes 32 VSS AM34 Vcc_core AM36 VSS page 78 AN3 NMI P 5 SMI P AN NCPin page 78 AN9 NCPin page 78 Chapter 11 Pin Descriptions 75 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 11 3 Detailed Pin Descriptions A20M Pin AMD Pin AMD Athlon System Bus Pins Analog Pin APIC Pins PICCLK PICD 1 0 CLKFWDRST Pin CLKIN RSTCLK SYSCLK Pins The information in this sectio
8. Chapter 1 Overview 3 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 4 Overview Chapter 1 Preliminary Information 25175H March 2005 2 AMD Athlon XP Processor Model 8 Data Sheet Interface Signals 2 1 2 2 This section describes the interface signals utilized by the AMD Athlon XP processor model 8 Overview The AMD Athlon system bus architecture is designed to deliver excellent data movement bandwidth for next generation x86 platforms as well as the high performance required by enterprise class application software The system bus architecture consists of three high speed channels a unidirectional processor request channel a unidirectional probe channel and a 64 bit bidirectional data channel source synchronous clocking and a packet based protocol In addition the system bus supports several control clock and legacy signals The interface signals use an impedance controlled push pull low voltage swing signaling technology contained within the Socket A socket For more information see AMD Athlon System Bus Signals on page 6 Chapter 11 Pin Descriptions on page 55 and the AMD Athlon System Bus Specification order 21902 Signaling Technology The AMD Athlon system bus uses a low voltage swing signaling technology that has been enhanced to provide larger noise margins reduced ringing and variable
9. N 1405 04015 H SSA SSA IN N N SSA DA SSA DA SSA DA SSA DA IN N IN DA IDA H 9 as EUAS 02405 N IN IN NJ NJ N N N NJ MJ EL OVS 9 1 DA yA DA N IDA SSA DA SSA DA SSA IDA SSA DA SSA N SSA SSA SSA d 3 5 1405 N unus N 9005 96405 8 80005 EDIS 6 09405 15 905 vits 015 5 1 SSA SSA DA SSA IDA SSA DA SSA DA SSA IDA SSA IDA SSA IDA SSA DA IDA d 2 10005 AH Sb 0S AH D 95405 65 09405 19405 N 220 velas 24015 84015 6801 10 8 SSA SSA SSA DA SSA SSA SSA DA SSA DA SSA DA SSA 8 V 0805 LA 2106 N Stats 6 0 1505 N 19805 59405 ESHOS 190 seis 015 60 V ze 9 se ve ce ze te oe ez ez zz ez sz vz ez ez iz oz ot af om st me et o 6 8 n 9 r z l Chapter 11 Tons t ip Pin Descri 56 Informat minary Prel apiswoyog WeISeIG Japoy 105592044 dX UOY LL
10. 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Table 25 Cross Reference by Pin Location continued Pin Name Description L P R Pin Name Description L R AD2 Vcc coRE AF30 NCPin page 78 Vcc coRE AF22 NCPin page 78 AD6 Vcc AD8 NCPin page78 AF36 Vcc core AD30 NCPin page 78 FERR page 75 P AD32 VSS AG RESET AD34 VSS AG NCPin page 78 AD36 VSS AG7 KeyPin page 78 1 20 P I 9 KeyPin page 78 PWROK P AG11 COREFB page 75 i AE5 ZP page 80 AGI3 COREFB page 75 3 AE7 AGI5 Key Pin page 78 AE31 NC Pin page 78 Key Pin page 78 AE33 SADDIN 5 P I G AG19 NCPin page 78 AE35 SDATAOUTCLK 0 P O P 2 NC Pin page 78 AE37 SDATA 9 P G AG23 NC Pin page 78 AF2 VSS 25 NC Pin page 78 AF4 VSS AG27 Key Pin page 78 AF6 NCPin page 78 AG29 Key Pin page 78 AF8 NC Pin page 78 FSB_Sense 0 page 77 G AF10 NC Pin page 78 AG33_ SADDIN 2 P G AF12 VSS AG35 SADDIN 11 P
11. 1 65 V 4 4A 376A 89A 54A 683W 620W Notes 1 2 See Figure 3 AMD Athlon XP Processor Model 8 Power Management States on page 9 The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the process and are not representative of the typical Stop Grant current that is currently about one third of the maximum specified current These currents occur when the AMD Athlon system bus is disconnected and has a low power ratio of 1 8 for Stop Grant disconnect and a low power ratio of 1 8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of 2003 1225 programmed into the Clock Control CLK Ctl MSR For more information refer to the AMD Athlon and AMD Duron Processors BIOS Software and Debug Developers Guide order 21656 The Stop Grant current consumption is characterized at 50 and not tested Thermal design power represents the maximum sustained power dissipated while executing publicly available software or instruction sequences under normal system operation at nominal Vcc Thermal solutions must monitor the temperature of the processor to prevent the processor from exceeding its maximum die temperature Chapter 6 Advanced 266 Front Side Bus AMD Athlon XP Processor Model 8 Specifications 23 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H
12. 4 The lumped ideality factor adds the effect of the series resistance term to the actual idealit factor The series resistance term indicates the resistance from the pins of the processor to the on die thermal diode The value of the lumped ideality factor depends on the sourcing current pair used 42 Electrical Data Chapter 8 Preliminary Information 25175H March 2005 Thermal Protection Characterization AMD Athlon XP Processor Model 8 Data Sheet The following section describes parameters relating to thermal protection The implementation of thermal control circuitry to control processor temperature is left to the manufacturer to determine how to implement Thermal limits in motherboard design are necessary to protect the processor from thermal damage is the temperature for thermal protection circuitry to initiate shutdown of the processor Tsp pgrAy is the maximum time allowed from the detection of the over temperature condition to processor shutdown to prevent thermal damage to the processor Systems that do not implement thermal protection circuitry or that do not react within the time specified by Tsp cause thermal damage to the processor during the unlikely events of fan failure or powering up the processor without a heat sink The processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal shutd
13. 66 Table 26 FID 3 0 Clock Multiplier Encodings 76 Table 27 Front Side Bus Sense Truth 77 List of Tables 9 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 Table 28 VID 4 0 Code to Voltage Definition 80 Table 29 Constants and Variables for the Ideal Diode Equation 83 Table 30 Constants and Variables Used in Temperature Offset Equations iei eres dee exe 84 Table31 5 89 T ble 332 Acronyms vv RI s Pe ERE E Re Cw 90 10 List of Tables Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Revision History Date Rev Description Public revision H of the AMD Athlon XP Processor Model 8 Data Sheet includes the following changes In Chapter 6 revised Table 2 Electrical and Thermal Specifications for Processors with a CPUID of 681 on page 23 m Chapter 12 revised Figure 18 OPN Example for the AMD Athlon XP Processor Model 8 on page 81 March 2003 H Public revision G of the AMD Athlon XP Processor Model 8 Data Sheet includes the following changes m In Chapter 6 revised Table 2 Electrical and Thermal Specifications for Processors with a CPUID of 681 on page 23 m Chapter 7 revised Table
14. Table 25 Cross Reference by Pin Location continued 25175H March 2003 Pin Name Description L P R Pin Name Description L P v30 VSS 76 Vcc core V32 VSS 78 V34 VSS 230 VSS V36 VSS 782 VSS WI FID 0 76 O O 734 VSS W FID 1 76 O O 756 VSS W5 VREFSYS page 80 P AAI DBRDY page 75 P O W7 NC Pin page 78 AA3 DBREQ page 75 P W31 NCPin page 78 AA5 W33 SDATAINCLK 0 P I G 7 KeyPin page 78 W35 SDATA 2 P B G AA NC Pin page 78 W37 SDATA I SDATA S X2 VSS AA35 SDATA 0 PB XA VSS 57 SDATA 13 6 VSS AB2 VSS X8 VSS 4 VSS X30 conr AB6 VSS 52 Vcc AB8 VSS X34 Vcc_core AB30 Vcc_corE X36 coRE AB32 Vcc comE Yl FID 2 page76 O O AB34 Vcc core FID 3 page 76 O O AB36 Vcc Y5 NC Pin page 78 ACI STPCLK page 79 P Y7 Key Pin page 78 AG PLLTEST page 78 Y31 NC Pin page 78 5 ZN page80 P Y33 NC Pin page 78 Y35 SDATA 3 P B G NC Pin page 78 Y37 SDATA 12 B SDATA 10 P B 72 core AC35 SDATA I4 P B Z4 AC37 SDATA 11 P B 70 Pin Descriptions Chapter 11 Preliminary Information
15. time without notice Trademarks AMD the AMD Arrow logo AMD Athlon AMD Duron and combinations thereof QuantiSpeed and 3DNow are trademarks of Advanced Micro Devices Inc HyperTransport is a licensed trademark of the HyperTransport Technology Consortium MMX is a trademark of Intel Corporation Windows is a registered trademark of Microsoft Corporation Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies Preliminary Information 25175H March 2005 AMD Athlon XP Processor Model 8 Data Sheet Contents Revision History 11 1 Overview v so Say mi 1 1 1 QuantiSpeed Architecture Summary 2 2 Interface Signals esr Re RUPTA RON NOR REE OR OR CHR 5 2 1 QOverVileW ee Sree die eee ES 5 2 2 Signaling 1 5 2 3 Push Pull PP Drivers 6 2 4 AMD Athlon System Bus 15 6 Logic Symbol Diagram 7 4 Power 9 4 1 Power Management States 9 Working 10 Halt States hs mte s ee eee peru 10 Stop Grant States uy 0 s u ee eee eee 10 Probe State HR eee eite eh dme 12 4 2 Connect
16. 16 locations are for processor type keying for forwards and backwards compatibility G7 G9 G15 G17 G23 G25 N7 Q7 Y7 AA7 AG7 AG9 AG15 AG17 AG27 and AG29 Motherboard designers should treat key pins like NC No Connect pins socket designer has the option of creating a top mold piece that allows key pins only where designated However sockets that populate all 16 key pins must be allowed so the motherboard must always provide for pins at all key pin locations See NC Pins for more information The motherboard should provide a plated hole for an NC pin The pin hole should not be electrically connected to anything NMI is an input from the system that causes a non maskable interrupt No pin is present at pin locations A1 and AN1 Motherboard designers should not allow for a PGA socket pin at these locations For more information see the AMD Athlon M Processor Based Motherboard Design Guide order 24363 PLLTEST PLLBYPASS PLLMON1 PLLMON2 PLLBYPASSCLK and PLLBYPASSCLK are the PLL bypass and test interface This interface is tied disabled on the motherboard All six pin signals are routed to the debug connector All four processor inputs PLLTEST PLLBYPASS PLLMON1 PLLMON2 are tied to corg with pullup resistors The PWROK input to the processor must not be asserted until all voltage planes in the system are within specification and all system clocks are running within specifica
17. 40 REF D9 12 71 13 26 S 1 455 2 375 E2 11 33 REF L 3 05 3 31 2 35 2 65 37 E4 787 8 42 N 455 E5 787 8 42 e 1 27 BSC E6 10 73 11 28 el 2 54 BSC E8 13 28 13 83 Mass 11 0 g REF E9 1 66 1 96 Note 1 Dimensions are given in millimeters 2 The mass consists of the completed package including processor surface mounted parts and pins Chapter 10 Mechanical Data 53 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 E6 E 1 E2 CHIP amp 9 12 E c A A 3 S2 A CORNE FD23 D4 t D5 TOP VIEW BOTTOM VIEW NOT TO SCALE PASSIVE COMPONENTS A2 COMPLIANT PADS L L 1 20 64 C A B A A 52999 SIDE VIEW GENERAL NOTES 1 All dimensions are specified in millimeters mm 2 Dimensioning and tolerancing per ASME Y14 5M 1994 This corner is marked with a triangle on both sides of the package identifies pin A1 corner and can be used for handling and orientation purposes Pin tips should have radius VEN Symbol M determines pin matrix size and N is number of pins x in front of package variation denotes non qualified package per AMD 01 002 3 7 The following features are not shown on drawings a Marking on die label on package b Laser elements c Die and passive fudicials 8 The die
18. 6 SYSCLK and SYSCLK AC Characteristics on page 28 In Chapter 10 renamed Table 21 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 680 on page 50 renamed Table 22 March 2003 G Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 681 on page 51 added Table 23 Part Number 27648 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 681 on page 53 renamed Figure 14 AMD Athlon XP Processor Model 8 Part Number 27291 OPGA Package on page 52 and added Figure 15 AMD Athlon XP Processor Model 8 Part Number 27648 OPGA Package on page 54 m In Chapter 12 revised Figure 18 OPN Example for the AMD Athlon XP Processor Model 8 on page 81 Public revision F of the AMD Athlon XP Processor Model 8 Data Sheet includes the following changes p In Chapter 6 revised Table 2 Electrical and Thermal Specifications for Processors with a CPUID of 681 on page 23 m In Chapter 8 revised Table 16 General AC and DC Characteristics on page 39 and Figure 12 General ATE Open Drain Test Circuit on page 41 December 2002 Public revision E of the AMD Athlon XP Processor Model 8 Data Sheet includes the following changes m In Chapter 6 revised Table 2 Electrical and Thermal Specifications for Processors with a CPUID of 681 on page 23 In Chapter 3 revis
19. 65 V Package Type D OPGA Model Number 1600 operates at 1400 MH22 1700 at 1467 MH22 1800 at 1533 MH22 1900 at 1600 MH22 2000 at 1667 MHz2 2100 at 1733 22 2200 at 1800 MHZ 2400 at 2000 MHZ 2600 at 2083 MHz or 2133 MHZ 2700 at 2167 MHz Maximum Power A Desktop Processor Architecture Segment AMD Athlon XP Processor Model 8 with QuantiSpeed Architecture for Desktop Products Notes 1 Spaces are added to the number shown above for viewing clarity only 2 This processor is available only with a 266 advanced FSB 3 This processor is available only with a 333 advanced FSB Figure 18 OPN Example for the AMD Athlon XP Processor Model 8 Chapter 12 Ordering Information 81 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 82 Ordering Information Chapter 12 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Appendix A Thermal Diode Calculations This section contains information about the calculations for the on die thermal diode of the AMD Athlon XP processor model 8 For electrical information about this thermal diode see Table 17 Thermal Diode Electrical Characteristics on page 42 Ideal Diode Equation The ideal diode equation uses the variables and constants defined in Table 29 Table 29 Constants and Variables for the Ideal Diode
20. AG5 PLTST PLLTEST AG NC AG19 PRCRDY PROCREADY AN23 NC AG21 PWROK AES NC AG23 RESET AG3 NC AG25 RCLK RSTCLK AN19 NC AH8 RCLK RSTCLK AL19 NC AJ7 SAHFO SADDIN 0 AJ29 NC AJ9 SAI 1 SADDIN 1 AL29 NC 1 2 SADDIN 2 AG33 NC AJ15 SAHES SADDIN 3 AJ37 NC SADDIN 4 AL35 Chapter 11 Pin Descriptions 59 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet Table 24 Pin Name Abbreviations continued 25175H March 2003 Abbreviation Full Name Pin Abbreviation Full Name Pin SAI 5 SADDIN 5 AE33 SD 3 SDATA 3 Y35 SAI 6 SADDIN 6 AJ55 SD 4 SDATA 4 U35 SAHF7 SADDIN 7 AG37 SD 5 SDATA 5 U33 SAI 8 SADDIN 8 AL33 SD 6 SDATA 6 37 SAI 9 SADDIN 9 AN37 SD 7 SDATA 7 533 SAI 10 SADDIN 10 AL37 SD 8 SDATA 8 AA33 SAI 11 SADDIN 11 AG35 SD 9 SDATA 9 AE37 SAHFI2 SADDIN 12 AN29 SD 10 SDATA 10 AC33 SAI 13 SADDIN 13 AN35 SD 11 SDATA 11 AG37 SADDIN 14 AN31 SD 12 SDATA 12 Y37 SAIC SADDINCLK AJ33 SD 13 SDATA 13 AA37 SAO 0 SADDOUT 0 SD 14 SDATA 14 AC35 SAO 1 SADDOUT 1 J3 SD 15 SDATA 15 4 535 SAO 2 SADDOUTD A C7 SD 16 SDATA 16 Q37 SAO 3 SADDOUT 3 A7 SD 17 SDATA 17 035 SAO 4 SADDOUT 4 E5 SD 18 SDATA 18 N37 SAO 5 SADDOUT 5 A5 SD 19 SDATA 19 J33 SAO 6 SADDOUT 6 E7 SD 20 SDATA 20 G33 SAO 7 SA
21. Abbreviations and 89 Related Publications llle 93 Table of Contents 5 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 6 Table of Contents Preliminary Information 25175H March 2005 AMD Athlon XP Processor Model 8 Data Sheet List of Figures Figure 1 Typical AMD Athlon XP Processor Model 8 System Block Diagram 59 e RE ER 3 Figure 2 Logic Symbol Diagram 7 Figure3 AMD Athlon XP Processor Model 8 Power Management States os uns ced Ws ec ge eae E 9 Figure 4 AMD Athlon System Bus Disconnect Sequence in the Stop Grant St te c su Rep es 14 Figure 5 Exiting the Stop Grant State and Bus Connect Sequence 15 Figure 6 Northbridge Connect State Diagram 16 Figure 7 Processor Connect State Diagram 17 Figure 8 SYSCLK Waveform 24 Figure9 SYSCLK Waveform 28 Figure 10 Voltage 35 Figure 11 SYSCLK and SYSCLK Differential Clock Signals 37 Figure 12 General ATE Open Drain Test Circuit 41 Figure 13 Signal Relationship Requirements During Power Up Sequence est Cede ea tate a a ater ss Ma 45 Figure 14 AMD Athlon XP
22. Assert CONNECT 5 PROCRDY is deasserted D Deassert CLKFWDRST 6 Aprobe needs service 7 PROCRDY is asserted Three SYSCLK periods after CLKFWDRST is deasserted Although reconnected to the system interface the 8 Northbridge must not issue any non NOP SysDC commands for a minimum of four SYSCLK periods after deasserting CLKFWDRST Figure 6 Northbridge Connect State Diagram 16 Power Management Chapter 4 Preliminary Information 25175H March 2005 AMD Athlon XP Processor Model 8 Data Sheet Connect 6 B 1 2 B Connect Pending 2 Disconnect Pending 5 Connect Pending 1 Disconnect 4 C Condition Action CONNECT is deasserted by the Northbridge for a A CLKFWDRST is asserted by the Northbridge previously sent Halt or Stop Grant special cycle B Issue a Connect special cyde Processor receives a wake up event and must cancel Return internal clocks to full speed and assert the disconnect request C PROCRDY 3 Deassert PROCRDY and slow down internal clocks Note Processor wake up event or CONNECT asserted by The Connect special cycle is only issued after a 4 Northbridge processor wake up event interrupt or 8e deassertion occurs If the AMD Athlon system 5 CLKFWDRST is deasserted by the Northbridge bus is connected so the Northbridge can probe the processor a Conn
23. CLKFR CLKFWDRST AJ21 KEY AG15 CLKIN ANT7 KEY AGT7 CLKIN ALT KEY AG27 CNNCT CONNECT AL23 KEY AG29 COREFB 19 COREFB AG13 NC A31 CPR CPU PRESENCEZ AK6 NC C13 DBRDY AAI NC E25 DBREQ AA3 NC 3 FERR AGI NC F8 FID 0 Wi NC F30 FID 1 W3 NC Gi FID 2 Yi NC 613 NC G19 FLUSH AL3 NC G21 FSBO FSB Sense 0 AG31 NC G27 FSBI FSB Sense 1 AH30 NC G29 IGNNE NC G31 INIT AJ3 NC H6 INTR H8 K7CO K7CLKOUT AL21 NC H10 K7CO K7CLKOUT 21 28 G7 NC H30 KEY G9 NC H32 KEY G15 NC J5 KEY G17 NC J31 KEY G23 NC K8 KEY G25 NC K30 KEY N7 NC L31 KEY Q7 NC 135 Y7 NC N31 58 Pin Descriptions Chapter 11 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Table 24 Pin Name Abbreviations continued Abbreviation Full Name Pin Abbreviation Full Name Pin NC 031 S31 NC AJ27 NC 051 NC AK8 NC U37 NC AL7 NC W7 NC AL9 NC W31 NC AL11 NC Y5 NC AL25 NC Y31 NC AL27 NC Y33 NC AM8 NC AA5 NC AN7 NC AA31 NC AN9 NC AC7 NC ANTI NC AC31 NC AN25 NC AD8 NC AN27 NC AD30 NMI AN3 NC AE7 PICCLK NI NC AEST PICD 0 PICD O AF6 PICD 1 N5 NC AF8 PLBYP PLLBYPASS AJ25 NC AF10 PLBYC PLLBYPASSCLK 15 28 PLBYC PLLBYPASSCLK 15 NC AF30 PLMNI PLLMON1 AN13 NC AF32 PLMN2 PLLMON2 AL13 NC
24. FID 3 0 DC Characteristics on page 33 and Table 19 APIC Pin AC and DC Characteristics on page 44 In Chapter 10 revised Table 21 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 680 on page 50 and Table 22 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 681 on page 51 In Chapter 12 revised Figure 18 OPN Example for the AMD Athlon XP Processor Model 8 on page 81 August 2002 Public revision C of the AMD Athlon XP Processor Model 8 Data Sheet includes the following changes In Chapter 5 revised Figure 2 Logic Symbol Diagram on page 7 In Chapter 6 added Table 1 Electrical and Thermal Specifications for Processors with a CPUID of 680 on page 22 and Table 2 Electrical and Thermal Specifications for Processors with a CPUID of 681 on page 23 In Chapter 8 revised Table 8 Interface Signal Groupings on page 31 In Chapter 10 added Table 21 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 680 on page 50 and Table 22 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 681 on page 51 In Chapter 11 revised Figure 16 AMD Athlon XP Processor Model 8 Pin Diagram Topside View on page 56 Figure 17 AMD Athlon XP Processor Model 8 Pin Diagram Bottomside View on page 57 Table 24
25. IDA IDA DA IDA SSA SSA SSA SSA tl EL inma dno N 6005 N esas El SSA SSA SSA SSA A DA DA DA al LL ow N N 8300 N 08405 540005 was LL 01 A DA N N SSA SSA SSA 01 6 N N NJ 1905 velas saa 6 3 3 SSA DA SSA SSA SSA DA N 3 DA DA 8 Li 3 NJ 3 IN NJ N JOHL vaut I elon gt OVS uns eos 4 9 SSA AD aw IN DA SSA DA SSA SSA SSA DA SSA N SSA SSA SSA 9 E e S ams NZ 3 sm DONS NSIOS 04 3 0 80 sws t SSA SSA DA SSA DA SSA DA SSA DA SSA SSA DA SSA DA SSA yA t e 5 13594 NOUN 1504 0940 Jou n SWL 18015 10 0015 60 6 SSA SSA DA SSA DA SSA SSA SSA DA SSA SSA SSA 5 l UNI Wi 45 Aqua 1 DDNS DL yu olan 0405 0405 110 1015 l N nv w w ov av ov i sv ve z a X M 1 1 i 3 q a v N 57 ions t ip Pin Descri Chapter 11 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet Table 24 Pin Name Abbreviations 25175H March 2003 Abbreviation Full Name Pin Abbreviation Full Name Pin A20M AE1 KEY AA7 AMD AH6 KEY AG7 ANLOG ANALOG AG9
26. March 2003 6 2 Advanced 266 FSB AMD Athlon XP Processor Model 8 SYSCLK and SYSCLK AC Characteristics Table 3 shows the SYSCLK SYSCLK differential clock AC characteristics of this processor Table 3 SYSCLK and SYSCLK AC Characteristics Symbol Parameter Description Minimum Maximum Units Notes Clock Frequency 50 133 MHz 1 Duty Cycle 30 70 t Period 75 ns 2 3 b High Time 1 05 ns t Low Time 1 05 ns ty Fall Time 2 ns t Rise Time 2 ns Period Stability 300 ps Notes 1 The AMD Athlon system bus operates at twice this clock frequency 2 Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed loop jitter bandwidth to allow the PLL to track the jitter The 20dB attenuation point as measured into a 20 or 30 pF load must be less than 500 kHz 3 Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency spread spectrum clock generators In no cases can the AMD Athlon system bus period violate the minimum specification above AMD Athlon system bus clock inputs can vary from 10096 of the specified frequency to 9996 of the specified frequency at a maximum rate of 100 kHz Figure 8 shows a sample waveform of the SYSCLK signal Vrhreshold AC Figure 8 SYSCLK Waveform 24 Advanced 266 Front Side Bus AMD Athlon XP Processor Model 8 Specifications Chapter 6 Prel
27. Pin Name Abbreviations on page 58 Table 25 Cross Reference by Pin Location on page 66 and added FSB Sense 1 0 Pins page 71 and Table 27 Front Side Bus Sense Truth Table on page 77 In Chapter 12 revised Figure 18 OPN Example for the AMD Athlon XP Processor Model 8 on page 81 June 2002 First public release of the AMD Athlon XP Processor Model 8 Data Sheet 12 Revision History Preliminary Information 25175H March 2005 AMD Athlon XP Processor Model 8 Data Sheet Overview The AMD Athlon XP processor model 8 with QuantiSpeed architecture powers the next generation in computing platforms delivering extreme performance for Windows XP The AMD Athlon XP processor model 8 based on leading edge 0 13 micron technology integrates the innovative design and manufacturing expertise of AMD to deliver improved performance lower power and smaller die size while maintaining the stable and compatible Socket A infrastructure of the AMD Athlon processor Delivered in an OPGA package the AMD Athlon XP processor model 8 delivers the integer floating point and 3D multimedia performance for highly demanding applications running on x86 system platforms The AMD Athlon XP processor model 8 delivers compelling performance for cutting edge software applications that include high speed Internet capability digital content creation digital photo editing digit
28. and Bus Connect Sequence The following sequence of events removes the processor from the Stop Grant state and connects it to the system bus 1 The Southbridge deasserts STPCLK informing the processor of a wake event When the processor recognizes STPCLK deassertion it exits the low power state and asserts PROCRDY notifying the Northbridge to connect to the bus The Northbridge asserts CONNECT 4 The Northbridge deasserts CLKFWDRST synchronizing the forwarded clocks between the processor and the Northbridge The processor issues a Connect special cycle on the system bus and resumes operating system and application code execution Chapter 4 Power Management 15 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet Connect State 25175H March 2005 Figure 6 below and Figure 7 on page 17 show the Northbridge Diagram and processor connect state diagrams respectively 4 A 2 Disconnect Disconnect Pending Requested 5 B Disconnect Reconnect Pending Pending 2 6 C Probe 7 D Pending 1 Condition Action 1 A disconnect is requested and probes still pending A Deassert CONNECT eight SYSCLK periods 2 A disconnect is requested and no probes are pending after last SysDC sent 3 A Connect special cycle from the processor Assert CLKFWDRST 4 No probes are pending C
29. and CLKFWDRST 5 Tea 15 RSTCLK rising edge to output valid for PROCRDY Test Load is 25 pF 6 Tsy ts setup of CONNECT CLKFWDRST to rising edge of RSTCLK Typ is hold of CONNECT CLKFWDRST from rising edge of RSTCLK Chapter 7 Advanced 333 Front Side Bus AMD Athlon XP Processor Model 8 Specifications 29 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 30 Advanced 333 Front Side Bus AMD Athlon XP Processor Model 8 Specifications 7 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 8 Electrical Data This chapter describes the electrical characteristics that apply to all desktop AMD Athlon M XP processors model 8 8 1 Conventions The conventions used in this chapter are as follows m Current specified as being sourced by the processor is negative m Current specified as being sunk by the processor is positive 8 2 Interface Signal Groupings The electrical data in this chapter is presented separately for each signal group Table 8 defines each group and the signals contained in each group Table8 Interface Signal Groupings Signal Group Signals Notes See Advanced 266 FSB AMD Athlon System Bus AC SADDIN 14 2 SADDOUT 14 2 SADDINCLK SADDOUTCLK Characteristics on page 25 AMD Athlon SFILLVAL SDATAINVAL SDATAOUTVAL SDATA 63 0 Advanced 333 FS
30. and Disconnect Protocol 12 Connect Protocol Be eure 12 Connect State Diagram 16 4 3 Clock Control tayuq INE OU 18 CPUID Support 22 19 Advanced 266 Front Side Bus AMD Athlon XP Processor Model 8 Specifications 21 6 1 Part Specific Electrical and Thermal Specifications for Advanced 266 FSB AMD Athlon XP Processors SZ ra 21 6 2 Advanced 266 FSB AMD Athlon XP Processor Model 8 SYSCLK and SYSCLK AC Characteristics 24 6 3 Advanced 266 FSB AMD Athlon System Bus AC Characteristics 25 7 Advanced 333 Front Side Bus AMD Athlon XP Processor Model 8 Specifications 27 7 1 Electrical and Thermal Specifications for the Advanced 333 FSB AMD Athlon XP Processor Model 8 27 7 2 Advanced 333 FSB AMD Athlon XP Processor Model 8 SYSCLK SYSCLK AC Characteristics 28 7 3 Advanced 333 FSB AMD Athlon System Bus AC Characteristics 29 Table of Contents 3 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 8 Electrical Data cx ER ee Doce NORMEN 31 8 1 ConventiOns ix yapu OEE OR EEE a 31 8 2 Interface Signal Groupings 31 8 3 Voltage Identi
31. and the processor resumes execution at the instruction boundary where STPCLK was initially recognized If RESET is sampled asserted during the Stop Grant state the processor exits the Stop Grant state and the reset process begins There are two mechanisms for asserting STPCLK hardware and software The Southbridge can force STPCLK assertion for throttling to protect the processor from exceeding its maximum case temperature This is accomplished by asserting the THERM input to the Southbridge Throttling asserts STPCLK for a percentage of a predefined throttling period STPCLK is repetitively asserted and deasserted until THERM is deasserted Software can force the processor into the Stop Grant state by accessing ACPI defined registers typically located in the Southbridge The operating system places the processor into the C2 Stop Grant state by reading the P_LVL2 register in the Southbridge If an ACPI Thermal Zone is defined for the processor the operating system can initiate throttling with STPCLK using the ACPI defined P_CNT register in the Southbridge The Northbridge connects the AMD Athlon system bus and the processor enters the Probe state to service cache snoops during Stop Grant for C2 or throttling In C2 probes are allowed as shown in Figure 3 on page 9 Chapter 4 Power Management II Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 Probe S
32. is centered on the package Figure 15 AMD Athlon XP Processor Model 8 Part Number 27648 OPGA Package 54 Mechanical Data Chapter 10 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 11 Pin Descriptions This chapter includes pin diagrams of the organic pin grid array OPGA for the AMD Athlon XP processor model 8 a listing of pin name abbreviations and a cross referenced listing of pin locations to signal names 11 1 Pin Diagram and Pin Name Abbreviations Figure 16 on page 56 shows the staggered pin grid array PGA for the AMD Athlon XP processor model 8 Because some of the pin names are too long to fit in the grid they are abbreviated Figure 17 on page 57 shows the bottomside view of the array Table 24 on page 58 lists all the pins in alphabetical order by pin name along with the abbreviation where necessary Chapter 11 Pin Descriptions 55 Informat minary Prel AMDA 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet pisdol 8 EPO 105592014 dX GINV 91 40814 ze 9 se ze oe 62 ez o sz ez z o for fer a fo
33. maximum sustained power dissipated while executing publicly available software or instruction sequences under normal system operation at nominal Vcc Thermal solutions must monitor the temperature of the processor to prevent the processor from exceeding its maximum die temperature 22 Advanced 266 Front Side Bus AMD Athlon XP Processor Model 8 Specifications Chapter 6 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Table 2 shows the part specific electrical and thermal specifications in the C0 working state and the S1 Stop Grant state for processors with a CPUID 681 Table 2 Electrical and Thermal Specifications for Processors with a CPUID of 681 TERA Icc Processor Current A on Working State Stop Grant S1 2 3 4 Semper ge Maximum Typical Maximum Typical Maximum Typical 1400 1600 1 60 V 303A 275A 8 1A 49A 485W 44 011 1 50 V 329A 29 9 54 3 9 A 49 4 W 44 9 W 1 60 V 30 9 28 0 8 1 A 4 9 49 4 W 44 9 W 1 50 V 34 0 30 9 54 3 9 51 0 W 46 3 W 90 59218005 1 60 V 31 9 A 28 9 A 8 1 A 4 9 51 0 W 46 3 W 1667 2000 1 60 V 377A 342A 81A 49A 60 3W 547W 1733 2100 1 60 V 388A 349A 8 1 A 49A 621W 55 9W 1800 2200 1 60 V 393A 356A 81A 49A 628W 570W 2000 2400 1 65 V 376A 8 9A 54A 683W 62 0W 85 C 2133 2600
34. same frequency though the processor is capable of other configurations 14 Time to valid is for any open drain pins See requirements 7 and 8 in the Power Up Timing Requirements chapter for more information Chapter 8 Electrical Data 39 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet Table 16 General AC and DC Characteristics continued 25175H March 2003 Symbol Parameter Description Condition Min Max Units Notes Tpit Input Time to Acquire 20 0 ns 7 8 Input Time to Reacquire 40 0 ns 9 13 TRISE Signal Rise Time 1 0 3 0 V ns 6 Signal Fall Time 1 0 3 0 V ns 6 Pin Capacitance 4 12 pF TvALID Time to data valid 100 ns 14 Notes 1 Characterzed across DC supply voltage range 2 Values specified at nominal Scale parameters between minimum maximum 3 Io and are measured at Vo maximum and Voy minimum respectively 4 Synchronous inputs outputs are specified with respect to RSTCLK and RSTCK at the pins 5 These are aggregate numbers 6 Edge rates indicate the range over which inputs were characterized Z lnasynchronous operation the signal must persist for this time to enable capture 8 This value assumes RSTCLK period is 10 ns gt TBIT 2 fRST 9 The approximate value for standard case in normal mode operation 10 This value is dependent on RSTCLK freq
35. shows the relationship between key signals in the Timing Description system during a power up sequence This figure details the requirements of the processor 3 5 V Supply f VCCA 2 5 V for PLL Warm reset condition RESET 1 RA i 27 NB_RESET WWW PWROK FID 5 0 System Clock Figure 13 Signal Relationship Requirements During Power Up Sequence Notes 1 Figure 13 represents several signals generically by using names not necessarily consistent with any pin lists or schematics 2 Requirements 1 8 in Figure 13 are described in Power Up Timing Requirements on page 46 Chapter 9 Signal and Power Up Requirements 45 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Power Up Timing Requirements The signal timing requirements are as follows 1 RESET must be asserted before PWROK 15 asserted The AMD Athlon XP processor model 8 does not set the correct clock multiplier if PWROK is asserted prior to a assertion It is recommended that RESET be asserted at least 10 nanoseconds prior to the assertion of PWROK In practice a Southbridge asserts RESET milliseconds before PWROK is asserted 2 All motherboard voltage planes must be within specification before PWROK is asserted PWROK is an output of the voltage regulation circuit on the motherboard PWROK indicates that and all other voltage pla
36. system clocks are designed to be running after 3 3 V has been within specification for three milliseconds PWROK assertion to deassertion of The duration of RESET assertion during cold boots is intended to satisfy the time it takes for the PLL to lock with a less than 1 ns phase error The processor PLL begins to run after PWROK is asserted and the internal clock grid is switched from the ring oscillator to the PLL The PLL lock time may take from hundreds of nanoseconds to tens of microseconds It is recommended that the minimum time between PWROK assertion to the deassertion of RESET be at least 1 0 milliseconds Southbridges enforce a delay of 1 5 to 2 0 milliseconds between PWRGD Southbridge version of PWROK assertion and NB_RESET deassertion PWROK must be monotonic and meet the timing requirements as defined in Table 16 General AC and DC Characteristics on page39 The processor should not switch between the ring oscillator and the PLL after the initial assertion of PWROK NB_RESET must be asserted causing CONNECT to also assert before RESET is deasserted In practice all Southbridges enforce this requirement If NB RESET does not assert until after RESET has deasserted the processor misinterprets the CONNECT assertion due to NB RESET being asserted as the beginning of the SIP transfer There must be sufficient overlap in the resets to ensure that CONNECT is sampled asserted by the processor
37. xx xx00 is in the least significant byte position little end In byte diagrams bit positions are numbered from right to left the little end is on the right and the big end is on the left Data structure diagrams in memory show low addresses at the bottom and high addresses at the top When data items are aligned bit notation on a 64 bit data bus maps directly to bit notation in 64 bit wide memory Because byte addresses increase from right to left strings appear in reverse order when illustrated Bit Ranges In text bit ranges are shown with a dash for example bits 9 1 When accompanied by a signal or bus name the highest and lowest bit numbers are contained in brackets and separated by a colon for example AD 31 0 Bit Values Bits can either be set to 1 or cleared to 0 Hexadecimal and Binary Numbers Unless the context makes interpretation clear hexadecimal numbers are followed by an h and binary numbers are followed by a b 88 Appendix B Conventions and Abbreviations Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Abbreviations and Acronyms Table 31 contains the definitions of abbreviations used in this document Table 31 Abbreviations Abbreviation Meaning A Ampere F Farad G Giga Gbit Gigabit Gbyte Gigabyte GHz Gigahertz H Henry h Hexadecima
38. 0 VSS 234 VSS AM24 VSS 756 VSS AM28 VSS AB2 VSS AM32 VSS AB8 VSS AM36 VSS AB4 ZN AG VSS AB6 ZP AE5 VSS AD32 VSS AD34 VSS AD36 VSS AF2 VSS AF4 VSS AF12 VSS AF16 VSS AH12 VSS AH16 VSS AH20 VSS AH24 VSS AH28 VSS AH32 VSS AH34 64 Pin Descriptions Chapter 11 Preliminary Information 25175H March 2005 11 2 AMD Athlon XP Processor Model 8 Data Sheet Table 25 on page 66 cross references Socket pin location to signal name The L Level column shows the electrical specification for this pin P indicates a push pull mode driven by a single source indicates open drain mode that allows devices to share the pin Note The AMD Athlon processor supports push pull drivers For more information see Push Pull PP Drivers on page 6 The P Port column indicates if this signal is an input output O or bidirectional B signal The R Reference column indicates if this signal should be referenced to VSS G Vcc core P planes for the purpose of signal routing with respect to the current return paths Chapter 11 Pin Descriptions 65 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet Table 25 Cross Reference by Pin Location 25175H March 2005 Pin Name Descrip
39. 06 REF S 1 455 2 375 2 35 2 65 L 3 05 3 31 E4 787 8 42 M 37 E5 787 8 42 N 453 E6 10 73 11 28 e 1 27 BSC E7 10 75 11 28 el 2 54 BSC E8 13 28 13 85 Mass 11 0 g REF Note 1 Dimensions given in millimeters 2 The mass consists of the completed package including processor surface mounted parts and pins 50 Mechanical Data Chapter 10 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 10 3 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 681 For AMD Athlon XP processors model 8 with a CPUID of 681 Table 22 shows the 27291 OPGA package dimensions in millimeters assigned to the letters and symbols used in the 27291 package diagram Figure 14 on page 52 Table 22 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 681 Letter or Minimum Maximum Letter or Minimum Maximum Symbol Dimension Dimension Symbol Dimension Dimension D E 49 27 49 78 E9 1 66 1 96 DI E1 45 72 BSC G H 4 50 D2 7 47 REF A 1 942 REF 03 3 30 3 60 Al 1 00 1 20 04 10 78 11 33 A2 0 80 0 88 D5 10 78 11 33 A3 0 116 D6 8 15 8 68 A4 Z 1 90 D7 12 33 12 88 oP 6 60 D8 3 05 3 35 ob 0 43 0 50 D9 12 71 15 26 Qb1 1 40 REF E 11 55 REF S 1 455 2 375 2 35 2 65 L 3 05 3 31 E4 787 8 42 M 37 E5 787 8 42 N
40. 14 5M 1994 This corner is marked with a triangle on both sides of the package to identify the pin A1 corner for orientation purposes Pin tips should have radius Symbol M determines pin matrix size and N is number of pins For staggered pin configuration pins on the same row are on a 2 54 mm grid Adjacent rows offset by 1 27 mm Figure 14 AMD Athlon XP Processor Model 8 Part Number 27291 OPGA Package 52 Mechanical Data Chapter 10 Preliminary Information 25175H March 2003 10 4 AMD Athlon XP Processor Model 8 Data Sheet Part Number 27648 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 681 For AMD Athlon XP processors model 8 with a CPUID of 681 Table 23 shows the part number 27648 OPGA package dimensions in millimeters assigned to the letters and symbols used in the 27648 package diagram Figure 15 on page 54 Table 23 Part Number 27648 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 681 Letter or Minimum Maximum Letter or Minimum Maximum Symbol Dimension Dimension Symbol Dimension Dimension D E 49 27 49 78 G H 4 50 DWEI 45 72 BSC A 1 917 REF D2 7 47 REF A1 0 977 1 177 03 3 30 3 60 A2 0 80 0 88 D4 10 78 11 55 0 116 D5 10 78 11 33 A4 1 90 D6 8 15 8 68 6 60 D7 12 33 12 88 ob 0 45 0 50 D8 3 05 3 55 Qb1 1
41. 2 for more information about Serialization Initialization Packets and SIP protocol The processor FID 3 0 outputs are open drain and 2 5 V tolerant To prevent damage to the processor if these signals are pulled High to above 2 5 V they must be electrically Isolated from the processor For information about the FID 3 0 isolation circuit see the AMD Athlon Processor Based Motherboard Design Guide order 24363 76 Pin Descriptions Chapter 11 Preliminary Information 25175H March 2005 FSB Sense 1 0 Pins FLUSH Pin IGNNE Pin INIT Pin INTR Pin JTAG Pins AMD Athlon XP Processor Model 8 Data Sheet See Frequency Identification FID 3 0 on page 33 for the DC characteristics for FID 3 0 FSB Sense 1 0 pins are either open circuit logic level of 1 or are pulled to ground logic level of 0 on the processor package with a 1 resistor In conjunction with a circuit on the motherboard these pins may be used to automatically detect the front side bus FSB setting of this processor Proper detection of the FSB setting requires the implementation of a pull up resistor on the motherboard Refer to the AMD Athlon Processor Based Motherboard Design Guide order 24363 and the technical note FSB Sense Auto Detection Circuitry for Desktop Processors order TN26673 for more information Table 27 is the truth table to determine the FSB of desktop processors Table 27 Front Side Bus Sense Tru
42. 4 shows the equation for calculating temperature offset in sensors that do not employ series resistance cancellation T Taie spec 273 15 1 ET n a 4 offset hy TS Equation 5 is the temperature offset for temperature sensors that utilize series resistance cancellation Add the result to the value measured by the temperature sensor Note that the value of ng rs in Equation 5 may not equal the value used in Equation 4 T Tiie mee T 273 15 1 2 offset n TS Appendix A Thermal Diode Calculations 85 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 86 Appendix A Thermal Diode Calculations Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Appendix B Conventions and Abbreviations Signals and Bits This section contains information about the conventions and abbreviations used in this document Active Low Signals Signal names containing a pound sign such as SFILL indicate active Low signals They are asserted in their Low voltage state and negated in their High voltage state When used in this context High and Low are written with an initial upper case letter Signal Ranges In a range of signals the highest and lowest signal numbers are contained in brackets and separated by a colon for example D 63 0 Reserved Bits and Signals Signals
43. 4 1 Note 4014 SUIWODU This chapter describes the power management control system of the AMD Athlon XP processor model 8 The power management features of the processor are compliant with the ACPI 1 0b and ACPI 2 0 specifications Power Management States The AMD Athlon XP processor model 8 supports low power Halt and Stop Grant states These states are used by advanced configuration and power interface ACPI enabled operating systems for processor power management Figure 3 shows the power management states of the processor The figure includes the ACPI Cx naming convention for these states Execute HLT 84110141 10 219151891 PRY 5 12415 aqoJd p2HUesseop 12415 Incoming Probe Stop Grant Cache Snoopable Stop Grant Cache Not Snoopable Sleep Probe Serviced Legend Hardware transitions Software transitions The AMD Athlon System Bus is connected during the following states 1 The Probe state 2 During transitions between the Halt state and the C2 Stop Grant state 3 During transitions between the C2 Stop Grant state and the Halt state 4 Working state Figure 3 AMD Athlon XP Processor Model 8 Power Management States Chapter 4 Power Management 9 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 Working State H
44. 453 E6 10 73 11 28 e 1 27 BSC E7 10 75 11 28 el 2 54 BSC E8 13 28 13 85 Mass 11 0 g REF Note 1 Dimensions are given in millimeters 2 The mass consists of the completed package including processor surface mounted parts and pins Chapter 10 Mechanical Data 51 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 D H 4X AN37 CORNER AN1 CORNER AN37 CORNER m 0 0 6 0 0 0 00 0 0 0 0 0 0 0 0 6 A L 2c 4X W ERAKI 9 9 O9 9 9 9 ws 0 00 9090900 9909595950 9 9 9 9 c 90909090 6 G9 9 9 9 9 9 9 9 9 E9 12X M ceo Fo E3 3X Pres i OROKOR E8 3X ew 9 ORI 2 eooo ORI E4 v 66029 69 99 4 ORK E 9666696065 3 0008 5 907570 9289620 5 PORR 8950 95 4 OKOK 6999 6 9 9 9 9 9 9 9 9 9 6 04070 99 992980 9 990 9 99 9599 c lo G 6 e T A1 CORNER A37 CORNER A37 CORNER L L BOTTOM VIEW TOP VIEW NOT TO SCALE PASSIVE COMPONENTS COMPLIANT THERMAL PADS m A4 NOTES Y e mmmn E SIDE VIEW GENERAL NOTES 1 opp py All dimensions are specified in millimeter mm Dimensioning and tolerancing ASME Y
45. 9 VID 4 0 DC Characteristics 33 Table 10 FID 3 0 DC Characteristics 33 Table11 AC and DC Characteristics 33 Table 12 cong AC and DC Characteristics 34 Table 13 Absolute Ratings 36 Table 14 SYSCLK and SYSCLK DC Characteristics 37 Table 15 AMD Athlon System Bus DC Characteristics 38 Table 16 General AC and DC 39 Table 17 Thermal Diode Electrical Characteristics 42 Table 18 Guidelines for Platform Thermal Protection of the i v ole dau ee PEG SN UN ere a 44 Table 19 APIC Pin AC and DC 1 44 Table 20 Mechanical Loading 49 Table 21 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID 0f 680 cs ere DES E EVO PEN 50 Table 22 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID Of 68T te Eb CR EE EAS 51 Table 23 Part Number 27648 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID 0f 681 uS es 53 Table 24 Pin Name Abbreviations 58 Table 25 Cross Reference by Pin Location
46. AMD Athlon XP Processor Model 8 Data Sheet AMD Athlon xp Preliminary Information 2001 2003 Advanced Micro Devices Inc rights reserved The contents of this document are provided in connection with Advanced Micro Devices Inc AMD products AMD makes no representations or war ranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and prod uct descriptions at any time without notice No license whether express implied arising by estoppel or otherwise to any intellectual property rights is granted by this publication Except as set forth in AMD s Standard Terms and Conditions of Sale AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to its products including but not limited to the implied warranty of merchantability fitness for a particular purpose or infringement of any intellectual property right AMD s products not designed intended authorized or warranted for use as components in systems intended for surgical implant into the body or in other applications intended to support or sustain life or in any other applica tion in which the failure of AMD s product could create a situation where per sonal injury death or severe property or environmental damage may occur AMD reserves the right to discontinue or make changes to its products at any
47. B AMD Athlon System Bus SDATAINCLK 3 0 SDATAOUTCLK 3 0 CLKFWDRST PROCRDY System Bus AC Characteristics on CONNECT page 29 AMD Athlon System Bus DC Characteristics on page 36 and CLKFWDRST Pin on page 73 See APIC Pins AC and DC Characteristics on page 44 and APIC Pins PICCLK PICD 1 0 on page 73 APIC PICD 1 0 PICCLK See Frequency Identification FID 3 0 on page 33 FID 3 0 Pins on page 75 and FSB Sense 1 0 Pins on page 76 Frequency FID 3 0 FSB Sense 1 0 See General AC and DC NAG otal TOM Characteristics on page 39 Chapter 8 Electrical Data 31 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet Table8 Interface Signal Groupings continued 25175H March 2005 Signal Group Power Signals VID 4 0 VCCA Vcc coge COREFB COREFB Notes See Voltage Identification VID 4 0 on page 35 VID 4 0 Pins on page 78 VCCA AC and DC Characteristics on page 35 Vcc conr Characteristics on page 34 VCCA Pin on page 78 and COREFB and COREFB Pins on page 74 Southbridge RESET INTR NMI INIT A20M FERR IGNNE STPCLK FLUSH See General AC and DC Characteristics on page 39 INTR Pin on page 76 NMI Pin on page 77 5 Pin page 78 INIT Pin on page 76 A20M Pin on page 73 F
48. CC Vcc_coRE D VCC Vcc conE H2 VCC Vcc_coRE 74 VCC Vcc_coRE H4 VCC Vcc_coRE 76 VCC _ H12 VCC Vcc_coRE 78 VCC Vcc H16 VCC conE AB30 VCC Vcc H20 VCC Vcc conE AB32 VCC Vcc_coRE H24 VCC Vcc conE AB34 VCC Vcc_coRE K32 VCC Vcc conE AB36 Vcc K34 conE AD2 VCC Vcc K36 VCC conE AD4 VCC Vcc_coRE M2 VCC Vcc_coRE AD6 VCC Vcc 4 VCC conE AF14 VCC Vcc M6 VCC Vcc conE AF18 VCC Vcc M8 VCC conE AF22 VCC Vcc P30 VCC conE AF26 VCC Vcc P32 VCC Vcc conE AF34 VCC Vcc_coRE P34 VCC Vcc_coRE AF36 VCC Vcc_coRE P36 VCC Vcc_coRE AH2 VCC Vcc R2 VCC Vcc_coRE AH4 VCC Vcc RA VCC conE AH10 Vcc R6 VCC Vcc AH14 VCC Vcc R8 conE 18 VCC Vcc T30 VCC conE AH22 VCC Vcc T32 VCC Vcc AH26 VCC Vcc T34 VCC Vcc conE AK10 VCC Vcc_coRE T36 VCC Vcc conE AK14 VCC Vcc V2 VCC Vcc conE 18 VCC Vcc_coRE V4 VCC Vcc AK22 VCC Vcc_coRE V6 VCC Vcc AK26 VCC Vcc V8 VCC Vcc_coRE AK30 62 Pin Descriptions Chapter 11 Preliminary Information 25175H March 2003 Table 24 Pin Abbreviations continued AMD Athlon XP Processor Model 8 Data Sheet
49. CLK and name it SYSCLK Connect CLKIN with RSTCLK and name it SYSCLK Length match the clocks from the clock generator to the Northbridge and processor See SYSCLK and SYSCLK on page 79 for more information 74 Pin Descriptions Chapter 11 Preliminary Information 25175H March 2005 CONNECT Pin COREFB and COREFB Pins CPU Pin DBRDY and DBREQ Pins FERR Pin FID 3 0 Pins AMD Athlon XP Processor Model 8 Data Sheet CONNECT is an input from the system used for power management and clock forward initialization at reset COREFB and COREFB are outputs to the system that provide processor core voltage feedback to the system CPU PRESENCE Z is connected to VSS on the processor package If pulled up on the motherboard CPU PRESENCE may be used to detect the presence or absence of a processor in the Socket A style socket DBRDY and DBREQ are routed to the debug connector is tied to with a pullup resistor FERR is an output to the system that is asserted for any unmasked numerical exception independent of the NE bit in CRO FERR is a push pull active High signal that must be inverted and level shifted to an active Low signal For more information about FERR and FERR see the Required Circuits chapter of the AMD Athlon Processor Based Motherboard Design Guide order 24363 FID 3 Y3 FID 2 Y1 FID 1 W3 and FID 0 W1 a
50. DDOUT 7 Ci SD421 SDATA 21 G37 8 SADDOUTI 8 G SD 22 SDATA 22 E37 SAO 9 SADDOUT 9 G SD 23 SDATA 25 HF G35 SAO 10 SADDOUT 10 Gl SD 24 SDATA 24 Q33 SAO 11 SADDOUT 11 El SD 25 SDATA 25 N33 SAO 12 SADDOUT 12 A3 SD 26 SDATA 26 L33 SAO 13 SADDOUT 13 G5 SD 27 SDATA 27 N35 SAO 14 SADDOUT 14 G3 SD 28 SDATA 28 L37 SAOC SADDOUTCLK E3 SD 29 SDATA 29 J37 SCNCK1 SCANCLK1 51 0 30 SDATA 30 A37 SCNCK2 SCANCLK2 55 04231 SDATA 31 4f 5 SCNINV SCANINTEVAL S3 0 32 SDATA 32 E31 SCNSN SCANSHIFTEN Q5 SD 33 SDATA 33 E29 SD 0 SDATA 0 AA55 SD 34 SDATA 34 A27 SD 1 SDATA 1 W37 SD 55 SDATA 35 A25 SD 2 SDATA 2 W35 SD 36 SDATA 36 E21 60 Pin Descriptions Chapter 11 Preliminary Information 25175H March 2003 Table 24 Pin Abbreviations continued AMD Athlon XP Processor Model 8 Data Sheet Abbreviation Full Name Pin Abbreviation Full Name Pin SD 37 SDATA 37 HF C23 SDOC 2 SDATAOUTCLK 2 A33 SD 38 SDATA 38 Q7 SDOC 3 SDATAOUTCLK 3 CH SD 39 SDATA 39 A23 SDOV SDATAOUTVALID AL31 SD 40 SDATA 40 A35 SFILLV SFILLVALID AJ31 SD 41 SDATA 41 4F C35 SMI AN5 SD 42 SDATA 42 C33 STPC STPCLK ACI SD 43 SDATA 43 C31 TCK QI SD 44 SDATA 44 A29 TDI UI SD 45 SDATA 45 C29 TDO U5 SD 46 SDATA 46 E23 THDA THERMDA S7 SD 47 SDATA 47 C25 THDC THERMDC
51. Die Model Number wees Working State CO Stop Grant S1 2 3 4 Temperature Maximum Typical Maximum Typical Maximum Typical 2083 2600 1 65 V 41 4 62 0 W 85 C 2167 2700 7 See Figure 3 AMD Athlon XP Processor Model 8 Power Management States page 9 2 The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the process and are not representative of the typical Stop Grant current that is currently about one third of the maximum specified current 3 These currents occur when the AMD Athlon system bus is disconnected and has a low power ratio of 1 8 for Stop Grant disconnect and a low power ratio of 1 8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of 2003 1225 programmed into the Clock Control CLK MSR For more information refer to the AMD Athlon and AMD Duron Processors BIOS Software and Debug Developers Guide order 21656 4 The Stop Grant current consumption is characterized at 50 C and not tested 5 Thermal design power represents the maximum sustained power dissipated while executing publicly available software or instruction sequences under normal system operation at nominal Vcc Thermal solutions must monitor the temperature of the processor to prevent the processor from exceeding its maximum die temperature Chapter7 Advanced 333 Front S
52. Duron Processors BIOS Software and Debug Developers Guide order 21656 Chapter 5 CPUID Support 19 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 20 CPUID Support Chapter 5 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 6 Advanced 266 Front Side Bus AMD Athlon XP Processor Model 8 Specifications This chapter describes the electrical specifications that are unique to the advanced 266 front side bus FSB AMD Athlon XP processor model 8 6 1 Part Specific Electrical and Thermal Specifications for Advanced 266 FSB AMD Athlon XP Processors Model 8 This section provides part specific electrical and thermal information for each type of the Advanced 266 FSB AMD Athlon XP processors model 8 in Table 1 on page 22 and Table 2 on page 23 Chapter 6 Advanced 266 Front Side Bus AMD Athlon XP Processor Model 8 Specifications 21 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 Table 1 shows the part specific electrical and thermal specifications in the CO working state and the S1 Stop Grant state for processors with a CPUID 680 Table 1 Electrical and Thermal Specifications for Processors with a CPUID of 680 Icc Processor Current Thermal Power5 Frequency in MHz ermal Fower Maximum Die Model Number s
53. ERR Pin on page 74 IGNNE Pin on page 76 STPCLK Pin on page 79 and FLUSH Pin on page 77 System Clocks SYSCLK SYSCLK Tied to CLKIN CLKIN and RSTCLK RSTCLK PLLBYPASSCLK PLLBYPASSCLK See Advanced 266 FSB AMD Athlon XP Processor Model 8 SYSCLK and SYSCLK AC Characteristics on page 24 Advanced 333 FSB AMD Athlon XP Processor Model 8 SYSCLK and SYSCLK AC Characteristics on page 28 Table 14 SYSCLK and SYSCLK DC Characteristics on page 37 SYSCLK and SYSCLK on page 78 and PLL Bypass and Test Pins on page 77 Test PLLBYPASS PLLTEST PLLMON1 PLLMON2 SCANCLK1 SCANCLK2 SCANSHIFTEN SCANINTEVAL ANALOG See General AC and DC Characteristics on page 39 PLL Bypass and Test Pins on page 77 Scan Pins on page 78 Analog Pin on page 73 Thermal THERMDA THERMDC Table 17 Thermal Diode Electrical Characteristics on page 42 and THERMDA and THERMDC Pins on page 78 Miscellaneous DBREQ DBRDY PWROK See General AC and DC Characteristics on page 39 DBRDY and DBREQ Pins on page 74 PWROK Pin on page 77 32 Electrical Data Chapter 8 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 8 3 Voltage Identification VID 4 0 Table 9 shows the VID 4 0 DC Characteristics For more infor mation on VID 4 0 DC Cha
54. Equation Equation Symbol Variable Constant Description Nt lumped Lumped ideality factor k Boltzmann constant q Electron charge constant T Diode temperature Kelvin VBE Voltage from base to emitter lc Collector current ls Saturation current Appendix A Thermal Diode Calculations 83 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 Equation 1 shows the ideal diode calculation Vez lumped f 2 1 q I Sourcing two currents and using Equation 1 derives the difference in the base to emitter voltage that leads to finding the diode temperature as shown in Equation 2 The use of dual sourcing currents allows the measurement of the thermal diode temperature to be more accurate and less susceptible to die and process revisions Temperature sensors that utilize series resistance cancellation can use more than two sourcing currents and are suitable to be used with the AMD thermal diode Equation 2 1s the formula for calculating the temperature of a thermal diode T V high V low k o Tu I in 2 Temperature Offset Correction A temperature offset may be required to correct the value measured by a temperature sensor An offset is necessary if a difference exists between the lumped ideality factor of the processor and the ideality factor assumed by the temperature sensor The lumped ideality factor can be cal
55. G AF14 Vcc coRE AG37 SADDIN 7 P P AF16 VSS AH2 Vcc core g i AF18 Vcc 4 s AF20 VSS AMDPin page 74 AF22 Vcc coRE 8 NCPin page 78 AF24 VSS Vcc 3 AF26 Vcc_coRE AHD VSS AF28 NC Pin page 78 AHM Vcc Chapter 11 Pin Descriptions 71 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet Table 25 Cross Reference by Pin Location continued 25175H March 2005 Pin Name Description L P R Pin Name Description L P 16 VSS AK2 VSS E 18 Vcc VSS E AH20 VSS CPU_PRESENCE page 75 e ess AH22 Vcc cone NCPin page78 AH24 VSS 10 Vcc core THE AH26 Vcc AKI2 vss EIE AH28 VSS Vcc core AH30 FSB_Sense 1 page 77 O G AKI6 VSS le AH32 VSS Vcc core es AH34 VSS 20 VSS Ei ees AH36 VSS AK2 Vcc core aie AM IGNNE page77 P 24 vss s AJ3 INIT page 77 P I AK26 Vc AJ5 Vcc AQ8 vss NC Pin page 78
56. Input Low Voltage 300 350 mV 1 2 V V V Output High Voltage CC CORE CC CORE mV d 400 300 VoL Output Low Voltage 300 400 mV Vin VSS Tristate Leakage Pullu n 1 mA LEAK_P 8 p Ground lie Tristate Leakage Pulldown VN 7 Vcc cone 600 Nominal Output High Current 6 mA 3 loL Output Low Current 6 mA 3 Tsu Sync Input Setup Time 2 0 ns 4 5 Tup Sync Input Hold Time 0 0 ps 45 TpELAY Output Delay with respect to RSTCLK 0 0 6 1 ns 5 Notes 1 Characterized across DC supply voltage range 2 Values specified at nominal Scale parameters between minimum and core maximum 3 Io and are measured at Vo maximum and Voy minimum respectively 4 Synchronous inputs outputs are specified with respect to RSTCLK and RSTCK at the pins 5 These are aggregate numbers 6 Edge rates indicate the range over which inputs were characterized Z lnasynchronous operation the signal must persist for this time to enable capture 8 This value assumes RSTCLK period is 10 ns gt TBIT 2 fRST 9 The approximate value for standard case in normal mode operation 10 This value is dependent on RSTCLK frequency divisors Low Power mode and core frequency 11 Reassertions of the signal within this time are not guaranteed to be seen by the core 12 This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase 13 This value assumes RSTCLK and K7CLKOUT are running at the
57. Processor Model 8 Part Number 27291 OPGA 52 Figure 15 AMD Athlon XP Processor Model 8 Part Number 27648 OPGA Package 54 Figure 16 AMD Athlon XP Processor Model 8 Pin Diagram Topside View sese e Rex reb Ra 56 Figure 17 AMD Athlon XP Processor Model 8 Pin Diagram Bottomside View 57 Figure 18 OPN Example for the AMD Athlon XP Processor usu Gee REGS u Oe en AER UNS 81 List of Figures 7 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 8 List of Figures Preliminary Information 25175H March 2005 List of Tables AMD Athlon XP Processor Model 8 Data Sheet Table 1 Electrical and Thermal Specifications for Processors with a CPUID 0 4680 22 Table 2 Electrical and Thermal Specifications for Processors with CPUID of 681 23 Table 3 SYSCLK and SYSCLK AC Characteristics 24 Table 4 AMD Athlon System Bus AC Characteristics 25 Table 5 Electrical and Thermal Specifications 27 Table 6 SYSCLK SYSCLK AC Characteristics 28 Table 7 AMD Athlon System Bus AC Characteristics 29 Table 8 Interface Signal Groupings 31 Table
58. RE DC MAX Vcc_CORE NOM CORE DC MIN CORE AC MIN AC ICORE MAX dt ICORE MIN Figure 10 Vcc Voltage Waveform Chapter 8 Electrical Data 35 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet Absolute Ratings 25175H March 2003 The AMD Athlon XP processor model 8 should not be subjected to conditions exceeding the absolute ratings as such conditions can adversely affect long term reliability or result in functional damage Table 13 lists the maximum absolute ratings of operation for the AMD Athlon XP processor model 8 Table 13 Absolute Ratings Parameter Description Min Max Vcc AMD Athlon XP processor model 8 core supply 0 5V Vcc Max 0 5 V VCCA AMD Athlon XP processor model 8 PLL supply 0 5 V VCCA Max 0 5 V Vp N Voltage on any signal pin 0 5 V Vcc Max 0 5 V TsrORAGE Storage temperature of processor 409 1009 36 Electrical Data Chapter 8 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 8 9 SYSCLK and SYSCLK DC Characteristics Table 14 shows the DC characteristics of the SYSCLK and SYSCLK differential clocks The SYSCLK signal represents CLKIN and RSTCLK tied together while the SYSCLK signal represents CLKIN and RSTCLK tied together For information about SYSCLK and SYSCLK se
59. U7 SD 48 SDATA 48 E17 TMS Q3 SD 49 SDATA 49 E13 TRST U3 SD 50 SDATA 50 VCC Vcc cone B4 SD 51 SDATA S1 15 VCC Vcc B8 SD 52 52 E9 VCC Vcc cont 12 SD 53 SDATA 53 VCC Vcc CORE B16 SD 54 SDATA 54 C9 VCC Vcc B20 SD 55 SDATA 55 A9 VCC Vcc coRE B24 SD 56 SDATA 56 C21 VCC Vcc coRE B28 SD 57 SDATA 57 A21 VCC Vcc coRE B32 SD 58 SDATA 58 E19 VCC Vcc coRE B36 SD 59 SDATA 59 19 VCC CORE D2 SD 60 SDATA 60 C17 VCC Vcc coRE D4 0461 SDATA 61 VCC Vcc cont D8 SD 62 SDATA 62 AT VCC cont 012 50463 SDATA 63 15 VCC Vcc cont D16 SDIC 0 SDATAINCLK 0 W33 VCC Vcc cont D20 SDIC I SDATAINCLK 1 135 VCC con D24 SDIC 2 SDATAINCLK 2 E27 VCC Vcc cont D28 SDICH3 SDATAINCLK 3 E15 VCC Vcc CORE D32 SDINV SDATAINVALID AN33 VCC F12 SDOC 0 SDATAOUTCLK O AE35 VCC CORE F16 SDOC I SDATAOUTCLK I C37 VCC VCC CORE F20 Chapter 11 Pin Descriptions 61 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Table 24 Pin Name Abbreviations continued Abbreviation Full Name Pin Abbreviation Full Name Pin VCC Vcc_coRE F24 VCC Vcc_coRE X30 VCC Vcc F28 conE X32 Vcc F32 VCC Vcc X34 VCC Vcc F34 conE X36 VCC Vcc_coRE F36 V
60. Vrhreshold AC SYSCLK Waveform 28 Advanced 333 Front Side Bus AMD Athlon XP Processor Model 8 Specifications Chapter 7 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 7 5 Advanced 333 FSB AMD Athlon System Bus AC Characteristics The AC characteristics of the AMD Athlon system bus of this processor are shown in Table 7 The parameters are grouped based on the source or destination of the signals involved Table 7 AMD Athlon System Bus AC Characteristics Group Symbol Parameter Min Max Units Notes TRISE Output Rise Slew Rate 1 3 V ns 1 All Signals TrALL Output Fall Slew Rate 1 3 V ns 1 Forward Tsu Input Data Setup Time 300 ps 3 Clocks Tup Input Data Hold Time 300 ps 3 Cin Capacitance on input Clocks 4 25 pF Cour Capacitance on output Clocks 4 12 pF TvAL RSTCLK to Output Valid 800 2000 ps 4 5 Sync Tsu Setup to RSTCLK 500 ps 4 6 Tup Hold from RSTCLK 500 ps 4 6 Notes 1 Rise and fall time ranges are guidelines over which the has been characterized 2 Tskew pirrepge 5 the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock as measured at the package with respect to different clock edges 3 Input SU and HD times are with respect to the appropriate Clock Forward Group input clock 4 The synchronous signals include PROCRDY CONNECT
61. al video image compression video encoding for streaming over the Internet soft DVD commercial 3D modeling workstation class computer aided design CAD commercial desktop publishing and speech recognition The AMD Athlon XP processor model 8 also offers the scalability and reliability that IT managers and business users require for enterprise computing The AMD Athlon XP processor model 8 features a seventh generation microarchitecture with an integrated exclusive L2 cache which supports the growing processor and system bandwidth requirements of emerging software graphics I O and memory technologies The high speed execution core of the AMD Athlon XP processor model 8 includes multiple x86 instruction decoders a dual ported 128 Kbyte split level one L1 cache an exclusive 256 Kbyte L2 cache three independent integer pipelines three address calculation pipelines and a superscalar fully pipelined out of order three way floating point engine The floating point engine is capable of delivering outstanding performance on numerically complex applications Chapter 1 Overview 1 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 The features of the AMD Athlon XP processor model 8 are QuantiSpeed architecture a high performance full speed cache an advanced 333 front side Bus FSB with a 2 7 Gigabyte per second system bus or an advanced 266 FSB with a 2 1 Gigabyte per
62. alt State Stop Grant States The following sections provide an overview of the power management states For more details refer to the AMD Athlon System Bus Specification order 21902 Note In all power management states that the processor is powered the system must not stop the system clock SYSCLK S YSCLK to the processor The Working state is the state in which the processor is executing instructions When the processor executes the HLT instruction the processor enters the Halt state and issues a Halt special cycle to the AMD Athlon system bus The processor only enters the low power state dictated by the CLK_Ctl MSR if the system controller Northbridge disconnects the AMD Athlon system bus in response to the Halt special cycle If STPCLK is asserted the processor will exit the Halt state and enter the Stop Grant state The processor will initiate a system bus connect if it is disconnected then issue a Stop Grant special cycle When STPCLK is deasserted the processor will exit the Stop Grant state and re enter the Halt state The processor will issue a Halt special cycle when re entering the Halt state The Halt state is exited when the processor detects the assertion of INITZ RESET or an interrupt via the INTR or NMI pins or via a local APIC interrupt message When the Halt state is exited the processor will initiate an AMD Athlon system bus connect if it is disconnected The processor enters the Sto
63. before RESET is deasserted The FID 3 0 signals are valid within 100 ns after PWROK is asserted The chipset must not sample the FID 3 0 signals until they become valid Refer to the AMD Athlon Processor Based Motherboard Design Guide order 24363 for the specific implementation and additional circuitry required The FID 3 0 signals become valid within 100 ns after RESET is asserted Refer to the AMD Athlon Processor Based Motherboard Design Guide order 24363 for the specific implementation and additional circuitry required Chapter 9 Signal and Power Up Requirements 47 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Clock Multiplier Selection FID 3 0 The chipset samples the FID 3 0 signals in a chipset specific manner from the processor and uses this information to determine the correct serial initialization packet SIP The chipset then sends the SIP information to the processor for configuration of the AMD Athlon system bus for the clock multiplier that determines the processor frequency indicated by the FID 3 0 code The SIP is sent to the processor using the SIP protocol This protocol uses the PROCRDY CONNECT and CLKFWDRST signals that are synchronous to SYSCLK For more information about FID 3 0 see FID 3 0 Pins on page 75 Serial Initialization Packet SIP Protocol Refer to AMD Athlon System Bus Specification ord
64. cs Address Remapping Table HSTL High Speed Transistor Logic 90 Appendix B Conventions and Abbreviations Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Table 32 Acronyms continued Abbreviation Meaning IDE Integrated Device Electronics ISA Industry Standard Architecture IPC Instructions Per Cycle JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LAN Large Area Network LRU Least Recently Used LVTTL Low Voltage Transistor Transistor Logic MSB Most Significant Bit MTRR Memory Type and Range Registers MUX Multiplexer NMI Non Maskable Interrupt OD Open Drain OPGA Organic Pin Grid Array PA Physical Address PBGA Plastic Ball Grid Array PCI Peripheral Component Interconnect PDE Page Directory Entry PDT Page Directory Table PGA Pin Grid Array PLL Phase Locked Loop PMSM Power Management State Machine POS Power On Suspend POST Power On Self Test PP Push Pull RAM Random Access Memory ROM Read Only Memory RXA Read Acknowledge Queue SCSI Small Computer System Interface SDI System DRAM Interface SDRAM Synchronous Direct Random Access Memory SIMD Single Instruction Multiple Data SIP Serial Initialization Packet SMbus System Management Bus Appendix B Conventions and Abbreviations 91 Preliminary Information AMD Ath
65. ction with an external temperature sensor to determine the die temperature of the processor The diode anode THERMDA and cathode are available as pins on the processor as described in THERMDA and THERMDC Pins on page 78 For information about thermal design for the AMD Athlon XP processor model 8 including layout and airflow considerations see the AMD Processor Thermal Mechanical and Chassis Cooling Design Guide order 23794 and the cooling guidelines on http www amd com Table 17 shows the AMD Athlon XP processor model 8 Electrical characteristics of the on die thermal diode For information Characteristics about calculations for the ideal diode equation and temperature offset correction see Appendix A Thermal Diode Calculations on page 77 Table 17 Thermal Diode Electrical Characteristics Symbol Parameter Min Nom Max Units Notes Description l Sourcing current 5 300 pA 1 Lumped ideality n f lumped factor 1 00000 1 00374 1 00900 2 3 4 Nf actual Actual ideality factor 1 00261 3 4 Series Resistance 0 93 Q 3 4 Notes 1 The sourcing current should always be used in forward bias only 2 Characterized at 95 C with a forward bias current pair of 10 uA 100 pA AMD recommends using a minimum of two sourcing currents to accurately measure the temperature of the thermal diode 3 Not 100 tested Specified by design and limited characterization
66. culated using the equations in this section to find the temperature offset that should be used with the temperature sensor Table 30 shows the constants and variables used to calculate the temperature offset correction Table 30 Constants and Variables Used in Temperature Offset Equations Equation Symbol Variable Constant Description actual Actual ideality factor Nf jumped Lumped ideality factor nr Ts Ideality factor assumed by temperature sensor Ihigh High sourcing current llow Low sourcing current T die spec Die temperature specification Tof set Temperature offset 84 Appendix A Thermal Diode Calculations Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet The formulas in Equation 3 and Equation 4 can be used to calculate the temperature offset for temperature sensors that do not employ series resistance cancellation The result is added to the value measured by the temperature sensor Contact the vendor of the temperature sensor being used for the value of lt Refer to the document On Die Thermal Diode Characterization order 25443 for further details Equation 3 shows the equation for calculating the lumped ideality factor lumped in sensors that do not employ series resistance cancellation Rr h n lumped Tl actual igh ow 1 3 g Tone 273 15 28 low Equation
67. e SYSCLK and SYSCLK on page 79 and Table 24 Pin Name Abbreviations on page 58 Table 14 SYSCLK and SYSCLK DC Characteristics Symbol Description Min Max Units Vrhreshold Ac Crossing before transition is detected AC 450 mV liga p Leakage current through P channel pullup to coge 1 mA lg Leakage current through N channel pulldown to VSS Ground 1 mA Differential signal crossover 2 100 Capacitance 4 25 pF Note Thefollowing processor inputs have twice the listed capacitance because they connect to two input pads SYSCLK and SYSCLKsE SYSCLK connects to CLKIN RSTCLK SYSCI connects to CLKIN RSTCLK Figure 11 shows the DC characteristics of the SYSCLK and SYSCLK signals Vihreshold bc 400mV Vihreshold ac 450mV Figure 11 SYSCLK and SYSCLK Differential Clock Signals Chapter 8 Electrical Data 37 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 8 10 AMD Athlon System Bus DC Characteristics Table 15 shows the DC characteristics of the AMD Athlon system bus used by the AMD Athlon XP processor model 8 Table 15 AMD Athlon System Bus DC Characteristics Symbol Parameter Condition Min Max Units Notes 0 5 x V 0 5 x V VREF DC Input Reference Voltage cc con cc mV 1 50 50
68. ect special cycle is not issued at 6 Forward clocks start three SYSCLK periods after that time it is only issued after a subsequent CLKFWDRST is deasserted processor wake up event Figure 7 Processor Connect State Diagram Chapter 4 Power Management 17 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 4 3 Clock Control The processor implements a Clock Control CLK Ctl MSR address C001 001Bh that determines the internal clock divisor when the AMD Athlon system bus is disconnected Refer to the AMD Athlon and AMD Duron Processors BIOS Software and Debug Developers Guide order 21656 for more details on the CLK_Ctl register 18 Power Management Chapter 4 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 5 CPUID Support AMD Athlon M XP processor model 8 version and feature set recognition can be performed through the use of the CPUID instruction that provides complete information about the processor vendor type name etc and its capabilities Software can make use of this information to accurately tune the system for maximum performance and benefit to users For information on the use of the CPUID instruction see the following documents m AMD Processor Recognition Application Note order 20734 AMD Athlon Processor Recognition Application Note Addendum order 21922 m AMD Athlon and AMD
69. ed Pin Name Description L P R Pin Name Description L P R NI PICCLK 74 O I 834 VSS N3 PICD 0 page 74 O B 6 VSS N5 PICD 1 page 74 O B 51 SCANCLK1 page 79 P N7 Key Pin page 78 S5 SCANINTEVAL page 79 P N31 NC Pin page 78 55 SCANCLK2 page 79 N33 SDATA 25 B P 97 THERMDA page 79 N35 SDATA 27 P IB P 531 NC Pin page 78 N37 SDATA 18 P B G 533 SDATA 7 P B G P2 VSS 35 15 B PA VSS 37 SDATA 6 P B G P6 VSS T2 VSS P8 VSS T4 VSS P30 6 VSS P32 Vcc coRE T8 VSS P34 Vcc T30 cone P36 Vcc T32 Vcc Q1 TCK page 77 P I 34 Q3 TMS page77 P I 136 Vcc core Q5 SCANSHIFTEN page 79 TDI page 77 P 07 page 78 U3 TRST page 77 031 NC Pin page 78 U5 TDO page 77 P O 055 SDATA 24 P B U7 THERMDC page 79 035 SDATA 17 P B G U31 NC Pin page 78 Q37 SDATA 16 P B G U33 SDATA 5 P B R2 Vec core 035 SDATA 4 P B R4 Vcc_coRE U37 NCPin page 78 R6 Vcc_coRE V2 Vcc conE R8 Vcc V4 Vcc R30 155 V6 Vcc core R32 VSS Vcc coRE Chapter 11 Pin Descriptions 69 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet
70. ed Figure 2 Logic Symbol Diagram on page 7 In Chapter 7 revised Table 5 Electrical and Thermal Specifications on page 27 In Chapter 8 revised Table 9 VID 4 0 DC Characteristics on page 33 In Chapter 12 revised Figure 18 OPN Example for the AMD Athlon XP Processor Model 8 on page 81 November 2002 E Revision History 11 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Date October 2002 Rev Description Public revision D of the AMD Athlon XP Processor Model 8 Data Sheet includes the following changes In Chapter 1 revised wording in Overview In Chapter 6 revised Table 2 Electrical and Thermal Specifications for Processors with a CPUID of 681 on page 25 added Table 5 SYSCLK and SYSCLK AC Characteristics on page 24 Figure 8 SYSCLK Waveform on page 24 and Table 4 AMD Athlon System Bus AC Characteristics on page 25 Added Chapter 7 Advanced 333 Front Side Bus AMD Athlon XP Processor Model 8 Specifications on page 27 Table 5 Electrical and Thermal Specifications on page 27 Table 6 SYSCLK and SYSCLK AC Characteristics on page 28 Figure 9 SYSCLK Waveform on page 28 and Table 7 AMD Athlon System Bus AC Characteristics on page 29 In Chapter 8 revised Table 8 Interface Signal Groupings on page 31 Table 9 VID 4 0 DC Characteristics on page 33 Table 10
71. ept Working State Stop Grant S1 2 3 4 Temperat re Maximum Typical Maximum Typical Maximum Typical 1467 17004 329A 299A 494W 44 9 W 1533 1800 150V 340A 309A 587A 37A 5L0W 463 W 1600 1900 35 0A 31 8A 52 5 W 47 7 W 90 C 1667 2000 1 60 V 37 7 34 2A 768A 4 7 603 W 54 7 W 1 65 V 36 5A 33 2A 8 85A 54A 1733 2100 1 60 V 38 8A 35 2A 7 68 A 4 7 62 1 W 56 4 W 1800 2200 1 65 V 41 2 374 8 85 5 4 67 9 W 61 7 W 85 Notes 7 See Figure 3 AMD Athlon XP Processor Model 8 Power Management States page 9 2 The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the process and are not representative of the typical Stop Grant current that is currently about one third of the maximum specified current 3 These currents occur when the AMD Athlon system bus 15 disconnected and has a low power ratio of 1 8 for Stop Grant disconnect and a low power ratio of 1 8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of 6003 1225h programmed into the Clock Control CLK Ctl MSR For more information refer to the AMD Athlon and AMD Duron Processors BIOS Software and Debug Developers Guide order 21656 4 The Stop Grant current consumption is characterized at 50 C and not tested 5 Thermal design power represents the
72. er 21902 for details of the SIP protocol 9 2 Processor Warm Reset Requirements Northbridge Reset Pins RESET cannot be asserted to the processor without also being asserted to the Northbridge RESET to the Northbridge is the same as PCI RESET The minimum assertion for PCI RESET is one millisecond Southbridges enforce a minimum assertion of RESET for the processor Northbridge and PCI of 1 5 to 2 0 milliseconds 48 Signal and Power Up Requirements Chapter 9 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Mechanical Data The AMD Athlon XP processor model 8 connects to the motherboard through a Pin Grid Array PGA socket named Socket This processor utilizes the organic pin grid array OPGA package type described in this chapter For more information see the AMD Athlon M Processor Based Motherboard Design Guide order 24363 Die Loading The processor die on the OPGA package is exposed at the top of the package This feature facilitates heat transfer from the die to an approved heat sink Any heat sink design should avoid loads on corners and edges of die The OPGA package has compliant pads that serve to bring surfaces in planar contact Tool assisted zero insertion force sockets should be designed so that no load is placed on the substrate of the package Table 20 shows the mechanical loading specifications for the processor die It is critica
73. essor from the AMD Athlon system bus before issuing the Stop Grant special cycle to the PCI bus or passing the Stop Grant special cycle to the Southbridge for systems that connect to the Southbridge with HyperTransport technologv This note applies to current chipset implementation alternate chipset implementations that do not require this are possible Note In response to Halt special cycles the Northbridge passes the Halt special cycle to the PCI bus or Southbridge immediately The processor can receive an interrupt after it sends a Halt special cycle or STPCLK deassertion after it sends a Stop Grant special cycle to the Northbridge but before the disconnect actually occurs In this case the processor sends the Connect special cycle to the Northbridge rather than continuing with the disconnect sequence In response to the Connect special cycle the Northbridge cancels the disconnect request The system is required to assert the CONNECT signal before returning the C bit for the connect special cycle assuming CONNECT has been deasserted For more information see the AMD Athlon System Bus Specification order 21902 for the definition of the C bit and the Connect special cycle Chapter 4 Power Management 13 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Figure 4 shows STPCLK assertion resulting in the processor in the Stop Grant state and the AMD Athlon s
74. ew lak eee 77 INITH PILI 2 77 INTR Pin ALR AER IOS 77 TIAG PmSs ier SR MEAE E uer TS 77 K7CLKOUT and K7CLKOUT Pins 78 Key Pins u ee ESPERE UE e RS 78 PANS as Sanm cee o aaa Rie Ue et Rd pure RT S CAPs 78 NMT Piman un Rex E ie Fos RENE eU ia 78 PGA Orientation Pins 78 PLL Bypass and Test 78 PWROK iere yr EHE TA q pay 78 SADDIN 1 0 and SADDOUT 1 0 Pins 79 Scan Bs TX sys RE OU QN gus 79 Seed Bab ela SP 79 Pin berto ees e eee Pa 79 SYSCLK and SYSCLK8 79 THERMDA and THERMDC Pins 79 geste ER E INTE 79 VID 4 0 ER ECCE 79 Pin Ver 80 ZN and ZP Ru ae on ee A 80 12 Ordering Information 81 Standard AMD Athlon XP Processor Model 8 Products 81 Appendix A Thermal Diode Calculations 83 Appendix A sedeo vh aie s wud sete A edes ue og e PR OUR 83 Ideal Diode Equation 83 Temperature Offset 84 Appendix B Conventions and Abbreviations 87 Signals and RR eer Re wae TR 87 Data 1 88
75. fication VID 4 0 33 8 4 Frequency Identification FID 3 0 33 8 5 AC and DC 33 8 6 Deco plmgz e de Med BEER SIE RID 34 8 7 Vcc coRE 34 8 8 Absolute Ratings 36 8 9 SYSCLK and SYSCLK DC Characteristics 37 8 10 AMD Athlon System Bus DC Characteristics 38 8 11 General AC and DC Characteristics 39 8 12 Open Drain Test Circuit 41 8 13 Thermal Diode Characteristics 42 Thermal Diode Electrical Characteristics 42 Thermal Protection Characterization 43 8 14 APIC Pins AC and DC Characteristics 44 9 Signal and Power Up Requirements 45 9 1 Power Up Requirements 45 Signal Sequence and Timing Description 45 Clock Multiplier Selection FID 3 0 48 9 2 Processor Warm Reset 48 Northbridge Reset 48 10 Mechanical Data 49 10 1 Die Loading ed eret en RR ae aqa brad a 49 10 2 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID OF 6080 NEM uq O BR aw
76. gn Guide order 24363 or contact your local AMD office for information about the decoupling required on the motherboard for use with the AMD Athlon XP processor model 8 8 7 Vcc Characteristics Table 12 shows the AC and DC characteristics for _ See Figure 10 on page 35 for a graphical representation of the CORE waveform Table 12 Vcc AC and DC Characteristics Symbol Parameter Limit in Working State Units Vcc Maximum static voltage above Vcc CORE NOM 50 mV Vcc coRE DC MIN Maximum static voltage below Vcc NOM 50 mV Vcc Ac MAX Maximum excursion above Vcc 150 mV Vcc Ac MIN Maximum excursion below Vcc NOM 100 mV AC Maximum excursion time for AC transients 10 us AC Negative excursion time for AC transients 5 us Note All voltage measurements are taken differentially at the COREFB COREFB pins 34 Electrical Data Chapter 8 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Figure 10 shows the processor core voltage Vcc cong waveform response to perturbation The tmin Ac negative AC transient excursion time and t4 Ac positive AC transient excursion time represent the maximum allowable time below or above the DC tolerance thresholds MAX AC CORE AC MAX CO
77. he Northbridge requires the processor to service a probe after the system bus has been disconnected it must first initiate a system bus connect In addition to the legacy STPCLK signal and the Halt and Stop Grant special cycles the AMD Athlon system bus connect protocol includes the CONNECT PROCRDY and CLKFWDRST signals and a Connect special cycle AMD Athlon system bus disconnects are initiated by the Northbridge in response to the receipt of a Halt or Stop Grant Reconnect is initiated by the processor in response to an interrupt for Halt or STPCLK deassertion Reconnect is initiated by the Northbridge to probe the processor 12 Power Management Chapter 4 Preliminary Information 25175H March 2005 AMD Athlon XP Processor Model 8 Data Sheet The Northbridge contains BIOS programmable registers to enable the system bus disconnect in response to Halt and Stop Grant special cycles When the Northbridge receives the Halt or Stop Grant special cycle from the processor and if there are no outstanding probes or data movements the Northbridge deasserts CONNECT a minimum of eight SYSCLK periods after the last command sent to the processor The processor detects the deassertion of CONNECT on a rising edge of SYSCLK and deasserts PROCRDY to the Northbridge In return the Northbridge asserts CLKFWDRST in anticipation of reestablishing a connection at some later point Note The Northbridge must disconnect the proc
78. ide Bus AMD Athlon XP Processor Model 8 Specifications 27 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 7 2 Advanced 333 FSB AMD Athlon XP Processor Model 8 SYSCLK and SYSCLK AC Characteristics Table 6 shows the SYSCLK SYSCLK differential clock AC characteristics of this processor Table6 SYSCLK and SYSCLK AC Characteristics Symbol Parameter Description Minimum Maximum Units Notes Clock Frequency 50 166 MHz 1 Duty Cycle 30 70 t Period 6 ns 2 3 b High Time 1 0 ns t Low Time 1 0 ns ty Fall Time 2 ns t Rise Time ns Period Stability 300 ps Notes 1 The AMD Athlon system bus operates at twice this clock frequency 2 Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed loop jitter bandwidth to allow the PLL to track the jitter The 20dB attenuation point as measured into a 20 or 30 pF load must be less than 500 kHz 3 Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency spread spectrum clock generators In no cases can the AMD Athlon system bus period violate the minimum specification above AMD Athlon system bus clock inputs can vary from 100 of the specified frequency to 99 of the specified frequency at a maximum rate of 100 kHz Figure 9 Figure 9 shows a sample waveform of the SYSCLK signal
79. iminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 6 3 Advanced 266 FSB AMD Athlon System Bus AC Characteristics The AC characteristics for the AMD Athlon system bus of this processor are shown in Table 4 The parameters are grouped based on the source or destination of the signals involved Table 4 AMD Athlon System Bus AC Characteristics Group Symbol Parameter Min Max Units Notes TgisE Output Rise Slew Rate 1 3 V ns 1 All Signals TrALL Output Fall Slew Rate 1 3 V ns 1 Output skew with respect to TSKEW SAMEEDGE the same clock 385 ps 2 Output skew with respect to a TSKEW DIFFEDGE different clock edge dis ps Forward Clocks Tsu Input Data Setup Time 300 ps 3 Tup Input Data Hold Time 300 ps 3 Cin Capacitance on input Clocks 4 25 pF Cour Capacitance on output Clocks 4 12 pF RSTCLK to Output Valid 250 2000 ps 4 5 Sync Tsu Setup to RSTCLK 500 ps 4 6 Hold from RSTCLK 1000 ps 4 6 Notes 1 Rise and fall time ranges are guidelines over which the has been characterized 2 Tsxew sameepce S the maximum skew within a clock forwarded group between any two signals or between any signal and its forward dock as measured at the package with respect to the same clock edge TsKEW DIFFEDGE S the maximum skew within a clock forwarded group between any two signals or between any signal and its forward dock as
80. ired Circuits chapter of the AMD Athlon M Processor Based Motherboard Design Guide order 24363 VREFSYS Pin VREFSYS W5 drives the threshold voltage for the system bus input receivers The value of VREFSYS is system specific In addition to minimize noise rejection from VREFSYS include decoupling capacitors For more information see the AMD Athlon Processor Based Motherboard Design Guide order 24363 ZN and ZP Pins ZN AC5 and ZP AE5 are the push pull compensation circuit pins In Push Pull mode selected by the SIP parameter SysPushPull asserted ZN is tied to Vcc with a resistor that has a resistance matching the impedance Zo of the transmission line ZP is tied to VSS with a resistor that has a resistance matching the impedance Z of the transmission line 80 Pin Descriptions Chapter 11 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 12 Ordering Information This section provides the ordering information for the AMD Athlon XP processor model 8 Standard AMD Athlon XP Processor Model 8 Products AMD standard products are available in several operating ranges The ordering part numbers OPN are formed by a combination of the elements as shown in Figure 18 OPN D onu Front Side Bus FSB C 266 D 333 Size of L2 Cache 5 256 Kbytes Die Temperature T 90 V 85 Operating Voltage L 1 50 V U 1 60 V 1
81. l K Kilo Kbyte Kilobyte Ibf Foot pound M Mega Mbit Megabit Mbyte Megabyte MHz Megahertz m Milli ms Millisecond mW Milliwatt H Micro HA Microampere Microfarad uH Microhenry us Microsecond uV Microvolt n nano nA nanoampere nF nanofarad nH nanohenry ns nanosecond ohm Ohm Appendix B Conventions and Abbreviations 89 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 Table 31 Abbreviations continued Abbreviation Meaning p pico pA picoampere pF picofarad pH picohenry ps picosecond Second V Volt Watt Table 32 contains the definitions of acronyms used in this document Table 32 Acronyms Abbreviation Meaning Advanced Configuration and Power Interface AGP Accelerated Graphics Port APCI AGP Peripheral Component Interconnect API Application Programming Interface APIC Advanced Programmable Interrupt Controller BIOS Basic Input Output System BIST Built In Self Test BIU Bus Interface Unit CPGA Ceramic Pin Grid Array DDR Double Data Rate DIMM Dual Inline Memory Module DMA Direct Memory Access DRAM Direct Random Access Memory DSP Digital Signal Processing EIDE Enhanced Integrated Device Electronics EISA Extended Industry Standard Architecture EPROM Enhanced Programmable Read Only Memory FIFO First In First Out GART Graphi
82. l Data on page 31 and the AMD Athlon System Bus Specification order 21902 6 Interface Signals Chapter 2 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 3 Logic Symbol Diagram Figure 2 is the logic symbol diagram of the processor This diagram shows the logical grouping of the input and output signals Clock SYSCLK SYSCLK 4 SDATA 63 0 VID 4 0 P SDATAINCLK 3 0 COREFB Voltage Data d lt f Control ata SDATAINVALID PWROK SFILIVALID FID O Control FSB SENSE IO Front Side Bus Autodetect be SvsCMD SADDIN 14 2 EL Probe Sys _ p SADDINCLK AMD Athlon XP FERR Processor Model 8 IGNNE 4 R t 8 SADDOUT 14 2 lt equest L4 SADDOUTCLK IIR 14 Legacy NMI at PROCRDY EUM Power B CIKFWDRST ly FLUSH Management gt CONNECT and Initialization B gt THERMDA i Thermal MY RESET THERMDC J Diode PICCLK PICD 1 0 APIC Figure 2 Logic Symbol Diagram Chapter 5 Logic Symbol Diagram 7 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 8 Logic Symbol Diagram Chapter 5 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 4 Power Management
83. l that the mechanical loading of the heat sink does not exceed the limits shown in Table 20 Table 20 Mechanical Loading Location Dynamic MAX Static MAX Units Note Die Surface 100 30 Ibf 1 Die Edge 10 10 Ibf 2 Notes 1 Load specified for coplanar contact to die surface 2 Load defined for a surface at no more than a two degree angle of inclination to die surface Chapter 10 Mechanical Data 49 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 10 2 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 680 For AMD Athlon XP processors model 8 with a CPUID of 680 Table 21 shows the 27291 OPGA package dimensions in millimeters assigned to the letters and symbols used in the 27291 package diagram Figure 14 on page 52 Table 21 Part Number 27291 OPGA Package Dimensions for AMD Athlon XP Processors Model 8 with a CPUID of 680 Letter or Minimum Maximum Letter or Minimum Maximum Symbol Dimension Dimension Symbol Dimension Dimension D E 49 27 49 78 E9 1 66 1 96 DI E1 45 72 BSC G H 4 50 D2 7 51 REF A 1 942 REF 03 3 30 3 60 Al 1 00 1 20 04 10 78 11 33 A2 0 80 0 88 D5 10 78 11 33 A3 0 116 D6 8 15 8 68 A4 Z 1 90 D7 12 33 12 88 oP 6 60 D8 3 05 3 35 ob 0 43 0 50 D9 12 71 13 26 Qb1 1 40 REF E2 11
84. lVREF_LEAK VREF Tristate Leakage Pullup Vin VREF Nominal 100 uA IVREF_LEAK_N VREF Tristate Leakage Pulldown Vin VREF Nominal 100 Input High Voltage VRF 200 core 500 mV Vu Input Low Voltage 500 Veer 200 mV Vin VSS l Tristate Leakage Pullu N 1 mA LEAK_P S akage p Ground N Tristate Leakage Pulldown Vin 1 mA E Nominal Cin Input Pin Capacitance 4 7 pF Ron Output Resistance 0 90 x Ret p 1 1 X Rep O 2 Impedance Set Point P Channel 40 70 2 Impedance Set Point Channel 40 70 O 2 Notes 1 5 nominally set to 5096 of Vcc_conr with actual values that are specific to motherboard design implementation Veer must be created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the 50 mV specification listed above 2 Measured at 2 38 Electrical Data Chapter 8 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet General AC and DC Characteristics Table 16 shows the AMD Athlon XP processor model 8 AC and DC characteristics of the Southbridge JTAG test and miscel laneous pins Table 16 General AC and DC Characteristics Symbol Parameter Description Condition Min Max Units Notes 2 cone V Input High Voltage u V 1 2 Mb dic 200 mV 300 mV Vit
85. lon XP Processor Model 8 Data Sheet Table 32 Acronyms continued Abbreviation Meaning SPD Serial Presence Detect SRAM Synchronous Random Access Memory SROM Serial Read Only Memory TLB Translation Lookaside Buffer TOM Top of Memory TIL Transistor Transistor Logic VAS Virtual Address Space VPA Virtual Page Address VGA Video Graphics Adapter USB Universal Serial Bus ZDB Zero Delay Buffer 25175H March 2005 92 Appendix B Conventions and Abbreviations Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Related Publications These documents provide helpful information about the AMD Athlon XP processor model 8 and can be found with other related documents at the AMD Web site http www amd com m AMD Athlon Processor x86 Code Optimization Guide order 22007 m AMD Processor Recognition Application Note order 20734 Methodologies for Measuring Temperature on AMD Athlon and AMD Duron M Processors order 24228 m AMD Thermal Mechanical and Chassis Cooling Design Guide order 23794 m Builders Guide for Desktop Tower Systems order 26003 Other Web sites of interest include the following m JEDEC home page www jedec org m IEEE home page www computer org m AGP Forum www agpforum or Appendix B Conventions and Abbreviations 93 Preliminary Information AMD Athlon XP Process
86. measured at the package with respec to different clock edges 3 Input SU and HD times are with respect to the appropriate Clock Forward Group input clock 4 The synchronous signals include PROCRDY CONNECT and CLKFWDRST 5 Tea 15 RSTCLK rising edge to output valid for PROCRDY Test Load is 25 pF 6 Tsy ts setup of CONNECT CLKFWDRST to rising edge of RSTCLK Typ is hold of CONNECT CLKFWDRST from rising edge of RSTCLK Chapter6 Advanced 266 Front Side Bus AMD Athlon XP Processor Model 8 Specifications 25 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 26 Advanced 266 Front Side Bus AMD Athlon XP Processor Model 8 Specifications Chapter 6 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 7 Advanced 333 Front Side Bus AMD Athlon XP Processor Model 8 Specifications This chapter describes the electrical specifications that are unique to the advanced 333 front side bus FSB AMD Athlon XP processor model 8 71 Electrical and Thermal Specifications for the Advanced 333 FSB AMD Athlon XP Processor Model 8 Table 5 shows the electrical and thermal specifications for this processor in the working state and the S1 Stop Grant state Table 5 Electrical and Thermal Specifications Icc Processor Current Thermal Power Frequency in MHz 3 ermal Fower Maximum
87. n pertains to Table 25 on page 66 A20M is an input from the system used to simulate address wrap around in the 20 bit 8086 AMD Socket A processors do not implement a pin at location AH6 All Socket A designs must have a top plate or cover that blocks this pin location When the cover plate blocks this location a non AMD part e g PGA370 does not fit into the socket However socket manufacturers are allowed to have a contact loaded in the AH6 position Therefore motherboard socket design should account for the possibility that a contact could be loaded in this position See the AMD Athlon M System Bus Specification order 21902 for information about the system bus pins PROCRDY PWROK RESET SADDIN 14 2 SADDINCLK SADDOUT 14 2 SADDOUTCLK SDATA 63 0 SDATAINCLK 3 0 SDATAINVALID SDATAOUTCLK 3 0 SDATAOUTVALID SFILLVALID Treat this pin as a NC The Advanced Programmable Interrupt Controller APIC is a feature that provides a flexible and expandable means of delivering interrupts in a system using an AMD processor The pins PICD 1 0 are the bi directional message passing signals used for the APIC and are driven to the Southbridge ora dedicated I O APIC The pin PICCLK must be driven with a valid clock input For more information see Table 19 APIC Pin AC and DC Characteristics on page 44 CLKFWDRST resets clock forward circuitry for both the system and processor Connect CLKIN with RST
88. nes in the system are within specification The motherboard is required to delay PWROK assertion for a minimum of three milliseconds from the 3 3 V supply being within specification This delay ensures that the system clock SYSCLK SYSCLK is operating within specification when PWROK is asserted The processor core voltage must be within specification as dictated by the VID 4 0 pins driven by the processor before PWROK is asserted Before PWROK assertion the AMD Athlon processor is clocked by a ring oscillator The processor PLL is powered by VCCA The processor PLL does not lock if VCCA is not high enough for the processor logic to switch for some period before PWROK is asserted VCCA must be within specification at least five microseconds before PWROK is asserted In practice VCCA Vcc core and all other voltage planes must be within specification for several milliseconds before PWROK is asserted After PWROK is asserted the processor PLL locks to its operational frequency 3 The system clock SYSCLK SYSCLK must be running before PWROK is asserted When PWROK is asserted the processor switches from driving the internal processor clock grid from the ring oscillator to driving from the PLL The reference system 46 Signal and Power Up Requirements Chapter 9 Preliminary Information 25175H March 2005 AMD Athlon XP Processor Model 8 Data Sheet clock must be valid at this time The
89. nt unit that executes all x87 floating point MMX SSE and 3DNow instructions m Hardware data pre fetch that increases and optimizes performance on high end software applications utilizing high bandwidth system capabilities m Advanced two level translation look aside buffer structures for both enhanced data and instruction address translation AMD Athlon XP processor model 8 with QuantiSpeed architecture incorporates three TLB optimizations the L1 DTLB increases from 32 to 40 entries the L2 ITLB and L2 DTLB both use exclusive architecture and the TLB entries can be speculatively loaded 2 Overview Chapter 1 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet The AMD Athlon XP processor model 8 delivers excellent system performance in a cost effective industry standard form factor The AMD Athlon XP processor model 8 is compatible with motherboards based on Socket A Figure 1 shows a typical AMD Athlon XP processor model 8 system block diagram Thermal Monitor AMD Athlon XP Processor Model 8 AMD Athlon System Bus AGP Bus Memory Bus System Controller Northbridge SDRAM or DDR LAN SCSI Modem Audio PCI Bus Peripheral Bus Controller Southbridge LPC Bus Dual EIDE BIOS Figure 1 Typical AMD Athlon XP Processor Model 8 System Block Diagram
90. or Model 8 Data Sheet 25175H March 2005 94 Appendix B Conventions and Abbreviations
91. or bus bits marked reserved must be driven inactive or left unconnected as indicated in the signal descriptions These bits and signals are reserved by AMD for future implementations When software reads registers with reserved bits the reserved bits must be masked When software writes such registers it must first read the register and change only the non reserved bits before writing back to the register Three State In timing diagrams signal ranges that are high impedance are shown as a straight horizontal line half way between the high and low levels Appendix B Conventions and Abbreviations 87 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 Data Terminology Invalid and Don t Care In timing diagrams signal ranges that are invalid or don t care are filled with a screen pattern The following list defines data terminology Quantities word is two bytes 16 bits Adoubleword is four bytes 32 bits lt A quadword is eight bytes 64 bits Addressing Memory is addressed as a series of bytes on eight byte 64 bit boundaries in which each byte can be separately enabled Abbreviations The following notation is used for bits and bytes Kilo K as in 4 Kbyte page Mega M as in 4 Mbits sec Giga G as in 4 Gbytes of memory space See Table 31 on page 89 for more abbreviations Little Endian Convention The byte with the address
92. own event Thermal protection circuitry reference designs and thermal solution guidelines are found in the following documents m AMD Athlon Processor Based Motherboard Design Guide orders 24363 m AMD Thermal Mechanical and Chassis Cooling Design Guide order 23794 See http www amd com for more information about thermal solutions Table 18 on page 44 shows the Tgyytpown and Tsp DELAY specifications for circuitry in motherboard design necessary for thermal protection of the processor Chapter 8 Electrical Data 43 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 Table 18 Guidelines for Platform Thermal Protection of the Processor Symbol Parameter Description Max Units Notes TsHutpown Thermal diode shutdown temperature for processor protection 125 11 2 5 pray Maximum allowed time from Tsuurpows detection to processor shutdown 500 ms 1 3 Notes 7 The thermal diode is not 100 tested it is specified by design and limited characterization 2 The thermal diode is capable of responding to thermal events of 40 C s or faster 3 The AMD Athlon XP processor model 8 provides a thermal diode for measuring die temperature of the processor The processor relies on thermal circuitry on the motherboard to turn off the A core voltage to the processor in response to a thermal shutdown event Refer to AMD Athlon Processor Based Mothe
93. p Grant state upon recognition of assertion of STPCLK input After entering the Stop Grant state the processor issues a Stop Grant special bus cycle on the AMD Athlon system bus The processor is not in a low power state at this time because the AMD Athlon system bus is still connected After the Northbridge disconnects the AMD Athlon system bus in response to the Stop Grant special bus cycle the processor enters a low power state dictated by the CLK Ctl MSR If the Northbridge needs to probe the processor during the Stop Grant state while the system bus is disconnected it must first connect the system bus Connecting the system bus I0 Power Management Chapter 4 Preliminary Information 25175H March 2005 AMD Athlon XP Processor Model 8 Data Sheet places the processor into the higher power probe state After the Northbridge has completed all probes of the processor the Northbridge must disconnect the AMD Athlon system bus again so that the processor can return to the low power state During the Stop Grant states the processor latches INIT INTR NMI SMI or a local APIC interrupt message if they are asserted The Stop Grant state is exited upon the deassertion of STPCLKZ or the assertion of RESET When STPCLK is deasserted the processor initiates a connect of the AMD Athlon system bus if it 1s disconnected After the processor enters the Working state any pending interrupts are recognized and serviced
94. r m je fa u o 6 8 z 9 s r z L NV is nas Lus N 0001 my NDD N N WS WN NV WV SSA IDA SSA DA SSA IDA SSA IDA SSA DA SSA IDA SSA IDA N SSA SSA IDA WV T ous HENS 85 06 8 N N DNO 0n D ADD A N IN IN DA 9 uw W v DA vA SSA DA SSA DA SSA IDA SSA DA SSA IDA SSA IDA N no SSA SSA N V cas 0 DIS nus ons N HA yn m N N N SONY N IN vA AUN fV HV SSA SSA SSA 189 SSA DA SSA IDA SSA IDA SSA DA SSA DA N awy DA IDA HV uns LLYS UNS 0851 N IN N N NJ dno 8340 M N 13534 OV JV vA yA N N N DA SSA IDA SSA DA SSA IDA SSA IN N N SSA SSA JV sas 042005 sns N IN d IWW qv SSA SSA SSA IN N DA DA IDA qv JV uns 05 0105 N IN NZ 1514 pas 2 av vA vA vA DA SSA SSA SSA SSA av VV 0405 8005 N NJ N done VV 1 SSA SSA SSA SSA DA DA DA IDA Z usns 405 N N clay X vA IDA DA DA SSA SSA SSA SSA X M us uns 042105 ON d ON S nn ou A SSA SSA SSA SSA 1 01 DA vA DA vA A vis 73 N 8 IPPpowW JOHL ou p 1 vA vA vA DA J0SS9320 1d dX GWV SSA SSA SSA SSA 1 S was 51405 0 N VOHL 20005 ANIDS mS SSA SSA SSA SSA DA IDA DA IDA 0 suc LAS vasis N NJ NSIOS SNL DL 0 d yA vA vA DA SSA SSA SSA SSA d N sts 165 0 N MJ Lor 0 N W SSA SSA SSA SSA DA DA DA IDA W 1 guns ON 95 ON elan ola 1 yA vA vA N N SSA SSA SSA f suns 2 6 N
95. r protection circuitry designs oard Design Guide order 24363 for thermal 8 14 APIC Pins AC and DC Characteristics Table 19 shows the AMD Athlon XP processor model 8 AC and DC characteristics of the APIC pins Table 19 APIC Pin AC and DC Characteristics Symbol Parameter Description Condition Min Max Units Notes Input High Voltage 17 2 625 V 1 2 Vit Input Low Voltage 300 700 mV 1 Output High Voltage 2 625 V 2 VoL Output Low Voltage 300 400 mV lLEAK P Tristate Leakage Pullup Vin VSS Ground 1 mA lLEAK Tristate Leakage Pulldown Vin 72 5 V 1 mA lot Output Low Current 9 mA TRISE Signal Rise Time 1 0 3 0 V ns 3 Signal Fall Time 1 0 3 0 V ns 3 Tsu Setup Time 1 ns Tup Hold Time 1 ns Pin Capacitance 4 12 Notes 1 Characterized across DC supply voltage range 2 The 2 625 V value is equal to 2 5 V plus a maximum of five percent 3 Edge rates indicate the range for characterizing the inputs 44 Electrical Data Chapter 8 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 9 Signal and Power Up Requirements The AMD Athlon XP processor model 8 is designed to provide functional operation if the voltage and temperature parameters are within the limits of normal operating ranges 9 1 Power Up Requirements Signal Sequence and Figure 13
96. racteristics see VID 4 0 Pins on page 78 Table9 VID 4 0 DC Characteristics Parameter Description Min Max lot Output Current Low 6 mA Vou Output High Voltage 5 25 Note The VID pins are either open circuit or pulled to ground It is recommended that these pins are not pulled above 5 25 V which is 5 0 V 5 8 4 Frequency Identification FID 3 0 Table 10 shows the FID 3 0 DC characteristics For more information see FID 3 0 Pins on page 75 Table 10 FID 3 0 DC Characteristics Parameter Description Min Max lor Output Current Low 6 mA Output High Voltage 2 625 V Note FID pins must not be pulled above this voltage by an external pullup resistor 8 5 VCCA AC and DC Characteristics Table 11 shows the AC and DC characteristics for VCCA For more information see Pin on page 78 Table 11 VCCA AC and DC Characteristics Symbol Parameter Min Nominal Max Units Notes VvccA VCCA Pin Voltage 2 25 2 5 2 75 V 1 lvccA VCCA Pin Current 0 50 mA GHz 2 Notes 1 Minimum and Maximum voltages are absolute No transients below minimum nor above maximum voltages are permitted 2 Measured at 2 5 Chapter 8 Electrical Data 33 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 8 6 Decoupling 25175H March 2005 See the AMD Athlon M Processor Based Motherboard Desi
97. re the 4 bit processor clock to SYSCLK ratio Table 26 on page 76 shows the encodings of the clock multipliers on FID 3 0 Chapter 11 Pin Descriptions 75 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 Table 26 FID 3 0 Clock Multiplier Encodings FID 3 0 Processor Clock to SYSCLK Frequency Ratio 0000 11 0001 11 5 0010 12 0011 gt 12 51 0100 5 0101 5 5 0110 6 0111 6 5 1000 7 1001 75 1010 8 1011 8 5 1100 9 1101 9 5 1110 10 1111 10 5 Notes 1 All ratios greater than or equal to 12 5x have the same FID 3 0 code of 0011b which causes the SIP configuration for all ratios of 12 5x or greater to be the same 2 BIOS initializes the CLK Ctl MSR during the POST routine This CLK setting is used with all FID combinations and selects a Halt disconnect divisor and a Stop Grant disconnect divisor For more information refer to the AMD Athlon and AMD Duron Processors BIOS Software and Debug Developers Guide order 21656 The FID 3 0 signals are open drain processor outputs that are pulled High on the motherboard and sampled by the chipset to determine the SIP Serialization Initialization Packet that is sent to the processor The FID 3 0 signals are valid after PWROK is asserted The FID 3 0 signals must not be sampled until they become valid See the AMD Athlon System Bus Specification order 2190
98. rocessor die providing more accurate temperature control to the system See Table 17 Thermal Diode Electrical Characteristics on page 42 for more information VCCA is the processor PLL supply For information about the VCCA pin see Table 5 VCCA AC and DC Characteristics on page 35 and the AMD Athlon Processor Based Motherboard Design Guide order 24363 The VID 4 0 Voltage Identification outputs are used to dictate the Vcc voltage level The VID 4 0 pins strapped to ground or left unconnected on the processor package The VID 4 0 pins are pulled up on the motherboard and used by the DC DC converter The VID codes and corresponding voltage levels are shown in Table 28 Chapter 11 Pin Descriptions 79 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 Table 28 VID 4 0 Code to Voltage Definition VID 4 0 V VID 4 0 V 00000 1 850 10000 1 450 00001 1 825 10001 1 425 00010 1 800 10010 1 400 00011 1 775 10011 1 375 00100 1 750 10100 1 350 00101 1 725 10101 1 325 00111 1 675 10111 1 275 01000 1 650 11000 1 250 01001 1 625 11001 1 225 01010 1 600 11010 1 200 01011 1 575 11011 1 175 01100 1 550 11100 1 150 01101 1 525 11101 1 125 01110 1 500 11110 1 100 01111 1 475 11111 No CPU For more information see the Requ
99. second system bus and 3DNow Professional technology The AMD Athlon system bus combines the latest technological advances such as point to point topology source synchronous packet based transfers and low voltage signaling to provide an extremely powerful scalable bus for an x86 processor The AMD Athlon XP processor model 8 is binary compatible with existing x86 software and backwards compatible with applications optimized for MMX SSE and 3DNow technology Using data format and single instruction multiple data SIMD operations based on the MMX instruction model the AMD Athlon XP processor model 8 can produce as many as four 32 bit single precision floating point results per clock cycle The 3DNow Professional technology implemented in the AMD Athlon XP processor model 8 includes new integer multimedia instructions and software directed data movement instructions for optimizing such applications as digital content creation and streaming video for the internet as well as new instructions for digital signal processing DSP and communications applications 1 1 QuantiSpeed Architecture Summary The following features summarize the AMD Athlon XP processor model 8 QuantiSpeed architecture m Advanced 333 FSB technology available m An advanced nine issue superpipelined superscalar x86 processor microarchitecture designed for increased instructions per cycle IPC and high clock frequencies m Fully pipelined floating poi
100. tate The Stop Grant state is also entered for the S1 Powered On Suspend system sleep state based on a write to the SLP_TYP and SLP EN fields in the ACPI defined Power Management 1 control register in the Southbridge During the S1 Sleep state system software ensures no bus master or probe activity occurs The Southbridge deasserts STPCLK and brings the processor out of the S1 Stop Grant state when any enabled resume event occurs The Probe state is entered when the Northbridge connects the AMD Athlon system bus to probe the processor for example to snoop the processor caches when the processor is in the Halt or Stop Grant state When in the Probe state the processor responds to a probe cycle in the same manner as when it is in the Working state When the probe has been serviced the processor returns to the same state as when it entered the Probe state Halt or Stop Grant state When probe activity is completed the processor only returns to a low power state after the Northbridge disconnects the AMD Athlon system bus again 4 2 Connect and Disconnect Protocol Connect Protocol Significant power savings of the processor only occur if the processor is disconnected from the system bus by the Northbridge while in the Halt or Stop Grant state The Northbridge can optionally initiate a bus disconnect upon the receipt of a Halt or Stop Grant special cycle The option of disconnecting is controlled by an enable bit in the Northbridge If t
101. th Table FSB Sense 1 FSB Sense 0 Bus Frequency 1 0 RESERVED 1 1 135 MHz 0 1 166 MHz 0 0 RESERVED The FSB Sense 1 0 pins are 3 3 V tolerant FLUSH must be tied to Vcc with a pullup resistor If a debug connector is implemented FLUSH is routed to the debug connector IGNNEZ is an input from the system that tells the processor to ignore numeric errors INIT is an input from the system that resets the integer registers without affecting the floating point registers or the internal caches Execution starts at 0 FFFF FFFOh INTR is an input from the system that causes the processor to start an interrupt acknowledge transaction that fetches the 8 bit interrupt vector and starts execution at that location TCK TMS TDI TRST and TDO are the JTAG interface Connect these pins directly to the motherboard debug connector Pull TDI TMS and TRST up to corg with pullup resistors Chapter 11 Pin Descriptions 77 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 K7CLKOUT and K7CLKOUT Pins Key Pins NC Pins PGA Orientation Pins PLL Bypass and Test Pins PWROK Pin K7CLKOUT and K7CLKOUT are each run for two to three inches and then terminated with a resistor pair 100 ohms to cong and 100 ohms to VSS The effective termination resistance and voltage 50 ohms and corp 2 These
102. tion For more information Chapter 9 Signal and Power Up Requirements on page 45 78 Pin Descriptions Chapter 11 Preliminary Information 25175H March 2005 SADDIN 1 0 and SADDOUT I1 0 Pins Scan Pins SMI Pin STPCLK Pin SYSCLK and SYSCLK THERMDA and THERMDC Pins VCCA Pin VID 4 0 Pins AMD Athlon XP Processor Model 8 Data Sheet The AMD Athlon XP processor model 8 does not support SADDIN 1 0 or SADDOUT 1 0 SADDIN 1 is tied to VCC with pullup resistors if this bit is not supported by the Northbridge future models can support SADDIN 1 SADDOUTT 1 0 are tied to VCC with pullup resistors if these pins are supported by the Northbridge For more information see the AMD Athlon System Bus Specification order 21902 SCANSHIFTEN SCANCLK1 SCANINTEVAL and SCANCLK2 are the scan interface This interface is AMD internal and is tied disabled with pulldown resistors to ground on the motherboard SMI is an input that causes the processor to enter the system Management mode STPCLK is an input that causes the processor to enter a lower power mode and issue a Stop Grant special cycle SYSCLK and SYSCLK are differential input clock signals provided to the PLL of the processor from a system clock generator See CLKIN RSTCLK SYSCLK Pins on page 74 for more information Thermal Diode anode and cathode pins are used to monitor the actual temperature of the p
103. tion L P R Pin Name Description L P R Al No Pin page 78 B24 Vcc coRE SADDOUI 12 P O G B6 vss A5 SADDOUI 5 P O G 828 Vcc A7 SADDOUT 3 P o 830 VSS A9 SDATA 55 P B P B2 Vcc con AM SDATA 61 P B P B34 VSS AB SDATA 53 P B G B6 15 SDATA 63 IO SADDOUT 7 AU 62 P B G IG SADDOUT S A19 NC Pin page 78 C5 SADDOUT 8 A21 SDATA 57 PIBIGI IC SADDOUTD E 25 SDATA 39 P B G GO SDATA 54 P B P A25 SDATA 55 P B P CH SDATAOUTCLK 3AE 27 SDATA 34 P B P Ci3 NC Pin page 78 A29 SDATA 44 PIB 15 SDATA 51 P B P A31 NC Pin page 78 SDATA 60 G A33 SDATAOUTCLK 2 P O P SDATA 59 P B G A35 SDATA 40 P G C SDATA 56 P B G A37 SDATA 30 P B C23 SDATA 37 P B2 VSS C25 SDATA 47 P B G B4 Vcc coRE C27 SDATAB8 F B6 VSS C29 SDATA 45 P B G B8 Vcc C31 SDATA 43 P B G BIO VSS C33 SDATA 42 P B G B12 Vec C35 SDATA 41 4 VSS C37 SDATAOUTCLK 1 B16 Vcc_core D2 Vcc conE 818 VSS 04 Vcc B20 Vcc D6 VSS B22 VSS Vcc 66 Pin Descriptions Chapter 11 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet Table 25 Cross Reference by Pin Location continued
104. uency divisors Low Power mode and core frequency 11 Reassertions of the signal within this time are not guaranteed to be seen by the core 12 This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase 13 This value assumes RSTCLK and K7CLKOUT are running at the same frequency though the processor is capable of other configurations 14 Time to valid is for any open drain pins See requirements 7 and 8 in the Power Up Timing Requirements chapter for more information 40 Electrical Data Chapter 8 Preliminary Information 25175H March 2003 AMD Athlon XP Processor Model 8 Data Sheet 8 12 Open Drain Test Circuit Figure 12 is a test circuit that may be used on automated test equipment ATE to test for validity on open drain pins Refer to Table 16 General AC and DC Characteristics on page 39 for timing requirements TEAM Vrermination 50 5 Open Drain Pin lo Output Current Notes Vrermination 1 2 V for VID and FID pins Vrermination 1 0 V for APIC pins 2 Io 6 mA for VID and FID pins lo 9 mA for APIC pins Figure 12 General ATE Open Drain Test Circuit Chapter 8 Electrical Data 41 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2005 8 13 Thermal Diode Characteristics Thermal Diode The AMD Athlon XP processor model 8 provides a diode that can be used in conjun
105. voltage levels The signals are push pull and impedance compensated The signal inputs use differential receivers that require a reference voltage The reference signal is used by the receivers to determine if a signal is asserted or deasserted by the source Termination resistors are not needed because the driver is impedance matched to the motherboard and a high impedance reflection is used at the receiver to bring the signal past the input threshold For more information about pins and signals see Chapter 11 Pin Descriptions on page 55 Chapter 2 Interface Signals 5 Preliminary Information AMD Athlon XP Processor Model 8 Data Sheet 25175H March 2003 2 5 Push Pull PP Drivers The AMD Athlon XP processor model 8 supports push pull PP drivers The system logic configures the processor with the configuration parameter called SysPushPull 1 PP The impedance of the PP drivers is set to match the impedance of the motherboard by two external resistors connected to the ZN and ZP pins See ZN and ZP Pins on page 80 for more information 2 4 AMD Athlon System Bus Signals The AMD Athlon system bus isa clock forwarded point to point interface with the following three point to point channels m A13 bit unidirectional output address command channel m A 13 bit unidirectional input address command channel m A 72 bit bidirectional data channel For more information see Chapter 8 Electrica
106. ystem bus disconnected STPCLK AMD Athlon System Bus CONNECT PROCRDY CLKFWDRST PCI Bus Figure 4 AMD Athlon System Bus Disconnect Sequence in the Stop Grant State An example of the AMD Athlon system bus disconnect sequence is as follows 1 The peripheral controller Southbridge asserts STPCLK to place the processor in the Stop Grant state 2 When the processor recognizes STPCLK asserted it enters the Stop Grant state and then issues a Stop Grant special cycle 3 When the special cycle is received by the Northbridge it deasserts CONNECT assuming no probes are pending initiating a bus disconnect to the processor 4 The processor responds to the Northbridge by deasserting PROCRDY 5 The Northbridge asserts CLKFWDRST to complete the bus disconnect sequence 6 After the processor is disconnected from the bus the processor enters a low power state The Northbridge passes the Stop Grant special cycle along to the Southbridge 14 Power Management Chapter 4 Preliminary Information 25175H March 2005 AMD Athlon XP Processor Model 8 Data Sheet Figure 5 shows the signal sequence of events that takes the processor out of the Stop Grant state connects the processor to the AMD Athlon system bus and puts the processor into the Working state _ _ PROCRDY CONNECT CLKFWDRST Figure 5 Exiting the Stop Grant State

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