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Acer TM7300 User's Manual

1. Service Guide p OD o HHA 2 NE Schematics D 19
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5. B Table 1 4 Hot Key Descriptions Fn Esc to memory Enters 40 Enters the BIOS setup utility Plug and Play Performs system configuration for Plug and Play operating Configuration systems like Windows 95 Fn F4 Screen Blackout Blanks the screen to save power to wake up the screen press any key Fn F5 Display Toggle Switches display from the built in display to external monitor to both built in and external if one is connected Fn F6 Fuel Gauge On Off Toggles battery gauge display on and off The gauge shows the percentage of charge left in the battery Shows a plug icon if a powered AC adapter is connected to the computer shows a speaker icon if speaker output is on Fn F7 shows T icon if turbo mode is Fn 2 Speaker On Off speaker output and off Fn F8 Lock System El the computer and requires a password to unlock it Resources Password Lock Accesses eject menu described page 7 Fn Ctrl T Volume Up Increases speaker volume Fn Ctrl J Decreases speaker volume Fn Ctrl Balance Right Shifts speaker balance to the right Fn Ctrl lt am Balance Left Shifts speaker balance to the left 1 6 Service Guide Table 1 4 Hot Key Descriptions HotKey Function Du sp _ A manco s RR et fe
6. 5 0 Em 5 5 a gt 2 4 18 11 3014 02 8 m 235248 NIS KENO EK o SN X s sra 001 PES 111078 ssa A 1 INI E N34 vOBENZS 15 sgean taye ait UR j i 887 5n 5 2 oe 4 x 10 DNE 3 2 a zu 08 lt UH QN 882 A 2 serg 11554 E ase 5 CEIRXEHO eS 2 11 besua 551 um 2 350 0 2 61 181 33 8 zj FT in 12 c 33u 4 334548 sp gt ap s i gt 8 0 26 gt 55 551 m L 8 D 28 Service Guide 1 805 gota 5812 8412 34
7. rp eee pe LN oM anda mm ww c E LL EJECT MENU The Fn F9 hot key combination brings up a special eject menu that allows you to perform several system configuration functions Eject Options Battery Suspend to disk Change CD ROM Disk Also Fn 1 Eject ini Dock Suspend Power Off Move Highlight Bar 4 Table 1 5 Eject Menu Descriptions eS ea Battery Store all current data and system information to the hard disk Suspend to Disk CD ROM Disk Open the CD ROM drive eject a CD Also Fn 1 Mini Dock Undock the computer Press the dock lock and pull the dock handle toward you to Suspend undock the computer See the mini dock manual for details Once the computer is successfully undocked press any key to resume Power Off Turn the computer off If you are using Windows 95 use the Shutdown command to turn off your computer System Introduction 1 7 1 3 1 6 System Specification Overview System Specifications Standard Optional Memory System Main 64MB Dual 64 bit memory banks External cache 512KB L2 cache synchronous SRAM Expandable to 128MB using 8 16 32 64MB soDIMMs Storage system One 2 5 inch high capacity Enhanced IDE hard disk One high speed IDE CD ROM drive module One 3 5 inch 1 44MB floppy drive
8. D e Appeadix 6 15 151 This appendix lists the spare parts of the notebook computer Table C 1 Spare Parts List aan 2 hz INVERTER 97016 ha 2 fo ASSY CHASSIS 13 3 LCD 970T 6M 44B07 001 60 42A23 001 50 42A01 002 56 17 42A 70230370013 023 W CAB65MM 23 40015 031 TOUCHPAD SYNAPTICS TM1202SC 56 1742A 001 112 SDRAM MDL 253309 A10 16MB 72 25330 00N 16 DIMM KMM466S424AT FO 100 5 72 46424 04 32MB SO DIMM M5M4V64S40ATP 10L 64M 72 54644 0 64MB COVER BATTERY PC 10 GF 050 970 42 46801 002 150 ASSY BATTERY 3700 60 46818 011 60 46818 021 Spare Parts List C 1 1 Spare Parts List SERES m j1 ASSY CD ROM MODULE 14 7300 6 44801 001 65 42 01 001 samo fe 00970 2 svrooLcasomsm ASSY HDD MODULE IBM 4GB 6M 44B03 001 56 02834 071 60 42A01 001 60 42 02 002 44 43 50 42003 002 50 42003 002 42003 002 COVER MIDDLE PC 10 GF 050 970 42 46822 001 500 onomea 1 fooonommactarosor ferem _ mamwon
9. 2 1 2 2 221 2 4 2 2 2 Architecture Block 2 6 2 2 3 Block Diagram ranen a a ee a 2 7 2 2 4 Pin Descriptlons A T 2 8 2 2 28 2 3 1 atu REM 2 28 2 3 2 2 30 2 3 3 Pin Descriptions 2 31 NMA 2 38 2 4 1 Features ndi e 2 38 24 2 Block 2 39 2 5 2 6 2 7 2 8 2 9 3 1 3 2 2 4 3 1 n 2 40 2 44 6 m 2 41 Philips 87C552 System Management Controller 2 43 2 5 1 2 43 2 5 2 Block 2 44 2 5 3 Pin 2 45 2 5 4 9 2 46 NS87338VJG Super Controller 2 2 48 2 6 1 22 2 2 2 222 2 2 2 2 22222 1 222 222 122 2 1 122 222 12 0201 022112 10221222 0222221122 2 48
10. TX Recwmg maronSNCIKBC 9 roses o Ecma Pse Paa Ks KBDDAT 0 Pas KB5_PTRDAT O Ecma psoas 7 wrie enable touch i fme 5 Panellb 3 2 10 0000 124 TFT 5 0 Charge contolenable N 85 BMGPWRENA O BMGVGCpoweentie Pos 8 5 0 Poa 85 SUSPEND O Sepemicowoembe FPosiMsPWREDg ewen 00 o eaey O Foz 6m5 smara SMCSMremes O O Froes pena Detect Pinter or exeral FOD FD memwa F12 85 CPUSTPE Detect GPU cockstop masus amy ecese 0 0 oam 20 21 202 1 22 Table 1 13 GPIO Port Definition Map pa 10 2 2 SM5 BAYSW Detect FDD CD bay installed not paa o o pas pps o o SoSo SoS C N 1 0 P3 0 5 5 RXD Receiving data from KBC to SMC P3
11. 3 12 4 Disassembly and Unit Replacement GSMS FAs ATO TMA ATO 5 0 558 58 0 er iE REOR 4 1 4 1 1 You 4 1 4 1 2 eed am eec erect 4 3 4 1 3 Disassembly 4 4 Removing ithe Module 4 6 Replacing the Hard Disk Drive 4 7 Replacing EE HEU HE 4 8 Removing the Keyboard 4 10 4 12 Removing iie tir P tte E Pr 4 13 Disassembling the 4 14 4 8 1 4 8 2 4 8 3 4 8 4 4 9 Disassembling the Display Appendices Appendix A Appendix B Appendix C Appendix D Appendix E Detaching the Lower Housing from the Inside Assembly Detaching the Upper Housing from the Inside Assembly Removing the Touchpad Removing the Main Model Number Definition Exploded View Diagram Spare Parts List Schematics BIOS POST Checkpoints ix List of Figures 14 1 2 1 8 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 1 13 1 14 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 4 1 4 2 4 3
12. 418 614 ETSUH EH zra zvu SUCRE 31388318 E14 ire E SUH irae rre ee 81 sense Tg oes ons TI eu 29 ONG Oo 207 668 SEB Stan EW por 68 cu LOS eg tey EHW lt 668 6 Ze izoaw enni 288 STON EWN 888 ee ASAEd ITATTA 1 se 6108 634 SE i amp 8IU8 EJd YE 81 E INS E34 eea eea ceu 612 1NS5I3d 50 zee 58 6 168 169 168 91 TFINS E34 ONS per 885815 qaz rer ose mier 8 1 8 6247765 828 628 ez 8 5 25 55 558 828180 MSD al ae 808 ge emer ENE 95 828 STOW ENE S1 Z 8038133 128 170 124 213 75 Lt CrON ETA SOR 76 Lt VTOK EKN greet sp aoa ead 328 3t MEAE ASAE 228 ASAE 4 5 25838834 so CL ITUU eJd 01 168 EWN SES Mas Ed
13. Vendor amp Model Name Ambit T62 036 C 00 Short circuit protection The DC DC converter shall be capable of withstanding a continuous short circuit to any output without damage or over stress to the component traces and cover material under the DC input 7 19 V from AC adapter or 18V from battery It shall operate in shut down mode for the shorting of any de output pins mV System Introduction 1 39 1 6 26 DC AC Inverter DC AC inverter is used to generate very high AC voltage then supply to LCD CCFT backlight use The DC AC inverter area should be void to touch while the system unit is turned on Table 1 37 DC AC Inverter Specifications 8 Ambit 62 055 00 Ambit T62 088 C 00 Used LCD type ITSV50D 12 1 TFT LG LP133X1 13 3 TFT Output voltage Vrms with load 650 typ 650 typ 1 6 27 Adapter Table 1 38 AC Adapter Specifications Specification Vendor amp Model Name ADP 45GB C1 50 115Vac 100 230Vac 84 min 115Vac full load Noise Ripple mV 300 mVp p 25 max Turn on delay time 2 sec 115 Vac Hold up time 5 ms min 115 Vac input full load Short circuit protection Output can be shorted without damage auto recovery Primary to secondary 3000 10mA for 1 second or 4242Vdc 10mA for 1 second Leakage current 25mA max 254Va
14. 4844 RE mH ec lg ls ss 07007707 V 5 M 840 0 iQ 2 Aem D Lx E PIDE Y SE Se 2 e vy AA 2 5 41 B ue 3 251 gt oo ww i Schematics 5 o o Ivi ni 252 2 2 5 23 ENTIRL CONFID u36 s194100Y 1 1 si d s 2 2 D 24 Service Guide Schematics 5 V 81 2 T uL 5 5 o Seine lt 9 gt a T j gt gt 25
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16. 2 40 87C552 Block 2 44 8705952 RN Diagram a 2 45 NS87338VJG Block 2 50 NS87338VJG Pin 2 51 GE PID6832 aver 2 60 162 036 C PinsDiagram 2 72 162 055 Diagramm 2 74 T62 088 C Pin 2 75 Removing the Battery 4 2 Using Plastic Stick on Connector With 4 3 Disassembly 4 5 Removing the 4 6 Removing the Hard Disk Drive Bay 4 7 Removing the Hard Disk 4 7 Installing a Memory 4 8 4 8 4 9 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 4 19 4 20 4 21 4 22 4 23 4 24 4 25 4 26 4 27 4 28 4 29 Installing and Removing 4 8 Removing the Display Hinge 4 10 Removing the Center Hinge Cover 4 10 Lifting Out t
17. NT30 21118 ure NTO SEON ENN 171 18 NT3O st 88 SEES NT3U 511 88 SEU 54 58 SEES Asp do RE NT3G T0 Mim IET ZOW EWN a lt 10i tTI 03483534 EL meit i tirit gt aan oe prj 19 Thr ONS 9 RM T UNS 6 SIND HNDI ale 3 6148146 1 S e tes al on 15164 E Ti z DP 222273 21 sx 252221 2008 44444 8 1 A AAA AA 14 ajale elele sze 23 ele 3 14545 B 1 55551140 1 ele 11 a i s 115 411 ees jene AJ M ele o 1 sisse 4 K a 4
18. i ODD m 1 20 20 avian IX RSV OV m z 005 000 ve i 200 wan 3 10 6 WaISAS 801104533 09 i 36vo Haan 10020899 56 02 555 NN 10 2 548 ASSY 36 2 834 10074089709 2 ASSY SISSVHO 100 v 5 9XeWN HOAW 3 95 0849 98 SI INO I9XG cNW AOTAN HOVW 48425 089 98 vi Tx 1046 EET Nd 200 0VcYl ET EX dNVd 319 14 20090Vcv I el D VOX 414 IXEETd WIT 1009 4096 1046 HOLY c0 0divev 491 AUS 4 10071 2 6 403 JONII 100 197 VE 8 026 4 A SSV IdNVd 021 200 IvVecv 09 L SNIT 021 100 vivav 9 10 6 04 NOISNO 21 100 50 27 5 319174 14 13439 021 T0080V2v TE IARSMA 13438 021 100 0 L 10 6 dOd A SSV 14 48 021 200vIiv2av 09 1239 4431 200 0 1 4 18
19. wo s Dorai Power Suppyputon 50V orsay 2 ws p Doo ala 2 42 25 Philips 87C552 System Management Controller The 87C552 Single Chip 8 Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family The 87C552 has the same instruction set as the 80C51 The 87C552 contains a 8kx8 a volatile 256x8 read write data memory five 8 bit ports one 8 bit input port two 16 bit timer event counters identical to the timers of the 80C51 an additional 16 bit timer coupled to capture and compare latches a 15 source two priority level nested interrupt structure an 8 input ADC a dual DAC pulse width modulated interface two serial interfaces UART and watchdog timer and on chip oscillator and timing circuits For systems that require extra capability the 87 552 can be expanded using standard TTL compatible memories and logic In addition the 87C552 has two software selectable modes of power reduction idle mode and power down mode The idle mode freezes the CPU while allowing the RAM timers serial ports and interrupt system to continue functioning The power down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative The device also functions as an arithmetic processor having facilities f
20. Operating 5 25 6Hz 0 38mm 25 6 250Hz 0 5G Sweep rate gt 1 minute octave Number of test cycles 2 axis X Y Z Non operating 5 27 1Hz 0 6G 27 1 50Hz 0 016 50 500Hz 2 0G Sweep rate 0 5 minutes octave Number of text cycles 4 axis X Y Z Non operating 5 62 6Hz 0 51mm 62 6 500Hz 4G Sweep rate 0 5 minutes octave Number of text cycles 4 axis X Y Z Non operating unpacked 40G peak 11 2 half sine Non operating packed 50G peak 11 2ms half sine Operating 10 000 feet Non operating 40 000 feet Air discharge 8kV no error 12 5kV no restart error 15kV no damage Contact discharge 4kV no error 6kV no restart error 8kV no damage System Introduction 1 43 1 44 1 9 Mechanical Specifications Table 1 40 Mechanical Specifications Specification Weight includes battery and FDD 12 1 TFT SVGA LCD and 12 5mm HDD 3 3 kgs 7 2 106 Adapter 230 g 0 52 Ib Dimensions round contour 297 313mm x 233 240mm x 50 53mm main footprint 11 7 x 9 1 x2 Service Guide Chapter Major Chips Description 2 This chapter discusses the major components 2 1 Major Component List Table 2 1 Major Chips List PIIX4 82371AB South Bridge 2160 Flat Panel Video Accelerator 87C552 Philips Single chip 8 bit controller for SMC System Management Controller NS97338 NS National Semiconductor Super controller CL PD6832 PCI to Card
21. 3 01 CLKRUN DEVSEL FRAME IDSEL 82371AB Pin Descriptions PCI ADDRESS DATA AD 31 0 is a multiplexed address and data bus During the first clock of a transaction AD 31 0 contain a physical byte address 32 bits During subsequent clocks AD 31 0 contain data A PIIX4 Bus transaction consists of an address phase followed by one or more data phases Little endian byte ordering is used AD 7 0 define the least significant byte LSB and AD 31 24 the most significant byte MSB When is a Target AD 31 0 are inputs during the address phase of a transaction During the following data phase s 4 may be asked to supply data on AD 31 0 for a PCI read or accept data for a PCI write As an Initiator PIIX4 drives a valid address on AD 31 2 and 0 on AD 1 0 during the address phase and drives write or latches read data on AD 31 0 during the data phase During Reset High Z After Reset High Z During POS High Z BUS COMMAND AND BYTE ENABLES The command and byte enable signals are multiplexed on the same PCI pins During the address phase of a transaction C BE 3 0 define the bus command During the data phase C BE 3 0 are used as Byte Enables The Byte Enables determine which byte lanes carry meaningful data applies to byte 0 C BE1 to byte 1 etc PIIX4 drives C BE 3 0 as an Initiator and monitors C BE 3 0 as a Target During Reset High Z After Reset High Z During
22. 9 9225 98 oz 100209208 012 009 98 043 OH 20008999 Por z avun vo 7 uo zavr NIS I3 ONN 00050 2 ASS 10079089709 m i Qux Weer zv 20 00 2 21090021 102 1 z 1004 05089928 TEXEN 2287 1002168 16 808 3890 1 022 9 09 i 899 808 1 2 004 14015010956 2 009092919 n DO ZOvZv 2 208 mper 129 s1 126690 ASSv Odd 044 20079 89 2 ZON DL si 13950 100 6 27 Zor WING 4400NVLS 10827 LON A302 107 D SNS 5 ASSV 004 10020089759 N ASSY 83400 OWA 09 snedeva 2 1 MIHIS TGSVI 98 20 2 MINIS 8 3Vid 002092515 ASSY M 1 10070 0 09 ASSV 13238 00 00 00 29
23. 1148 gt sdis E 8 08 S 2312415114 fet 198 19854 338 3 634 617 815 tea Rud 198 HA RR 028 ONS ger 888 ONS 23 2338 3 t34 61 91 5 2514 858 658143 8411 esa 8 30 1 22561 81 5 per 8858 ase Re 3355010433 258 158 714 58 1658 76 YON 088 pss teoei etum cog 2955 85 TEUK 03183631 521 858 5581 56 NEAEd 258 124155 0031235301 VEL ecg ts Bey 624 1411 cca 13 E 288 gou es zsa 048818 LICE tet 158 189 7z 8 E34 ter 158 158 spa 5 TW5 852 858 088 3045 S arr 678 SEDE E d reom eni ett 608 rey TUI ort TUW EHW LiT 618 ieu EF ed LIFI 1780 aru SUN CHW us Her HEP err 7B tee TeX wir err 28 ETU evX eun ett 578 Evel ep
24. PIIX4 implements the passive release SYSTEM ERROR SERR can be pulsed active by any PCI device that detects a system error condition Upon sampling SERR active PIIX4 can be programmed to generate a non maskable interrupt NMI to the CPU During Reset High Z After Reset High Z During POS High Z STOP STOP indicates that 4 as a Target is requesting an initiator to stop the current transaction As an Initiator STOP causes 4 to stop the current transaction STOP is an output when is a Target and an input when 4 is an Initiator STOP5 is tri stated from the leading edge of PCIRST STOP remains tri stated until driven by PIIX4 as a slave During Reset High Z After Reset High Z During POS High Z 2 10 Service Guide Table 2 2 82371AB Pin Descriptions Lee m emm 0 TRDY TARGET READY TRDY indicates PIIX4 s ability to complete the current data phase of the transaction TRDY is used in conjunction with IRDY A data phase is completed when both TRDY and IRDY are sampled asserted During a read TRDY indicates that as a Target has place valid data AD 31 0 During a write it indicates PIIX4 as a Target is prepared to latch data TRDY is an input to PIIX4 when is the Initiator and an output when 4 is a Target TRDY is tri stated from the leading edge of PCIRST TRDY remains tri stated until driven by as a slave During Reset High Z After Reset
25. Service Guide 1 43 Media Board Top Side mi 02 011 MADE IN TAIWAN R 0 C TOLERANCES ARE 707 Media ae 010 28 AUG 97 1 xxx 005 ERATIONS DECIMALS ANGLES Figure 1 7 Media Board Top Side System Introduction 1 13 1 4 4 Media Board Bottom Side TD nm C SILK BOT Media Des b L PILOT U 5 ATE EV wy 8 Auc ar Figure 1 8 Media Board Bottom Side 1 14 Service Guide 1 5 Jumpers Connectors 1 5 1 Mainboard CN7 CN13 14 CN15 CN1 USB 8 CN9 Multimedia board connector CN2 VG
26. 1 34 External CRT Resolution 1 34 LCD Resolution 1 34 Audio Speciflcations heim nea EE 1 35 E 1 35 Parallel Port 1 36 Serial Port 1 36 Touchpad 1 36 SIR FIR 1 37 Speciications Ee 1 37 CD ROM 1 38 Diskette Drive 1 38 Hard Disk Drive 1 39 Keyboard 1 39 1 35 1 36 1 37 1 38 1 39 1 40 2 10 341 3 2 441 1 1 D 1 E 1 Battery 1 40 DC DC Converter 1 40 DC AC Inverter 1 41 Adapter 1 41 Environmental 1 44 Mechanical 1 45 a 2 1 82971AB Pin Descriptions aeu uua 2 9
27. DMA ACKNOWLEDGE These signals are the DMA grants for 9 11 protocol They are used by a 4 to acknowledge DMA services and follow the PCI Expansion Channel Passing protocol as defined in the section the PC PCI request is not needed these pins can be used as general purpose outputs During Reset High After Reset High During POS High GPO TERMINAL COUNT PIIX4 asserts TC to DMA slaves as a terminal count indicator PIIX4 asserts TC after a new address has been output if the byte count expires with that transfer TC remains asserted until AEN is negated unless AEN is negated during an autoinitialization TC is negated before AEN is negated during an autoinitialization During Reset Low After Reset Low During POS Low Major Chips Description 2 15 Table 2 2 82371AB Pin Descriptions nme 0 APICACK GPO12 APIC ACKNOWLEDGE This active low output signal is asserted by 4 after its internal buffers are flushed in response to the APICREQ signal When the I O APIC samples this signal asserted it knows that PIIX4 s buffers are flushed and that it can proceed to send the APIC interrupt The APICACK output is synchronous to PCICLK If the external APIC is not used then this is a general purpose output During Reset High After Reset High During POS High GPO APIC CHIP SELECT This active low output signal is asserted when the APIC Chip Select is enable
28. is depressed from system powered on till POST or not If yes set BIOS Setup parameter too default settings or keep the original settings BIOS POST Checkpoints E 1 Table E 1 POST Checkpoint List Tests programmable interrupt controller 8259 nitializes system interrupt Enables system shadow RAM ssues 161 software SMI to communicate with PMU Initializes interrupt vectors Set fixed CMOS setting CPU clock checking Sets the DRAM timing in correspondent to the system speed Scans PCI Devices to Initialize the PCI buffer that used by BIOS solations for PnP ISA Card Initializes video display Note If system has any display card here it should be initialized via its ROM or corresponding initialization program VGA BIOS POST e Enables video shadow RAM Displays Acer or OEM logo if necessary Displays Acer copyright message if necessary Displays BIOS serial number External Cache sizing Tests keyboard interface Note The keyboard LEDs should flash once 3 3E 35h 4h ___ Configurations for PnP ISA Card Initializes the PCI device according to ESCD data if ESCD data is valid Initialize the PCI Devices by BIOS Initialize the PCI VGA card En san Sch SE are available to read valid time and date information 24h 30h 34h 5Ah 56h 3Fh 3Ch 3Eh 4Ch 35h 4Eh 4Fh 50h Exh
29. 7300 Series Notebook Computer Service Guide 10096 Recycled Paper PART NO 49 42A01 001 DOC NO SG238 9712A PRINTED IN TAIWAN Copyright Copyright 1998 by Acer Incorporated All rights reserved No part of this publication may be reproduced transmitted transcribed stored in a retrieval system or translated into any language or computer language in any form or by any means electronic mechanical magnetic optical chemical manual or otherwise without the prior written permission of Acer Incorporated Disclaimer Acer Incorporated makes no representations or warranties either expressed or implied with respect to the contents hereof and specifically disclaims any warranties of merchantability or fitness for any particular purpose Any Acer Incorporated software described in this manual is sold or licensed as is Should the programs prove defective following their purchase the buyer and not Acer Incorporated its distributor or its dealer assumes the entire cost of all necessary servicing repair and any incidental or consequential damages resulting from any defect in the software Further Acer Incorporated reserves the right to revise this publication and to make changes from time to time in the contents hereof without obligation of Acer Incorporated to notify any person of such revision or changes Intel is a registered trademark and Pentium is a trademark of Intel Corporation Other brand and product name
30. List System activities System activities and timer retriggers _ Power off either or both FDD and CD ROM Tri state FDD and CD ROM interfaces and stop IDE controller clock Timer retriggers The I O access to 3F4 3F5 FDD 7 376 CD ROM will retrigger the timer Detective hardware The FDDBEN signal on of U21 PIIX4 is from L to CD ROM change buffer is disabled The pin T14 PX3 CD FDPON of U21 PIIX4 is from to FDD CD ROM is powered off 1 6 7 2 Component activities in power saving mode 9 disk The hard disk is fully power managed This means that when the hard disk is not in use the hard disk is powered off The following pins are dedicated toward the management of power on the hard disk 1 HDD power enable pinY15 PX3 HDPON This pin turns the power on off for the hard disk only 2 HDD reset pinW14 PX3_HDRST of PIIX4 This pin provides the reset to the drive when the drive is newly powered up The reset pin is asserted when the drive is first powered up then the reset is removed after the drive is powered up and before the interface is enabled CD ROM The CD ROM and the hard disk are both IDE devices They share the same controller The following pins are dedicated toward the management of power on the CD ROM 1 CD ROM buffer enable pin M3 of U21 PX3 FDDBEN of PIIX4 The CD buffer enable separates the CD
31. 5 0 0 Enable over temperature of CP orsysem ur OMdMedn mou N opnar i 1 Detect evsion i Detect module revision eens er moa is 1 DeetMMOmoerison mog Detect ao module revision GPit7 SM5_FLOATREGH Ka 1 Detect oat request rom SHO PXa_FLASHRGY i 0 Enable ash BIOS recovery 00 mms 0000 1 Detect socket A activi for 028832 Pereme acr Detect socket B activi ________ Table 1 13 GPIO Port Definition Map FLED MIREGH o O O O y FLED 1 KOS NUMLEDH 9 ______ N oO oS ma ms mse System Introduction 1 21 Table 1 13 GPIO Port Definition Map amo fo moa 1 MEMBOAG oof memoy sao memeo 1 memory bao MODE _____ ___ Detect KBD mode PAA KSE MENGIAS 1 Adress Oofmemonybankt SS Psw I Enae Passoa O 1 _ Adress tof memory san exa oem 1
32. AT3 CPAR 7 16 14 A IOWRICAD15 14 13 ATUCADI2 VSUCVST OE CAD11 9 L RING GNO A DiS CADB CET CC BEOK n A 014 A_D7 CAD7 A_D13 CAD6 4 5 A DI2 CADA DS CAD3 lt _011 2 A_D4 CAD1 _ 1 RING GND ADO ADI lt gt lt m lt AD3 A pound sign at the end of a pin name indicates an active low signal for the PCI bus A dash at the beginning of a pin name indicates an active low signal for the PCMCIA bus Service Guide the end of a pin name indicates active low signal that is a general interface for the CL PD6832 A double dagger superscript at the end of the pin name indicates signals that are used for power on configuration switches Thel O type code I O column indicates the input and output configurations of the pins on the CL PD6832 The possible types are defined below ho mem 0 GOD openan ounn The power type code Pwr column indicates the output drive power source for an output or the up power source for an input pin on the CL PD6832 The possible types are defined below Power Type Output or Pull up Power Source 5v powered from a 5 volt power
33. bridge such as the Intel 380FB PClset which implements a PCI ISA docking station environment PIIX4 supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disks and CD ROMs Up to four IDE devices be supported in Bus Master mode PIIX4 contains support for Ultra DMA 33 synchronous DMA compatible devices PIIX4 contains a Universal Serial Bus USB Host Controller that is Universal Host Controller Interface UHCI compatible The Host Controller s root hub has two programmable USB ports PIIX4 supports Enhanced Power Management including full Clock Control Device Management for up to 14 devices and Suspend and Resume logic with Power On Suspend Suspend to RAM or Suspend to Disk It fully supports Operating System Directed Power Management via the Advanced Configuration and Power Interface ACPI specification PIIX4 integrates both a System Management Bus SMBus Host and Slave interface for serial communication with other devices 2 2 2 Architecture Block Diagram The following is the architectural block diagram of the PIIX4 with respect to its implementation in this notebook computer Host to PCI Bridge Host Bus Main Memory DRAM Second Level Cache CD ROM Quse D BMI IDE Ultra DMA 33 PIIX4 Hard Disk GP I O 30 SMBus ISA EIO 8 3 5V Tolerant Figure 2 1 PIIX4 Architecture Block Diagram 2 6 Service Guide 2
34. 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 1 13 1 14 1 15 1 16 1 17 1 18 1 19 1 20 1 21 1 22 1 23 1 24 1 25 1 26 1 27 1 28 1 29 1 30 1 31 1 32 1 33 1 34 Rear Port 1 3 Port rd rd tnt dit tels 1 5 Indicator Light 1 5 Hot Key Descriptions 1 6 Eject Menu Item Description Ssss aiaa 1 7 System Specifications note teres 1 9 Mainboard Jumpers Pads Settings Bottom Side 1 17 System Memory ER ERE 1 19 Interrupt Map ede veneered ene 1 19 1 19 Channel 1 20 GPIO Port Definition 1 21 Port Definition Map 1 22 Devices Assignment a 1 25 1 26 CPU Module 1 31 BIOS 1 32 System Memory 1 32 SIMM Memory Combination 1 33 Video Memory 1 33 Video Display
35. T logo Blank logo Y Keyboard language version 0 Swiss for ANW with US power cord US for standard model with US power cord US for standard model with European power cord US for ACI w o power cord US for ACLA with US power cord US for AAC with US power cord US for PRC with CCIB power cord Spanish for ACLA with US power cord Turkish for ACI w o power cord Chinese for ACI w o power cord Arabic for ACI w o power cord Belgian for ANW with European power cord Chinese for STK with US power cord Danish for ANW with European power cord US for ACI w o power cord Hebrew French for AWE with European power cord German for ACE with European power cord US for AWE with European power cord Dutch Italian for AWE with European power cord Japanese for OEM with Japanese power cord Korean for ACI with European power cord US for ACE with European power cord Eastern European US for ACE with European power cord Pan European Norwegian for AWE with European power cord Portuguese for AWE with European power cord US for ACLA with US power cord Brazilian Portuguese Russian for ACI with US power cord Spanish for AWE with European power cord Thai for ACI with US power cord UK for AWE with UK power cord Swedish for AWE with European power cord Finnish Swedish for AWE with European power cord Swedish Swiss for ACE with European power cord Swiss German Swiss for ACE with European power cord Swiss French w o
36. 1 5 1 2 4 5 EE et 1 6 1 2 5 Automate 1 8 1 3 System Specification 1 9 1 4 Board EayoUL 1 11 1 4 1 System Board 5106 RR PEE 1 12 1 4 2 System Board Bottom 1 13 1 4 3 Media Board 1 14 1 4 4 Media Board Bottom 1 15 1 5 Jumpers and Connectors nnn 1 16 1 5 1 1 16 1 5 2 Boards 1 18 1 6 System Configurations and Specifications 1 19 1 6 1 System Memory 1 19 1 6 2 Interrupt Channel 1 19 1 6 3 Address Map rre 1 19 1 6 4 Channel 1 20 1 6 5 GPIO Port Definition enm 1 21 1 6 6 PCI Devices 1 25 1 6 7 Power 1 25 1 6 8 CPU 1 31 1 6 9 1 32 1 0 10 SystemiMemory 1 32 16 11
37. Clock Active clock input signal of 14 318 MHz 24MHz or 48MHz ZWS Zero Wait State This pin is the Zero Wait State open drain output pin when bit 6 of FCR is 0 ZWS is driven low when the EPP or ECP is written and the access can be shortened 2 58 Service Guide 27 CL PD6832 PCI to CardBus Host Adapter The CL PD6832 is a single chip PC Card host adapter solution capable of controlling two fully independent CardBus sockets The chip is compliant with PC Card Standard PCMCIA 2 1 and JEDIA 4 1 and is optimized for use in notebook and handheld computers where reduced form factor and low power consumption are critical design objectives The CL PD6832 chip employs energy efficient mixed voltage technology that can reduce system power consumption The chip also provides both Hardware and Software Suspend modes which stop the internal clock and an automatic Low Power Dynamic mode which stops the clocks on PC Card sockets and stops internal clock distribution thus turning off much of the system power The CL PD6832 allows easy translation of incoming memory commands to PC Card 16 commands for processors with memory commands only The CL PD6832 enables such processors to use PC Card I O devices with fully programmable windows PC applications typically access PC Cards through the socket card services software interface To assure full compatibility with existing Socket card services software and PC card applications the register
38. IOIS16 Card Interface mode this input is CCLKRUN interpreted as the status of the write protect switch on the PCMCIA card In I O Card Interface mode this input indicates the size of the I O data at the current address on the PCMCIA card In CardBus mode this pin is the CardBus CLKRUN signal which starts and stops the CardBus clock CCLK INPACK Input Acknowledge The INPACK function CREQ is not applicable PCI bus environments However for compatibility with other Cirrus Logic products this pin should be connected to the PCMCIA socket s INPACK pin In CardBus mode this pin is the CardBus REQ signal Ready Interrupt Request In Memory Card Interface mode this input indicates to the CL PD6832 that the card is either ready or busy Card Interface mode this input indicates a card interrupt request In CardBus mode this pin is the CardBus Interrupt Request signal This signal is active low and level sensitive WAIT Wait This input indicates a request by the CSERR card to the CL PD6832 to halt the cycle in progress until this signal is deactivated CardBus mode this pin is the CardBus SERR signal CD 2 1 Card Detect These inputs indicate to the CCD 2 1 CL PD6832 that a card is in the socket They are internally pulled high to the voltage of the 5V power pin In CardBus mode these inputs are used in conjunction with CVS 2 1 to detect the presence and type of card Major Chips
39. MIDI baud rate support Infrared support on UART2 IrDA 1 0 SIR IrDA 1 1 MIR and FIR and Sharp SIR The Address Decoder e 6 bit or 10 bit decoding External Chip Select capability when 10 bit decoding Full relocation capability No limitation Enhanced Power Management Special configuration registers for power down Enhanced programmable power down command Auto power down and wake up modes 2 special pins for power management Typical current consumption during power down is less than 10 uA Reduced pin leakage current Voltage support 3 3 5V operation The General Purpose Pins for 2 separate programmable chip select decoders can be programmed for game port control Plug and Play Compatible 16 bit addressing full programmable 10 selectable IRQs 4selectable DMA Channels SIRQ Inputs allows external devices to mapping IRQs 100 Pin TQFP package PC97338VJG Major Chips Description 2 49 2 6 2 Block Diagram Config Serial Serial IR Inputs Interface Interface Interface Configuration UART pol IrDA HP amp Sharp IR Floppy Disk Controller with Digital Data Separator Enhabced 8477 Registers 16550 or 16450 16550 or 16450 i Floppy Drive ain Power 4 Interface urpose Down Logic arallel Port Registers Hifh Curr
40. from MEMRi only if BIOS space has been decoded depending on the cycle type When the rising edge of IOR or MEMR occurs PIIX4 negates XDIR For DMA read cycles from the X Bus XDIR is driven low from DACKx falling and negated from rising At all other times XDIR is negated high If the X Bus not used then this signal can be programmed to be a general purpose output During Reset High After Reset High During POS High GPO XDIR GPO22 2 14 Service Guide Table 2 2 82371AB Pin Descriptions 05 TRANSCEIVER OUTPUT ENABLE is tied directly to the output enable of a 74 245 that buffers the X Bus data XD 7 0 from the system data bus SD 7 0 is asserted anytime a PIIX4 supported X Bus device is decoded and the devices decode is enabled in the X Bus Chip Select Enable Register BIOSCS KBCCS RTCCS MCCS or the Device Resource 0 and Device Resource C PCCS1 XOE is asserted from the falling edge of the ISA commands IOWz MEMR or for PCI Master and ISA master initiated cycles is negated from the rising edge of the ISA command signals for PCI Master initiated cycles and the SA 16 0 and LA 23 17 address for ISA master initiated cycles is not generated during any access to an X Bus peripheral in which its decode space has been disabled If an X Bus not used then this signal can be programmed to be a general pur
41. 2 26 Service Guide Table 2 2 82371AB Pin Descriptions continued Wane CONFIG2 CONRGURATION SELECT2 This input signal is used to select the positive or subtractive decode of FFFFOOOOh FFFFFFFFh memory address range top 64 Kbytes If CONFIG 2 0 the will positively decode this range If CONFIG 2 1 the 4 will decode this range with subtractive decode timings only The input value of this pin must be static and may not dynamically change during system operations PWROK POWER OK When asserted PWROK is an indication to PIIX4 that power and PCICLK have been stable for at least 1 ms PWROK can be driven asynchronously When PWROK is negated PIIX4 asserts CPURST PCIRST RSTDRV When PWROK driven active high PIIX4 negates CPURST PCIRST and RSTDRV SPKR SPEAKER The SPKR signal is the output of counter timer 2 and is internally ANDed with Port 061h bit 1 to provide the Speaker Data Enable This signal drives an external speaker driver device which in turn drives the ISA system speaker During Reset Low After Reset Low During POS Last State TEST TEST MODE SELECT The test signal is used to select various test modes of 4 This signal must be pulled up to Vcc SUS for normal operation VCC CORE VOLTAGE SUPPLY These pins are the primary voltage supply for the PIIX4 core and IO periphery and must be tied to 3 3V VCC RTC V RTC WELL VOLTAGE SUPPLY This pin is the supply voltage for
42. 2 34 Service Guide 2 3 2160 Descriptions Number Pinname vo Description BLUE This DAC analog output drives the CRT interface Analog 101 REXT DAC Current reference This pin is used as current reference Analog the internal DAC Please refer to the NM2160 system schematics for the external circuit 79 CSYNC Composite Sync This output is the composite synchronization T S signal for RGB to NTSC or PAL SECAM External Analog Encoders 74 NTSC PAL O NTSC PAL SECAM Encoding Selection This pin is used to select T S the mode NTSC or PAL SECAM in which the external analog encoder need to be driven 147 FSC Sub Carrier Frequency Selection This pin provides an appropriate Sub carrier frequency 1xfsc or 4xfsc to an external NTSC or PAL SECAM analog encoder RED This DAC analog video red component output is to drive the Analog external RGB to NTSC or PAL SECAM analog encoders 97 G GREEN This DAC analog video green component output is to Analog drive the external RGB to NTSC or PAL SECAM analog encoders BLUE This DAC analog video blue component is to drive the Analog external RGB to NTSC or PAL SECAM analog encoders external Standby Standby Status1 The direction of the pin is controlled by GR18 bit Status1 3 In output mode this pin indicates the state of standby mode The state of this pin is reflected in register CR25 bit 5 and can be used as a status pin Suspend Suspend Th
43. A4h Sets video mode Issues 3rd software SMI to communicate with PMU Starts all power management timers Checks whether system is resumed from OV suspend or not Clear memory buffer used for POST Select boot device Shutdown 5 e Shutdown A e Shutdown B BOh BDh BEh Fh B BIOS POST Checkpoints E 3
44. Figure 4 24 Removing the PC Card Slots 4 18 Service Guide 49 Disassembling Display Follow these steps to disassemble the display 1 Remove the teardrop shaped LCD bumpers at the top of the display and the long bumper on the LCD hinge Figure 4 25 Removing the LCD Bumpers 2 Remove four screws on the display bezel or 6 ES Screw list 216 x2 for 11 3 or 11 8 LCD 2 516 x2 for 12 1 LCD M2 5L6 bind head x2 Figure 4 26 Removing the Display Bezel Screws Disassembly and Unit Replacement 4 19 3 Pull out and remove the display bezel by pulling on the inside of the bezel sides Figure 4 27 Removing the Display Bezel 4 Remove the four display panel screws and unplug the inverter and display panel connectors Then tilt up and remove the display panel Screw list QM2 5L6 bind head x4 Figure 4 28 Removing the Display Panel Screws and the Display Connectors 4 20 Service Guide 5 Remove two display assembly screws and unplug the display cable connector from the display cable assembly Then remove the LCD inverter and ID boards Screw list M2 5L6 bind head x2 LCD Inverter DC AC inverter Figure 4 29 Removing the Display Cable Assembly Disassembly and Unit Replacement 4 21 A Model Number Definition This appendix shows the model number definition of the notebook TravelMate 7300 VU WXY 2 s 2 Acer or TI logo
45. High Z During POS High Z Note All of the signals in the host interface are described in the Pentium Processor data sheet The preceding table highlights PIIX4 specific uses of these signals BALE IOCHK GPIO IOCHRDY 1 5168 Major Chips Description 2 11 ADDRESS ENABLE AEN is asserted during cycles to prevent slaves from misinterpreting cycles as valid cycles When negated AEN indicates that an 1 slave may respond to address and 1 commands When asserted AEN informs resources on the ISA bus that a transfer is occurring This signal is also driven high during 4 initiated refresh cycles During Reset High Z After Reset Low During POS Low BUS ADDRESS LATCH ENABLE BALE is asserted by 4 to indicate that the address SA 19 0 LA 23 17 and signal lines are valid The LA 23 17 address lines are latched on the trailing edge of BALE BALE remains asserted throughout DMA and ISA master cycles During Reset High Z After Reset Low During POS Low CHANNEL CHECK IOCHK can be driven by any resource on the ISA bus When asserted it indicates that a parity or an uncorrectable error has occurred for a device or memory on the ISA bus A NMI will be generated to the CPU if the NMI generation is enabled If the EIO bus is used this signal becomes a general purpose input is accessing an ISA slave or during DMA transfers IOCHRDY is output when an exter
46. Lid Switch Figure 1 1 Lid Switch When you close the display lid the computer saves all data either to the hard disk or to memory depending on the When Lid Is Closed setting see section 3 4 1 When all data is saved the computer turns itself off When you reopen the lid the computer retrieves your data and resumes where you left off 1 2 Service Guide 1 2 Ports The computer s ports allow you to connect peripheral devices to your computer just as you would to a desktop PC The main ports are found on the computers rear panel The computer s left panel contains the computer s multimedia ports and PC card slots 1 2 1 Rear Panel Ports The computer s rear panel contains the computer s main ports and connectors as shown in the illustration below DC in Port PS 2 Port Serial Port Parallel Port Mini Dock Connector External CRT Port USB Port Infrared Port Figure 1 2 Rear Port Location Table 1 1 Rear Port Descriptions Bm ________ 0 DC in port E AC adapter and power outlet PS 2 port PS 2 compatible device PS 2 keyboard keypad mouse Serial port Serial device serial mouse UART16650 compatible Parallel port EPP ECP Parallel device parallel printer external floppy drive SETS HD External CRT port Se External monitor up to 1024x768x256 colors USB port 058 058 Infrared port Infrared aware dev
47. NM2160 Pin 2 31 5 UM 2 41 870552 Pin DESC PIONS fb ev 2 46 NS87338VJG Pin 2 52 CL PD6832 Pin 2 62 T62 036 C Pin 2 72 62 055 Descriptions RT EXTR EE ERE ERR IR ERR D Led 2 74 162 088 Pin Description 2 75 About My Computer 3 2 Start Up 3 11 Guide to Disassembly 4 4 Exploded View Diagram 5 B 1 Spare Parts 5 i eee oe Doer Deere Ea C 1 Schematics Diagram 1 66 60 nnns 1 POST Gheckpolnt Elster iere eire tiere ei E 1 xiii Chapter System Introduction The computer is packed with features that make it as easy to work with as it is to look at Here are some of the computer s features 1 1 Features PERFORMANCE Intel Pentium II 266 MHz processor 64 bit main memory and 512KB external L2 cache memory large display in active matrix TFT PCI local bus
48. lt lt lt lt lt lt lt 3388 2822860 88888208846 2800 8 28888884808888 01 225 2 99 lt 292252542 2598505552 922555558022 25552225229 OOO DLO 01 3 0 300920 06 TOA 00 CL PD6832 208 Pin PQFP or 203 204 2065 206 D PCI VCC 208 gi KaoYeoccog zd zs29UPTHTSuSSd4SunS s9 34895989 99z2429 9392923 CHT EO lt AES lt 2 gt CO GOS gt 1251212 2 9528252525255555285552 256 620 05555 gt 29929992 lt lt 0 lt lt gt 2 lt lt 5 9 Guto Tr 20010 95 5 2 z 58 amp E 8 8 CL PD6832 Diagram Pin Descriptions The following conventions apply to the pin description tables 2 60 RIL SB 253 at A VS2ICVS2 AGICAD20 25 019 RING ATICADIE 24 1 12 28 2 2 1 A_A2VICDEVSEL ALADY IREQICIN A_A20 CSTOPE A_ WE CGNT A_AISICBLOCK RING AM CPERRE A
49. o o E 17 o PLATE WAME LOGO mammas 0050 1 Prices subject to change without notice 2 Level 1 1 Stands for field replaceable Units FRU and customer replaceable Units CRU for System level 1 service repair use 3 Level 1 2 Stands for subassemblies of FRUs and CRUs which for component level service repair use 4 Level 2 Stands for consumed parts which are easily damaged while replacement action taken 2 Service Guide D Schematics This appendix includes the schematic diagrams of the notebook Table D 1 Schematics Diagram List System Board Ds wes Do Purp amp DowRessos Schematics D 1 Table D 1 Schematics Diagram List D 2 Service Guide Schematics RIPT UNETION D PAGE TION DESCRIPTION SYSTEM FUNC GE PORT INTERFACE PARALLEL PAGE INTERFACE SERIAL 8 USB PORT TORY 05 AND DEBUG CONNE FLASH SEN CLOCK BOARD CONNECTOR DIR MODULE CONNECTOR CONNECTOR CKING 00 ONNECTOR MOUSE AND MONITOR ER DATA TERMINATOR DRAM PWR NN amp CPUCORE BRIDGE 8 IN VR ROU ROLLER CON TERY amp RI BAT RTC CIRCUIT ROL
50. or with MTR1 and IDLE Major Chips Description 2 55 2 6 NS97338VJG Descriptions MSENO 50 49 MSEN1 Normal Mode MSENO 86 84 MSEN1 PPM Mode MTRO 44 41 MTR1 Normal Mode MTR1 8 PMM Mode PDO 7 92 89 87 84 4 1 21 m v RDATA 3 Normal Mode RDATA PPM Mode 2 3 1 7 7 3 E 2 56 Infrared Transmit Infrared serial data output Software configuration selects either IrDA or Sharp IR protocol This pin is multiplexed with SOUT2 BOUT CFGO Master Reset Active high output that resets the controller to the idle state and resets all disk interface outputs to their inactive states The DOR DSR CCR Mode command Configure command and Lock command parameters are cleared to their default values The Specify command parameters are not affected Media Sense These pins are Media Sense input pins when bit 0 of FCR is 0 Each pin has a 10 KO internal pull up resistor When bit 0 of FCR is 1 these pins are Data Rate output pins and the pull up resistors are disabled Media Sense These pins gives additional Media Sense signals for PPM Mode and PNF 0 FDC Motor Select 0 1 These are the motor enable lines for drives 0 and 1 and are controlled by bits D7 D4 of the Digital Output register They are active low outputs They are encoded with information to control four FDDs when bit 4 of the Function Enable Register FER is set MTRO exchanges log
51. su m 4 i Gi ee 2 0 4 sy 53 wg al 5 N 2 4 2128 5 E oy Schematics 585 2 6 Yo 7 enie INIH 2N1U 8 180114
52. 08 z Mas ouv ez 10000796 i 12029899 28 z 04240 244 100102209 i 10089 Jung i e SIL 139599 865980 00 xw 10050829 ASSY H3ADO 10010 2709 1 5 811 ASSY 08 00 10010 0959 W i 009 13N ico riser is 203 OREL MINDS 89 98 3 ioo vzeo zr 03 Taeva mamos 091225 198 OT E 00 39NH 1006089709 3 Z UO SNGZVZY 01 1048 201 20 2 55 107 1 13 3 3 8 100518916 200 100780899 Oy 08908 016092758 3 i 04 0010097 BE 1 05 105089709 4 3 9365 ioozoesv 08888998 obs 51008 ez ow 0892257198 z per 88 Da saver ve oov ASSY 0 00010895 08 1001997 zr OND 10050 2 16 LOX t BONY 10021899 7 5 10010 29 55 909 n HOnOL 1071892 WAN 10258998 f snaasvo 10011897 502 12 SI Lasva
53. 20 es T meas e DMA Acknowledge OUTL Left mixed analog output OUTR Right mixed analog output VREFI 111 Voltage reference input 1 O reference ouipat Dux 0 02 Dux 00 tMUNEmu uen p Umen 1 02 Sen 000 wm SYNDAG sample hold susa Riom SYNDAC sample hot capacior Donn 20 Major Chips Description 2 41 Table 2 4 Pin Descriptions numer io O Reemwhe 0000000 oco 1 vocon Non o tem 20 oo 1 0 sen i __ Eternal aymhesier enable mput o synthesizer chip select synthesizer clock input or ZV Eternal aynesize cock input oF ZV UR cookiou 1 1 Eternal synthesizer data input or svoo synthesizer masier cock ouput RSVD Reserved for future use wo momen 1 mp _ 1 xa h xo h 000 120 Dao h fe
54. 4 4 4 5 4 6 4 7 SWIICH 1 2 Rear Port LoGation er trt e 1 3 Left Port 1 4 1 5 System Board 1 12 System Board Bottom eene 1 13 Media Board 000000000 nian oi an onain 1 14 Media Board Bottom 5 1 15 Mainboard Jumpers and Connectors Side 1 16 Mainboard Jumpers and Connectors Bottom Side 1 17 Media Board Jumpers and Connectors Top Side 1 18 Media Board Jumpers and Connectors Bottom 506 1 18 System Functional Block Diagram 1 42 System Bus Block 1 43 4 Architecture Block 2 6 PIIX4 Simplified Block 2 7 2160 EE 2 30 NMA Block Diagram art ee P en n Ee d Pb P 2 39 Pin
55. 54h 58h 5Ch 5Eh 60h 64h 68h Enables UIE then checks RTC update cycle Note The RTC executes an update cycle per second When the UIE is set an interrupt occurs after every update cycle and indicates that over 999ms 70h LE Parallel port testing E 2 Service Guide Table E 1 POST Checkpoint List Checkpoint Description 84h KB device initialization 74h 78h 7Ch Oh Set KB led upon setup requests Enable KB device 86h Issue 2nd software SMI to communicate with PMU e Enable the use of BIOS Setup system information and fuel gauge Tests and initializes FDD Note The FDD LED should flash once and its head should be positioned password checking HDD CD testing 8 parameter table setup Initializes HDD CD enhanced features Displays POST status if necessary Changes POST mode to default text mode Initializes ROM Note I O ROM is an optional extension of the BIOS located on an installed add on card as a part of the I O subsystem POST detects I O ROMs and gives them opportunity to initialize themselves and their hardware environment 6Ch 6Dh 88h 90h 94h Shadows I O ROM if setup requests Builds up free expansion ROM table Initializes Card ROM e Writes ESCD data into NVRAM e Writes ESCD data into NVRAM Initializes timer counter for DOS use Initializes security feature ACh e Enables NMI e Enables parity checking 9 9 6h 7h AOh
56. 7 RING GND B_A19 CBLOCK 6 3 B_ WE CGNT _B_A2O CSTOP lt 4 BURDYHREQ CINT B A2I CDEVSEL AT amp CCLK 22 _ 15 1 m 2 4 _ 12 2 B A24 CAD17 at BH 18 4 4 B_A25 CAD19 RING GND A amp CAD20 VS2 CVS2 B AS CAD21 R SET CRST amp 22 3d _ 23 B_ INPACK CREQ 2 B A2 CAD24 B_ REG CC CBE3 Jd AUCADOS BVO2 SPKR LED CAUDIO 3 B AO CAD26 gt SVDi STSCHG RI CSTSCHG e RING_GND B OB CAD2B lt a _01 29 10 31 B 8 SOCKET VCC 8 WP HOISTG CCLKRUNS B CD2 CCD2s 3 i INTA ARQ9 RI OUT ANTBsARO 10 SOUT ANTC ASLD SIN ANTD ASDAT 4 3 RST CLKRUNE Figure 2 10 2 7 3 Pin Diagram o 5 a 2 2 9 2 ent 5 9 5 E 3 PEL o Ex So 3 005 8 8 OE ABs ooo 3S G lt o 625 25589238239 55555258686 2805 888 8 8 dhe Se 0 lt 65 lt 65 lt 9 lt gt 2 Or 05 lt lt
57. CHARGON BMCVCC 11 12 PSVRON CHARGFB 13 9 14 CHARGSP 13 14 P12VRON GND 15 16 GND GND 15 16 GND CHARGOUT 17 18 CHARGOUT P5VRON 17 18 CHARGOUT 19 20 CHARGOUT P5VRON 19 20 Figure 2 11 T62 036 C Diagram 2 8 2 Pin Descriptions Table 2 8 T62 036 C Pin Descriptions VDCF 1 1 2 3 4 18VDC input from battery DCIN UE 2 7 19VDC input from AC adapter 10 CHARGCL 11 Enables Charger output This input is driven by an open drain signal to set the charging current limit to a high 3 5A max or low 2A The lower limit is set when the signal is low switch on The system will generally set this signal low when the battery has been discharged to a low level The battery current sensor is built into the charger circuitry The resistance of the drain switch is less than 1 Note this signal sets the limit value of the charging current The CHARGFB and CHARGSP signals may restrict the charging current to a lower level CHARGON 12 This is a logic level signal active high to enable the adapter current output This signal allows the system board to turn off the charger output whenever the battery pack reports unsafe conditions such as over temperature error or no communication It may be used in response to any other detectable unsafe system conditions 1uA maximum loading This signal is provided by cur
58. DSKCHG 87 Disk Change This pin offers an additional Disk Change signal in PPM PPM Mode Mode when PNF 0 DSR1 74 UARTs Data Set Ready When low this indicates that the data set or DSR2 66 modem is ready to establish a communications link The DSR signal is a modem status input The CPU tests the DSR signal by reading bit 5 DSR of the Modem Status Register MSR for the appropriate channel Bit 5 is the complement of the DSR signal Bit 1 DDSR of the MSR indicates whether the DSR input has changed state since the previous reading of the MSR NOTE Whenever the DDSR bit of the NSR is set an interrupt is generated if Modem Status interrupts are enabled DSTRB 76 EPP Data Strobe This signal is used in EPP mode as data strobe It is an active low signal DTR1 69 UARTs Data Terminal Ready When low this output indicates to the DTR2 61 modem or data set that the UART is ready to establish a communications link The DTR signal can be set to an active low by programming bit 0 of the Modem Control Register to a high level A Master Reset operation sets this signal to its inactive high state Loop mode operation holds this signal to its inactive state ERR 77 Parallel Port Error This input is set low by the printer when an error is detected This pin has a nominal 25 KOHM pull up resistor attached to it 2 54 Service Guide 2 6 NS97338VJG Descriptions HDSEL 32 FDC Head Select This output dete
59. GPI12 Not available if using ring indicator feature Bit 27 GPI 13 21 Non multiplexed GPIs which are always available Non multiplexed GPIs which are always available which are always available Non multiplexed GPO which is always available Non multiplexed GPO which is always available which is always available LM 7 17 23 mem mm GENCFG Available as GPO only if EIO mode Bit 0 Non multiplexed which is always available The GPO 8 signal will be driven low upon removal of power from the PIIX4 core power plane Major Chips Description 2 25 Control Register and Bit PCI Function 1 GENCFG Not available as GPO if using for PC PCI Can be Bits 8 10 individually enabled so GPO 11 is available if REQ C not used XBCS Not available as GPO if using external APIC Bit 8 XBCS Not available as GPO if using external APIC Bit 8 GPO14 XBCS Not available as GPO if using external APIC Bit 8 GPO15 SUSB SUSB GENCFG Not available as GPO if using for power Bit 17 management GPO16 SUSC SUSC GENCFG Not available as GPO if using for power Bit 17 management GPO17 CPU_STP CPU_STP GENCFG Not available as GPO if using for clock control Bit 18 GPO18 PCI_STP PCI_STP GENCFG Not available as GPO if using for clock control Bit 19 GPO19 ZZ ZZ GENCFG Not available as GPO if using for power Bit 20 management GPO20 505 5 1 5
60. Guide 43 Replacing Hard Disk Drive Follow these steps 1 Turn the computer over to access the base 2 Remove the two screws from the hard disk drive bay cover and remove the cover Figure 4 5 Removing the Hard Disk Drive Bay Cover 3 Lift up 1 then pull out the hard disk drive then flip the hard disk drive over and unplug the hard disk drive connector Figure 4 6 Removing the Hard Disk Drive If you want to install a new hard disk drive reverse the steps described above Disassembly and Unit Replacement 4 7 44 Replacing Memory The memory slots SIMM1 and 51 2 are accessible via the memory door at the base of the unit Follow these steps to install memory module s 1 Turn the computer over to access the base 2 Remove the screws from the memory door and remove the door Figure 4 7 Installing a Memory Module 3 Remove the memory module s from its shipping container 4 Align the connector edge of the memory module with the key the connector Insert the edge of the memory module board into the connector Use a rocking motion to fully insert the module Push downward on each side of the memory module until it snaps in place To remove the memory module release the slot locks found on both ends of the memory slot to release the DIMM Then pull out the memory module Figure 4 8 Installing and Removing Memory Service Guide memory order for Suspe
61. Hardware Clock Throttle mode by asserting This causes to cycle STPCLK at a preset programmable rate If this function is not needed this pin can be used as a general purpose input 22 LOW POWER FOR L2 CACHE SRAM This signal is used to power down GPO19 a cache s data SRAMs when the clock logic places the CPU into the Stop Clock If this function is not needed this pin can be used as a general purpose output During Reset Low After Reset Low During POS Low Some of the General Purpose Input and Output signals are multiplexed with other PIIX4 signals The usage is determined by the system configuration The default pin usage is shown in Table 1 and Table 2 The configuration can be selected via the General Configuration register and X Bus Chip Select register GPI 21 0 GENERAL PURPOSE INPUTS These input signals can be monitored via the GPIREG register located in Function 3 Power Management System IO Space at address PMBase 30h See Table 1 for details 2 24 Service Guide Table 2 2 82371 Pin Descriptions GPO 30 0 GENERALPURPOSE OUTPUTS These output signals can be controlled via _ 0 GENERAL PURPOSE OUTPUTS These output signals can be controlled via the GPIREG register located in Function 3 Power Management System IO Space at address PMBase 34h If a GPO pin is not multiplexed with another signal or defaults to GPO then its state after reset is the reset condition of the
62. Interface Allows CPU to Communicate Via SMBus Slave Interface Allows External SMBus Master to Control Resume Events Real Time Clock 256 byte Battery Back CMOS SRAM e Includes Date Alarm Two 8 byte Lockout Ranges Microsoft Win95 Compliant 324 mBGA Package Major Chips Description 2 5 82371AB PCI ISA IDE Xcelerator PIIX4 is a multi function PCI device implementing a PCI to ISA bridge function a PCI IDE function a Universal Serial Bus host hub function and an Enhanced Power Management function As a PCI to ISA bridge PIIX4 integrates many common 1 functions found in ISA based PC systems two 82C37 DMA Controllers two 82C59 Interrupt Controllers an 82C54 Timer Counter and a Real Time Clock In addition to compatible transfers each DMA channel supports Type F transfers PIIX4 also contains full support for both PC PCI and Distributed DMA protocols implementing DMA The Interrupt Controller has Edge or Level sensitive programmable inputs and fully supports the use of an external Advanced Programmable Interrupt Controller APIC and Serial Interrupts Chip select decoding is provided for BIOS Real Time Clock Keyboard Controller second external microcontroller as well as two Programmable Chip Selects PIIX4 provides full Plug and Play compatibility PIIX4 can be configured as Subtractive Decode bridge or as a Positive Decode bridge This allows the use of a subtractive decode
63. MHz Remark include North bridge MTXC voltage regulator and thermal sensor 1 30 Service Guide 1 6 9 BIOS Table 1 17 BIOS Specifications C PCI V2 1 APM V1 1 E IDE and PnP ESCD format V1 0a Unlock BIOS feature If user changes the BIOS Setup setting and causes the system cannot boot press Ed before system turns on till POST completed then system will load BIOS Setup the default settings 1 6 10 System Memory Table 1 18 System Memory Specifications tem Specification SIMM data bus width 64 bit SIMM package 144 pin Small Outline Dual In line Memory Module soDIMM Boot block is an area inside of BIOS with the program for system boot Avoid this area to be modified while BIOS flash then system still can boot even the BIOS flash process is not successful System Introduction 1 31 1 6 10 1 51 Memory Combination List Table 1 19 SIMM Memory Combination List 1 6 11 Video Memory Table 1 20 Video Memory Specification o Specification Memory location Inside of graphic controller NMG2160 1 32 Service Guide 1 6 12 Video Display Modes Table 1 21 Video Display Specification 800 600 16 1024x768 64K colors High Color 1 6 12 1 External CRT Resolution Modes Table 1 22 External CRT Resolution Modes Resolution x Color CRT Refresh Rate Simultaneous on on Ext CRT TFT LCD
64. POS High Z CLOCK RUNG This signal is used to communicate to PCI peripherals that the PCI clock will be stopped Peripherals can assert CLKRUN to request that the PCI clock be restarted or to keep it from stopping This function follows the protocol described in the PCI Mobile Design Guide Revision 1 0 During Reset Low After Reset Low During POS High DEVICE SELECT 4 asserts DEVSEL to claim PCI transaction through positive decoding or subtractive decoding if enabled As an output PIIX4 asserts DEVSEL when it samples IDSEL active in configuration cycles to PIIX4 configuration registers PIIX4 also asserts DEVSEL when an internal PIIX4 address is decoded or when PIIX4 subtractively or positively decodes a cycle for the ISA EIO bus or IDE device As an input DEVSEL indicates the response to a PIIX4 initiated transaction and is also sampled when deciding whether to subtractively decode the cycle DEVSEL is tri stated from the leading edge of PCIRST DEVSEL remains tri stated until driven by 4 as a target During Reset High Z After Reset High Z During POS High Z CYCLE FRAME FRAMEZ is driven by the current Initiator to indicate the beginning and duration of an access While FRAMEZ is asserted data transfers continue When FRAME is negated the transaction is in the final data phase FRAMEZ is an input to PIIX4 when it is the Target FRAMEZ is an output when is the initiator FRAME remains tri stated until
65. Set IDE Interface Bus Master capability and synchronous DMA Mode The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks and CD ROMs Each IDE device can have independent timings The IDE interface supports PIO IDE transfers up to 14 Mbytes sec and Bus Master IDE transfers up to 33 Mbytes sec It does not consume any ISA DMA resources The IDE interface integrates 16x32 bit buffers for optimal transfers PIIX4 s IDE system contains two independent IDE signal channels They can be electrically isolated independently allowing for the implementation of a glueless Swap Bay They can be configured to the standard primary and secondary channels four devices or primary drive 0 and primary drive 1 channels two devices This allows flexibility in system design and device power management Compatibility Modules DMA Controller Timer Counters Interrupt Controller The DMA controller incorporates the logic of two 82C37 DMA controllers with seven independently programmable channels Channels 0 3 are hardwired to 8 bit count by byte transfers and channels 5 7 are hardwired to 16 bit count by word transfers Any two of the seven DMA channels can be programmed to support fast Type F transfers The DMA controller also generates the ISA refresh cycles The DMA controller supports two separate methods for handling legacy DMA via the PCI bus The PC PCI protocol allows PCl based peripherals to initia
66. Table 1 8 System Memory Map 0 000 0CDFFF System CardBus 0 00 OCFFFF Mini dock CardBus 0 0000 OFFFFF 64 KB system BIOS System BIOS 010000 07FFFF Extended memory Onboard memory 080000 027FFF SIMM memory 0000 FFFFFF 256 KB system ROM Duplicate of code assignment at OE0000 0FFFFF 1 6 2 Interrupt Channel Map Table 1 9 Interrupt Channel Map Interrupt Number Interrupt Source Device Name System Timer Keyboard Cascade IrDA 2F8h Serial Port 1 3F8h Audio Floppy Disk Controller FDC Parallel Port Real Time Clock RTC USB System CardBus Reserved for PCMCIA card Reserved for PCMCIA card Mini dock CardBus PS 2 Mouse Co processor Hard disk CD ROM 1 6 3 Address Table 1 10 VO Address Address Range Device OOOO O 000 00F DMA controller 1 020 021 Interrupt controller 1 02E 02F NS97338 peripheral controller 040 043 Timer 1 048 04B Timer 2 060 06E Keyboard controller chip select 1 18 Service Guide 1 10 VO Address Address Range 00000 070 071 080 08F DMA page register 0 0 0A1 Interrupt controller 2 0DF DMA controller 2 1F0 1F7 Hard disk select 3F6 3F7 Hard disk select 170 177 CD ROM select 376 377 CD ROM select 220 22F Audio 240 24F Audio default 260 26F Audio 280 28F Audio 278 27F Parallel port 3 2E8 2
67. Table 2 5 87C552 Pin Descriptions 2 Digital Power Supply 5V power supply pin during normal operation idle and power down mode STADC 3 Start ADC Operation Input starting analog to digital conversion ADC operation can also be started by software PWMO 4 O Pulse Width Modulation Output 0 PWM1 5 O Pulse Width Modulation Output 1 EW Enable Watchdog Timer Enable for T3 watchdog timer and disable power down mode 0 0 0 7 57 50 Port 0 0 is an 8 bit open drain bidirectional I O port Port 0 pins that have 1s written to them float and can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program and data memory In this application it uses strong internal pull ups when emitting 1s Port 0 is also used to input the code byte during programming and to output the code byte during verification P1 0 P1 7 16 23 Port 1 8 bit I O port Alternate functions include 16 21 1 0 1 5 Quasi bidirectional port pins 22 23 1 6 1 7 Open drain port pins 16 19 1 CTOL CT3I P1 0 P1 3 Capture timer input signals for timer T2 1 T2 P1 4 T2 event input RT2 P1 5 T2 timer reset signal Rising edge triggered CL P1 6 Serial port clock line 2 C bus SDA 1 7 Serial port data line 2 C bus Port 1 is also used to input 2 the lower order address byte during EPROM programming and verification AO is on
68. Video MeMO EE PERRO ER 1 33 1 6 12 Video Display 1 34 1 6 13 1 35 1 7 1 8 1 9 2 1 2 2 2 3 2 4 16 14 1 35 16 15 gt lt Parallel 1 36 1562165 1 36 VGA Ern t er 1 36 1 6 18 1 37 1 37 1 6 20 7 CD ROM eo 1 38 1 60 21 Diskette 1 38 16 22 1 39 1 6 22 Keyboard 1 39 16 24 1 40 1 6 25 DC DG Converter 1 40 1 6 26 DC AC Inverter 1 41 1 6 275 1 41 System 05181549 n e eras 1 42 1 7 1 System Functional Block 1 42 1 7 2 System Bus Block 1 43 Environmental 1 44 Mechanical 1 45 2 Major Chips Description Major Component 51 5
69. a lower speed operation through clock throttling while the CPU temperature is higher than 80 shut down the system while higher than 95 C The system returned to normal condition while the CPU temperature is lower to 75 System The system can also be put into a low power state However this state can only be performed after the individually power managed components have achieved their low power state The state where the system is put into lower power mode is termed static suspend suspend to memory System thermal alarm System thermal rating is obtained by the a thermal sensor aside charger and signaled by the pin 64 SM5 THERM SYS of Full charge to battery is only available when the system temperature is less than 56 while trickle charge higher than 58 System shutdown will be automatically executed while temperature is higher than 85 C 1 6 7 3 Suspend There are two forms of suspend and resume on the notebook static suspend suspend to memory and zero volt suspend suspend to disk Zero volt suspend is as the name implies an OFF condition The entire computer state is saved to a disk file and the computer is turned off In static suspend all components are placed into an idle state and the clocks are stopped to the entire machine except for the 32 kHz clock for memory refresh In either case all separate components in the system are put into their lowest power state at the start of either suspend proces
70. additional Track 0 signal in PPM Mode PPM Mode when 0 VDDB C 48 97 Power Supply This is the 3 3V 5V supply voltage for the PC87332VJG circuitry VSSB E 40 7 Ground This is the ground for the PC87332VJG circuitry 59 221 Wait This signal is used mode by the parallel port device extend its access cycle It is an active low signal ANDATA FDC Write Data This output is the write precompensated serial data Normal Mode that is written to the selected floppy disk drive Precompensation is software selectable ANDATA FDC Write Data This pin provides an additional Write Data signal in PPM Mode PPM Mode when 0 See PE Write Gate This output signal enables the write circuitry of the Normal Mode selected disk drive WGATE has been designated to prevent glitches during power up and power down This prevents writing to the disk when power is cycled Write Gate This gives an additional Write Gate signal in PPM Mode 0 Write Protect This input indicates that the disk in the selected Normal Mode drive is write protected FDC Write Protect This pin gives an additional Write Gate signal in PPM mode when PNF 0 Write An active low input to signal a write from the microprocessor to the controller ANRITE EPP Write Strobe This signal is used in EPP mode as write strobe is active low CNN NC
71. are already properly configured If resource conflicts arise you can set this parameter to Yes to reset and reallocate PnP resources after which the BIOS automatically resets this parameter to No which is the default setting 3 6 Service Guide 3 4 Power Saving Options Selecting Power Saving Options on the BIOS Utility main screen presents a screen that allows you to adjust several power saving settings 3 4 4 When is Closed The computer s lid switch acts as its power switch opening the display wakes up the computer closing the display puts it to sleep The When Lid is Closed setting determines which suspend mode the computer enters when the display is closed Suspend to Disk or Suspend to Memory The default is Suspend to Disk Suspend to Disk With this setting the computer saves all data to the hard disk when you close the display The computer wakes up when you reopen the display Suspend to Memory With this setting the computer saves all data to memory when you close the display or press the suspend hot key Fn Esc Z The computer wakes up when you reopen the display or press any key computer will not enter suspend mode if you close the display To enter suspend mode disconnect the external monitor open and reclose the display lt Note external monitor is connected to computer the Important Sleep Manager automatically creates a suspend to disk file when it is run If the file becomes in
72. by Maxim s socket power control chip This pin is open drain in the SMB mode of operation In this mode an external pull up is required This pin is used for configuration information during hardware reset Refer to misc Control 3 register bit 2 This pin is connected to the system s 5 volt 127 PWR power supply In systems where 5 volts is not available this pin can be connected to the system s 3 3 volt supply but no 5volt connections to the CL PD8632 will be allowed CORE VDD This pin provides power to the core circuitry of the CL PD6832 This pin must be connected to the 3 3 volt supply CORE GND CL PD6832 ground lines should be 26 connected to system ground RING GND CL PD6832 ground lines should be 14 28 44 57 72 87 101 connected to system ground 115 129 146 163 177 193 Major Chips Description 2 71 2 8 Ambit T62 036 C DC DC Converter This T62 036 C DC DC converter supplies multiple DC 5V 3 3V 12V output to system and also supplies the battery charge current 0 3 5A The total inputs from the notebook would be limited by the total output of 65 watts maximum 2 8 1 Pin Diagram T62 036 C CN1 CN2 VDCF 1 0 vpcr P12VR 1 0 092 VDCF 3 4 GND 3 4 GND GND 5 6 GND P3VR 5 6 DCIN 7 9 9 8 DCIN P3VR 7 9 9 8 DCIN 9 10 DCIN GND 9 10 GND CHARGCL 11 12
73. by the IDE device on the negation edge of PDIOW The IDE device is selected either by the ATA register file chip selects PDCS1 PDCS3 and the PDA 2 0 lines or the IDE DMA slave arbitration signals PDDACK For Ultra DMA 33 mode this signal is used as the STOP signal which is used to terminate an Ultra DMA 33 transaction If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector During Reset High After Reset High During POS High Z PRIMARY IO CHANNEL READY In normal IDE mode this input signal is directly driven by the corresponding IDE device IORDY signal In an Ultra DMA 33 read cycle this signal is used as STROBE with the 4 latching data on rising and falling edges of STROBE In an Ultra DMA 33 write cycle this signal is used as the DMARDY signal which is negated by the drive to pause Ultra DMA 33 transfers If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector This is a Schmitt triggered input Table 2 2 82371 Pin Descriptions 0 SECONDARY DISK ADDRESS 2 0 These signals indicate wh
74. data signal for USB port 0 During Reset High Z After Reset High Z During POS High Z SERIAL BUS PORT 1 This signal pair comprises the differential data signal for USBPI OVER CURRENT DETECT These signals are used to monitor the status of the USB port 1 During Reset High Z After Reset High Z During POS High Z 2 22 Service Guide Table 2 2 82371AB Pin Descriptions ne BATLOW BATTERY LOW Indicates that battery power is low PIIX4 can be programmed GPI9 to prevent a resume operation when the BATLOW signal is asserted If the Battery Low function is not needed this pin can be used as a general purpose input CPU_STP CPU CLOCK STOP Active low control signal to the clock generator used to GPO17 disable the CPU clock outputs If this function is not needed then this signal can be used as a general purpose output For values During Reset After Reset and During POS see the Suspend Resume and Resume Control Signaling section EXTSMI EXTERNAL SYSTEM MANAGEMENT INTERRUPT EXTSMI is a falling edge triggered input to PIIX4 indicating that an external device is requesting the system to enter SMM mode When enabled a falling edge on EXTSMI results in the assertion of the SMI signal to the CPU EXTSMI is an asynchronous input to PIIX4 However when the setup and hold times are met it is only required to be asserted for one PCICLK Once negated EXTSMI must remain negated for leas
75. driven by PIIX4 an Initiator During Reset High Z After Reset High Z During POS High Z INITIALIZATION DEVICE SELECT IDSEL is used as a chip select during PCI configuration read and write cycles PIIX4 samples IDSEL during the address phase of a transaction If IDSEL is sampled active and the bus command is a configuration read or write PIIX4 responds by asserting DEVSEL on the next cycle Major Chips Description 2 9 Table 2 2 82371AB Pin Descriptions _ IRDY INITIATOR READY IRDY indicates PIIX4 s ability as an Initiator to complete the current data phase of the transaction It is used in conjunction with TRDY A data phase is completed on any clock both IRDY and TRDY are sampled asserted During a write IRDY indicates PIIX4 has valid data present on AD 81 0 During a read it indicates 4 is prepared to latch data IRDY is an input to 4 when PIIX4 is the Target and an output when is an Initiator IRDY remains tri stated until driven by PIIX4 as a master During Reset High Z After Reset High Z During POS High Z CALCULATED PARITY SIGNAL PAR is even parity and is calculated on 36 bits AD 31 0 plus C BE 3 0 Even parity means that the number of 1 s within the 36 bits plus PAR are counted and the sum is always even PAR is always PCIRST 4 asserts PCIRST during power up and when a hard reset sequence 15 initiated through the RC register PCIRST is
76. e gt Hd dub ddl ELLO EE PUE UU OQS UBT BOGS ROOT 09075 526232 92 7 OOOO gt Ong lt lt lt 32554223 20045542 lt lt lt 50 2 lt gt lt 2 lt 5 lt lt 02002080295 QU 5 2160 Pin Diagram BGNTF MIESTE 5 PMCLKI STATUSA PNLCKI gt PVCLKI STATUSS PNLCKO RESET XCKEN RIC32K STATUS2 IDSEL VSSP CSYNC HVOD SUSPEND STANDBY STATUSI PAL IRDVE 2 3 3 Pin Descriptions Conventions used in the pin description types Input 2160 2160 Input and Output to from 2160 T S Tri state during un driven state S T S Before becoming tri state the pin will be driven inactive O D Open drain type output Table 2 3 NM2160 Pin Descriptions Number Pinname lO Description 00000000 Multiplexed Address and Data 31 0 These multiplexed and bi directional pins are used to transfer address and data on the PCI bus The bus master will drive the 32 bit physical address during address phase and data during data phase for write cycles 2160 will drive the data bus during data phase for read cycles Multiplex
77. frequency for an external Analog Encoder 2 3 2160 Descriptions Number Pinname vo Description External Clock Enable This pin is used to select between internally synthesized clocks or externally supplied clocks A low level on the pin selects internal mode and a high level selects external mode In the external clock mode the internal clock synthesizers will be disabled completely Both PVCLK and PMCLK pins should be driven with the desired clock rates in external mode This pin should be driven all the time during normal operation PMCLKI Memory Clock This pin is used for feeding external memory clock SRATUS4 or observing internal memory clock When in internal clock PNLCKI the internal memory clock can be brought out using this pin When in external clock mode 1 should be driven from an external memory clock source General purpose Status bit 4 can be read from register CR27 bit 1 GR17 bit O defines the function of this pin GR17 bit 7 enables the Modulated Clock Input function PNLCKI from the Spread Spectrum Clock Generator Video Clock This is used for feeding external video clock or STATUS3 observing internal video clock When in internal clock mode PNLCKO 0 the internal video clock can be brought out using this pin When in external clock 1 PVCLKI should be driven from an external vide
78. general purpose output For values During Reset After Reset and During POS see the Suspend Resume and Resume Control Signaling section POWER BUTTON Input used by power management logic to monitor external RSMRST RESUME RESET This signal resets the internal Suspend Well power plane logic and portions of the RTC well logic SMBALERT SM BUS ALERT Input used by System Management Bus logic to generate an GPH 1 interrupt IRQ or SMI or power management resume event when enabled If this function is not needed this pin can be used as a general purpose input SMBCLK SMBDATA Major Chips Description 2 23 SM BUS CLOCK System Management Bus Clock used to synchronize transfer of data on SMBus During Reset High Z After Reset High Z During POS High Z SM BUS DATA Serial data line used to transfer data on SMBus During Reset High Z After Reset High Z During POS High Z Table 2 2 82371AB Pin Descriptions 0 SUSA SUSPEND PLANE A CONTROL Conirol signal asserted during power management suspend states SUSA is primarily used to control the primary power plane This signal is asserted during POS STR and STD suspend states During Reset Low After Reset High During POS Low SUSB SUSPEND PLANE CONTROL Control signal asserted during power GPO15 management suspend states SUSB is primarily used to control the secondary power plane This signal is asserted during STR and STD suspend states If the po
79. is aimed toward the conservation of power on the device and system level when the devices or system is not in use This implies that if any device is detected as not active for a sustained period of time the device will be brought to some lower power state as Soon as practicable With the exception of thermal management if a device has a demand upon it full performance and bandwidth will be given to that device for as long as the user demands it Power management should not cause the user to sacrifice performance or functionality in order to get longer battery life The longer battery life should be obtained through managing resources not in use Pathological cases of measuring CPU speed or trying to periodically check for reaction time of specific peripherals can detect the presence of power management However in general since the device 1 is trapped and the device managed in SMI the power management of devices should be invisible to the user and the application Thermal management is the only overriding concern to the power management architecture By definition thermal management only comes into play when the resources of the computer are used in such a way as to accumulate heat and operate many devices at maximum bandwidth to create a thermal problem inside the unit This thermal problem indicates a danger of damaging components due to excessively high operating temperatures Hence in order to maintain a safe operating environment ther
80. keyboard power cord Memory amp CPU w o memory w o CPU 48MB P55C 200 CPU 48MB P55C 233 CPU 48MB P55C 266 CPU 64MB P55C 233 CPU 32MB PII 266 CPU 64MB PII 266 CPU 48MB 300 CPU 32MB P55C 200 CPU 32MB P55C 233 CPU 32MB P55C 266 CPU 64MB P55C 200 CPU 64MB P55C 266 CPU 48MB PII 266 CPU 32MB 300 CPU 64MB 300 CPU U7EAZAITOUOGX NXxz cdomsovzzrme rommgogoy oouoosowv ozr omoz W HDD amp FDD amp CD ROM Model Number Definition A 1 0 w o HDD FDD CD ROM 3 3 0GB HDD FDD CD ROM VU LCD size T 12 1 TFT LCD 2 4 TE 2 0GB HDD FDD CD ROM 4 0GB HDD FDD CD ROM 13 3 TFT LCD Service Guide teppeundix 6 Exploded View Diagram This appendix includes exploded view diagrams of the notebook Table B 1 Exploded View Diagram List O O O O System assembly 13 3 inch LCD Module assembly Exploded View Diagram IVU sz Mach IVU owesazvese pz JOUN CMM 3608
81. lo dde 6 ch 55 cis 105 55 Teo E gt 2 sse CONFIDENTIRL 55 H8 1934 CER AL AGASd 0 41 Schematics BIOS POST Checkpoints This appendix lists the POST checkpoints of the notebook BIOS Table E 1 POST Checkpoint List Determines if the current booting procedure is from cold boot press reset button or turn the system from warm boot press Ctrl Alt Del Note At the beginning of POST port 64 bit 2 8042 system flag is read to determine whether this POST is caused by cold or warm boot If it is a cold boot a complete POST is performed If it is a warm boot the chip initialization and memory test is eliminated from the
82. mode this pin is the Cardbus DEVSEL signal A20 PCMCIA socket address 20 output In CSTOP CardBus mode this pin is the Cardbus STOP signal A19 PCMCIA socket address 19 output In 88 CBLOCK CardBus mode this signal is the CardBus LOCK signal used for locked transactions A18 PCMCIA socket address 18 output In 85 RFU CardBus mode this pin is reserved for future use A17 PCMCIA socket address 17 output In CAD16 CardBus mode this pin is the Cardbus address data bit 16 A16 PCMCIA socket address 16 output In CCLK CardBus mode this pin supplies the clock to the inserted card A15 PCMCIA socket address 15 output In CIRDY CardBus mode this pin is the Cardbus IRDY signal 14 PCMCIA socket address 14 output CPERR CardBus mode this pin is the Cardbus PERR signal A13 PCMCIA socket address 13 output In CPAR CardBus mode this pin is the Cardbus PAR signal Major Chips Description 2 65 Table 2 7 CL PD6832 Descriptions 12 2 11 9 CAD 12 9 14 A8 CC BE1 A 7 0 CAD 18 20 26 D 13 3 0 6 4 2 31 30 28 7 5 8 1 0 D 1 0 CAD 29 27 Description PCMCIA socket address 12 output CardBus mode this pin is the Cardbus C BE2 signal PCMCIA socket address 11 9 outputs CardBus mode these pins are the Cardbus address data bits 12 9 and 14 respectively PCMCIA socket address 8 output CardBus mode this pin is the Ca
83. module 1 Remove six screws that secure the CPU heat sink to the chassis Figure 4 13 Removing the CPU Heat Sink 2 Remove one screw and pull up the CPU module CN8 CN12 When inserting a CPU module take note of the female and male connectors on the CPU module These should match the corresponding male and female connectors on the main board Figure 4 14 Removing the CPU Module 4 12 Service Guide 4 7 Removing Display Follow these steps to remove the display module 1 Remove the two screws that secure the display cable to the motherboard Then unplug the display cable CN6 Figure 4 15 Unplugging the Display Cable 2 Remove the four display hinge screws Detach the display from the main unit and set aside Figure 4 16 Removing the Display Hinge Screws and Removing the Display Disassembly and Unit Replacement 4 13 48 Disassembling the Housing This section discusses how to disassemble the housing and during its course includes removing and replacing of certain major components like the hard disk drive memory and the main board 4 8 1 Detaching the Lower Housing from the Inside Assembly To detach the lower housing from the inside assembly turn the unit over and remove seven 7 base screws Then snap out the lower part of the housing Figure 4 17 Removing the Lower Housing 4 14 Service Guide 4 8 2 Upper Housing from the Inside Assembly Foll
84. module internal external use Display Active matrix TFT LCD 13 3 1024x768 64K colors XGA Video system PCI local bus video with 128 bit graphics accelerator Audio system 16 bit stereo audio with built in FM synthesizer Built in microphone and dual angled speakers Higher capacity E IDE hard disk Second optional hard disk drive module 34061 Up to 1024x768 256 color ultra VGA monitor LCD projection panel Communications PC card modem system Operating Windows 95 98 system Keyboard and pointing device 84 85 key with Win95 keys auto tilt feature Touchpad centrally located on palm rest ports One 9 pin RS 232 serial port UART16550 compatible One 25 pin parallel port EPP ECP compliant One 15 pin CRT port One 6 pin PS 2 connector One 240 pin mini dock connector Ports continued One type or two type II PC Card slot s 101 102 key PS 2 compatible keyboard or 17 key numeric keypad External serial or PS 2 mouse or similar pointing device Serial mouse printer or other serial devices Parallel printer or other parallel devices floppy drive module when used externally Up to a 1024x768 ultra VGA monitor 17 key numeric keypad PS 2 keyboard mouse or trackball Mini dock LAN card or other PC cards Service Guide Table 1 6 System Specifications One fast infrared port IrDA compliant External IR adapter One 3 5mm minijack microphone in l
85. normal plastic enclosed cables Therefore to prevent damage make sure that you unlock the connectors before pulling out the cables Do not force cables out of the connectors D The cables used here are special FPC flexible printed circuit CONNECTORS WITH LOCKS Unplugging the Cable To unplug the cable first unlock the connector by pulling up the two clasps on both sides of the connector with a plastic stick Then carefully pull out the cable from the connector Plugging the Cable To plug the cable back first make sure that the connector is unlocked then plug the cable into the connector With a plastic stick press the two clasps on both sides of the connector to secure the cables in place Ss Unplugging Plugging _ the Cable the Cable 1 Unplugging the Cable Plugging the Cable Figure 4 2 Using Plastic Stick on Connector With Locks Disassembly and Unit Replacement 4 3 Connectors mentioned in the following procedures are assumed to be no lock connectors unless specified otherwise 4 1 3 Disassembly Sequence The disassembly procedure described in this manual is divided into eight major sections Section 4 2 Removing the module Section 4 3 gt Replacing the hard disk drive Section 4 4 gt Replacing memory Section 4 5 Removing the keyboard Section 4 6 Replacing the CPU Section 4 7 gt Removing the display Section 4 8 Disassemblin
86. of the transaction IRDY is used in conjunction with TRDY TRDY Target Ready This output indicates the target agent s ability to complete the current data phase of the transaction TRDY is used in conjunction with IRDY STOP Stop This output indicates the current target is requesting the master to stop the current transaction LOCK Lock Transaction This signal is used by a 58 master to perform a locked transaction to a target memory LOCK is used to prevent more than one master from using a particular system resource IDSEL Initialization Device Select This inputis used 15 as a chip select during configuration read and write transactions This is a point to point signal The CL PD6832 must be connected to its own unique IDSEL line from the PCI bus arbiter or one of the high order AD bus pins DEVSEL Device Select when actively driven indicates that CL PD6832 has decoded its own address as the target of the current access As an input indicates whether any device on the bus has been selected PERR Parity Error The CL PD6832 drives this output active low if it detects a data parity error during a write phase 2 62 Service Guide Table 2 7 CL PD6832 Pin Descriptions aee retener 10 Tren SERR System Error This output is pulsed by the CL PD6832 to indicate an address parity error RST INTA 1899 OUT INTB IRQ10 SOUT INTC ISLD Pa
87. power control pin T14 of U21 PX3 CD FDPON of PIIX4 please see CD ROM portion for details Video The video controller has two interfaces for controlling power consumption The sleep mode is controlled by software and is performed by BIOS calls The suspend operation is controlled by a PX3 VDPD signal pin N1 of PIIX4 The video timer is not controlled or retriggered by video activity Instead the timer is retriggered by PS 2 mouse and keyboard activity Serial port The serial port is a UART1 and is contained within the 87368 super chip The UART1 operates off of a 14 MHz clock The serial port also has a transceiver a MAX211 Therefore there are several steps to the power conservation of the serial port as below 1 Disable the UART1 decode in the 87338 chip 2 Tri state the UART1 output pins 3 Assert the Power Down pin pin M4 PX3_SPPD of PIIX4 on the MAX3243 chip through the Ring Indicate signal even while in the power down mode if the Resume On Modem Ring in BIOS Setup is set to enabled The MAX3243 pin25 PX3 SPPD of MAX3243 chip will still pass 4 Disable the 14MHz clock If the floppy and the SIR are also disabled If the 14MHz is disabled through the 87336 power down mode then all serial and floppy functions will fail System Introduction 1 27 Recovery power down is the opposite procedure SIR UART The FIR port is basically UART2 The UART operates off of a 14MHz clock The IR p
88. set in the CL PD6832 is a superset of the CL PD6729 register set The CL PD6729 register set is accessible through either the memory or the 1 space The chip provides fully buffered PC Card interfaces meaning that no external logic is required for buffering signals to from the interface and power consumption can be controlled by limiting signal transitions on the PC Card bus 2 7 1 Features Single chip CardBus host adapter Direct connection to PCI bus and two Card sockets Compliant with PCI 2 1 Card Standard and JEDIA 4 1 CL PD672X compatible register set EXCA TM compatible Programmable interrupt protocol PCI PC PCI External Hardware or PCI Way interrupt signalling modes Serial interface to power control devices Automatic Low Power Dynamic mode for lowest power consumption Programmable Suspend mode and hardware Suspend capability Seven fully programmable memory or windows per socket Programmable CardBus timing up to 33 MHz ATA disk interface support Mixed voltage operation 3 3 5 0V Supports low voltage PC Card specification Socket to socket transfer bus master capability Programmable per socket activity indication bits Pin compatible with CL PD6730 Major Chips Description 2 59 208 PQFP 2 7 2 lt 17 016 13 a ATB 14
89. signal is asserted After Reset is immediately after negation of PCIRST and the signal may change value anytime thereafter The term High Z means tri stated The term Undefined means the signal could be high low tri stated or in some in between level Some of the power management signals are reset with the RSMRST input signal The functionality of these signals during RSMRST assertion is described in the Suspend Resume and Power Plane Control section The buffer types are shown below BUFFER TYPE DESCRIPTION input only signal O totem pole output bi direction tri state input output pin s t s sustained tri state OD open drain input open drain output is a standard input buffer with open drain output V This is not a standard signal It is a power supply pin 3 3V 2 5V Indicates the buffer is 3 3V or 2 5V only depending on the voltage 3 3V or 2 5V connected to pins 3 3V 5V Indicates that the output is 3 3V and input is 3 3V receiver with 5V tolerance 5V Indicates 3 3V receiver with 5V tolerance All 3V output signals can drive 5V TTL inputs Most of the 3V input signals are 5V tolerant The 3V input signals which are powered via the RTC or Suspend power planes should not exceed their power supply voltage see Power Planes chapter for additional information The open drain OD CPU interface signals should be pulled up to the CPU interface signal voltage 2 8 Service Guide 2 2
90. software events STPCLK connects directly to the CPU and is synchronous to PCICLK During Reset High Z After Reset High Z During POS High Z Service Guide Table 2 2 82371AB Pin Descriptions PCICLK FREE RUNNING PCI CLOCK A clock signal running at 30 or 33 MHz PCICLK provides timing for all transactions on the PCI Bus All other PCI signals are sampled on the rising edge of PCICLK and all timing parameters are defined with respect to this edge Because many of the circuits in PIIX4 run off the PCI clock this signal MUST be kept active even if the PCI bus clock is not active OSC 14 31818 MHZ CLOCK Clock signal used by the internal 8254 timer This clock signal may be stopped during suspend modes CRYSTAL INPUTS These connected directly to 32 768 crystal RTCX2 External capacitors are required These clock inputs are required even if the internal RTC is not being used SUSCLK SUSPEND CLOCK 32 768 kHz output clock provided to the Host to PCI bridge used for maintenance of DRAM refresh This signal is stopped during Suspend SYSCLK to Disk and Soft Off modes For values During Reset After Reset and During POS see the Suspend Resume and Resume Control Signaling section ISA SYSTEM CLOCK SYSCLK is the reference clock for the ISA bus It drives the ISA bus directly The SYSCLK is generated by dividing PCICLK by 4 The SYSCLK frequencies supported are 7 5 MHz and 8 33 M
91. suspend states such as Power On Suspend Suspend to DRAM and Suspend to Disk A hardware based thermal management circuit permits software independent entrance to low power states PIIX4 has dedicated pins to monitor various external events e g interfaces to a notebook lid suspend resume button battery low indicators etc PIIX4 contains full support for the Advanced Configuration and Power Interface ACPI Specification System Management Bus SMBus PIIX4 contains an SMBus Host interface that allows the CPU to communicate with SMBus slaves and an SMBus Slave interface that allows external masters to activate power management events Configurability PIIX4 provides a wide range of system configuration options This includes full 16 bit decode internal modules dynamic disable on all the internal modules various peripheral decode options and many options on system configuration 2 2 1 Features Supported Kits for Microprocessors 82440BX ISA DP Kit Multifunction PCI to ISA Bridge Supports PCI at 30 MHz and 33 MHz Supports PCI Rev 2 1 Specification Supports Full ISA or Extended EIO Bus Supports Full Positive Decode or Subtractive Decode of PCI Supports ISA and EIO at 1 4 of PCI Frequency Supports both Mobile and Desktop Deep Green Environments 3 3V Operation with 5V Tolerant Buffers Ultra low Power for Mobile Environments Support Power On Suspend Suspend t
92. the pin description IRQ 3 7 9 11 14 15 this can also be programmed to provide the mouse interrupt function When the mouse interrupt function is selected a low to high transition on this signal is latched by PIIX4 and an INTR is generated to the CPU as IRQ12 An internal IRQ12 interrupt continues to be generated until a Reset or an read access to address 60h falling edge of IOR is detected PIRQ A D VOD PROGRAMMABLE INTERRUPT REQUEST The PIRQx signals are active low level sensitive shareable interrupt inputs They be individually steered to ISA interrupts IRQ 3 7 9 12 14 15 The USB controller uses PIRQD as its output signal SERIAL INTERRUPT REQUEST Serial interrupt input decoder typically used in GPI7 conjunction with the Distributed DMA protocol If not using serial interrupts this A20M pin can be used as a general purpose input ADDRESS 20 MASK PIIX4 asserts A20M to the CPU based on combination of Port 92 Register bit 1 FAST A20 and A20GATE input signal During Reset High Z After Reset High Z During POS High Z CPU RESET PIIX4 asserts CPURST to reset the CPU PIIX4 asserts CPURST during power up and when a hard reset sequence is initiated through the RC register CPURST is driven inactive a minimum of 2 ms after PWROK is driven active CPURST is driven active for a minimum of 2 ms when initiated through the RC register The inactive edge of CPURST is driven synchrono
93. 0 It is drive select 1 when bit 4 of FCR is O It is drive select 0 when bit 4 of FCR is 1 This signal is active low FDC Drive 2 or 3 DR23 is asserted when either Drive 2 or Drive 3 is assessed except during logical drive exchange DRATEO FDC Data Rate 0 1 These outputs reflect the currently selected FDC DRATE1 data rate bits 0 and 1 in the Configuration Control Register CCR or Normal Mode the Data Rate Select Register DSR whichever was written to E The pins are totem Toe buffered ae 6 mA sink 6 mA source DMA Bes 0 1 2 active high output that signals the DMA controller that a data transfer is required This DMA request can be sourced by one of the following FDC or Parallel Port When it is not sourced by and of them it is in TRI STATE When the sourced device is disabled or when the sourced device is configured with no DMA it is also in TRI STATE Upon reset is used by the FDC DRQO 1 3 in TRI STATE is multiplexed with IRQ15 and SIRQI1 FDD Drive2 This input indicates whether a second disk drive has been installed The state of this pin is available from Status Register A in PS 2 mode See PNF for further information DSKCHG Disk Change The input indicates if the drive door has been opened Normal Mode The state of this pin is available from the Digital Input Register This pin can also be configured as the RGATE data separator diagnostic input via the Mode command
94. 05 5 1 GENCFG Not available as GPO if using for power Bit 21 management 21 505 2 505 2 GENCFG Not available as if using for power Bit 22 management GPO22 XDIR XDIR GENCFG Not available as GPO if using X bus transceiver Bit 28 23 Not available as if using X bus transceiver Bit 28 GPO24 RTCCS RTCCS GENCFG Not available as GPO if using external RTC that Bit 29 doesn t do self decode GPO25 RTCALE RTCALE GENCFG Not available as GPO if using external RTC that Bit 30 doesn t do self decode GPO26 5 5 Not available if using external Bit 31 doesn t do self decode GPO 27 28 GPO Non multiplexed GPOs which are always available GPO29 IRQ9OUT GPO XBCS Not available as GPO if using external APIC This Bit 8 signal is used for IRQ9 output in APIC mode where it is level triggered active low Tero Non muttipexed GPO which is always available Signal Multiplexed Name With 9 11 Table 2 2 82371AB Pin Descriptions continued CONFIG1 CONRGURATION SELECT 1 This input signal is used to select the type of microprocessor being used in the system If CONFIG1 0 the system contains a Pentium microprocessor If CONFIG1 1 the system contains a Pentium Il microprocessor It is used to control the polarity of INIT and CPURST signals
95. 1 5 5 TXD O Transmitting data from SMC to 3 CF5 DOCKED m Detect completely docked or not P3 4 SM5 LIDSW 1 5 5 5 lO CPU system over temperature ese 0 e P3 7 SM5 ON RES O ON RESUME switch for Japan version P4 0 5 5 FANON NGC 0 0 000 O P4 2 SM5_FLOATREQ Docking float request P4 3 SM5_UNDOCK_GNT O Undock grant P4 4 SM5 ICONT Charge current control P4 5 5 5 FLAOTGNT4 1 Docking float grant P4 6 5 PWRRDYB Power ready delay about 4ms after power good P5 0 CHARGSP Charging set point P5 1 SM5 MAIN 1 Main battery detection P5 2 5 5 ACPWRGD source power good P5 3 5 5 NBPWRGD processor module power good P5 4 5 5 ATFINT CPU thermal interrupt panic 5 5 SM5 SYS System thermal input analog P5 6 5 5 AUX _ Aux AC adapter in P5 7 5 5 MAIN Main AC adapter in SMS CON 5 5 LCD brightness 1 6 6 PCI Devices Assignment Table 1 14 PCI Devices Assignment System Introduction 1 23 7 PMIXCNenhBrdge 000 MM 1131 1 6 7 Power Management in this design
96. 12 33 gt gt 5 lt amp 9 5 3 x 5 5 9x 9 mt 55 1 75 ADFLTR AVDD 2 1 DVSS RSVD 2 73 RSVD RSVD 4 72 RSVD RSVD CD 5 71 RSVD RSVD 6 70 SYEN RSVD 7 69 1 SYCS RSVD 8 68 1 Al RSVD 9 67 7 A13 RSVD 10 66 zc 1 RESET 12 64 1 SYCLK 63 SYLR AOR 14 62 C SYIN DVDD 21 15 L 3 SYCLKO AEN 16 60 21 DVDD All 223 17 39 DI VOLUP Alo Cj 18 58 CZ A9 19 57 L 2 0 20 1 1 IRQs 1 2 1807 ILL 550 1899 LL X531 X240 X241 s 21 lt lt lt lt lt lt 5 gt gt 21282 lt 2 lt 2 lt 22 Ls 100 SQFP View Figure 2 5 Diagram 2 40 Service Guide 244 Pin Descriptions Conventions used the pin description types Input Pin with Pull up Resistor T TTL tri state output pin Schmitt TTL Schmitt input pin Output Pin with Pull up Resistor Table 2 4 Pin Descriptions Number vo Je makes e i 0 1 2 r 0 Re 21
97. 2 3 Block Diagram AD S1 0 FRAMES TRDY IRDY STOP DEVSEL SERR PAR IDSEL PHOLD PHLKA CLKRUN RACINE PWROK CPURST RSTDRV INIT PCIRSTS IRQO GPO14 5 IRQ8S GPIG IRQ12 M INTR NMI IRQr15 14 11 9 7 3 1 SERIRQ GPI7 PRIQ A C IROSOUT4 GPO29 _ STPCLK i SLP SUSCLK BATLOWHGPI9 THRM GPI8 2 RSMRST PWRBTN SUSAS SUSBH GPO15 SUSCS GPO16 ZZ GPO19 PCIREQ D A Osc DREQI 5 3 0 7 5 8 08 REFRESH REQIA C GPI 2 4 GNT A CH GPO S 1 1 CLK48 USBPOx USBP1x OC 1 0 CONFIG 2 1 TEST Figure 2 2 Major Chips Description PCI Bus Interface Interrupt Universal Serial PIIX4 Simplified Block Diagram ISA Bus Interface Piimary IDE Interface Secondary IDE Interface General Purpose Inputs and Outputs 50 15 0 1068168 16 MEMW AEN IOCHRDY iOCHK amp GPIO SYSCLK BALE JOR SMEMR SMEMW ZEROWS SAT19 0 LAPS 17VGPO 7 1 SBHE 81 PDCS3 PDAI2 0 PDDH5 0 PDDREQ PDIOIR PDIOWF PIORDY 800814 800831 SDA 2 0 SDD 15 0 SDDACK SDDREQ SDIOR SDIOW SIORDY PCS 1 0 XDIRH GPO22 XOES GPO23 RTCALE GPO25 FERR IGNNE BIOSCS RICCSHGPO24 KBCCS WGPO26 20 A2ZOGATE MCCS APICCSI GP
98. 2 6 2 Block Diagraim erre Er RED EE 2 50 2 6 3 E 2 51 2 6 4 Pin 2 52 CL PD6832 Host 2 59 2 7 1 2 2 22 222 12 2221 122 22222 221 2 1 2122221 120 122 12 22211221001 021 2212122 2 59 2 7 2 Pin 2 60 2 7 3 Piri DescripllOlis 2 60 Ambit T62 036 C DC DC 2 72 2 8 1 PiN eter PIPER 2 72 2 6 2 55 521 1 2 1 1 2 eu HEBR 2 72 Ambit DC AC Inverter cece 2 74 2 9 1 T62 055C S 2 74 2 9 2 2 PPA tata Sees A E 2 75 3 BIOS Setup Utility About 9 3 2 System 3 3 3 2 1 3 3 3 2 2 65 21 3 3 3 2 3 Hard 3 3 3 2 4 Num Lock After 3 3 3 2 5 LCD Expansion 3 3 3 2 6 Internal Speaker neon rr
99. 3 3Volts or 5Volts operation EMI Reduction Spread Spectrum Clocking technology for reduced panel Hardware Cursor and Icon e Relocatable Hardware Cursor and Icon 64X64 Hardware Cursor 64X64 or 128X128 Hardware Icon Green PC Support Display Power management DPMS DAC Power Down modes Suspend Standby Clock management VGA disable support PCI Mobile Computing clockrun support Resolution and Color Support VGA TFT DSTN CRT 285Hz 640X480 256 64k 16M SVGA TFT DSTN CRT 285Hz 800X600 256 64k 16M XGA TFT DSTN CRT 275Hz 1024X768 256 64k Colors Simultaneous CRT Flat Panel operation Simultaneous TV Flat Panel operation Display Enhancements TV Out Support ZV Zoomed Video Port 24 Bit Integrated RAMDAC with Gamma Correction 36 bit panel support Hardware expansion for low resolution display mode compensation to panels Virtual Screen Panning Support Integrated Dual Clock Synthesizer VESA DDC1 and DDC2b Major Chips Description 2 29 2 3 2 2 3 2 30 132 8858 9999 S es BB Toone 2o x gt zziz m 52 gt 2499 55555425455555505 2022808865500 02220 gt 44 44 A dO nd 425 LECT S TO ERO E TET 2230202500000 CO TELL gt e x gt
100. 801 anzz a IRL b ovo 0 22 i 1 5 2 8 if D 30 Service Guide TETEN FTA d 234348 334248 agen T 49170 SSvOIOHYZ 19178 anita 5821 61 31 Schematics ONFIDENTIA OAR bJ PPP 531414 32 18851577661 782 57578 8 quny ANOLSIH BAOU 19 11 3014 02 140151 8152699 1 JS OL 8S 438 WOSS 39NUHO 302254 33 Schematics C3 REQ 1 8 jeC3 LOCKs 26 FRAMES 16
101. A port CN10 FDD CD ROM connector CN3 Mini dock port CN14 CN15 board connector CN4 Parallel port CN13 Hard disk drive connector CN5 Serial Port CN12 Speaker out Line out Jack CN6 PS2 mouse keyboard port CN11 Microphone in Line in Jack CN7 AC adapter plug in port U1 SIR FIR infrared LED Figure 1 9 Mainboard Jumpers and Connectors Top Side System Introduction 1 15 19 18 SW1 CN16 CN17 CN22 20 CN19 DC DC converter connector CN22 Battery connector CN17 Left speaker connector CN16 Right speaker connector CN20 Debug port SW 1 Reset Switch SW2 Jumper Setting Figure 1 10 Mainboard Jumpers and Connectors Bottom Side The following table shows the settings of the mainboard s bottom side jumper pads Table 1 7 Mainboard Jumpers Pads Settings Bottom Side SW2 1 Keyboard type selection OFF Other keyboard ON Japan keyboard SW2 2 Password settings OFF Enable password ON Bypass password 2 3 BIOS type selection OFF Acer BIOS BIOS 1 16 1 5 2 Media Board CN2 Lid switch CN6 Touchpad connector CN1 LCD connector CN4 CN5 Keyboard connector Figure 1 11 Media Board Jumpers and Connectors Top Side ud N8 CN9 CN7 CN8 Mainboard connector CN9 PCMCIA socket connector Figure 1 12 Media Board Jumpers and Connectors Bottom Side System Introduction 1 17 16 System Configurations and Specifications 1 6 1 System Memory
102. B 1 PCMCIA LM75 GPoweNTR PXi 2 GPO12 APICACK 17 PX3_ROM 0 Enable ROMCS GPO13 APICCS His oc ve o O O o Enable wPowrdwmizemhe tmbeMmXCpowerdmm be 0 Power down PD6832 Cardbus controller sekor es 0 1 Tumottspesker __ re Enebe Fash veo conr GPO29 PX3_FPAGE1 F3 Force BIOS to high page 1F segment and 3 E segments PX3_FPAGE2 F4 FPAGE2 FPAGE1 0 F EO 1 F 1 0 F E2 1 reserved v20 0 0 Enable by SMI RTC wake GPO18 PCI STP amp PX3_PCISTP GPO19 ZZ 1222 GPO20 SUS_STAT1 PX3_SUSTAT GPO21 SUS_STAT2 T18 PM3_A_ACT PD 1 2 2 GPO17 CPU_STP PX3_CPUSTP 1 20 Service Guide Table 1 12 GPIO Port Definition Map 77 obean xs wi 0 SM5 9 Detect FODIGD bay tristaled G notinsaled 9 Detect FOD or CD ied 1 00 0 00 o o o
103. BIOS Setup Serial 1 3F8h IRQ4 Serial 2 2F8h IRQ3 or Serial 3 8 IRQ4 or Serial 4 2E8h IRQ3 or Disabled 1 6 17 Touchpad Table 1 28 Touchpad Specifications em External pointing device serial or PS 2 mouse hot plug System Introduction 1 35 1 6 18 58 1 29 SIR FIR Specifications Specification O OO 115 2 Kbit s Max SIR 4 Mbit s FIR Max Transfer distance 100cm Compatible standard IrDA Infrared Data Association Output data signal voltage level Active 0 5 Non active 0 5 Angle of operation 15 Number of IrDA ports 1 16550 UART support Yes Selectable serial port by BIOS Setup 2F 8h IRQ3 or Disabled 1 6 19 LCD Table 1 30 LCD Specifications ______ Specification Vendor amp Model Name LG LP133X1 Supply voltage for LCD display 3 3 typ Supply voltage for LCD backlight Vrms 700 typ 1 36 Service Guide 1 6 20 CD ROM Table 1 31 CD ROM Specifications em e 128 Interface Enhanced IDE ATAPI compatible communicate with system via system E IDE channel 2 Applicable disc format Red Book Yellow Book CD ROM XA CD I Bridge Photo CD Video CD CD I CD I Ready CD G and Multi session Photo CD CD EXTRA Loading mechanism Drawer type manual load release 1 6 21 Diskette Drive Table 1 32 Diskette Drive Specifications em 0 Media r
104. Bus Host Adapter T62 088 C 00 Ambit DC AC Inverter T62 055 C 00 Major Chips Description 2 1 2 2 Intel PIIX4 is a multi function PCI device that integrates many system level functions PCI to ISA EIO Bridge is compatible with the PCI Rev 2 1 specification as well as the IEEE 996 specification for the ISA AT bus On PCI PIIX4 operates as a master for various internal modules such as the USB controller DMA controller IDE bus master controller distributed DMA masters and on behalf of ISA masters PIIX4 operates as a slave for its internal registers or for cycles that are passed to the ISA or EIO buses All internal registers are positively decoded PIIX4 can be configured for a full ISA bus or a subset of the ISA bus called the Extended IO EIO bus The use of the EIO bus allows unused signals to be configured as general purpose inputs and outputs PIIX4 can directly drive up to five ISA slots without external data or address buffering It also provides byte swap logic recovery support wait state generation and SYSCLK generation X Bus chip selects are provided for Keyboard Controller BIOS Real Time Clock a second microcontroller as well as two programmable chip selects PIIX4 can be configured as either a subtractive decode PCI to ISA bridge or as a positive decode bridge This gives a system designer the option of placing another subtractive decode bridge in the system e g an Intel 380FB Dock
105. CI bus master IDE function It is not associated with any AT compatible DMA channel If the IDE signals are configured for PDIOW PIORDY Primary and Secondary this signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector 2 20 Service Guide PRIMARY DISK IO READ In normal IDE this is the command to the IDE device that it may drive data onto the PDD 15 0 lines Data is latched by PIIX4 on the negation edge of PDIOR The IDE device is selected either by the ATA register file chip selects PDCS1 PDCS3 and the PDA 2 0 lines or the IDE DMA slave arbitration signals PDDACK In an Ultra DMA 33 read cycle this signal is used as DMARDY which is negated by the PIIX4 to pause Ultra DMA 33 transfers In an Ultra DMA 33 write cycle this signal is used as the STROBE signal with the drive latching data on rising and falling edges of STROBE If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector During Reset High After Reset High During POS High PRIMARY DISK IO WRITE In normal IDE mode this is the command to the IDE device that it may latch data from the PDD 15 0 lines Data is latched
106. Description 2 67 Table 2 7 CL PD6832 Descriptions Description Pin No Pin No socket socket Card Enable pin is driven low by the CL PD6832 during card access cycles to control byte word card access CE1 enables even numbered address bytes and CE2 enables odd numbered address bytes When configured for 8 bit cards only CE1 is active and 0 is used to indicate access of odd or even numbered bytes In CardBus mode this pin is the CardBus address data bit 10 CE1 Card Enable pin is driven low by the CL CC BEO PD6832 during card access cycles to control byte word card access CE1 enables even numbered address bytes and CE2 enables odd numbered address bytes When configured for 8 bit cards only CE1 is active and 0 is used to indicate access of odd or even numbered bytes In CardBus mode this pin is the CardBus C BEO signal RESET Card Reset This output is low for normal CRST operation and goes high to reset the card To prevent reset glitches to a card this signal is high impedance unless a card is seated in the socket card power is applied and the card s interface signals are enabled In CardBus mode this pin is the RST input to the card which is active low BVD2 SPKR Battery Voltage Detect 2 Speaker LED LED CAUDIO In Memory Card Interface mode this input serves as the BVD2 battery warning status input In Card Interface mode this input can be configured as a card s SP
107. Detective hardware change Parallel port COM1 COM2 FIR 30sec System activities System activities and timer retriggers Parallel serial port pins are in standby mode serial port clock is stopped and parallel port and UART1 decode in the 87338 chip is disabled Timer retriggers Parallel port COM1 COM2 FIR activities Detective hardware 1 The 25 of U4 MAX3243 is from to change Timer value First phase heuristic time out table for entering HDD standby mode 10sec 20sec 30sec 40sec 50sec 60sec 70sec 80sec 90sec 2min 3min 4min 5min 30min if AC plugged in Second phase fixed timer for entering HDD suspend mode 10sec System activities System activities and timer retriggers First phase time out heuristic results in hard disk spin down and IDE interface disable The second time out 10sec results in hard disk power off and IDE controller clock is stopped and its internal HDD buffer disabled Timer retriggers The access to 1F0 7 will retrigger the timer Detective hardware 1 020 pin Y15 PX3_HDPON is from to L HDD is powered off change Timer value The system with internal floppy 30sec The system with internal CD ROM 1min 2min 3min 4min 5min 6min 7min 8min 9min 10min 15min 30min AC This parameter is for both internal CD ROM and external floppy System Introduction 1 25 Table 1 15 PMU
108. EF COM 4 2F8 2FF COM 2 IrDA 300 301 MPU 401 port default 310 311 MPU 401 port 320 321 MPU 401 port 330 321 MPU 401 port 378 37F Parallel port 2 388 38B FM synthesizer 3BC 3BE Parallel port 1 3B4 3B5 Video subsystem 3 0 3C5 3C6 3C9 Video DAC 3C0 3CF Enhanced graphics display 3D0 3DF Color graphics adapter 3E8 3EF COM3 3F7 Floppy disk controller 3F8 3FF COM 1 Serial 1 CF8 CFF PCI configuration register 1 6 4 DMA Channel Map Table 1 11 DMA Channel Map Funcion 0087 Audio default IrDA option 0083 Audio default ECP option IrDA option 0081 Diskette 0082 Audio option FIR IrDA option ECP option Cascade Cascade 008B 0089 Spare 008A 1 0 1 1 1 2 1 3 2 4 2 5 2 6 2 7 System Introduction 1 19 1 6 5 GPIO Port Definition Table 1 12 GPIO Port Definition Map 1 susar o Power down clock generator xa 64 o Enbedokngresm exe oron vs O _ 1 TumonCDFDD power eros xe nonse wia eReserCDitetae 7 xa smese 0 Selestone oftwee SMbuss GPO7 PX3_SMBSEL1 T12 SMBSEL1 SMBSELO 0 DRAM bank 0 SMB 1 DRAM bank 1 SMB 0 MMO LM75 amp clock gen SM
109. GPOREG register If the defaults to another signal then it defaults to that signal s state after reset The GPO pins that default to GPO remain stable after reset The others may toggle due to system boot or power control sequencing after reset prior to their being programmed as GPOs The GPO8 signal is driven low upon removal of power from the PIIX4 core power plane All other GPO signals are invalid buffers powered off GPI SIGNALS Signal Multiplexed Control Register Name With and Bit PCI Function 1 GPIO IOCHK GENCFG Available as GPI only if in EIO bus mode Bit 0 GPI1 GPI Non multiplexed GPI which is always available This signal when used by power management logic is active low GPI 2 4 Not available if used for PC PCI be Bits 8 10 individually enabled so for instance GPI 4 is available if REQ C is not used GPI5 APICREQ a XBCS Not available as GPI if using an external APIC Bit 8 GPI6 IRQ8 GENCFG Not available as GPI if using external RTC or Bit 14 external APIC SERIRQ GENCFG Not available as if using Serial IRQ protocol Bit 16 GPI8 THRM THRM GENCFG Not available as GPI if using thermal monitoring Bit 23 GPI9 BATLOW BATLOW GENCFG Not available as GPI if using battery low feature Bit 24 GPI10 LID GENCFG Not available as GPI if using LID feature Bit 25 GPI11 SMBALERT SMBALERT GENCFG Not available as GPI if using SMBALERT feature Bit 15
110. HK is asserted depending on how the NMI Status and Control Register is programmed The CPU detects an NMI when it detects a rising edge on NMI After the NMI interrupt routine processes the interrupt the NMI status bits in the NMI Status and Control Register are cleared by software The NMI interrupt routine must read this register to determine the source of the interrupt The NMI is reset by setting the corresponding NMI source enable disable bit in the NMI Status and Control Register To enable NMI interrupts the two NMI enable disable bits in the register must be set to 0 and the NMI mask bit in the NMI Enable Disable and Real Time Clock Address Register must be set to 0 Upon PCIRST this signal is driven low During Reset Low After Reset Low During POS Low SLEEP This signal is output to the Pentium processor in order to put it into Sleep state For Pentium processor it is a No Connect During Reset High Z After Reset High Z During POS High Z SYSTEM MANAGEMENT INTERRUPT SMI is an active low synchronous output that is asserted by in response to one of many enabled hardware or software events The CPU recognizes the falling edge of SMI as the highest priority interrupt in the system with the exception of INIT CPURST and FLUSH During Reset High Z After Reset High Z During POS High Z STOP CLOCK 5 is an active low synchronous output that is asserted by PIIX4 in response to one of many hardware or
111. Hz For PCI accesses to the ISA bus SYSCLK may be stretched low to synchronize BALE falling to the rising edge of SYSCLK During Reset Running After Reset Running During POS Low PRIMARY DISK ADDRESS 2 0 These signals indicate which byte in either the ATA command block or control block is being addressed If the IDE signals are configured for Primary and Secondary these signals are connected to the corresponding signals on the Primary IDE connector If the IDE signals are configured for Primary 0 and Primary 1 these signals are used for the Primary 0 connector During Reset High Z After Reset Undefined During POS PDA 2 0 PDCS1 PRIMARY DISK CHIP SELECT FOR 1F0H 1F7H RANGE For ATA command register block If the IDE signals are configured for Primary and Secondary this output signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector During Reset High After Reset High During POS High PRIMARY DISK CHIP SELECT FOR 3F0 3F7 RANGE For ATA control register block If the IDE signals are configured for Primary and Secondary this output signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector During Reset High After Reset High During
112. Jo YS mom _ 8 0 Y esas m Y mosse ess Jo Y moe ess Jo Y m o o Y _ m Jo Y Toara Leors s 1 6 122 Resolution Modes lt lt lt lt lt lt lt Table 1 23 LCD Hesolution Modes Femmes mme lt lt lt lt 11 77 meme 12 O lt lt lt System Introduction 1 33 1 6 13 Audio Table 1 24 Audio Specifications 1 Compatibility Sound Blaster Game Windows Sound System Plug amp Play ISA 1 0a 1 6 14 PCMCIA Table 1 25 PCMCIA Specifications Specification Supported card type Type ll include CardBus Card Number of slots Two Type ll or one 1 MPU 401 is a RolancHMIB standard that most game software use for audio 1 34 Service Guide 1 6 15 Parallel Port Table 1 26 Parallel Port Specifications o em Number of parallel ports ECP EPP support Yes by BIOS Setup ECP DMA channel by BIOS Setup DRQ1 or DRQ3 Connector type 25 pin D type Selectable parallel port by BIOS Setup Parallel 1 378h IRQ7 Parallel 2 3BCh IRQ7 or Parallel 3 278h IRQ5 Disabled 1 6 16 gt Serial Port Table 1 27 Serial Port Specifications em 0 Selectable serial port by
113. KR binary audio input For ATA or non ATA SFF 68 disk drive support this input can also be configured as a drive status LED input In CardBus mode this pin is the AUDIO input from the card 2 68 Service Guide Table 2 7 CL PD6832 Pin Descriptions BVD1 STSCHG RI CSTSCHG VS2 CVS2 VS1 51 Description Pin No Pin No socket socket Battery Voltage Detect 1 Status Change Ring Indicate In Memory Card Interface mode this input serves as the BVD1 battery dead status input Card Interface mode this input is the STSCHG input which indicates to the CL PD6832 that the card s internal status has changed If bit 7 of the Interrupt and General Control register is set to 1 this pin serves as the ring indicate input for wakeup on ring system power management support In CardBus mode this pin is the CardBus Status change used by the card to alert the System to changes in READY WP and BVD 2 1 Voltage Sense 2 This pin is used in conjunction with VS1 to determine the operating voltage of the card This pin is internally pulled high to the voltage of the 5V power pin under the combined control of the external data write bits and the CD pull up control bits This pin connects to PCMCIA socket pin 57 Voltage Sense 1 This pin is used in conjunction with VS2 to determine the operating voltage of the card This pin is internally pulled high to the voltage of t
114. LATCH ENABLE RTCALE is used to latch the appropriate memory address into the RTC A write to port 70h with the appropriate RTC memory address that will be written to or read from causes RTCALE to be asserted RTCALE is asserted on falling IOW and remains asserted for two SYSCLKs If the internal Real Time Clock is used this signal can be programmed as a general purpose output During Reset Low After Reset Low During POS Low GPO RTCALE GPO25 RTCCS REAL TIME CLOCK CHIP SELECT RTCCS Z is asserted during read or write 24 accesses to RTC location 71h RTCCS be tied to a pair of external OR gates to generate the real time clock read and write command signals If the internal Real Time Clock is used this signal can be programmed as a general purpose output During Reset High After Reset High During POS High GPO X BUS TRANSCEIVER DIRECTION XDIR is tied directly to the direction control of a 74245 that buffers the X Bus data XD 7 0 XDIR is asserted driven low for all read cycles regardless if the accesses is to a PIIX4 supported device XDIR is asserted for memory cycles only if BIOS or APIC space has been decoded For PCI master initiated read cycles XDIR is asserted from the falling edge of either OR or MEMR from only if BIOS or APIC space has been decoded depending on the cycle type For ISA master initiated read cycles XDIR is asserted from the falling edge of either or MEMR
115. LATCHES HH TxD AD CMSRO CMSR5 RST CMTO CMT1 19 ALTERNATE FUNCTION OF PORT 0 3 ALTERNATE FUNCTION OF PORT 3 ALTERNATE FUNCTION OF PORT 1 41 ALTERNATE FUNCTION OF PORT 4 ALTERNATE FUNCTION OF PORT 2 5 ALTERNATE FUNCTION OF PORT 5 Figure 2 6 87C552 Block Diagram 2 44 Service Guide 2 5 3 Pin Diagram P4 3 CMSR3 P4 4 CMSR4 P4 5 CMSR5 P4 6 CMTO P4 7 CMT1 RST P1 0 CTOI P1 1 CT1I 1 2 21 1 1 4 2 P1 5 RT2 P1 6 SCL P1 7 SDA P3 0 RxD P3 1 TxD P3 2 INTO Figure 2 7 Major Chips Description 0 ADCO 1 ADC1 2 ADC2 3 ADC3 4 ADC4 5 ADC5 6 ADC6 7 ADC7 7 P4 0 CMSRO 6 EW 5 PWM1 4 PWMO s 3 STADC 2 VDD 61 AVDD Et 67 5 66 5 65 P5 64 P5 63 P5 62 P5 9 P4 2 CMSR2 8 P4 1 CMSR1 8 C552 CO gt P 00 ro O1 1 00 VVVVUZ2xKxK lt lt 0000 02 00 C TO TO 2210505 E N a Sa gt gt gt gt 87C552 Pin Diagram AVSS AVref AVref P0 0 ADO P0 1 AD1 P0 2 AD2 P0 3 AD3 P0 4 AD4 P0 5 AD5 P0 6 AD6 P0 7 AD7 EA VPP ALE PROG PSEN P2 7 A15 P2 6 A14 2 5 13 2 45 2 5 4 Pin Descriptions
116. LER CON BOARD ER CONTROLL ERMENT SYSTEM MANAG CIRCUI DUTP SPEAKER 90 INTERFAC AND IRL NT CONFID OVANCED LABS ACER STEM BOARD 9701 J c a Service Guide 5 748957651 8 Aad azis di m 310004 HEN val XT 5 Dido dl 223010192 33501845 5881 Q32NUAQU 8328 di orz Tesca SWITTE 4 33401n41 Tid al 5771 114 410 s
117. Low 2 12 Service Guide Table 2 2 82371AB Pin Descriptions ee SA 19 0 SYSTEM ADDRESS 19 0 These bi directional address lines define the selection with the granularity of 1 byte within the 1 Megabyte section of memory defined by the LA 23 17 address lines The address lines SA 19 17 that are coincident with LA 19 17 are defined to have the same values as LA 19 17 for all memory cycles For accesses only SA 15 0 are used and SA 19 16 undefined SA 19 0 are outputs when PIIX4 owns the ISA Bus SA 19 0 are inputs when an external ISA Master owns the ISA Bus During Reset High Z After Reset Undefined During POS Last SA SBHE SYSTEM BYTE HIGH ENABLE SBHE indicates when asserted that a byte is being transferred on the upper byte SD 15 8 of the data bus SBHE is negated during refresh cycles SBHE is an output when PIIX4 owns the ISA Bus SBHE SD 15 0 SMEMR is an input when an external ISA master owns the ISA Bus During Reset High Z After Reset Undefined During POS High SYSTEM DATA SD 15 0 provide the 16 bit data path for devices residing on the ISA Bus SD 15 8 correspond to the high order byte and SD 7 0 correspond to the low order byte SD 15 0 are undefined during refresh During Reset High Z After Reset Undefined During POS High Z STANDARD MEMORY READ PIIX4 asserts SMEMR to request an ISA memory slave to drive data onto the data lines If the access is below the 1 M
118. MEMORY WRITE MEMW i is the command to a memory slave that it may latch data from the ISA data bus MEMW is an output when PIIX4 owns the ISA Bus MEMWG is an input when ISA master other than PIIX4 owns the ISA Bus For DMA cycles PIIX4 as a master asserts MEMW During Reset High Z After Reset High During POS High REFRESH REFRESH As an output REFRESH is used by PIIX4 to indicate when a refresh cycle is in progress It should be used to enable the SA 7 0 address to the row address inputs of all banks of dynamic memory on the ISA Bus Thus when is asserted the entire expansion bus dynamic memory is refreshed Memory slaves must not drive any data onto the bus during refresh As an output this signal is driven directly onto the ISA Bus This signal is an output only when PIIX4 DMA refresh controller is a master on the bus responding to an internally generated request for refresh As an input REFRESH is driven by 16 bit ISA Bus masters to initiate refresh cycles During Reset High Z After Reset High During POS High RSTDRV RESET DRIVE 4 asserts RSTDRV to reset devices that reside on the ISA EIO Bus 4 asserts this signal during a hard reset and during power up RSTDRV is asserted during power up and negated after PWROK is driven active is also driven active for a minimum of 1 ms if a hard reset has been programmed in the RC register During Reset High After Reset Low During POS
119. O13 APICACKI GPO12 J APCIREQU GPIS 5 SMBCLK SMBDATA GPI 21 13 1 a GPI 12 2 0 Multiplexed GPO 30 28 27 8 0 GPO 29 268 9 7 1 Multiplexed 2 2 4 Pin Descriptions This section provides a detailed description of each signal The signals are arranged in functional groups according to their associated interface The symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage level When is not present after the signal name the signal is asserted when at the high voltage level The terms assertion and negation are used exclusively This is done to avoid confusion when working with a mixture of active low and active high signal The term assert or assertion indicates that a signal is active independent of whether that level is represented by a high or low voltage The term negate or negation indicates that a signal is inactive Certain signals have different functions depending on the configuration programmed in the PCI configuration space The signal whose function is being described is in bold font Some of the signals are multiplexed with General Purpose Inputs and Outputs The default configuration and control bits for each are described in Table 1 and Table 2 Each output signal description includes the value of the signal During Reset After Reset and During POS During Reset refers to when the PCIRST
120. OS Setup Information 3 1 3 1 Selecting About My Computer presents you with two screens of details about the computer and its peripherals These screens are for information only you cannot change the settings on these screens The following table tells you what each of the items on the About My Computer screens are Table 1 1 Item System Architecture System BIOS System ID Processor Coprocessor Internal Cache L1 External Cache L2 Total Memory Bank A Bank B System Peripherals Graphics Controller Display Output Hard Drive 0 Hard Drive 1 Floppy Drive A Floppy Drive B Expansion Peripherals PCMCIA Slot 0 PCMCIA Slot 1 Parallel Port Serial Port IrDA FIR Onboard USB AC Adapter Main Battery Onboard Audio Base Address MPU Base Address IRQ Setting DMA Channel 3 2 About My Computer Parameters Description System architecture information BIOS version ID information on major components Processor type and speed Coprocessor type Internal cache size and whether it is enabled or not External cache size and whether it is enabled or not Total memory size Bank A memory module size type and speed Bank B memory module size type and speed Graphics controller type and video memory size Display type and resolution IDE 0 drive type and size hard disk IDE 1 drive type CD ROM or other IDE drives Floppy drive A type Floppy drive B type Card presence in slot 0 detect
121. Other hard disk settings are configured automatically for optimum drive performance You can change the Hard Disk 0 entry to User if you want to enter drive settings manually To determine your drive settings check the data found on your hard disk or supplied in the hard disk vendor documentation Auto to allow the BIOS to auto detect the drive settings at D Caution We suggest that you leave this parameter set to each boot up The Hard Disk 1 entry is used when a CD ROM drive module or second IDE drive option is installed in the module bay 3 2 4 Num Lock After Boot When set to Enabled Num Lock After Boot tells the computer to turn on Num Lock automatically on startup activating the keyboard s embedded numeric keypad The default setting is Enabled 3 2 5 LCD Expansion Mode When set to Enabled LCD Expansion Mode allows full screen views in DOS mode The default setting is Disabled BIOS Setup Information 3 3 3 2 6 Internal Speaker This parameter lets you enable or disable the internal speaker The default setting is Enabled CN Tip You can also toggle the speaker on and off by pressing 9 the speaker hot key combination Fn F7 3 2 7 Silent Boot When set to Enabled the computer shows the computer logo onscreen and hides the POST routine messages The default setting is Enabled 3 2 8 Fast Boot When set to Enabled the computer bypasses the memory tests to speed up the boot up process The default setting is Dis
122. P1 0 etc Port 2 8 bit quasi bidirectional 1 port Alternate function High order address byte for external memory A08 A15 Port 2 is also used to input the upper order address during EPROM programming and verification A8 is on P2 0 A9 on P2 1 through A12 on P2 4 Port 3 8 bit quasi bidirectional 1 port Alternate functions include RxD P3 0 Serial input port P2 0 P2 7 39 46 0 1 2 3 P3 0 P3 7 2 46 Service Guide Table 2 5 87 552 Pin Descriptions P4 0 P4 7 Port 4 8 bit quasi bidirectional I O port Alternate functions include 7 12 CMSRO0 CMSR5 P4 0 P4 5 Timer T2 compare and set reset outputs on a match with timer T2 13 14 13 14 1 P4 6 P4 7 Timer T2 compare and toggle outputs on a match with timer T2 P5 0 P5 7 68 62 Ports 8 bit input port 1 ADCO ADC7 P5 0 P5 7 Alternate function Eight input channels to ADC RST 15 Reset Input to reset the 876552 It also provides a reset pulse as output when timer T3 overflows XTAL1 35 Crystal Input 1 Input to the inverting amplifier that forms the oscillator and input to the internal clock generator Receives the external clock signal when an external oscillator is used XTAL2 paced Crystal Input 2 Output of the inverting amplifier that forms the oscillator Left open circuit when an external clock is used 36 37 Digital ground PSEN 22012 Program Store Enable Active low read strobe to external
123. POS High PRIMARY DISK DATA 15 0 These signals are used to transfer data to or from the IDE device If the IDE signals are configured for Primary and Secondary these signals are connected to the corresponding signals on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector During Reset High Z After Reset Undefined During POS PDD PDCS3 PDD 15 0 Major Chips Description 2 19 Table 2 2 82371AB Pin Descriptions PDDACK PRIMARY DMA ACKNOWLEDGE This signal directly drives the IDE device signal It is asserted by PIIX4 to indicate to IDE DMA slave devices that a given data transfer cycle assertion of PDIOR or PDIOW is a DMA data transfer cycle This signal is used in conjunction with the PCI bus master IDE function It is not associated with any AT compatible DMA channel If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector During Reset High After Reset High During POS High PDDREQ PRIMARY DISK DMA REQUEST This input signal is directly driven from the IDE device DMARQ signal It is asserted by the IDE device to request a data transfer PDIOR and used in conjunction with the P
124. POST routine Disables Non Maskable Interrupt NMI Alarm Interrupt Enable AIE Periodical Interrupt Enable PIE and Update ended Interrupt Enable UIE Note These interrupts are disabled in order to avoid any mis action happened during the POST routine DMA 8237 testing amp initialization System timer 8254 testing amp initialization Initializes RTC time base Note The RTC has an embedded oscillator that generates 32 768 KHz frequency To initial RTC time base turn on this oscillator and set a divisor to 32768 so that 1Ch Verifies CMOS shutdown byte battery and check sum Note Several parts of the POST routine require the system to be in protected mode When returning to real mode from protected mode the processor is reset therefore POST is re entered In order to prevent re initialization of the system POST reads the shutdown code stored in location OFh in CMOS RAM Then it jumps around the initialization procedure to the appropriate entry point The CMOS shutdown byte verification assures that CMOS OFh area is fine to execute POST properly Initializes CMOS default setting RTC can count time correctly Tests 128K base memory Note The 128K base memory area is tested for POST execution The remaining memory area is tested later 20h Tests keyboard controller 8041 8042 Determines keyboard type AT XT PS 2 then write default command byte upon KB type Detects whether keyboard
125. Q3 is multiplexed with DRV2 PNF DR23 Parallel Port Select This input is set high by the printer when it is selected This pin has a nominal 25 KQ pull down resistor attached to Parallel Port Select Input When this signal is low it selects the printer This pin is in a tristate condition 10 ns after a 0 is loaded into the corresponding Control Register bit The system should pull this pin high using a 4 7 KQ resistor UARTS Serial Output This output sends composite serial data to the communications link peripheral device modem or data set The SOUT signal is set to a marking state logic 1 after a Master Reset operation Parallel Port Data Strobe This output indicates to the printer that a valid data is available at the printer port This pin is in a tristate condition 10 ns after a 0 is loaded into the corresponding Control s mes bit The system should pull high using a 4 7 STEP Normal Mode STEP PPM Mode TC Terminal Count Control signal from the DMA controller to indicate the termination of a DMA transfer TC is accepted only when FDACK is active TC is active high in PC AT and Model 30 modes and active low in PS 2 mode TRKO FDC Track 0 This input indicates the controller that the head of the Normal Mode selected floppy disk drive is at track zero Major Chips Description 2 57 2 6 NS97338VJG Descriptions Pm Desorption 1 TRKO 91 FDC Track 0 This pin gives an
126. ROM from the IDE controller This buffer must be disabled before the CD ROM is turned off The buffer is re enabled after the CD ROM is turned on and brought out of reset 2 CD ROM power control pin T 14 of U21 PX3_CD FDPON of PIIX4 The power control pin is used to turn the CD ROM unit off or on This pin is shared as a power on off pin for the floppy disk as well If either the internal or external floppy or the CD ROM is active then this control pin must be asserted on 1 26 Service Guide 3 CD ROM Reset pin U13 of U21 PX3_CDRST of PIIX4 The reset pin is used to assert the hard reset needed for the CD ROM during power up The reset pin is asserted before CD ROM power up and is deasserted after CD ROM power up and before the buffer is enabled Floppy The floppy has two components involved in the process The floppy drive and the controller imbedded in the 87338 super chip The enable disabled function is controlled by 87338 chip In power saving mode there are following condition happened to floppy drive 1 External pin tri state Enabled whenever the floppy is turned off This control signal is same to CD ROM buffer enable pin pin M3 of U21 PX3 FDDBEN of PIIX4 please see CD ROM portion for details 2 PLL disabled Disabled whenever the floppy and both serial channels are inactive or disabled 3 FDC power disable Disables the active decode of the floppy unit This control signal is same to CD ROM
127. S setup utility or unlock system resources the password prompt appears and you must type the supervisor or user password to continue Important The system continues to ask for your password until you enter the correct password you forget your password you must reset the configuration values stored which requires opening the system unit Contact your dealer for assistance To remove a password select the password you want to remove and press lt or gt BIOS Setup Information 3 9 3 5 2 Diskette Drive Access Control This parameter allows you to control the read and write functions of the floppy drive The available options are Normal Write Protect and Disabled The default is Normal With this parameter set to Normal the floppy drive functions normally When the parameter is set to Write Protect all write functions to the floppy drive are disabled but you can still read from a disk in the floppy drive When the parameter is set to Disabled the floppy drive is disabled 3 5 3 Hard Disk Drive Access Control This parameter allows you to control the read and write functions of the hard drive The available options are Normal Write Protect and Disabled The default is Normal With this parameter set to Normal the hard drive functions normally When the parameter is set to Write Protect all write functions to the hard drive are disabled When the parameter is set to Disabled the hard drive is disabled 3 5 4 St
128. S97338VJG Descriptions mm uo 68 60 UARTS Ring Indicator When low this indicates that a telephone RI2 signal has been received by the modem The RI signal is a modem status input whose condition is tested by the CPU by reading bit 6 RI of the Modem Status Register MSR for the appropriate serial channel Bit 6 is the complement of the RI signal Bit 2 TERI of the MSR indicates whether the RI input has changed from low to high since the previous reading of the MSR NOTE When the TERI bit of the is set and Modem Status interrupts are enabled an interrupt is generated UARTs Request to Send When low this output indicates to the modem or data set that the UART is ready to exchange data The RTS signal can be set to an active low by programming bit 1 RTS of the Modem Control Register to a high level A Master Reset operation sets this signal to its inactive high state Loop mode operation holds this signal to its inactive state UARTS Serial Input This input receives composite serial data from the communications link peripheral device modem or data set System interrupt 1 2 and 3 This input can be routed to one of the following output pins IRQ3 IRQ7 IRQ9 IRQ12 SIRQ12 and SIRQ13 can be also routed to IRQ15 Software configuration determines to which output pin the input pin is routed to SIRQ1 is multiplexed with IRQ15 SRIQ12 is multiplexed with DRATE1 MSEN1 CSO and SIR
129. System Security from the BIOS Utility main screen a screen appears that allows you to set security options Important If a password is currently present the system prompts you to input the password before entering the System Security screen 3 51 Supervisor and User Passwords The supervisor and user passwords both prevent unauthorized access to the computer When these passwords are present the computer prompts for the user or supervisor password during system boot up and resume from suspend The supervisor password also gives full access to the BIOS setup utility The user password give limited access setting the user password If you enter the setup utility with the user password you cannot modify the supervisor password or certain BIOS settings Important supervisor password must be set prior to To set a password follow these steps 1 Select the desired password Supervisor or User to set edit and press lt A special password prompt resembling a key appears 2 Enter a password of up to eight characters The characters do not appear the screen as you type them After typing your password press Enter The same password prompt reappears 3 Retype your password and press Enter verify your first entry After you set a password the computer sets the Supervisor Password or User Password parameter to Present The next time you boot up resume from suspend mode run the BIO
130. abled 3 4 Service Guide 3 3 Advanced System Configuration For advanced users the System Configuration menu item contains two hidden pages that allow you to view and configure more technical aspects of the computer Caution computer is already tuned for optimum performance and you should not need access these advanced screens If you do not fully understand the items these special screens do not change their values To access the Advanced System Configuration screens press F8 at the BIOS Utility main screen before selecting the System Configuration menu item When you now select System Configuration and the Basic System Configuration screen appears you will see Page 1 3 in its upper right corner Press PgDn to access page 2 the first Advanced System Configuration screen and PgDn again to access page3 the second Advanced System Configuration screen Each time you press F8 at the main screen you toggle between accessing the single screen Basic System Configuration and three screen Advanced System Configuration Note F8 acts as a toggle on the BIOS Utility main screen 3 3 4 Internal Cache Internal cache refers to cache built into the CPU When enabled this setting boosts system performance It is also called CPU cache or L1 level one cache The default setting is Enabled 3 3 2 External Cache External cache greatly increases system performance by lessening the load on main memory It is a
131. al is an open collector sink signal to drive LED1 The LED current is limited by a series resistor of 1KQ 2 74 Service Guide 2 9 T62 055 C Descriptions BATTLED This signal is an open collector sink signal to drive LED2 The LED current is limited by a series resistor of 1KQ BMCVCC 14 This a 5 volt supply for powering the LEDs It should not be used for any other purpose ADVDD 18 This is a 5 volt power line for the analog circuits and display LEDs on the inverter board AUDGND GND 19 20 This is the return ground for the microphone circuit It should not be connected to VGND or other circuit on the inverter board OUT 21 This is the output of the microphone preamplifier circuit MIC CON Microphone input AUDGND GND 2 9 2 T62 088C This is the return ground for the microphone circuit It should not be connected to VGND or other circuit on the inverter board 2 9 2 1 Pin Diagram 65mm s 80mm jc _ f 00 0 20 03 Qoi 11 Figure 2 13 T62 088 C Pin Diagram 2 9 2 2 Pin Descriptions Table 2 10 T62 088 C Pin Descriptions c o b Oo 7 Major Chips Description 2 75 2 10 T62 088 C Pin Descriptions m LEDs the inverter board our o 2 Microphone preampiiier cirout oup s 2 DE Mo E On Off On 1 8V min O
132. andwidth to perform full screen 30fps video acceleration of MPEG Indeo Cinepak and other video playback CODECs The bandwidth headroom also allows the NM2160 to deliver the highest quality video playback of any notebook graphics solution without compromising simultaneous graphics performance The unique integration of the NM2160 also allows the NM2160 to consume 70 less power than equivalent video solutions with fewer chips and less board space 2 3 1 Features 128 Bit Graphics Acceleration High speed BitBLT Engine e Color Expansion Accelerated Text Hardware Clipping X Y Coordinates Addressing Memory Mapped Bus Mastering Z Buffer data stripping VGA I O relocatable to MMIO Space Video Acceleration e Integrated frame buffer for Video and Graphics 16M Color video in all modes Color space Conversion YUV to RGB e Arbitrary video scaling up to 8X ratio e Bilinear interpolation and Filtering e Video Overlay capability from on off screen memory Color Key Support Independent Brightness Control for Video Window Supports different color depths between video and graphics Supports RGB graphics and video in YUV format in one Integrated frame buffer e Continuous down scaling independent of X amp Y direction Memory Support 2 28 Service Guide High Speed 2Mbytes of integrated DRAM 128 bit Memory Interface Bus Support PCI 2 1 compliance Local Bus Zero wait states
133. art Up Sequences This parameter determines which drive the system boots from when you turn on the system The following table describes the available settings Table 1 2 Start Up Sequences Setting Description A then C System boots from the diskette in floppy drive A If the diskette is missing or a non system default diskette the system boots from hard disk C C then A System boots from hard disk C If the hard disk is a non system disk the system boots from floppy drive A System boots from the diskette in floppy drive A If the diskette is missing or a non system disk ette an error message appears System boots from hard disk C If the hard disk is a non system disk an error message appears CD ROM then System boots from a CD if one is installed in the CD ROM drive If no CD is present the C then A system boots from the hard disk C If the hard disk is a non system disk then the system boots from floppy drive A 3 5 5 Refresh New BIOS LT Warning Contact your dealer to upgrade your BIOS 3 10 Service Guide 3 6 Reset Default Settings When you select the Reset To Default Settings from the BIOS Utility main screen a dialog box appears asking you to confirm that you want to reset all settings to their factory defaults BIOS Setup Information 3 11 Chapter Disassembly and Unit Replacement This chapter contains step by step procedures on how to disassemble the notebook computer for maintenanc
134. byte range 00000000h 000FFFFFh during DMA compatible PIIX4 master or ISA master cycles PIIX4 asserts SMEMR is a delayed version of During Reset High Z After Reset High During POS High ZERO WAIT STATES ISA slave asserts ZEROWS after its address and command signals have been decoded to indicate that the current cycle can be shortened A 16 bit ISA memory cycle can be reduced to two SYSCLKs An 8 bit memory or I O cycle be reduced to three SYSCLKs ZEROWS has no effect during 16 bit I O cycles If IOCHRDY is negated and ZEROWS is asserted during the same clock then ZEROWS is ignored and wait states are added as function of IOCHRDY ZEROWS A20GATE BIOSCS Major Chips Description 2 13 ADDRESS 20 GATE This input from the keyboard controller is logically combined with bit 1 FAST_A20 of the Port 92 Register which is then output via the A20M signal BIOS CHIP SELECT This chip select is driven active during read or write accesses to enabled BIOS memory ranges BIOSCS is driven combinatorially from the ISA addresses SA 16 0 and LA 23 17 except during DMA cycles During DMA cycles BIOSCS is not generated During Reset High After Reset High During POS High SMEMW STANDARD MEMORY WRITE PIIX4 asserts to request an ISA memory slave to accept data from the data lines If the access is below the 1 Mbyte range 00000000h 000FFFFFh during DMA compatible PIIX4
135. c 60Hz 1 CISPR 55022 and CISPR55014 class B 230Vac and 115Vac requirements Scandinavia 2 47 CFR Part15 class B 115Vac with of margin USA 1 40 Service Guide System Block Diagrams 1 7 System Functional Block Diagram 1 7 1 91821 26 c X 005 8 WOY dd 51015 141 VOX L 141 149 Hod peed Z Sd 10 1x3 AOtZ AOOL 1199 A9 E 199 01 5646 8 01 ef ur eur System Functional Block Diagram Figure 1 13 1 41 System Introduction System Bus Block Diagram 1 7 2 preogikoy 01 DNDIOOG 09 TCINN TALO CEXMTE WALSAS sng LSOH AINGOW OWN n 1026 79 8 5 9 01 System Bus Block Diagram Figure 1 14 Service Guide 1 42 1 8 Environmental Requirements Table 1 39 Environmental Requirements Non operating C unpacked 10 60 Non operating C storage package 20 60 Operating non condensing 20 80 Non operating non condensing 20 80 unpacked Non operating non condensing storage 20 90
136. cycles this signal is used as the STOP signal which is used to terminate an Ultra DMA 33 transaction If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector During Reset High After Reset High During POS High SIORDY SECONDARY IO CHANNEL READY In normal IDE mode this input signal is directly driven by the corresponding IDE device IORDY signal In an Ultra DMA 33 read cycle this signal is used as STROBE with the PIIX4 latching data on rising and falling edges of STROBE In an Ultra DMA write cycle this signal is used as the DMARDY signal which is negated by the drive to pause Ultra DMA 33 transfers If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector This is a Schmitt triggered input Note After reset all undefined signals on the primary channel will default to the same values as the undefined signals on the secondary channel USB power supply lines The corresponding USB port is disabled when its over OC 1 0 current signal is asserted SERIAL BUS PORT 0 This signal pair comprises the differential
137. d Primary Slave these signals are used for the Primary Slave connector Table 2 2 82371AB Pin Descriptions SDIOR SECONDARY DISK IO READ In normal IDE mode this is the command to the IDE device that it may drive data onto the SDD 15 0 lines Data is latched by the PIIX4 on the negation edge of SDIOR The IDE device is selected either by the ATA register file chip selects SDCS1 SDCS3 and the SDA 2 0 lines or the IDE DMA slave arbitration signals SDDACK In an Ultra DMA 33 read cycle this signal is used as DMARDY which is negated by the PIIX4 to pause Ultra DMA 33 transfers In an Ultra DMA 33 write cycle this signal is used as the STROBE signal with the drive latching data on rising and falling edges of STROBE If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector During Reset High After Reset High During POS High SDIOW SECONDARY DISK IO WRITE In normal IDE mode this is the command to the IDE device that it may latch data from the SDD 15 0 lines Data is latched by the IDE device on the negation edge of SDIOW The IDE device is selected either by the ATA register file chip selects SDCS1 SDCS3 and the SDA 2 0 lines or the IDE DMA slave arbitration signals SDDACK In read and write
138. d and a PCI originated cycle is positively decoded within the programmed 1 APIC address space If the external APIC is not used this pin is a general purpose output During Reset High After Reset High During POS High GPO APIC REQUEST This active low input signal is asserted by an external APIC device prior to sending an interrupt over the APIC serial bus When 4 samples this pin active it will flush its F type DMA buffers pointing towards PCI Once the buffers are flushed PIIX4 asserts APICACK which indicates to the external APIC that it can proceed to send the APIC interrupt The APICREQ input must be synchronous to PCICLK If the external APIC is not used this pin is a general purpose input INTERRUPT See CPU Interface Signals APICCS GPO13 APICREQ GPI5 INTR INTERRUPT REQUEST 1 IRQ1 is always edge triggered and can not be modified by software to level sensitive A low to high transition on IRQ1 is latched by 4 IRQ1 must remain asserted until after the interrupt is acknowledged If the input goes inactive before this time a default IRQ7 is reported in response to the interrupt acknowledge cycle IRQ 3 7 9 11 14 15 INTERRUPT REQUESTS 3 7 9 11 14 15 The IRQ signals provide both system board components and ISA Bus I O devices with a mechanism for asynchronously interrupting the CPU These interrupts may be programmed for either an edge sensitive or a high level sensitive assertion mode Edge sensi
139. driven inactive a minimum of 1 ms after PWROK is driven active PCIRST is driven for a minimum of 1 ms when PHOLD mechanism by toggling PHOLD inactive for one PCICLK During Reset High Z After Reset High During POS High PHLDA PCI HOLD ACKNOWLEDGE active low assertion indicates that PIIX4 has been granted use of the PCI Bus Once PHLDA is asserted it cannot be negated unless PHOLD is negated first initiated through the RC register PCIRST is driven asynchronously relative to PCICLK During Reset Low After Reset High During POS High calculated on 36 bits regardless of the valid byte enables PAR is generated for address and data phases and is only guaranteed to be valid one PCI clock after the corresponding address or data phase PAR is driven and tri stated identically to the AD 31 0 lines except that PAR is delayed by exactly one PCI clock PAR is an output during the address phase delayed one clock for all PIIX4 initiated transactions It is also an output during the data phase delayed one clock when is the Initiator of a PCI write transaction and when it is the Target of a read transaction During Reset High Z After Reset High Z During POS High Z PCI RESET PIIX4 asserts PCIRST to reset devices that reside on the PCI bus PCI HOLD An active low assertion indicates that PIIX4 desires use of the PCI Bus Once the PCI arbiter has asserted PHLDA to it may not negate it until PHOLD is negated by
140. e 3 4 3 2 7 Silent BOO 3 4 3 2 8 acbidce d 3 vii 3 3 3 4 3 5 3 6 4 1 4 2 4 3 44 4 5 4 6 4 7 4 8 viii Advanced System 3 5 3 3 1 Internal Sachen oco E E 3 5 3 3 2 External Cache s cedet 3 5 3 3 3 Enhanced IDE 3 5 3 3 4 Onboard Communication 3 6 3 3 5 Onboard USB ese tees DM I 3 6 3 3 6 Reset PnP 3 7 Power Saving en Peer a 3 8 3 4 1 When is Closed sete te ete Ha Meters 3 8 3 4 2 Suspend to Disk on Critical Battery 3 8 3 4 3 Display Always On 3 8 3 4 4 Resume On Modem 05 200020 0 000 3 8 3 4 5 Resume On Schedules ERR n 3 9 System n Ptr 3 10 3 5 1 Supervisor and User 3 10 3 5 2 Diskette Drive Access 222 0000 3 11 3 5 3 Hard Disk Drive Access 3 11 3 5 4 Start Up Sequences ii x ee nr nb 3 11 3 5 5 Refresh New BIOS 3 11 Reset To Default
141. e and troubleshooting To disassemble the computer you need the following tools Wrist grounding strap and conductive mat for preventing electrostatic discharge Flat bladed screwdriver Phillips screwdriver Hexagonal screwdriver Tweezers Plastic stick disassembly process group the screws with the corresponding The screws for the different components vary in size During the components to avoid mismatch when putting back the components 4 1 General Information 4 1 1 Before You Begin Before proceeding with the disassembly procedure make sure that you do the following 1 Turn off the power to the system and all peripherals 2 Unplug the AC adapter and all power and signal cables from the system 3 Remove the battery pack from the notebook by 1 press the battery compartment cover latch and slide it toward the front of the computer and 2 pull out the battery pack Disassembly and Unit Replacement 4 1 Figure 4 1 Removing the Battery Pack Removing all power sources from the system prevents accidental short circuit during the disassembly process 4 2 Service Guide 4 12 Connector Types There are two kinds of connectors on the main board Connectors with no locks Unplug the cable by simply pulling out the cable from the connector Connectors with locks You can use a plastic stick to lock and unlock connectors with locks cables which are more delicate than
142. e may be occasions where we have to sacrifice performance in order to achieve operational safety Heuristic power management is designed to operate and adapt to the user while the user is using it It is the plug and play equivalent for power management There are no entries in BIOS Setup which are required to be set by the user in order to optimize the computers battery life or operation The only BIOS Setup entries are for condition information for suspend resume operations Normal operations and power management are done automatically see chapter 3 for details interface closely the APM function in Win95 or Win3 1 must be enabled and set to advanced level for optimum power management and the driver that installed in system must be Acer authorized and approved gt Since power management is implemented linking with 1 24 Service Guide 1 6 7 1 PMU Timers There are several devices related timers available on the V1 LS chip Each timer may have zero or more devices assigned to the timer for the purpose of retriggering the timer Table 1 15 PMU Timers List Timer value 30sec 1min 1 5min 2min 2 5min 3min 3 5min 4min 4 5min 6min 7min 8min 9min 10min 15min 20min 30min if AC plugged in System activities System activities and timer retriggers The video display CRT and LCD is in power saving mode Timer retriggers KBC PS 2 mouse will retrigger the timer
143. e since the previous reading of the MSR NOTE Whenever the MSR DDCD bit is set an interrupt is generated if Modem Status interrupts are enabled FDC Density Select DENSEL indicates that a high FDC density data rate 500 Kbs 1 Mbs or 2 Mbs or a low density data rate 250 300 Kbs is selected DENSEL is active high for high density 5 25 inch drives when IDENT is high and active low for high density 3 5 inch drives when IDENT is low is also programmable via the Mode command FDC Density Select This pin offers an additional Density Select signal in PPM Mode when 0 FDC Direction This output determines the direction of the floppy disk drive FDD head movement active step in inactive step out during a seek operation During reads or writes DIR is inactive FDC Direction This pin offers an additional Direction signal in PPM Mode when PNF 0 FDC Drive Select 0 1 These are the decoded drive select outputs that are controlled by Digital Output Register bits DO D1 The Drive Select outputs are gated with DOR bits 4 7 These are active low outputs They are encoded with information to control tour FDDs when bit 4 of the Function Enable Register FER is set DRO exchanges logical drive values with DR1 when bit 4 of Function Control Register is set 2 53 2 6 NS97338VJG Descriptions FDC Drive Select 1 This pin offers an additional Drive Select signal in PPM Mode when PNF
144. e type III Card Microphone in Line in External microphone line input device Speaker out Line out Amplified speakers or headphones PC CARD SLOTS The computer contains two PC card slots on the left panel that accommodate two type or one type card s Consult your dealer for available PC card options MULTIMEDIA PORTS The computer provides a Mic In Line in port and a Speaker out Line out port on the left panel to accommodate multimedia audio devices such as a microphone speakers or headphones 1 2 3 Indicator Lights The display panel contains a power indicator light and a battery indicator light as shown in the illustration below Power Indicator Battery Indicator Figure 1 4 Indicator Lights Table 1 3 Indicator Light Descriptions Power Indicator 1 Lights when power is on Flashes when the computer is suspend to memory mode Battery Indicator Lights when the battery pack is charging Flashes when battery power is low System Introduction 1 5 12 4 Hot Keys The computers special Fn key used in combination with other keys provides hot key combinations that access system control functions such as screen contrast brightness volume output and the BIOS setup utility Lz WL We 1 VOC J 100101122101 211011101 12 L JOJO JOO 11001 01101011 2888 VUUS
145. ecognition 2DD 720K 2HD 1 2M 3 mode 2HD 1 44M ewm s 15 t Input Voltage 5 10 System Introduction 1 37 1 6 22 Hard Disk Drive Table 1 33 Hard Disk Drive Specifications Specification Vendor amp Model Name IBM DTCA 23240 IBM DTCA 24090 Disks Rotational speed RPM 4000 4000 Voltage tolerance V 525 __ 1 6 23 Keyboard Table 1 34 Keyboard Specifications ______ ____ Specification Vendor amp Model Name SMK 1902 SMK KAS1902 SMK KAS1902 0251R 0211R English 0232R Germany Japanese Total number of keypads 84 keys 85 keys 88 keys Windows95 keys Yes Logo key Yes Logo key Yes Logo key S key Application key Application key External External PS 2 keyboard hot plug External PS 2 keyboard hot plug hot plug Internal amp external keyboard work simultaneously Keyboard automatic tilt feature The ee has the option of automatically tilting to a six degree angle whenever you open the lid This feature is set by an keyboard automatic tilt latch on the rear side of the system unit 1 38 Service Guide 1 6 24 Battery Table 1 35 Battery Specifications C wm 0 Seona 1 6 25 DC DC Converter DC DC converter generates multiple DC voltage level for whole system unit use and offer charge current to battery Table 1 36 DC DC Converter Specifications ___
146. ection allows you to set addresses and interrupts for the computer s serial and parallel ports Serial Port The Serial Port parameter can be set to Enabled or Disabled The Base Address parameter accepts the following values 3F8h 2F8h 3E8h or 2E8h The IRQ parameter accepts 4 or 3 The default values are Enabled 3F8h and 4 IrDA FIR The IrDA FIR parameter can be set to Enabled or Disabled The Base Address parameter accepts the following values 3F8h 2F8h 3E8h or 2E8h The IRQ parameter accepts 4 or The DMA Channel parameter accepts 3 0 or 1 The default values are Enabled 2F8h 3 and 3 Parallel Port The Parallel Port parameter can be set to Enabled or Disabled The Base Address parameter accepts 378h or 278h The IRQ parameter accepts 7 or 5 The Operation Mode parameter accepts the following values EPP ECP Bi directional or Standard The ECP DMA Channel parameter lets you set the DMA channel used in ECP mode You must choose DMA channel 1 or 3 with this parameter if you select ECP as your parallel port operation mode The default values are Enabled 378h 7 and EPP Caution order to prevent resource conflicts the BIOS Utility does not allow you to set the same IRQ and adaress values for different devices 3 3 5 Onboard USB When enabled you can connect USB devices to the onboard USB port on the rear of the computer The default setting is Enabled 3 3 6 Reset PnP Resources The system resources
147. ed Command and Byte Enable These multiplexed pins C BE2 provide the command during address phase and byte enable s C BE1 during data phase to the NM2160 NM2160 drives this pin in the C BEO Bus Master mode Major Chips Description 2 31 2 3 2160 Descriptions Frame This active low signal is driven by the bus master to indicate the beginning and duration of an access NM2160 drives this pin in the Bus Master mode Parity Even parity across AD31 0 amp C BE3 0 is driven by the bus master during address and write data phases and driven by 2160 during read data phases TRDY Target ready This active low signal indicates NM2160 s ability to complete the current data phase of the transaction During a read cycle indicates that valid data is present on AD 31 00 During a write it indicates NM2160 is prepared to accept data Wait states will be inserted until both TRDY amp IRDY are asserted together Input when NM2160 is in Bus Master STOP Stop This active low signal indicates that NM2160 is requesting the master to terminate at the end of current transaction Input when NM2160 is in Bus Master DEVSEL Device Select This active low signal indicates that NM2160 has decoded its address as the target of the current access Input when NM2160 is in Bus Master Initialization Device Select This input signal is used as chip select during configuration read and write tran
148. ed by the socket service Card presence in slot 1 detected by the socket service Parallel port base address and IRQ Serial port base address and IRQ Infrared port base address and IRQ USB port if enabled or not Connected AC adapter information Installed battery type information Audio base address Audio MPU 401 base address Audio IRQ settings Audio DMA channels Service Guide 3 2 System Configuration Selecting System Configuration presents a Basic System Configuration screen where you can change several items in your computer s configuration Press T or to move from one item to another and or to change settings Press F1 to get help a selected item Press Esc to exit the Basic System Configuration screen and return to the main BIOS Utility screen 3 2 1 Date and Time The current date is in Day of the week Month Day Year format for example Mon Aug 11 1997 The current time is in Hour Minutes Seconds format The system uses a 24 hour clock for example 6 25 50 PM appears as 18 25 50 3 2 2 Floppy Drives The default setting for Floppy Drive A is 1 44 MB 3 5 inch Floppy Drive B is set to None and it is only enabled if you connect an additional external floppy drive 3 2 3 Hard Disks The Hard Disk 0 entry refers to the computer s internal hard disk With this entry set to Auto the BIOS automatically detects the hard disk and displays its capacity cylinders heads and sectors
149. egister pair can be relocated using a power up strapping option and the software configuration after power up When idle advanced power management features allows the PC97338 to enter extremely low power modes under software control The PC97338 operates at a 3 3 5V power supply 2 6 1 Features 10096 compatible with ISA and EISA architectures Floppy Disk Controller Software compatible with the DP8473 the 765A and the N82077 16 byte FlFO disabled by default Burst and Non Burst modes Perpendicular Recording drive support New high performance internal digital data separator no external filler components required Low power CMOS with enhanced power down mode Automatic media sense support with full TDR Tape Drive Register implementation Supports fast 2 Mbps and standard 1 Mbps 500 kbps 250 kbps tape drives 2 48 Service Guide The Bidirectional Parallel Port Enhanced Parallel Port EPP compatible Extended Capabilities Port ECP compatible including level 2 support Bidirectional under either software or hardware control Compatible with ISA and EISA architectures e Ability to multiplex FDC signals on parallel port pins allows use of an external Floppy Disk Drive FDD e Includes protection circuit to prevent damage to the parallel port when a connected printer is powered up or is operated at a higher voltage The UARTs Software compatible with the PC16550A and PC16450
150. ent Driver Ports Control Interrupt Data Handshake Figure 2 8 NS97338VJG Block Diagram 2 50 osc Interrupt and DMA Floppy Drive Interface lt gt Service Guide 2 6 3 Pin Diagram a t 5 5 8 E lt B 55 55 5 lt Las Sey 5 5 SA X o 2 Alo gale Slo ic lala oic lala gt 71 70 69 68 67 66 65 64 63 62 61 60 59 AFD DSTRB DENSEL INIT DIR SUN STEP ASTRB 7 5 1 PD6 DRATEO PDS MSENO PD4 DSKCHG VSSD PD2 WP PDUTRKO STB WRITE 1807 1806 IROS ADRATEO VDDC IRQ4 MR 7 8 9 10 11 12 13 14 15 16 17 C IRSL1 550 Figure 2 9 NS97338VJG Pin Diagram Major Chips Description T gt gt 88224 86 o PC87338VJG 29 28 27 26 19 20 21 22 23 24 25 AEN A9 5 4 DRATEO MSENO DRATETMSENTICSO SIROG DACKS VDDB DRV2 PNF DR23 SIROIS ZRSL2 DENSEL ADRATE 1 INDEX MTRO DRO MTRIADLERSL2 VSSB 2 51 2 6 4 Pin Description Table 2 6 NS97338VJG Pin Descriptions ADRATEO ADRATE1 BADDRO 1 2 52 Addres
151. ervice Guide 2 3 2160 Descriptions Number Pinname vo 136 154 DVSS 1 DRAM ground 173 AVSSM a Analog ground for MCLK synthesizer AVSSV Analog ground for synthesizer 99 AVSSR1 a Analog ground for DAC AVSSR2 Analog ground for DAC current reference AVSSX1 Analog ground for crystal oscillator 25 42 57 HVDD Host bus interface VDD 5v or 3v Includes the PCI VL CRT 78 Power management External clock pins PMCLKI and PVCLKI and Miscellaneous pins 2762407 VDD LogicVDD 3V only 134 156 DVDD DRAM VDD 3V only 175 116 132 1 LVDD NE Panel VDD 5v or 3v 8 MMVDD ZVPorVDD s5V AVDDM Analog VDD for MCLK synthesizer 3V only AVDDV Analog VDD for synthesizer 3V only AVDDR1 VDD for DAC 3V only AVDDR2 Analog for DAC current reference 3V only 94 AVDDX1 Analog VDD for crystal oscillator If external 14 MHz source is used AVDDX1 can be 5 or based on the XTAL1 clock source levels 133 VBB A capacitor across ground to this pin is required Please refer to NM2160 system schematics for more details Major Chips Description 2 37 2 4 1 is a single audio that integrates OPL3 FM and its 1661 Sigma delta CODEC MPU401 MIDI interface and a 3D enhanced controller including all the analog components which is suitable for multi media application This LSI is
152. esents the signal if the serial channel has been designated as COM2 or IRQ4 presents the signal if the serial port is designated as COM1 or COMS The interrupt is reset low inactive after the appropriate interrupt service routine is executed IRQ5 Interrupt 5 Active high output that indicates a parallel port interrupt Legacy Mode When enabled this pin follows the ACK signal input When it is not enabled this signal is tri state This pin is only when ECP is enabled and 5 is configured IRQ6 Interrupt 6 Active high output to signal the completion of the Legacy Mode execution phase for certain FDC commands Also used to signal when a data transfer is ready during a non DMA operation 1807 Interrupt 7 Active high output that indicates a parallel port interrupt Legacy Mode When enabled this signal follows the ACK signal input When it is not enabled this signal is tri state This pin is only when ECP is enabled and IRQ7 is configured IRRX1 65 Infrared Receive 1 and 2 Infrared serial data input signals IRRX1 is IRRX2 66 multiplexed with SIN2 IRRX2 is multiplexed with DSR2 and IRQ12 and IRSLO IRSLO Infrared Control 0 1 These signals control the infrared Analog Front IRSL1 End AFE IRSELO is multiplexed with DSR2 IRQ12 and IRRX2 IRSL2 41 or Infrared Control 2 These signals control the infrared Analog Front 47 End AFE IRSL2 is multiplexed with either DRV2 PNF DR23 and SIRQI13
153. ff 0 8V max This is a 5 volt for powering the LEDs BATTLED Connect to D6 LED 13 14 15 DC 7 19V Microphone circuit input Microphone circuit ground 10 11 ____ 12 13 14 15 2 ___ AUDGND 5 10 11 12 1 3 2 76 Service Guide Chapter 2 BIOS Setup Information The computer BIOS setup utility allows you to configure the computer and its hardware settings The computer comes correctly configured and you do not need to run the BIOS setup utility to use the computer However you might need to use the BIOS utility if you want to customize the way your computer works or if you receive an error message after making hardware or software changes With the BIOS setup utility you can Checkthe system configuration Change the system date time or speed Add or change the location of the external mouse Change the system startup sequence the power saving suspend mode change resume options Set change or remove a system password Press Fn F2 to access the BIOS setup utility You will see the BIOS Utility main screen shown below BIOS Utility About My Computer System Configuration Power Saving Options System Security Reset to Default Settings Move Highlight Bar 4 Select Esc Exit Press T or J to highlight the menu item you want Then press Enter to access the highlighted item Press Esc to exit BI
154. fully compliant with Plug and Play ISA 1 0a and supports all the necessary features i e 16bit address decode more IRQs and DMAs in compliance with PC 96 This LSI also supports the expandability i e Zoomed Video and Modem interface in a Plug and Play manner and power management power down power save partial power down and suspend resume that is indispensable with power conscious application 2 4 1 Features Built in OPL3 FM Synthesizer Supports Sound Blaster Game compatibility Supports Windows Sound System compatibility Supports Plug amp Play ISA 1 0a compatibility Full Duplex operation Built in MPU401 Compatible MIDI port Built in the enhanced controller including all the analog components Supports 16 bit addresss decode Port for external Wavetable synthesizer Hardware and software master volume control Supports monaural input 24mA TL bus drive capability Supports Power Management power down power save partial power down and suspend resume 5V 43 3V power supply for digital 5V power supply for analog 100 pin SQFP package 2 38 Service Guide 2 4 2 Block Diagram BLOCK DIAGRAM Figure 2 4 Block Diagram Major Chips Description 2 39 2 4 3 Pin Diagram PIN LAYOUT 2 2 22 HANNE lt lt 2 gt gt lt lt lt 2
155. g the inside assembly frame Section 4 9 Disassembling the display The following table lists the components that need to be removed during servicing For example if you want to remove the motherboard you must first remove the keyboard then disassemble the inside assembly frame in that order Table 4 1 Guide to Disassembly Sequence Prerequisite 7 Install CPU Remove the keyboard Remove the keyboard Remove two speaker covers on both sides and one center hinge cover Remove or replace the hard disk drive Remove the hard disk drive bay cover Install additional memory Remove the SIMM door Remove the touchpad 1 Remove the keyboard 2 Remove the LCD display module 3 Remove the upper unit of lower case Replace the LCD Remove the LCD display module Remove the motherboard for service 1 Remove the keyboard or replacement 2 Remove the LCD display module 3 Remove the lower unit of lower case 4 4 Service Guide The following diagram details the disassembly flow Figure 4 3 Disassembly Flow Disassembly and Unit Replacement 4 2 Removing the Module If you are going to disassemble the unit it is advisable to remove the module first before proceeding Follow these steps to remove the module 1 Slide out and hold the module release button 2 Press the module release latch and slide out the module Module Release Button Module Release Figure 4 4 Removing the Module 4 6 Service
156. he 4 11 Unplugging the Keyboard Connectors and Removing the Keyboard 4 11 Removing the CPU Heat 5 4 12 Removing the CPU 4 12 Unplugging the Display 4 13 Removing the Display Hinge Screws and Removing the Display 4 13 Removing the Lower 4 14 Removing the Battery Bay 22 4 15 Detaching the Upper Housing from the Inside Frame Assembly 4 15 Removing the Touchpad 4 16 Unplugging the Speaker Connectors and Battery Pack Connector 4 16 Removing the Main 4 17 Removing the Charger Board and Multimedia Board 4 17 Removing the Card 5 0 nennen 4 18 Removing the LCD 4 19 Removing the Display Bezel 000000 4 19 Removing the Display 4 20 Removing the Display Panel Screws and the Display Connectors 4 20 Removing the Display Cable 4 21 Xi List of Tables
157. he 5V power pin under the combined control of the external data write bits and the CD pull up control bits This pin connects to PCMCIA socket pin 43 Connect these pins to the Vcc supply of the 200 180 PW socket pins 17 and 51 of the respective 160 R PCMCIA socket These pins can be 0 3 3 143 or 5 depending on card presence card type and system configuration The socket interface out puts listed in this table Table 2 2 will operate at the voltage applied to these pins independent of the voltage applied to other CL PD6832 pin groups Major Chips Description 2 69 Table 2 7 CL PD6832 Descriptions ER SPKR OUTt Speaker Output This output can be used asa 128 digital output to a speaker to allow system to PU support PCMCIA card fax modem voice and audio sound output This output is enabled by setting the socket s Misc Control 1 register bit 4 to 1 for the socket whose speaker signal is to be directed from BVD2 SPKR LED to this pin This pin is used for configuration information during hardware reset Refer to Misc Control 3 register bit 0 LED OUT LED Output This output can be used as an HW SUSPEND LED driver to indicate disk activity when a t socket s BVD2 SPKR LED pin has been programmed for LED support The Extension Control 1 register bit 2 must be set to 1 to enable this output to reflect any activity on BVD2 SPKR LED and a socket s ATA Control reg
158. ical motor values with MTR1 when bit 4 of FCR is set FDC Motor Select 1 This pin offers an additional Motor Select 1 signal in PPM mode when PNF 0 This pin is the motor enable line for drive 1 when bit 4 of FCR 150 It is the motor enable line for drive 0 when bit 4 of FCR 1 This signal is active low FDC Power Down This pin is PD output when bit 4 of PMC is 1 It is DR1 when bit 4 of PMC is 0 PD is active high whenever the FDC is in power down state either via bit 6 of the DSR or bit of FER or bit 0 of PTR or via the mode command Parallel Port Data These bidirectional pins transfer data to and from the peripheral data bus and the parallel port Data Register These pins have high current drive capability Parallel Port Paper End This input is set high by the printer when it is out of paper This pin has a nominal 25 pull down resistor attached to it Printer Not Floppy PNF is the Printer Not Floppy pin when bit 2 of FCR is 1 It selects the device which is connected to the PPM pins A parallel printer is connected when PNF 1 and a floppy disk drive is connected when PNF 0 This pin is the DRV2 input pin when bit 2 of FCR is 0 Read Active low input to signal a data read by the microprocessor FDD Read Data This input is the raw serial data read from the floppy disk drive FDD Read Data This pin supports an additional Read Data signal in PPM Mode when 0 Service Guide 2 6 N
159. ice computer with IR port desktop with IR adapter IR capable printer System Introduction 1 3 UNIVERSAL SERIAL BUS USB PORT The computer s USB Universal Serial Bus port located on the rear panel allows you to connect peripherals without occupying too many resources Common USB devices include the mouse and keyboard FAST INFRARED FIR PORT The computer s FIR fast infrared port located on the rear panel allows you to transfer data to IR aware machines without cables For example you can transfer data between two IR capable computers or send data to an IR aware printer without using a cable The infrared port is IIDA compliant and can transfer data at speeds of up to 4 megabits per second Mbps at a distance of up to one meter To use the infrared port position two IR aware devices such that their IR ports are no more than one meter apart and offset no more than 15 degrees When the two computers are in position simply begin the data transfer as you normally would See your file transfer software for details 1 2 2 Left Panel Ports The computer s left side panel contains the computer s multimedia ports and PC card slots as shown in the illustration on the next page 1 PC Card Slots 2 Microphone in Line in Port 3 Speaker out Line out Port Figure 1 3 Left Port Location 1 4 Service Guide Table 1 2 Left Port Descriptions Poe Gomedsto 0 PC Card slots Two type PC Cards or on
160. ices that a given data transfer cycle assertion of SDIOR or SDIOW is a DMA data transfer cycle This signal is used in conjunction with the PCI bus master IDE function It is not associated with any AT compatible DMA channel If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector During Reset High After Reset High During POS High SECONDARY DISK DMA REQUEST This input signal is directly driven from the IDE device DMARQ signal It is asserted by the IDE device to request a data transfer and used in conjunction with the PCI bus master IDE function It is not associated with any AT compatible DMA channel If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector SDDACK SDDREQ Major Chips Description 2 21 SDD 15 0 SECONDARY DISK DATA 15 0 These signals are used to transfer data to or from the IDE device If the IDE signals are configured for Primary and Secondary these signals are connected to the corresponding signals on the Secondary IDE connector If the IDE signals are configured for Primary Master an
161. ich byte in either the ATA command block or control block is being addressed If the IDE signals are configured for Primary and Secondary these signals are connected to the SDCS1 SDCS3 corresponding signals on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector During Reset High Z After Reset Undefined During POS SDA SECONDARY CHIP SELECT FOR 170H 177H RANGE For ATA command register block If the IDE signals are configured for Primary and Secondary this output signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector During Reset High After Reset High During POS High SECONDARY CHIP SELECT FOR 370H 377H RANGE For ATA control register block If the IDE signals are configured for Primary and Secondary this output signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector During Reset High After Reset High During POS High Z During Reset High Z After Reset Undefined During POS SDD SECONDARY DMA ACKNOWLEDGE This signal directly drives the IDE device signal It is asserted by PIIX4 to indicate to IDE DMA slave dev
162. ine in Microphone or line in device jack One 3 5mm minijack speaker out line out Speakers or headphones jack One USB port USB device Weight includes battery with FDD 3 5 kg 7 5 1 5 with CD ROM 3 8 kg 7 8 1 5 Dimensions LxWxH Carrying bag Round contour 309 245 56 Main footprint 12 2 x 9 6 x 2 2 Temperature Operating 10 C 35 C 50 F 95 F Non operating 10 C 60 C 14 F 140 F Humidity non condensing Operating 20 80 RH Non operating 20 80 RH AC adapter 100 240Vac 50 60Hz autosensing AC Extra AC adapter adapter Battery pack Extra battery pack Type 57WH Lithium lon battery with intelligent charging and built in battery gauge Charge time 2 0 hour rapid charge 4 0 hour in use charge System Introduction 1 9 14 Board Layout 1 10 Service Guide 1 41 System Board Side 998 110 104 NVAIVL NI 3QVN 8p I r0l 6 2008 waists 1016 832 Figure 1 5 System Board Side System Introduction 1 4 2 System Board Bottom Side fi
163. ions 1 i STPCLK CLK48 48 MHZ CLOCK 48 MHz clock used by the internal USB host controller This signal may be stopped during suspend modes 2 18 INITIALIZATION INIT is asserted in response to any one of the following conditions When the System Reset bit in the Reset Control Register is reset to 0 and the Reset CPU bit toggles from 0 to 1 initiates a soft reset by asserting INIT also asserts INIT if a Shut Down Special cycle is decoded on the PCI Bus if the RCIN signal is asserted or if a write occurs to Port 92h bit 0 When asserted INIT remains asserted for approximately 64 PCI clocks before being negated This signal is active high for Pentium processor and active low for Pentium processor as determined by 1 signal Pentium Processor During Reset Low After Reset Low During POS Low Pentium Processor During Reset High After Reset High During POS High CPU INTERRUPT INTR is driven by to signal the CPU that an interrupt request is pending and needs to be serviced It is asynchronous with respect to SYSCLK or PCICLK and is always an output The interrupt controller must be programmed following PCIRST to ensure that INTR is at a known state During Reset Low After Reset Low During POS Low NON MASKABLE INTERRUPT NMI is used to force a nonmaskable interrupt to the CPU 4 generates an NMI when either SERR or IOC
164. is pin can be configured as control Suspend input or status Suspend output The active high input mode is used for controlling hardware Suspend When asserted NM2160 is forced into suspend mode where all the inputs are disabled and chip goes into the low power mode NM2160 will come out of suspend only by de asserting this pin During output mode this pin will indicate the software suspend status Activity Activity This pin when in input mode and asserted indicates the system activity A high on this pin can be used to reset internal timers This pin when in output mode is a General Purpose Output pin as defined by CR2F bits 5 amp 4 which can be used to control the IMI chip for reduced EMI Real Time Clock 32Khz Status2 This is used to feed 32 kHz Status2 from an external source It is used to generate the refresh timing for the internal display memory during Standby and software Suspend modes 14 MHz can be used to generate the memory refresh timing in above modes General purpose Status bit 3 can be read from register CR27 bit 0 Major Chips Description 2 35 2 3 2160 Descriptions Number Pinname vo Description Chrominance Data 7 0 These the 8 bits of chrominance data that are input to the ZV port of NM2160 Luminance Data 7 0 These are the 8 bits of luminance data that are input to the ZV port of NM2160 Y 0 144 HREF Horizontal Synchronization Pulse This input
165. ister bit 1 must be set to 1 to allow the level of the BVD2 SPKR LED pin to reflect disk activity Serves as HW SUSPENDXE input pin when Misc Control 3 register bit 4 is set to 1 This pin is used for configuration information during hardware reset Refer to Misc Control 3 register bit 1 Serial Clock This input is used as a reference clock 10 100 kHz usually 32 kHz to control the serial interface of the socket power control chips CAUTION This pin must be driven at all times SDATA Serial Data System Management Bus Data SMBDATAt This pin serves as output pin SDATA when used with the serial interface of Texas Instruments TPS2202AIDF socket power control chip and serves as a bidirectional pin SMBDATA when used with Intel s System Management Bus used by Maxim s socket power control chip This pin is open drain for the SMB mode of operation and requires an external pull up This pin is used for configuration information during hardware reset Refer to Misc Control 3 register bit 3 2 70 Service Guide 2 7 CL PD6832 Descriptions pinnamoe Desorption immune Powe SLATCH Serial Latch System Management Bus 130 2or3 SMBLCKt Clock This pin serves as output pin SLATCH PU when used with the serial interface of Texas Instruments TPS2202AIDF socket power control chip and serves as a bidirectional pin SMBCLK when used with Intel s System Management Bus used
166. lso called L2 level 2 cache The default setting is Enabled 3 33 Enhanced IDE Features The Enhanced IDE Features section includes four parameters for optimizing hard disk performance These performance features depend on drive support Newer drives support most or all of these features Hard Disk Size gt 504MB If your hard disk size is greater than 504MB and you use DOS or Windows set this parameter to DOS Windows3 x Win95 If you use NetWare UNIX or Windows NT set this parameter to Others The default setting is DOS Windows3 x Win95 Multiple Sectors Read Write This parameter enhances hard disk performance by reading writing more data at once The available values are Auto or Disabled The default Auto setting allows the system to adjust itself to the optimum read write setting Advanced PIO Mode Advanced PIO Programmed Input Output Mode enhances drive performance by optimizing the hard disk timing The available values are Auto and Mode 0 The default setting is Auto BIOS Setup Information 3 5 Disk 32 Access This parameter allows your hard disk to use 32 bit access The available values are Auto and Disabled The default setting is Auto CN Tip We suggest you set all of these parameters to Auto Y whenever that choice is available This allows the computer to use the hard drive at the highest possible performance level 3 3 4 Onboard Communication Ports The Onboard Communication Ports s
167. master or ISA master cycles asserts SMEMW SMEMWG3 is a delayed version of MEMW During Reset High Z After Reset High During POS High Table 2 2 82371AB Pin Descriptions nm 0 5 KEYBOARD CONTROLLER CHIP SELECT KBCCS is asserted during I O 26 read or write accesses to locations 60h and 64h It is driven combinatorially from the ISA addresses SA 19 0 and LA 23 17 If the keyboard controller does not require a separate chip select this signal can be programmed to a general purpose output During Reset High After Reset High During POS High GPO MCCS MICROCONTROLLER CHIP SELECT MCCS is asserted during I O read write accesses to locations 62h and 66h It is driven combinatorially from the ISA addresses SA 19 0 and LA 23 17 During Reset High After Reset High During POS High 0 PROGRAMMABLE CHIP SELECTS These active low selects asserted PCS1 for ISA I O cycles which are generated by PCI masters and which hit the programmable I O ranges defined in the Power Management section The X Bus buffer signals and XDIR are enabled while the chip select is active i e it is assumed that the peripheral which is selected via this pin resides on the X Bus During Reset High After Reset High During POS High RCIN RESET CPU This signal from the keyboard controller is used to generate an INIT signal to the CPU REAL TIME CLOCK ADDRESS
168. max loading P5VR 17 18 5V output 0 2 5A 19 20 Major Chips Description 2 73 2 9 Ambit DC AC Inverter This notebook uses two kinds of DC AC inverters One T62 088 C is designed for the 13 3 inch TFT LG LP133X1 LCD the other T62 055 C for the 12 1 inch TFT IBM ITSV50D LCD 2 9 1 T62 055C 2 9 1 1 Pin Diagram CN1 T62 055 C Figure 2 12 T62 055 C Pin Diagram 2 9 1 2 Pin Descriptions Table 2 9 T62 055 C Pin Descriptions This is the High voltage side of the Lamp The shorter wire to lamp connects to this output Max lamp start voltage Vrms 1300 Typical lamp run voltage 25 C Vrms 650 Min open circuit voltage Vrms 1100 Max open circuit voltage Vrms 1500 GND GND 1 6 This the return signal for the input power and control signals and is an extension of the system ground CNTADJ lo 29 Contrast adjustment reserved DCIN 3 4 5 This is the input DC voltage to supply the operating power Max value 19VDC Min value 7 VDC BRTADJ 7 This is an analog signal in the range of 0 to volts to control the lamp current Vbrite 1 volt Lamp current 50 10 of Max Vbrite 3volts Lamp current Max 4 5mA PANEL ON A control pin to control on off lamp This input enable the inverter operation Lamp On when high and disables the inverter when low This signal is output from a 3 3V CMOS device Max loading 1000 Logic Low 0 8 volts Max Logic High 21 8 volts Min PWRLED 12 This sign
169. n complies with the Mobile PC PCI Extended Interrupt Specification GNT Grant This signal indicates that access to the 2 4 bus has been granted REQ Request This signal indicates to the arbiter 3 4 that the CL PD6832 requests use of the bus PCI PCI Bus Vcc These pins be connected to 6 21 37 50 PWR either a 3 3 or 5 volt power supply The PCI bus interface pin outputs listed in this table will operate at the voltage applied to these pins independent of the voltage applied to other CL PD6832 pin groups 2 64 Service Guide Table 2 7 CL PD6832 Descriptions Description Pin No Pin No socket socket A B REG Register Access In Memory Card Interface 112 mode this output chooses between attribute and common memory In I O Card Interface mode this signal is active low for non DMA transfers and high for DMA transfers In ATA mode this signal is always high In CardBus mode this pin is the command and byte enables A 25 24 PCMCIA socket address 25 24 outputs 102 99 CAD 19 17 In CardBus mode these pins are the CardBus address data bits 19 and 17 respectively N zu N 23 PCMCIA socket address 23 output CFRAME CardBus mode this pin is the Cardbus FRAME signal A22 PCMCIA socket address 22 output In 94 CTRDY CardBus mode this pin is the Cardbus TRDY signal 21 PCMCIA socket address 21 output 92 CDEVSEL CardBus
170. nal ISA Bus Master owns the ISA Bus and is accessing DRAM or a PIIX4 register As a PIIX4 output IOCHRDY is driven inactive low from the falling edge of the ISA commands After data is available for an ISA master read or 4 latches the data for a write cycle IOCHRDY is asserted for 70 ns After 70 ns PIIX4 floats IOCHRDY The 70 ns includes both the drive time and the time it takes 4 to float IOCHRDY PIIX4 does not drive this signal when ISA Bus master is accessing an ISA Bus slave During Reset High Z After Reset High Z During POS High Z 16 BIT 1 CHIP SELECT This signal is driven by 1 devices on the ISA Bus to indicate support for 16 bit I O bus cycles READ is the command to an ISA I O slave device that the slave may drive data on to the ISA data bus SD 15 0 The 1 slave device must hold the data valid until after IOR is negated IOR is an output when PIIX4 owns the ISA Bus IOR is an input when an external ISA master owns the ISA Bus During Reset High Z After Reset High During POS High CHANNEL READY Resources the ISA Bus negate IOCHRDY to indicate that wait states are required to complete the cycle This signal is normally high IOCHRDY is an input when PIIX4 owns the ISA Bus and the CPU or a PCI agent Table 2 2 82371AB Pin Descriptions nm 0 lOW WRITE IOW is the command to an ISA I O slave device that the slave may latch data f
171. nd function to operate in your system If Sleep Manager is active it will auto adjust the partition file on your notebook for OV Suspend to function properly D You must run the Sleep Manager utility after installing additional If you are using an operating system other than Windows 95 or DOS you may need to re partition your hard disk drive to allow for the additional memory Check with your system administrator 5 When you are done replace and screw back the memory upgrade door Disassembly and Unit Replacement 45 Removing Keyboard Follow these steps to remove the keyboard 1 Slide out the two display hinge covers on both sides of the notebook Figure 4 9 Removing the Display Hinge Covers 2 Pull out first from the edges and remove the center hinge cover Figure 4 10 Removing the Center Hinge Cover 4 10 Service Guide 3 Lifting out keyboard takes three steps a lifting up keyboard b rotating the keyboard to one side and c pulling out the keyboard in the opposite direction Figure 4 11 Lifting Out the Keyboard 4 Flip the keyboard over and unplug the keyboard connectors CN4 CN5 to remove the keyboard At this point you can also remove the touchpad cable from its connector CN6 Figure 4 12 Unplugging the Keyboard Connectors and Removing the Keyboard Disassembly and Unit Replacement 4 11 46 Replacing CPU Follow these steps to remove the CPU
172. ns a Motorola MC146818A compatible real time clock with 256 bytes of battery backed RAM The real time clock performs two key functions keeping track of the time of day and storing system data even when the system is powered down The RTC operates on a 32 768 kHz crystal and a separate 3V lithium battery that provides up to 7 years of protection The RTC also supports two lockable memory ranges By setting bits in the configuration space two 8 byte ranges can be locked to read and write accesses This prevents unauthorized reading of passwords or other system security information The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance rather than just 24 hours in advance GPIO and Chip Selects Various general purpose inputs and outputs are provided for custom system design The number of inputs and outputs varies depending on PIIX4 configuration Two programmable chip selects are provided which allows the designer to place devices on the X Bus without the need for external decode logic Pentium and Pentium Processor Interface The PIIX4 CPU interface allows connection to all Pentium and Pentium processors The Sleep mode for the Pentium processors is also supported Major Chips Description 2 3 Enhanced Power Management PIIX4 s power management functions include enhanced clock control local and global monitoring support for 14 individual devices and various low power
173. o RAM Suspend to Disk and Soft OFF System States All Registers Readable and Restorable for Proper Resume from 0 V Suspend Power Management Logic Global and Local Device Management Suspend and Resume Logic Supports Thermal Alarm Support for External Microcontroller 2 4 Service Guide Full Support for Advanced Configuration and Power Interface Revision 1 0 Specification and OS Directed Power Management Integrated IDE Controller ndependent Timing of up to 4 Drives Mode 4 and Bus Master IDE Transfers up to 14 Mbytes sec Supports Ultra DMA 33 Synchronous Mode Transfers up to 33 Mbytes sec Integrated 16 32 bit Buffer for IDE PCI Burst Transfers Supports Glue less Swap Bay Option with Full Electrical Isolation Enhanced DMA Controller e Two 82C37 DMA Controllers Supports PCI with PC PCI Channels and Distributed Protocols Simultaneously Fast Type F for Reduced PCI Bus Usage Interrupt Controller Based on Two 82C59 15 Interrupt Support e Independently Programmable for Edge Level Sensitivity Supports Optional APIC Serial Interrupt Input Timers Based on 82C54 System Timer Refresh Request Speaker Tone Output USB Two USB 1 0 Ports for Serial Transfers at 12 or 1 5 Mbit sec Supports Legacy Keyboard and Mouse Software with USB based Keyboard and Mouse Supports Design Guide SMBus Host
174. o clock source General purpose Status bit 3 can be read from register CR27 bit 2 GR17 bit 1 defines the function of this pin GR17 bit 7 enables the Reference clock output function IPNCL KO to the Spread Spectrum Clock Generator First Line Marker This signal indicates start of a frame For STN panels this pin is connected to FLM pin For TFT panels this pin is connected to the VSYNC pin Line Pulse This signal indicates start of a line For STN panels this pin is connected to the CP1 pin For TFT panels this pin is connected to the HSYNC pin Shift Clocki This signal is used to drive the panel shift clock or as a General Purpose Output Pin This clock is used for panels which use two clocks one for the upper panel and the other for the lower panel This pin is also configured as a General Purpose Output Pin as defined in register CR2F bits 1 amp 0 to control the IMI chip for reduced EMI Panel horizontal Display Enable MOD This signal indicates the horizontal display time to the panels For some panels it is used to drive the shift clock enable pin This pin can also be configured to drive FPHDE for certain types of TFT panels which require separate horizontal display time indicator Modulation This signal is used to drive the panel MOD or AC input Major Chips Description 2 33 2 3 2160 Descriptions Number Pmmme wo 108 Flat Panel Backlight This is used to control the backlight p
175. or both binary and BCD arithmetic plus bit handling capabilities The instruction set consists of over 100 instructions 49 one byte 45 two byte and 17 three byte With a 16MHz 24MHz crystal 58 of the instructions are executed in 0 75ms 0 5ms and 4096 in 1 5ms 1ms Multiply and divide instructions require 3ms 2ms 2 5 1 Features 30051 central processing unit 9 8kx8 EPROM expandable externally to 64k bytes An additional 16 bit timer counter coupled to four capture registers and three compare registers Two standard 16 bit timer counters 256x8 RAM expandable externally to 64k bytes Capable of producing eight synchronized timed outputs 9 10 0 ADC with eight multiplexed analog inputs Two 8 bit resolution pulse width modulation outputs Five 8 bit I O ports plus one 8 bit input port shared with analog inputs serial I O port with byte oriented master and slave functions Ful duplex UART compatible with the standard 80C51 On chip watchdog timer Speedranges 16MHz Extended temperature ranges OTP package available Major Chips Description 2 43 2 5 2 Block Diagram PWMT 7 SDA T1 TWO 16 BIT PROGRAM SERIAL TIMER EVENT MEMORY PORT COUNTERS Lina 80051 CORE EXCLUDING 8 BIT INTERNAL BUS ell PARALLEL VO SERIAL FOUR PORTS AND UART 16 BIT EXTERNAL BUS PORT CAPTURE
176. ort has a DA converter The 2 disable control circuit is within the 87338 chip 1 Tri state the UART2 output pins 2 Disable the 14MHz clock If the floppy and the serial port are also disabled If the 14MHz is disabled through the National power down mode then all serial and floppy functions will fail Recovery from power down is the opposite procedure Parallel port Since there are no clock operations on the parallel port the requirement to power down this area of the 87338 chip are less critical Also if the floppy is operated through the parallel port the parallel port must be enabled to allow operation to continue 1 Disable the parallel port decode PCMCIA Thermal MD3_ATFINT of US LM75 in media Board Modem Modem power enable This 43 5 5_ of SMC will control the power to all of the modem chips Once powered down the modem chip set has no means of recovery except through full software initialization 1 28 Service Guide The CPU clock The clock to the CPU be physically stopped is static so current state is retained During a clock stop state the CPU is stopped and the internal cache and external bus signals are inoperative Therefore any bus master or DMA activity is halted as well CPU thermal alarm Thermal alarm is signaled by the assertion of the one control pin pin4 of U7 PT3_ATFZNT from MMO module will trigger
177. ow these steps 1 Remove three screws in the battery bay Figure 4 18 Removing the Battery Bay Screws 2 Turn the unit back over and remove two screws close to the back part of the unit Then snap out the upper part of the housing 1 first from the rear of the unit then 2 the front end of the unit Figure 4 19 Detaching the Upper Housing from the Inside Frame Assembly Disassembly and Unit Replacement 4 15 4 8 3 Removing Touchpad Follow these steps to remove the touchpad 1 Unplug the touchpad connector CN5 2 Pullup and remove the touchpad Figure 4 20 Removing the Touchpad 4 8 4 Removing the Main Board Follow these steps to remove the main board from the inside assembly 1 Unplug the speaker connectors CN17 and CN23 and the battery pack connector CN21 Figure 4 21 Unplugging the Speaker Connectors and Battery Pack Connector 4 16 Service Guide 2 Remove four screws to remove the main board from the inside assembly Figure 4 22 Removing the Main Board 3 Remove the charger board CN19 and CN20 and the multimedia board CN10 and CN7 from the main board Figure 4 23 Removing the Charger Board and Multimedia Board Disassembly and Unit Replacement 4 17 4 The card slot module is usually part of the main board spare This removal procedure is for reference only To remove the PC card slot module remove two screws 4 ex
178. ower to the panels or as a General Purpose Output Pin as defined by register CR2F bits 3 amp 2 5 Panel data These pins are used to provide the data interface to PDATA34 different kinds of panels The following table shows the functions of these pins based on the selected panel type PDATA32 PDATA31 PDATA29 PDATA28 PDATA27 PDATA26 PDATA25 PDATA24 PDATA23 PDATA22 21 PDATA20 PDATA19 PDATA18 PDATA17 LCD ID S 0 pins are general purpose read only bits which can be LCD IDO used for panel identification During these LCD ID pins PDATA16 are inputs The state of these bits are reflected in register CR2Eh LCD 101 bits 3 0 The state of these bit can also be sampled anytime on PDATA15 the fly through register GR17 bit 3 Internally these pins are pulled LCD 1 2 up recommended external pull down resistor value is 22k ohm PDATA14 LCD ID3 PDATA13 PDATA12 PDATA11 PDATA10 9 7 5 4 2 VSYNC CRT Vertical Sync This output is the vertical synchronization T S pulse for the CRT monitor HSYNC CRT Horizontal sync This output is the horizontal synchronization T S pulse for the CRT monitor RED This DAC analog output drives the CRT interface Analog 97 G GREEN This DAC analog output drives the CRT interface Analog
179. p this time field can be enabled then set to any value It is possible to set it for a date and time in the past In this case the unit will resume at the next occurrence of the specified time date ignorant If a proper future date is specified then the resume will only happen long enough to evaluate the date and the machine will re suspend After a successful resume has taken place the resume on schedule field will automatically disable Enabling of this field will disable the suspend to disk function except for battery very low The auto disable of resume on schedule still allows the unit to suspend to disk at the next occurrence of a suspend condition with the lid closed 2 Lid switch f the suspend to disk option is used then the lid switch will turn the unit on reboot and then resume to the application at the end of POST If the suspend to memory option is in place or a suspend to disk block is present then the lid switch opening will resume the machine 3 Keystroke Any key use on the internal keyboard will wake up the system from static suspend addition a keystroke from an external keyboard on the primary PS 2 port will also wake the system up Mouse motion from any source will not wake the system up 4 Battery very low The SMC will wake the SMI if the battery reaches a very low condition during static suspend 1 6 8 CPU Module Table 1 16 CPU Module Specifications O Specification CPU Type Pentium II 266
180. pose output During Reset High After Reset High During POS High GPO DACK 0 1 2 3 DMA ACKNOWLEDGE The output lines indicate that a request for service has been granted by or that a 16 bit master has been granted the DACK 5 6 7 bus The active level high or low is programmed via the DMA Command Register These lines should be used to decode the DMA slave device with the IOR IOW line to indicate selection If used to signal acceptance of a bus master request this signal indicates when it is legal to assert MASTER If the DREQ goes inactive prior to DACK being asserted the DACK signal will not be asserted During Reset High After Reset High During POS High DREQ 0 1 2 3 DMA REQUEST The DREQ lines are used to request DMA service from PIIX4 s DREQ 5 6 7 DMA controller or for a 16 bit master to gain control of the ISA expansion bus The active level high or low is programmed via the DMA Command Register All inactive to active edges of DREQ are assumed to be asynchronous The request must remain active until the appropriate DACKx signal is asserted REQ A C PC PCI DMA REQUEST These signals are the DMA requests for PC PCI GPI 2 4 protocol They are used by a PCI agent to request DMA services and follow the PCI Expansion Channel Passing protocol as defined in the section the PC PCI request is not needed these pins can be used as general purpose inputs GNT A C
181. program memory ALE PROG 48 Address Latch Enable Latches the low byte of the address during accesses to external memory It is activated every six oscillator periods During an external data memory access one ALE pulse is skipped ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external pull up This pin is also the program pulse input PROG during EPROM programming 49 External Access When is held at TTL level high the CPU executes out of the internal program ROM provided the program counter is less than 8192 When is held at TTL low level the CPU executes out of external program memory is not allowed to float This pin also receives the 12 75V programming supply voltage during EPROM programming Ss __ analog to Digital Conversion Reference Resistor Lowera Aven Analog Digital Conversion Reference Resistor Hihera faves Analog Power Supply Major Chips Description 2 47 2 6 NS97338VJG Super I O Controller The PC97338VJG is a single chip solution for most commonly used I O peripherals in ISA and EISA based computers It incorporates a Floppy Disk Controller FDC two full featured UARTs and an IEEE 1284 compatible parallel port Standard PC AT address decoding for all the peripherals and a set of configuration registers are also implemented in this highly integrated member of the Super family Ad
182. purium NT3U di Xi ITWI IId 1811 3014 02 4 lt 4 di 5 3t 1 eta 4 241 aT 12808 tid NI20 41 di 1041 221 pt asneaote 2 171 1714 REASd zai 77 WINI 8 VUE ld 1 T 1 T OINA gt NShEd andio andio anda andio angia andio andio andia and a an sc t elt 32 01041 saz areg zez req vee 9723 3723 area F ASEA ase hran 2 1 gt 4 ui Ed 23461142 2 ace ace TNS ort 81 ONS KA 97 UNS eer 888 588 528 BAUE iS BEL Ene 898 8 89 tra 018048141 jog 080 99 PRI rotis cet 298 ion 8 S ae 1d 198 fao 9 339 133 IS31 114 ger aag 988 38 001114 ASKEG psa TIADING SET EN SET 50 98 28 1148 998 ASASd 79 T ret DE EWN eautte 11459 PEDI ERA ega esu 2101 5581 a ru ira 288
183. rdbus C BE1 signal PCMCIA socket address 7 0 outputs In CardBus mode these pins are the Cardbus address data bits 18 and 20 26 respectively PCMCIA socket data I O bit 15 In CardBus mode this pin is the Cardbus address data bit 8 PCMCIA socket data I O bit 14 In CardBus mode this pin is reserved for future use PCMCIA socket data bits 13 3 In CardBus mode this pin is the Cardbus address data bit 6 4 2 31 30 28 7 5 3 1 and 0 respectively PCMCIA socket data 1 bit 1 0 20 3 mode these pins are the Cardbus address data bits 29 and 27 respectively Output Enable This output goes 2 active low to indicate a memory read from the PCMCIA socket to the CL PD6832 In CardBus mode this pin is the Cardbus address data bit 11 Write Enable This output goes active low 2013 to indicate a memory write from CL PD6832 to the PCMCIA socket In CardBus mode this is the CardBus GNT signal Service Guide Table 2 7 CL PD6832 Pin Descriptions Description Pin No Pin No socket socket Read This output goes active low for reads from the socket to the CL PD6832 In CardBus mode this pin is the CardBus address data bit 13 Write This output goes active low for writes from the CL PD6832 to the socket In CardBus mode this pin is the CardBus address data bit 15 WP Write Protect Is 16 Bit Memory
184. rent sensor in the system to indicate the current drawn from the AC adapter or other power 2 72 Service Guide Table 2 8 T62 036 C Descriptions source such as docking station power supply This level is 2 Amps per volt nominal The source impedance is less than 1K O CHARGSP 14 Analog input from the system board to limit the total current consumed by the system from the AC adapter This signal shall be compared by the module with the CHARGFB from the system mother board and the battery charger output current adjusted until CHARGFB does not exceed CHARGSP The system board generates CHARGESP in conjunction with a ID resistor embedded in the LCD cable The scale is 2 amps per volt The source impedance is less than 2 Note The battery charger output may be reduced below the level of CHARGESP by the battery charger current limit signal CHARGECL CHRGOUT 17 18 Battery charger current source output at 3 5A max The output 19 20 current is controlled by two control signals which limit the battery charging current and AC adapter output current The output voltage is limited to 13 2V 13 5V P12VR NN 12 output 0 0 5A 3 4 15 Ground 16 5 6 7 8 3 3V output 0 3A 11 13 5V output 0 0 5A Used for resuming from suspend to memory mode PSVRON o 12 Enables P3VR Logic level Active high luA max loading P5VRON o 14 Enables PSVR Logic level Active high luA
185. rity This pin is sampled the clock cycle after completion of each corresponding address or write data phase For read operations this pin is driven from the cycle after TRDY is asserted until the cycle after completion of each data phase It ensures even parity across AD 31 0 and C BE 3 0 PCI Clock This input provides timing for all transactions on the PCI bus to and from the CL PD6832 All PCI bus interface signals described in this table except RST INTA INTB INTC and INTD are sampled on the rising edge of PCI_CLK and all CL PD6832 PCI bus interface timing parameters are defined with respect to this edge This input can be operated at frequencies from 0 to 33 MHz Device Reset This input is used to initialize all registers and internal logic to their reset states and place most CL PD6832 pins a high impedance state PCI Bus Interrupt A ISA Interrupt Request 9 This output indicates a programmable interrupt request generated from any of a number of card actions Although there is no specific mapping requirement for connecting interrupt lines from the CL PD6832 to the System a common use is to connect this pin to the PCI bus INTA interrupt line and using PCI Interrupt Signaling mode In External Hardware Interrupt Signaling mode this pin indicates interrupt request IRQ9 Ring Indicate Output PCI Bus Interrupt B ISA Interrupt Request 10 In PCI Interrupt Signaling mode this output can be used as an in
186. rmines which side of the FDD is Normal Mode accessed Active selects side 1 inactive selects side O HDSEL FDC Head Select This pin offers an additional Head Select signal in PPM Mode PPM Mode when PNF 0 IDLE FDD IDLE IDLE indicates that the FDC is in the IDLE state and can be powered down Whenever the is in IDLE state or in power down state the pin is active high INDEX 45 1 Index This input signals the beginning of a FDD track INDEX 92 Index This pin gives an additional Index signal in PPM mode when Normal Mode PNF 0 78 Initialize When this signal is low it causes the printer to be initialized This pin is in a tristate condition 10 ns after a 1 is loaded into the corresponding Control Register bit The system should pull this pin high using a 4 7 resistor IORCHDY 51 Channel Ready When IORCHDY is driven low the EPP extends the host cycle IRQ3 4 Interrupt 3 4 5 6 7 9 10 11 12 and 15 This can be totem IRQ5 7 94 pole output or an open drain output The interrupt can be sourced by IRQ9 11 57 one of the following UART1 and or UART2 parallel FDC SIRQI1 IRQ12 15 pin SIRQI2 pin or SIRQIS pin PnP Mode IRQS is multiplexed with IRQ12 is multiplexed with DSR2 and IRRX2 IRQ15 is multiplexed with SIRQI1 IRQ3 4 Interrupt 3 4 These are active high interrupts associated with the Legacy Mode serial ports IRQ3 pr
187. rom the ISA data bus SD 15 0 IOW is an output when owns the ISA IOWs is an input when an external ISA master owns the ISA Bus During Reset High Z After Reset High During POS High LA 23 17 ISA LA 23 17 LA 23 17 address lines allow accesses to physical memory on GPO 7 1 the ISA Bus up to 16 Mbytes LA 23 17 are outputs when PIIX4 owns the ISA Bus The LA 23 17 lines become inputs whenever 15 master owns the 15 Bus If the EIO bus is used these signals become a general purpose output During Reset High Z After Reset Undefined During POS Last LA GPO MEMCS16 MEMORY CHIP SELECT 16 MEMCS16 is a decode of LA 23 17 without any qualification of the command signal lines ISA slaves that are 16 bit memory devices drive this signal low PIIX4 ignores MEMCS16 during I O access cycles and refresh cycles MEMCS16 is an input when PIIX4 owns the ISA Bus PIIX4 drives this signal low during ISA master to PCI memory cycles During Reset High Z After Reset High Z During POS High Z MEMR MEMORY READ is the command to a memory slave that it may drive data onto the ISA data bus MEMR is an output when is a master on the ISA Bus is an input when an ISA master other than PIIX4 owns the ISA Bus This signal is also driven by PIIX4 during refresh cycles For DMA cycles PIIX4 as a master asserts MEMR During Reset High Z After Reset High During POS High MEMW
188. s 1 Devices turned off The HDD except for suspend to disk since the file goes there CD ROM floppy are turned off at the start of any suspend 2 Devices brought to a low power state The audio serial port transceiver MAX213 FIR keyboard controller PCMCIA controller chip will be put into a low power state instantly through a pin asserting or prematurely expiring the device timer 3 Devices zero clocked Since the remainder of the devices video CPU IDE controller ISA bus 87338 s devices serial and floppy are by design static devices their lowest power states are achieved by removing the clock to the device The very act of going into a suspend to memory means that the enable pin to the clock generator chip is deasserted removing all but the 32 kHz signal from the board This excludes however the clocks dedicated to the internal modem They will remained powered and oscillating System Introduction 1 29 For suspend to disk all devices are read saved to local memory and the local memory video memory are saved to a disk file which is created by SLEEP MANAGER utility The machine is then commanded to an off state Resume events for zero volt suspend suspend to disk The only resume event for zero volt suspend is the raising of the lid of the computer This electronically enables the power to the rest of the machine Resume events for static suspend suspend to memory 1 Resume on schedule n BIOS Setu
189. s These address lines from the microprocessor determine which internal register is accessed 0 15 are don t cares during DMA transfer Parallel Port Acknowledge This input is pulsed low by the printer to indicate that it has received the data from the parallel port This pin has nominal 25 KO pull up resistor attached to it FDD Additional Data Rate 0 1 These outputs are similar to DRATEO They are provided in addition to DRATEO 1 They reflect the currently selected FDC data rate bits 0 and 1 in the Configuration Control Register CCR or the Data Rate Select Register DSR whichever was written to last ADRATEO is configured when bit 0 of ASC is 1 ADRATE1 is configured when bit 4 of ASC is 1 See IRQ5 and DENSEL for further information Parallel Port Automatic Feed XT When this signal is low the printer automatically line feed after printing each line This pin is in a tristate condition 10 ns after 0 is loaded into the corresponding Control Register bit The system should pull this pin high using a 4 7 KQ resistor Address Enable When this input is high it disables function selection via 15 0 Access during DMA transfer is not affected by this pin EPP Address Strobe This signal is used in EPP mode as address strobe It is an active low signal Base Address These bits determine one of the four base addresses from which the Index and Data Registers are offset An internal pull down resistor of 30 KQ is on
190. s are trademarks and or registered trademarks of their respective holders ii About this Manual Purpose This service guide aims to furnish technical information to the service engineers and advanced users when upgrading configuring or repairing the TM7300 series notebook computer Manual Structure This service guide contains technical information about the TM7300 series notebook computer It consists of three chapters and five appendices Chapter 1 System Introduction This chapter describes the system features and major components It contains the TM7300 series notebook computer board layout block diagrams cache and memory configurations power management and mechanical specifications Chapter 2 Major Chips Description This chapter describes the features and functions of the major chipsets used in the system board It also includes chipset block diagrams pin diagrams and pin descriptions Chapter 3 BIOS Setup Utility This chapter describes the parameters in the BIOS Ultility screens Chapter 4 Disassembly and Unit Replacement This chapter describes how to disassemble the TM7300 series notebook computer to make replacements or upgrades Appendix A Model Number Definition This appendix shows the different configuration options for the TM7300 series notebook computer Appendix B Exploded View Diagram This appendix illustrates the system board and CPU silk screens Appendix C Spare Parts List This appendi
191. sactions gt fas BCLK Bus Clock This input provides the timing for all transactions on PCI bus BREQ Bus Request This active low output is used to indicate the arbiter T S that NM2160 desires use of the bus 88 BGNT Bus Grant This active low input indicates NM2160 that access to the bus has been granted RESET Reset This active low input is used to initialize 2160 INTA Interrupt request A This active low level sensitive output indicates an interrupt request 145 CLKRUN Clockrun master device will control this signal to the 2160 O D according to the Mobile Computing PCI design guide If this signal is sampled high by the NM2160 and the PCI clock related functions are not completed then it will drive this signal Low to request the Central Clock Resource for the continuation of the PCI clock This function can be Enabled Disabled through register GR12 bit 5 93 XTAL1 Oscillator Input This pin is used to feed in a reference clock of 14MHZ 14 31818Mhz from an external oscillator OR a Clock Source to the internal PLL NM2160 CR70 5 can be programmed to provide a 1Xfsc or 4xfsc NTSC sub carrier frequency for an external analog Encoder XTAL2 17MHZ 2 32 Service Guide Oscillator Input This pin is used to feed in a reference clock of 17 734480Mhz from an external oscillator OR a Clock Source to the internal PLL NM2160 CR70 5 can be programmed to provide a 1Xfsc or 4xfsc PAL SECAM sub carrier
192. signal provides the horizontal synchronization pulse to the ZV port 168 PCLK Video Clock This signal is used to clock the valid video data and the HREF signal into the ZV Port The maximum rate is 16 MHz During display time rising edge of PCLK is used to clock the 16 bit pixel data into the ZV Port 146 VS Vertical SYNC This signal supplies the Vertical synchronization pulse to the ZV Port of 2160 87 MTEST Memory test This active low signal is used for internal memory testing This should be tied high for normal system operation 145 CLKRUN Clockrun master device will control this signal to the 2160 O D according to the Mobile computing PCI design guide If this signal is sampled high by the NM2160 and the PCI clock related functions are not completed then it will drive this signal Low to request the Central Clock Resource for the continuation of the PCI clock This function can be Enabled Disabled through reg GR12 bit 5 110 VGADIS VGA Disable This pin when active disables all the accesses to the NM2160 controller but maintains all the screen refreshes GR12 bit 4 enables disables this feature NOTE When driven by an external source the swing on this pin should not be above LVDD 11 DDC2BD DDC Data O D 12 DDC2BC DDC Clock pin O D 10 29 44 VSSP Host bus interface ground ZV interface ground and Panel 59 80 114 Interface ground 125 138 153 23 64 109 EN Logic ground 88 2 36 S
193. supply 2 A SOCKET VCC powered from the Socket A Vcc supply connecting to PC Card pins 17 and 51 of Socket A 3 B SOCKET VCC powered from the Socket B Vcc supply connecting to PC Card pins 17 and 51 of Socket B PCI VCC powered from the PCI bus power supply CORE VDD powered from a 3 3 volt power supply Major Chips Description 2 61 The following table lists the pin descriptions Table 2 7 CL PD6832 Pin Descriptions PinName Description _ PinNumber Power 0 31 0 PCI Bus Address Input Data Input Outputs 4 5 7 12 16 20 4 These pins connect to PCI bus signals 22 24 38 43 45 AD 31 0 46 48 49 51 56 C BE 3 0 PCI Bus Command Byte Enables The 13 25 36 47 command signaling and byte enables are multiplexed on the same pins During the address phase of a transaction C BE 3 0 are interpreted as the bus commands During the data phase C BE 3 0 are interpreted as byte enables The byte enables are to be valid for the entirety of each data phase and they indicate which bytes in the 32 bit data path are to carry meaningful data for the current data phase FRAME Cycle Frame This signal driven by current master indicates that a bus transaction is beginning While FRAME is asserted data transfers continue When FRAME is deasserted the transaction is in its final phase IRDY Initiator Ready This input indicates the initiating agent s ability to complete the current data phase
194. t four PCICLKs to allow the edge detect logic to reset EXTSMI is asserted by in response to being activated within the Serial IRQ function An external pull up should be placed on this signal LID LID INPUT This signal can be used to monitor the opening and closing of the 10 display lid of a notebook computer It can be used to detect both low to high transition or a high to low transition and these transitions will generate an SMI if enabled This input contains logic to perform a 16 ms debounce of the input signal If the LID function is not needed this pin can be used as a general purpose input PCIREQ A D PCI REQUEST Power Management input signals used to monitor PCI Master Requests for use of the PCI bus They are connected to the corresponding PCI i REQJ 0 3 signals on the Host Bridge GPO18 PWRBTN system events most typically a system on off button or switch This input contains logic to perform a 16 ms debounce of the input signal RING INDICATE Input used by power management logic to monitor external GPH2 system events most typically used for wake up from a modem If this function is not needed then this signal can be individually used as a general purpose input PCI CLOCK STOP Active low control signal to the clock generator used to disable the clock outputs The 4 free running PCICLK input must remain on If this function is not needed this can be used as a
195. t is ready to exchange data The CTS signal is a modem status input The CPU tests the condition of this CTS signal by reading bit 4 CTS of the Modem Status Register MSR for the appropriate serial channel Bit 4 is the complement of the CTS signal Bit 0 DCTS has no effect on the transmitter CTS2 is multiplexed with A13 When it is not selected it is masked to 0 NOTE Whenever MSR DCTS bit is set an interrupt is generated if Modem Status interrupts are enabled Data These are bidirectional data lines to the microprocessor DO is the LSB and D7 is the MSB These signals have a 24 mA sink buffered outputs DMA Acknowledge 0 1 2 3 These active low inputs acknowledge the DMA request and enable the RD and WR inputs during a DMA transfer It can be used by one of the following FDC or Parallel Port If none of them uses this input pin it is ignored If the device which uses on of this pins is disabled or configured with no DMA this pin is also ignored is multiplexed with DRATE1 MSEN1 50 and SIRQI2 UARTs Data Carrier Detect When low this indicates that the modem or data set has detected the data carrier The DCD signal is a modem status input The CPU tests the condition of this DCD signal by reading bit 7 DCD of the Modem Status Register MSR for the appropriate serial channel Bit 7 is the complement of the DCD signal Bit 3 DDCD of the MSR indicates whether DCD input has changed stat
196. te DMA cycles by encoding requests and grants via three PC PCI REQ GNT pairs The second method Distributed DMA allows reads and writes to 82C37 registers to be distributed to other PCI devices The two methods can be enabled concurrently The serial interrupt scheme typically associated with Distributed DMA is also supported 2 2 Service Guide The timer counter block contains three counters that are equivalent function to those found in one 82C54 programmable interval timer These three counters are combined to provide the system timer function refresh request and speaker tone The 14 31818 MHz oscillator input provides the clock source for these three counters PIIX4 provides an ISA Compatible interrupt controller that incorporates the functionality of two 82C59 interrupt controllers The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible In addition PIIX4 supports a serial interrupt scheme PIIX4 provides full support for the use of an external IO APIC All of the registers in these modules can be read and restored This is required to save and restore System state after power has been removed and restored to the circuit Enhanced Universal Serial Bus USB Controller The PIIX4 USB controller provides enhanced support for the Universal Host Controller Interface UHCI This includes support that allows legacy software to use a USB based keyboard and mouse RTC PIIX4 contai
197. terrupt output connected to the PCI bus INTB interrupt line If Misc Control 2 register bit 7 is 1 as a ring indicate output from a socket s BVD1 STSCHG RI input In External Hardware Interrupt Signaling mode this pin indicates interrupt request IRQ10 Serial Interrupt Output PCI Bus Interrupt C Serial IRQ Load In PCI Interrupt Signaling mode this output can be used as an interrupt output connected to the PCI bus INTC interrupt line In PC PCI Serial Interrupt Signaling mode this pin is the serial interrupt output SOUT In External Hardware Interrupt Signaling mode this pin is the load signal ISLD used to load the serially transmitted interrupt data into the external serial to parallel shifters Major Chips Description 2 63 Table 2 7 CL PD6832 Descriptions i 12 Serial Interrupt Input PCI Bus Interrupt D 206 Serial IRQ Data PCI Interrupt Signaling mode this output can be used as an interrupt output connected to the PCI bus INTD interrupt line In PC PCI Serial Interrupt Signaling mode this pin is the serial interrupt input SIN In External Hardware Interrupt Signaling mode this pin is the IRQ vector data ISDAT that is serially transmitted to the external serial to parallel shifters CLKRUN Clock Run This pin is an input to indicate the 208 4 status of PCI CLK and an open drain output to request the starting or speeding up of PCI CLK This pi
198. the RTC logic and must be tied to 3 3V VCC SUS V SUSPEND WELL VOLTAGE SUPPLY These pins are the primary voltage supply for the PIIX4 suspend logic and IO signals and must be tied to 3 3V VCC USB V USB VOLTAGE SUPPLY This pin is the supply voltage for the USB input output buffers and must be tied to 3 3V VREF V VOLTAGE REFERENCE This pin is used to provide a 5V reference voltage for 5V safe input buffers VREF must be tied to 5V in a system requiring 5V tolerance In a 5V tolerant system this signal must power up before or simultaneous to VCC It must power down after or simultaneous to VCC In a non 5V tolerant system 3 3V only this signal can be tied directly to VCC There are then no sequencing requirements CORE GROUND These pins are the primary ground for VSS USB USB GROUND This pin is the ground for the USB input output buffers Major Chips Description 2 27 2 3 NM2160 2160 is a high performance Panel Video Accelerator that integrates one single chip 2 Mbytes of High Speed DRAM 24 bit true color RAMDAC Graphics Video Accelerator Dual clock synthesizer TV Out support ZV Zoomed Video port Z Buffer Data Stripping PCI Bus Mastering and a high speed glueless 32 bit PCI 2 1 compliance interface By integrating the display buffer DRAM and 128 bit graphics video accelerator the NM2160 achieves the leading performance in the smallest footprint available The NM2160 has sufficient b
199. this pin Use a 10 KQ resistor to pull this pin to VCC UARTs Baud Output This multi function pin supports the associated serial channel Baud Rate generator output signal if the test mode is selected in the Power and Test Configuration Register and the DLAB bit LCR7 is set After the Master Reset this pin offers the SOUT function Parallel Port Busy This pin is set high by the printer when it cannot accept another character It has a nominal 25 KQ pull down resistor attached to it SIO Configuration Strap These CMOS inputs select 1 of 4 default configurations in which the PC97338 powers up An internal pull down resistor of 30 KQ is on this Use a 10 KQ resistor to pull these pins to VCC CFGO is multiplexed with 50072 BOUT2 and IRTX Programmable Chip Select CSO 1 are programmable chip select and or latch enable and or output enable signals that can be used as game port I O expand etc The decoded address and the assertion conditions are configured via the 97338VJG s configuration registers Service Guide Table 2 6 NS97338VJG Descriptions m Tec Tie Trees 7 10 17 T DACKO DACK1 2 3 49 DCD1 DCD2 75 67 46 DENSEL 76 PPM Mode DIR Normal Mode DIR PPM Mode DRO 42 43 DR1 Normal Mode Major Chips Description UARTs Clear to Send When low this indicates that the modem or data se
200. tive is the default configuration An active IRQ input must remain asserted until after the interrupt is acknowledged If the input goes inactive before this time a default IRQ7 is reported in response to the interrupt acknowledge cycle IRQ 8 IRQ8 is always an active low edge triggered interrupt and can not be modified by software IRQ8 must remain asserted until after the interrupt is acknowledged If the input goes inactive before this time a default IRQ7 is reported in response to the interrupt acknowledge cycle If using the internal RTC then this be programmed as a general purpose input enabling an APIC this signal becomes an output and must not be programmed as a general purpose input 9 IRQ9OUTE is used to route the internally generated SCI and SMBus interrupts out of the PIIX4 for connection to an external IO APIC If APIC is disabled this signal pin is a General Purpose Output During Reset High After Reset High During POS IRQQ9OUT GPO IRQ8 GPI6 IRQ9OUT GPO29 IRQO INTERRUPT REQUEST 0 This output reflects the state of the internal IRQO GPO14 signal from the system timer If the external APIC is not used this pin is a general purpose output During Reset Low After Reset Low During POS IRQ0 GPO 2 16 Service Guide Table 2 2 82371AB Pin Descriptions 12 INTERRUPT REQUEST 12 In addition to providing the standard interrupt function as described in
201. usly to the rising edge of PCICLK If a hard reset is initiated through the RC register resets signal is active high for Pentium processor and active low for Pentium its internal registers in both core and suspend wells to their default state This processor as determined by 1 signal For values During Reset After Reset and During POS see the Suspend Resume and Resume Control Signaling section CPURST FERR IGNNE NUMERIC COPROCESSOR ERROR This pin functions as a FERR signal supporting coprocessor errors This signal is tied to the coprocessor error signal on the CPU If FERR is asserted PIIX4 generates an internal IRQ13 to its interrupt controller unit PIIX4 then asserts the INT output to the CPU FERR is also used to gate the IGNNE signal to ensure that IGNNE is not asserted to the CPU unless is active IGNORE NUMERIC EXCEPTION This signal is connected to the ignore numeric exception pin on the CPU IGNNEZ is only used if the PIIX4 coprocessor error reporting function is enabled If FERR is active indicating a coprocessor error write to the Coprocessor Error Register FOh causes the IGNNE to be asserted IGNNE remains asserted until FERR is negated If FERR is not asserted when the Coprocessor Error Register is written the IGNNE signal is not asserted During Reset High Z After Reset High Z During POS High Z Major Chips Description 2 17 Table 2 2 82371AB Pin Descript
202. valid suspend to disk mode becomes unavailable and the computer automatically switches to suspend to memory mode 3 4 2 Suspend to Disk on Critical Battery With this parameter is set to Enabled the computer enters suspend to disk mode when the battery becomes critically low The default setting is Enabled 3 4 3 Display Always On This parameter lets you specify whether the display is always on or not When enabled the screen will not blank To save power the default setting is Disabled 3 4 4 Resume On Modem Rings You can set the computer to resume from suspend to memory mode upon detection of a specific number of modem rings ranging from 1 to 7 Enabling this option overrides the suspend to disk function BIOS Setup Information 3 7 3 4 5 Resume On Schedule When this parameter is set to Enabled the computer resumes from suspend to memory mode at the specified date and time Enabling this option overrides the suspend to disk function The Resume Date and Resume Time parameters let you set the date and time for the resume operation The date and time fields take the same format as the System Date and Time parameters in the System Configuration screen If you set a date and time prior to when the computer enters suspend mode this field is automatically disabled A successful resume occurring from a date and time match also automatically disables this field 3 8 Service Guide 35 System Security When you select
203. vanced power management features mixed voltage operation and integrated Serial Infrared both IrDA and Sharp support makes the PC97338 an ideal choice for low power and or portable personal computer applications The PC97338 FDC uses a high performance digital data separator eliminating the need for any external filter components It is fully compatible with the PC8477 and incorporates a superset of DP8473 NEC PD765 and N82077 floppy disk controller functions All popular 5 25 and 3 5 floppy drives including the 2 88 MB 3 5 floppy drive are supported In addition automatic media sense and 2 Mbps tape drive support are provided by the FDC The two UARTs are fully NS16450 and NS16550 compatible Both ports support MIDI baud rates and one port also supports IrDA 1 0 SIR with data rate of 115 2Kbps IrDA 1 1 MIR and FIR with data rate of 1 152Mbps and 4 0Mbps respectively and Sharp SIR with data rate of 38 4Kbps respectively compliant signaling protocol The parallel port is fully IEEE 1284 level 2 compatible The SPP Standard Parallel Port is fully compatible wit ISA and EISA parallel ports In addition to the SPP EPP Enhanced Parallel Port and ECP Extended Capabilities Port modes are supported by the parallel port A set of configuration registers are provided to control the Plug and Play and other various functions of the PC97338 These registers are accessed using two 8 bit wide index and data registers The ISA address of the r
204. ve 060 yz 7 1 asep T b OK vei 198 8 1 61 81 54 20614 szu 4 ezu 608 4 angio 37 a 391 jai EY OW THON EWN 19118 andio Tel za 558 5 288 BLONT EWN TNS TZ ONS 8623 1924 1623 TNS Tz TNS 423 183 s lt ace 86 27 718 24 423 45 47 EWN 50 6129 Steet SUS E34 EWN ettare SL 3DiS E34 55 F 8084 REL 4 ATEN 58 etu 4 4 i 19 AEREE PUK EWN IEE EW 818 818 5 ASHE 488 Sie sru eee ste ASAE 6 AShEd 61 81 5421135130 814 884 INC 58 61581514 310 T E34 181 HH coe eid 5 18 ere HH T SWJ EHH 61 81 2t Sc 3NUNJ E Jd 218 T SET ERN zia 508 1161 109 254 ce tie Twa TE TT ELEI UNS UNS S CEUTW EIi ZUTW EId 9 018 08 ot Sede 28 TOW 88 60 CE coaavasayy 671 58 58 NIJO 82198 9 LS NIJO 84148
205. video with 128 bit graphics accelerator Flexible module bay 3 5 inch floppy drive or CD ROM drive or DVD ROM drive or LS120 or second hard disk drive option High capacity Enhanced IDE hard disk An advanced power management system with two power saving modes lithium lon smart battery pack e High speed connectivity MULTIMEDIA AND COMMUNICATIONS 3 16 bit stereo audio with built in FM synthesizer and 3D sound effect Built in microphone and dual angled stereo speakers Support for simultaneous display on the built in screen and an external monitor for presentations Full screen 30 frames per second true color MPEG video playback Infrared wireless communication ERGONOMICS Intuitive FlashStart automatic power on Sleek smooth and stylish design 3 Automatic tilt up 12 1 inch models only full sized full function keyboard e Wide and comfortable palm rest System Introduction 1 1 3 Ergonomically positioned touchpad pointing device EXPANDABILITY CardBus PC Card PCMCIA slots two type or one type with Zoomed Video port function Mini dock option with two CardBus PC Card slots two type or one type 111 USB port onboard Upgradeable memory and hard disk 1 1 22 FlashStart Automatic Power On The computer has no on off switch Instead it uses a lid switch located near the center of the display hinge that turns the computer on and off automatically
206. wer plane control is not needed this pin can be used as a general purpose output During Reset Low After Reset High During POS High GPO SUSC SUSPEND PLANE C CONTROL Control signal asserted during power GPO16 management suspend states primarily used to control the tertiary power plane It is asserted only during STD suspend state If the power plane control is not needed this pin can be used as a general purpose output During Reset Low After Reset High During POS High GPO 505 5 14 SUSPEND STATUS 1 This signal is typically connected to the Host to PCI GPO20 bridge and is used to provide information on host clock status SUS_STAST1 is asserted when the system may stop the host clock such as Stop Clock or during POS STR and STD suspend states If this function is not needed this pin can be used as a general purpose output During Reset Low After Reset High During POS Low GPO 505 2 SUSPEND STATUS 2 This signal will typically connect to other system GPO 1 peripherals and is used to provide information on system suspend state It is asserted during POS STR and STD suspend states If this function is not needed this pin can be used as a general purpose output During Reset Low After Reset High During POS Low GPO THRM THERMAL DETECT Active low signal generated by external hardware to start the Hardware Clock Throttling mode enabled the external hardware can force the system to enter into
207. x lists the spare parts for the TM7300 series notebook computer with their part numbers and other information iii Conventions This appendix contains the schematic diagrams for the system board BIOS POST Checkpoints This appendix lists and describes the BIOS POST checkpoints The following are the conventions used in this manual Text entered by user Screen messages 25 Ever etc iv 2 gt 9 Represents text input by the user Denotes actual messages that appear onscreen Represent the actual keys that you have to press on the keyboard NOTE Gives bits and pieces of additional information related to the current topic WARNING Alerts you to any damage that might result from doing or not doing specific actions CAUTION Gives precautionary measures to avoid possible hardware or software problems IMPORTANT Reminds you to do specific actions relevant to the accomplishment of procedures TIP Tells how to accomplish a procedure with minimum steps through little shortcuts Table of Contents Chapter 1 System Introduction 1 1 Features EEEEMMMMEEEEMIMMEEEEEMMMMMEMM 1 1 1 1 2 FlashStart Automatic 1 2 1 2 Emu 1 3 1 2 1 Rear Panel Ports rrt cerne ket ee ei enero eaae 1 3 1 2 2 Left Panel et OE REEL ERE 1 4 1 2 3

Acer TM7300 User's Manual

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