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Micron 4GB DDR3

1. Front view 2 7 0 106 133 50 5 256 MAX T 733 20 5 244 a oe 0 9 0 035 TYP gt 0 50 0 02 R A E 4x r 0 75 0 03 R U1 U2 U3 U4 U5 U6 U7 U8 E 30 50 1 20 8X 23 3 0 92 39 85 1 175 R r 1 7 7 TYP 2 50 0 098 D A 17 3 0 68 2X J ug t TYP 2 30 0 091 TYP 4 li 0 76 0 030 R kL t 1 37 0 054 2 20 0 087 TYP 1 0 0 039 0 80 0 031 9 5 0 374 1 17 0 046 TYP TYP TYP 1 45 0 057 TYP 54 68 2 15 Pin 120 TYP 123 0 4 84 TYP 15 0 0 59 4X TYP 4 1 0 0 039 R 8X Back view oS TX 5 1 0 2 TYP EN f J we 2X TYP J No components this side of module C D C 3 0 0 118 4x TYP t 3 05 0 12 vve C TLL MMM UTM MUTT E t N Pin 240 Pin 121 5 0 0 197 TYP 71 0 2 79 A 47 0 1 85 TYP TYP Notes 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted 2 The dimensional diagram is for reference only 8000 S Federal Way P O Box 6 Boise ID 83707 0006 Tel 208 368 3900 www micron com productsupport Customer Comment Line 800 932 4992 Micron and the Micron logo are trademarks of Micron Technology Inc All other trademarks are the property of their respective owners This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein Although considered final these specifications are subject to change as further product developme
2. _ SPD EEPROM Vbp p p p R SDRAM v I gt gt Address command TT and control termination VREFCA gt DDR3 SDRAM VREFDQ t gt DDR3 SDRAM Vss E DDR3 SDRAM 1 The ZQ ball on each DDR3 component is connected to an external 2400 1 resistor that is tied to ground It is used for the calibration of the component s ODT and output driver PDF 09005aef837d3ecf jtf8c128_256_512x64az pdf Rev H 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2009 Micron Technology Inc All rights reserved In icron 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM General Description General Description DDR3 SDRAM modules are high speed CMOS dynamic random access memory mod ules that use internally configured 8 bank DDR3 SDRAM devices DDR3 SDRAM mod ules use DDR architecture to achieve high speed operation DDR3 architecture is essen tially an 8n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I O pins A single read or write access for the DDR3 SDRAM mod ule effectively consists of a single 8n bit wide one clock cycle data transfer at the inter nal DRAM core and eight corresponding n bit wide one half clock cycle data transfers at the I O pins DDR3 modules use two sets of differential signals DQS DQS to capture data and CK and CK to capture commands addresses and control signals
3. 09005aef837d3ecf 1 2 jtf8c128_256_512x64az pdf Rev H 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2009 Micron Technology Inc All rights reserved Macron Table 14 DDR3 Ipp Specifications and Conditions 2GB Die Revision M 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Ipp Specifications Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb 256 Meg x 8 com ponent data sheet Parameter Symbol 1866 1600 1333 1066 Units Operating current 0 One bank ACTIVATE to PRECHARGE Ippo 600 560 520 480 mA Operating current 1 One bank ACTIVATE to READ to PRECHARGE lpp1 680 640 600 560 mA Precharge power down current Slow exit IDD2P0 96 96 96 96 mA Precharge power down current Fast exit Ipp2P1 336 296 256 216 mA Precharge quiet standby current IDD2Q 360 320 280 240 mA Precharge standby current IDD2N 284 344 304 264 mA Precharge standby ODT current IDD2NT 400 360 320 280 mA Active power down current lpp3p 440 400 360 320 mA Active standby current lpp3n 480 440 400 360 mA Burst read operating current DD4R 1368 1248 1128 1040 mA Burst write operating current Ippaw 1280 1160 1040 920 mA Refresh current IppsB 1600 1560 1520 1480 mA Self refresh temperature current MAX Tc 85 C Ipp6 96 96 96 96 mA Self refresh temperature current SRT ena
4. See the Pin Assignments Table for density specific addressing information BAx Input Bank address inputs Define the device bank to which an ACTIVE READ WRITE or PRECHARGE command is being applied BA define which mode register MRO MR1 MR2 or MR3 is loaded during the LOAD MODE command CKx Input Clock Differential clock inputs All control command and address input signals are CKx sampled on the crossing of the positive edge of CK and the negative edge of CK CKEx Input Clock enable Enables registered HIGH and disables registered LOW internal circui try and clocks on the DRAM DMx Input Data mask x8 devices only DM is an input mask signal for write data Input data is masked when DM is sampled HIGH along with that input data during a write ac cess Although DM pins are input only DM loading is designed to match that of the DQ and DQS pins ODTx Input On die termination Enables registered HIGH and disables registered LOW termi nation resistance internal to the DDR3 SDRAM When enabled in normal operation ODT is only applied to the following pins DQ DQS DQS DM and CB The ODT input will be ignored if disabled via the LOAD MODE command Par_In Input Parity input Parity bit for Ax RAS CAS and WE RAS CAS WE Input Command inputs RAS CAS and WE along with S define the command being entered RESET Input Reset RESET is an active LOW asychronous input that is connected to each DRAM LVCMOS
5. DQ12 Ww DQ DQ44 wr DQ DQ13 W DQ DQ45 W DQ DQ14 pw DQ Doae w DQ DQ15 M DQ DQ47 M DQ um ZQ mM zQ DQS2 S5 M DQS6 55 M DQS2 M DQS6 M ee ree DM CSF DOS DOSH DQIE M DQ PM CS DOS DASH DQ48 W4DQ DQ17 M DQ DQ49 MH DQ DQ18 M DQ DQ50 W DQ DQ19 M DQ DQ51 M DQ DQ20 WDQ U3 DQ52 H DQ U7 DQ21 H DQ DQ53 my DQ DQ22 M DQ DQ54 WDQ DQ23 M DQ DQ55 y DQ vo ZQ rw Za DQS3 S5 DQS7 SS y DQS3 WwW DQs7 WW DM3 W DM7 MN poet DM CS DOS DOSH DM CSF DAS DOSH DQ25 W DQ DQ56 W 4 DQ DQ2z6 W DQ DQ57 WW DQ DQ27 W DQ DQ58 DQ DQ28 W DQ u4 DQ59 M DQ u8 DQ2 W DQ DQ60 M DQ DQ30 W DQ DQ61 yH DQ DQ3tT W DQ DQ62 DQ W DQ DQ63 Wr DQ yw ZQ mH ZQ ss Vss Note BA 2 0 A 15 14 13 0 RAS CAS WE CKEO ODTO RESET BA 2 0 DDR3 SDRAM A 15 14 13 0 DDR3 SDRAM RAS DDR3 SDRAM CAS DDR3 SDRAM WE DDR3 SDRAM CKE0 DDR3 SDRAM _ ODT0 DDR3 SDRAM gt RESET DDR3 SDRAM Address command control and clock line terminations DDR3 CKEO A 15 14 13 0 SDRAM RAS CAS WE Ver SO ODTO BA 2 0 DDR3 SDRAM CKO I W V cKO it WA rt DD U9 scL gt SPD EEPROM SDA WP AO A1 A2 vl sko ski shz CKO cKO gt DDR3 SDRAM x8 CK1 cK1 Unused clock termination Vopsep
6. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals Fly By Topology DDR3 modules use faster clock speeds than earlier DDR technologies making signal quality more important than ever For improved signal quality the clock control com mand and address buses have been routed in a fly by topology where each clock con trol command and address pin on each DRAM is connected to a single trace and ter minated rather than a tree structure where the termination is off the module near the connector Inherent to fly by topology the timing skew between the clock and DQS sig nals can be easily accounted for by using the write leveling feature of DDR3 Serial Presence Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence detect The SPD data is stored ina 256 byte EEPROM The first 128 bytes are programmed by Micron to comply with JEDEC standard JC 45 Appendix X Serial Presence Detect SPD for DDR3 SDRAM Modules These bytes identify module specific timing parameters configuration infor mation and physical attributes The remaining 128 bytes of storage are available for use by the customer System READ WRITE operations between the master system logic and the slave EEPROM device occur via a standard I C bus using the DIMM s SCL clock SDA data and SA address pins Write protect WP is connected to V ss per manent
7. I Z 1G1__ 4GB 512 Meg x 64 8 5 GB s 1 87ns 1066 MT s 7 7 7 Notes 1 Data sheets for the base device parts can be found on Micron s Web site 2 All part numbers end with a two place code not shown that designates component and PCB revisions Con sult factory for current revision codes Example MT8JTF51264AZ 1G4E1 PDF 09005aef837d3ecf jtf8c128_256_512x64az pdf Rev H 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2009 Micron Technology Inc All rights reserved Macron Pin Assignments Table 6 Pin Assignments 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Pin Assignments 2 Pin 172 is NC for 1GB A14 for 2GB and 4GB 240 Pin DDR3 UDIMM Front 240 Pin DDR3 UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 Vreroo 31 DQ25 61 A2 91 DQ41 121 Vs 151 Vs 181 A1 211 Vss 2 Vss 132 Vss 62 Vpop 92 Vss 122 DQ4 152 DM3 182 Vpp 212 DM5 3 DQO 33 DQS3 63 CK1 93 DQS5 123 DQ5 153 NC 183 Vop 213 NC 4 DQ1 34 DQS3 64 CK1 94 DQS5 124 Vss 154 Vss 184 CKO 214 Vss 5 Vss 135 Vss 165 Vpp 95 Vss 125 DMO 155 DQ30 185 CKO 215 DQ46 6 DQSO 36 DQ26 66 Vpp 96 DQ42 1
8. 0 05 2 0 pA Table 18 Serial Presence Detect EEPROM AC Operating Conditions Parameter Condition Symbol Min Max Units Notes Clock frequency tSCL 10 400 kHz Clock pulse width HIGH time THIGH 0 6 us Clock pulse width LOW time tLOW 1 3 us SDA rise time tR 300 us 1 SDA fall time tF 20 300 ns 1 Data in setup time tSU DAT 100 ns Data in hold time tHD DI 0 us Data out hold time tHD DAT 200 900 ns Data out access time from SCL LOW tAA DAT 0 2 0 9 us Start condition setup time tSU STA 0 6 us Start condition hold time tHD STA 0 6 us Stop condition setup time tSU STO 0 6 us Time the bus must be free before a new transition can tBUF 1 3 us start WRITE time tw 10 ms Notes 1 Guaranteed by design and characterization not necessarily tested 2 To avoid spurious start and stop conditions a minimum delay is placed between the fall ing edge of SCL and the falling or rising edge of SDA 3 For a restart condition or following a WRITE cycle PDF 09005aef837d3ecf jtf8c128_256_512x64az pdf Rev H 04 13 EN 16 Micron Technology Inc reserves the right to change products or specifications without notice 2009 Micron Technology Inc All rights reserved In icron 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Module Dimensions Module Dimensions Figure 3 240 Pin DDR3 UDIMM
9. 26 NC 156 DQ31 186 VDD 216 DQ47 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 NC 217 Vss 8 Vss 38 Vss 68 NC 98 Vss 128 DQ6 158 NC 188 AO 218 DQ52 9 DQ2 39 NC 69 Vpp 99 DQ48 129 DQ7 159 NC 189 VDD 219 DQ53 10 DQ3 40 NC 70 A10 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss 11 Vs 141 Vs 71 BAO 101 Vss 131 DQ12 161 NC 191 Vpp 221 DM6 12 DQ8 42 NC 72 Vpp 102 DQS6 132 DQ13 162 NC 192 RAS 222 NC 13 DQ9 43 NC 73 WE 103 DQS6 133 Vss 163 Vss 193 SO 223 Vss 14 Vs 44 Vss 74 CASH 104 Vss 134 DM1 164 NC 194 Vpp 224 DQ54 15 DQS1 45 NC 75 Vopp 105 DQ50 135 NC 165 NC 195 ODTO 225 DQ55 16 DQS1 46 NC 76 NC 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss 17 Ys 47 Vs 177 NC 107 Vss 137 DQ14 167 NC 197 Vpp 227 DQ60 18 DQ10 48 NC 78 Vpp 108 DQ56 138 DQ15 168 RESET 198 NC 228 DQ61 19 DQ11 49 NC 79 NC 109 DQ57 139 Vss 169 NC 199 Vss 229 Vss 20 Vss 50 CKEO 80 Vss 110 Vss 140 DQ20 170 Vopp 200 DQ36 230 DM7 21 DQ16 51 Vpp 81 DQ32 111 DQS7 141 DQ21 171 NC A15 201 DQ37 231 NC 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 Vss 172 NC A142 202 Vss 232 Vss 23 Vss 53 NC 83 Vss 113 Vss 143 DM2 173 Vop 203 DM4 233 DQ62 24 DQS2 54 Vpp 84 DQS4 114 DQ58 144 NC 174 A12 204 NC 234 DQ63 25 DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 175 A9 205 Veg 235 Vss 26 Vss 5
10. 6 A7 86 Vss 116 Vss 146 DQ22 176 VDD 206 DQ38 236 Vppspp 27 DQ18 57 Vopp 87 DQ34 117 SAO 147 DQ23 177 A8 207 DQ39 237 SA1 28 DQ19 58 A5 88 DQ35 118 SCL 148 Vss 178 A6 208 Vss 238 SDA 29 Vss 59 A4 89 Vss 119 SA2 149 DQ28 179 Vopp 209 DQ44 239 Vss 30 DQ24 60 Vpp 90 DQ40 120 Vit 150 DQ29 180 A3 210 DQ45 240 Vit Notes 1 Pin 171 is NC for 1GB and 2GB A15 for 4GB PDF 09005aef837d3ecf jtf8c128_256_512x64az pdf Rev H 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2009 Micron Technology Inc All rights reserved Macron Pin Descriptions 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Pin Descriptions The pin description table below is a comprehensive list of all possible pins for all DDR3 modules All pins listed may not be supported on this module See Pin Assignments for information specific to this module Table 7 Pin Descriptions Symbol Type Description Ax Input Address inputs Provide the row address for ACTIVE commands and the column ad dress and auto precharge bit A10 for READ WRITE commands to select one location out of the memory array in the respective bank A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank A10 LOW bank selected by BAx or all banks A10 HIGH The address inputs also provide the op code during a LOAD MODE command
11. 95V All CAS WE other pins not under test BA S CKE OV ODT CK CK DM 2 0 2 loz Output leakage current OV lt DQ DQS 5 0 5 pA Vout lt Vppq DQ and ODT are DQS disabled ODT is HIGH IVREF VREF supply leakage current VREFDQ Vpp 2 8 0 8 pA or Vrerca Vpp 2 All other pins not under test OV Ta Module ambient operating Commercial 0 70 C 2 3 temperature Industrial 40 85 C Te DDR3 SDRAM component case Commercial 0 85 C 2 3 4 operating temperature Industrial 40 95 C Notes 1 Vy termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins 2 Ta and Tc are simultaneous requirements 3 For further information refer to technical note TN 00 08 Thermal Applications avail able on Micron s Web site 4 The refresh rate is required to double when 85 C lt Tc lt 95 C PDF 09005aef837d3ecf 9 Micron Technology Inc reserves the right to change products or specifications without notice jtf8c128_256_512x64az pdf Rev H 04 13 EN 2009 Micron Technology Inc All rights reserved 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM DRAM Operating Conditions Macron DRAM Operating Conditions Recommended AC operating conditions are given in the DDR3 component data sheets Component specifications are available on Micron s web site Module speed grades cor rel
12. Active standby current lpp3n 328 304 280 256 mA Burst read operating current DD4R 1392 1256 1120 984 mA Burst write operating current Ippaw 1128 1000 880 760 mA Refresh current IppsB 1936 1880 1824 1792 mA Self refresh temperature current MAX Tc 85 C Ipp6 160 160 160 160 mA Self refresh temperature current SRT enabled MAX Tc 95 C IDD6ET 200 200 200 200 mA All banks interleaved read current lpbp7 2008 1760 1520 1280 mA Reset current lops 160 160 160 160 mA PDF 09005aef837d3ecf 1 5 jtf8c128_256_512x64az pdf Rev H 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2009 Micron Technology Inc All rights reserved Macron Serial Presence Detect EEPROM For the latest SPD data refer to Micron s SPD page www micron com SPD 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Serial Presence Detect EEPROM Table 17 Serial Presence Detect EEPROM DC Operating Conditions All voltages referenced to Vppspp Parameter Condition Symbol Min Max Units Supply voltage Vppspp 3 0 3 6 V Input low voltage Logic 0 All inputs Vil 0 6 Vppspp 0 3 V Input high voltage Logic 1 All inputs Vin Vppspp 0 7 Vppspp 1 0 V Output low voltage lout 3MA VoL 0 4 V Input leakage current Vin GND to Vpp lu 0 1 2 0 yA Output leakage current Vout GND to Vpp lLo
13. Macron 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Features DDR3 SDRAM UDIMM MT8JTF12864AZ 1GB MT8JTF25664AZ 2GB MT8JTF51264AZ 4GB Features DDR3 functionality and operations supported as defined in the component data sheet 240 pin unbuffered dual in line memory module UDIMM Fast data transfer rates PC3 14900 PC3 12800 PC3 10600 PC3 8500 or PC3 6400 1GB 128 Meg x 64 2GB 256 Meg x 64 or 4GB 512 Meg x 64 Vpp Vppg 1 5V 0 075V Vppspp 3 0V to 3 6V Reset pin for improved system stability Nominal and dynamic on die termination ODT for data strobe and mask signals Single rank Fixed burst chop BC of 4 and burst length BL of 8 via the mode register set MRS Adjustable data output drive strength Serial presence detect SPD EEPROM Gold edge contacts Halogen free Fly by topology Terminated control command and address bus Table 1 Key Timing Parameters Figure 1 240 Pin UDIMM MO 269 R C A Module height 30mm 1 181in Options Marking e Operating temperature Commercial 0 C lt T4 lt 70 C None Industrial 40 C lt T4 lt 85 C I e Package 240 pin DIMM halogen free Z e Frequency CAS latency 1 07ns CL 13 DDR3 1866 1G9 1 25ns CL 11 DDR3 1600 1G6 1 5ns CL 9 DDR3 1333 1G4 1 87ns CL 7 DDR3 1066 1G1 Note 1 Contact Micron fo
14. Q Module DQ Number Number DQ Module DQ Number U1 0 15 138 1 13 132 2 14 137 3 8 12 4 11 19 5 12 131 6 10 18 7 9 13 U3 0 31 156 1 29 150 2 30 155 3 24 30 4 27 37 5 28 149 6 26 36 7 25 31 U5 0 47 216 1 45 210 2 46 215 3 40 90 4 43 97 5 44 209 6 42 96 7 41 91 U7 0 63 234 1 61 228 2 62 233 3 56 108 4 59 115 5 60 227 6 58 114 7 57 109 PDF 09005aef837d3ecf 6 Micron Technology Inc reserves the right to change products or specifications without notice jtf8c128_256_512x64az pdf Rev H 04 13 EN 2009 Micron Technology Inc All rights reserved Macron Functional Block Diagram Figure 2 Functional Block Diagram SO 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Functional Block Diagram DQso WwW DQS4 WW DQso M DQS4 M DMO MN DM4 M DM CS DQS DQS DM CS DQS DQS Deo H DQ DQ32 W4DQ DQ1 H PQ DQ33 W4 DQ DQ2 H DQ DQ34 M DQ DQ3 MH DQ U1 DQ35 M DQ u5 DQ4 H DQ DQ36 H DQ DQ5 DQ DQ37 r DQ Das r4 DQ DQ38 r DQ DQ7 yH DQ DQ39 r DQ mwiza mza Dosie Sy DQS5 EVN DQs1 WW DQS5 W DM1 DM5 M Das po PM CSF DOS DOSH pas oe CSH DOS DQS DQ9 M DQ DQ41 W DQ DQ10 W DQ DQ42 W4 DQ DQ11 Ww DQ U2 pe4az W DQ U6
15. SO Table 3 Part Numbers and Timing Parameters 1GB Modules Base device MT41J128M8 1Gb DDR3 SDRAM Module Module Memory Clock Clock Cycles Part Number Density Configuration Bandwidth Data Rate CL tRCD tRP MT8JTF12864A I Z 1G9__ 1GB 128 Meg x 64 14 9 GB s 1 07ns 1866 MT s 13 13 13 MT8JTF12864A I Z 1G6__ 1GB 128 Meg x 64 12 8 GB s 1 25ns 1600 MT s 11 11 11 MT8JTF12864A I Z 1G4_ 1GB 128 Meg x 64 10 6 GB s 1 5ns 1333 MT s 9 9 9 MT8JTF12864A I Z 1G1__ 1GB 128 Meg x 64 8 5 GB s 1 87ns 1066 MT s 7 7 7 Table 4 Part Numbers and Timing Parameters 2GB Modules Base device MT41J256M8 2Gb DDR3 SDRAM Module Module Memory Clock Clock Cycles Part Number Density Configuration Bandwidth Data Rate CL tRCD tRP MT8JTF25664A I Z 1G9__ 2GB 256 Meg x 64 14 9 GB s 1 07ns 1866 MT s 13 13 13 MT8JTF25664A I Z 1G6__ 2GB 256 Meg x 64 12 8 GB s 1 25ns 1600 MT s 11 11 11 MT8JTF25664A I Z 1G4__ 2GB 256 Meg x 64 10 6 GB s 1 5ns 1333 MT s 9 9 9 MT8JTF25664A I Z 1G1__ 2GB 256 Meg x 64 8 5 GB s 1 87ns 1066 MT s 7 7 7 Table 5 Part Numbers and Timing Parameters 4GB Modules Base device MT41J512M8 4Gb DDR3 SDRAM Module Module Memory Clock Clock Cycles Part Number2 Density Configuration Bandwidth Data Rate CL RCD RP MT8JTF51264A I Z 1G9__ 4GB 512 Meg x 64 14 9 GB s 1 07ns 1866 MT s 13 13 13 MT8JTF51264A 1 Z 1G6__ 4GB 512 Meg x 64 12 8 GB s 1 25ns 1600 MT s 11 11 11 MT8JTF51264A I Z 1G4__ 4GB 512 Meg x 64 10 6 GB s 1 5ns 1333 MT s 9 9 9 MT8JTF51264A
16. and the registering clock driver After RESET goes HIGH the DRAM must be reinitial ized as though a normal power up was executed Sx Input Chip select Enables registered LOW and disables registered HIGH the command decoder SAX Input Serial address inputs Used to configure the temperature sensor SPD EEPROM ad dress range on the I2C bus SCL Input Serial clock for temperature sensor SPD EEPROM Used to synchronize communi cation to and from the temperature sensor SPD EEPROM on the IC bus CBx O Check bits Used for system error detection and correction DQx 1 0 Data input output Bidirectional data bus DQSx 1 0 Data strobe Differential data strobes Output with read data edge aligned with DQSx read data input with write data center aligned with write data PDF 09005aef837d3ecf jtf8c128_256_512x64az pdf Rev H 04 13 EN 4 Micron Technology Inc reserves the right to change products or specifications without notice 2009 Micron Technology Inc All rights reserved Macron 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Pin Descriptions Table 7 Pin Descriptions Continued Symbol Type Description SDA 1 0 Serial data Used to transfer addresses and data into and out of the temperature sen sor SPD EEPROM on the I C bus TDQSx Output Redundant data strobe x8 devices only TDQS is enabled disabled via the LOAD TDQSx MODE command to the extended mode regi
17. ate with component speed grades as shown below Table 11 Module and Component Speed Grades DDR3 components may exceed the listed module speed grades module may not be available in all listed speed grades Module Speed Grade Component Speed Grade 2G1 093 1G9 107 1G6 125 1G4 15E 1G1 187E 1G0 187 80C 25E 80B 25 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully de signed terminations controlled board impedances routing topologies trace length matching and decoupling However good signal integrity starts at the system level Micron encourages designers to simulate the signal characteristics of the system s memory bus to ensure adequate signal integrity of the entire memory system Power Operating voltages are specified at the DRAM not at the edge connector of the module Designers must account for any system voltage drops at anticipated power levels to en sure the required supply voltage is maintained PDF 09005aef837d3ecf 1 0 Micron Technology Inc reserves the right to change products or specifications without notice jtf8c128_256_512x64az pdf Rev H 04 13 EN 2009 Micron Technology Inc All rights reserved Macron lbp Specifications Table 12 DDR3 Ipp Specifications and Conditions 1GB Die Revision G 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM lbp Specifications Value
18. bled MAX Tc 95 C IDD6ET 120 120 120 120 mA All banks interleaved read current lpbp7 2040 1920 1800 1680 mA Reset current lops 112 112 112 112 mA PDF 09005aef837d3ecf 1 3 jtf8c128_256_512x64az pdf Rev H 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2009 Micron Technology Inc All rights reserved Macron Table 15 DDR3 Ipp Specifications and Conditions 2GB Die Revision K 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Ipp Specifications Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb 256 Meg x 8 com ponent data sheet Parameter Symbol 1866 1600 1333 1066 Units Operating current 0 One bank ACTIVATE to PRECHARGE Ippo 344 336 328 312 mA Operating current 1 One bank ACTIVATE to READ to PRECHARGE lpp4 464 448 432 400 mA Precharge power down current Slow exit IDD2P0 96 96 96 96 mA Precharge power down current Fast exit Ipp2P1 120 120 120 120 mA Precharge quiet standby current IDD2Q 176 176 176 176 mA Precharge standby current IDD2N 184 184 184 184 mA Precharge standby ODT current IDD2NT 288 272 256 232 mA Active power down current lpp3p 176 176 176 176 mA Active standby current lpp3n 296 280 264 248 mA Burst read operating current DD4R 880 800 704 600 mA Burst write operating current Ippaw 912 824 728 632 mA R
19. efresh current IppsB 1472 1456 1448 1432 mA Self refresh temperature current MAX Tc 85 C Ipp6 96 96 96 96 mA Self refresh temperature current SRT enabled MAX Tc 95 C IDD6ET 120 120 120 120 mA All banks interleaved read current lpbp7 1368 1304 1256 1024 mA Reset current lops 112 112 112 112 mA PDF 09005aef837d3ecf 1 4 jtf8c128_256_512x64az pdf Rev H 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2009 Micron Technology Inc All rights reserved Macron Table 16 DDR3 Ipp Specifications and Conditions 4GB Die Revision E 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Ipp Specifications Values are for the MT41J512M8 DDR3 SDRAM only and are computed from values specified in the 4Gb 512 Meg x 8 com ponent data sheet Parameter Symbol 1866 1600 1333 1066 Units Operating current 0 One bank ACTIVATE to PRECHARGE Ippo 496 440 376 352 mA Operating current 1 One bank ACTIVATE to READ to PRECHARGE lpp4 560 528 496 472 mA Precharge power down current Slow exit IDD2P0 144 144 144 144 mA Precharge power down current Fast exit Ipp2P1 296 256 224 208 mA Precharge quiet standby current IDD2Q 280 256 224 216 mA Precharge standby current IDD2N 280 256 232 224 mA Precharge standby ODT current IDD2NT 336 312 280 256 mA Active power down current lpp3p 328 304 280 256 mA
20. ly disabling hardware write protection For further information refer to Micron technical note TN 04 42 Memory Module Serial Presence Detect PDF 09005aef837d3ecf 8 Micron Technology Inc reserves the right to change products or specifications without notice jtf8c128_256_512x64az pdf Rev H 04 13 EN 2009 Micron Technology Inc All rights reserved IA icron 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the module This is a stress rating only and functional operation of the module at these or any other condi tions outside those indicated in each device s data sheet is not implied Exposure to ab solute maximum rating conditions for extended periods may adversely affect reliability Table 9 Absolute Maximum Ratings Symbol Parameter Min Max Units Vpp Vpp supply voltage relative to Vss 0 4 1 975 V Vin Vout Voltage on any pin relative to Vss 0 4 1 975 V Table 10 Operating Conditions Symbol Parameter Min Nom Max Units Notes Vbo Vbp supply voltage 1 425 1 5 1 575 V lyrr Termination reference current from Vr 600 600 mA Vit Termination reference voltage DC com 0 49 x Vpp 20mV 0 5 x Vpp 0 51 x Vpp 20mV V 1 mand address bus l Input leakage current Address 16 0 16 yA Any input OV lt Vin lt Vpp Vrer inputs RAS input OV lt Viy lt 0
21. nt and data characterization some times occur PDF 09005aef837d3ecf 1 7 Micron Technology Inc reserves the right to change products or specifications without notice jtf8c128_256_512x64az pdf Rev H 04 13 EN 2009 Micron Technology Inc All rights reserved
22. r industrial temperature module offerings Data Rate MT s Speed Industry ats amp s s RCD RP tRC Grade Nomenclature 13 11 10 CL 9 CL 8 CL 7 CL 6 CL 5 ns ns ns 1G9 PC3 14900 1866 1600 1333 1333 1066 1066 800 667 13 125 13 125 47 125 1G6 PC3 12800 1600 1333 1333 1066 1066 800 667 13 125 13 125 48 125 1G4 PC3 10600 1333 1333 1066 1066 800 667 13 125 13 125 49 125 1G1 PC3 8500 1066 1066 800 667 13 125 13 125 50 625 1G0 PC3 8500 1066 800 667 15 15 52 5 80B PC3 6400 800 667 15 15 52 5 PDF 09005aef837d3ecf jtf8c128_256_512x64az pdf Rev H 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2009 Micron Technology Inc All rights reserved Products and specifications discussed herein are subject to change by Micron without notice Macron 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Features Table 2 Addressing Parameter 1GB 2GB 4GB Refresh count 8K 8K 8K Row address 16K A 13 0 32K A 14 0 64K A 15 0 Device bank address 8 BA 2 0 8 BA 2 0 8 BA 2 0 Device configuration 1Gb 128 Meg x 8 2Gb 256 Meg x 8 4Gb 512 Meg x 8 Column address 1K A 9 0 1K A 9 0 1K A 9 0 Module rank address 1 SO 1 SO 1
23. ron Technology Inc All rights reserved Macron Table 13 DDR3 Ipp Specifications and Conditions 2GB Die Revision D 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM Ipp Specifications Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb 256 Meg x 8 com ponent data sheet Parameter Symbol 1866 1600 1333 1066 Units Operating current 0 One bank ACTIVATE to PRECHARGE Ippo 840 760 680 600 mA Operating current 1 One bank ACTIVATE to READ to PRECHARGE lpp1 880 840 800 760 mA Precharge power down current Slow exit IDD2P0 96 96 96 96 mA Precharge power down current Fast exit Ipp2P1 320 280 240 200 mA Precharge quiet standby current IDD2Q 360 320 280 240 mA Precharge standby current IDD2N 376 336 296 256 mA Precharge standby ODT current IDD2NT 440 400 360 320 mA Active power down current lpp3p 360 320 280 240 mA Active standby current lpp3n 400 360 320 280 mA Burst read operating current DD4R 1600 1440 1280 1120 mA Burst write operating current Ippaw 1640 1480 1320 1160 mA Refresh current lDD58 1760 1720 1600 1520 mA Self refresh temperature current MAX Tc 85 C Ipp6 96 96 96 96 mA Self refresh temperature current SRT enabled MAX Tc 95 C IDD6ET 120 120 120 120 mA All banks interleaved read current lpp7 3880 3480 3080 2680 mA Reset current lops 112 112 112 112 mA PDF
24. s are for the MT41J128M8 DDR3 SDRAM only and are computed from values specified in the 1Gb 128 Meg x 8 com ponent data sheet Parameter Symbol 1866 1600 1333 1066 Units Operating current 0 One bank ACTIVATE to PRECHARGE Ippo 560 560 520 480 mA Operating current 1 One bank ACTIVATE to READ to PRECHARGE Ipp1 720 720 680 640 mA Precharge power down current Slow exit Ipp2P0 96 96 96 96 mA Precharge power down current Fast exit Ipp2P1 280 240 240 200 mA Precharge quiet standby current Ipp29 360 320 280 280 mA Precharge standby current lpp2n 400 360 320 280 mA Precharge standby ODT current IDD2NT 480 440 400 360 mA Active power down current Ipp3P 280 280 240 240 mA Active standby current lop3n 400 360 320 320 mA Burst read operating current Ippar 1240 1120 1000 840 mA Burst write operating current lppaw 1280 1160 1000 880 mA Refresh current IppsB 1400 1360 1320 1280 mA Self refresh temperature current MAX Tc 85 C Ipp6 64 64 64 64 mA Self refresh temperature current SRT enabled MAX Tc 95 C IDDGET 80 80 80 80 mA All banks interleaved read current lpp7 2080 1960 1880 1560 mA Reset current Ipps 112 112 112 112 mA PDF 09005aef837d3ecf 1 1 jtf8c128_256_512x64az pdf Rev H 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2009 Mic
25. ster EMR When TDQS is enabled DM is disabled and TDQS and TDQS provide termination resistance otherwise TDQS are no function Err_Out Output Parity error output Parity error found on the command and address bus open drain EVENT Output Temperature event The EVENT pin is asserted by the temperature sensor when criti open drain cal temperature thresholds have been exceeded VDp Supply Power supply 1 5V 0 075V The component Vpp and Vppgo are connected to the module Vpp Vppspp Supply Temperature sensor SPD EEPROM power supply 3 0 3 6V VREFCA Supply Reference voltage Control command and address Vpp 2 VREFDQ Supply Reference voltage DQ DM Vp 2 Vss Supply Ground Vit Supply Termination voltage Used for control command and address Vpp 2 NC No connect These pins are not connected on the module NF No function These pins are connected within the module but provide no functional ity PDF 09005aef837d3ecf jtf8c128_256_512x64az pdf Rev H 04 13 EN 5 Micron Technology Inc reserves the right to change products or specifications without notice 2009 Micron Technology Inc All rights reserved I icron 1GB 2GB 4GB x64 SR 240 Pin DDR3 UDIMM DQ Map DQ Map Table 8 Component to Module DQ Map Component Component Reference Component Module Pin Reference Component Module Pin Number D

Micron 4GB DDR3

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