Micron 8GB DDR3
Contents
1. 10 ms Notes 1 Guaranteed by design and characterization not necessarily tested 2 To avoid spurious start and stop conditions a minimum delay is placed between the fall ing edge of SCL and the falling or rising edge of SDA 3 For a restart condition or following a WRITE cycle PDF 09005aef837cdd2d jtf16c256_512_1gx64az pdf Rev 04 13 EN 17 Micron Technology Inc reserves the right to change products or specifications without notice 2008 Micron Technology Inc All rights reserved In icron 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM Module Dimensions Module Dimensions Figure 3 240 Pin DDR3 UDIMM Front view 4 0 0 157 133 50 5 256 MAX N 133 20 5 244 E at ha 0 9 0 035 TYP 0 50 0 02 R Paj f ax r 0 75 0 03 R U1 U2 U3 U4 U5 U6 U7 U8 30 50 1 20 8x f 23 3 0 92 29 85 1 175 P 7 a A P 7 a TYP 2 50 0 098 D ug A 17 3 0 68 wn f B amp TYP 2 30 0 091 TYP C4 0 76 0 030 R j J t EU Gos 2 20 0 087 TYP gt 1 0 0 039 0 80 0 031 9 5 0 374 Se TYP TYP TYP 1 45 0 057 TYP __ _ 54 68 2 15 Pin 120 TYP 123 0 4 84 TYP 15 0 0 59 4X TYP E Back view 1 0 0 9 5G m 45 4X 5 1 0 2 TYP EN F i 3 1 0 122 2X2. 43 97 7 40 90 U7 0 58 114 1 61 228 2 63 234 3 57 109 4 62 233 5 60 227 6 59 115 7 56 108 PDF 09005aef837cdd2d 6 Micron Technology Inc reserves the right to change products or specifications without notice jtf16c256_512_1gx64az pdf Rev 04 13 EN 2008 Micron Technology Inc All rights reserved Macron 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM DQ Map Table 8 Component to Module DQ Map Continued Component Component Reference Component Module Pin Reference Component Module Pin Number DQ Module DQ Number Number DQ Module DQ Number U10 0 61 228 U11 0 53 219 1 58 114 1 50 105 2 57 109 2 49 100 3 63 234 3 55 225 4 56 108 4 48 99 5 59 115 5 51 106 6 60 227 6 52 218 7 62 233 7 54 224 U12 0 45 210 U13 0 37 201 1 42 96 1 34 87 2 41 91 2 33 82 3 47 216 3 39 207 4 40 90 4 32 81 5 43 97 5 35 88 6 44 209 6 36 200 7 46 215 7 38 206 U14 0 29 150 U15 0 21 141 1 26 36 1 18 27 2 25 31 2 17 22 3 31 156 3 23 147 4 24 30 4 16 21 5 27 37 5 19 28 6 28 149 6 20 140 7 30 155 7 22 146 U16 0 13 132 U17 0 5 123 1 10 18 1 2 9 2 9 13 2 1 4 3 15 138 3 7 129 4 8 12 4 0 3 5 11 19 5 3 10 6 12 131 6 4 122 7 14 137 7 6 128 PDF 09005aef837cdd2d jtf16c256_512_1gx64az pdf Rev 04 13 EN Micron Technology Inc
3. 8n bit wide one clock cycle data transfer at the inter nal DRAM core and eight corresponding n bit wide one half clock cycle data transfers at the I O pins DDR3 modules use two sets of differential signals DQS DQS to capture data and CK and CK to capture commands addresses and control signals Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals Fly By Topology DDR3 modules use faster clock speeds than earlier DDR technologies making signal quality more important than ever For improved signal quality the clock control com mand and address buses have been routed in a fly by topology where each clock con trol command and address pin on each DRAM is connected to a single trace and ter minated rather than a tree structure where the termination is off the module near the connector Inherent to fly by topology the timing skew between the clock and DQS sig nals can be easily accounted for by using the write leveling feature of DDR3 Serial Presence Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence detect The SPD data is stored ina 256 byte EEPROM The first 128 bytes are programmed by Micron to comply with JEDEC standard JC 45 Appendix X Serial Presence Detect SPD for DDR3 SDRAM Modules These bytes identify module specific timing parameters configuration infor mation and physical attributes The r
4. TYP T 3 u10 U11 U12 U13 U14 U15 U16 U17 C C 3 0 0 118 4x TYP fi 3 05 0 12 TYP C DAMENE anaana RE AMANOOOOARAAOAAAOOOOSAAAAAAOOOONRARORIOOONRRD t pin 240 k Pin 121 5 0 0 197 TYP 71 0 2 79 47 0 1 85 TYP TYP Notes 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted 2 The dimensional diagram is for reference only Refer to the JEDEC MO document for ad ditional design dimensions 8000 S Federal Way P O Box 6 Boise ID 83707 0006 Tel 208 368 3900 www micron com productsupport Customer Comment Line 800 932 4992 Micron and the Micron logo are trademarks of Micron Technology Inc All other trademarks are the property of their respective owners This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein Although considered final these specifications are subject to change as further product development and data characterization some times occur PDF 09005aef837cdd2d 1 8 Micron Technology Inc reserves the right to change products or specifications without notice jtf16c256_512_1gx64az pdf Rev 04 13 EN 2008 Micron Technology Inc All rights reserved
5. 1 575 V lvTT Termination reference current from Vrt 600 600 mA Vet Termination reference voltage command address 0 483 x Vpp 0 5xVpp 0 517 x Vpp V 1 bus l Input leakage current Address inputs 32 0 32 yA Any input OV lt Vin lt Vpop RAS CAS Veer input OV lt Viy lt 0 95V WE BA All other pins not under test 0V sz CKE ODT 16 0 16 CK CK DM 4 loz Output leakage current DQ DQS DQS 10 0 10 yA OV lt Vout Vopaq DQs and ODT are disabled IVREF VREF leakage current Vref valid VREF level 16 0 16 yA Ta Module ambient operating tempera Commercial 0 70 C 2 3 ture Industrial 40 85 C Te DDR3 SDRAM component case oper Commercial 0 95 C 2 3 4 ating temperature Industrial 40 95 C Notes 1 Vy termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins 2 Ta and Tc are simultaneous requirements 3 For further information refer to technical note TN 00 08 Thermal Applications available on Micron s Web site 4 The refresh rate is required to double when 85 C lt Tc lt 95 C PDF 09005aef837cdd2d 1 0 Micron Technology Inc reserves the right to change products or specifications without notice jtf16c256_512_1gx64az pdf Rev 04 13 EN 2008 Micron Technology Inc All rights reserved 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM DRAM Operating Con
6. 1 Gig x 64 10 6 GB s 1 5ns 1333 MT s 9 9 9 MT16JTF1G64A I Z 1G1__ 8GB 1 Gig x 64 8 5 GB s 1 87ns 1066 MT s 7 7 7 Notes 1 Data sheets for the base device parts can be found on Micron s Web site 2 All part numbers end with a two place code not shown designating component and PCB revisions Consult factory for current revision codes Example MT16JTF51264AZ 1G6K1 PDF 09005aef837cdd2d jtf16c256_512_1gx64az pdf Rev 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2008 Micron Technology Inc All rights reserved Macron Pin Assignments Table 6 Pin Assignments 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM Pin Assignments 2 Pin 172 is NC for 2GB A14 for 4GB and 8GB 240 Pin UDIMM Front 240 Pin UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 Vrerpg 31 DQ25 91 DQ41 121 Vs 151 Vs 181 Al 211 Vss 2 Vss 32 Vos 92 Vss 122 DQ4 152 DM3 182 Vpp 212 DM5 3 DQO 33 DQS3 93 DQS5 123 DQ5 153 NC 183 Vopp 213 NC 4 pai 34 DQS3 94 DQS5 124 Vss 154 Vss 184 CKO 214 Vss 5 Vss 351 Veg 95 Vss 125 DMO 155 DQ30 185 CKO 215 DQ46 6 DQSO 36 DQ26 96 DQ42 126 NC 156 DQ31
7. 186 VDD 216 DQ47 7 DQSO 37 DQ27 97 DQ43 1127 Vss 157 Vss 1187 NC 217 Vss 8 Vss 38 Vss 98 Vss 128 DQ6 158 NC 188 AO 218 DQ52 9 DQ2 39 NC 99 DQ48 129 DQ7 159 NC 189 Vpp 219 DQ53 10 DQ3 40 NC 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss 11 Vs 41 Vss 101 Vss 131 DQ12 161 NC 191 Vpp 221 DM6 12 DQ8 42 NC 102 DQS6 132 DQ13 162 NC 192 RAS 222 NC 13 DQ9 43 NC 103 DQS6 133 Vss 163 Vss 193 SO 223 Vss 14 Vs 144 Vss 104 Vss 134 DM1 164 NC 194 Vpp 224 DQ54 15 DQS1 45 NC 105 DQ50 135 NC 165 NC 195 ODTO 225 DQ55 16 DQS1 46 NC 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss 17 Vs 47 Vss 107 Vss 137 DQ14 167 NC 197 Vpp 227 DQ60 18 DQ10 48 NC 108 DQ56 138 DQ15 168 RESET 198 NC 228 DQ61 19 DQ11 49 NC 109 DQ57 139 Vss 169 CKE1 199 Vss 1229 Veg 20 Vss 50 CKEO 110 Vss 140 DQ20 170 Vpp 200 DQ36 230 DM7 21 DQ16 51 Vpp 111 DQS7 141 DQ21 171 NC A15 201 DQ37 231 NC 22 DQ17 52 BA2 112 DQS7 142 Vss 172 NC A142 202 Vss 232 Vg 23 Vss 53 NC 113 Vss 143 DM2 173 Vopp 203 DM4 233 DQ62 24 DQS2 54 Vpp 114 DQ58 144 NC 174 A12 204 NC 234 DQ63 25 DQS2 55 A11 115 DQ59 145 Ves 175 AQ 205 Veg 1235 Vss 26 Vss 56 A7 116 Vss 146 DQ22 176 VDD 206 DQ38 236 Vppspp 27 DQ18 57 VbDp 117 SAO 147 DQ23 177 A8 207 DQ39 237 SA1 28 DQ19 58 A5 118 SCL 148 Vss 178 A6 208 Vss 238 SDA 29 Vss 59 A4 119 SA2 149 DQ28 179 VDpp 209 DQ
8. 2008 Micron Technology Inc All rights reserved Macron Serial Presence Detect EEPROM For the latest SPD data refer to Micron s SPD page www micron com SPD 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM Serial Presence Detect EEPROM Table 17 Serial Presence Detect EEPROM DC Operating Conditions All voltages referenced to Vppspp Parameter Condition Symbol Min Max Units Supply voltage Vppspp 3 0 3 6 V Input low voltage Logic 0 All inputs Vil 0 45 Vppspp X 0 3 V Input high voltage Logic 1 All inputs Vin Vppspp X 0 7 Vppspp 1 0 V Output low voltage lout 3MA VoL 0 4 V Input leakage current Vin GND to Vpp lu 0 1 2 0 yA Output leakage current Vout GND to Vpp lLo 0 05 2 0 pA Table 18 Serial Presence Detect EEPROM AC Operating Conditions Parameter Condition Symbol Min Max Units Notes Clock frequency tSCL 10 400 kHz Clock pulse width HIGH time THIGH 0 6 us Clock pulse width LOW time tLOW 1 3 us SDA rise time tR 300 us 1 SDA fall time tF 20 300 ns 1 Data in setup time tSU DAT 100 ns Data in hold time tHD DI 0 us Data out hold time tHD DAT 200 900 ns Data out access time from SCL LOW tAA DAT 0 2 0 9 us Start condition setup time tSU STA 0 6 us Start condition hold time tHD STA 0 6 us Stop condition setup time tSU STO 0 6 us Time the bus must be free before a new transition can tBUF 1 3 us start WRITE time tw
9. 224 224 mA Notes 1 One module rank in the active Ipp the other rank in Ipp2po slow exit 2 All ranks in this Ipp condition PDF 09005aef837cdd2d 1 2 jtf16c256_512_1gx64az pdf Rev 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2008 Micron Technology Inc All rights reserved Macron Table 13 DDR3 Ipp Specifications and Conditions 4GB Die Revision M 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM lbp Specifications Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb 256 Meg x 8 com ponent data sheet Notes 1 One module rank in the active lpp the other rank in Ipp2po slow exit 2 All ranks in this Ipp condition Parameter Symbol 1866 1600 1333 1066 Units Operating current 0 One bank ACTIVATE to PRECHARGE Ippo 696 656 616 576 mA Operating current 1 One bank ACTIVATE to READ to PRECHARGE Ipp1 776 736 696 656 mA Precharge power down current Slow exit IDD2P02 192 192 192 192 mA Precharge power down current Fast exit lDD2P12 672 592 512 432 mA Precharge quiet standby current lDD2Q 720 640 560 480 mA Precharge standby current Ipp2Nn2 768 688 608 528 mA Precharge standby ODT current Ipp2nT2 496 456 416 376 mA Active power down current Ipp3p2 880 800 720 640 mA Active standby current Ipp3n2 960 880 800 720 mA Burst read operating current Ip
10. 44 239 Vss 30 DQ24 60 VDD 120 Vr 150 DQ29 180 A3 210 DQ45 240 Vit Notes 1 Pin 171 is NC for 2GB and 4GB A15 for 8GB PDF 09005aef837cdd2d jtf16c256_512_1gx64az pdf Rev 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2008 Micron Technology Inc All rights reserved Macron Pin Descriptions 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM Pin Descriptions The pin description table below is a comprehensive list of all possible pins for all DDR3 modules All pins listed may not be supported on this module See Pin Assignments for information specific to this module Table 7 Pin Descriptions Symbol Type Description Ax Input Address inputs Provide the row address for ACTIVE commands and the column ad dress and auto precharge bit A10 for READ WRITE commands to select one location out of the memory array in the respective bank A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank A10 LOW bank selected by BAx or all banks A10 HIGH The address inputs also provide the op code during a LOAD MODE command See the Pin Assignments Table for density specific addressing information BAx Input Bank address inputs Define the device bank to which an ACTIVE READ WRITE or PRECHARGE command is being applied BA define which mode register MRO MR1 MR2 or MR3 is loaded during the LOAD MODE co
11. CSF DOS DOSH DM CSH DQS DOSH Vbo gt DDR3 SDRAM DQ24 M DQ DQ DQ56 WDQ DQ V Address command DQ25 Ww DQ DQ DQ57 Ww DQ DQ T alee DQ26 DQ DO DQ58 DQ DO and control termination DQ27 Ww DQ U4 DQ U14 Das9 Ww DQ U8 DQ U10 AA L DDR3 SDRAM DQ28 v DQ DQ DQ60 v DQ DQ DQ29 W DQ DQ DQ61 W DQ DQ VREFDQ t gt DDR3 SDRAM DQ30 v DQ DQ DQ62 v DQ DQ DQ31 mv DQ DQ DQ63 wr DQ DQ Vs ___ _1 _1 ppr3 spRAM wiz zamma mza zama Vss Vss Vss Vss Note 1 The ZQ ball on each DDR3 component is connected to an external 2400 resistor that is tied to ground Used for the calibration of the component s on die termination and out put driver PDF 09005aef837cdd2d jtf16c256_512_1gx64az pdf Rev 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2008 Micron Technology Inc All rights reserved In icron 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM General Description General Description DDR3 SDRAM modules are high speed CMOS dynamic random access memory mod ules that use internally configured 8 bank DDR3 SDRAM devices DDR3 SDRAM mod ules use DDR architecture to achieve high speed operation DDR3 architecture is essen tially an 8n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I O pins A single read or write access for the DDR3 SDRAM mod ule effectively consists of a single
12. IA icron 2GB 4GB 8GB x64 DR 240 Pin pens ven DDR3 SDRAM UDIMM MT16JTF25664AZ 2GB MT16JTF51264AZ 4GB MT16JTF1G64AZ 8GB Features Figure 1 240 Pin UDIMM MO 269 R C B Module height 30 0mm 1 181in DDR3 functionality and operations supported as per component data sheet 240 pin unbuffered dual in line memory module UDIMM Fast data transfer rates PC3 14900 PC3 12800 PC3 10600 PC3 8500 or PC3 6400 2GB 256 Meg x 64 4GB 512 Meg x 64 8GB 1 Gigx Options Marking 64 e Operating temperature E Commercial 0 C lt T lt 70 C None Vons Wong bev 20 pV Industrial 40 C lt T4 lt 85 C I s Vppspp 3 0 3 6V Ps Package e Reset pin for improved system stability 240 pin DIMM halogen free Z e Nominal and dynamic on die termination ODT for e Frequency CAS latency data strobe and mask signals 1 07ns CL 13 DDR3 1866 1G9 e Dual rank 1 25ns CL 11 DDR3 1600 1G6 e 8 internal device banks for concurrent operation 1 5ns CL 9 DDR3 1333 1G4 1 87ns CL 7 DDR3 1066 1G1 Fixed burst length BL of 8 and burst chop BC of 4 via the mode register Note 1 Contact Micron for industrial temperature module offerings Adjustable data output drive strength Serial presence detect SPD EEPROM Gold edge contacts Halogen free Addresses are mirrored for second rank Fly by topolo
13. IVATE to PRECHARGE Ippo 840 760 680 640 mA Operating current 1 One bank ACTIVATE to READ to PRECHARGE Ipp1 896 856 816 776 mA Precharge power down current Slow exit IDD2P02 320 320 320 320 mA Precharge power down current Fast exit lDD2P12 672 592 512 480 mA Precharge quiet standby current lpp297 832 752 672 624 mA Precharge standby current Ipp2Nn2 880 800 720 672 mA Precharge standby ODT current Ipp2nT2 600 560 520 480 mA Active power down current Ipp3p2 1088 1008 928 848 mA Active standby current lboan 1072 992 912 832 mA Burst read operating current Ippar 1816 1656 1496 1336 mA Burst write operating current Ippaw 1640 1480 1320 1160 mA Refresh current lbosg 2000 1920 1840 1800 mA Self refresh temperature current MAX Tc 85 C Ipp62 352 352 352 352 mA Self refresh temperature current SRT enabled MAX Tc 95 C IDD6ET 448 448 448 448 mA All banks interleaved read current Ipp7 2800 2480 2160 1840 mA Reset current lpps 352 352 352 352 mA PDF 09005aef837cdd2d 1 5 jtf16c256_512_1gx64az pdf Rev 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2008 Micron Technology Inc All rights reserved Macron Table 16 DDR3 Ipp Specifications and Conditions 8GB Die Revisions E and J 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM lbp Specifications Values are for the MT41J512M8 DDR3 SDRAM only and are computed from values specifie
14. K A 9 0 1K A 9 0 1K A 9 0 Module rank address 2 S 1 0 2 S 1 0 2 S 1 0 Table 3 Part Numbers and Timing Parameters 2GB Base device MT41J128M8 1Gb DDR3 SDRAM Module Module Band Memory Clock Da CL RCD RP Part Number Density Configuration width ta Rate Clock Cycles MT16JTF25664A I Z 1G9__ 2GB 256 Meg x 64 14 9 GB s 1 07ns 1866 MT s 13 13 13 MT16JTF25664A 1 Z 1G6__ 2GB 256 Meg x 64 12 8 GB s 1 25ns 1600 MT s 11 11 11 MT16JTF25664A I Z 1G4__ 2GB 256 Meg x 64 10 6 GB s 1 5ns 1333 MT s 9 9 9 MT16JTF25664A I Z 1G1__ 2GB 256 Meg x 64 8 5 GB s 1 87ns 1066 MT s 7 7 7 Table 4 Part Numbers and Timing Parameters 4GB Base device MT41J256MB8 2Gb DDR3 SDRAM Module Module Band Memory Clock Da CL RCD RP Part Number Density Configuration width ta Rate Clock Cycles MT16JTF51264A I Z 1G9__ 4GB 512 Meg x 64 14 9 GB s 1 07ns 1866 MT s 13 13 13 MT16JTF51264A I Z 1G6__ 4GB 512 Meg x 64 12 8 GB s 1 25ns 1600 MT s 11 11 11 MT16JTF51264A 1 Z 1G4__ 4GB 512 Meg x 64 10 6 GB s 1 5ns 1333 MT s 9 9 9 MT16JTF51264A I Z 1G1__ 4GB 512 Meg x 64 8 5 GB s 1 87ns 1066 MT s 7 7 7 Table 5 Part Numbers and Timing Parameters 8GB Base device MT41J512M8 4Gb DDR3 SDRAM Module Module Memory Clock CL RCD RP Part Number Density Configuration Bandwidth Data Rate Clock Cycles MT16JTF1G64A I Z 1G9__ 8GB 1 Gig x 64 14 9 GB s 1 07ns 1866 MT s 13 13 13 MT16JTF1G64A I Z 1G6__ 8GB 1 Gig x 64 12 8 GB s 1 25ns 1600 MT s 11 11 11 MT16JTF1G64A I Z 1G4__ 8GB
15. Q ODT1 ODT1 Rank 1 DQ5 Wr DQ DQ DQ37 v DQ DQ RESET gt RESET DDR3 SDRAM DQ6 W DQ DQ DQ38 DQ DQ DQ7 W DQ DQ DQ39 DQ DQ Tap e Zamm umR zamma y a pasi ss A z Vss DQS5 Ss We r Vss Command address and clock line terminations DQS1 WW G DQS5 DM1 DM5 ws on DM CS DQS DOSH DM CSH DOS DOSH DM CSF DOS DOS DM CS DOS DOSHI CKE 1 0 A 15 14 0 RAS CAS WE v pa w4 pQ PQ DAI W DQ DQ s 1 0 ODT 1 0 BA 2 0 it a9 wH DQ pDo Da4 w DQ DQ DQ10 Ww DQ po DQ42 WDQ DQ DDR3 DQ11 w DQ U2 pa U16 DQ43 W DQ U6 DQ U12 SDRAM DQ12 DQ pDo DQ44 DQ DQ DQ13 w DQ Do DQ45 w DQ DQ oe W E Vbp DQ14 w DQ pa DQ46 w DQ DQ 11 0 Ws dais wr DQ po DQ47 DQ DQ rwW 1za zam mza zam u9 Vss Vss bose Vss Vss DQS2 Q W scL gt SPD EEPROM sbA DQS2 DQS6 WP AO A1 A2 DM2 pms A S T DM CS DQS DOSH DM CSH DOS DOSH DM CS DOS DOSH DM CS DQS DOSH Vss SAO SA1 SA2 DQ16 v DQ DQ Daas v Do DQ DQ17 M DQ DQ DQ49 M DQ DQ Rank 0 U1 U8 DQ18 M DQ DQ DQ50 M DQ DQ Rank 1 U10 U17 DQ19 Ww DQ U3 DQ U15 DQ51 wDQ U7 DQ U11 DQ20 y DQ DQ DQ52 M DQ DQ DQ21 wW DQ DQ DQ53 Ww DQ DQ Prin gt Rank o DQ22 Ww DQ DQ DQ54 v DQ DQ OF DQ23 DQ DQ Da55 DQ DQ aa W129 zaw mza zawa an gt Rank 1 DQS3 SS 4p s 5 pas7 w z j DQS3 w DQS7 DM3 WA A DM ne Vons SPD EEPROM DM CS DQS DOSH DM CSH DOS DOSH DM
16. Technology Inc All rights reserved Macron lbp Specifications Table 12 DDR3 Ipp Specifications and Conditions 2GB Die Revision G 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM lbp Specifications Values are for the MT41J128M8 DDR3 SDRAM only and are computed from values specified in the 1Gb 128 Meg x 8 com ponent data sheet Parameter Symbol 1866 1600 1333 1066 Units Operating current 0 One bank ACTIVATE to PRECHARGE Ippo 656 656 616 576 mA Operating current 1 One bank ACTIVATE to READ to PRECHARGE Ipp1 816 816 776 736 mA Precharge power down current Slow exit IDD2P02 192 192 192 192 mA Precharge power down current Fast exit lDD2P12 560 480 480 400 mA Precharge quiet standby current Ipp2Q7 720 640 560 560 mA Precharge standby current Ipp2Nn2 800 720 640 560 mA Precharge standby ODT current Ipp2nt2 576 536 496 456 mA Active power down current Ipp3p2 560 560 480 480 mA Active standby current Ipp3n2 800 720 640 640 mA Burst read operating current Ippar 1336 1216 1096 936 mA Burst write operating current Ippaw 1376 1256 1096 976 mA Refresh current IppsB 1496 1456 1416 1376 mA Self refresh temperature current MAX Tc 85 C lpp62 128 128 128 128 mA Self refresh temperature current SRT enabled MAX Tc 95 C Ipp6ET2 160 160 160 160 mA All banks interleaved read current Ipp7 2160 2056 1976 1656 mA Reset current Ipps 224 224
17. d in the 4Gb 512 Meg x 8 com ponent data sheet Notes 1 One module rank in the active lpp the other rank in Ipp2po slow exit 2 All ranks in this Ipp condition Parameter Symbol 1866 1600 1333 1066 Units Operating current 0 One bank ACTIVATE to PRECHARGE Ippo 640 584 520 496 mA Operating current 1 One bank ACTIVATE to READ to PRECHARGE Ipp1 704 672 540 616 mA Precharge power down current Slow exit IDD2P02 288 288 288 288 mA Precharge power down current Fast exit lDD2P12 592 512 448 416 mA Precharge quiet standby current lDD2Q 560 512 448 416 mA Precharge standby current Ipp2Nn2 560 512 464 448 mA Precharge standby ODT current Ipp2nT2 480 456 424 400 mA Active power down current lpp3p2 656 608 560 512 mA Active standby current Ipp3n2 656 608 560 512 mA Burst read operating current Ippar 1536 1400 1264 1128 mA Burst write operating current Ippaw 1272 1144 1024 904 mA Refresh current Ipps 2080 2024 1968 1936 mA Self refresh temperature current MAX Tc 85 C Ipp62 320 320 320 320 mA Self refresh temperature current SRT enabled MAX Tc 95 C lpp6ET 400 400 400 400 mA All banks interleaved read current Ipp7 2152 1904 1664 1424 mA Reset current lpps2 320 320 320 320 mA PDF 09005aef837cdd2d 1 6 jtf16c256_512_1gx64az pdf Rev 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice
18. ditions Macron DRAM Operating Conditions Recommended AC operating conditions are given in the DDR3 component data sheets Component specifications are available on Micron s web site Module speed grades cor relate with component speed grades as shown below Table 11 Module and Component Speed Grades DDR3 components may exceed the listed module speed grades module may not be available in all listed speed grades Module Speed Grade Component Speed Grade 2G1 093 1G9 107 1G6 125 1G4 15E 1G1 187E 1G0 187 80C 25E 80B 25 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully de signed terminations controlled board impedances routing topologies trace length matching and decoupling However good signal integrity starts at the system level Micron encourages designers to simulate the signal characteristics of the system s memory bus to ensure adequate signal integrity of the entire memory system Power Operating voltages are specified at the DRAM not at the edge connector of the module Designers must account for any system voltage drops at anticipated power levels to en sure the required supply voltage is maintained PDF 09005aef837cdd2d 1 1 Micron Technology Inc reserves the right to change products or specifications without notice jtf16c256_512_1gx64az pdf Rev 04 13 EN 2008 Micron
19. emaining 128 bytes of storage are available for use by the customer System READ WRITE operations between the master system logic and the slave EEPROM device occur via a standard I C bus using the DIMM s SCL clock SDA data and SA address pins Write protect WP is connected to V ss per manently disabling hardware write protection For further information refer to Micron technical note TN 04 42 Memory Module Serial Presence Detect PDF 09005aef837cdd2d 9 Micron Technology Inc reserves the right to change products or specifications without notice jtf16c256_512_1gx64az pdf Rev 04 13 EN 2008 Micron Technology Inc All rights reserved Ia icron 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the module This is a stress rating only and functional operation of the module at these or any other condi tions outside those indicated in each device s data sheet is not implied Exposure to ab solute maximum rating conditions for extended periods may adversely affect reliability Table 9 Absolute Maximum Ratings Symbol Parameter Min Max Units Vpp Vpp supply voltage relative to Vss 0 4 1 975 V Vin Vout Voltage on any pin relative to Vss 0 4 1 975 V Table 10 Operating Conditions Symbol Parameter Min Nom Max Units Notes VDp Vpp supply voltage 1 425 1 5
20. emperature sensor SPD EEPROM ad dress range on the I2C bus SCL Input Serial clock for temperature sensor SPD EEPROM Used to synchronize communi cation to and from the temperature sensor SPD EEPROM on the IC bus CBx O Check bits Used for system error detection and correction DQx 1 0 Data input output Bidirectional data bus DQSx 1 0 Data strobe Differential data strobes Output with read data edge aligned with DQSx read data input with write data center aligned with write data PDF 09005aef837cdd2d jtf16c256_512_1gx64az pdf Rev 04 13 EN 4 Micron Technology Inc reserves the right to change products or specifications without notice 2008 Micron Technology Inc All rights reserved Macron 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM Pin Descriptions Table 7 Pin Descriptions Continued Symbol Type Description SDA 1 0 Serial data Used to transfer addresses and data into and out of the temperature sen sor SPD EEPROM on the I C bus TDQSx Output Redundant data strobe x8 devices only TDQS is enabled disabled via the LOAD TDQSx MODE command to the extended mode register EMR When TDQS is enabled DM is disabled and TDQS and TDQS provide termination resistance otherwise TDQS are no function Err_Out Output Parity error output Parity error found on the command and address bus open drain EVENT Output Temperature event The EVENT pin is asser
21. ge quiet standby current Ipp297 352 352 352 352 mA Precharge standby current Ipp2Nn2 368 368 368 368 mA Precharge standby ODT current Ipp2nT2 384 368 352 328 mA Active power down current Ipp3p2 352 352 352 352 mA Active standby current Ipp3n2 592 560 528 496 mA Burst read operating current Ippar 976 896 800 696 mA Burst write operating current Ippaw 1008 920 824 728 mA Refresh current Ipps 1568 1552 1544 1528 mA Self refresh temperature current MAX Tc 85 C Ipp62 192 192 192 192 mA Self refresh temperature current SRT enabled MAX Tc 95 C IDD6ET 216 216 216 216 mA All banks interleaved read current Ipp7 1464 1400 1352 1120 mA Reset current lpps 208 208 208 208 mA PDF 09005aef837cdd2d 1 4 jtf16c256_512_1gx64az pdf Rev 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2008 Micron Technology Inc All rights reserved Macron Table 15 DDR3 Ipp Specifications and Conditions 8GB Die Revision D 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM lbp Specifications Values are for the MT41J512M8 DDR3 SDRAM only and are computed from values specified in the 4Gb 512 Meg x 8 com ponent data sheet Notes 1 One module rank in the active lpp the other rank in Ipp2po slow exit 2 All ranks in this Ipp condition Parameter Symbol 1866 1600 1333 1066 Units Operating current 0 One bank ACT
22. gy Terminated control command and address bus Table 1 Key Timing Parameters Data Rate MT s Speed Industry CL CL CL RCD tRP tRC Grade Nomenclature 13 11 10 CL 9 CL 8 CL 7 CL 6 CL 5 ns ns ns 1G9 PC3 14900 1866 1600 1333 1333 1066 1066 800 667 13 125 13 125 47 125 1G6 PC3 12800 1600 1333 1333 1066 1066 800 667 13 125 13 125 48 125 1G4 PC3 10600 1333 1333 1066 1066 800 667 13 125 13 125 49 125 1G1 PC3 8500 1066 1066 800 667 13 125 13 125 50 625 1G0 PC3 8500 1066 800 667 15 15 52 5 80B PC3 6400 800 667 15 15 52 5 PDF 09005aef837cdd2d 1 Micron Technology Inc reserves the right to change products or specifications without notice jtf16c256_512_1gx64az pdf Rev 04 13 EN 2008 Micron Technology Inc All rights reserved Products and specifications discussed herein are subject to change by Micron without notice Macron 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM Features Table 2 Addressing Parameter 2GB 4GB 8GB Refresh count 8K 8K 8K Row address 16K A 13 0 32K A 14 0 64K A 15 0 Device bank address 8 BA 2 0 8 BA 2 0 8 BA 2 0 Device page size per bank 1KB 1KB 1KB Device configuration 1Gb 128 Meg x 8 2Gb 256 Meg x 8 4Gb 512 Meg x 8 Column address 1
23. mmand CKx Input Clock Differential clock inputs All control command and address input signals are CKx sampled on the crossing of the positive edge of CK and the negative edge of CK CKEx Input Clock enable Enables registered HIGH and disables registered LOW internal circui try and clocks on the DRAM DMx Input Data mask x8 devices only DM is an input mask signal for write data Input data is masked when DM is sampled HIGH along with that input data during a write ac cess Although DM pins are input only DM loading is designed to match that of the DQ and DQS pins ODTx Input On die termination Enables registered HIGH and disables registered LOW termi nation resistance internal to the DDR3 SDRAM When enabled in normal operation ODT is only applied to the following pins DQ DQS DQS DM and CB The ODT input will be ignored if disabled via the LOAD MODE command Par_In Input Parity input Parity bit for Ax RAS CAS and WE RAS CAS WE Input Command inputs RAS CAS and WE along with S define the command being entered RESET Input Reset RESET is an active LOW asychronous input that is connected to each DRAM LVCMOS and the registering clock driver After RESET goes HIGH the DRAM must be reinitial ized as though a normal power up was executed Sx Input Chip select Enables registered LOW and disables registered HIGH the command decoder SAX Input Serial address inputs Used to configure the t
24. par 1464 1344 1224 1136 mA Burst write operating current Ippaw 1376 1256 1136 1016 mA Refresh current lppsp 1696 1656 1616 1576 mA Self refresh temperature current MAX Tc 85 C Ipp62 192 192 192 192 mA Self refresh temperature current SRT enabled MAX Tc 95 C lpp6ET2 216 216 216 216 mA All banks interleaved read current Ipp7 2136 2016 1896 1776 mA Reset current lpps 208 208 208 208 mA PDF 09005aef837cdd2d 1 3 jtf16c256_512_1gx64az pdf Rev 04 13 EN Micron Technology Inc reserves the right to change products or specifications without notice 2008 Micron Technology Inc All rights reserved Macron Table 14 DDR3 Ipp Specifications and Conditions 4GB Die Revision K 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM lbp Specifications Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb 256 Meg x 8 com ponent data sheet Notes 1 One module rank in the active lpp the other rank in Ipp2po slow exit 2 All ranks in this Ipp condition Parameter Symbol 1866 1600 1333 1066 Units Operating current 0 One bank ACTIVATE to PRECHARGE Ippo 440 432 424 408 mA Operating current 1 One bank ACTIVATE to READ to PRECHARGE Ipp1 560 544 528 496 mA Precharge power down current Slow exit Ipp2P02 192 192 192 192 mA Precharge power down current Fast exit Ipp2p12 240 240 240 240 mA Prechar
25. reserves the right to change products or specifications without notice 2008 Micron Technology Inc All rights reserved S1 Macron Functional Block Diagram Figure 2 Functional Block Diagram 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM Functional Block Diagram So DQSO M Dasa a BA 2 0 BA 2 0 DDR3 SDRAM DQso DQS4 w m A 15 14 0 gt A 15 14 13 0 DDR3 SDRAM DMO DMA RAS gt RAS DDR3 SDRAM CAS CAS DDR3 SDRAM DM CS DQS DOSH DM CSH DOS DOSH DM CS DOS DOSH DM CS DOS DOSH Wen WEE DORI SDRAM DQ0 W DQ DQ DQ32 W DQ DQ CKEO gt CKEO Rank 0 Dai Ww DQ DQ DQ33 Ww DQ DQ areal ts BO B34 velba i CKE1 CKE1 Rank 1 DQ3 WY DQ u1 DQ U17 DQ35 w pDQ U5 DQ U13 ODTO ODTO Rank 0 DQ4 Ww DQ DQ DQ36 W DQ D
26. ted by the temperature sensor when criti open drain cal temperature thresholds have been exceeded VDp Supply Power supply 1 5V 0 075V The component Vpp and Vppgo are connected to the module Vpp Vppspp Supply Temperature sensor SPD EEPROM power supply 3 0 3 6V VREFCA Supply Reference voltage Control command and address Vpp 2 VREFDQ Supply Reference voltage DQ DM Vp 2 Vss Supply Ground Vit Supply Termination voltage Used for control command and address Vpp 2 NC No connect These pins are not connected on the module NF No function These pins are connected within the module but provide no functional ity PDF 09005aef837cdd2d jtf16c256_512_1gx64az pdf Rev 04 13 EN 5 Micron Technology Inc reserves the right to change products or specifications without notice 2008 Micron Technology Inc All rights reserved I icron 2GB 4GB 8GB x64 DR 240 Pin DDR3 UDIMM DQ Map DQ Map Table 8 Component to Module DQ Map Component Component Reference Component Module Pin Reference Component Module Pin Number DQ Module DQ Number Number DQ Module DQ Number U1 0 10 18 1 13 132 2 15 138 3 9 13 4 14 137 5 12 131 6 11 19 7 8 12 U3 0 26 36 1 29 150 2 31 156 3 25 31 4 30 155 5 28 149 6 27 37 7 24 30 U5 0 42 96 1 45 210 2 47 216 3 41 91 4 46 215 5 44 209 6
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