Elixir 2GB DDR2-800 PC2-6400 SO-DIMM
Contents
1. elixir Note All dimensions are typical with tolerances of 0 15 unless otherwise stated Units Millimeters Inches Note Device position and scale are only for reference REV 1 0 07 2010 17 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HG5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Cel DS Unbuffered DDR2 SO DIMM elixir Package Dimensions 2GB 2 Ranks 128M x8 DDR2 SDRAMs FRONT 67 60 P 63 60 tt gt e S vt x A TT o m S o s 8 E S EET N 2X 0 1 80 TRY 1 ak 199 218 Q1 405 4 Detail A N Detail B f 4 20 E 47 40 VEM 2 70 2 45 B2. SSTL SSTL SSTL SSTL SSTL Supply Input SSTL SSTL SSTL Supply SSTL Input Supply Polarity Positive Edge Negative Edge Active High Active Low Active Low Active High Active High Negative and Positive Edge Active High Function The positive line of the differential pair of system clock inputs which drives the input to the on DIMM PLL All the DDR2 SDRAM address and control inputs are sampled on the rising edge of their associated clocks The negative line of the differential pair of system clock inputs which drives the input to the on DIMM PLL Activates the SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode Enables the associated SDRAM command decoder when low and disables the command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue When sampled at the positive rising edge of the clock RAS CAS WE define the operation to be executed by the SDRAM Reference voltage for SSTL 18 inputs On Die Termination control signals Selects which SDRAM bank is to be active During a Bank Activate command cycle AO A12 A13 define the row address RAO RA12 RA13 when sampled at the rising clock edge A13 applies on 2GB SODIMM only During a Read or Write command cycle A0 A9 defines the col
3. N DM DQO W 1 00 DQ32 M 00 pai N VO1 DQ33 N VO1 Daz N 02 DQ34 N 102 DQ N 4 103 D0 D8 DQ35 N 103 D4 D12 DQ4 N 104 DQ36 N WVO4 DQ5 N WwO5 DQ37 N WVO5 DQe N 1 06 DQ38 N WVO6 DQ7 N 4 VO7 DQ39 N VO7 DOS N Das CSO CKEO ODTO CS1 CKEi ODT1 Dass N Das CSO CKED ODTO CS1 CKE1 ODT1 Dasi M DQS Dass N DQs DM N DM DM5 N DM Dos N 100 DQ40 M WVOO0 Dag N WVO1 DQ41 N VO1 DQ10 N 102 DQ42 N WVO2 DQii N 103 D1 D9 DQ43 N VOS D5 D 13 DQ12 N 104 DO44 N VO4 DQ13 M 1 05 DQ45 A 05 DQ14 N 106 DQ46 N VO6 DQ15 M 1 07 DQ47 M 1 07 Das N Das CSO CKEO ODTO CS1 CKE1 ODTI Dass N Das CSO CKEO ODTO CS1 CKE1 ODT1 DQR N DQS DQS6 M DQS DM2 M DM DM6 M DM DQ16 N VOO DQ48 N WVOO0 DQ17 M 101 DQ49 M 101 DQ18 M WVO2 DQ50 M V O2 DQ19 N WVOS3 D2 D10 DQ51 N VOS D6 D 14 DQ20 VO4 DQ52 N WVO4 DQ21 M VO5 DQ53 N WVO5 DQ22 N VO6 DQ54 N WVoe DQ23 N VO7 DQ55 N VO7 Dass N Das CS0 CKEO ODTO CSi CKEi ODTI DOS AV Das CSO CKEO ODTO CSi CKE ODTI DAS N DAQS DQS7 M bDGS DM3 N DM DM7 N DM DQ24 N WOO pase N 100 DQ25 N VO1 DQ57 N VO1 DQ 6 N 02 pass N 102 DQ27 N 103 D3 D 11 DQ59
4. 34 Data Input Setup Time Before Clock tps 10 05 35 Data Input Hold Time After Clock tDH 17 12 36 Write Recovery Time twa 3C 3C REV 1 0 7 07 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HGS5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Unbuffered DDR2 SO DIMM Serial Presence Detect 1GB 2 Ranks 64Mx16 DDR2 SDRAMs Part 2 of 2 Byte Description 37 Internal Write to Read Command delay twra 38 Internal Read to Precharge delay tare 39 Reserved 40 Extension of Byte 41 tac and Byte 42 tarc 41 Minimum Core Cycle Time tac 42 Min Auto Refresh Command Cycle Time tarc 43 Maximum Clock Cycle Time tcx 44 Max DQS DQ Skew Factor tQHS 45 Read Data Hold Skew Factor tQHS 46 61 Reserved 62 SPD Reversion 63 Checksum for Byte 0 62 64 71 Manufacturers JEDEC ID Code 72 Module Manufacturing Location 73 91 Module Part number 92 255 Reserved REV 1 0 07 2010 C elixir Serial PD Data Entry Hex Note 3C AC 1E TE 1E 1E 00 00 06 36 3C 39 7F 7F 80 80 18 14 22 1E 13 13 A6 8C 00 00 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HGS5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Cel M Unbuffered DDR2 SO DIMM elixir Serial Presence De
5. N 103 D7 D15 DQ28 N 1 04 DQ60 N 1 04 DQ29 M VO5 DQ61 N VO5 DQ30 N 106 DQe2 N VO6 DQ31 A Vo7 DQ63 M VO7 10 Ohms 5 TUA 1 CK0 BAO BA2 TW SDRAMS D D15 F 5 6pF 8 loads AO A13 N gt SDRAMS D D15 Voosep J SerialPD Em p TRASOM Voo L SDRAMS D D15 VDD and VDDQ gt RAS PE SDRAMS ID D15 Veer F x ISDEAMS DIDIS 5 6pF 8loads CAS 4 SDRAMS D D15 Vss 4 gt SDRAMS D D15 SPD cki 0x WE LN SDRAMS D D15 1 i S Notes Serial PD Unless otherwise noted resistor values are22ohms 5 SCL SCL DQ wiring way differ from that described in this drawing AO described in this drawinghowever DO DM DOGS DOGS sAo gt P relationships are maintained as shown SA1 gt SDA gt A2 e REV 1 0 07 2010 WP NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HGS5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Cel M Unbuffered DDR2 SO DIMM elixir Serial Presence Detect 1GB 2 Ranks 64Mx16 DDR2 SDRAMs Part 1 of 2 Serial PD Data Entry Hex Note Byte Description 3C AC 0 Number of Serial PD Bytes Written during Production
6. tpp 3C 32 28 Minimum Row Active to Row Active delay tarp 1E 1E 29 Minimum RAS to CAS delay taco 3C 32 30 Minimum Active to Precharge Time tras 2D 2D 31 Module Rank Density 01 01 32 Address and Command Setup Time Before Clock tis 20 17 33 Address and Command Hold Time After Clock tiu 27 25 34 Data Input Setup Time Before Clock tps 10 05 35 Data Input Hold Time After Clock tDH 17 12 36 Write Recovery Time twa 3C 3C REV 1 0 9 07 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HGS5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Unbuffered DDR2 SO DIMM Serial Presence Detect 2GB 2 Ranks 128 M x 8 DDR2 SDRAMs Part 2 of 2 Byte Description 37 Internal Write to Read Command delay twra 38 Internal Read to Precharge delay tare 39 Reserved 40 Extension of Byte 41 tac and Byte 42 tarc 41 Minimum Core Cycle Time tac 42 Min Auto Refresh Command Cycle Time tarc 43 Maximum Clock Cycle Time tcx 44 Max DQS DQ Skew Factor tQHS 45 Read Data Hold Skew Factor tQHS 46 61 Reserved 62 SPD Reversion 63 Checksum for Byte 0 62 64 71 Manufacturers JEDEC ID Code 72 Module Manufacturing Location 73 91 Module Part number 92 255 Reserved REV 1 0 07 2010 10 C elixir Serial PD Data Entry Hex Note 3C AC 1E TE 1E 1E 00 00 06 36 3C 39 7F 7F 80 80 18 14 22 1E 13 13
7. 16 FC 00 00 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HG5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Cel M Unbuffered DDR2 SO DIMM elixir Environmental Requirements Symbol Parameter Rating Units TOPR Operating Temperature ambient 0 to 65 C Hopr Operating Humidity relative 10 to 90 TsrG Storage Temperature 50 to 100 C HsrG Storage Humidity without condensation 5 to 95 Barometric pressure operating amp storage up to 9850ft 105 to 69 kPa Note Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability Absolute Maximum DC Ratings Symbol Parameter Rating Units Vpp Voltage on VDD pins relative to Vss 1 0 to 2 3 V VDDQ Voltage on VDDQ pins relative to Vss 0 5 to 2 3 V VppL Voltage on VDDL pins relative to Vss 0 5 to 2 3 V Vin Vout Voltage on I O pins relative to Vss 0 5 to 2 3 V TsrG Storage Temperature Plastic 55 to 100 C Note Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is stress rating only and functional operation of the device at these or any other conditions above
8. 180 DQ60 31 DQS1 32 CKO 81 Vop 82 Vpp 131 DQS4 132 Vss 181 DQ57 182 DQel 33 Vss 34 Vss 83 NC 84 NC 133 Vss 134 DQ38 183 Vss 184 Vss 35 DQ10 36 DQ14 85 BA2 86 NC 135 DQ34 136 DQ39 185 DM7 186 DQS7 37 DQ11 38 DQ15 87 Voo 88 Vop 137 DQ35 138 Vss 187 Vss 188 DQS7 39 Vss 40 Vss 89 A12 90 A11 139 Vss 140 DQ44 189 DQ58 190 Vss 41 Vss 42 Vss 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 Vss 193 Vss 194 DQ63 45 DQ17 46 DQ21 95 Vop 96 Vpp 145 Vss 146 DQS5 195 SDA 196 Vss 47 Vss 48 Vss 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SAO 49 DQS2 50 NC 99 A3 100 A2 149 Vss 150 Vss 199 Vboosep 200 SA1 Note All pin assignments are consistent for all 8 byte unbuffered versions A13 is for 2GB modules only REV 1 0 3 07 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HGS5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Unbuffered DDR2 SO DIMM C elixir Input Output Functional Description Symbol CKO CK1 KO Q K1 CKEO CKE1 VREF ODTO ODT1 BAO BA1 BA2 A0 A9 A10 AP A11 A12 A13 DQO DQ63 Vpop Vss DQS0 DQS7 DQS0 DQS7 DMO DM7 SAO SA1 SDA SCL Vopspp REV 1 0 07 2010 Type
9. 80 80 1 Total Number of Bytes in Serial PD device 08 08 2 Fundamental Memory Type 08 08 3 Number of Row Addresses on Assembly oD 0D 4 Number of Column Addresses on Assembly 0A 0A 5 Number of DIMM Ranks Package and Height 61 61 6 Data Width of Assembly 40 40 7 Reserved 00 00 8 Voltage Interface Level of this Assembly 05 05 9 DDR2 SDRAM Device Cycle Time at CL 5 30 25 10 DDR2 SDRAM Device Access Time tac from Clock at CL 5 45 40 11 DIMM Configuration Type 00 00 12 Refresh Rate Type 82 82 13 Primary DDR2 SDRAM Width 10 10 14 Error Checking DDR2 SDRAM Device Width 00 00 15 Reserved 00 00 16 DDR2 SDRAM Device Attributes Burst Length Supported 0C 0C 17 DDR2 SDRAM Device Attributes Number of Device Banks 08 08 18 DDR2 SDRAM Device Attributes CAS Latencies Supported 38 38 19 DIMM Mechanical Characteristics 01 01 20 DDR2 SDRAM DIMM Type Information 04 04 21 DDR2 SDRAM Module Attributes 00 00 22 DDR2 SDRAM Device Attributes General 03 03 23 Minimum Clock Cycle at CL 4 3D 3D 24 Maximum Data Access Time from Clock at CL 4 50 50 25 Minimum Clock Cycle Time at CL 3 50 50 26 Maximum Data Access Time from Clock at CL 3 60 60 27 Minimum Row Precharge Time trp 3C 32 28 Minimum Row Active to Row Active delay tarp 28 28 29 Minimum RAS to CAS delay taco 3C 32 30 Minimum Active to Precharge Time tras 2D 2D 31 Module Rank Density 80 80 32 Address and Command Setup Time Before Clock tis 20 17 33 Address and Command Hold Time After Clock tiu 27 25
10. M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Unbuffered DDR2 SO DIMM ODT DC Electrical Characteristics Parameter Condition Rtt effective impedance value for EMRS A6 A2 0 1 750hm Rtt effective impedance value for EMRS A6 A2 1 0 1500hm Rtt effective impedance value for EMRS A6 A2 1 1 500hm Deviation of Vy with respect to VDDQ 2 Note1 Test condition for Rtt measurements x Input AC DC logic level Symbol Parameter VIH AC Input High Logic1 Voltage VIL AC Input Low LogicO Voltage VIH DC Input High Logic1 Voltage ViL DC Input Low LogicO Voltage REV 1 0 07 2010 C elixir Symbol Min Nom Max Units Note Rtt1 eff 60 90 ohm 1 Rtt2 eff 120 180 ohm 1 Rtt3 eff 40 60 ohm 1 Delta VM 6 6 1 PC2 5300 PC2 6400 Min Max Min Max MES VREF 0 200 VREF 0 200 V VREF 0 200 VREF 0 200 V VREF 0 125 VDDQ 0 3 VREF 0 125 VDDQ 0 3 V 0 3 VREF 0 125 0 3 VREF 0 125 V 12 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HGS5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Cel M Unbuffered DDR2 SO DIMM elixir Operating Standby and Refresh Currents Tease 0 C 85 C Vppa Voo 1 8V 0 1V 1GB 2 Ranks 64Mx16 DDR2 SDRAMs PC2 5300 PC2 6400 Symbol Parameter Condition Unit 3C AC Operating Current one bank
11. active precharge tac tac min tex tck IDDO mm DQ DM and DGS inputs changing twice per clock cycle address 660 792 mA and control inputs changing once per clock cycle Operating Current one bank active read precharge Burst 4 tac tnc IDD1 mm CL 4 tex tex mmn lour OMA address and control inputs 748 858 mA changing once per clock cycle IDD2P Precharge Power Down Standby Current all banks idle power down 79 79 mA mode CKE lt Vi max tok tex Min IDD2Q Precharge quiet standby current 440 528 mA Idle Standby Current CS Viu uy all banks idle CKE 2 Vin miny tck tck IDD2N MIN address and control inputs changing once per clock cycle TW We mA Active Standby Current one bank active precharge CS 2 Vin uy CKE IDD3N 2 Vin min tac tras max tck tek min DQ DM and DOS inputs changing 506 616 mi twice per clock cycle address and control inputs changing once per clock cycle Operating Current one bank Burst 4 reads continuous burst IDDAR address and control inputs changing once per clock cycle DQ and DOS 880 1320 mA outputs changing twice per clock cycle CL 4 tex tok uw lour OMA Operating Current one bank Burst 4 writes continuous burst IDDAW address and control inputs changing once per clock cycle DQ and DQS 880 1320 mA inputs changing twice per clock cycle CL 4 tek tek min IDD5B Burst Refresh Current tac trec viv 1100 1210 mA IDD6 Self Refresh Current CKE lt
12. command 7 5 7 5 ns tccp CAS to CAS 2 2 tck twn Write recovery time 15 15 ns WR Write recovery time with Auto Precharge twn tck twn tck ns WR WR tpAL Auto precharge write recovery precharge time sion abe tox twtr Internal write to read command delay 7 5 7 5 i ns tRTP Internal read to precharge command delay 7 5 7 5 ns tarc terc E txsNR Exit self refresh to a Non read command 410 2 410 ns txsRD Exit self refresh to a Read command 200 i 200 tex txp Exit precharge power down to any Non read command 2 2 tox txaRD Exit active power down to read command tok txARDS Exit active power down to read command 7 AL P 8 AL tck tcKE CKE minimum pulse width x tek tort OCD drive mode output delay 0 12 0 12 ns ODT tAOND ODT turn on delay 2 2 2 2 tck tAON ODT turn on TAC min tac max 0 7 tac min tac max 0 7 ns tac min 2 lek avg tac min 2 tek avg ud tAONPD ODT turn on Power down mode 42 beso 42 fei ns tAOFD ODT turn off delay 2 5 2 5 2 5 2 5 tck taor ODT turn off tacimin tac maxy 0 6 tac min tac maxy 0 6 ns tac min 2 5tck avg laC min 2 5tck avg tAOFPD ODT turn off Power down mode 42 bat 42 bios ns tANPD ODT to power down entry latency 3 3 tck tAXPD ODT power down exit latency 8 8 tek Speed Grade Definition 3C AC Symbol Parameter Unit Min Max Min Max tRAS Row Active Time 45 70000 45 70000 ns trop RAS to CAS delay 15 s 12 5 s ns tro Row Cycle Time 60 57 5 ns trp Row P
13. 0 2V 79 79 mA Operating Current four bank four bank interleaving with BL 4 IDD7 address and control inputs randomly changing 50 of data changing at 1364 1738 mA every transfer tnc tac min lour OMA Note Module IDD was calculated from component IDD It may differ from the actual measurement REV 1 0 13 07 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HGS5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Cel M Unbuffered DDR2 SO DIMM elixir Operating Standby and Refresh Currents Toase 0 C 85 C Vppa Von 1 8V 0 1V 2GB 2 Ranks 128M x 8 DDR2 SDRAMs PC2 5300 PC2 6400 Symbol Parameter Condition Unit 3C AC Operating Current one bank active precharge tac tac min tex tck IDDO mm DQ DM and DGS inputs changing twice per clock cycle address 836 968 mA and control inputs changing once per clock cycle Operating Current one bank active read precharge Burst 4 tac tac IDD1 Mix CL 4 tex tek min lour OMA address and control inputs 924 1100 mA changing once per clock cycle Precharge Power Down Standby Current all banks idle power down IDD2P 158 158 mA mode CKE lt Vi max tok tek Min IDD2Q Precharge quiet standby current 528 616 mA Idle Standby Current CS gt V all banks idle CKE gt V Htec t IDD2N y IH MIN IH MIN l
14. A13 is for 2GB modules only REV 1 0 2 07 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HG5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Cel M Unbuffered DDR2 SO DIMM elixir Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back VREF 2 Vss 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46 Vss 4 DQ4 53 Vss 54 Vss 103 Vop 104 Voo 153 DQ43 154 DQ47 DQO 6 DQ5 55 DQ18 56 DQ22 105 A10 AP 106 BA1 155 Vss 156 Vss Dat 8 Vss 57 DQ19 58 DQ23 107 BAO 108 RAS 157 DQ48 158 DQ52 Qo ow Vss 10 DMO 59 Vss 60 Vss 109 WE 110 CSO 159 DQ49 160 DQ53 11 DQSO 12 Vss 61 DQ24 62 DQ28 111 Vop 112 Vodo 161 Vss 162 Vss 13 DQSO 14 DQ6 63 DQ25 64 DQ29 1138 CAS 114 ODTO 163 NC 164 CK1 15 Vss 16 DQ7 65 Vss 66 Vss 115 CS1 116 A13 NC 165 Vss 166 CK1 17 DQ2 18 Vss 67 DM3 68 DQS3 117 Vpp 118 Voo 167 DQS6 168 Vss 19 DQ3 20 DQ12 69 NC 70 DQS3 119 ODTI 120 NC 169 DQS6 170 DM6 21 Vss 22 DQ13 71 Vss 72 Vss 121 Vss 122 Vss 171 Vss 172 Vss 23 DQ8 24 Vss 73 DQ26 74 DQ30 128 DQ32 124 DQ36 173 DQ50 174 DQ54 25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 27 Vss 28 Vss 77 Vss 78 Vss 127 Vss 128 Vss 177 Vss 178 Vss 29 DQS1 30 CKO 79 CKEO 80 CKE1 129 DQS4 130 DM4 179 DQ56
15. ACK SIDE 3 80 MAX U gt o oO 20 1100 4 0 10 Detail A Detail B 0 45 4 00 0 10 E RS 25 MAX Y 0 A 1 00 0 1 sl os k Note All dimensions are typical with tolerances of 0 15 unless otherwise stated Units Millimeters Inches Note Device position and scale are only for reference REV 1 0 18 07 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HG5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Cel DS Unbuffered DDR2 SO DIMM elixir Revision Log Rev Date Modification 0 1 01 2010 Preliminary Edition 1 0 07 2010 Official Release Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd Kueishan Taoyuan 333 Taiwan R O C Tel 886 3 328 1688 Please visit our home page for more information http www elixir memory com Printed in Taiwan 2010 REV 1 0 19 07 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
16. M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HGB5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Unbuffered DDR2 SO DIMM elixir Based on DDR2 667 800 64Mx16 1GB 128Mx8 2GB SDRAM G Die Features Performance PC2 5300 PC2 6400 speeder 3C AC Unit DIMM CAS Latency 5 5 fck Clock Freqency 333 400 MHz tck Clock Cycle 3 2 5 ns Data Transfer Speed 667 800 Mbps 200 Pin Small Outline Dual In Line Memory Module SO DIMM 1GB 128Mx64 Unbuffered DDR2 SO DIMM based on 64M x16 DDR2 SDRAM G Die devices 2GB 256Mx64 Unbuffered DDR2 SO DIMM based on 128M x8 DDR2 SDRAM G Die devices Intended for 333MHz and 400MHz applications Inputs and outputs are SSTL 18 compatible e Voo Vooo 1 8V 0 1V SDRAMs have 8 internal banks for concurrent operation Differential clock inputs Data is read or written on both clock edges e DRAM DLL aligns DQ and DGS transitions with clock transitions Address and control signals are fully synchronous to positive clock edge Auto Refresh CBR and Self Refresh Modes Description Automatic and controlled precharge commands Programmable Operation DIMM CAS Latency 3 4 5 Burst Type Sequential or Interleave Burst Length 4 8 Operation Burst Read and Write 13 10 2 Addressing 1GB 14 10 2 Addressing 2GB 7 8 us Max Average Periodic Refresh Interval Serial Presence Detect Gold contacts 1GB module s SDRAMs are 84
17. RATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HG5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Cel e Unbuffered DDR2 SO DIMM elixir Ordering Information Part Number Speed Organization Power Leads Note M2N2G64TU8HGBB AC DDR2 800 PC2 6400 400MHz 2 5ns CL 5 M2N2G64TU8HG5B 3C DDR2 667 PC2 5300 333MHz 3 0ns CL 5 256Mx64 M2N2G64TU8HG4B AC DDR2 800 PC2 6400 400MHz 2 5ns CL 5 way Goid M2N1G64TUH8G5F AC DDR2 800 PC2 6400 400MHz 2 5ns CL 5 M2N1G64TUH8G5F 3C DDR2 667 PC2 5300 333MHz 3 0ns Q CL 5 128Mx64 M2S1G64TUH8G4F AC DDR2 800 PC2 6400 400MHz 2 5ns CL 5 Pin Description CKO CK1 CKO CK1 Differential Clock Inputs DQ0 DO63 Data input output CKEO CKE1 Clock Enable DQS0 DQS7 Bidirectional data strobes RAS Row Address Strobe DQS0 DQS7 Differential data strobes CAS Column Address Strobe DM0 DM7 Input Data Masks WE Write Enable Voo Power 1 8V cso CS1 Chip Selects VREF Ref Voltage for SSTL_18 inputs A0 A9 A11 A13 Row Address Inputs VopsPp Serial EEPROM positive power supply A0 A9 Column Address Inputs Vss Ground A10 AP Column Address Input Auto precharge SCL Serial Presence Detect Clock Input BAO BA1 BA2 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input output ODTO ODT1 Active termination control lines SAO SA1 Serial Presence Detect Address Inputs NC No Connect Note
18. S D0 D7 A0 A12 JN J SDRAMS DO D7 cko gt RAS N gt DRAMS D0 D7 V ppsPp 9 SPD 4 loads 2 wan Von e F J __ D0 D7 VDD and VDDQ EKO TAS N SDRAMS D0 D7 VREF w DO D7 wE w gt SDRAMS D0 D7 Vss e Y p D0 D7 SPD CRI iiid Vopip 9 CKI Serial PD SCL 9 Notes aed 1 DQ wiring may differ from that di i in thi ing SA1 2 DODOS DM REIS Serene ae aS howi WP gt AO M A2 SDA 3 DQ DQS DM DQS resistors are 22 5 Ohms 4 Voom strap connections for memory device Vop Vona STRAP OUT OPEN Voo Vova STRAP IN Vss Vopis not equal to Vona REV 1 0 5 07 2010 i NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HGS5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Unbuffered DDR2 SO DIMM Functional Block Diagram 2GB 2 Ranks 128M x8 DDR2 SDRAMs 3 Ohms 5 elixir ODT1 ODT A CKE1 CKEO csi cso paso M Das CSO CKEO ODTO CS1 CKE1i ODT1 pass N Das CSO CKE ODTO CS1 CKE1 ODT1 DQS0 M Das DQM M Das DMO N DM DM
19. SO DIMM elixir AC Timing Specifications for DDR2 SDRAM Devices Used on Module Tease 0 C 85 C Vona 1 8V 0 1V Voo 1 8V 0 1V See AC Characteristics Part 1 of 2 Symbol Parameter Unit Notes Min Max Min Max tac DQ output access time from CK CK 0 45 0 45 0 40 0 40 ns tpasck DQS output access time from CK CK 0 4 0 4 0 35 0 35 ns tcH CK high level width 0 48 0 52 0 48 0 52 tck teL CK low level width 0 48 0 52 0 48 0 52 tox Minimum half clk period for any given cycle defined by clk high Min tCH ab Min tCH ab tup tci or clk low tc time s tCL abs s tCL abs tox tck Clock Cycle Time 3 8 2 5 8 ns tpH DQ and DM input hold time 175 125 ps tps DQ and DM input setup time 100 50 ps tipw Input pulse width 0 6 0 6 tck tDIPW DQ and DM input pulse width each input 0 35 0 35 tck thz Data out high impedance time from CK CK tac max E tacmax NS tzoa Data out low impedance time from CK CK 2Xlacmin tacma 2Xtacmin tacmax IS tizipas PQS low impedance time from CK CK tac min tac max tac min tacmax NS tpaso DQS DQ skew DQS amp associated DQ signals 0 24 z 0 20 ns tous Data hold Skew Factor z 0 34 a 0 30 ns tay Data output hold time from DQS e Fm ns tpass Write command to 1 DQS latching transition 0 25 0 25 0 25 0 25 tck tDQSH DQS input high pul
20. ball BGA Package 2GB module s SDRAMs are 60 ball BGA Package RoHS compliance M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HG5B M2N2G64TU8HGAB are unbuffered 200 Pin Double Data Rate 2 DDR2 Synchronous DRAM Small Outline Dual In Line Memory Module SO DIMM organized as two ranks of 128Mx64 1GB 256Mx64 2GB high speed memory array M2N1G64TUH8GS5F M2S1G64TUH8G4F uses eight 64Mx16 84 ball BGA packaged devices and M2N2G64TU8HGS5B M2N2G64TU8HGAB uses sixteen 128Mx8 60 ball BGA packaged devices These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR2 SODIMMs provide a high performance flexible 8 byte interface in a space saving footprint The DIMM is intended for use in applications operating of 333MHz 400MHz clock speeds and achieves high speed data transfer speed of 667Mbps 800Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs A0 A12 1GB A0 A13 2GB and I O inputs BAO BA1 and BA2 using the mode register set cycle The DIMM uses serial presence detect implemented via a serial EEPROM using a standard IIC protocol The first 128 bytes of SPD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer REV 1 0 1 07 2010 NANYA TECHNOLOGY CORPO
21. cK lck 528 704 mA MIN address and control inputs changing once per clock cycle Active Standby Current one bank active precharge CS 2 Vin uy CKE gt Vin MIN inc tras MAX tck tok MIN DQ DM and DQS inputs changing IDD3N twice per clock cycle address and control inputs changing once per ee 9E mA clock cycle Operating Current one bank Burst 4 reads continuous burst IDD4R address and control inputs changing once per clock cycle DQ and DQS 1144 1408 mA outputs changing twice per clock cycle CL 4 tek tok uw lour OMA Operating Current one bank Burst 4 writes continuous burst IDDAW address and control inputs changing once per clock cycle DQ and DQS 1144 1408 mA inputs changing twice per clock cycle CL 4 tek tek min IDD5B Burst Refresh Current tac trec uw 1672 1892 mA IDD6 Self Refresh Current CKE lt 0 2V 158 158 mA Operating Current four bank four bank interleaving with BL 4 IDD7 address and control inputs randomly changing 50 of data changing at 2112 2552 mA every transfer tnc tac min lour OMA Note Module IDD was calculated from component IDD It may differ from the actual measurement REV 1 0 14 07 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HGS5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Cel M Unbuffered DDR2
22. o9 vO 9 DQ10 N VO 10 wo 10 DQ42 4 VO 10 roio DQ11 A WO 11 L vou DQ43 J WO 11 VO 11 DQ12 M VO 12 vo 12 DQ44 M VO 12 VO 12 DQ13 N WO 13 L wo 18 DQ45 JN WO 13 VO 13 DQ14 M VO 14 _ wvo14 DQ46 M VO 14 VO 14 DQ15 N WO 15 L 4 1015 DQ47 N WO 15 VO 15 Das2 N mas cs C O pas CSC O Dase y bas CS C O IDAS CS C O Das2 Jy LDQS r 2 L Lpas K D DQSe LDQS K D LDQS K D DM2 N LDM __ LDM EotT DM6 LDM LU LDM so DQ16 N WOO woo DQ48 N WOO yo o DQ17 M VO 1 EE o DQ49 M yo 1 yo 1 DQ18 N V O2 L 02 DQ50 N 02 yo2 DQ19 M yo 3 L 03 DQ51 M VO 3 VO 3 DQ20 N 104 _ vo4 DQ52 N 1 04 VO 4 DQ21 N o5 05 DQ53 N 05 VO 5 DQ22 N o6 LI voe DQ54 N 106 Vo 6 DQ23 107 E voz DQ55 N 107 VO 7 pas3 UDQS Di __ UDQS D5 DQS7 UDGS D3 UDQS D7 DQS3 MH UDQS L upas DQS7 J A UDQS UDQS DM3 J UDM L UDM DM7 N UDM UDM DQ24 N 108 L 108 DQ56 N O8 VO 8 DQ25 N o9 L o9 DQ57 N o9 yo9 DQ26 JA WO 10 L wo 10 DQ58 JV VO 10 VO 10 DQ27 VO 11 LER DQ59 M VO 11 VO 11 DQ28 J WO 12 L MIS DQ60 JA WO 12 VO 12 DQ29 J WO 13 L wo 13 DQ61 J VO 13 VO 13 DQ30 JA WO 14 __ wo 14 DQ62 JA WO 14 VO 14 DQ31 JV WO 15 L wo 15 DQ63 A VO 15 VO 15 BA0 BA2 N SDRAM
23. recharge Time 15 12 5 ns REV 1 0 16 07 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HG5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Unbuffered DDR2 SO DIMM Package Dimensions 1GB 2 Ranks 64Mx16 DDR2 SDRAMs FRONT 67 60 ia 63 60 e 9 vt E x 8 S 8 S e N 2x 0 d 1 80 39 7 7 41 199 2 15 40 NA gt Detail NW Detail B i 4 20 gt Ph 47 40 2 7 OF le 2 45 BACK SIDE 1 00 0 10 P O 3 80 MAX gt j Detail A Detail B x g 0 45 4 00 0 10 5 Eai ol eo EN 1 00 0 1
24. se width 0 35 0 35 tck tpas DQS input low pulse width 0 35 0 35 tek toss Maca to CK setup time 0 2 0 2 i tok tosi rie ded ai hold time from CK 0 2 0 2 tox tMRD Mode register set command cycle time 2 2 s tck twpsr Write postamble 0 40 0 60 0 40 0 60 tck twere Write preamble 0 35 0 35 z tck tH Address and control input hold time 0 275 E 0 250 ns tis Address and control input setup time 0 2 0 175 ns tRPRE Read preamble 0 9 1 1 0 9 1 1 tck RPST Read postamble 0 4 0 6 0 4 0 6 tck tela Pii UN clocks remains ON after CKE asynchronously tis iei 0s ae ns tRFC Refresh to active Refresh command time 127 5 127 5 ns pe Te Interval 39 39 us ineri Average Periodic Refresh Interval 78 78 us 0 C lt Tcase S 85 C REV 1 0 15 07 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HG5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 PC2 5300 PC2 6400 Unbuffered DDR2 SO DIMM elixir AC Timing Specifications for DDR2 SDRAM Devices Used on Module Tease 0 C 85 C Vppa 1 8V 0 1V Voo 1 8V 0 1V See AC Characteristics Part 2 of 2 3C AC Symbol Parameter Unit Notes Min Max Min Max tRRD Active bank A to Active bank B
25. tect 2GB 2 Ranks 128Mx8 DDR2 SDRAMs Part 1 of 2 Serial PD Data Entry Hex Note Byte Description 3C AC 0 Number of Serial PD Bytes Written during Production 80 80 1 Total Number of Bytes in Serial PD device 08 08 2 Fundamental Memory Type 08 08 3 Number of Row Addresses on Assembly OE OE 4 Number of Column Addresses on Assembly 0A 0A 5 Number of DIMM Ranks Package and Height 61 61 6 Data Width of Assembly 40 40 7 Reserved 00 00 8 Voltage Interface Level of this Assembly 05 05 9 DDR2 SDRAM Device Cycle Time at CL 5 30 25 10 DDR2 SDRAM Device Access Time tac from Clock at CL 5 45 40 11 DIMM Configuration Type 00 00 12 Refresh Rate Type 82 82 13 Primary DDR2 SDRAM Width 08 08 14 Error Checking DDR2 SDRAM Device Width 00 00 15 Reserved 00 00 16 DDR2 SDRAM Device Attributes Burst Length Supported 0C 0C 17 DDR2 SDRAM Device Attributes Number of Device Banks 08 08 18 DDR2 SDRAM Device Attributes CAS Latencies Supported 38 38 19 DIMM Mechanical Characteristics 01 01 20 DDR2 SDRAM DIMM Type Information 04 04 21 DDR2 SDRAM Module Attributes 00 00 22 DDR2 SDRAM Device Attributes General 03 03 23 Minimum Clock Cycle at CL 4 3D 3D 24 Maximum Data Access Time from Clock at CL 4 50 50 25 Minimum Clock Cycle Time at CL 3 50 50 26 Maximum Data Access Time from Clock at CL 3 60 60 27 Minimum Row Precharge Time
26. those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability Storage temperature is the case surface temperature on the center top side of the DRAM Operating temperature Conditions Symbol Parameter Rating Units Note TCASE Operating Temperature Ambient 0 to 95 C 1 Note 1 Case temperature is measured at top and center side of any DRAMs 2 tcAsE gt 85 C 2 tper 3 9 us DC Electrical Characteristics and Operating Conditions Symbol Parameter Min Max Units Notes VDD Supply Voltage 1 7 1 9 V 1 VDDL DLL Supply Voltage 1 7 1 9 V 1 VDDQ Output Supply Voltage 1 7 1 9 V 1 Vss Vssa Supply Voltage I O Supply Voltage 0 0 V VREF Input Reference Voltage 0 49VDDQ 0 51VDDQ V 1 2 VTT Termination Voltage VREF 0 04 VREF 0 04 V 3 Note 1 There is no specific device VDD supply voltage requirement for SSTL 18 compliance However VDDQ must be less than or equal to VDD under all conditions 2 VREFis expected to be equal to 0 5 V DDQ of the transmitting device and to track variations in the DC level of the same Peak to peak noise on VREF may not exceed 2 of the DC value 3 VTT of transmitting device must track VREF of receiving device REV 1 0 11 07 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUH8G5F M2S1G64TUH8G4F M2N2G64TU8HGS5B
27. umn address CA0 CA9 when sampled at the rising clock edge In addition to the column address AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle If AP is high autoprecharge is selected and BAO BA1 BA2 define the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BA1 BA2 to control which bank s to precharge If AP is high all 8 banks will be precharged regardless of the state of BAO BA1 BA2 If AP is low then BAO BA1 BA2 are used to define which bank to pre charge Data and Check Bit Input Output pins Power and ground for the DDR2 SDRAM input buffers and core logic Data strobe for input and output data The data write masks associated with one data byte In Write mode DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect DM8 is associated with check bits CBO CB7 and is not used on x64 modules Address inputs Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address This bi directional pin is used to transfer data into or out of the SPD EEPROM A resistor must be connected from the SDA bus line to V DD to act as a pull up This signal is used to clock data into and out of the SPD EEPROM A resistor may be connected from the SCL bus time to V DD to act as a pull
28. up Serial EEPROM positive power supply NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2N1G64TUHS8G5F M2S1G64TUH8G4F M2N2G64TUSHG5B M2N2G64TU8HG4B 1GB 128M x 64 2GB 256M x 64 elixir PC2 5300 PC2 6400 Unbuffered DDR2 SO DIMM Functional Block Diagram 1GB 2 Ranks 64Mx16 DDR2 SDRAMs 3 Ohms 5 opT1 ODTO CKE1 CKEO csi W cso Daso bas CS C O pas CSC O DaS4 tpas CS C O mE CS C O DQS0 N LDQS E 2 LDQS is 2 DaS4 LDQS s 2 LDQS E 2 DMO M LDM LDM DM4 LDM LDM Dao N woo L 4 woo DQ32 N WOO yo 0 pai N o1 __ ion DQ33 01 yO 1 paz N o2 _ wvo2 pasa VO2 yo 2 pas N o3 L vos DQ35 N 103 V0 3 DQ4 M 04 _ vo4 DQ36 M VO 4 VO 4 pas N o5 L 05 DQ37 N o5 yo5 pas N woe L woe DQ38 106 yo 6 DQ7 N o7 L voz DQ39 N 107 o7 DGSi Jv UDGS Do __ aS D4 DGS5 UDQS D2 UDQS D6 DQS1 M UDQS _ upas DQS5 J UDQS UDQS DM1 N UDM L UDM DM5 N UDM UDM pas N os L ros DQ40 N o8 08 pas N o9 L woe DQ41 N
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