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Silicon Power 2GB PC3-10600

1. A12 is sampled during READ and WRITE commands to determine if burst chop on the fly will be performed The address inputs also provide the opcode during mode register command set A0 A13 128Mx8 Bank address inputs BAO BA1 define to which device bank an ACTIVE READ WRITE or BA0 BA2 Input PRECHARGE command is being applied BAO BA1 define which mode register including MR EMR EMR 2 and EMR 3 is loaded during the LOAD MODE command CKO CKO Clock CK and CK are differential clock inputs All address and control input signals are CK1 CK1 Input sampled on the crossing of the positive edge of CK and negative edge of CK Output data i DQs and DQS DQS is referenced to the crossings of CK and CK Clock enable CKE registered HIGH activates and CKE registered LOW deactivates S clocking circuitry on the DDR3 SDRAM Data input mask DM is an input mask signal for write data Input data is masked when DM is DMO DM7 input sampled HIGH along with that input data during a write access DM is sampled on both p edges of DQS Although DM pins are input only the DM loading is designed to match that of DQ and DQSTpins BR On die termination ODT registered HIGH enables termination resistance internal to the BR Input DDR3 SDRAM When enabled ODT is only applied to the following pins DQ DQS DQS and DM The ODT input will be ignored if disabled via the LOAD MODE command RAS CAS apat Command inputs RAS CAS and WE al
2. SP004GBLTU133V01 2 256Mx8 2Ranks PC3 10600 DDR3 1333 SP002GBLTU106S21 2 PC3 8500 DDR3 1066 1GB x 2 Kit Package SP002GBLTU133S21 2 PC3 10600 DDR3 1333 SPOO3GBLTU106S31 2 PC3 8500 DDR3 1066 1GB x 3 Kit Package SPO03GBLTU133531 2 PC3 10600 DDR3 1333 SPOO4GBLTU106S21 2 DDR3 1066 SPOO4GBLTU133S21 2 2GB x 2 Kit Package PC3 10600 DDR3 1333 SPOO4GBLTU160S21 2 PC3 12800 DDR3 1600 SPOO4GBLTU106V21 2 PC3 8500 DDR3 1066 SPOO4GBLTU160V21 2 SPOOGGBLTU106S31 2 PC3 8500 DDR3 1066 SPOO6GBLTU160S31 2 SPOO6GBLTU133V31 2 2GB x 3 Kit Package PC3 10600 DDR3 1333 SPOO6GBLTU160V31 2 PC3 12800 DDR3 1600 SPOO8GBLTU106V21 2 PC3 8500 DDR3 1066 4GB x 2 Kit Package SPOO8GBLTU133V21 2 PC3 10600 DDR3 1333 SP012GBLTU106V31 2 PC3 8500 DDR3 1066 4GB x 3 Kit Package SP012GBLTU133V31 2 PC3 10600 DDR3 1333 Note This document supports all LTU Series DDR3 240Pin UDIMM products Some item was be EOL in this list Please contact with our sales Dep 7 7 7 SP004GBLTU133V21 2 2GB x 2 Kit Package PC3 10600 DDR3 1333 99 9 7 7 7 2 Rev 1 2 Nov 2010 O SILICON POWER DDR3 Unbuffered DIMM Spec Sheet Pin Assignments 240 Pin UDIMM Front Pin Symbot Pin Rana Pin Sal Pn symbor 3 dao 33 Das3 63 CkK1__ 93 DASB 6 DQSO 36 Daze 66 VDD 96 Dad 8 vss 38 vss_ 68 Nc 98 vss 9 baz 39 Nc _ 69 voD fes Dass pio DG 40 NC B V W V V 240 Pin
3. 9 0 8 0 031 9 5 0 374 l TYP TYP TYP l 54 68 2 15 Pin 120 TYP 123 0 4 84 TYP Back view No Components This Side of Module 3 0 0 118 4x TYP on p Pin 240 5 0 0 197 TYP Pin 121 lt 71 0 2 79 l 47 0 1 85 TYP TYP Note 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted Note 2 The dimensional diagram is for reference only 3 05 0 12 Typ C 5 Rev 1 2 Nov 2010 O SILICON POWER DDR3 Unbuffered DIMM Spec Sheet Simplified Mechanical Drawing x8 2Ranks Front view 4 0 0 157 133 50 5 256 MAX 133 20 5 244 pas 0 75 0 03 R 8 30 5 1 2 29 85 1 175 2 5 0 098 D 2x l 17 3 0 68 TYP 2 3 0 091 TYP LLL Pin 1 0 76 0 030 R sel l 1 37 0 054 2 2 0 087 TYP 1 0 0 039 0 8 0 031 9 5 0 374 1 17 0 046 TYP TYP j TYP 1 45 0 057 TYP 54 68 2 15 Pin 120 TYP 123 0 4 84 TYP Back view 3 0 0 118 4x TYP Pin 240 on L ME 5 0 0 197 TYP Pin 121 e 11 0 2 79 e s 47 0 1 85 TYP sike Note 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted Note 2 The dimensional diagram is for reference only 3 05 0 12 TYP TU 6 Rev 1 2 Nov 2010
4. O SILICON POWER DDR3 Unbuffered DIMM Spec Sheet Features e DDR3 functionality and operations supported as defined in the component data sheet e 240 pin unbuffered dual in line memory module UDIMM e Fast data transfer rates PC3 8500 PC3 10600 PC3 12800 e 1GB 128 Meg x 64 2GB 256 Meg x 64 4GB 512Meg x 64 e Voo Vppa 1 5V 0 075V e Vppspp 3 0V to 3 6V e Reset pin for improved system stability e Nominal and dynamic on die termination ODT for data strobe and mask signals e Single or Dual rank e Fixed burst chop BC of 4 and burst length BL of 8 via the mode register set MRS e Adjustable data output drive strength e Serial presence detect SPD EEPROM e Gold edge contacts e Pb free e Fly by topology e Terminated control command and address bus 1 Rev 1 2 Nov 2010 O SILICON POWER DDR3 Unbuffered DIMM Spec Sheet Module Specification Module Density amp Timing Part Number Bandwidth Data Rate Configuration Bandwidth tCL tRCD tRP SPOO1GBLTU106S01 2 1GB 128Mx64 PC3 8500 DDR3 1066 7 7 7 SPOO1GBLTU133S01 2 128Mx8 1Rank PC3 10600 DDR3 1333 SP002GBLTU106S01 2 PC3 8500 DDR3 1066 SP002GBLTU133S01 2 2GB 200Nx08 RG3 10600 DDR3 1333 99 9 C 128Mx8 2Ranks SP002GBLTU160S01 2 PC3 12800 DDR3 1600 9 9 9 SP002GBLTU106V01 2 2GB 256Mx64 PC3 8500 DDR3 1066 SP002GBLTU133V01 2 256Mx8 1Rank PC3 10600 DDR3 1333 SP004GBLTU133V01 2 4GB 512Mx64 PC3 8500 DDR3 1066
5. UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol ize Das Tas NG iss A0 218 Dasz 132 13 134 rez ne nor voo 227 Daso ves 166 cKer tes vss 220 vss _ 140 Dazo 170 vob 200 Dass 230 Dm7 an no Tan 172 a vss a vss 71 Bao Ta T vss 72 voo 102 basek 3 73 we 103 Dase 7a case 104 vss 75 105 a Das an VSS 9 NG NG MEN NC 75 VDD NC 76 St 106 Da51 vss 47 vss 77 oDri 107 vss 20 vss 50 cKEO 80 vss 110 vss 2 vss se A7 ss vss me vss 2 vss so m eo vss mo sa 30 Dazs ec ven 90 paw 12 vrr L NC AO NC DD NC E Ss NC DD NC S1 9 1 101 102 103 104 105 106 107 9 VSS 0 SS 9 3 5 136 T 8 9 1 NC VDD 141 NC 142 vss 172 Nc a14 202 vss 232 vss VDD A12 A9 as Dm2 13 voo 208 pwa 233 Dasz aa T no ia m2 204 ne 234 Dass 145 VSS 175 205 VSS 235 VSS 3 Rev 1 2 Nov 2010 O SILICON POWER DDR3 Unbuffered DIMM Spec Sheet Pin Description Address inputs Provide the row address for ACTIVE commands and the column address and auto precharge bit for READ WRITE commands to select one location out of the memory array in the respective bank A10 is sampled during a PRECHARGE command to determine A0 A14 dit whether the PRECHARGE applies to one bank A10 LOW or all banks A10 HIGH If only p one bank is to be precharged the bank is selected by BA
6. ong with S define the command being WE p entered input Reset RESET is an active LOW CMOS input referenced to Vss The RESET input receiver RESET LVCMOS is a CMOS input defined as a rail to rail signal with DC HIGH 2 0 8 gt V on and DC LOW lt 0 2 XV pp SO S1 pe S enables registered LOW and disables registered HIGH the command SAT2 0 bit Presence detect address inputs These pins are used to configure the SPD EEPROM 2 0 E address range SCL l t Serial clock for presence detect SCL is used to synchronize the presence detect data p transfer to and from the module ED Data Sa G with read data input with write data for source synchronous operation DQSO DQST Edge aligned with read data center aligned with write data n e e nan a into and out of the SPD EEPROM on the module Tem perature sensor SPD EEPROM power supply 3 0V to 3 6V NC Noconnect These pins are not connected on the module NU Not used These pins are not used in specific module configuration operations 4 Rev 1 2 Nov 2010 O SILICON POWER DDR3 Unbuffered DIMM Spec Sheet Simplified Mechanical Drawing x8 1Rank Front view 2 7 0 106 133 50 5 256 MAX 133 20 5 244 7 _ S i 0 30 5 1 2 29 85 1 175 2 5 0 098 D 2x 17 3 0 68 TYP 2 3 0 091 TYP ar PO pi pitit 0 76 0 030 R e L 1 37 0 054 E 1 17 0 046 1 0 0 03

Silicon Power 2GB PC3-10600

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