Dataram 2GB DDR3-1333
Contents
1. Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high ss u 2 DTM64305C Optimizing Value and Performance 2GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Operating Voltage 1 5V 0 075 Type SSTL 15 On board 12 temperature sensor with integrated serial presence detect SPD EEPROM Data Transfer Rate 8 5 Gigabytes sec pud seis aras d Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT wd i d I wi Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 and 8 Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Fully RoHS Compliant Front Side Vaerpo 31 DQ25 Vss 32 000 33 DQS3 001 34 0083 Vss 35 Vss DQSO 36 DQ26 DQSO 37 DQ27 Vss 38 Vss 002 gt 139 1000803 140 1 11Vsg 41 Vas 12098 42 DQS8 13DQ9 43 DQS8 14Vss 44 Vss 15 DQS1 45 CB2 16 0051 46 1755 M7 Vas 18 0010 48 Vt 190911 49 Vr 20 Vss 50 CKEO 210916 1551 22DQ17 52 2 23Vss 153 2410082 54 Vpp 25 0952 55A11 26 Vss 56 AT 270018 57 28 0019 58 A5 29Vas 59 A4 30 DQ24 160 Not used DOA 0 N gt 61 2 62 63 CK1 64 1 65 Vpp 66 Vpp 67 68 Par In 69 VDD 70 A10 AP 71 BAO 7255 73 WE 74 CAS 75 Vpp 76 S1 77 ODT12. O_ DMRI8 0 DECOUPLING CKE1 bns CKE1R ODT1 Y ODT4R VDD PAR IN ERR_OUT VREF DQ GLOBAL SDRAM CONNECTS CKO L R CLK 1 0 g Vss 120 All 39 OHMS OHMS REF_CA BA 2 0 R IL R CLK 1 0 V TT All SDRAMs 15 0 RESET RASR SDRAMS CASR WER VTT m 240 OHMS TEMPERATURE MONITOR ZQ SCL SERIAL PD CKE 1 0 R ODT 1 0 R SAO 1 2 RS 1 0 VTT Vss DTM64305C 2GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Document 06536 Revision A 7 May 09 Dataram Corporation 2009 DTM64305C Optimizing Value and Performance 2GB _ 240 Pin oRx8 Registered ECC DDR3 DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability Ambient Temperature Operating TA Oo 70 C DRAM Case Temperature Operating Tos 0 95 C Voltage on Vpp relative to Vss V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note I O Reference Voltage 0 49 0 50 0 51 1 Reference Voltage VREFCA 0 49 Vpp 0 50 Vpp 0 51 Vpp 1 Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations the Vpp DC level Pea
3. 1 181 17 30 0 681 Y 5 00 A 0 197 5 175 du phu 47 00 71 00 0 204 1 850 2 795 123 00 ET 4 843 Back view Side view 4 00Max 0 157 Max 4 00 Min 0 157 Min 1 27 10 0 0500 0 0040 Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Se N 2 Document 06536 Revision A 7 May 09 Dataram Corporation 2009 D Optimizing Value and Performance IRS1O Rn od pn 5 IDQSR4 O 9 DMROO ann DMRAO ann TDQSR9 O 111 5 13 11 DQR 7 0 O44 1 0 7 0 RANK 0 7 0 RANK DQR 39 32 O 1 0 7 0 RANK 0 UO 7 0 RANK DQSR1O m allium DQSR5 ml IDQSR1 DQSR5 1 DMR5O TDQSR100 TDQSR140 DQR 15 8 DQR 47 40 DQSR20 DQSR6 DQSR2 DQSR6 DMR2O DMR6O TDQSR110 TDQSR15O DQR 23 16 DQR 55 48 DQSR3 DQSR7 DQSR3 DQSR7 DMR3O DMR7O TDQSR120 TDQSR160 DQR 31 24 56 63 DQSR8O DQSR8 DMR8O TDQSR17 CBR 7 0 TO SDRAMS V DD All 39 OHMS 100 nF 39 OHMS 10 22 OHMS 00163 0 abo i DQRI63 0 t im oT aa WNW O 151 IRS1 LCLK 1 0 RCLK 1 0 CB 7Z 0 O O CBR 7 0 ed bord 15 0 A 15 0 R DQS 17 0 Q NN O DQSR 17 0 IRAS RASR DQS 17 0 O O DQSR 17 0 ICAS Tn ANE I DM 8 0 O VAW
4. 7 X Bit 4 CL 8 X Bit 5 CL 9 Bit 6 CL 10 Document 06536 Revision A 7 May 09 Dataram Corporation 2009 Page 8 DTM64305C Optimizing Value and Performance 2GB _ 240 Pin oRx8 Registered ECC DDR3 DIMM Bit 7 CL 11 C gt lt 15 CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 13 125ns gt lt 13 125ns 16 17 18 19 0 2 13 125ns oignificant Byte tWTRmin tRTPmin Upper Nibble for tFAW Bit 3 Bit 0 tFAW Most Significant Nibble 1 Bit 7 Bit 4 Reserved Upper Nibbles for tRAS and tRC 0x11 Bit 3 Bit 0 tRAS Most Significant Nibble 1 Bit 7 Bit 4 tRC Most Significant Nibble 1 22 Minimum Active to Precharge Delay Time tRASmin Least 37 5ns oignificant Byte 23 Active to Active Refresh Delay Time tRCmin Least 50 625ns 0x95 Ed oignificant Byte 24 Minimum Refresh Recovery Delay Time tRFCmin Least 110 0ns 0x70 oignificant Byte Minimum Refresh Recovery Delay Time tRFCmin Most 110 0ns 0x03 26 27 28 29 Minimum Four Activate Window Delay Time tFAWmin Least 300 oignificant Byte 30 SDRAM Optional Features 0x82 Bit 0 RZQ 6 Bit 1 RZQ 7 X Bit 6 Bit 2 Reserv
5. 78 79 52 80 Vss 81DQ32 82 DQ33 83 Vss 84 DQS4 85 0084 86 Vss 87 DQ34 88 DQ35 89 Vss 90 DQ40 Pin Configuration Back Side 91 41 121 55 151 Vss 92 Vss 122004 152 DM3 93 DQS5 123 005 153 NC 94 0085 124 154 Vss 95 Vss 125 155 0030 96 0042 126 156 0031 97 0043 127 Vss 157 Vss 98 Vss 128006 4158 CB4 99 0048 129007 159 5 1000049 130 160 Vss 101Vss 1310012 161 DM8 102 0086132 0013 162 NC 1030056 f133 Vss 163 Vss 104 55 134 1 164 6 1050950 165 CB7 1060051 136 Vss 1166 Vss 107 Vss 1370014 108 0056 138 0015 1168 RESET 1090957 13955 169 CKE1 110Vss 1400020 170 111 DQS7141 0021 171 A15 1120057 142055 172 14 113 55 143DM2 173 1140058 44 174 12 1150059 145 175 AQ 116Vss 1460022 176 Vpp 117 1470023 177 A8 118SCL 148Vass 178 AG 1198 2 149DQ28 179 120V4 1500029 180 181 1 182 183 184 185 186 Vpp 187 Event 188 189 Vpp 190 BA1 191 Vpp 192 RAS 193 S0 Identification DTM64305C 256Mx72 Performance range Clock Module Speed CL tncp trp 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64305C is a registered 256Mx72 memory module which conforms to JEDEC s DDR3 PC3 8500 standard The assembly is Dual Rank Each Rank is comprised of nine 128Mx8 DD
6. R3 Hynix SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C DQ62 DQ63 Vss Vppspp SA1 Pin Description CB 7 0 DQ 63 0 DQS 8 0 DQS 8 0 DM 8 0 CK 1 0 CK 1 0 CKE 1 0 ICAS RAS S 3 0 IWE A 15 0 BA 2 0 ODT 1 0 SA 2 0 SCL SDA Vss VREFDQ VREFCA Vit Event NC Function Data Check Bits Data Bits Differential Data Strobes Data Mask Differential Clock Inputs Clock Enables Column Address Strobe Row Address Strobe Chip Selects Write Enable Address Inputs Bank Addresses On Die Termination Inputs SPD Address SPD Clock Input SPD Data Input Output Ground Power SPD EEPROM Power Reference Voltage for DQ Reference Voltage for CA Termination Voltage Temperature Sensing No Connection Document 06536 Revision A 7 May 09 Dataram Corporation 2009 Page 1 DTM64305C Optimizing Value and Performance 2GB _ 240 Pin oRx8 Registered ECC DDR3 DIMM D Front view 133 35 5 250 9 50 0 374 30 00
7. ed Bit 7 DLL Off Mode Support 31 SDRAM Drivers Supported 0x05 Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Reserved Document 06536 Revision A 7 May 09 Dataram Corporation 2009 Page 9 DTM64305C Optimizing Value and Performance 2GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Module Nominal Height xOF Bit 4 Bit 0 Module Nominal Height in mm 29 h 30 Bit 7 Bits Reserved 0 61 Module Maximum Thickness 0x11 M Bit 3 Bit 0 Front in mm baseline thickness 1 mm Bit 7 Bit 4 Back in mm baseline thickness 1 62 Reference Raw Card Used 0x01 ll Bit 4 Bit 0 Reference Raw Bit 6 5 Reference Raw Card Revision Bit 7 Reserved 63 j Address Mapping from Edge Connector to DRAM 0x05 Bit 0 Rank 1 Mapping Registered DIMM Reserved 1 Bit 7 Bit 1 Reserved 0 UNUSED UNUSED 0x00 UNUSED 0x01 UNUSED 0x00 0x20 CRC Cyclical Redundancy Code CRC CRC 0x04 D om A T os A R 052 1040 6 0x36 4 3 0x33 0 5 0x35 146 147 0x20 UNUSED UNUSED 0x00 UNUSED UNUSED 0x00 Document 06536 Revision A 7 May 09 Dataram Corporation 2009 Page 10 DTM64305C Optimizing Value and Performance 2 _ 240 2Rx8 Re
8. gistered ECC DDR3 DIMM Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06536 Revision A 7 May 09 Dataram Corporation 2009 Page 11
9. k to peak noise on may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Unit Logical Low Logic 0 DC i 0 1 V AC Input Logic Levels Single Ended 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical Low Logic 0 Vner 0 175 V Document 06536 Revision A 7 May 09 Dataram Corporation 2009 Page 4 DTM64305C Optimizing Value and Performance 2GB _ 240 Pin oRx8 Registered ECC DDR3 DIMM Differential Input Logic Levels 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix 0 150 0 150 V Capacitance T4 25 C f 100 MHz 00163 0 CBI7 7 0058 0 DQS 8 0 Input Output Capacitance ZQ Capacitance DC Characteristics 0 to 70 C Voltage referenced to Vss 0 V Input Leakage Current 1 2 Any input 0 V VIN VDD Output Leakage Current OV lt VOUT VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and are disabled Document 06536 Revision A 7 May 09 Dataram Corpora
10. n A 7 May 09 Dataram Corporation 2009 Page 7 DTM64305C Optimizing Value and Performance 2GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 SPD Revision Key Byte DRAM Device Type 1 2 3 Key Byte Module Type Bit 3 Bit 0 Module Type RDIMM Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks Bit 3 Bit 0 Total SDRAM capacity in megabits 1Gb Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 5 SDRAM Addressing 0x11 Bit 2 Bit 0 Column Address Bits 10 Bit 5 Bit 3 Row Address Bits Bit 7 6 Reserved Reserved Module Organization Bit 2 Bit 0 SDRAM Device Width 8 Bits Bit 5 Bit 3 Number of Ranks 2 Rank Bit 7 6 Reserved 0 Module Memory Bus Width Bit 2 Bit 0 Primary bus width in bits 64 Bits Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved Fine Timebase FTB Dividend Divisor Bit 3 Bit 0 Fine Timebase FTB Divisor Bit 7 Bit 4 Fine Timebase FTB Dividend 10 Medium Timebase MTB Dividend 1 Medium Timebase MTB Divisor 12 SDRAM Minimum Cycle Time tCKmin 1 875ns Bit 0o CL 4 Bit 2 6 X Bit 3
11. old Time after DQS Strobe tu S ps DQ Input Pulse Width tw 400 ps 005 Output Access Time from Clock ps Write DQS High Level Width fos 04 06 Write DQS Low Level Width tos 04 O6 DQS Out Edge to Data Out Edge Skew was T m5 ps Data Input Setup Time Before DQS Strobe ts 30 DQS Falling Edge from Clock Hold Time ton 02 DGS Falling Edge to Clock Setup Time o tck avg Address and Command Hold Time after Clock ps Address and Command Setup Time before Clock tis OH ps Load Mode Command Cycle Time ee tck Active to Precharge Time ns Active to Active Auto Refresh Time 55 n Average Periodic Refresh Interval 0 C lt Tcase lt 85 C 0 7 78 Us Average Periodic Refresh Interval 85 lt lt 95 tno 07 8 Us Auto Refresh Row Cycle Time nooo ns Row Precharge Time DEM ae ns Read DQS Preamble Time tere 09 tck avg Read DQS Postamble Time tck avg Row Active to Row Active Delay tko Mex4nCK 75ns ns Internal Read to Precharge Command Delay tare Max 4nCK 7 5ns ns Write 098 Preamble Setup Time a MERIT Write DQS Postamble Time 0T tes Write Recovery Time p wa 15 n Internal Write to Read Command Delay lwTR Max 4nCK 7 5ns ns Notes 1 maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06536 Revisio
12. tion 2009 Page 5 DTM64305C Optimizing Value and Performance 2GB _ 240 Pin ORx8 Registered ECC DDR3 DIMM lbp Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss alue Precharge Current Operating One Operating current One bank ACTIVATE to READ to Precharge Current Precharge Power T PCIE ULL power down current Slow exit Ipp2P mA Down Current Precharge Power Iap2P power down current Fast exit MA Down Current Precharge Quiet xx Precharge quiet standby current Precharge Standby In 2N Precharge standby current 1664 mA Current n Active Power Down xx Active power down current Active Standby Active standby current Operating Burst Burst write operating current Operating Burst Burst read operating current Burst Refresh e Refresh current pen Self refresh temperature current MAX Tc 85 Operating Bank interleave Read lop7 All bank interleaved read current 2654 mA Current One module rank in this operation the rest in IDD2P slow exit All module ranks in this operation Document 06536 Revision A 7 May 09 Dataram Corporation 2009 Page 6 DTM64305C Optimizing Value and Performance 2GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM AC Operating Conditions Internal read command to first data ns CAS to CAS Command Delay Clock High Level Width Clock Low Level Width Data Input H
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