Dataram DTM64360A memory module
Contents
1. SDRAM Addressing Bit 2 Bit 0 Column Address Bits Bit 5 Bit 3 Row Address Bits Bit 7 6 Reserved Reserved Module Organization Bit 2 Bit 0 SDRAM Device Width Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved 0 Module Memory Bus Width Bit 2 Bit 0 Primary bus width in bits 64 Bits Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase FTB Dividend Divisor Bit 3 Bit 0 Fine Timebase FTB Divisor Bit 7 Bit 4 Fine Timebase FTB Dividend Medium Timebase MTB Dividend 8 MTB Medium Timebase MTB Divisor 0 125ns SDRAM Minimum Cycle Time tCKmin 1 5ns Reserved UNUSED 14 CAS Latencies Supported Least Significant Byte 0x3C Bit 0 CL 4 Bit 1 CL 2 5 Document 06122 Revision A 16 Dec 10 Dataram Corporation 2010 Page 8 D2 DATARAM DTM64360A NNNM GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Bit 2 CL 6 Bit 3 CL 7 Bit 4 CL 8 Bit 5 CL 9 Bit 6 CL 10 Bit 7 CL 11 lt gt lt gt lt CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved Minimum CAS Latency Time tAAmin 13 125ns Minimum Write Recovery Time tWRmin 15 0ns Minimu2. 16 Dec 10 Dataram Corporation 2010 Page 3 JoDATARAM Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability DTM64360A 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsroRAGE 55 100 C Ambient Temperature Operating TA 0 70 C DRAM Case Temperature Operating TcasE 0 95 C Voltage on Vpp relative to Vss Vbp 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V I O Reference Voltage VREFDQ 0 49 Vpp 0 50 Vpp 0 51 Vpp V 1 1 O Reference Voltage VREFCA 0 49 Vpp 0 50 Vpp 0 51 Voo V 1 Notes For Reference Vpp 2 15 mV The value of VREF is expected to equal one half VDD and to track variations in the VDD DC level Peak to peak noise on VREF may not exceed 1 of its DC value For Reference VREF VDD 2 15 mV DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin pc Vrer 0 1 Vpp V Logical Low Logic 0 ViL DC Vss
3. VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled a a ae a a a a a a a E a Document 06122 Revision A 16 Dec 10 Dataram Corporation 2010 Page 5 J2 DATARAM DTM64360A NNNM GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Test Condition Viaxi Unit Operating One Bank Active pO Operating current One bank ACTIVATE to PRECHARGE 1214 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Ipp1 PRECHARGE 1304 mA Precharge Current Precharge Power Precharge power down current Slow exit Down Current loo2P 230 HA Precharge Power Precharge power down current Fast exit Down Current loo2P Bes am Precharge Quiet Precharge quiet standby current Standby Current Ipo2Q 1073 mA Precharge Standby Precharge standby current Current Ipp2N 1304 mA Active Power Down Active power down current Current Ipo3P m MA Active Standby Active standby current Current Ipp3N 1079 mA Operating Burst Burst write operating current Write Current Ipo4W Lad Bus Operating Burst Burst read operating current Read Current Ioo4R 1619 ARA Burst Refresh Refresh current Current looS 330 MA Self Refresh Self refresh temperature current MAX Tc 85 C Current Ipp6 336 mA Operating Bank Interleave Read
4. Vrer 0 1 V AC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH AC Vrer 0 175 V Logical Low Logic 0 ViL AC Vrer 0 175 V ea ae CCS a a a a I a ee ci Document 06122 Revision A 16 Dec 10 Dataram Corporation 2010 Page 4 PDATARAM Optimizing Value and Performance DTM64360A 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High Vin piFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low ViL DiFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage E relative to VDD 2 Vix 9 150 29090 M Capacitance T4 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO Cck 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control SO CKEO ODTO C 1 5 2 5 DQ 63 0 CB 7 0 DQS 8 0 DQS 8 0 Input Output Capacitance DM 8 0 TDQS 17 9 Cio 1 5 2 5 pF DC Characteristics T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 18 18 pA 1 2 Any input 0 V VIN VDD Output Leakage Current lo 10 10 pA 2 3 OV VOUT lt
5. lan All bank interleaved read current 1979 mA Current Document 06122 Revision A 16 Dec 10 Dataram Corporation 2010 Page 6 JQDATARAM Optimizing Value and Performance DTM64360A 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay tccp 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 5 1 875 ns Clock Low Level Width cL avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe tou 65 ps DQ Input Pulse Width toipw 400 ps DQS Output Access Time from Clock tpasck 255 255 ps Write DQS High Level Width toasH 0 45 0 55 tcxiavg Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tek avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tup minimum of tcu or tci ns Address and Command Hold Time after Clock tin 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time tMRD 4 tck DQ to DQS Hold taH 0 38 tck avg Active to Precharge Time tras 36 O tREFI ns Active to Active Auto Refresh Time tre 49 125 ns RAS to CAS Delay trep 13 125 ns Av
6. 25DQ55 SA 2 0 SPD Address 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss SCL SPD Clock Input 17Vss 47 Vss 77 0pT1 t107Vss 137DQ14 167 NC TEST 197 Voo 227DQ60 SDA SPD Data Input Output 18 DQ10 48 Vr 78 Voo 108DQ56 138DQ15 168 RESET 198 93 NC 228DQ61 EVENT Temperature Sensing 19 DQ11 49 Vrr 79 82 NC 109 DQ57 139 Vss 169 CKE1 1199 Vss 229 Vss IRESET Reset for register and DRAMs 20Vss 50 CKEO 80 Vss 110Vss 140DQ20 170 Vpp 200DQ36 230 DM7 PAR_IN Parity bit for Addr Ctrl 21 DQ16 51 Vp 81DQ32 111 DOs7 i41DQ21 4171A15 201DQ37 231 TDQS16 ERR OUT Error bit for Parity Error 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 Vss 172 A14 202 Vss 232 Vss A12 BC Combination input Addr12 Burst Chop 23Vss 53 En Our 83Vss 113Vsg 143DM2 173 Vpp 203 DM4 233DQ62 A10 AP Combination input Addr10 Auto precharge 24 DQS254 Vp 84 DQs4 114 DQ58 144 TDQS11474 A12 BC 204 TDQS13 2324DQ63 Vss Ground 25 DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 175 AQ 205 Vss 235 Vss Vo Power 26Vss 56 A7 86 Vss 116Vss 146DQ22 176 Vpp 206DQ38 236 Vposro Vopsep SPD EEPROM Power 27 DQ18 57 Voo 87 DQ34 1177840 i47DQ23 177A8 207 DQ39 237 SA1 VREFDa Reference Voltage for DQ s 28DQ19 58A5 88 DQ35 118SCL 148 Vss 178 A6 208 Vss 238 SDA VnEFCA Reference Voltage for CA 29Vss 59A4 89 Vss 119SA2 149DQ28 179 Vpp 209 DQ44 239 Vsg Vor Termination Voltage 30 DQ24 60 Vpop 90 DQ40 120v 150DQ29 180A3 210DQ45 240 Vrr NC No Connection Not used SS SSS SS SS SS
7. 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06122 Revision A 16 Dec 10 Dataram Corporation 2010 Page 13
8. R8 O IDQSR8O DMR8O TDQSR170 CBR 7 0 O All 15 OHMS DQ 63 0 O O DQR 63 0 CB 7 0 O VW O CBR 7 0 DQS 8 0 O O DOQSR 8 0 DQS 8 0 O O DQSR 8 0 DM 8 0 O O DMRI 8 0 TDQS 17 9 O VW O TDQSR 17 9 GLOBAL SDRAM CONNECTS All 47 OHMS BA 2 0 R A 15 0 R IRASR ICASR IWER VTT All 47 OHMS CKEOR ODTOR RSO VTT TO SDRAMS All 22 OHMS SO w IRSO IS1 w BA 2 0 ww BA 2 0 R A 15 0 w I A 15 0 R IRAS WWw IRASR ICAS y ICASR ME w J INER CKE0 Q CKEOR opto w D ODTOR oa PAR IN w ERR_OUT CKO L R CLK O 120 OHMS ICKO I L R CLK O RESET pee SDRAMS All 240 OHMS za iid Vss DQSR4 O DQSR4 O DMR4O TDQSR13 0 2 z o O e DQR 39 32 O VO 7 0 RANK 0 DQSR5 O DQSR5 O DMR5O TDQSR140 DQR 47 40 O DQSR6 O DQSR6 O DMR6 O TDQSR15O DQR 55 48 O DQSR7 O DQSR7 O DMR7 O TDQSR16O DM 2 z TDQS TDQS ICS DQS DQS DQR 63 56 O 0 7 0 VDD All 36 OHMS 100 nF RCLKO E zm RCLKO VDD All 36 OHMS 100 nF LCLKO UAE LCLKO 75 OHMS CK1 O VW O_ CK1 DECOUPLING VDDSPD Serial PD VDD All Devices VREF DQ All SDRAMs Vss All Devices VREF CA All SDRAMs VTT F All SDRAMs C EVENT TEMPERATURE MONITOR SDA Scr SERIAL PD SAO SA1 SA2 Document 06122 Revision A
9. SSS eee a E Document 06122 Revision A 16 Dec 10 Dataram Corporation 2010 Page 1 J2 DATARAM DTM64360A NNNM 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Front view 133 35 5 250 9 50 0 374 30 00 1 181 k 17 30 0 681 O 5 00 0 197 en 5 175 47 00 71 00 0 204 1 850 2 795 123 00 4 843 Back view Side view 3 94 Max 0 155 Max Wi 4 00 Min 0 157 Min O NAMNNNNNNNMNNNNNNANNNNNNMNNNNNNNNNNNNNNNNNNNNN NNNMNNN NNNMNNN O i 1 27 10 RT 0 0500 40 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Ec SPELETMCP M r H se ee O 4H JoMs et Page 2 Document 06122 Revision A 16 Dec 10 Dataram Corporation 2010 D2 DATARAM DTM64360A 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Optimizing Value and Performance IRS0 O DQSROO DQSRO O DMROO TDQSR9O DQRI7 0 O DQSR1 O DQSR1O DMR1O TDQSR100 DQR 15 8 O TDQSR110 DQR 23 16 O DQSR3 IDQSR3 DMR3 TDQSRI20 7 DMN SON NN zo GU OO a a aa EF S DQR 31 24 V O 7 0 DQS
10. USED 120 121 Module Manufacturing Date UNUSED 122 125 Module Serial Number Cyclical Redundancy Code CRC Cyclical Redundancy Code CRC Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Z gt gt gt 136 Module Part Number 0x52 137 Module Part Number 0x41 138 Module Part Number 0x4D 139 Module Part Number 0x20 140 Module Part Number 0x36 141 Module Part Number 0x34 O A Document 06122 Revision A 16 Dec 10 Dataram Corporation 2010 Page 11 D2 DATARAM DTM64360A Optimizing Value and Performance 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM 142 Module Part Number 3 0x33 143 Module Part Number 6 0x36 144 Module Part Number 0 0x30 145 Module Part Number 0x20 146 147 Module Revision Code 0x20 148 DRAM Manufacturer ID Code Least Significant Byte UNUSED 0x00 149 DRAM Manufacturer ID Code Most Significant Byte UNUSED 0x00 pos Manufacturer s Specific Data UNUSED 0x00 Pin Open for customer use UNUSED 0x00 Document 06122 Revision A 16 Dec 10 Dataram Corporation 2010 Page 12 yee DTM64360A 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM 778 ee Value and Performance PYPDATARAM d BH Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609
11. erage Periodic Refresh Interval 0 C lt Tease lt 85 C tREFI 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C tREFI 3 9 us Auto Refresh Row Cycle Time treo 160 ns Row Precharge Time tre 13 125 ns Read DQS Preamble Time tRPRE 0 9 Note 1 tck avg Read DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay trtp Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twPsT 0 3 ck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min The maximum postamble is bound by tHZDQS max Document 06122 Revision A 16 Dec 10 Dataram Corporation 2010 Page 7 D2 DATARAM DTM64360A NNNM 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Function Value Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 SPD Revision Rev 1 0 Key Byte DRAM Device Type DDR3 SDRAM Key Byte Module Type Bit 3 Bit 0 Module Type RDIMM Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks Bit 3 Bit 0 Total SDRAM capacity in megabits Bit 6 Bit 4 Bank Address Bits Bit 7 Reserved
12. m RAS to CAS Delay Time tRCDmin 13 125ns Minimum Row Active to Row Active Delay Time tRRDmin 6 0ns Minimum Row Precharge Delay Time tRPmin 13 125ns Upper Nibbles for tRAS and tRC Bit 3 Bit 0 tRAS Most Significant Nibble Bit 7 Bit 4 tRC Most Significant Nibble Minimum Active to Precharge Delay Time tRASmin Least Significant Byte 23 B Active to Active Refresh Delay Time tRCmin Least Significant 49 125ns 0x89 Minimum Refresh Recovery Delay Time tRFCmin Least Significant 160 0ns 24 Byte 0x00 25 Minimum Refresh Recovery Delay Time tRFCmin Most Significant Byte 160 0ns 0x05 26 Minimum Internal Write to Read Command Delay Time tWTRmin 7 5ns 0x3C 27 Minimum Internal Read to Precharge Command Delay Time tRTPmin 7 5ns 0x3C Upper Nibble for tFAW 28 Bit 3 Bit 0 tFAW Most Significant Nibble 0 0x00 Bit 7 Bit 4 Reserved 0 29 Br Four Activate Window Delay Time tFAWmin Least Significant 30 0ns OxFO SDRAM Optional Features Bit 0 RZQ 6 X 30 Bit 1 RZQ 7 X 0x83 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support Document 06122 Revision A 16 Dec 10 Dataram Corporation 2010 Page 9 D2 DATARAM DTM64360A NNNM GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM SDRAM Drivers Supported Extended Temperature Range X Extended Temperature Refresh Rate Auto Self Refresh ASR X 31 On die Thermal Sen
13. rved 0 69 SSTE32882 RC1 MS Nibble RCO LS Nibble UNUSED 0x00 Document 06122 Revision A 16 Dec 10 Dataram Corporation 2010 Page 10 D2 DATARAM DTM64360A NNNM GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM SSTE32882 RC3 MS Nibble RC2 LS Nibble Drive Strength Command Address 70 Bit 1 Bit 0 RC2 DA3 4 Value RESERVED 0x00 Bit 3 Bit 2 RC2 DBAO 1 Value RESERVED Bit 5 Bit 4 RC3 DA4 3 value Command Address A Outputs Light Bit 7 Bit 6 RC3 DBAO 1 value Command Address B Outputs Light SSTE32882 RC5 MS Nibble RC4 LS Nibble Drive Strength Control and Clock Bit 1 Bit 0 RC4 DA3 4 Control Signals A Outputs Light Bit 3 Bit 2 RCA DBAO 1 Control Signals B Outputs Light Bit 5 Bit 4 RC5 DA4 3 value Y1 V1 and Y3 Y3 Clock Outputs Light Bit 7 Bit 6 RC5 DBAO 1 value YO YO and Y2 Y2 Clock Outputs Light SSTE32882 RC7 MS Nibble RC6 LS Nibble UNUSED SSTE32882 RC9 MS Nibble RC8 LS Nibble UNUSED SSTE32882 RC11 MS Nibble RC10 LS Nibble UNUSED SSTE32882 RC13 MS Nibble RC12 LS Nibble UNUSED SSTE32882 RC15 MS Nibble RC14 LS Nibble UNUSED Module Specific Section UNUSED Module Specific Section UNUSED Module Specific Section UNUSED Module Manufacturer ID Code Least Significant Byte 118 Module Manufacturer ID Code Most Significant Byte 119 Module Manufacturing Location UN
14. sor ODTS Readout 0x05 Reserved Reserved Reserved Partial Array Self Refresh PASR Module Thermal Sensor 32 Bit 6 Bit 0 Thermal Sensor Accuracy 0 0x80 Bit 7 Thermal Sensor With TS SDRAM Device Type Bit 6 Bit 0 Non Standard Device Description 0 33 Bit 7 SDRAM Device Type Std Mono 0x00 34 59 Reserved UNUSED 0x00 Module Nominal Height 60 Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 Ox0F Bit 7 Bits Reserved 0 Module Maximum Thickness Bit 3 Bit 0 Front in mm baseline thickness 1 mm Bit 7 Bit 4 Back in mm baseline thickness 1 mm Reference Raw Card Used Bit 4 Bit 0 Reference Raw Card Bit 6 Bit 5 Reference Raw Card Revision Bit 7 Reserved Registered DIMM Module Attributes Bit 1 Bit 0 of Registers used on RDIMM 1 Register Bit 3 Bit 2 of Rows of DRAMs on RDIMM 1 Row Bit 7 Bit 4 Reserved 0 RDIMM Thermal Heat Spreader Solution 64 Bit 6 Bit 0 Heat Spreader Thermal Characteristics 0 0x00 Bit 7 Heat Spreader Solution No HS 65 Register Manufacturer ID Code Least Significant Byte Optional UNUSED 0x00 66 Register Manufacturer ID Code Most Significant Byte Optional UNUSED 0x00 67 Register Revision Number Optional y OxFF Register Type 68 Bit 2 0 Support Device SSTE32882 9x00 Bit 7 3 Rese
15. ully RoHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 Vaeroa 31 DQ25 61 A2 91 DQ41 121 Vss 151 Vss 181A1 211 Vss CB 7 0 Data Check Bits 2 Vss 32Vss 62 Voo 92 Vss i22DQ4 1452DM3 182 Voo 212 DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 93 DQS5123DQ5 153 TDQS12 183 Voo 213 TDQS14 DQS B 0 DQS 8 0 Differential Data Strobes 4 DQ1 34DQS3 64 ICK1 94 DQSS5 124 Vss 154 Vss 184 CKO 214 Vss DM 8 0 Data Mask 5 Vss 35 Vss 65 Voo 95 Vs i25DMO 155DQ30 185 CKO 215DQ46 TDQS 17 9 Termination strobes 6 DQS036 DQ26 66 Vop o6 DQ42 126 TDQs9 156 DQ31 186 Voo 216DQ47 CK t0 CK 1 0 Differential Clock Inputs 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 EVENT 217 Vss CKE 1 0 Clock Enables 8 Vss 38 Vss 68Par In 98 Vss 128DQ6 158CB4 188 AO 218DQ52 CAS Column Address Strobe 9 DQ2 39CBO 69 VDD 99 po48 i29DQ7 459CcB5 189 Voo 219DQ53 RAS Row Address Strobe 10DQ3 40CB1 70A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss IS 3 0 Chip Selects 11Vss 141 Vss 71 BAO 101Vss 131DQ12 161DM8 191 Voo 221 DM6 WE Write Enable 12DQ8 42 DQS8 72 Vop 102 DQse i32DQ13 t62 TDQs17 M92 RAS 222 TDQS15 A 15 0 Address Inputs 13DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 163 Vss 193 S0 223 Vss BA 2 0 Bank Addresses 14Vss 44 Vs 74 ICAS 104Vss t34DM1 464CB6 194 Voo 224DQ54 ODT 1 0 On Die Termination Inputs 15 DQS1 45 CB2 75 Vop 105 DQ50 135 TDQS10465 CB7 195ODTO 2
16. ye DTM64360A MM 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Identification DTM64360A 256Mx72 2GB 1Rx8 PC3 10600R 9 10 A0 Performance range Clock Module Speed CL trep trp 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Features Description 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm DTM64360A is a registered 256Mx72 memory module high which conforms to JEDEC s DDR3 PC3 10600 Operating Voltage 1 5V 0 075 standard The assembly is a Single Rank The Rank is comprised of nine 256Mx8 DDR3 1333 Hynix SDRAMs VO Type setis One 2K bit EEPROM is used for Serial Presence On board I2C temperature sensor with integrated serial Detect and a combination register PLL with Address presence detect SPD EEPROM and Command Parity is also used Data Transfer Rate 10 6 Gigabytes sec Both output driver strength and input termination Data Bursts 8 and burst chop 4 mode impedance are programmable to maintain signal E integrity on the I O signals in a Fly by topology ZQ Calibration for Output Driver and On Die Termination ODT A thermal sensor accurately monitors the DIMM module Programmable ODT Dynamic ODT during Writes and can prevent exceeding the maximum operating t t f i Programmable CAS Latency 6 7 8 and 9 Bins Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 15 10 3 F
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