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Intel Pentium SL2YM processor

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1. 2X 0 058 2x 0 136 Left 0 005 0 005 M 2X0 253 001056a Datasheet 47 Pentium II Processor at 350 MHz 400 MHz and 450 MHz 48 Figure 22 intel Pentium II Processor S E C C Package Latch Arm Extended Thermal Plate and Cover Detail Dimensions Reference Dimensions Only 0 075 4 7 MA 0 236 f 4 0 122 0 113 d i j 0 084 J Detail A Detail B Bottom Side View a k 0 120 Min 0 316 gt e 0 116 0 082 gt 0 216 0 291 0 276 Tod 45 jJ Detail C Detail D Detail E 001057a Note All dimensions without tolerance information are considered reference dimensions only Datasheet a ntel Pentium II Processor at 350 MHz 400 MHz and 450 MHz Figure 23 Pentium II Processor S E C C Package Extended Thermal Plate Attachment Detail Dimensions m U B J s P bi a Q eo on N e eo Gi Hi 8B x g 3 eU o cb x a o S Oo YI O 8 x ai ts d st 88 os S fluo i OQO a E e chy O 8 Cp H Cp amp p 2 Y a oo oo kal e kal e e e e e 9 8 8 8 9 e e e eo e H H g 8 g e o D A e eo eo o eo Datasheet 49 a Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel A Figure 24 Pentium II Processor S E C C Package
2. 000888 Fan Heatsink Power and Signal Specifications Description Min Typ Max 12 V 12 volt fan power supply 9V 12 V 13 8 V Ic Fan current draw 100 mA SENSE SENSE frequency motherboard should pull this pin 2 pul f luti up to appropriate VCC with resistor pres per Ta Tevo usan Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Figure 48 Recommended Motherboard Power Header Placement Relative to Fan Power Connector and Pentium II Processor Motherboard fan power header should be positioned within 4 75 inches of the fan power connector lateral distance Fan power connector location 1 56 inches above motherboard Table 40 Motherboard Fan Power Connector Location Fig Ref Labels Dimensions Inches Min Typ Max y Aproximate perpendicular distance of the fan power 1 44 connector from the center of the 242 contact slot connector w Aproximate parallel distance of the fan power connector 145 from the edge of the 242 contact slot connector j Lateral distance of the motherboard fan power header X 4 75 location from the fan power connector 6 4 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor 6 4 1 Boxed Processor Cooling Requirements The boxed processor will be cooled with a fan heatsink The boxed processor fan heatsin
3. Edge Fingers BCLK at BCLK at Core Logic 000807 For Figure 6 through Figure 12 the following apply l 2 Figure 6 through Figure 12 are to be used in conjunction with Table 9 through Table 20 All AC timings for the AGTL signals at the processor edge fingers are referenced to the BCLK rising edge at 0 50 V This reference is to account for trace length and capacitance on the processor substrate allowing the processor core to receive the signal with a reference at 1 25 V All AGTL signal timings address bus data bus etc are referenced at 1 00 V at the processor edge fingers All AC timings for the AGTL signals at the processor core pins are referenced to the BCLK rising edge at 1 25 V All GTL signal timings address bus data bus etc are referenced at 1 00 V at the processor core pins All AC timings for the CMOS signals at the processor edge fingers are referenced to the BCLK rising edge at 0 50 V This reference is to account for trace length and capacitance on the processor substrate allowing the processor core to receive the signal with a reference at 1 25 V All CMOS signal timings compatibility signals etc are referenced at 1 25 V at the processor edge fingers All AC timings for the APIC I O signals at the processor edge fingers are referenced to the PICCLK rising edge at 0 7 V All APIC I O signal timings are referenced at 1 25 V at the processor edge fingers All AC timi
4. sssssssessssseseseeeeeeen enne 12 2 2 2 AutoHALT Powerdown State State 2 sss 12 2 2 3 Stop Grant State State 3 12 2 2 4 HALT Grant Snoop State State A 13 2 2 5 Sleep State State b seien rei eee dian nuc 13 2 2 6 Deep Sleep State State 6 eesssessssseeeereeeenennnnn 13 2 227 Olock Gontrol iiu Ed eres IY EO se eR EEEEE EE aad 14 2 8 Power and Ground Pins sss eren enne errnnrtret nnne 14 2 4 Decoupling Guidelines kA EEN 14 2 4 1 Processor VCCoongg Decoupling sssscessssscsssrresssrrnnsrrinnnnensrinnnnnnnnnnnnnt 15 2 4 2 Processor System Bus AGTL Decoupling esses 15 2 5 Processor System Bus Clock and Processor Clocking 15 2 5 1 Mixing Processors of Different Freouences 15 2 6 Voltage Identification ener enne 15 2 7 Processor System Bus Unused Pins seen 17 2 8 Processor System Bus Signal Groupe ssssseesssssriesssserissssirrssrirrnsrrinnnnnennsnsenn 17 2 8 1 Asynchronous vs Synchronous for System Bus Signals 19 2 8 2 System Bus Frequency Select Signal 100 663 19 2 9 Test Access Port TAP CGonnecton 20 2 10 Maximum Ratings ener en nnne nennen nen 20 2 11 Processor DC Gpecificaitons nnne 21 2 12 AGTL System Bus Specifications sese 24 2 13 System Bus AC Specifications eene 25 System
5. If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through Stop Grant State If RESET is driven active while the processor is in the Sleep State the SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the Reset sequence While in the Sleep state the processor is capable of entering its lowest power state the Deep Sleep state by stopping the BCLK input see Section 2 2 6 Once in the Sleep or Deep Sleep states the SLP pin can be deasserted if another asynchronous system bus event occurs The SLP pin has a minimum assertion of one BCLK period Deep Sleep State State 6 The Deep Sleep state is the lowest power state the processor can enter while maintaining context The Deep Sleep state is entered by stopping the BCLK input after the Sleep state was entered from the assertion of the SLP pin The processor is in Deep Sleep state immediately after BLCK is stopped It is recommended that the BLCK input be held low during the Deep Sleep State Stopping of the BCLK input lowers the overall current consumption to leakage levels To re enter the Sleep state the BLCK input must be restarted A period of 1 ms to allow for PLL stabilization must occur before the processor can be considered to be in the Sleep state Once in the S
6. A57 D 24 AGTL I O A112 RS 1 AGTL Input B56 D 25 AGTL I O B111 RS 2 AGTL Input B55 D 26 AGTL I O B115 RSP AGTL Input A56 D 27 AGTL T O B101 SLOTOCC SC 242 Occupied B52 D 28 AGTL T O B8 SLP CMOS Input B54 D 29 AGTL I O B3 SMI CMOS Input ASS D 30 AGTL I O B6 STPCLK CMOS Input A53 D 31 AGTL I O B7 TCK JTAG Input B51 D 32 AGTL UO A9 TDI JTAG Input ASI D 33 AGTL I O All TDO JTAG Output B48 D 34 AGTL I O A13 TESTHI CMOS Test Input A52 D 35 AGTL T O A15 THERMTRIP CMOS Output B46 D 36 AGTL I O B10 TMS JTAG Input A49 D 37 AGTL UO A104 TRDY AGTL Input B50 D 38 AGTL I O Bll TRST JTAG Input A45 D 39 AGTL I O B13 VCC_CORE Processor core VCC B47 D 40 AGTL I O B17 VCC_CORE Processor core VCC B42 D 41 AGTL HO B25 VCC_CORE Processor core VCC A43 D 42 AGTL I O B29 VCC_CORE Processor core VCC A48 D 43 AGTL I O B33 VCC_CORE Processor core VCC B44 D 44 AGTL I O B37 VCC_CORE Processor core VCC 63 Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 36 Signal Listing in Order by Signal Name Sheet 4 of 4 6 0 Intel Pin No Pin Name Signal Buffer Type Pin No Pin Name Signal Buffer Type A44 D 45 AGTL I O B45 VCC_CORE Processor core VCC A39 D 46 AGTL I O B49 VCC_CORE Processor core VCC B43 D 47 AGTL HO B53 VCC_CORE
7. EMI pins should be connected to motherboard ground and or to chassis ground through zero ohm 0 resistors The zero ohm resistors should be placed in close proximity to the Pentium II processor connector The path to chassis ground should be short in length and have a low impedance These pins are used for EMI management purposes FERR The FERR Floating point Error signal is asserted when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting FLUSH When the FLUSH input signal is asserted processors write back all data in the Modified state from their internal caches and invalidate all internal cache lines At the completion of this operation the processor issues a Flush Acknowledge transaction The processor does not cache any new data while the FLUSH signal remains asserted FLUSHE is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O Write bus transaction On the active to inactive transition of RESET each processor samples FLUSH to determine its power on configuration See P6 Family of Processors Hardware Developer s Manual Order Number 244001 for details HIT HITM Lo Lo The HIT Snoop Hit and HITM Hit Mod
8. Extended Thermal Plate Attachment Detail Dimensions Continued fof 0 0032 1 000 x 1 000 L TT T NJ WM AO Oe E e 1 250 p a 2 500 gt re Figure 25 Pentium II Processor Substrate S E C C Package Edge Finger Contact Dimensions Thermal Plate X CO CO 17 H o Oo Oo co poe QO O O O Pin A1 5 old y am pa AS oe V I tam VV NP Substrate See Detail A in JL ogo 007 ext Figure S 005 2 835 a 1 85 WI al Iw 2 992 008 bit 2 01 008 lt 5 000 gt X NOTE All dimensions without tolerance information are considered reference dimensions only 007 vsd Datasheet 50 In Pentium II Processor at 350 MHz 400 MHz and 450 MHz Figure 26 Pentium II Processor Substrate S E C C Package Edge Finger Contact Dimensions Detail A 1 098 098 ei Pin A74 010 T ER 008 wo tM JM O seos VCO MI I 039 ai ke i DN Wl Je ta 074 002 Al 121 X 0 16 002 SEI dL dE NOTE 1 All d imensions without tole
9. Fower Cable m D Connector i Fan Heatsink E N7 S E C C 2 Processor Package d 242 Contact Slot Connector 31 Datasheet 67 Pentium II Processor at 350 MHz 400 MHz and 450 MHz 68 Figure 43 Top View Air Space Requirements for the Boxed Processor i E LIE Li nuca Pug K 5 ires P reir i Eni t t e Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 37 Boxed Processor Fan Heatsink Spatial Dimensions 6 2 2 6 2 3 Datasheet Fig Ref Refers to Label Figure Dimensions Inches Min Typ Max A Figure 39 S E C C Fan Heatsink Depth off processor extended 11 13 thermal plate Figure 39 S E C C Fan Heatsink Height Above Motherboard Note 1 0 5 Figure 40 S E C C Fan Heatsink Height 2 1 2 2 Figure 40 S E C C Fan Heatsink Width plastic shroud only 4 8 4 9 S E C C Power Cable Connector Location From Edge B Figura of Fan Heatsink Shroud bs Se F Figure 41 S E C C 2 Fan Heatsink Depth off processor substrate 1 3 1 4 G Figure 41 S E C C 2 Fan Heatsink Height Above Motherboard 0 4 0 6 H Figure 42 S E C C 2 Fan Heatsink Height 2 0 2 2 I Figure 42 S E C C 2 Fan Heatsink Width plastic shroud only 4 7 4 8 e S E C C 2 Power Cable Connector Locati
10. A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability For unused pins it is suggested that 10 KQ resistors be used for pull ups except for PICD 1 0 discussed above and 1 kQ resistors be used as pull downs Processor System Bus Signal Groups In order to simplify the following discussion the Pentium II processor system bus signals have been combined into groups by buffer type All Pentium II processor system bus outputs are open drain and require a high level source provided externally by the termination or pull up resistor AGTL input signals have differential input buffers which use Vnzr as a reference signal AGTL output signals require termination to 1 5 V In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving EMI pins should be connected to motherboard ground and or to chassis ground through zero ohm 0Q resistors The OQ resistors should be placed in close proximity to the SC 242 connector The path to chassis ground should be short in length and have a low impedance The CMOS Clock APIC and TAP inputs can each be driven from ground to 2 5 V The CMOS APIC and TAP outputs are open drain and should be pulled high to 2 5 V This ensures not
11. Pentium Il Processor at 350 MHz 400 MHz and 450 MHz Product Features Available at 350 MHz 400 MHz and 450 MHz frequencies System bus frequency at 100 MHz Binary compatible with applications running on previous members of the Intel microprocessor line Dynamic execution micro architecture Datasheet Optimized for 32 bit applications running on advanced 32 bit operating systems Single Edge Contact Cartridge S E C C and S E C C 2 packaging technology the S E C cartridges deliver high performance with improved handling protection and socketability Integrated high performance 16 KB Dual Independent Bus architecture instruction and 16 KB data nonblocking Separate dedicated external System Bus and dedicated internal high speed cache e e cache bus e Available with integrated 512 KB unified nonblocking level two cache Enables systems which are scaleable up to two processors Error correcting code for System Bus data Power Management capabilities System Management mode Multiple low power states The Intel Pentium II processor is designed for high performance desktops and for workstations and servers It is binary compatible with previous Intel Architecture processors The Pentium II processor provides the best performance available for applications running on advanced operating systems such as Windows 95 Windows NT and UNIX This is achieved by integrating the best attributes of Intel processo
12. Signal Listing in Order by Signal Name Sheet 2 of 4 Intel Pin No Pin Name Signal Buffer Type Pin No Pin Name Signal Buffer Type B87 Ast 21 AGTL HO A30 GND Vss A85 A 22 AGTL I O A34 GND Vss A87 A 23 AGTL HO A38 GND Vss B83 A 24 AGTL I O A42 GND Vss B88 A 25 AGTL I O A46 GND Vss B82 A 26 AGTL I O A50 GND Vss A84 A 27 AGTL I O A54 GND Vss B84 A 28 AGTL I O A58 GND Vss B80 A 29 AGTL I O A62 GND Vss A81 A 30 AGTL I O A66 GND Vss A83 A 31 AGTL I O A70 GND Vss B79 A 32 AGTL HO A74 GND Vss A79 A 33 AGTL I O A78 GND Vss A80 A 34 AGTL I O A82 GND Vss B78 A 35 AGTL HO A86 GND Vss A5 A20M CMOS Input A90 GND Vss A115 ADS AGTL I O A94 GND Vss B118 AERR AGTL I O A98 GND Vss A117 AP 0 AGTL HO A102 GND Vss B116 AP 1 AGTL HO A106 GND Vss A75 BCLK Processor Clock Input A110 GND Vss A77 BERR AGTL I O A114 GND Vss A24 BINIT AGTL HO A118 GND Vss A101 BNR AGTL I O B110 HIT AGTL I O B19 BP 2 AGTL I O A109 HITM AGTL I O A21 BP 3 AGTL I O A4 IERR CMOS Output A23 BPM 0 AGTL HO A8 IGNNE CMOS Input B24 BPM 1 AGTL I O B4 INIT CMOS Input A103 BPRI AGTL Input A17 LINT O INTR CMOS Input A76 BRO AGTL I O B16 LINT 1 NMI CMOS Input B75 BRI AGTL Input B106 LOCK AGTL I O B72 D 0 AGTL I O B18 PICCLK APIC Clock In
13. TRDY The TRDY Target Ready signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRD Y must connect the appropriate pins of all Pentium II processor system bus agents TRST The TRST Test Reset signal resets the Test Access Port TAP logic TRST must be driven low during power on Reset This can be done with a 680 ohm pull down resistor VID 4 0 The VID 4 0 Voltage ID pins can be used to support automatic selection of power supply voltages These pins are not signals but are either an open circuit or a short circuit to VSS on the processor The combination of opens and shorts defines the voltage required by the processor The VID pins are needed to cleanly support voltage specification variations on Pentium II processors See Table 1 for definitions of these pins The power supply must supply the voltage that is requested by these pins or disable itself 7 2 Signal Summaries Table 42 through Table 45 list attributes of the Pentium II processor output input and I O signals Table 42 Output Signals Name Active Level Clock Signal Group FERR Low Asynch CMOS Output TERR Low Asynch CMOS Output PRDY Low BCLK AGTL Output SLOTOCC Low Asynch Power Other TDO High TCK JTAG Output THERMTRIP Low Asynch CMOS Output VID 4 0 High Asynch Power Other Datasheet 81 Pentium II Processor at 350
14. A minimum of 3 clocks must be guaranteed between two active to inactive transitions of TRDY 6 RESET can be asserted active asynchronously but must be deasserted synchronously 7 Specification is for a minimum 0 40 V swing 8 Specification is for a maximum 1 0 V swing 9 After Veccore Veci2 and BCLK become stable Table 13 System Bus AC Specifications AGTL Signal Group at the Processor Core Pins has T Parameter Min Max Unit Figure Notes T7 AGTL Output Valid Delay 0 20 3 45 ns 7 4 T8 AGTL Input Setup Time 2 10 ns 8 5 6 7 T9 AGTL Input Hold Time 0 85 ns 8 8 T10 RESET Pulse Width 1 00 ms 10 6 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 These specifications are tested during manufacturing 3 All AC timings for the AGTL signals are referenced to the BCLK rising edge at 1 25 V at the processor core pin All AGTL signal timings compatibility signals etc are referenced at 1 00 V at the processor core pins 4 Valid delay timings for these signals are specified into 25Q to 1 5 V and with VREF at 1 0 V 5 A minimum of 3 clocks must be guaranteed between two active to inactive transitions of TRDY 6 RESET can be asserted active asynchronously but must be deasserted synchronously 7 Specification is for a minimum 0 40 V swing 8 Specification is for a maximum 1 0 V swing 9 This should be me
15. D 61 AGTL I O B32 D 63 AGTL I O A33 D 55 AGTL I O B33 VCC_CORE Processor core VCC A34 GND Vss B34 D 56 AGTL I O A35 D 60 AGTL I O B35 D 50 AGTL I O A36 D 53 AGTL I O B36 D 54 AGTL I O A37 D 57 AGTL I O B37 VCC_CORE Processor core VCC A38 GND Vss B38 D 59 AGTL HO A39 D 46 AGTL I O B39 D 48 AGTL HO A40 D 49 AGTL I O B40 D 52 AGTL I O A41 D 51 AGTL I O B41 EMI EMI Management A42 GND Vss B42 D 41 AGTL I O A43 D 42 AGTL HO B43 D 47 AGTL I O A44 D 45 AGTL I O B44 D 44 AGTL I O A45 D 39 AGTL I O B45 VCC_CORE Processor core VCC A46 GND Vss B46 D 36 AGTL I O A47 Reserved Reserved for Future Use B47 D 40 AGTL I O A48 D 43 AGTL I O B48 D 34 AGTL I O A49 D 37 AGTL I O B49 VCC_CORE Processor core VCC ASO GND Vss B50 D 38 AGTL HO ASI D 33 AGTL HO B51 D 32 AGTL HO A52 D 35 AGTL I O B52 D 28 AGTL I O A53 D 31 AGTL I O B53 VCC_CORE Processor core VCC A54 GND Vss B54 D 29 AGTL I O A55 D 30 AGTL I O B55 D 26 AGTL I O A56 D 27 AGTL I O B56 D 25 AGTL I O A57 D 24 AGTL I O B57 VCC_CORE Processor core VCC A58 GND Vss B58 D 22 AGTL I O A59 D 23 AGTL I O B59 D 19 AGTL I O A60 D 21 AGTL I O B60 D 18 AGTL I O A61 D 16 AGTL I O B61 EMI EMI Management A62 GND Vss B62 D 20 AGTL I O A63 D 13 AGTL I O B63 D 17 AGTL I O A64 D 11 AGTL I O B64 D 15 AGTL I O A65 D 10 AGTL I O B65 VCC_CORE Processor core VC
16. MHz 400 MHz and 450 MHz 82 Table 43 Intel Input Signals Name Active Level Clock Signal Group Qualified A20M Low Asynch CMOS Input Always BPRI Low BCLK AGTL Input Always BRI1I Low BCLK AGTL Input Always BCLK High Clock Always DEFER Low BCLK AGTL Input Always FLUSH Low Asynch CMOS Input Always IGNNE Low Asynch CMOS Input Always INIT Low Asynch CMOS Input Always INTR High Asynch CMOS Input APIC disabled mode LINT 1 0 High Asynch CMOS Input APIC enabled mode NMI High Asynch CMOS Input APIC disabled mode PICCLK High APIC Clock Always PREQ Low Asynch CMOS Input Always PWRGOOD High Asynch CMOS Input Always RESET Low BCLK AGTL Input Always RS 2 0 Low BCLK AGTL Input Always RSP Low BCLK AGTL Input Always SLP Low Asynch CMOS Input During Stop Grant state SMI Low Asynch CMOS Input STPCLK Low Asynch CMOS Input TCK High JTAG Input TDI High TCK JTAG Input TESTHI High Asynch Power Other Always TMS High TCK JTAG Input TRST Low Asynch JTAG Input TRDY Low BCLK AGTL Input NOTE 1 Synchronous assertion with active TDRY ensures synchronization Datasheet n Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 44 Input Output Signals Single Driver Name Active Level Clock Signal Group Qualified 100 663 Low Asynch Power Other Always A 35 3 Lo
17. Processor core VCC B39 D 48 AGTL HO B57 VCC_CORE Processor core VCC A40 D 49 AGTL I O B65 VCC_CORE Processor core VCC B35 D 50 AGTL I O B69 VCC_CORE Processor core VCC A41 D 51 AGTL I O B73 VCC_CORE Processor core VCC B40 D 52 AGTL I O B77 VCC_CORE Processor core VCC A36 D 53 AGTL I O B85 VCC_CORE Processor core VCC B36 D 54 AGTL I O B89 VCC_CORE Processor core VCC A33 D 55 AGTL I O B93 VCC_CORE Processor core VCC B34 D 56 AGTL HO B97 VCC_CORE Processor core VCC A37 D 57 AGTL I O B105 VCC_CORE Processor core VCC B31 D 58 AGTL I O B113 VCC L2 Other Vcc B38 D 59 AGTL I O B117 VCC L2 Other Vcc A35 D 60 AGTL I O B121 VCC_L2 Other Vcc A32 D 61 AGTL I O Al VCC_VTT AGTL VTT Supply B30 D 62 AGTL I O A3 VCC VTT AGTL VTT Supply B32 D 63 AGTL I O B5 VCC VTT AGTL VTT Supply Alll DBS Y AGTL HO B9 VCC VTT AGTL VTT Supply A105 DEFER AGTL Input B109 VCC5 Other VCC A25 DEP 0 AGTL I O B120 VID 0 Voltage Identification A27 DEP 1 AGTL I O A120 VID 1 Voltage Identification B26 DEP 2 AGTL I O A119 VID 2 Voltage Identification A28 DEP 3 AGTL I O B119 VID 3 Voltage Identification B27 DEP 4 AGTL I O A121 VID 4 Voltage Identification Boxed Processor Specifications 6 1 64 Introduction The Pentium II processor is also offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from motherboards and components Boxed Pentium II p
18. fingers and to the processor core Vcccogg must return to within the static voltage specification within 100 Us after a transient event 10 These are the tolerance requirements across a 20 MHz bandwidth at the processor edge fingers The requirements at the processor edge fingers account for voltage drops and impedance discontinuities at the processor edge fingers and to the processor core Vcccogg must return to within the static voltage specification within 2 Us after a transient event 11 These are estimated values not actual measurements 12 Max Icc measurements are measured at Vcc max voltage 95 C 2 C under maximum signal loading conditions The Max Icc currents specified do not occur simultaneously under the stress measurement condition 13 Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output voltage at maximum current output is no greater than the nominal i e typical voltage level of Vcccogg Veccogg Typ In this case the maximum current level for the regulator IcccoRg REG can be reduced from the specified maximum current Icccore Max and is calculated by the equation IcccorE_REG Icccong Max X Veccong rv Vcccogg rvp Veccong Tolerance Transient 14 The current specified is the current required for a single Pentium II processor A similar amount of current is drawn through the termination resistors on the opposite end of the AGTL bus unless single ended ter
19. in Figure 16 for the non AGTL signal group Figure 16 Non AGTL Overshoot Undershoot Settling Limit and Ringback Vg No Settling Limit Overshoot Rising Edge Ringback Falling Edge Ringback Settling Limit 000767b 40 Datasheet Intel 3 3 1 3 3 2 Table 25 Table 26 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Overshoot Undershoot Guidelines Overshoot or undershoot is the absolute value of the maximum voltage above the nominal high voltage or below Vss The overshoot undershoot guideline limits transitions beyond Vcc or Vss due to the fast signal edge rates See Figure 16 for non AGTL signals The processor can be damaged by repeated overshoot events on 2 5 V tolerant buffers if the charge is large enough i e if the overshoot is great enough However excessive ringback is the dominant detrimental system timing effect resulting from overshoot undershoot i e violating the overshoot undershoot guideline will make satisfying the ringback specification difficult The overshoot undershoot guideline is 0 7 V and assumes the absence of diodes on the input These guidelines should be verified in simulations without the on chip ESD protection diodes present because the diodes will begin clamping the 2 5 V tolerant signals beginning at approximately 0 7 V above the 2 5 V supply and 0 7 V below Vss If signals are not reaching the clamp
20. is called the SC 242 connector in this and other documentation Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel Figure 1 1 1 1 1 1 Second Level L2 Cache Implementations Processor Core Processor Core L2 Pentium Pro Processor Pentium II Processor Dual Cavity Substrate and Components Package Terminology In this document a symbol after a signal name refers to an active low signal This means that a signal is in the active state based on the name of the signal when driven to a low level For example when FLUSH is low a flush has been requested When NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHEL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level The term system bus refers to the interface between the processor system core logic a k a the AGPset components and other bus agents The system bus is a multiprocessing interface to processors memory and I O The term cache bus refers to the interface between the processor and the L2 cache components TagRAM and BSRAM s The cache bus does NOT connect to the system bus and is not visible to other agents on the system bus S E C Cart
21. only correct operation for current Pentium II processors but compatibility for future Pentium II products as well See Table 2 for recommended pull up resistor values on each CMOS signal 150Q resistors are expected on the PICD 1 0 lines other values in Table 2 are specified for proper logic analyzer and test mode operation only 17 Pentium II Processor at 350 MHz 400 MHz and 450 MHz In Table2 Recommended Pull up Resistor Values Approximate for CMOS Signals 1 2 3 Recommended Resistor Value Approximate CMOS Signal 1500 TDI TDO TMS PICD 0 PICD 1 1500 2200 FERR IERR THERMTRIP 1500 3300 A20M IGNNE INIT LINT 1 NMI LINT 0 INTR PWRGOOD SLP PREQ 4100 STPCLK SMI 5002 FLUSH 1KQ 100KQ TESTHI NOTES 1 These resistor values are recommended for system implementations using open drain CMOS buffers 2 150Q resistors are expected for these signals This value may vary by system and should be correlated with the output drive characteristics of the devices generating the input signals Other approximate values are recommended for proper operation with the Pentium II processor Logic Analyzer Interface 3 TRST must be pulled to ground via a 680 resistor or driven low at power on with the assertion of RESET see Table 19 4 1K 10KQ pullup to 2 0 V Veccore or if 2 5 V ramps after core pull up TESTHI to 2 5V Vec2 5 with a 100 KO resistor The groups and the
22. processor varies from the Pentium Pro processor in its output buffer implementation The buffers that drive most of the system bus signals on the Pentium II processor are actively driven to VCCcorg for one clock cycle after the low to high transition to improve its rise times and reduce noise These signals should still be considered open drain and require termination to a supply that provides the high signal level Because this specification is different from the standard GTL specification it is referred to as Assisted Gunning Transitistor Logic AGTL in this document AGTL logic and GTL logic are compatible with each other and may both be used on the same system bus AGTL signals are open drain and require termination to a supply that provides the high signal level AGTL inputs use differential receivers which require a reference signal Vrer Vrer is used by the receivers to determine if a signal is a logical 0 or a logical 1 and is generated on the S E C cartridges for the processor core Local Vrer copies should be generated on the motherboard for all other devices on the AGTL system bus Termination usually a resistor at each end of the signal trace is used to pull the bus up to the high voltage level and to control reflections on the transmission line The processor contains termination resistors that provide termination for one end of the Pentium II processor system bus These specifications assume another resistor at the end of each si
23. signals contained within each group are shown in Table 3 Refer to Section 7 0 for descriptions of these signals 18 Datasheet In Table 3 2 8 1 2 8 2 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz System Bus Signal Groups Group Name Signals AGTL Input BPRI BR1 DEFER RESET RS 2 0 RSP TRDY AGTL Output PRDY A 35 3 ADS AERR AP 1 0 BERR BINIT BNR BP 3 2 BPM 1 0 BRO aot D 63 0 DBS Y DEP 7 0 DRDY HIT HITM LOCK REQ 4 0 RP A20M FLUSH IGNNE INIT LINTO INTR LINT1 NMI PREQ PVRGOOD SMI CMOS Inputs SLP4 STPCLK CMOS Outputs FERR IERR THERMTRIP System Bus Clock BCLK APIC Clock PICCLK APIC HO PICD 1 0 TAP Input TCK TDI TMS TRST TAP Output TDO Power Other VCCcorr VCCL2 VCCS VID 4 0 VTT Vss SLOTOCC THERMDP THERMDN 100 66 EMI NOTES 1 The BRO pin is the only BREQ signal that is bidirectional The internal BREQ signals are mapped onto BR pins after the agent ID is determined See Section 7 0 for more information QN UA E C 4 See Section 7 0 for information on the PVRGOOD signal See Section 7 0 for information on the SLP signal See Section 7 0 for information on the THERMTRIP signal These signals are specified for 2 5 V operation See Table 2 for recommended pull up resistor values Vcccore is the p
24. through Figure 22 show the S E C C package dimensions Figure 23 and Figure 24 show the extended thermal plate dimensions and Figure 25 and Figure 26 provide details of the processor substrate edge finger contacts Figure 27 and Table 31 contain processor marking information The processor edge connector defined in this document is referred to as the SC 242 connector See the Slot 1 Connector Specification Order Number 243397 for further details on the SC 242 connector For Figure 18 through Figure 35 the following apply 1 Unless otherwise specified the following drawings are dimensioned in inches 2 All dimensions provided with tolerances are guaranteed to be met for all normal production product 3 Figures and drawings labeled as Reference Dimensions are provided for informational purposes only Reference Dimensions are extracted from the mechanical design database and are nominal dimensions with no tolerance information applied Reference Dimensions are NOT checked as part of the processor manufacturing Dimensions in parentheses without tolerances are Reference Dimensions 4 Drawings are not to scale Figure 18 Pentium II Processor S E C C Package Top and Side View PP Top View Left Latch Cover Right Latch Thermal Plate D N D a E A E Al Oo o Oo o 9 e e o Leem KH Left Cover Side vi
25. 0 0 ns 11 6 7 T40 TDO Float Delay 25 0 ns 11 6 7 10 T41 All Non Test Outputs Valid Delay 2 0 25 0 ns 11 6 8 9 T42 All Non Test Inputs Setup Time 25 0 ns 11 6 8 9 10 T43 All Non Test Inputs Setup Time 5 0 ns 11 5 8 9 T44 All Non Test Inputs Hold Time 13 0 ns 11 5 8 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 All AC timings for the TAP signals are referenced to the TCK rising edge at 1 25 V at the processor core pins All TAP signal timings TMS TDI etc are referenced at 1 25 V at the processor core pins 3 These specifications are tested during manufacturing unless otherwise noted 4 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 667 MHz 5 Referenced to TCK rising edge 6 Referenced to TCK falling edge 7 Valid delay timing for this signal is specified to 2 5 V 5 See Table 2 for pull up resistor values 8 Non Test Outputs and Inputs are the normal output or input signals besides TCK TRST TDI TDO and TMS These timings correspond to the response of these signals due to TAP operations 9 During Debug Port operation use the normal specified timings rather than the TAP signal timings 10 Not 100 tested Specified by design characterization 32 Datasheet intel Figure 5 Note Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz BCLK to Core Logic Offset
26. 0 008 1 ax g 180 KEEP IN AN 125 4 002 1 386 1 908 D i z 0000 s Ki uad J 1 463 N 3 uo UO S X 1 205 a 2 275 010 xX if j T 1 370 A i Al B of i i n H i p BUE amp c3 ca a EeecdsSs zal lil Y N a 0744 002 PLGA 685 4 013 955 013 1389 erc 1444 OLGA 725 013 954 013 x 008 4 685 on 77 Datasheet 53 a Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel s Figure 31 Pentium II Processor Assembly S E C C 2 Package Cover View with Dimensions PLGA 015 071 542 OLGA c 015 I 4 918 006 021 2 ES J d 1 849 010 2 440 005 2 X z X e bo 1 Ve UN 615 4 013 Hd Y Y E 1 546 013 y a 5 000 010 Figure 32 Pentium II Processor Assembly S E C C 2 Package Heat Sink Attach Boss Section 005 ebe 025 001 f i i 062 007 e E 005 020 010 t 5 0 C
27. 1 N Figure 45 Fan Heatsink support clearance above motherboard 0 430 Oo Figure 45 Fan Heatsink support standoff diameter 0 275 0 300 P Figure 45 Dori da support front edge to heatsink support hole 0 240 Q Figure 45 Fan Heatsink support standoff protrusion beneath motherboard 0 06 R Figure 45 Motherboard thickness 0 05 0 06 0 075 S Figure 46 Spacing between FHS Supports 4 084 T Figure 46 Fan Heatsink support width 0 600 U Figure 46 Fan Heatsink support inner edge to heatsink support hole 0 400 NOTE 1 All dimensions are in inches Unless otherwise specified all dimensions with three significant digits have a tolerance of 30 005 inches All dimensions with two significant digits have a tolerance of 0 01 inches 70 Datasheet _ ntel Pentium II Processor at 350 MHz 400 MHz and 450 MHz Figure 45 Side View Space Requirements for Boxed Processor Fan Heatsink Supports ka O AE A A kueg EL a F hai mm E Figure 46 Top View Space Requirements for Boxed Processor Fan Heatsink Supports Datasheet 71 Pentium II Processor at 350 MHz 400 MHz and 450 MHz In 6 3 6 3 1 72 Figure 47 Table 39 Boxed Processor Requirements Fan Heatsink Power Supply The boxed processor s fan heatsink requires a 12 V power supply A fan power cable will be shipped with the boxed processor to draw power from a power header on the motherboard The power cable connector and pinout are shown in Fi
28. 1 0 Valid Delay 3 0 12 0 ns 7 4 5 6 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 Not 100 tested Specified by design characterization 3 All AC timings for the APIC I O signals are referenced to the PICCLK rising edge at 0 7 V at the processor edge fingers All APIC I O signal timings are referenced at 1 25 V at the processor edge fingers 4 Referenced to PICCLK rising edge 5 For open drain signals valid delay is synonymous with float delay 6 Valid delay timings for these signals are specified to 2 5 V 4 596 See Table 2 for recommended pull up resistor values Datasheet n Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 18 System Bus AC Specifications APIC Clock and APIC I O at the Processor Core Pins 1 2 3 T Parameter Min Max Unit Figure Notes T21 PICCLK Frequency 2 0 33 3 MHz T22 PICCLK Period 30 0 500 0 ns 6 T23 PICCLK High Time 12 0 ns 6 T24 PICCLK Low Time 12 0 ns 6 T25 PICCLK Rise Time 1 0 5 0 ns 6 T26 PICCLK Fall Time 1 0 5 0 ns 6 T27 PICD 1 0 Setup Time 8 0 ns 8 4 T28 PICD 1 0 Hold Time 2 5 ns 8 4 T29 PICD 1 0 Valid Delay 1 5 10 0 ns 7 4 5 6 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 These specifications are tested during manufacturing 3 All
29. 1 0 1 1 80 4 0 0 1 0 0 1 854 0 0 0 1 1 1 904 0 0 0 1 0 1 954 0 0 0 0 1 2 00 0 0 0 0 0 2 054 1 1 1 1 1 No Core 1 1 1 1 0 2 14 1 1 1 0 1 2 24 1 1 1 0 0 2 34 1 1 0 1 1 24 1 1 0 1 0 2 54 1 1 0 0 1 2 6 1 1 0 0 0 2 7 1 0 1 1 1 2 87 1 0 1 1 0 2 9 1 0 1 0 1 3 0 1 0 1 0 0 3 1 1 0 0 1 1 3 2 1 0 0 1 0 3 3 1 0 0 0 1 3 4 1 0 0 0 0 3 5 NOTES 1 0 Processor pin connected to Vss 2 1 Open on processor may be pulled up to TTL VIH on motherboard 3 VRM output should be disabled for Vcccos values less than 1 80 V 4 To ensure the system is ready for the Pentium II processors the values in BOLD in Table must be supported Note that the 11111 all opens ID can be used to detect the absence of a processor core in a given slot as long as the power supply used does not affect these lines Detection logic and pull ups should not affect VID inputs at the power source see Section 7 0 The VID pins should be pulled up to a TTL compatible level with external resistors to the power source of the regulator only if required by the regulator or external logic monitoring the VID 4 0 signals The power source chosen must be guaranteed to be stable whenever the supply to the voltage regulator is stable This will prevent the possibility of the processor supply going above the specified V ccc in the event of a failure in the supply for the VID lines In the case of a DC to DC converter this can be accomplished by us
30. 116 Reserved Reserved for Future Use B116 AP 1 AGTL I O A117 AP 0 AGTL I O B117 VCC I2 Other Vcc A118 GND Vss B118 AERR AGTL I O A119 VID 2 Voltage Identification B119 VID 3 Voltage Identification A120 VID 1 Voltage Identification B120 VID 0 Voltage Identification A121 VIDI A4 Voltage Identification B121 VCC_L2 Other Vcc Table 36 is the Pentium II processor substrate edge connector listing in order by signal name Pin No Pin Name Signal Buffer Type Pin No Pin Name Signal Buffer Type B21 100 66 BCLK Frequency Select A29 DEP 5 AGTL HO B98 A 3 AGTL I O A31 DEP 6 AGTL I O A100 A 4 AGTL I O B28 DEP 7 AGTL I O A97 A 5 AGTL I O B107 DRDY AGTL HO B99 A 6 AGTL T O Bl EMI EMI Management B96 A 7 AGTL I O B41 EMI EMI Management B95 A 8 AGTL I O B61 EMI EMI Management A99 A 9 AGTL I O B81 EMI EMI Management A96 A 10 AGTL T O B100 EMI EMI Management B92 A 11 AGTL I O AT FERR CMOS Output B94 A 12 AGTL I O B2 FLUSH CMOS Input A93 A 13 AGTL I O B76 Reserved Reserved for Future Use A95 A 14 AGTL I O A2 GND Vss B90 Ast 15 AGTL I O A6 GND Vss A92 A 16 AGTL I O A10 GND Vss B91 A 17 AGTL I O Al4 GND Vss A91 A 18 AGTL I O A18 GND Vss A89 A 19 AGTL I O A22 GND Vss B86 A 20 AGTL I O A26 GND Vss 61 Pentium II Processor at 350 MHz 400 MHz and 450 MHz 62 Table 36
31. 17 AGTL I O A92 A 16 AGTL I O B92 A 11 AGTL I O A93 A 13 AGTL I O B93 VCC_CORE Processor core VCC A94 GND Vss B94 A 12 AGTL I O A95 A 14 AGTL I O B95 A 8 AGTL I O A96 A 10 AGTL I O B96 A 7 AGTL I O A97 A 5 AGTL I O B97 VCC_CORE Processor core VCC A98 GND Vss B98 A 3 AGTL I O A99 A 9 AGTL I O B99 A 6 AGTL I O A100 A 4 AGTL I O B100 EMI EMI Management A101 BNR AGTL I O B101 SLOTOCC SC 242 Occupied A102 GND VSS B102 REQ 0 AGTL I O A103 BPRI AGTL Input B103 REQ 1 AGTL I O A104 TRDY AGTL Input B104 REQ 4 AGTL I O A105 DEFER AGTL Input B105 VCC_CORE Processor core VCC A106 GND Vss B106 LOCK AGTL I O A107 REQ 2 AGTL I O B107 DRDY AGTL I O 60 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 35 Signal Listing in Order by Pin Number Sheet 4 of 4 Table 36 Signal Listing in Order by Signal Name Sheet 1 of 4 Datasheet Pin No Pin Name Signal Buffer Type Pin No Pin Name Signal Buffer Type A108 REQ 3 AGTL VO B108 RS 0 AGTL Input A109 HITM AGTL I O B109 VCC5 Other Vcc A110 GND Vss B110 HIT AGTL I O Alll DBSY AGTL HO B111 RS 2 AGTL Input A112 RS 1 AGTL Input B112 Reserved Reserved for Future Use A113 Reserved Reserved for Future Use B113 VCC_L2 Other Vcc A114 GND Vss B114 RP AGTL I O A115 ADS AGTL I O B115 RSP AGTL Input A
32. 29 System Bus AC Specifications CMOS Signal Group at the Processor Core Pins 29 System Bus AC Specifications Reset Conditions seeeeessssss 30 System Bus AC Specifications APIC Clock and APIC I O at the Processor Edge Fillgerss mtt neo I PERDU ep eiae 30 System Bus AC Specifications APIC Clock and APIC l O at the Processor GOLG PInS ot eee iene rere rer t uin rn Mr um A Ere Ee 31 System Bus AC Specifications TAP Connection at the Processor Edge le iio eto DR REOR ER 31 System Bus AC Specifications TAP Connection at the Processor Core Pins 32 BCLK Signal Quality Specifications for Simulation at the Processor Core 37 BCLK Signal Quality Guidelines for Edge Finger Measurement 38 AGTL Signal Groups Ringback Tolerance Specifications at the Processor Ier 39 AGTL Signal Groups Ringback Tolerance Guidelines for Edge Finger ELE VE 39 Signal Ringback Specifications for Non AGTL Signal Simulation at the ProGessot GOIG aiio pee D e RE dee rU H 41 Signal Ringback Guidelines for Non AGTL Signal Edge Finger Measurement 41 Thermal Specifications for S E C C Packaged Processors 43 Thermal Specifications for S E C C 2 Packaged Processors 43 Thermal Diode Parameters sssssssssssssssssses eene eene nnne 44 Thermal Diode Interface cccecceeeceeeeeeceeeeeceeeeeeeeeeeeeceaaaaeaeeeeeeeeseeeeeeeenanaeees
33. 43502 for details 74 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 41 Signal Description Sheet 2 of 8 Datasheet Name Type Description A20M If the A20M Address 20 Mask input signal is asserted the Pentium II processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O Write bus transaction During active RESET each processor begins sampling the A2ZOM IGNNE and LINT 1 0 values to determine the ratio of core clock frequency to bus clock frequency See Table 9 On the active to inactive transition of RESET each processor latches these signals and freezes the frequency ratio internally System logic must then release these signals for normal operation ADS Lo The ADS Address Strobe signal is asserted to indicate the validity of the transaction address on the A 35 3 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the n
34. 44 Description Table for Processor Markings S E C C Packaged Processor 52 Description Table for Processor Markings S E C C 2 Packaged Processor 57 S E C C Materials ccc ree ec Tc tet ed EEN 57 e E EE 57 Signal Listing in Order by Pin Number 58 Signal Listing in Order by Signal Name seen 61 Boxed Processor Fan Heatsink Spatial Dimensions eeeeeeeeeeeeeeereeeeenenn 69 Boxed Processor Fan Heatsink Support Dimensions sseseeseeeseeerserernenre 70 Fan Heatsink Power and Signal Specifications seeen 72 Motherboard Fan Power Connector Location ssssssssssesnnrenssesssrrnrnnnrennsnesene 73 Signal Description iiec REENEN SREL eege 74 e FEIER 81 Input Signals erret faving eei ope Liao Ete RUE ERA EE LL Yea eR Plagas 82 Input Output Signals Single Driver 83 Input Output Signals Multiple Driver 83 Datasheet 1 0 Pentium II Processor at 350 MHz 400 MHz and 450 MHz Introduction Datasheet The Pentium II 350 MHz 400 MHz 450 MHz processor is the next in the Pentium II processor line of Intel processors The Pentium II processor like the Pentium Pro processor implements a Dynamic Execution microarchitecture a unique combination of multiple branch prediction data flow analysis and speculative execution This enables these processors to deliver higher performance than the Pentium processor while maintaining binary compatibility with all previous Intel A
35. 850 eme cds le 2 9904 008 oe 2 0104 008 P biv 5 000 Figure 36 Pentium II Processor Markings S E C C 2 Package 2 D Matrix Mark See Note Dynamic Mark Area Th NOTE Hologram Please refer to the Pentium II Location Processor Specification Update for this information a 56 Datasheet n Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 32 Description Table for Processor Markings S E C C 2 Packaged Processor Code Letter Description A Logo B Product Name C Trademark D Logo E Product Name F Dynamic Mark Area with 2 D matrix 5 3 Processor Package Materials Information Both the the S E C C and S E C C 2 processor cartridges are comprised of multiple pieces to make the complete assembly This section provides information relevant to the use and acceptance of the package Table 33 and Section 34 contain piece part information of the S E C C and S E C C 2 processor packages respectively Table 33 S E C C Materials S E C C Piece Piece Material Maximum Piece Weight Grams Extended Thermal Plate Aluminum 6063 T6 84 0 Latch Arms GE Lexan 940 V0 30 glass filled Less than 2 0 per latch arm Cover GE Lexan 940 V0 24 0 Total Pentium II Processor 150 NOTE 1 Unless otherwise noted these specifica
36. A N A 5 90 5 105 5 75 400 512 24 3 N A N A 5 90 5 105 5 75 350 512 21 5 5 80 N A N A 5 105 5 75 NOTES 1 These values are specified at nominal Vcccor for the processor core and nominal Vccv2 for the L2 cache 2 Processor power includes the power dissipated by the processor core the L2 cache and the AGTL bus termination The maximum power for each of these components does not occur simultaneously For S E C C packaged processors the extended thermal plate is the attach location for all thermal solutions The maximum and minimum extended thermal plate temperatures are specified in Table 27 For S E C C 2 packaged processors thermal solutions attach to the processor by connecting through the substrate to the cover The maximum and minimum temperatures of the pertinent locations are specified in Table 28 A thermal solution should be designed to ensure the temperature of the specified locations never exceeds these temperatures The total processor power is a result of heat dissipation that is a combination of heat from both the processor core and L2 cache The overall system chassis thermal design must comprehend the entire processor power In S E C C packaged processors the extended thermal plate power is a component of this power and is composed of a combination of the processor core and the L2 cache dissipating heat through the extended thermal plate The heatsink need only be designed to dissipate the extended thermal plate power See Tabl
37. A8 IGNNE CMOS Input B8 SLP CMOS Input A9 TDI JTAG Input B9 VCC VTT AGTL VTT Supply A10 GND Vss B10 TMS JTAG Input All TDO JTAG Output Bll TRST JTAG Input A12 PWRGOOD CMOS Input B12 Reserved Reserved for Future Use A13 TESTHI CMOS Test Input B13 VCC CORE Processor core VCC Al4 GND Vss B14 THERMDP Diode Anode A15 THERMTRIP CMOS Output B15 THERMDN Diode Cathode A16 Reserved Reserved for Future Use B16 LINT 1 NMI CMOS Input A17 LINT O INTR CMOS Input B17 VCC CORE Processor core VCC A18 GND Vss B18 PICCLK APIC Clock Input A19 PICD 0 CMOS UO B19 BP 2 AGTL I O A20 PREQ CMOS Input B20 Reserved Reserved for Future Use A21 BP 3 AGTL I O B21 100 66 BCLK Frequency Select A22 GND VSS B22 PICD 1 CMOS I O A23 BPM 0 AGTL I O B23 PRDY AGTL Output A24 BINIT AGTL I O B24 BPM 1 AGTL I O A25 DEP 0 AGTL I O B25 VCC_CORE Processor core VCC A26 GND Vss B26 DEP 2 AGTL I O A27 DEP 1 AGTL I O B27 DEP 4 AGTL UO A28 DEP 3 AGTL I O B28 DEP 7 AGTL UO A29 DEP 5 AGTL I O B29 VCC_CORE Processor core VCC A30 GND Vss B30 D 62 AGTL I O A31 DEP 6 AGTL I O B31 D 58 AGTL I O Datasheet Table 35 Signal Listing in Order by Pin Number Sheet 2 of 4 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Pin No Pin Name Signal Buffer Type Pin No Pin Name Signal Buffer Type A32
38. AC timings for the APIC I O signals are referenced to the PICCLK rising edge at 1 25 V at the processor core pins All APIC I O signal timings are referenced at 1 25 V at the processor core pins 4 Referenced to PICCLK rising edge 5 For open drain signals valid delay is synonymous with float delay 6 Valid delay timings for these signals are specified to 2 5 V 5 See Table 2 for recommended pull up resistor values Table 19 System Bus AC Specifications TAP Connection at the Processor Edge Fingers 123 T Parameter Min Max Unit Figure Notes T30 TCK Frequency 16 667 MHz T31 TCK Period 60 0 ns 6 T32 TCK High Time 25 0 ns 6 1 7V T33 TCK Low Time 25 0 ns 6 Q0 7 V T34 TCK Rise Time 5 0 ns 6 0 7 V 1 7 V T35 TCK Fall Time 5 0 ns 6 1 7 V 0 7 V T36 TRST Pulse Width 40 0 ns 12 Asynchronous T37 TDI TMS Setup Time 55 ns 11 5 T38 TDI TMS Hold Time 14 5 ns 11 5 T39 TDO Valid Delay 2 0 13 5 ns 11 6 7 T40 TDO Float Delay 28 5 ns 11 6 7 T41 All Non Test Outputs Valid Delay 2 0 27 5 ns 11 6 8 9 T42 All Non Test Inputs Setup Time 27 5 ns 11 6 8 9 T43 All Non Test Inputs Setup Time 5 5 ns 11 5 8 9 T44 All Non Test Inputs Hold Time 14 5 ns 11 5 8 9 Datasheet 31 Pentium II Processor at 350 MHz 400 MHz and 450 MHz In NOTES 1 2 oo JA CL La 9 Unless otherwise noted all specifications in this table appl
39. As with the Pentium Pro the Pentium II processor has a dedicated L2 cache bus thus maintaining the dual independent bus architecture to deliver high bus bandwidth and high performance see Figure 1 Pentium II processors use either a Single Edge Contact Cartridge S E C C or a Single Edge Contact Cartridge 2 S E C C 2 packaging technology These packaging technologies allow the L2 cache to remain tightly coupled to the processor while enabling use of high volume commercial SRAM components The L2 cache is performance optimized and tested at the package level The S E C C and S E C C 2 packages utilize surface mounted technology and a substrate with an edge finger connection Pentium II processors at 350 400 and 450 MHz while available at higher core frequencies than the previously released Pentium II processors at 233 266 300 and 333 MHz also provide additional features while utilizing either a compatible S E C C package or the follow on S E C C 2 package The S E C C package has the following features an extended thermal plate a cover and a substrate with an edge finger connection The extended thermal plate allows heatsink attachment or customized thermal solutions The S E C C 2 package has a cover and a substrate with an edge finger conenction This allows the thermal solutions to be placed directly onto the processor core package The edge finger connection maintains socketability for system configuration The edge finger connector
40. Buffer Models for IV characteristics Parameter correlated to measure into a 25Q resistor terminated to 1 5 V Refer to the IO Buffer Models for IV characteristics Non AGTL Signal Group DC Specifications i Symbol Parameter Min Max Unit Notes VIL Input Low Voltage 0 3 0 5 V VIH Input High Voltage 2 0 2 625 V 2 5 V 5 maximum VOL Output Low Voltage 0 4 V 2 All outputs are open VOH Output High Voltage N A 2 625 V drain to 2 5 V 5 JOL Output Low Current 14 mA ILI Input Leakage Current 100 HA 3 ILo Output Leakage Current 15 HA 4 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 Parameter measured at 14 mA for use with TTL inputs 3 OS Vin 2 5 V 5 4 0 lt Vour 2 5 V 5 AGTL System Bus Specifications It is recommended that the AGTL bus be routed in a daisy chain fashion with termination resistors to Vrr at each end of the signal trace These termination resistors are placed electrically between the ends of the signal traces and the Vrr voltage supply and generally are chosen to approximate the substrate impedance The valid high and low levels are determined by the input buffers using a reference voltage called Vnzr Table 8 lists the nominal specification for the AGTL termination voltage Vrr The AGTL reference voltage Vnzr is generated on the processor substrate f
41. Bus Signal Gimulatons ENEE 36 3 1 System Bus Clock BCLK Signal Quality Specifications and Measurement EDI E 37 3 2 AGTL Signal Quality Specifications and Measurement Guidelines 38 3 3 Non AGTL Signal Quality Specifications and Measurement Guidelines 40 3 83 1 Overshoot Undershoot Guidelines esssseesssseeseeerneesssrneserenneeernnneneeena 41 3 8 2 Ringback Specification sse 41 3 3 3 Settling Limit Guidelme kk 42 Thermal Specifications and Design Considerations eesessesseresseerressrrrrsssrrrrrnsrrrrssne 42 4 1 Thermal SPSCiiCAatlons EE 43 4 4 1 Thermal Diode ente Rhen Rune nhanh a cen nie a iaaa uen 44 S E C C and S E C C 2 Mechanical Specifications seseseees 44 5 1 S E C C Mechnical Gpecftcaions seen 45 3 Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel m 6 0 7 0 Figures 5 2 S E C C 2 Mechanical Specification 52 5 3 Processor Package Materials Information eee 57 5 4 Pentium U Processor Signal Listing ssseeneen 58 Boxed Processor Specifications ccccecesscceeeeeseeeeeeeeeeeeeeeeesaeeeeeeeeaaeeeseeeseeeeeeeeseenaesees 64 6 1 lag elei ode poe rc 64 6 2 Mechanical Specifications encena inan naer aE Enia ENAR ET 66 6 2 1 Boxed Processor Fan Heatsink Dimensions sees 66 6 2 2 Boxed Processor Fan Heatsink Weoht 69 6 2 3 Boxed Processor Retention Mec
42. C A66 GND Vss B66 D 12 AGTL HO A67 D 14 AGTL I O B67 D 7 AGTL I O A68 D 9 AGTL I O B68 D 6 AGTL I O A69 D 8 AGTL I O B69 VCC_CORE Processor core VCC 59 Pentium II Processor at 350 MHz 400 MHz and 450 MHz l n Table 35 Signal Listing in Order by Pin Number Sheet 3 of 4 Pin No Pin Name Signal Buffer Type Pin No Pin Name Signal Buffer Type ATO GND VSS B70 D 4 AGTL I O ATI D 5 AGTL I O B71 D 2 AGTL I O A72 D 3 AGTL HO B72 D 0 AGTL I O A73 D 1 AGTL I O B73 VCC_CORE Processor core VCC ATA GND Vss B74 RESET AGTL Input A75 BCLK Processor Clock Input B75 BRI AGTL Input A76 BRO AGTL I O B76 Reserved Reserved for Future Use A77 BERR AGTL I O B77 VCC_CORE Processor core VCC A78 GND VSS B78 A 35 AGTL I O A79 A 33 AGTL I O B79 A 32 AGTL I O A80 A 34 AGTL I O B80 A 29 AGTL I O A81 A 30 AGTL I O B81 EMI EMI Management A82 GND VSS B82 Ast 26 AGTL I O A83 A 31 AGTL I O B83 A 24 AGTL I O A84 A 27 AGTL I O B84 A 28 AGTL I O A85 A 22 AGTL I O B85 VCC_CORE Processor core VCC A86 GND Vss B86 A 20 AGTL I O A87 A 23 AGTL I O B87 A 21 AGTL I O A88 Reserved Reserved for Future Use B88 A 25 AGTL I O A89 A 19 AGTL I O B89 VCC_CORE Processor core VCC A90 GND Vss B90 A 15 AGTL I O A91 A 18 AGTL I O B91 A
43. II processor system bus agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity SLOTOCC The SLOTOCC signal is defined to allow a system design to detect the presence of a terminator card or processor in a SC 242 connector Combined with the VID combination of VID 4 0 11111 see Section 2 6 a system can determine if a SC 242 connector is occupied and whether a processor core is present See the table below for states and values for determining the type of cartridge in the SC 242 connector SC 242 Occupation Truth Table Signal Value Status 0 Anything other than Processor with core in SC 242 connector Hr SLOTOCC VID 4 0 SLOTOCC 0 Terminator cartridge in SC 242 connector VID 4 0 11111 i e no core present SLOTOCC 1 VID 4 0 Any value SC 242 connector not occupied SLP The SLP Sleep signal when asserted in Stop Grant state causes processors to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertions of the SLP STPCLK and RESET signals while in S
44. OVE 54 Datasheet a ntel Pentium II Processor at 350 MHz 400 MHz and 450 MHz Figure 33 Pentium II Processor Assembly S E C C 2 Package Side View OLGA Substrate Shown PLGA 44 006 OLGA 004 005 CORE PACKAGE TQFP BS RAM PACKAGE 29 025 064 005 La ee a xum Le Tan J A Y See Figure 40 Figure 34 Detail View of Cover in the Vicinity of the Substrate Attach Features Y 075 m 280 m Datasheet 55 a Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel A Figure 35 Pentium II Processor Substrate S E C C 2 Package Edge Finger Contact Dimensions OLGA Package q Ll e 2 20 e paoi S I all zt H Eo J di K TT O 42 D ose e PIN AI2I PIN Al Ss 084 S I REE TR AIR MI T l SUBSTRATE i RENT DETAIL A IN NEXT FIGURE 2 835 1
45. SE CC Package Extended Thermal Plate Side MIEL EE 46 20 Pentium II Processor SE CC Package Bottom View Dimensions 46 21 Pentium II Processor S E C C Package Latch Arm Extended Thermal Plate Lug and Cover Lug Dimensions 47 22 Pentium II Processor S E C C Package Latch Arm Extended Thermal Plate and Cover Detail Dimensions Reference Dimensions Only 48 23 Pentium II Processor SE CC Package Extended Thermal Plate Attachment Detail Dimensions nen 49 Datasheet Tables Datasheet 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 OORUN Pentium II Processor at 350 MHz 400 MHz and 450 MHz Pentium II Processor SE CC Package Extended Thermal Plate Attachment Detail Dimensions Continued esses 50 Pentium II Processor Substrate S E C C Package Edge Finger Contact Dimensions cee ee eee ee cece eeaaeaaeaeeeeeeeeeeeeeseceaanaesaeeeeeeeeess 50 Pentium II Processor Substrate S E C C Package Edge Finger Contact Dimensions Detail A 51 Pentium II Processor Markings S E C C Package 51 Pentium II Processor S E C C 2 Package Top and Side Views OLGA tee tidem 52 Pentium II Processor S E C C 2 Package Top and Side Views PEGA Processor Ee E 53 Pentium Il Processor Assembly S E C C 2 Package Primary View 53 Pentium II Processor Assembly S E C C 2 Package Cover View with Mi
46. The L1 and L2 caches are not affected If BINIT observation is disabled during power on configuration a central agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR IO The BNR Block Next Request signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wire OR signal which must connect the appropriate pins of all Pentium II processor system bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges BP 3 2 VO The BP 3 2 Breakpoint signals are outputs from the processor that indicate the status of breakpoints BPM 1 0 IO The BPM 1 0 Breakpoint Monitor signals are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPRI The BPRI Bus Priority Request signal is used to arbitrate for ownership of the Pentium II processor system bus It must connect the appropriate pins of all Pentium II processor system bus agents Observing BPRI active as asserted by the priority age
47. asured after Vcccoss Vcci2 and BCLK become stable Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 14 System Bus AC Specifications CMOS Signal Group at the Processor Edge Fingers 12 34 T Parameter Min Max Unit Figure Notes T11 CMOS Output Valid Delay 1 00 10 5 ns 7 5 T12 CMOS Input Setup Time 4 50 ns 8 6 7 8 T13 CMOS Input Hold Time 1 50 ns 8 6 7 TIJ EE Pulse Width except 2 BCLKs 7 pid and Inactive T15 PWRGOOD Inactive Pulse Width 10 BCLKs 7 10 8 NOTES L 2 3 MON Lin ZE 8 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes Not 100 tested Specified by design characterization All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0 5 V at the processor edge fingers All CMOS signal timings address bus data bus etc are referenced at 1 25 V These signals may be driven asynchronously Valid delay timings for these signals are specified to 2 5 V 5 See Table 2 for pull up resistor values To ensure recognition on a specific clock the setup and hold times with respect to BCLK must be met INTR and NMI are only valid when the local APIC is disabled LINT 1 0 are only valid when the local APIC is enabled When driven inactive or after Vcccoss Vcci2 and BCLK become stable Table 15 System Bus AC Specifications CMOS Signal Grou
48. at a core frequency as low as its minimum rating Voltage Identification There are five voltage identification pins on the SC 242 connector These pins can be used to support automatic selection of power supply voltages These pins are not signals but are either an open circuit or a short circuit to Vss on the processor The combination of opens and shorts defines the voltage required by the processor core The VID pins are needed to cleanly support voltage specification variations on current and future Pentium II processors These pins VID 0 through VID 4 are defined in Table 1 A 1 in this table refers to an open pin and a 0 refers to a short to ground The definition provided in Table 1 is a superset of the definition previously defined for the Pentium Pro processor The power supply must supply the voltage that is requested or disable itself 15 a Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel s 16 Table 1 To ensure the system is ready for current and future Pentium II processors the range of values in bold in Table 1 must be supported A smaller range will risk the ability of the system to migrate to a higher performance Pentium II processor and or maintain compatibility with current Pentium II processors Voltage Identification Definition L23 Processor Pins VID4 VID3 VID2 VIDI VIDO VCCcong 01111 00110 Reserved 0 0
49. ccogg and Icccogg supply the processor core and the TagRAM and BSRAM I O buffers 3 This specification applies only to the Pentium II processor Unless otherwise noted this specification applies to all Pentium II processor frequencies and cache sizes 4 This specification applies only to the Pentium II processor when operating with a 100 MHz Pentium II processor system bus Unless otherwise noted this specification applies to all Pentium II processor cache sizes 5 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 5 and Table 1 for more information 6 Use the Typical Voltage specification with the Tolerance specifications to provide correct voltage regulation to the processor 7 Vccr5 and Icc 2 supply the second level cache Unless otherwise noted this specification applies to all Pentium II processor cache sizes Systems should be designed for these specifications even if a smaller cache size is used 8 Var must be held to 1 5 V 9 It is recommended that Nr be held to 1 5 V 3 while the Pentium II processor system bus is idle This is measured at the processor edge fingers 9 These are the tolerance requirements across a 20 MHz bandwidth at the SC 242 connector pin on the bottom side of the baseboard The requirements at the SC 242 connector pins account for voltage drops and impedance discontinuities across the connector processor edge
50. e if INIT is sampled active during the active to inactive transition of RESET the processor will execute its Built in Self Test BIST Whether or not BIST is executed the processor will begin program execution at the power on Reset vector default 0_FFFF_FFFOh RESET must connect the appropriate pins of all Pentium II processor system bus agents RP Lo The RP Request Parity signal is driven by the request initiator and provides parity protection on ADS and REQ 4 0 It must connect the appropriate pins of all Pentium II processor system bus agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This definition allows parity to be high when all covered signals are high RS 2 0 The RS 2 0 Response Status signals are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all Pentium II processor system bus agents 79 Pentium II Processor at 350 MHz 400 MHz and 450 MHz l n 80 Table 41 Signal Description Sheet 7 of 8 Name Type Description RSP The RSP Response Parity signal is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect the appropriate pins of all Pentium
51. e 27 for current Pentium II processor thermal design specifications Datasheet 43 Pentium II Processor at 350 MHz 400 MHz and 450 MHz 4 1 1 Table 29 Table 30 5 0 intel For S E C C 2 packaged processors no extended thermal plate exists and thermal solutions need to contact the core package directly and attach through the substrate to the cover The total processor power that must be dissipated for S E C C 2 processors can be thought of just as it is for S E C C packaged processors a combination of both the processor core and L2 cache In regards to the core thermal specifications depend on the packaging technology used Pentium II processors in S E C C 2 utilizing PLGA core packaging technology have a case temperature specified Pentium II processors in S E C C 2 utilizing OLGA core packaging technology have a junction temperature specified Specifics on how to measure these two paramaters are outlined in AP 586 Pentium II Processor Thermal Design Guidelines Order Number 243331 In addition there are surface mounted SRAM components for the L2 Cache on the substrate that have a separate TcasE specification in Table 28 Thermal Diode The Pentium II processor incorporates an on die diode that must be used to monitor the die temperature junction temperature thermal sensor located on the motherboard or a stand alone measurement kit may monitor the die temperature of the Pentium II processor for thermal managemen
52. e advatange of S E C C package technology This technology uses an extended thermal plate for heatsink attachment The extended thermal plate interface is intended to provide accessiblity for multiple types of thermal solutions Follow on releases of the Pentium II processor use S E C C 2 packaging technology This pakaging technology doesn t incorporate an extended thermal plate Processors which use S E C C 2 packaging technology have either a PLGA or an OLGA processor core that is surface mounted onto the substrate All three of these package variations require unique thermal measuring processes This chapter provides needed data for designing a thermal solution However for the correct thermal measuring processes please refer to AP 586 Pentium II Processor Thermal Design Guidelines Order Number 243331 Figure 17 provides a side view of an S E C C package This figure provides the thermal plate location Figure 17 Pentium II Processor S E C C Side View 42 Left Latch Right Latch Extended Thermal Plate Datasheet l n Pentium II Processor at 350 MHz 400 MHz and 450 MHz 4 1 Thermal Specifications Table 27 and Table 28 provide the thermal design power dissipation and maximum and minimum temperatures for Pentium II processors with S E C C and S E C C 2 package technologies respectively While the processor core dissipates the majority of the thermal power thermal power dissipated b
53. e must be greater than the minimum specified period Valid System Bus Core Frequency and Cache Bus Frequencies 1 2 Core Frequency MHz BCLK Frequency MHz Frequency Multiplier L2 Cache MHz 350 00 100 00 7 2 175 00 400 00 100 00 4 1 200 00 450 00 100 00 9 2 225 00 Datasheet NOTES 1 Contact your local Intel representative for the latest information on processor frequencies and or frequency multipliers 2 While other bus ratios are defined operation at frequencies other than those listed are not supported 27 Pentium II Processor at 350 MHz 400 MHz and 450 MHz l n 28 Table 12 System Bus AC Specifications AGTL Signal Group at the Processor Edge Fingers 155 Tf Parameter Min Max Unit Figure Notes T7 AGTL Output Valid Delay 0 71 4 66 ns 7 4 T8 AGTL Input Setup Time 1 97 ns 8 5 6 7 T9 AGTL Input Hold Time 1 61 ns 8 8 T10 RESET Pulse Width 1 00 ms 10 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 Not 100 tested Specified by design characterization 3 All AC timings for AGTL signals are referenced to the BCLK rising edge at 0 7 V at the processor edge fingers All AGTL signal timings compatibility signals etc are referenced at 1 00 V at the processor edge fingers 4 Valid delay timings for these signals are specified into 50 to 1 5 V and with Vrer at 1 0 V 5
54. eive power from the system bus these pins should not be driven allowing the level to return to Vrr for minimum power drawn by the termination resistors in this state In addition all other input pins on the system bus should be driven to the inactive state BINIT will be recognized while the processor is in Stop Grant state If STPCLK is still asserted at the completion of the BINIT bus initialization the processor will remain in Stop Grant mode If the STPCLK is not asserted at the completion of the BINIT bus initialization the processor will return to Normal state FLUSH will not be serviced during Stop Grant state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the deassertion of the STPCLK signal A transition to the HALT Grant Snoop state will occur when the processor detects a snoop on the system bus see Section 2 2 4 A transition to the Sleep state see Section 2 2 5 will occur with the assertion of the SLP signal Datasheet 2 2 4 2 2 5 2 2 6 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz While in the Stop Grant State SMI INIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event will be recognized upon return to the Normal state HALT Grant Snoop State State 4 The
55. em bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long term reliability of the component Specifications are provided for simulation at the processor core guidelines are provided for correlation to the processor edge fingers These edge finger guidelines are intended for use during testing and measurement of system signal integrity Violations of these guidelines are permitted but if they occur simulation of signal quality at the processor core should be performed to ensure that no violations of signal quality specifications occur Meeting the specifications at the processor core in Table 21 Table 23 and Table 25 ensures that signal quality effects will not adversely affect processor operation but does not necessarily guarantee that the guidelines in Table 22 Table 24 and Table 26 will be met Datasheet l n Pentium II Processor at 350 MHz 400 MHz and 450 MHz 3 1 System Bus Clock BCLK Signal Quality Specifications and Measurement Guidelines Table 21 describes the signal quality specifications at the processor core for the Pentium II processor system bus clock BCLK signal Table 22 describes guidelines for signal quality measurement at the processor edge fingers Figure 13 describes the signal quality waveform for the system bus clock at the processor core pins Figure 14 describes the signal quality waveform for the system bus clock at
56. er consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 3 for a visual representation of the Pentium II processor low power states Figure 3 Stop Clock State Machine HALT Instruction and HALT Bus Cycle Generated INIT BINIT INTR SMl RESET STPCLK Asserted 1 Normal State Normal execution 2 Auto HALT Power Down State BCLK running Snoops and interrupts allowed Snoop Snoop STPCLK De asserted STPCLK STPCLK Event Event Asserted De asserted Occurs Serviced 4 HALT Grant Snoop State Snoop Event Occurs 3 Stop Grant State BCLK running BCLK running Service snoops to caches Snoop Event Serviced gt Snoops and interrupts allowed SLP SLP Asserted De asserted 5 Sleep State BCLK running No snoops or interrupts allowed BCLK BCLK Input Input Stopped Restarted 6 Deep Sleep State BCLK stopped No snoops or interrupts allowed PCB757a Datasheet 11 Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel 2 2 1 2 2 2 2 2 3 12 For the processor to fully realize the low current consumption of the Stop Grant Sleep and Deep Sleep states a Model Specific Register MSR bit must be set For the MSR at 02AH Hex bit 26 must be set to a 1 this is the power on default setting for the processor to stop all internal clocks dur
57. ew Right Right Right Thermal Plate Left Side Side View v006a vsd 45 Pentium II Processor at 350 MHz 400 MHz and 450 MHz 46 Figure 19 Pentium II Processor S E C C Package Extended Thermal Plate Side Dimensions Figure 20 3 805 020 9 CD Gi J 2 473 016 Pe ee a 2 0705 020 r 2X 125 005 1 2354 020 D ec Y C Co A v 2X 3424 005 These dimensions are from the bottom of the substrate edge fingers 2X 365 005 745 005 e 1 877 020 gt v005a Pentium II Processor S E C C Package Bottom View Dimensions Ba Cover 5 255 006 Li Oreg l F E LU ji KE Thermal Plate M 2 1814 015 gt lt 3 2434 015 gt 5 341 010 gt 4 5 505 010 gt v007 Datasheet RW ntel Pentium II Processor at 350 MHz 400 MHz and 450 MHz Figure 21 Pentium II Processor S E C C Package Latch Arm Extended Thermal Plate Lug and Cover Lug Dimensions 2X 0 238 2X 0 103 0 005 je gt gt 2X 0 174 0 005 2X 0 488 2X 0 647 0 020 0 020
58. ew transaction This signal must connect the appropriate pins on all Pentium II processor system bus agents T O The AERR Address Parity Error signal is observed and driven by all Pentium II processor system bus agents and if used must connect the appropriate pins on all Pentium II processor system bus agents AERR observation is optionally enabled during power on configuration if enabled a valid assertion of AERR aborts the current transaction If AERR observation is disabled during power on configuration a central agent may handle an assertion of AERR as appropriate to the error handling architecture of the system AP 1 0 IO The AP 1 0 Address Parity signals are driven by the request initiator along with ADS A 35 3 REQ 4 0 and RP AP1 covers A 35 24 and APO covers A 23 3 A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins of all Pentium II processor system bus agents BCLK The BCLK Bus Clock signal determines the bus frequency All Pentium II processor system bus agents must receive this signal to drive their outputs and latch their inputs on the BCLK rising edge All external timing parameters are specified with respect to the BCLK signal BERR T O The BERR Bus Error signal i
59. fications This section documents the mechanical specifications of the boxed Pentium II processor fan heatsinks Motherboard manufacturers and system designers should take into account the spacial requirement for both the boxed Pentium II processor in the S E C C package and the boxed Pentium II processor in the S E C C 2 package Boxed Processor Fan Heatsink Dimensions The boxed processor is shipped with an attached fan heatsink Clearance is required around the fan heatsink to ensure unimpeded air flow for proper cooling The space requirements and dimensions for the boxed processor in the S E C C package are shown in Figure 39 Side View Figure 40 Front View and Figure 43 Top View Spacial requirements and dimensions for the boxed processor in the S E C C 2 package are shown in Figure 41 Side View Figure 42 Front View and Figure 43 Top View All dimensions are in inches Figure 39 Side View Space Requirements for the Boxed Processor with S E C C Packaging 66 Fan Heatsink SE CC Processor Package DP A F U d 242 Contact Slat Connector Datasheet _ ntel Pentium II Processor at 350 MHz 400 MHz and 450 MHz Figure 40 Front View Space Requirements for the Boxed Processor with S E C C Packaging
60. frequency of 66 MHz On 19 Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel Figure 4 2 9 2 10 20 motherboards which support operation at either 66 or 100 MHZ this signal must be pulled up to 3 3 V with a 1 4 W 200 resistor as shown in Figure 4 and provided as a frequency selection signal to the clock driver synthesizer If the system motherboard is not capable of operating at 100 MHz e g Intel 440FX PCIset and 440LX AGPset based systems it should ground this signal and generate a 66 MHz system bus frequency This signal can also be incorporated into RESET logic on the motherboard if only 100 MHz operation is supported thus forcing the RESET signal to remain active as long as the 100 66 signal is low 100 66 Pin Example 3 3 Volts CK100 Pentium II Processor Processor Core Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the Pentium II processor be first in the TAP chain and followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting a 2 5 V input Similar considerations must be made for TCK TMS and TRST Two copies of each signal may be required with each driving a different voltage level The Debug Port will have to be placed at the start and end of t
61. ge of the BCLK input All AGTL timings are referenced to Vrer for both 0 and 1 logic levels unless otherwise specified The timings specified in this section should be used in conjunction with the I O buffer models provided by Intel These I O buffer models which include package information are available for the Pentium II processor in Quad format as the Pentium II Processor I O Buffer Models Quad Format Electronic Form on Intel s website http www intel com GTL layout guidelines are also available in AP 827 100 MHz GTL Layout Guidelines for the Pentium II Processor and Intel 440BX AGPset Order Number 243735 Care should be taken to read all notes associated with a particular timing parameter 25 Pentium II Processor at 350 MHz 400 MHz and 450 MHz In Table 9 System Bus AC Specifications Clock at the Processor Edge Fingers 1 2 3 T Parameter Min Nom Max Unit Figure Notes System Bus Frequency 100 00 MHz a eer ead frequencies T1 BCLK Period 10 0 ns 6 4 5 TIB SC 242 to Core Logic BCLK Offset 0 78 ns 6 Absolute Value 8 T2 BCLK Period Stability See Table 10 T3 BCLK High Time 2 1 ns 6 2 0 V T4 BCLK Low Time 1 97 ns 6 Q 0 5 V6 TS BCLK Rise Time 0 88 237 ns 6 05 V 2 0 v T6 BCLK Fall Time 1 13 2 94 ns 6 Q0Vv o5v NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 All AC timings fo
62. gnal trace to ensure adequate signal quality for the AGTL signals see Table 8 for the bus termination voltage specifications for AGTL and the Pentium II Processor Developer s Manual Order Number 243502 for the GTL bus specification Solutions exist for single ended termination as well though solution space is affected Figure 2 is a schematic representation of AGTL bus topology with Pentium II processors The AGTL bus depends on incident wave switching Therefore timing calculations for AGTL signals are based on flight time as opposed to capacitive deratings Analog signal simulation of the Pentium II processor system bus including trace lengths is highly recommended when designing a system with a heavily loaded AGTL bus especially for systems using a single set of termination resistors i e those on the processor substrate with the Intel 440BX AGPset Such designs will not match the solution space allowed for by installation of termination resistors on the motherboard See Intel s World Wide Web page http developer intel com to download the buffer models Pentium II Processor I O Buffer Models Quad Format Electronic Form Datasheet n Pentium II Processor at 350 MHz 400 MHz and 450 MHz Figure2 AGTL Bus Topology Pentium II Pentium II Processor Processor 2 2 Clock Control and Low Power States Pentium II processors allow the use of AutoHALT Stop Grant Sleep and Deep Sleep states to reduce pow
63. gure 47 Motherboards must provide a matched power header to support the boxed processor Table 39 contains specifications for the input and output signals at the fan heatsink connector The cable length will be 7 0 0 25 inches The fan heatsink outputs a SENSE signal which is an open collector output that pulses at a rate of two pulses per fan revolution A motherboard pull up resistor provides Vou to match the motherboard mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header identification and location should be documented in the motherboard documentation or on the motherboard itself Figure 48 shows the location of the fan power connector relative to the 242 contact slot connector The motherboard power header should be positioned within 4 75 inches lateral of the fan power connector Boxed Processor Fan Heatsink Power Cable Connector Description Pin Signal 1 GND Straight square pin 3 pin terminal housing with polarizing ribs and friction locking ramp 2 12V 0 100 pin pitch 0 025 square pin width 3 SENSE Waldom Molex P N 22 01 3037 or equivalent Match with straight pin friction lock header on motherboard Waldom Molex P N 22 23 2031 AMP P N 640456 3 or equivalent
64. h signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration During active RESET the Pentium II processor begins sampling the A20M IGNNE and LINT 1 0 values to determine the ratio of core clock frequency to bus clock frequency See Table 9 On the active to inactive transition of RESET the Pentium II processor latches these signals and freezes the frequency ratio internally System logic must then release these signals for normal operation LOCK IO The LOCK signal indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all Pentium II processor system bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the Pentium II processor system bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the Pentium II processor system bus throughout the bus locked operation and ensure the atomicity of lock PICCLK The PICCLK APIC Clock signal is an input clock to the processor and core logic or I O APIC which is required for operation of all processo
65. hanism and Fan Heatsink Supports 69 6 3 Boxed Processor Requirements AANEREN 72 6 3 4 Fan Heatsink Power Supply sse 72 6 4 Thermal Specifications ek 73 6 4 4 Boxed Processor Cooling Requirements eessseeseeereerreeressennsn 73 Pentium II Processor Signal Description 74 7 1 Alphabetical Signals Reference eene enne 74 7 2 elt e 81 1 Second Level L2 Cache Implementations seen 8 2 ENN EIN VE 11 3 Stop Clock State Machine 11 4 100 665 Pin Example eite eir eo reden n Rt ee NERE n DRRRR IRR ERRRRER ERREUR 20 5 BOLK t0 Gore Logic Offsel euet treni ttr NEE hee oor UL sev need ats 33 6 BCLK PICCLK and TCK Generic Clock Waveiom eese 34 7 System Bus Valid Delay Timings sesasi rrsiisnn nanninannan aaa nn 34 8 System Bus Setup and Hold TIMINGS seen 34 9 System Bus Reset and Configuration Timing 35 10 Power On Reset and Configuration Tummimgs 35 11 Test Timings TAP CGonpechon nennen 36 12 Estate E 36 13 BCLK TCK PICCLK Generic Clock Waveform at the Processor Core Pins 37 14 BCLK TCK PICCLK Generic Clock Waveform at the Processor Edge cem M 38 15 Low to High AGTL Receiver Ringback Tolerance eese 40 16 Non AGTL Overshoot Undershoot Settling Limit and Ringback 40 17 Pentium II Processor S E C C Side View 42 18 Pentium II Processor SE CC Package Top and Side View 45 19 Pentium II Processor
66. he TAP chain with the TDI of the first component coming from the Debug Port and the TDO from the last component going to the Debug Port In a two way MP system be cautious when including an empty SC 242 connector in the scan chain All connectors in the scan chain must have a processor installed to complete the chain or the system must support a method to bypass the empty connectors SC 242 terminator substrates should not connect TDI to TDO in order to avoid placing the TDO pull up resistors in parallel See Slot 1 Bus Terminator Card Design Guidelines Order Number 243409 for more details Maximum Ratings Table 4 contains Pentium II processor stress ratings only Functional operation at the absolute maximum and minimum is not implied nor guaranteed The processor should not receive a clock while subjected to these conditions Functional operating conditions are given in the AC and DC tables in Section 2 11 and Section 2 13 Extended exposure to the maximum ratings may affect device reliability Furthermore although the processor contains protective circuitry to resist damage from static electric discharge one should always take precautions to avoid high static voltages or electric fields Datasheet Intel Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 4 Absolute Maximum Ratings 2 11 Datasheet Symbol Parameter Min Max Unit Notes TSTORAGE Processor storage temperat
67. his section are defined at the Pentium II processor edge fingers See Section 7 0 for the processor edge finger signal definitions and Section 5 0 for the signal listing Most of the signals on the Pentium II processor system bus are in the AGTL signal group These signals are specified to be terminated to 1 5 V The DC specifications for these signals are listed in Table 6 To allow connection with other devices the Clock CMOS APIC and TAP signals are designed to interface at non AGTL levels The DC specifications for these pins are listed in Table 7 Table 5 through Table 8 list the DC specifications for Pentium II processors operating at 100 MHz processor system bus frequencies Specifications are valid only while meeting specifications for case temperature clock frequency and input voltages Care should be taken to read all notes associated with each parameter 21 Pentium II Processor at 350 MHz 400 MHz and 450 MHz 22 Intel Voltage and Current Specifications 1 Symbol Parameter Core Freq Min Typ Max Unit Notes VCCcorE Vcc for processor core 1 9 2 00 2 1 V 2 4 5 6 vce Voe for second level 3135 330 3465 V 33v45 7 cache VTT AG TL DEE 1365 Lan 1635 V 1 549 8 voltage Baseboard Processor core voltage Tolerance static tolerance level at 0 070 0 070 V 4 9 Static SC 242 pins Baseboard Processor core voltage Tolerance
68. ications Reset Conditions 1 Intel T Parameter Min Max Unit Figure Notes T16 Reset Configuration Signals g e A 14 5 BRO FLUSH 4 BCLKs 9 SE oi INIT Setup Time T17 Reset Configuration Signals A 14 5 BRO FLUSH 2 20 BCLKs 9 Ri d INIT Hold Time T18 Reset Configuration Signals A20M IGNNE LINT 1 0 1 ms 9 ee RESET Setup Time T19 Reset Configuration Signals Avex asseition of A20M IGNNE LINT 1 0 5 BCLKs 9 2 A RESET Delay Time T20 Reset Configuration Signals A20M IGNNE LINT 1 0 2 20 BCLKs 9 10 After clock that deasserts RESET Hold Time NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 For a Reset the clock ratio defined by these signals must be a safe value their final or a lower multiplier within this delay unless PVRGOOD is being driven inactive Table 17 System Bus AC Specifications APIC Clock and APIC I O at the Processor Edge Fingers ee T Parameter Min Max Unit Figure Notes T21 PICCLK Frequency 2 0 33 3 MHz T22 PICCLK Period 30 0 500 0 ns 6 T23 PICCLK High Time 12 0 ns 6 T24 PICCLK Low Time 12 0 ns 6 T25 PICCLK Rise Time 1 0 5 0 ns 6 T26 PICCLK Fall Time 1 0 5 0 ns 6 T27 PICD 1 0 Setup Time 8 5 ns 8 4 T28 PICD 1 0 Hold Time 3 0 ns 8 4 T29 PICD
69. ified signals convey transaction snoop operation results and must connect the appropriate pins of all Pentium II processor system bus agents Any such agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR The IERR Internal Error signal is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the Pentium II processor system bus This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET BINIT or INIT TI Pentium II Processor at 350 MHz 400 MHz and 450 MHz l n 78 Table 41 Signal Description Sheet 5 of 8 Name Type Description IGNNE The IGNNE Ignore Numeric Error signal is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the correspo
70. ing the input voltage to the converter for the VID line Datasheet 2 7 2 8 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz pull ups A resistor of greater than or equal to 10 kQ may be used to connect the VID signals to the converter input Note that no changes have been made to the physical connector between the VRM 8 1 and VRM 8 2 specifications though pin definitions have changed Processor System Bus Unused Pins All RESERVED pins must remain unconnected Connection of these pins to Nom Vccr2 Vss or to any other signal including each other can result in component malfunction or incompatibility with future Pentium II processors See Section 5 4 for a pin listing of the processor and the location of each RESERVED pin All TESTHI pins must be connected to 2 5 V via a pull up resistor of between 1 and 100 k value PICCLK must be driven with a valid clock input and the PICD 1 0 lines must be pulled up to 2 5 V even when the APIC will not be used A separate pull up resistor must be provided for each PICD line see Table 2 for recommended values For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level Unused AGTL inputs should be left as no connects AGTL termination is provided on the processor Unused active low CMOS inputs should be connected to 2 5 V Unused active high inputs should be connected to ground Vss Unused outputs can be left unconnected
71. ing these modes For more information see the Pentium II Processor Developer s Manual Order Number 243502 Due to the inability of processors to recognize bus transactions during the Sleep and Deep Sleep states two way MP systems are not allowed to have one processor in Sleep Deep Sleep state and the other processor in Normal or Stop Grant state simultaneously Normal State State 1 This is the normal operating state for the processor AutoHALT Powerdown State State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the AutoHALT Power Down state See the Intel Architecture Software Developer s Manual Volume III System Programmer s Guide Order Number 243192 for more information FLUSH will be serviced during the AutoHALT state and the procesor will return to the AutoHALT state The system can generate a STPCLK while the processor is in the AutoHALT Power Down state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state Stop Grant State State 3 The Stop Grant state on the processor is entered when the STPCLK signal is asserted Since the AGTL signal pins rec
72. ing voltage this will not be an issue A system should not rely on the diodes for overshoot undershoot protection as this will negatively affect the life of the components and make meeting the ringback specification very difficult Ringback Specification Ringback refers to the amount of reflection seen after a signal has switched The ringback specification is the voltage that the signal rings back to after achieving its maximum absolute value See Figure 16 for an illustration of ringback Excessive ringback can cause false signal detection or extend the propagation delay The ringback specification applies to the input pin of each receiving agent Violations of the signal ringback specification are not allowed under any circumstances for non AGTL signals Ringback can be simulated with or without the input protection diodes that can be added to the input buffer model However signals that reach the clamping voltage should be evaluated further See Table 25 for the signal ringback specifications for non AGTL signals for simulations at the processor core and Table 26 for guidelines on measuring ringback at the edge fingers Signal Ringback Specifications for Non AGTL Signal Simulation at the Processor Core Maximum Ringback Input Signal Group Transition with Input Diodes Present Unit Figure Non AGTL Signals 021 1 7 V 16 Non AGTL Signals 10 0 7 V 16 NOTE 1 Unless otherwise noted all specifications in
73. input should be capable of delivering a recommended minimum dlcc dt defined in Table 5 while maintaining the required tolerances also defined in Table 5 Processor System Bus AGTL Decoupling The Pentium II processor contains high frequency decoupling capacitance on the processor substrate bulk decoupling must be provided for by the system motherboard for proper AGTL bus operation See AP 827 100 MHz GTL Layout Guidelines for the Pentium II Processor and Intel 440BX AGPset Order Number 243735 AP 587 Pentium II Processor Power Distribution Guidelines Order Number 243332 and the Pentium II Processor Developer s Manual Order Number 243502 for more information Processor System Bus Clock and Processor Clocking The BCLK input directly controls the operating speed of the Pentium II processor system bus interface All Pentium II processor system bus timing parameters are specified with respect to the rising edge of the BCLK input See the Pentium II Processor Developer s Manual Order Number 243502 for further details Mixing Processors of Different Frequencies Mixing processors of different internal clock frequencies is not supported and has not been validated by Intel One should also note that when attempting to mix processors rated at different frequencies in a two way MP system a common bus clock frequency and a set of multipliers must be found that is acceptable to both processors in the system A processor may run
74. ins must be connected to a system ground plane Decoupling Guidelines Due to the large number of transistors and high internal clock speeds the processor is capable of generating large average current swings between low and full power states This causes voltages on power planes to sag below their nominal values if bulk decoupling is not adequate Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 5 Failure to do so can result in timing violations or a reduced lifetime of the component Datasheet In 2 4 1 2 4 2 2 5 2 5 1 2 6 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Processor VCCcogg Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and keep an interconnect resistance from the regulator or VRM pins to the SC 242 connector of less than 0 3 mQ This can be accomplished by keeping a maximum distance of 1 0 inches between the regulator output and SC 242 connector The recommended Vcc 4 interconnect is a 2 0 inch wide the width of the VRM 8 2 connector by 1 0 inch long maximum distance between the SC 242 connector and the VRM 8 2 connector plane segment with a 1 ounce plating Bulk decoupling for the large current swings when the part is powering on or entering exiting low power states is provided on the voltage regulation module VRM The Vcceor
75. ion in Table 14 and Table 15 and be followed by a 1 ms RESET pulse The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation PWRGOOD Relationship at Power On sox HEREIN NE NX FN E XXL V e Veer PWRGOOD Vuen 1 msec gt RESET 0026 00 REQ 4 0 VO The REQ 4 0 Request Command signals must connect the appropriate pins of all Pentium II processor system bus agents They are asserted by the current bus owner over two clock cycles to define the currently active transaction type RESET Asserting the RESET signal resets all processors to known states and invalidates their L1 and L2 caches without writing back any of their contents RESET must remain active for one microsecond for a warm Reset for a power on Reset RESET must stay active for at least one millisecond after VCCcorg and CLK have reached their proper specifications On observing active RESET all Pentium II processor system bus agents will deassert their outputs within two clocks A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the P6 Family of Processors Hardware Developer s Manual Order Number 244001 for details The processor may have its outputs tristated via power on configuration Otherwis
76. k will keep the processor temperature within the specifications see Section 4 0 provided airflow through the fan heatsink is unimpeded and the air temperature entering the fan is below 45 C see Figure 43 for measurement location Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life Figure 43 illustrates an acceptable airspace clearance for the fan heatsink Datasheet 73 Pentium II Processor at 350 MHz 400 MHz and 450 MHz l n 7 0 Pentium II Processor Signal Description This section provides an alphabetical listing of all Pentium II processor signals The tables at the end of this section summarize the signals by direction output input and I O 7 1 Alphabetical Signals Reference Table 41 Signal Description Sheet 1 of 8 Name Type Description 100 663 IO This bidirectional signal is used to select the system bus frequency A logic low will select a 66 MHz system bus frequency and a logic high 3 3 V will select a 100 MHz system bus frequency The frequency is determined by the processor s PCIset and frequency synthesizer All system bus agents must operate at the same frequency in a two way MP Pentium II procesor configuration this signal must connect the pins of both Pentium II processors This signal will be grounded by processors that are on
77. leep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and APIC processor core units SMI The SMI System Management Interrupt signal is asserted asynchronously by system logic On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler STPCLK The STPCLK Stop Clock signal when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK The TCK Test Clock signal provides the clock input for the Pentium II processor Test Bus also known as the Test Access Port TDI The TDI Test Data In signal transfers serial test data into the Pentium II processor TDI provides the serial input needed for JTAG specification support TDO The TDO Test Data Out signal transfers serial test data out of the Pen
78. leep state the SLP pin can be deasserted to re enter the Stop Grant state 13 Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel 2 2 7 23 2 4 14 While in Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals are allowed on the system bus while the processor is in Deep Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior Clock Control The processor provides the clock signal to the L2 cache During AutoHALT Power Down and Stop Grant states the processor will process a system bus snoop The processor will not stop the clock to the L2 cache during AutoHALT Power Down or Stop Grant states Entrance into the Halt Grant Snoop state will allow the L2 cache to be snooped similar to the Normal state When the processor is in Sleep and Deep Sleep states it will not respond to interrupts or snoop transactions During the Sleep state the clock to the L2 cache is not stopped During the Deep Sleep state the clock to the L2 cache is stopped The clock to the L2 cache will be restarted only after the internal clocking mechanism for the processor is stable i e the processor has re entered Sleep state PICCLK should not be removed during the AutoHALT Power Down or Stop Grant states PICCLK can be removed during the Sleep or Deep Sleep state
79. lieu 54 Pentium Il Processor Assembly S E C C 2 Package Heat Sink Attach BOSS S CUOM TE 54 Pentium II Processor Assembly S E C C 2 Package Side View OLGA Substrate Shown sess enne nnns 55 Detail View of Cover in the Vicinity of the Substrate Attach Features 55 Pentium II Processor Substrate S E C C 2 Package Edge Finger Contact BID t 56 Pentium II Processor Markings S E C C 2 Package 56 Boxed Pentium II Processor in the S E C C Packaging Installed in Retention Mechanism Fan Power Cable Not Shown seen 65 Boxed Pentium II Processor in the S E C C 2 Packaging Fan Power Cable NOt SHOWN c eee 65 Side View Space Requirements for the Boxed Processor with S E C C PACK AG IN DEE 66 Front View Space Requirements for the Boxed Processor with S E C C miii sz re Tuo e S 67 Side View Space Requirements for the Boxed Processor with S E C C 2 Packaging P eae 67 Front View Space Requirements for the Boxed Processor with S E C C 2 PACK AG Dojo DEE 68 Top View Air Space Requirements for the Boxed Processor 68 Heatsink Support Hole Locations and Gize nnn nssensrn enerne nnen 70 Side View Space Requirements for Boxed Processor Fan Heatsink Supports 71 Top View Space Requirements for Boxed Processor Fan Heatsink Suppo
80. ly capable of operating at a host frequency of 66 MHz On motherboards which support operation at either 66 or 100 MHz this signal must be pulled up to 3 3 V with a 200Q resistor as shown in the figure below and provided as a frequency selection signal to the clock driver synthesizer If the system motherboard is not capable of operating at 100 MHz e g Intel 440FX and 440LX PClIset based systems it should ground this signal and generate a 66 MHz system bus frequency This signal can also be incorporated into RESET logic on the motherboard if only 100 MHz operation is supported thus forcing the RESET signal to remain active as long as the 100 66 signal is low 100 66 Pin Example 3 3 Volts CK100 100 66 Pentium II Processor Processor Core A 35 3 VO The A 35 3 Address signals define a 2 byte physical memory address space When ADS is active these pins transmit the address of a transaction when ADS is inactive these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the Pentium II processor system bus The A 35 24 signals are parity protected by the AP1 parity signal and the A 23 3 signals are parity protected by the APO parity signal On the active to inactive transition of RESET the processors sample the A 35 3 pins to determine their power on configuration See the Pentium II Processor Developer s Manual Order Number 2
81. mination is used see Section 2 1 15 The current specified is also for AutoHALT state 16 Maximum values are specified by design characterization at nominal Vcccogg and nominal V cc 17 Based on simulation and averaged over the duration of any change in current Use to compute the maximum inductance tolerable and reaction time of the voltage regulator This parameter is not tested 18 dIcc dt specifications are measured and specified at the SC 242 connector pins 19 Vccs and Iccs are not used by the Pentium II processors This supply is used for the SC 242 Test Kit 23 Pentium II Processor at 350 MHz 400 MHz and 450 MHz In Table 6 Table 7 2 12 24 AGTL Signal Groups DC Specifications 1 Symbol Parameter Min Max Unit Notes VIL Input Low Voltage 0 3 0 82 V VIH Input High Voltage 1 22 VTT V 2 3 7 8 Ron Buffer On Resistance 16 67 Q 6 IL Leakage Current 100 HA 4 ILO Output Leakage Current 15 HA 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 Vin and Vou for the Pentium II processor may experience excursions of up to 200 mV above Vrr for a single system bus clock However input signal drivers must comply with the signal quality specifications in Section 3 0 Minimum and maximum Vrr are given in Table 8 0 Vin 2 0 V 5 0 Vour 2 0 V 45906 Refer to the I O
82. n processor marking information Figure 28 Pentium II Processor S E C C 2 Package Top and Side Views OLGA Processor Core m TOP VIEW BGA COVER H P PACKAGE 7 la E y T T y o o e 0000 e 3 e BOREAM l e ol do pBBnB y 00 uuu u e o o N o FFP O5 sesal 2 COVER SIDE VIEW T SIDE SUSTRATE VIEW me Datasheet n Pentium II Processor at 350 MHz 400 MHz and 450 MHz Figure 29 Pentium II Processor S E C C 2 Package Top and Side Views PLGA Processor Core e TOP VIEW PLGA NER PACKAGE m b I CH E E Ty I enee o o see a K 22b HLEN d ounoocoto ougag0 00 2 Cr aot M WA EAE MAMA COVER SIDE VIEW RIGHT SIDE SUBSTRATE SIDE VIEW VIEW Figure 30 Pentium II Processor Assembly S E C C 2 Package Primary View 2X 156 KEEP OUT 2X 201 KEEP OUT m 4 68
83. nding I O Write bus transaction During active RESET the Pentium II processor begins sampling the A20M IGNNE and LINT 1 0 values to determine the ratio of core clock frequency to bus clock frequency See Table 9 On the active to inactive transition of RESET the Pentium II processor latches these signals and freezes the frequency ratio internally System logic must then release these signals for normal operation INIT The INIT Initialization signal when asserted resets integer registers inside all processors without affecting their internal L1 or L2 caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all Pentium II processor system bus agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST LINT 1 0 The LINT 1 0 Local APIC Interrupt signals must connect the appropriate pins of all APIC Bus agents including all processors and the core logic or I O APIC component When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINTI becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Bot
84. ng Edge Ringback 0 5 V 14 3 V6 Tline Ledge Voltage 1 0 1 7 V 14 At Ledge Midpoint 4 VT Tline Ledge Oscillation 0 2 V 14 Peak to Peak NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 This is the Pentium II processor system bus clock overshoot and undershoot measurement guideline 3 The rising and falling edge ringback voltage guideline is the minimum rising or maximum falling absolute voltage the BCLK signal may dip back to after passing the Vin rising or Vu falling voltage limits This guideline is an absolute value 4 The BCLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge The midpoint voltage level of this ledge should be within the range of the guideline 5 The ledge V7 is allowed to have peak to peak oscillation as given in the guideline Figure 14 BCLK TCK PICCLK Generic Clock Waveform at the Processor Edge Fingers Voltage K T3 Time 000808 3 2 AGTL Signal Quality Specifications and Measurement Guidelines Many scenarios have been simulated to generate a set of GTL layout guidelines which are available in AP 827 100 MHz GTL Layout Guidelines for the Pentium II Processor and Intel 440BX AGPset Order Number 243735 Refer to the Pentium II Processor Developer s Manual Order Number 243502 for the GTL buffer s
85. ngs for the TAP signals at the processor edge fingers are referenced to the TCK rising edge at 0 70 V All TAP signal timings TMS TDI etc are referenced at 1 25 V at the processor edge fingers 33 Pentium II Processor at 350 MHz 400 MHz and 450 MHz Figure 6 BCLK PICCLK and TCK Generic Clock Waveform CLK T5 pT25 T34 Rise Time T6 T26 T35 Fall Time T3 T23 T32 High Time T4 T24 T33 Low Time T1 T22 T31 BLCK TCK PCICLK Period Note BCLK is referenced to 0 5 V and 2 0 V PICCLK and TCK are referenced to 0 7 V and 1 7 V 000761a Figure 7 System Bus Valid Delay Timings CLK Tx Signal Valid Tpw Tx T7 T11 T29 Valid Delay Tpw T14 T15 Pulse Wdith V 1 0V for GTL signal group 1 25V for CMOS APIC and JTAG signal groups 000762b Figure 8 System Bus Setup and Hold Timings CLK Ts T8 T12 T27 Setup Time Th T9 T13 T28 Hold Time V 1 0V for GTL signal group 1 25V for CMOS APIC and JTAG signal groups 000763b 34 Datasheet Figure 9 Figure 10 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz System Bus Reset and Configuration Timings abbia uu RESET Configuration wont oven TTT as i C YTD LINT 1 0 T Configuration Z id A 14 5 BRO Valid MM FLUSH INT T T9 and T9 GTL Input Hold Time T T8 and T8 GTL Inpu
86. nology were shipped with fan heatsink supports These supports differ from supports for passive heatsinks The boxed processor fan heatsink support requires heatsink support holes in the motherboard Location and size of these holes are given in Figure 44 69 Pentium II Processor at 350 MHz 400 MHz and 450 MHz In Figure 44 Heatsink Support Hole Locations and Size 242 Contact Slot Connector 0 156 Thru 1760 Ze 0 187 Thru Recommendations E 2 932 t 1 860 gt 2X 0 300 diameter trace keepout all external layers 0 250 diameter trace keepout all internal layers All dimensions in inches Any motherboard components placed in the area beneath the fan heatsink supports must recognize the clearance given in Table 38 Component height restrictions for passive heatsink support designs as described in AP 588 Mechanical and Assembly Technology for S E C Cartridge Processors Order Number 243333 still apply Motherboards designed for use by system integrators should not have objects installed in the heatsink support holes Otherwise removal instructions for objects preinstalled in the heatsink support holes should be included in the motherboard documentation Table 38 Boxed Processor Fan Heatsink Support Dimensions Fig Ref Refers to Label Figure Dimensions Inches Min Typ Max M Figure 45 Fan Heatsink support height 2 26
87. nt causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BRO BRIX IO The BRO and BR1 Bus Request pins drive the BREQ 1 0 signals in the system The BREQ 1 0 signals are interconnected in a rotating manner to individual processor pins The table below gives the rotating interconnect between the processor and bus signals BRO I O and BR1 Signals Rotating Interconnect Bus Signal Agent 0 Pins Agent 1 Pins BREQO BRO BRIX BREQI BRIX BRO During power up configuration the central agent must assert the BRO bus signal All symmetric agents sample their BR 1 0 pins on active to inactive transition of RESET Th pin on which the agent samples an active level determines its agent ID All agents then configure their pins to match the appropriate bus signal protocol as shown below BR 1 0 Signal Agent IDs Pin Sampled Active in RESET Agent ID BRO 0 BRIX 1 D 63 0 IO The D 63 0 Data signals are the data signals These signals provide a 64 bit data path between the Pentium II processor system bus agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer Datasheet Pentium II Process
88. on From Edge d PRAE of Fan Heatsink Shroud n EN Figure 43 Airflow keep out zones from end of fan heatsink 0 40 L Figure 43 Airflow keepout zones from face of fan heatsink 0 20 NOTE 1 See Figure 45 label N Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 225 grams See Section 4 0 and Section 5 0 for details on the heatsink preformance requirements and processor weight Boxed Processor Retention Mechanism and Fan Heatsink Supports The boxed processor requires processor retention mechanism s to secure the processor in the 242 contact slot connector S E C C processors must use either the retention mechanism described in AP 588 Mechanical and Assembly Technology for S E C Cartridge Processors Order Number 243333 or retention mechanisms that have been designed to support S E C C S E C C 2 and Single Edge Processor Package S E P P form factors also known as universal retention mechanisms S E C C 2 processors must use either retention mechanisms described in AP 826 Mechanical Assembly and Customer Manufacturing Technology for S E P Packages Order Number 243748 The boxed processor will not ship with a retention mechanism Motherboards designed for use by system integrators must include retention mechanisms that support the S E C C and S E C C 2 form factors and the appropriate installation instructions Some boxed Pentium II processors using the S E C C packaging tech
89. or at 350 MHz 400 MHz and 450 MHz Table 41 Signal Description Sheet 4 of 8 Datasheet Name Type Description DBSY VO The DBS Y Data Bus Busy signal is asserted by the agent responsible for driving data on the Pentium II processor system bus to indicate that the data bus is in use The data bus is released after DBS Y is deasserted This signal must connect the appropriate pins on all Pentium II processor system bus agents DEFER The DEFER signal is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or I O agent This signal must connect the appropriate pins of all Pentium II processor system bus agents DEP 7 0 f VO The DEP 7 0 Data Bus ECC Protection signals provide optional ECC protection for the data bus They are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins of all Pentium II processor system bus agents which use them The DEP 7 0 signals are enabled or disabled for ECC protection during power on configuration DRDY VO The DRDY Data Ready signal is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi cycle data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all Pentium II processor system bus agents EMI
90. or the processor core but should be set to 2 3 Vrr for other AGTL logic using a voltage divider on the motherboard It is important that the motherboard impedance be specified and held to a 65Q 15 tolerance and that the Datasheet Table 8 2 13 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz intrinsic trace capacitance for the AGTL signal group traces is known and well controlled For more details on GTL see the Pentium II Processor Developer s Manual Order Number 243502 and AP 827 100 MHz GTL Layout Guidelines for the Pentium II Processor and Intel 440BX AGPset Order Number 243735 AGTL Bus Specifications 1 2 Symbol Parameter Min Typ Max Units Notes VTT Bus Termination Voltage 1 365 1 50 1 635 V 1 5 V 9 RTT Termination Resistor 56 Q 5 VREF Bus Reference Voltage 2 3 VTT V 4 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 Pentium II processors contain AGTL termination resistors at the end of each signal trace on the processor substrate Pentium II processors generate Vrer on the processor substrate by using a voltage divider on Vrr supplied through the SC 242 connector 3 Vrr must be held to 1 5 V 9 dIccvrr dt is specified in Table 5 It is recommended that Vrr be held to 1 5 V 3 while the Pentium II processor system bus is idle This is measured at the processo
91. ower supply for the processor core and L2 cache I O logic Vcc12 is the power supply for the L2 cache component core logic VID 4 0 is described in Section 2 6 Vr is used to terminate the system bus and generate VREF on the processor substrate Vss is system ground TESTHI should be connected to 2 5 V with a 1 100 kQ resistor Vcc5 is not connected to the Pentium II processors This supply is used for the Slot 1 Test Kit SLOTOCCt is described in Section 7 0 100 668 is described in Section 2 8 2 and Section 7 0 EMI pins are described in Section 7 0 THERMDP THERMDN are described in Section 7 0 Asynchronous vs Synchronous for System Bus Signals All AGTL signals are synchronous to BCLK All of the CMOS Clock APIC and TAP signals can be applied asynchronously to BCLK All APIC signals are synchronous to PICCLK All TAP signals are synchronous to TCK System Bus Frequency Select Signal 100 663 This bidirectional signal is used to select the system bus frequency A logic low will select a 66 MHz system bus frequency and a logic high 3 3 V will select a 100 MHz system bus frequency The frequency is determined by the processor s AGPset and frequency synthesizer All system bus agents must operate at the same frequency in a two way MP Pentium II processor configuration this signal must connect the pins of both Pentium II processors This signal will be grounded by processors that are only capable of operating at a host
92. p at the Processor Core Pins 1554 T Parameter Min Max Unit Figure Notes T11 CMOS Output Valid Delay 0 00 8 00 ns 7 3 T12 CMOS Input Setup Time 4 00 ns 8 6 7 8 T13 CMOS Input Hold Time 1 30 ns 8 6 7 T14 CMOS Input Pulse Width except Active and Inactive PWRGOOD BCLKs states T15 PWRGOOD Inactive Pulse Width 10 BCLKs 7 10 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 3 KZ tA H Datasheet These specifications are tested during manufacturing All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1 25 V at the processor core pins All CMOS signal timings address bus data bus etc are referenced at 1 25 V These signals may be driven asynchronously Valid delay timings for these signals are specified to 2 5 V 5 See Table 2 for pull up resistor values This specification applies to Pentium II processors operating with a 100 MHz Pentium II processor system bus only To ensure recognition on a specific clock the setup and hold times with respect to BCLK must be met INTR and NMI are only valid when the local APIC is disabled LINT 1 0 are only valid when the local APIC is enabled When driven inactive or after Veccore Vcc and BCLK become stable 29 Pentium II Processor at 350 MHz 400 MHz and 450 MHz 30 Table 16 System Bus AC Specif
93. pecification 38 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 23 provides the AGTL signal quality specifications for Pentium II processors for use in simulating signal quality at the processor core Table 24 provides AGTL signal quality guidelines for measuring and testing signal quality at the processor edge fingers Figure 15 describes the signal quality waveform for AGTL signals at the processor core and edge fingers For more information on the AGTL interface see the Pentium II Processor Developer s Manual Order Number 243502 Table 23 AGTL Signal Groups Ringback Tolerance Specifications at the Processor Core 53 Tf Parameter Min Unit Figure Notes a Overshoot 100 mV 15 4 t Minimum Time at High 0 50 ns 15 4 p Amplitude of Ringback 20 mV 15 4 5 6 Final Settling Voltage 20 mV 15 4 6 Duration of Squarewave Ringback N A ns 15 NOTES Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes Specifications are for the edge rate of 0 3 0 8 V ns See Figure 15 for the generic waveform All values specified by design characterization This specification applies to Pentium II processors operating with a 100 MHz Pentium II processor system bus only Ringback below Vrer 20 mV is not supported Intel recommends performing simulations using an amplitude of 120 mV to allow margin for o
94. processor will respond to snoop transactions on the Pentium II processor system bus while in Stop Grant state or in AutoHALT Power Down state During a snoop transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the Pentium II processor system bus has been serviced whether by the processor or another agent on the Pentium II processor system bus After the snoop is serviced the processor will return to the Stop Grant state or AutoHALT Power Down state as appropriate Sleep State State 5 The Sleep state is a very low power state in which the processor maintains its context maintains the phase locked loop PLL and has stopped all internal clocks The Sleep state can only be entered from Stop Grant state Once in the Stop Grant state the SLP pin can be asserted causing the processor to enter the Sleep state The SLP pin is not recognized in the Normal or AutoHALT states Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP or RESET are allowed on the system bus while the processor is in Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior
95. put A73 D 1 AGTL I O A19 PICD 0 CMOS UO B71 D 2 AGTL I O B22 PICD 1 CMOS UO A72 D 3 AGTL HO B23 PRDY AGTL Output B70 D 4 AGTL I O A20 PREQ CMOS Input ATI D 5 AGTL I O Al2 PWRGOOD CMOS Input B68 D 6 AGTL I O B102 REQ 0 AGTL I O Datasheet Table 36 Signal Listing in Order by Signal Name Sheet 3 of 4 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Pin No Pin Name Signal Buffer Type Pin No Pin Name Signal Buffer Type B67 D 7 AGTL I O B103 REQ 1 AGTL I O A69 D 8 AGTL I O A107 REQ 2 AGTL I O A68 D 9 AGTL I O A108 REQ 3 AGTL I O A65 D 10 AGTL I O B104 REQ 4 AGTL I O A64 D 11 AGTL I O A16 Reserved Reserved for Future Use B66 D 12 AGTL I O A47 Reserved Reserved for Future Use A63 D 13 AGTL I O A88 Reserved Reserved for Future Use A67 D 14 AGTL I O A113 Reserved Reserved for Future Use B64 D 15 AGTL I O A116 Reserved Reserved for Future Use A61 D 16 AGTL I O B12 Reserved Reserved for Future Use B63 D 17 AGTL I O B14 THERMDP Diode Anode B60 D 18 AGTL I O B15 THERMDN Diode Cathode B59 D 19 AGTL I O B20 Reserved Reserved for Future Use B62 D 20 AGTL I O B112 Reserved Reserved for Future Use A60 D 21 AGTL I O B74 RESET AGTL Input B58 D 22 AGTL I O B114 RP AGTL I O A59 D 23 AGTL I O B108 RS 0 AGTL Input
96. r edge fingers 4 Vrer is generated on the processor substrate to be 2 3 Vrr nominally System Bus AC Specifications The Pentium II processor system bus timings specified in this section are defined at the Pentium II processor edge fingers and the processor core pads Unless otherwise specified timings are tested at the processor core during manufacturing Timings at the processor edge fingers are specified by design characterization See Section 7 0 for the Pentium II processor edge connector signal definitions See the Pentium II Processor at 233 266 300 and 333 MHz Order Number 243335 for more detail Table 9 through Table 20 list the AC specifications associated with the Pentium II processor system bus These specifications are broken into the following categories Table 9 through Table 11 contain the system bus clock core frequency and cache bus frequencies Table 12 and Table 13 contain the AGTL specifications Table 14 and Table 15 are the CMOS signal group specifications Table 16 contains timings for the Reset conditions Table 17 and Table 18 cover APIC bus timing and Table 19 and Table 20 cover TAP timing For each pair of tables the first table contains timing specifications for measurement or simulation at the processor edge fingers The second table contains specifications for simulation at the processor core pads All Pentium II processor system bus AC specifications for the AGTL signal group are relative to the rising ed
97. r the AGTL signals are referenced to the BCLK rising edge at 0 50 V at the processor edge fingers This reference is to account for trace length and capacitance on the processor substrate allowing the processor core to receive the signal with a reference at 1 25 V All AGTL signal timings address bus data bus etc are referenced at 1 00 V at the processor edge fingers 3 All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0 7 V at the processor edge fingers This reference is to account for trace length and capacitance on the processor substrate allowing the processor core to receive the signal with a reference at 1 25 V All CMOS signal timings compatibility signals etc are referenced at 1 25 V at the processor edge fingers 4 The internal core clock frequency is derived from the Pentium II processor system bus clock The system bus clock to core clock ratio is determined during initialization as described in Section 2 5 Table 11 shows the supported ratios for each processor 5 The BCLK period allows a 40 5 ns 0 0ns tolerance for clock driver variation 6 This specification applies to Pentium II processors when operating with a Pentium II processor system bus frequency of 100 MHz 7 The BCLK offset time is the absolute difference needed between the BCLK signal arriving at the Pentium II processor edge finger at 0 5 V vs arriving at the core logic at 1 25 V The positive offset is needed to account for the dela
98. rance information are considered reference dimensions only 2 Z reference datum shown in Figure 35 010 vsd Figure 27 Pentium II Processor Markings S E C C Package 2 D Matrix Mark See Note Li D E F fr D A Vv A amp f LB c Y B NOTE Please refer to the Pentium II 8 pentium jl Hologram Processor Specification Update 3 A Location for this information o intel Datasheet 51 a Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel s Table 31 Description Table for Processor Markings S E C C Packaged Processor 5 2 52 Code Letter Description A Logo B Product Name C Trademark D Logo E Product Name F Dynamic Mark Area with 2 D matrix S E C C 2 Mechanical Specification S E C C 2 packaged drawings and dimension details are provided in Figure 28 through Figure 35 Figure 28 shows all views of the Pentium II processor in an S E C C 2 package using an OLGA packaged processor core Figure 29 shows all views of a Pentium II processor in an S E C C 2 package using a PLGA packaged processor core Figure 30 through Figure 34 show the S E C C 2 package dimensions Figure 35 provides dimensions of the processor substrate edge finger contacts and Figure 36 and Table 32 contai
99. rchitecture processors The Pentium II processor also executes MMX technology instructions for enhanced media and communication performance The Pentium II processor utilizes multiple low power states such as AutoHALT Stop Grant Sleep and Deep Sleep to conserve power during idle times The Pentium II processor utilizes the same multiprocessing system bus technology as the Pentium Pro processor This allows for a higher level of performance for both uni processor and two way multiprocessor 2 way MP systems Memory is cacheable for up to 4 GB of addressable memory space allowing significant headroom for business desktop systems Please refer to the Intel Specification Update document s S spec number table to determine the cacheability for a given processor The Pentium II processor system bus operates in the same manner as the Pentium Pro processor system bus The Pentium II processor system bus uses a variant of GTL signal technology called AGTL signal technology The Pentium II processor deviates from the Pentium Pro processor by using commercially available die for the second level L2 cache The L2 cache the TagRAM and burst pipelined synchronous static RAM BSRAM memories are now multiple die Transfer rates between a Pentium II processor s core and L2 cache are one half the processor core clock frequency and scale with the processor core frequency Both the TagRAM and BSRAM receive clocked data directly from the Pentium II processor core
100. re pin All CMOS signal timings compatibility signals etc are referenced at 1 25 V at the processor core pins 4 The internal core clock frequency is derived from the Pentium II processor system bus clock The system bus clock to core clock ratio is determined during initialization as described in Section 2 5 Table 11 shows the supported ratios for each processor 5 The BCLK period allows a 0 5 ns tolerance for clock driver variation 6 This specification applies to the Pentium II processor when operating with a Pentium II processor system bus frequency of 100 MHz 7 Due to the difficulty of accurately measuring clock jitter in a system it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 to 20 pF This should be measured on the rising edges of adjacent BCLKs crossing 1 25 V at the processor core pin The jitter present must be accounted for as a component of BCLK timing skew between devices 8 The clock driver s closed loop jitter bandwidth must be set low to allow any PLL based device to track the jitter created by the clock driver The 20 dB attenuation point as measured into a 10 to 20 pF load should be less than 500 kHz This specification may be ensured by design characterization and or measured with a spectrum analyzer 9 Not 100 tested Specified by design characterization as a clock driver requirement 10 The average period over a luS period of tim
101. ridge Terminology The following terms are used often in this document and are explained here for clarification Pentium II processor The entire product including internal components substrate extended thermal plate and cover e S E C C The processor packaging technology is called a Single Edge Contact Cartridge Initial releases of the Pentium II processor are based upon this packaging technology S E C C 2 The follow on to S E C C processor packaging technology The biggest difference from its predecessor is that it has no extended thermal plate thus reducing thermal resistance Processor substrate The structure on which components are mounted inside the S E C C or S E C C 2 package technology with or without components attached Processor votre The processor s execution engine Datasheet 1 2 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Extended Thermal Plate This S E C C 100 MHz processor feature is the surface used to attach a heatsink or other thermal solution to the processor The extended thermal plate has an extended skirt as compared to the 66 MHz Pentium II processors for increased thermal capabilities Cover The plastic casing that covers the backsire of the substrate and holds processor branding and marking information Latch arms An S E C C processor feature which can be used as a means for securing the processor in the retention mechanism s PLGA Plas
102. rocessor at 233 266 300 333 MHz Order Number 243335 Pentium II Processor Specification Update Order Number 243337 Slot 1 Connector Specification Order Number 243397 Slot 1 Bus Terminator Card Design Guidelines Order Number 243409 Intel Architecture Software Developer s Manual Order Number 243193 Volume I Basic Architecture Order Number 243190 Volume II Instruction Set Reference Order Number 243191 Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel 2 0 Volume III System Programming Guide Order Number 243192 P6 Family of Processors Hardware Developer s Manual Order Number 244001 Pentium II Processor I O Buffer Models Quad Format developer intel com Electrical Specifications 2 1 10 Processor System Bus and Vrer Most Pentium II processor signals use a variation of the low voltage Gunning Transceiver Logic GTL signaling technology The Pentium II processor system bus specification is similar to the GTL specification but has been enhanced to provide larger noise margins and reduced ringing The improvements are accomplished by increasing the termination voltage level and controlling the edge rates This specification is different from the standard GTL specification and is referred to as GTL For more information on GTL specifications see AP 827 100 MHz GTL Layout Guidelines for the Pentium II Processor and Intel 440BX AGPset Order Number 243735 The Pentium II
103. rocessors are supplied with an attached fan heatsink This section documents motherboard and system requirements for the fan heatsink that will be supplied with the boxed Pentium II processor This section is particularly important for OEM s that manufacture motherboards for system integrators Unless otherwise noted all figures in this section are dimensioned in inches Figure 37 shows a mechanical representation of a boxed Pentium II Datasheet _ ntel Pentium II Processor at 350 MHz 400 MHz and 450 MHz processor in the Single Edge Contact Cartridge S E C C package in its retention mechanism with heatsink supports installed Figure 38 shows a mechanical representation of a boxed Pentium II processor in the S E C C 2 package Note The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink The large arrows in Figure 37 denote the direction of airflow Figure 37 Boxed Pentium II Processor in the S E C C Packaging Installed in Retention Mechanism Fan Power Cable Not Shown Heatsink Support Mechanism Pri r ocesso Fan Retention Mechanism Fan Power Connector Motherboard Heatsink Support Mechanism Figure 38 Boxed Pentium II Processor in the S E C C 2 Packaging Fan Power Cable Not Shown HEATSINK FAN POWER CONNECTOR Datasheet 65 a Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel s 6 2 6 2 1 Mechanical Speci
104. rs the dynamic execution Dual Independent Bus architecture plus Intel MMX technology bringing a new level of performance for systems buyers The Pentium II processor is scaleable to two processors in a multiprocessor system and extends the power of today s Pentium II processor with performance headroom for business media communication and internet capabilities Systems based on Pentium II processors also include the latest features to simplify system management and lower the cost of ownership for large and small business environments The Pentium II processor offers great performance for today s and tomorrow s applications Order Number 243657 003 August 1998 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designe
105. rs core logic and I O APIC components on the APIC bus PICD 1 0 IO The PICD 1 0 APIC Data signals are used for bidirectional serial message passing on the APIC bus and must connect the appropriate pins of all processors and core logic or I O APIC components on the APIC bus PRDY The PRDY Probe Ready signal is a processor output used by debug tools to determine processor debug readiness PREQ The PREQ Probe Request signal is used by debug tools to request debug operation of the processors Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 41 Signal Description Sheet 6 of 8 Datasheet Name Type Description PWRGOOD The PWRGOOD Power Good signal is a 2 5 V tolerant processor input The processor requires this signal to be a clean indication that the clocks and power supplies VCCcoge etc are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high 2 5 V state The figure below illustrates the relationship of PWRGOOD to other system signals PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specificat
106. rs must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or imcompatibilities arising from future changes to them The Pentium Il processor may contain design defects or errors known as errata which may cause the product to deviate from published specifcations Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Copyright Intel Corporation 1998 Third party brands and names are the property of their respective owners Datasheet intel Pentium II Processor at 350 MHz 400 MHz and 450 MHz Contents 1 0 2 0 3 0 4 0 5 0 Datasheet yirere Ure fole c 7 1 1 Rule e ore I 8 1 1 1 S E C Cartridge Terminologie 8 1 2 PRETEEN COS egene ess tee eene EEN ede ee EE aa exa ba aaa 9 Electrical Specifications eseseeeee eene nn ennt nne nennen 10 2 1 Processor System Bus and VREF sisirin eene 10 2 2 Clock Control and Low Power Gates 11 2 2 1 Normal State State 1
107. rts 71 Boxed Processor Fan Heatsink Power Cable Connector Description 72 Recommended Motherboard Power Header Placement Relative to Fan Power Connector and Pentium Il Processor cssscsessscscsestsssesesescsescecsestaceeeeesanees 73 Voltage Identification Definition sssini AA 16 Recommended Pull up Resistor Values Approximate for CMOS Signals 18 System Bus Signal Groups tocco rtt einen 19 Absolute Maximum Ratings sesoses EEEE 21 Voltage and Current Specifications ssssseeeeennnnn 22 AGTL Signal Groups DC Specifications sseeeeeeeeee 24 5 Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel 5 13 14 15 16 17 18 19 20 21 22 23 24 25 Non AGTL Signal Group DC Specifications ccc eeeeeeeeeeeeeeeeeeeeeeeneeeeees 24 AGTL Bus Specifications 25 System Bus AC Specifications Clock at the Processor Edge Fingers 26 System Bus AC Specifications Clock at Processor Core Pins 27 Valid System Bus Core Frequency and Cache Bus Frequencies 27 System Bus AC Specifications AGTL Signal Group at the Processor Edge Fingers eoi iere ecc d eed e E eua c c V Da e de LE 28 System Bus AC Specifications AGTL Signal Group at the Processor Core Pins utei eti fete co EID ed Ide ee de Hh ess EC Reto eds 28 System Bus AC Specifications CMOS Signal Group at the Processor Edge Fingers
108. s When transitioning from the Deep Sleep state to the Sleep state PICCLK must be restarted with BCLK Power and Ground Pins The operating voltage of the processor die and of the L2 cache die differ from each other There are two groups of power inputs on the Pentium II processor package to support this voltage difference between the components in the package There are also five pins defined on the package for voltage identification VID These pins specify the voltage required by the processor core These have been added to cleanly support voltage specification variations on current and future Pentium II processors For clean on chip power distribution Pentium II processors have 27 Vcc power and 30 Vss ground inputs The 27 Vcc pins are further divided to provide the different voltage levels to the components Vcco4 inputs for the processor core and some L2 cache components account for 19 of the Vcc pins while 4 Vrr inputs 1 5 V are used to provide an AGTL termination voltage to the processor and 3 Vcc inputs 3 3 V are for use by the L2 cache TagRAM and BSRAMS One Vccs pin is provided for use by the Slot 1 Test Kit Vccs Vccr and Vcc4 must remain electrically separated from each other On the circuit board all Vcc o pins must be connected to a voltage island and all Vcci pins must be connected to a separate voltage island an island is a portion of a power plane that has been divided or an entire plane Similarly all Vss p
109. s asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all Pentium II processor system bus agents and must connect the appropriate pins of all such agents if used However Pentium II processors do not observe assertions of the BERR signal BERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled Asserted optionally for internal errors along with IERR Asserted optionally by the request initiator of a bus transaction after it observes an error e Asserted by any bus agent when it observes an error in a bus transaction 75 Pentium II Processor at 350 MHz 400 MHz and 450 MHz l n 76 Table 41 Signal Description Sheet 3 of 8 Name Type Description BINIT IO The BINIT Bus Initialization signal may be observed and driven by all Pentium II processor system bus agents and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future information If BINIT observation is enabled during power on configuration and BINIT is sampled asserted all bus state machines are reset and any data which was in transit is lost All agents reset their rotating ID for bus arbitration to the state after Reset and internal count information is lost
110. t Setup Time T 110 and T10 RESET Pulse Width T T16 Reset Configuration Signals A 14 5 f BRO FLUSH INIT Setup Time T 2T17 Reset Configuration Signals A 14 5 BRO FLUSH INIT Hold Time T20 Reset Configuration Signals A20M IGNNE LINT 1 0 Hold Time Ty 119 Reset Configuration Signals A20M IGNNE LINT 1 0 Delay Time Tz T18 Reset Configuration Signals A20M IGNNE LINT 1 0 Setup Time PCD 764 Power On Reset and Configuration Timings sc TIT N ZA ZA ZA KZA S azo Dot MMM seen INTR NMI 15 and T15 PWRGOOD Inactive Pulse Width Tat T T10 and T10 RESET Pulse Width T T20 Reset Configuration Signals A20M IGNNE LINT 1 0 Hold Time D0007 02 35 a Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel A Figure 11 Figure 12 3 0 Test Timings TAP Connection TCK TDI TMS Input Signals TDO Output Signals T T43 All Non Test Inputs Setup Time Ts T44 All Non Test Inputs Hold Time T T40 TDO Float Delay Ty T37 TDI TMS Setup Time Tw T38 TDI TMS Hold Time Ty T39 TDO Valid Delay Ty 741 All Non Test Outputs Valid Delay Tz T42 All Non Test Outputs Float Delay PCB766a Test Reset Timings Tg T37 TRST Pulse Wath PCB 773 System Bus Signal Simulations 36 Signals driven on the Pentium II processor syst
111. t or instrumentation purposes Table 29 and Table 30 provide the diode parameter and interface specifications Thermal Diode Parameters Symbol Min Typ Max Unit Notes Trorward bias 5 500 uA 2 n ideality 1 0000 1 0065 1 0173 3 4 NOTES 1 Not 100 tested Specified by design characterization 2 Intel does not support or recommend operation of the thermal diode under reverse bias 3 At room temperature with a forward bias of 630 mV 4 n ideality is the diode ideality factor parameter as represented by the diode equation I Io e Vd q nkT 1 Thermal Diode Interface Pin Name SC 242 Connector Signal Pin Description THERMDP B14 diode anode THERMDN B15 diode cathode S E C C and S E C C 2 Mechanical Specifications 44 Pentium II processors use either S E C C or S E C C 2 package technology Both package types contain the processor core L2 cache and other passive components The cartridges connect to the motherboard through an edge connector Mechanical specifications for the processor are given in this section See Section 1 1 1 for a complete terminology listing Datasheet Note Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz S E C C Mechnical Specifications S E C C package drawings and dimension details are provided in Figure 18 through Figure 27 Figure 18 shows all views of the Pentium II processor in an S E C C package Figure 19
112. the processor edge fingers Table 21 BCLK Signal Quality Specifications for Simulation at the Processor Core I T Parameter Min Nom Max Unit Figure Notes V1 BCLK VIL 0 5 V 13 V2 BCLK VIH 2 0 V 13 2 V3 VIN Absolute Voltage Range 0 7 3 3 V 13 2 V4 Rising Edge Ringback 1 7 V 13 3 V5 Falling Edge Ringback 0 7 V 13 3 NOTES Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 This is the Pentium II processor system bus clock overshoot and undershoot specification for 100 MHz system bus operation 3 The rising and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the BCLK signal can dip back to after passing the Vin rising or Vir falling voltage limits This specification is an absolute value Figure 13 BCLK TCK PICCLK Generic Clock Waveform at the Processor Core Pins T 3 gt v3 v2 v4 o ED e G gt V1 V5 V3 T6 gt T4 75 Time Datasheet 37 Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table22 BCLK Signal Quality Guidelines for Edge Finger Measurement y T Parameter Min Nom Max Unit Figure Notes V1 BCLK VIL 0 5 V 14 V2 BCLK VIH 2 0 V 14 V3 VIN Absolute Voltage Range 0 5 3 3 V 14 2 V4 Rising Edge Ringback 2 0 V 14 3 V5 Falli
113. ther sources of system noise CL E GA H rs Table 24 AGTL Signal Groups Ringback Tolerance Guidelines for Edge Finger Measurement 1 2 3 T Parameter Min Unit Figure Notes a Overshoot 100 mV 15 T Minimum Time at High 0 5 ns 15 4 p Amplitude of Ringback 210 mV 15 4 5 d Final Settling Voltage 210 mV 15 4 Duration of Squarewave Ringback N A ns 15 Datasheet NOTES 1 Unless otherwise noted all guidelines in this table apply to all Pentium II processor frequencies and cache sizes 2 Guidelines are for the edge rate of 0 3 0 8 V ns See Figure 15 for the generic waveform 3 All values specified by design characterization 4 This guideline applies to Pentium II processors operating with a 100 MHz Pentium II processor system bus only 5 Ringback below Vrer 210 mV is not supported 39 a Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel A Figure 15 Low to High AGTL Receiver Ringback Tolerance tT gt Y Qa VREF 0 2 al Um sia al Y H eem E E E oe ee REF p 4 j VREF 0 2 PE 5 gt Vstart Time Note High to Low case is analogous 000914a 3 3 Non AGTL Signal Quality Specifications and Measurement Guidelines There are three signal quality parameters defined for non AGTL signals overshoot undershoot ringback and settling limit All three signal quality parameters are shown
114. this table apply to all Pentium II processor frequencies and cache sizes Signal Ringback Guidelines for Non AGTL Signal Edge Finger Measurement 1 Maximum Ringback Input Signal Group Transition with Input Diodes Present Unit Figure Non AGTL Signals 021 2 0 V 16 Non AGTL Signals 10 0 7 V 16 NOTE 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 41 Pentium II Processor at 350 MHz 400 MHz and 450 MHz l ntel 3 3 3 4 0 Settling Limit Guideline Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition The amount allowed is 10 of the total signal swing Vum Vo above and below its final value A signal should be within the settling limits of its final value when either in its high state or low state before it transitions again Signals that are not within their settling limit before transitioning are at risk of unwanted oscillations which could jeopardize signal integrity Simulations to verify settling limit may be done either with or without the input protection diodes present Violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions Thermal Specifications and Design Considerations Initial Pentium II processors tak
115. tic Land Grid Array This package technology incorporates a heat slug within the package that contacts the extended thermal plate OLGA Organic Land Grid Array This package technology permits attaching the heatsink directly to the die Additional terms referred to in this and other related documentation SC 242 The 242 contact slot connector previously referred to as Slot 1 connector that the S E C C and S E C C 2 plug into just as the Pentium Pro processor uses Socket 8 Retention mechanism An enabled mechanical piece which holds the S E C cartridge in the SC 242 connector Heatsink support The support pieces that are mounted on the motherboard to provide added support for heatsinks The L2 cache TagRAM BSRAM die keep industry names References The reader of this specification should also be familiar with material and concepts presented in the following documents AP 485 Intel Processor Identification and the CPUID Instruction Order Number 241618 AP 827 100 MHz GTL Layout Guidelines for the Pentium II Processor and Intel 440BX AGPset Order Number 243735 AP 586 Pentium II Processor Thermal Design Guidelines Order Number 243331 AP 587 Pentium II Processor Power Distribution Guidelines Order Number 243332 AP 588 Mechanical and Assembly Technology for S E C Cartridge Processors Order Number 243333 AP 589 Pentium II Processor Electro Magnetic Interference Order Number 243334 Pentium II P
116. tions apply to all S E C C packaged Pentium II processor frequencies and cache sizes Table 34 S E C C 2 Materials S E C C 2 Piece Piece Material Maximum Piece Weight Grams Cover GE Lexan 940 V0 18 0 Total Pentium II Processor 57 0 NOTE 1 Unless otherwise noted these specifications apply to all S E C C 2 packaged Pentium II processor frequencies and cache sizes Datasheet 57 Pentium II Processor at 350 MHz 400 MHz and 450 MHz 5 4 58 Pentium II Processor Signal Listing Intel Table 35 and Table 36 provide the processor edge finger and Pentium II processor connector signal definitions for Pentium II processors The signal locations on the SC 242 edge connector are to be used for signal routing simulation and component placement on the motherboard Table 35 is the Pentium II processor substrate edge finger listing in order by pin number Table 35 Signal Listing in Order by Pin Number Sheet 1 of 4 Pin No Pin Name Signal Buffer Type Pin No Pin Name Signal Buffer Type Al VCC_VTT AGTL VTT Supply Bl EMI EMI Management A2 GND Vss B2 FLUSH CMOS Input A3 VCC_VTT AGTL VTT Supply B3 SMI CMOS Input A4 IERR CMOS Output B4 INIT CMOS Input AS A20M CMOS Input B5 VCC VTT AGTL VTT Supply A6 GND Vss B6 STPCLK CMOS Input AT FERR CMOS Output B7 TCK JTAG Input
117. tium II processor TDO provides the serial output needed for JTAG specification support TESTHI The TESTHI signal must be connected to a 2 5 V power source through a 1 100 KQ resistor for proper processor operation THERMDN Thermal Diode Cathode Used to calculate core temperature See Section 4 1 THERMDP Thermal Diode Anode Used to calculate core temperature See Section 4 1 Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 41 Signal Description Sheet 8 of 8 Name Type Description THERMTRIP The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approximately 135 C This is signaled to the system by the THERMTRIP Thermal Trip pin Once activated the signal remains latched and the processor stopped until RESET goes active There is no hysteresis built into the thermal sensor itself as long as the die temperature drops below the trip level a RESET pulse will reset the processor and execution will continue If the temperature has not dropped below the trip level the processor will continue to drive THERMTRIP and remain stopped TMS The TMS Test Mode Select signal is a JTAG specification support signal used by debug tools
118. transient tolerance level 0 110 0 110 V 4 9 Transient at SC 242 pins VCCcorE Processor core voltage Tolerance static tolerance level at 0 085 0 085 V 4 10 Static edge fingers VCCcogg Processor core voltage Tolerance transient tolerance level 0 140 0 140 V 4 10 Transient at edge fingers 350 MHz 10 8 A 2 4 12 13 ICCcong Icc for processor core 400 MHz 12 0 A 2 4 12 13 450 MHz 13 6 A 2 4 12 13 g 350 MHz 0 7 A 4 7 12 Ica eim second level 400 MHz 0 9 A 147 12 450 MHz 1 0 A 4 7 12 IVTT Termination voltage 23 A 14 supply current 350 MHz 0 8 A 4 11 12 15 ISGnt en iR to 400 MHz 0 9 A 4 11 12 15 process 450 MHz 1 0 A 4 11 12 15 ICC Stop Grant for e second level cache Ge i 58 350 MHz 0 8 A 4 11 12 ISLP ll for processor 400 MHz 0 9 A 4 1112 450 MHz 1 0 A 4 11 12 Icc Sleep for second ISLg jevel cache 0 1 A 4 7 12 IDSLP Icc Deep Sleep for 0 35 A 12 processor core Icc Deep Sleep for 0 1 A Ve second level cache Power supply current dICCcopgp dt dew ate 20 Alus 3 16 17 18 dicc dt L2 cache powert supply 1 Alus 16 17 18 current slew rate Termination current slew See dICCyrr dt tate 8 A us Table g 17 18 vocs 5 V supply voltage 4 75 5 00 5 25 V 5 Vv 45 Iccs Icc for 5 V supply 10 A 19 voltage Datasheet Datasheet Pentium II Processor at 350 MHz 400 MHz and 450 MHz NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes 2 Ve
119. ure 40 85 C Any processor supply voltage VCC AID with respect to VSS 0 5 Operating voltage 1 0 V 1 2 AGTL buffer DC input VAGT voltage with respect to Vss eps VOCconn 0 7 y CMOS buffer DC input Keen voltage with respect to Vss ens 3 3 y IviD Max VID pin current 3 mA ISLOTOCC Max SLOTOCC pin current 5 mA Mech Max Mechanical integrity of latch Latch Arms arms 3n SSC B Mech Max Edge Mechanical integrity of Insertions e 2 50 5 6 Fingers processor edge fingers Extractions NOTES 1 Operating voltage is the voltage to which the component is designed to operate See Table 5 2 This rating applies to the Veccorr Veci2 Vcc5 and any input except as noted below to the processor 3 Parameter applies to CMOS APIC and TAP bus signal groups only 4 The mechanical integrity of the latch arms is specified to last a maximum of 50 cycles 5 The electrical and mechanical integrity of the processor edge fingers are specified to last for 50 insertion extraction cycles 6 While insertion extraction cycling above 50 insertions will cause an increase in the contact resistance above 0 1Q and a degradation in the material integrity of the edge finger gold plating it is possible to have processor functionality above the specified limit The actual number of insertions before processor failure will vary based upon system configuration and environmental conditions Processor DC Specifications The processor DC specifications in t
120. w BCLK AGTL I O ADS ADS 1 ADS Low BCLK AGTL I O Always AP 1 0 Low BCLK AGTL I O ADS ADS 1 BRO Low BCLK AGTL I O Always BP 3 2 Low BCLK AGTL I O Always BPM 1 0 Low BCLK AGTL I O Always D 63 0 Low BCLK AGTL I O DRDY DBSY Low BCLK AGTL I O Always DEP 7 0 Low BCLK AGTL I O DRDY DRDY Low BCLK AGTL I O Always LOCK Low BCLK AGTL I O Always REQ 4 0 Low BCLK AGTL I O ADS ADS 1 RP Low BCLK AGTL I O ADS ADS 1 Table 45 Input Output Signals Multiple Driver Name Active Level Clock Signal Group Qualified AERR Low BCLK AGTL I O ADS 3 BERR Low BCLK AGTL I O Always BNR Low BCLK AGTL I O Always BINIT Low BCLK AGTL I O Always HIT Low BCLK AGTL I O Always HITM Low BCLK AGTL VO Always PICD 1 0 High PICCLK APIC I O Always Datasheet 83
121. y between the SC 242 connector and processor core The positive offset ensures both the processor core and the core logic receive the BCLK edge concurrently 8 See Section 3 1 for Pentium II processor system bus clock signal quality specifications 9 Not 100 tested Specified by design characterization as a clock driver requirement 26 Datasheet Table 11 Pentium II Processor at 350 MHz 400 MHz and 450 MHz Table 10 System Bus AC Specifications Clock at Processor Core Pins 1 2 3 T Parameter Min Nom Max Unit Figure Notes All processor core System Bus Frequency 100 00 MHz frequencies T1 BCLK Period 10 0 ns 6 4 5 6 10 T2 BCLK Period Stability 250 ps 6 6 7 8 10 T3 BCLK High Time 2 6 ns 6 gt 2 0 V T4 BCLK Low Time 2 47 ns 6 Q 0 5 V T5 BCLK Rise Time 0 38 1 25 ns 6 0 5 V 2 0 V T6 BCLK Fall Time 0 38 1 5 ns 6 2 0 V 0 5 vin NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium II processor frequencies and cache sizes 2 All AC timings for the AGTL signals are referenced to the BCLK rising edge at 1 25 V at the processor core pin All AGTL signal timings address bus data bus etc are referenced at 1 00 V at the processor core pins 3 All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1 25 V at the processor co
122. y the L2 cache also impacts the overall processor power specification Systems should design for the highest possible thermal power even if a processor with a lower thermal dissipation is planned Table 27 Thermal Specifications for S E C C Packaged Processors 1 Extended Processor Core L2 Cache Processor Thermal Plate Min Max Min Max Frequency Size Power Power TPLATE TPLATE TCOVER TCOVER MHz Kbytes W W C C C C 450 4 512 27 1 26 4 5 70 5 75 400 512 24 3 23 6 5 75 5 75 3504 512 21 5 20 8 5 75 3 75 NOTES 1 These values are specified at nominal Vcccore for the processor core and nominal Vcc for the L2 cache 2 Processor power includes the power dissipated by the processor core the L2 cache and the AGTL bus termination The maximum power for each of these components does not occur simultaneously 3 Extended Thermal Plate power is the processor power that is dissipated through the extended thermal plate 4 These processors use the extended thermal plate for the Pentium II processor see Figure 17 Table 28 Thermal Specifications for S E C C 2 Packaged Processors Processor Min Max Min Max Core L2 Cache Processor PLGA PLGA OLGA OLGA L2Cache L2 Cache Min Max Frequency Size Power TcasE TcasE Tyunc Tyunc Min Tcase Max Tcase Tcover Tcover MHz Kbytes W C CC CC CC CC CO CC CO 450 512 27 1 N
123. y to all Pentium II processor frequencies and cache sizes All AC timings for the TAP signals are referenced to the TCK rising edge at 0 7 V at the processor edge fingers All TAP signal timings TMS TDI etc are referenced at 1 25 V at the processor edge fingers Not 100 tested Specified by design characterization 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 667 MHz Referenced to TCK rising edge Referenced to TCK falling edge Valid delay timing for this signal is specified to 2 5 V 4 596 See Table 2 for pull up resistor values Non Test Outputs and Inputs are the normal output or input signals besides TCK TRST TDI TDO and TMS These timings correspond to the response of these signals due to TAP operations During Debug Port operation use the normal specified timings rather than the TAP signal timings Table 20 System Bus AC Specifications TAP Connection at the Processor Core Pins 1 2 3 T Parameter Min Max Unit Figure Notes T30 TCK Frequency 16 667 MHz T31 TCK Period 60 0 ns 6 T32 TCK High Time 25 0 ns 6 17y T33 TCK Low Time 25 0 ns 6 0 7 V 1 T34 TCK Rise Time 5 0 ns 6 0 7 V 1 7 v 10 T35 TCK Fall Time 5 0 ns 6 1 7 V 0 7 V 10 T36 TRST Pulse Width 40 0 ns 12 Asynchronous T37 TDI TMS Setup Time 5 0 ns 11 5 T38 TDI TMS Hold Time 14 0 ns 11 5 T39 TDO Valid Delay 1 0 1

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