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Intel Core 2 Duo E7300

1. Table 25 Numerical Land Table 25 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction Land Land Name Signal Buffer Direction Type Type U27 vcc Power Other Y3 PSI Asynch CMOS Output U28 VCC Power Other Y4 A20 Source Synch Input Output U29 VCC Power Other Y5 VSS Power Other u30 VCC Power Other Y6 A193 Source Synch Input Output V1 MSID1 Power Other Output Y7 VSS Power Other V2 RESERVED Y8 VCC Power Other V3 VSS Power Other Y23 VCC Power Other V4 A155 Source Synch Input Output Y24 VCC Power Other V5 A14 Source Synch Input Output Y25 VCC Power Other V6 VSS Power Other Y26 VCC Power Other V7 VSS Power Other Y27 VCC Power Other V8 VCC Power Other Y28 VCC Power Other V23 VSS Power Other Y29 VCC Power Other V24 VSS Power Other Y30 VCC Power Other V25 VSS Power Other AA1 dr Power Other Output V26 VSS Power Other AA2 FC39 Power Other V27 VSS Power Other AA3 VSS Power Other V28 VSS Power Other AA4 A21 Source Synch Input Output V29 VSS Power Other AA5 A23 Source Synch Input Output v30 VSS Power Other AA6 VSS Power Other Wi MSIDO Power Other Output TESTHI12 AA7 VSS Power Other We FC44 Power Other Input AA8 VCC Power Other w3 TESTHI1 Power Other Input AA23 VSS Power Other W4 VSS Power Other AA24 VSS Power Other w5 A16 Source Synch Input Output AA25 VSS Power Other W6 A18 Source Synch Input Output AA26 VSS Power
2. p SN BOTTOM VIEW 1 5 MAX ALLOWABLE COMPONENT HEIGHT SIDE VIEW TOP VIEW L3 l e co EN eo co e DO NOT SCALE DRAWING breer 3 oF 3 SANTA CLARA CA 95052 8119 eae 2200 MISSION COLLEGE BLVD P O BOX 58119 conr intel DEPARTMENT ATD Datasheet Package Mechanical Specifications 3 2 3 3 Table 21 3 4 Table 22 Datasheet intel Processor Component Keep Out Zones The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out zones Decoupling capacitors are typically mounted to either the topside or land side of the package substrate See Figure 7 and Figure 8 for keep out zones The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep in Package Loading Specifications Table 21 provides dynamic and static load specifications for the processor package These mechanical maximum load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearin
3. je et Core Frequency Core Frequency T Frequency to FSB 266 MHz r7 iod MHz Seen BCLK Notes Frequency Z FSB 1 6 1 60 GHz 2 GHZ 1 7 1 86 GHz 2 33 GHz 1 7 5 2 GHz 2 50 GHz E 1 8 2 13 GHz 2 66 GHz 1 8 5 2 26 GHz 2 83 GHz 2 1 9 2 40 GHz 3 GHz 1 9 5 2 53 GHz 3 16 GHz 1 10 2 66 GHz 3 33 GHz 1 10 5 2 80 GHz 3 50 GHz 1 11 2 93 GHz 3 66 GHz 1 11 5 3 06 GHz 3 83 GHz 2 1 12 3 20 GHz 4 GHz 1 12 5 3 33 GHz 4 16 GHz 1 13 3 46 GHz 4 33 GHz 1 13 5 3 60GHz 4 50 GHz 1 14 3 73 GHz 4 66 GHz 1 15 4 GHz 5 GHz NOTES 1 Individual processors operate only at or below the rated frequency 2 Listed frequencies are not necessarily committed production frequencies 31 m e n tel Electrical Specifications Table 17 2 8 3 2 8 4 Table 18 32 FSB Frequency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 Table 17 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency The Intel Core 2 Duo processor E7000 series operates at a 1333 MHz FSB and 1066 MHz FSB frequency selected by a 333 MHz BCLK 1 0 or 266 MHz BCLK 1 0 frequency The Intel Core 2 Duo processor E8000 series operates at a 1333 MHz FSB frequency selected by a 333
4. http www intel com products processor manuals 12 8 Datasheet m Electrical Specifications n tel 2 2 1 2 2 2 2 1 2 2 2 Datasheet Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals DC electrical characteristics are provided Power and Ground Lands The processor has VCC power VTT and VSS ground inputs for on chip power distribution All power lands must be connected to Vcc while all VSS lands must be connected to a system ground plane The processor VCC lands must be supplied the voltage determined by the Voltage IDentification VID lands The signals denoted as VTT provide termination for the front side bus and power to the I O buffers A separate supply must be implemented for these lands that meets the V specifications outlined in Table 4 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate Larger bulk storage Cg such as electrolytic or aluminum polymer capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running conditio
5. 26 Datasheet e Electrical Specifications n t el 2 7 3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless otherwise stated All specifications apply to all frequencies and cache sizes unless otherwise stated Table 11 GTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes VIL Input Low Voltage 0 10 GTLREF 0 10 V 2 5 Vin Input High Voltage GTLREF 0 10 Vr 0 10 V 3 4 5 VoH Output High Voltage Vr 0 10 Vir V 4 5 V I Output Low Current N A TT MAX A n n R r_min 2 Ron_min Input Leakage Ij Current N A 100 HA 6 Output Leakage n ILo Current N A 100 HA 7 Ron Buffer On Resistance 7 49 9 16 Q NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vi is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3 Vip is defined as the voltage range at a receiving agent that will be interpreted as a logical high value Vin and Voy may experience excursions above VT The V referred to in these specifications is the instantaneous Vr r Leakage to Vss with land held at V Leakage to V with land held at 300 mV Our Table 12 Open Drain and TAP Output Signal Group DC Specifications Symbol Parameter Min Max Unit Notes VoL Output Low Volt
6. Land Listing and Signal Descriptions Datasheet intel Table 25 Numerical Land Table 25 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction Land Land Name Signal Buffer Direction Type Type H29 FC15 Power Other K8 vcc Power Other H30 BSEL1 Asynch CMOS Output K23 VCC Power Other JA VIS Power Other Output K24 VCC Power Other K25 VCC Power Other J2 FC3 Power Other K26 VCC Power Other J3 FC22 Power Other K27 VCC Power Other J4 VSS Power Other K28 VCC Power Other J5 REQ1 Source Synch Input Output K29 VCC Power Other J6 REQ4 Source Synch Input Output K30 VCC Power Other J7 VSS Power Other Li LINT1 Asynch CMOS Input J8 VCC Power Other L2 SLP Asynch CMOS Input J9 Vcc Power Other L3 VSS Power Other J10 Vcc Power Other L4 A06 Source Synch _ Input Output J11 VCC Power Other L5 A033 Source Synch _ Input Output J12 VCC Power Other L6 VSS Power Other J13 Vcc Power Other L7 VSS Power Other J14 VCC Power Other L8 VCC Power Other J15 Vcc Power Other L23 vss Power Other J16 FC31 Power Other L24 VSS Power Other J17 FC34 Power Other L25 VSS Power Other J18 VCC Power Other L26 VSS Power Other J19 Vcc Power Other L27 VSS Power Other J20 Vcc Power Other L28 VSS Power Other J21 VCC Power Other L29 VSS Power Other J22 VEC Power Other L30
7. Di9 VSS RSVD RSVD FC20 HITM amp TRDY VSS Rsvp D25 vss D45 D22 vss Di2 D20 VSS VSS HIT VSS ADS RSVD ps2 vss Di4 Dii vss FC41 DSTBNOR vss D3 Dit vss LOCK BNR DRDY vss comps D13 vss D10 amp DsTBPOR VSS D6 D5 VSS D0 RSO DBSY VSS D50 amp COMPO VSS Dos D8 VSS DBIOR D7 VSS D4 D2 RS2 VSS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Datasheet 45 AN AM AL AK AJ AH AG AF AE AD AC AB AA a r 372 v o Ug m m 46 intel Land Listing and Signal Descriptions Table 24 Alphabetical Land Table 24 Alphabetical Land Assignments Assignments Land Name PM Direction Land Name Dd TET Direction A3 L5 Source Synch Input Output BNR C2 Common Clock Input Output A4 P6 Source Synch Input Output BPMO AJ2 Common Clock Input Output A53 M5 Source Synch Input Output BPM1 AJi Common Clock Input Output A63 L4 Source Synch Input Output BPM2 AD2 Common Clock Input Output A73 M4 Source Synch Input Output BPM3 AG2 Common Clock Input Output A8 R4 Source Synch Input Output BPM4 AF2 Common Clock Input Output A93 T5 Source Synch Input Output BPM5 AG3 Common Clock Input Output A10 U6 Source Synch Input Output BPRI G8 Common Clock Input A114 T4 Source Synch Input Output BRO F3 Common Clock
8. Input Output A123 U5 Source Synch Input Output BSELO G29 Asynch CMOS Output A13 U4 Source Synch Input Output BSEL1 H30 Asynch CMOS Output A14 V5 Source Synch Input Output BSEL2 G30 Asynch CMOS Output A15 V4 Source Synch Input Output COMP0 A13 Power Other Input A16 W5 Source Synch Input Output COMP1 T1 Power Other Input A17 AB6 Source Synch Input Output COMP2 G2 Power Other Input A18 W6 Source Synch Input Output COMP3 R1 Power Other Input A195 Y6 Source Synch Input Output COMP8 B13 Power Other Input A203 Y4 Source Synch Input Output DO B4 Source Synch Input Output A21 AA4 Source Synch Input Output D1 C5 Source Synch Input Output A22 AD6 Source Synch Input Output D2 A4 Source Synch Input Output A23 AA5 Source Synch Input Output D3 C6 Source Synch Input Output A24 AB5 Source Synch Input Output D4 A5 Source Synch Input Output A25 AC5 Source Synch Input Output D5 B6 Source Synch Input Output A26 AB4 Source Synch Input Output D6 B7 Source Synch Input Output A27 AF5 Source Synch Input Output D7 A7 Source Synch Input Output A28 AF4 Source Synch Input Output D8 A10 Source Synch Input Output A29 AG6 Source Synch Input Output D9 A11 Source Synch Input Output A30 AG4 Source Synch Input Output D10 B10 Source Synch Input Output A31 AG5 Source Synch Input Output D11 C11 Source Synch Input Output A32 AH4
9. Input Output F2 FC5 Power Other D21 VSS Power Other F3 BRO Common Clock Input Output D22 D46 Source Synch _ Input Output F4 VSS Power Other D23 VCCPLL Power Other F5 RS1 Common Clock Input D24 VSS Power Other F6 FC21 Power Other D25 VTT Power Other F7 VSS Power Other D26 VIT Power Other F8 D17 Source Synch _ Input Output D27 VIT Power Other F9 D18 Source Synch _ Input Output D28 VTT Power Other F10 VSS Power Other 57 58 intel Land Listing and Signal Descriptions Table 25 Numerical Land Table 25 Numerical Land Assignment Assignment Land Land Name i das Direction Land Land Name ok dod Direction F11 D23 Source Synch _ Input Output G20 DSTBN2 Source Synch _ Input Output F12 D24 Source Synch _ Input Output G21 D44 Source Synch _ Input Output F13 VSS Power Other G22 D47 Source Synch _ Input Output F14 D28 Source Synch _ Input Output G23 RESET Common Clock Input Fi5 D30 Source Synch _ Input Output G24 TESTHI6 Power Other Input F16 VSS Power Other G25 TESTHI3 Power Other Input F17 D37 Source Synch _ Input Output G26 TESTHI5 Power Other Input F18 D38 Source Synch _ Input Output G27 TESTHI4 Power Other Input F19 VSS Power Other G28 BCLK1 Clock Input F20 D41 Source Synch _ Input Output G29 BSELO Asy
10. R 1 RI 4 BASIC id 0 2 BASIC 6 215 BASIC 0 2 BASIC 6 215 BASIC Y r HEET 2 oF 3 DO NOT SCALE DRAWING 2200 MISSION COLLEGE BLVD P O BOX 58119 o core intel SANTA CLARA CA 95052 8119 prac e DEPARTMENT ATD Datasheet 37 intel Figure 9 38 Processor Package Drawing Sheet 3 of 3 Package Mechanical Specifications e ul l a 3E c88285 0 Y w T 25 OOOOOOOOOQOOOOOO OOOOOOOOOQOOOOOO OOO0O000000Q0000000 OOOOOOOOOQOCOOOOO OOOOOOOOOQOOOOOO OOOOOOOOOQOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOQOOOOO OOOOOOQOOOOO OOOO OOOO OOOOOOOOOO OOOOOOOOOO OOOOOOOOOO OOOOOOOOOO OOOOOOOOOO OOOOOOOOOO OOOOOOOOOO OOOOOOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO 00000 I OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO LoooooooQO o OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOQOOOOOO0OO 13 T 185 OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO 0 115 OOOOOOOOO 000000000 OOOOOOOOO O00000000 5555555 OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOO 000 j
11. Signal Description Sheet 6 of 10 Name Type Description ITP CLK 1 0 Input ITP_CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board ITP CLK 1 0 are used as BCLK 1 0 references for a debug port implemented on an interposer If a debug port is implemented in the system ITP_CLK 1 0 are no connects in the system These are not processor signals LINT 1 0 Input LINT 1 0 Local APIC Interrupt must connect the appropriate pins lands of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured using BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these signals as LINT 1 0 is the default configuration LOCK Input Output LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins lands of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbi
12. Source Synch Input Output D12 D8 Source Synch Input Output A33 AH5 Source Synch Input Output D13 B12 Source Synch Input Output A34 AJ5 Source Synch Ipput Output D14 C12 Source Synch Input Output A35 AJ6 Source Synch Ipput Output D15 D11 Source Synch Input Output A20M K3 Asynch CMOS Input D16 G9 Source Synch Input Output ADS D2 Common Clock Input Output D17 F8 Source Synch Input Output ADSTB0 R6 Source Synch Input Output D18 F9 Source Synch Input Output ADSTB1 AD5 Source Synch Input Output D19 E9 Source Synch Input Output BCLKO F28 Clock Input D20 D7 Source Synch Input Output BCLK1 G28 Clock Input D21 E10 Source Synch Input Output Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Alphabetical Land Table 24 Alphabetical Land Assignments Assignments Land Name Fand cic Direction Land Name Cand Signa Butrer Direction Type Type D22 D10 Source Synch Input Output D61 A19 Source Synch Input Output D23 Fil Source Synch Input Output D62 A22 Source Synch Input Output D24 F12 Source Synch Input Output D63 B22 Source Synch Input Output D25 D13 Source Synch Input Output DBIO A8 Source Synch Input Output D26 E13 Source Synch Input Output D
13. n a a B o ala la la fa jo Jo Jo Jo Jo Jo o Jo Jo Jo lo Jo Jo o o Jo o o o Jo o Jo Jo Jo o Jo a a o Ln Ln Ln ln Ln Ln Ln Ln Ln ln in Ln Ln Ln Ln ln Ln ln Ln Ln Ln Ln Dt he IA m 10 IN EQ QN tan IS IN a IN Q ls INS S IN Q S dog RS IR IA ft IN S a IS IR ON jn IN Q Jv fa IN IR IN fio S J Joo fo fun m le xo s fon S m S Joo IS o m fon 9 I Joo JR fo s o IQ le S xo e m JN J 7 c 5 Jo Jo Om mnm fe n fr Se PSE a m m as mi mia IN IN IN mm yum iS mg 3 ELEME HH Hu alt a Hu Hu Hu ELLE HH ELE Hu a Bo o jo lo o o Jo o o Jo o o Jo o o o Jo Jo o o Jo o o o o lo o lo o o o lo o o o Jo o o o o o o o o o o o a Jin O JA JO n JO a JO m JO JO m O f JO ju O f JO a JO ju JO a JO jiu O a JO ju O f JO a O f O a O JO a JO ju O a a EN o lo la lo Jo la Jo lo la la lo Jo la la Jo Jo la la lo Jo la Jo Jo la lo lo la Jo Jo la Jo Jo la la lo Jo la la lo Jo a m lo je jo je red a et f le le je je e nes et l le le le fe f f ret eet e le le et fa fa l lele le le fH fa et eh le leje eed ue a mu o jo Jo Jo lo Jo Jo Jo la la Jo Jo lo Jo Jo Jo Jo Jo la Ja lo Jo lo Jo Jo Jo Jo Jo Ja Ja fa fa a Eu O o jo jo JO JO JO JO JO JO JO JO JO JO jo JO a a a a a a f m f m a a a O JO JO JO JO JO jo JO JO jo JO jo jo JO a B o o o o o o Jo o jo Jo o Jo Jo o o o o o o
14. 35 17 4 ADSTB1 Synchronous 1 O assoc strobe D 15 0 DBI0 DSTBP0 DSTBN0 D 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 Synchronous to GTL Strobes ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 BCLK 1 0 A20M DPRSTP DPSLP IGNNE INIT LINTO CMOS INTR LINT1 NMI SMI 3 STPCLK PWRGOOD SLP TCK TDI TMS TRST BSEL 2 0 VID 7 0 PSI Open Drain Output FERR PBE IERR THERMTRIP TDO Open Drain Input PROCHOT 4 Output FSB Clock Clock BCLK 1 0 ITP_CLK 1 0 2 VCC VTT VCCA VCCIOPLL VCCPLL VSS VSSA GTLREF 1 0 COMP 8 3 0 RESERVED Power Other TESTHI 12 10 0 VCC_SENSE VCC_MB_REGULATION VSS_SENSE VSS MB REGULATION DBR 2 VTT OUT LEFT VTT OUT RIGHT VTT SEL FCx PECI MSID 1 0 NOTES 1 Refer to Section 4 2 for signal descriptions 2 In processor systems where no debug port is implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects 25 n te Electrical Specifications 3 The value of these signals during the active to inactive edge of RESET defines the processor configuration options See Section 6 1 for details 4 PROCHOT signal type is open drain output and CMOS input Table 9 Signal Characteristics Signals with RTT Signals with No Rrr A20M
15. 8T MATERIAL 7 0 08 Jl 0 203 C H l e O0000000000000000000000000000000 OOOOOO0O00000000000000000000000000 OOOOOOOOOOOOOOOO OOOOOOOOOO0O00000 00000000000000000000000000000000 OOOOOOOOOOOOOOOOQOOOOOOOOOOOOOQO tt QOOOOOOOO0O0000000000000000000000099 T IHS SEALANT ANGLES 0 5 THIRD ANGLE PROJECTION PACKAGE SUBSTRATE DIMENSIONS 46 UNLESS OTHERWISE SPECIFIED INTERPRET DIMENSIONS AND TOLERANCES M MANUSHAROW IN ACCORDANCE WITH ASHE Y14 5N 1994 T9 o000000000 GG900009 GOS 99 I Ls E E He Cle COMMENTS eT S zo3 c o E SECTION E E 34 3 2 3 2 3 0 82 WAX 31 55 37 55 4 242 2 593 MILLIMETERS 33 93 BASIC 34 88 BASIC 16 965 BASIC 11 44 BASIC 1 11 BASIC 1 08 BASIC MIN 31 45 31 45 33 9 33 9 3 806 0 74 SYMBOL 8 i B c i c 9 F Fa 82 e c 1 M B 1 1 1 I 1 1 TOP VIEN FRONT VIEW E xmi B SCALE 50 1 o o O s O IHS LID TN ee 36 Datasheet Package Mechanical Specifications Figure 8 Processor Package Dr
16. Alphabetical Land Table 24 Alphabetical Land Assignments Assignments Land Name E Direction Land Name p a Direction VSS AF30 Power Other VSS AK2 Power Other VSS AF6 Power Other VSS AK20 Power Other VSS AF7 Power Other VSS AK23 Power Other VSS AG10 Power Other VSS AK24 Power Other VSS AG13 Power Other VSS AK27 Power Other VSS AG16 Power Other VSS AK28 Power Other VSS AG17 Power Other VSS AK29 Power Other VSS AG20 Power Other VSS AK30 Power Other VSS AG23 Power Other VSS AK5 Power Other VSS AG24 Power Other VSS AK7 Power Other VSS AG7 Power Other VSS AL10 Power Other VSS AH1 Power Other VSS AL13 Power Other VSS AH10 Power Other VSS AL16 Power Other VSS AH13 Power Other VSS AL17 Power Other VSS AH16 Power Other VSS AL20 Power Other VSS AH17 Power Other VSS AL23 Power Other VSS AH20 Power Other VSS AL24 Power Other VSS AH23 Power Other VSS AL27 Power Other VSS AH24 Power Other VSS AL28 Power Other VSS AH3 Power Other VSS AL7 Power Other VSS AH6 Power Other VSS AM1 Power Other VSS AH7 Power Other VSS AM10 Power Other VSS AJ10 Power Other VSS AM13 Power Other VSS AJ13 Power Other VSS AM16 Power Other VSS AJ16 Power Other VSS AM17 Power Other VSS AJ17 Power Other VSS AM20 Power Other VSS AJ20 Power Other VSS AM23 Power Other VSS AJ23 Power Other VSS AM24 Power Other VSS AJ24 Power Other VSS AM27 Power Other VSS AJ27 Power Other VSS AM28 Power Other V
17. BCLK 1 0 BPM 5 0 BSEL 2 0 A 35 3 ADS ADSTB 1 0 BNR BPRI COMP 8 3 0 FERR PBE IERR IGNNE D 63 0 DBI 3 0 DBSY DEFER INIT ITP_CLK 1 0 LINTO INTR LINT1 DRDY DSTBN 3 0 DSTBP 3 0 HIT NMI MSID 1 0 PWRGOOD RESET SMI HITM LOCK PROCHOT REQ 4 0 STPCLK TDO TESTHI 12 10 0 RS 2 0 TRDY THERMTRIP VID 7 0 GTLREF 1 0 TCK TDI TMS TRST VTT_SEL Open Drain Signals THERMTRIP FERR PBE IERR BPM 5 0 BRO TDO FCx NOTES 1 Signals that do not have Rrr nor are actively driven to their high voltage level Table 10 Signal Reference Voltages GTLREF Vr1 2 BPM 5 0 RESET BNR HIT HITM BRO A 35 0 ADS ADSTB 1 0 BPRI D 63 0 DBI 3 0 DBSY DEFER DRDY DSTBN 3 0 DSTBP 3 0 LOCK REQ 4 0 RS 2 0 TRDY A20M LINTO INTR LINT1 NMI IGNNE INIT PROCHOT PWRGOOD SMI STPCLK TCK TDI TMS TRST NOTE 1 See Table 12 for more information 2 7 2 CMOS and Open Drain Signals Legacy input signals such as A20M IGNNE INIT SMI and STPCLK use CMOS input buffers All of the CMOS and Open Drain signals are required to be asserted de asserted for at least eight BCLKs in order for the processor to recognize the proper signal state See Section 2 7 3 for the DC specifications See Section 6 2 for additional timing requirements for entering and leaving the low power states
18. D30 VTT Power Other C22 VSS Power Other E2 VSS Power Other C23 VCCIOPLL Power Other E3 TRDY Common Clock Input C24 VSS Power Other E4 HITM Common Clock Input Output C25 VTT Power Other E5 FC20 Power Other C26 VTT Power Other E6 RESERVED C27 VTT Power Other E7 RESERVED C28 VTT Power Other E8 VSS Power Other C29 VIT Power Other E9 D19 Source Synch _ Input Output C30 VIT Power Other E10 D21 Source Synch _ Input Output D1 RESERVED E11 vss Power Other D2 ADS Common Clock Input Output E12 DSTBP1 Source Synch Input Output D3 VSS Power Other E13 D26 Source Synch _ Input Output D4 HIT Common Clock Input Output E14 VSS Power Other D5 VSS Power Other E15 D33 Source Synch _ Input Output D6 VSS Power Other E16 D34 Source Synch _ Input Output D7 D20 Source Synch _ Input Output E17 VSS Power Other D8 D12 Source Synch Input Output E18 D39 Source Synch _ Input Output D9 VSS Power Other E19 D40 Source Synch _ Input Output D10 D22 Source Synch _ Input Output E20 VSS Power Other Dili D15 Source Synch Input Output E21 D42 Source Synch Input Output D12 VSS Power Other E22 D45 Source Synch _ Input Output D13 D25 Source Synch _ Input Output E23 RESERVED D14 RESERVED E24 FC10 Power Other D15 VSS Power Other E25 VSS Power Other D16 RESERVED E26 VSS Power Other D17 D49 Source Synch Input Output E27 VSS Power Other D18 VSS Power Other E28 VSS Power Other D19 DBI2 Source Synch Input Output E29 FC26 Power Other D20 D48 Source Synch _
19. E8600 E8500 E8400 E8300 E8200 and E7600 only Supports Intel Trusted Execution Technology Intel TXT Intel Core 2 Duo processors E8600 E8500 E8400 E8300 and E8200 only Supports Execute Disable Bit capability Advance Dynamic Execution Very deep out of order execution Enhanced branch prediction Optimized for 32 bit applications running on advanced 32 bit operating systems Intel Advanced Smart Cache 6 MB Level 2 cache Intel Core 2 Duo processor E8000 series only 3 MB Level 2 cache Intel Core 2 Duo processor E7000 series only Intel Advanced Digital Media Boost Enhanced floating point and multimedia unit for enhanced video audio encryption and 3D performance Power Management capabilities System Management mode e Multiple low power states e 8 way cache associativity provides improved cache hit rate on load store operations e 775 land Package e FSB frequency at 1333 MHz e FSB frequency at 1066 MHz Intel Core 2 Duo processor E7000 series only e Binary compatible with applications running on previous members of the Intel microprocessor line The Intel Core 2 Duo processor E8000 and E7000 series are based on the Enhanced Intel Core microarchitecture The Enhanced Intel Core microarchitecture combines the performance across applications and usages where end users can truly appreciate and experience the performance These applications include Internet audio and streaming
20. Extended HALT is not enabled the default powerdown state entered will be HALT Refer to the sections below for details about the HALT and Extended HALT states 6 2 2 1 HALT Powerdown State HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions When one of the processor cores executes the HALT instruction that processor core is halted however the other processor continues normal operation The halted core will transition to the Normal state upon the occurrence of SMI INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself 88 Datasheet Features 6 2 2 2 6 2 3 6 2 3 1 Datasheet intel The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT powerdown state See the Intel Architecture Software Developer s Manual Volume 3B System Programming Guide Part 2 for more information The system can generate a STPCLK while the processor is in the HALT powerdown state When the system de asserts the STPCLK interrupt the processor will return execution to the HALT state While in HALT powerdown state the processor will process bus snoops Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled using the BIOS When one of the processor cores executes the HALT instruct
21. Guidelines see Section 1 2 100 Datasheet e Debug Tools Specifications n t el 8 8 1 8 1 1 8 1 2 Datasheet Debug Tools Specifications Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Intel Core 2 Duo processor E8000 and E7000 series systems Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Intel Core 2 Duo processor E8000 and E7000 series systems the LAI is critical in providing the ability to probe and capture FSB signals There are two sets of considerations to keep in mind when designing an Intel Core 2 Duo processor E8000 and E7000 series system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI lands plug into the processor socket while the processor lands plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sur
22. Other W7 VSS Power Other AA27 VSS Power Other w8 YCC Power Other AA28 VSS Power Other W23 VCC Power Other AA29 VSS Power Other W24 VCC Power Other AA30 VSS Power Other W25 VCC Power Other AB1 VSS Power Other W26 vcc Power Other AB2 IERR Asynch CMOS Output W27 VCC Power Other AB3 FC37 Power Other W28 VCC Power Other AB4 A26 Source Synch _ Input Output W29 VCC Power Other AB5 A24 Source Synch Input Output w30 VCC Power Other AB6 A173 Source Synch Input Output FCO AB7 VSS Power Other Y1 BOOTSELECT Power Other AB8 VCC Power Other Y2 VSS Power Other AB23 VSS Power Other 61 intel Land Listing and Signal Descriptions Table 25 Numerical Land Table 25 Numerical Land Assignment Assignment Land Land Name is das Direction Land Land Name di dud Direction AB24 VSS Power Other AE1 TCK TAP Input AB25 VSS Power Other AE2 VSS Power Other AB26 VSS Power Other AE3 FC18 Power Other AB27 VSS Power Other AE4 RESERVED AB28 VSS Power Other AE5 VSS Power Other AB29 VSS Power Other AE6 RESERVED AB30 VSS Power Other AE7 VSS Power Other AC1 TMS TAP Input AE8 SKTOCC Power Other Output AC2 DBR Power Other Output AE9 VCC Power Other AC3 VSS Power Other AE10 VSS Power Other ACA RESERVED AE11 VCC Power Other AC5 A25 Source Synch Input Output AE12 VCC Power Other AC6 VSS Power Other AE13 VSS Power Other AC7 VSS Power Ot
23. Other Input REQ3 4 K6 Source Synch Input Output TESTHI6 G24 Power Other Input REQ4 J6 Source Synch Input Output TESTHI7 F24 Power Other Input RESERVED v2 TESTHI8 FC42 G3 Power Other Input RESERVED A20 TESTHI9 FC43 G4 Power Other Input RESERVED ACA THERMTRIP M2 Asynch CMOS Output RESERVED AE4 TMS AC1 TAP Input Datasheet m e Land Listing and Signal Descriptions n t el Table 24 Alphabetical Land Table 24 Alphabetical Land Assignments Assignments Land Name E Direction Land Name 2 E 22 Direction TRDY E3 CommonClock Input VCC AF22 Power Other TRST AG1 TAP Input VCC AF8 Power Other VCC AA8 Power Other VCC AF9 Power Other VCC AB8 amp Power Other VCC AG11 Power Other VCC AC23 Power Other VCC AG12 Power Other vcc AC24 Power Other VCC AG14 Power Other vcc AC25 Power Other VCC AG15 Power Other VCC AC26 Power Other VCC AG18 Power Other WCC AC27 Power Other VCC AG19 Power Other vcc Ac28 Power Oter VCC AG21 Power Other VEC AC29 Power Other VCC AG22 Power Other vcc AC30 Power Other VCC AG25 Power Other vcc acs Power Other VCC AG26 Power Other Vcc AD23 Power Other VCC AG27 Power Other VCC AD24 Power Other VCC AG28 Power Other Vcc AD25 Power Other VCC AG29 Power Other VCC AD26 Power Other VCC AG30 Power Other VEC AD27 Po
24. Other VCC J24 Power Other VCC AM14 Power Other Vcc J25 Power Other VCC AM15 Power Other Vcc J26 Power Other VCC AM18 Power Other VCC J27 Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Alphabetical Land Table 24 Alphabetical Land Assignments Assignments Land Name seis E Direction Land Name p TO Direction VCC J28 Power Other VCC T27 Power Other VCC J29 Power Other VCC T28 Power Other VEC J30 Power Other VCC T29 Power Other VCC J8 Power Other VCC T30 Power Other VCC J9 Power Other VCC T8 Power Other VEC K23 Power Other VCC U23 Power Other Vcc K24 Power Other VCC U24 Power Other Vcc K25 Power Other VCC U25 Power Other Vcc K26 Power Other VCC U26 Power Other VCC K27 Power Other VCC U27 Power Other VCC K28 Power Other VCC U28 Power Other Vcc K29 Power Other VCC U29 Power Other VEC K30 Power Other VCC u30 Power Other vcc K8 Power Other VCC U8 Power Other VEC L8 Power Other VCC v8 Power Other Vcc M23 Power Other VCC W23 Power Other VCC M24 Power Other VCC W24 Power Other VEC M25 Power Other VCC W25 Power Other MEG M26 Power Other VCC W26 Power Other VEC M27 Power Other VCC W27 Power Other VCC M28 Power Other VCC W28 Power Other VCC M29 Power Other VCC W29 Power Other YCC M30 Power Other VCC W30 Power Other VCG M8 Power Ot
25. The VID signals are needed to support the processor voltage specification variations See Table 2 for definitions of these signals The VR must supply the voltage that is requested by the signals or disable itself VID_SELECT Output This land is tied high on the processor package and is used by the VR to choose the proper VID table Refer to the Voltage Regulator Design Guide for more information VRDSEL Input This input should be left as a no connect in order for the processor to boot The processor will not boot on legacy platforms where this land is connected to Vss vss Input VSS are the ground pins for the processor and should be connected to the system ground plane VSSA Input VSSA provides isolated ground for internal PLLs on previous generation processors It may be left as a No Connect on boards supporting the processor VSS_SENSE Output VSS_SENSE is an isolated low impedance connection to processor core Vss It can be used to sense or measure ground near the silicon with little noise VSS_MB_ REGULATION Output This land is provided as a voltage regulator feedback sense point for Vss It is connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator Design Guide VTT Miscellaneous voltage supply VTT_OUT_LEFT VTT_OUT_RIGHT Output The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a volta
26. assertion or de assertion of PROCHOT PROCHOT is a bi directional signal As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled for both cores The TCC will remain active until the system de asserts PROCHOT PROCHOT will not be asserted as an output or observed as an input when the processor is in the Stop Grant Sleep Deep Sleep and Deeper Sleep low power states hence the thermal solution must be designed to ensure the processor remains within specification If the processor enters one of the above low power states with PROCHOT already asserted PROCHOT will remain asserted until the processor exits the low power state and the processor DTS temperature drops below the thermal trip point PROCHOT allows for some protection of various components from over temperature situations The PROCHOT signal is bi directional in that it can either signal when the processor either core has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC using PROCHOT can provide a means for thermal protection of system components Bi directional PROCHOT can allow V
27. bus clock and is referred to as a double clocked or 2X address bus Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 10 7 GB s Intel has enabled support components for the processor including heatsink heatsink retention mechanism and socket Manufacturability is a high priority hence mechanical assembly may be completed from the top of the baseboard and should not require any special tooling intel Introduction 1 1 Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Front Side Bus refers to the interface between the processor and system core logic a k a the chipset components The FSB is a multiprocessing interface to processors memory and I O 1 1 1 Processor Terminology Definitions Commonly used terms are explained here for clarification 10 Intel Core 2 Duo processor E8000 series Dual core processor in the FC L
28. can thus help improve the overall security of the system See the Intel Architecture Software Developer s Manual for more detailed information Intel 64 Architecture An enhancement to Intel s IA 32 architecture allowing the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture Further details on Intel 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at http developer intel com technology 64bitextensions Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology allows trade offs to be made between performance and power consumptions based on processor utilization This may lower average power consumption in conjunction with OS support Intel virtualization Technology Intel VT A set of hardware enhancements to Intel server and client platforms that can improve virtualization solutions Intel VT will provide a foundation for widely deployed virtualization solutions and enables more robust hardware assisted virtualization solutions More information can be found at http www intel com technology virtualization Intel Trusted Execution Technology Intel TXT A key element in Intel s safer computing initiative which defines a set of hardware enhancements that interoperate with an Intel TXT enabled OS to help protect against software based attacks Intel TXT creates a hardware fo
29. intel Intel Core 2 Duo Processor E8000 and E7000 Series Datasheet June 2009 Document Number 318732 006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Core 2 Duo processor E8000 and E7000 series may contain design defects or errors known as errata which may cause the product to deviate from publish
30. lo Jo o Jo Jo o o Jo o Jo o Jo o Jo JH Il fa a EM o jo Jo Jo lo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo lo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo 15 Datasheet m e n tel Electrical Specifications 2 4 2 5 16 Reserved Unused and TESTHI Signals All RESERVED lands must remain unconnected Connection of these lands to Vcc Vss Vr or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 4 for a land listing of the processor and the location of all RESERVED lands In a system level design on die termination has been included by the processor to allow signals to be terminated within the processor silicon Most unused GTL inputs should be left as no connects as GTL termination is provided on the processor silicon However see Table 8 for details on GTL signals that do not include on die termination Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the motherboard
31. motherboard for most GTL signals Datasheet e Electrical Specifications n t e 2 7 1 Table 8 Datasheet FSB Signal Groups The front side bus signals have been combined into groups by buffer type GTL input signals have differential input buffers which use GTLREF 1 0 as a reference level In this document the term GTL Input refers to the GTL input group as well as the GTL I O group when receiving Similarly GTL Output refers to the GTL output group as well as the GTL I O group when driving With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals which are dependent upon the rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asychronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 8 identifies which signals are common clock source synchronous and asynchronous FSB Signal Groups Signal Group Type Signals Se AE Ed to BPRI DEFER RESET RS 2 0 TRDY GTL Common Synchronous to ADS BNR BPM 5 0 BRO DBSY DRDY Clock I O BCLK 1 0 HIT HITM LOCK Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO GTL Source Synchronous to A
32. nominal trace impedance is 50 Q then a value between 40 Q and 60 Q should be used Power Segment Identifier PSID Power Segment Identifier PSID is a mechanism to prevent booting under mismatched power requirement situations The PSID mechanism enables BIOS to detect if the processor in use requires more power than the platform voltage regulator VR is capable of supplying For example a 130 W TDP processor installed in a board with a 65 W or 95 W TDP capable VR may draw too much power and cause a potential VR issue Datasheet Electrical Specifications n t el 2 6 2 6 1 Table 3 Datasheet Voltage and Current Specification Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and
33. packaged in a Flip Chip Land Grid Array FC LGA8 package that interfaces with the motherboard using an LGA775 socket The package consists of a processor core mounted on a substrate land carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 6 shows a sketch of the processor package components and how they are assembled together Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket The package components shown in Figure 6 include the following e Integrated Heat Spreader IHS e Thermal Interface Material TIM e Processor core die e Package substrate e Capacitors Processor Package Assembly Sketch Core die TIM M IHS Substrate RR Capacitors LGA775 Socket System B d 4 yste oa T Socket and motherboard are included for reference and are not part of processor package Package Mechanical Drawing The package mechanical drawings are shown in Figure 7 and Figure 8 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include e Package reference with tolerances total height length width etc e IHS parallelism and tilt e Land dimensions e Top side and back side component keep out dimensions e Reference datums e All drawing dimensions are in mm in e Guidelines on
34. potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines 35 e n te Package Mechanical Specifications Figure 7 Processor Package Drawing Sheet 1 of 3 I 1 wr or 3 C88285 7 2200 MISSION COLLEGE BLVD P O BOX 58119 SANTA CLARA CA 95052 8119 MODEL 0 203 c 3 IJ corr C88285 DO NOT SCALE DRAWING IHS LID Z 0 05 intel y OOOO0000000000060000000000 0009 OOOOOO00000000006000000000000000 OOOOOOOO000000000000000000000000 OOOOOOOOOOOOOOOO OOOOOO0000000000 000000000000000000000000000000006 w OOO000000000000009000000000000000 OOOOOOOOOOOOOOOO OO00000000000000 OOOOOOO0O00000000000000000000000000 OOOOOOOOO o ep pun SIE ORANTNG NUMBER DEPARTWENT ATD TRE ME 5 1 Al I5 600000000 40000600 600000000 06000000 OOOOOOOOO 000000000 OOOOOOOOO 1 EN 600000000 I OOOOOCOOO wem A SCALE 02 23 05 DATE 02 23 05 DATE DATE DATE FINISH 00000000 j l OOOOOOOO OOOOOOOO 1 900000000 5 BOTTOM VIEW OOOOOOOOO OOOOOOOO OOOOOOOOO OOOOOOOO 000000000 1 OOOOOOOO OOOOOOOOO L L lt I Q0000000 ODOOOODOO OOOOOOOO OOOOOOOOO 000000000 DESIGNED BY CHECKED BT APPROVED
35. processor s temperature specification see Chapter 5 is the responsibility of the system integrator The motherboard must supply a constant 12 V to the processor s power header to ensure proper operation of the variable speed fan for the boxed processor Refer to Table 32 for the specific requirements Figure 28 Boxed Processor Fan Heatsink Set Points Higher Set Point Highest Noise Level Increasing Fan Speed amp Noise Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature Degrees C Datasheet 99 e n t el Boxed Processor Specifications Table 33 Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Boxed Processor Fan Speed Notes Point C When the internal chassis temperature is below or equal to this set point the fan operates at its lowest speed 1 Recommended maximum internal chassis temperature for nominal operating environment X lt 30 When the internal chassis temperature is at this point the fan operates between its lowest and highest speeds Recommended maximum internal chassis temperature for worst case operating environment Z gt 38 When the internal chassis temperature is above or equal to _ this set point the fan operates at its highest speed NOTES 1 Set point variance is approximately 1 C from fan heatsink to fan heatsink If the boxed processor fan heatsink 4 pin connector is
36. the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operating point Transition of the VID code will occur first in order to ensure proper operation once the processor reaches its normal operating frequency Refer to Figure 17 for an illustration of this ordering Datasheet m e Thermal Specifications and Design Considerations n t el Figure 17 5 2 3 Datasheet Thermal Monitor 2 Frequency and Voltage Ordering TM2 Temperature MAX m Frequency VID VID u2 PROCHOT The PROCHOT signal is asserted when a high temperature situation is detected regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled It should be noted that the Thermal Monitor 2 TCC cannot be activated using the on demand mode The Thermal Monitor TCC however can be activated through the use of the on demand mode On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor feature On Demand mode is intended as a means t
37. trace for front side bus signals For unused GTL input or I O signals use pull up resistors of the same value as the on die termination resistors R77 For details see Table 15 TAP and CMOS signals do not include on die termination Inputs and utilized outputs must be terminated on the motherboard Unused outputs may be terminated on the motherboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing All TESTHI 12 10 0 lands should be individually connected to V using a pull up resistor which matches the nominal trace impedance The TESTHI signals may use individual pull up resistors or be grouped together as detailed below A matched resistor must be used for each group e TESTHI 1 0 e TESTHI 7 2 e TESTHI8 FC42 cannot be grouped with other TESTHI signals e TESTHI9 FC43 cannot be grouped with other TESTHI signals e TESTHI10 cannot be grouped with other TESTHI signals e TESTHI12 FC44 cannot be grouped with other TESTHI signals Terminating multiple TESTHI pins together with a single pull up resistor is not recommended for designs supporting boundary scan for proper Boundary Scan testing of the TESTHI signals For optimum noise margin all pull up resistor values used for TESTHI 12 10 0 lands should have a resistance value within 20 of the impedance of the board transmission line traces For example if the
38. way as in the HALT Snoop State or Stop Grant Snoop State After the snoop is serviced the processor will return to the Extended HALT state or Extended Stop Grant state Sleep State The Sleep state is a low power state in which the processor maintains its context maintains the phase locked loop PLL and stops all internal clocks The Sleep state is entered through assertion of the SLP signal while in the Extended Stop Grant or Stop Grant state The SLP pin should only be asserted when the processor is in the Extended Stop Grant or Stop Grant state SLP assertions while the processor is not in these states is out of specification and may result in unapproved operation In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP DPSLP or RESET are allowed on the FSB while the processor is in Sleep state Snoop events that occur while in Sleep state or during a transition into or out of Datasheet Features 6 2 6 6 2 7 Datasheet intel Sleep state will cause unpredictable behavior Any transition on an input signal before the processor has returned to the Stop Grant state will result in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through
39. 1 VID5 VRDSEL PROCHOT FC25 vec vss vcc vcc vss VCC VCC VSS FC8 VSS ViD4 ITP_CLK0 VSS FC24 vec vss vcc vcc vss VCC VCC VSS A35 A34 vss ITP_CLK1 BPMO BPM1 vec vss VCC VCC vss VCC VCC VSS VSS A33 A32 VSS RSVD VSS vec VSS vcc vcc vss VCC VCC VSS A29 A31 A30 BPM5 BPM3 TRST vec VSS vcc vcc vss VCC VCC VSS VSS A27 A28H VSS BPM4 TDO vec vss vec vcc vss vec SKTOCC vss RSVD VSS RSVD FC18 VSS TCK VCC VSS A22 ADSTB1 VSS FC36 BPM2 TDI VCC VSS VSS A25 RSVD VSS DBR TMS VCC VSS A17 A24 A26 FC37 IERR VSS VTT OUT vcc vss vss A238 A214 VSS FC39 wear vec vss A198 VSS A20 PSII VSS FCO BOOTSELECT vcc vss A188 A168 vss TESTHM ovid MSIDO VCC VSS VSS A14 A15 VSS RSVD MSID1 VCC VSS A108 A128 A138 FC30 FC29 FC28 VCC VSS VSS A9 ATHE VSS DPRSTP COMP1 vcc VSS ADSTBOR VSS ase FERRY vss COMP3 VCC VSS Adi RSVD VSS INIT SMI DPSLP VCC VSS VSS RSVD RSVD VSS IGNNE PWRGOOD VCC vss REQ2 A5 ATR STPCLK THERMTRIP VSS VCC VSS VSS A3 A6 VSS SLP LINT1 VCC vss REQ3 VSS REQO A20M amp VSS LINTO VTT_OUT vec vec vec vec vec voc vec vss REO4s REQ1 VSS FC22 FC3 o vss vss vss vss vss VSS VSS vss vss TESTHMO FC35 VSS GTLREF1 GTLREFO D29 D27 amp DSTBN14 amp DBM amp FC38 D16 amp BPR DEFER RSVD peci a iy CoMP2 FC27 D28 amp vss D24 D23 vss Dies D17 vss FC21 RS1 VSS BRO FC5 vss D26 bsrBP14 vss D21
40. 100 4 D 0 113 4 Vcc Minimum P dd D 0 125 4 D 0 138 5 D 0 150 4 D 0 163 NOTES 1 2 3 Datasheet The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 6 3 This loadline specification shows the deviation from the VID set point The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details 21 intel Table 6 22 Electrical Specifications Intel Core 2 Duo Processor E7000 Series Vcc Static and Transient Tolerance Voltage Deviation from VID Setting V 2 4 Icc A Maximum Voltage Typical Voltage Minimum Voltage 1 65 mo 1 73 mo 1 80 mo 0 000 0 019 0 038 0 008 0 028 0 047 10 0 017 0 036 0 056 15 0 025 0 045 0 065 20 0 033 0 054 0 074 25 0 041 0 062 0 083 30 0 050 0 071 0 092 35 0 058 0 079 0 101 40 0 066 0 088 0 110 45 0 074 0 097 0 119 50 0 083 0 105 0 128 55 0 091 0 114 0 137 60 0 099 0 123 0 146 65 0 107 0 131 0 155 70 0 116 0 140 0 164 75 0 124 0 148 0 173 NOTES 1 Theloadline specification includes both static and transient limits exce
41. 300 Musee lide i 0 1 Vir Vp p NOTES 1 V supplies the PECI interface PECI behavior does not affect Vr min max specifications Refer to Table 4 for AWN Vr specifications The leakage specification applies to powered devices on the PECI bus The input buffers use a Schmitt triggered input design for improved noise immunity One node is counted for each client and one node for the system host Extended trace lengths might appear as additional nodes 29 intel 2 7 3 2 Table 15 30 GTL Front Side Bus Specifications Electrical Specifications In most cases termination resistors are not required as these are integrated into the processor silicon See Table 9 for details on which GTL signals do not include on die termination Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF Table 15 lists the GTLREF specifications The GTL reference voltage GTLREF should be generated on the system board using high precision voltage divider circuits GTL Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes GTLREF pull up on Intel GTLREF PU 3 Series Chipset family 57 6 0 99 57 6 57 6 1 01 Q 2 boards GTLREF pull down on GTLREF_PD Intel 3 Series Chipset 100 0 99 100 100 1 01 Q 2 family boards Ry Termination Resistance 45 50 55 Q COMP 3 0 COMP Resistance 49 40 49 90 50 40 Q COMP8 CO
42. 6 65 6 Figure 15 Intel Core 2 Duo Processor E7000 Series Thermal Profile 72 0 68 0 64 0 y 0 45x 44 9 60 0 Tease C 56 0 52 0 48 0 44 0 0 10 20 30 40 50 60 Power W 80 Datasheet m e Thermal Specifications and Design Considerations n t el 5 1 2 Figure 16 5 2 5 2 1 Datasheet Thermal Metrology The maximum and minimum case temperatures Tc for the processor is specified in Table 27 This temperature specification is meant to help ensure proper operation of the processor Figure 16 illustrates where Intel recommends Tc thermal measurements should be made For detailed guidelines on temperature measurement methodology refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 Case Temperature Tc Measurement Location Measure T at this point geo metric center of the package 37 5 mm Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption by modulating starting and stopping the internal processor core clocks The Thermal Monitor feature must be enabled for the processor to be operating within specifications The temperature at which The
43. BI1 G11 Source Synch Input Output D27 G13 Source Synch Input Output DBI2 D19 Source Synch Input Output D28 F14 Source Synch Input Output DBI3 C20 Source Synch Input Output D29 G14 Source Synch Input Output DBR AC2 Power Other Output D30 F15 Source Synch Input Output DBSY B2 Common Clock Input Output D31 G15 Source Synch Input Output DEFER G7 Common Clock Input D32 G16 Source Synch Input Output DPRSTP T2 Asynch CMOS Input D33 E15 Source Synch Input Output DPSLP P1 Asynch CMOS Input D34 E16 Source Synch Input Output DRDY Ci Common Clock Input Output D35 G18 Source Synch Input Output DSTBNO C8 Source Synch Input Output D36 G17 Source Synch Input Output DSTBN1 G12 Source Synch Input Output D37 F17 Source Synch Input Output DSTBN2 G20 Source Synch Input Output D38 F18 Source Synch Input Output DSTBN3 A16 Source Synch Input Output D39 E18 Source Synch Input Output DSTBPO B9 Source Synch Input Output D40 E19 Source Synch Input Output DSTBP1i E12 Source Synch Input Output D41 F20 Source Synch Input Output DSTBP2 G19 Source Synch Input Output D42 E21 Source Synch Input Output DSTBP3 C17 Source Synch Input Output D43 F21 Source Synch Input Output FCO BOOTSELECT YI Power Other D44 G21 Source Synch Input Output FC3 J2 Power Other D45 E22 Source Synch Input Output FC5 F2 Power Other D46 D22 So
44. DPSLP pin must be de asserted BCLK can be restarted after DPSLP de assertion as described above A period of 15 microseconds to allow for PLL stabilization must occur before the processor can be considered to be in the Sleep state Once in the Sleep state the SLP pin must be de asserted to re enter the Stop Grant state While in the Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions of signals are allowed on the FSB while the processor is in the Deep Sleep state When the processor is in the Deep Sleep state it will not respond to interrupts or snoop transactions Any transition on an input signal before the processor has returned to the Stop Grant state will result in unpredictable behavior PECI is not available and will not respond while in the Deep Sleep State Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 for guidance on how to ensure PECI thermal data is available when the Deep Sleep State is enabled Deeper Sleep State The Deeper Sleep state is similar to the Deep Sleep state but the core voltage is reduced to a lower level The Deeper Sleep state is entered through assertion of the DPRSTP pin while in the Deep Sleep state Exit from Deeper Sleep is initiated by DPRSTP de assertion PECI is not available and will not respond while in the Deeper Sleep State Refer to the appropriate Thermal and Mechanical Design Guidelines
45. FSB interrupts BCLK running lt Snoops and interrupts allowed A Snoop Snoop Event Event STPCLK STPCLK Occurs Serviced Asserted De asserted STPCLK STPCLK De asserted Asserted v Extended HALT Snoop or HALT Snoop State BCLK running Service Snoops to caches v Stop Grant State BCLK running Snoops and interrupts Snoop Event Occurs P Extended Stop Grant or Stop Grant Snoop State Snoop Event Serviced BCLK running v lI d one s lt Service Snoops to caches SLP SLP Asserted De asserted DPSLP DPRSTP Asserted Asserted Sleep State Deep Sleep State l PEE c ponte d BCLK running BCLK can be stopped can be stoppe No Snoops or No Snoops or No Snoops or interrupts allowed 4 1 interrupts allowed lt interrupts allowed PECI unavailable in DPSLP PECI unavailable in DPRSTP PECI unavailable in this state De asserted this state De asserted this state 6 2 1 Normal State This is the normal operating state for the processor 6 2 2 HALT and Extended HALT Powerdown States The processor supports the HALT or Extended HALT powerdown state The Extended HALT powerdown state must be configured and enabled using the BIOS for the processor to remain within specification The Extended HALT state is a lower power state as compared to the Stop Grant State If
46. GA8 package with a 6 MB L2 cache Intel Core 2 Duo processor E7000 series Dual core processor in the FC LGA8 package with a 3 MB L2 cache Processor For this document the term processor is the generic form of the Intel Core 2 Duo processor E8000 series and Intel Core 2 Duo processor E7000 series Voltage Regulator Design Guide For this document Voltage Regulator Design Guide may be used in place of Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket Enhanced Intel Core microarchitecture A new foundation for Intel architecture based desktop mobile and mainstream server multi core processors For additional information refer to http www intel com technology architecture coremicro Keep out zone The area on or near the processor that system design can not use Processor core Processor die with integrated L2 cache LGA775 socket The processors mate with the system board through a surface mount 775 land LGA socket Integrated heat spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Retention mechanism RM Since the LGA775 socket does not include any mechanical features for heatsink attach a retention mechanism is required Component thermal solutions should attach to the processor using a r
47. IERR asserted until the assertion of RESET This signal does not have on die termination Refer to Section 2 6 2 for termination requirements IGNNE Input IGNNE Ignore Numeric Error is asserted to the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is de asserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT Input INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins lands of all processor FSB agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST 70 Datasheet Land Listing and Signal Descriptions intel Table 26
48. IR DAR RE E 94 7 2 1 Boxed Processor Cooling Solution Dimensions eese 94 7 2 2 Boxed Processor Fan Heatsink Weight ee ee eee nene 95 7 2 3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly 95 7 3 Electrical REQUIFEMENKES u cccediceetaicicsscmoresamaneane names bondi ag AERIENE EEEIEE wa awaq 95 7 3 1 Fan Heatsink Power S pply u a u eens eene nenne nennt naaa a aa a 95 7 4 Thermal Specifications ener iara repr e pene Roe IRI E DEAE RR ud tavauagiatdwaecesen c FRA tapas 97 7 4 1 Boxed Processor Cooling Requirements r 97 7 4 2 Variable Speed Fan usasqa dee due ka ope eaae su Uo naar Da KS IMPER PME TRA RA 99 8 Debug Tools Specifications ores xus sue e orsi da dX ERR Ye Rau Cus E3ZR Ra Eger FERE REIR 101 8 1 Logic Analyzer Interface LAI uu orie innies cinta tnu da oa sed reo xk ae EFFERRE ERR RR scenes 101 8 1 1 Mechanical Considerations eeeiens enean panna ni nane gana xu raa aa panna awqa 101 8 1 2 Electrical Considerations ccceecee cece eect eee eee eee eee sa ss noitia ianiai 101 Datasheet Figures 1 Intel Core 2 Duo Processor E8000 Series Vcc Static and Transient Tolerance 21 2 Intel Core 2 Duo Processor E7000 Series Vcc Static and Transient Tolerance 23 3 Vcc Overshoot Example Waveforms sirarni aiian sna ie mah pini oin Er ua d 24 4 Differential Clock
49. J21 Power Other VCC AM22 Power Other VCC AJ22 Power Other Vcc AM25 Power Other YCC AJ25 Power Other VCC AM26 Power Other VCC AJ26 Power Other Vcc AM29 Power Other VCC AJ8 Power Other VCC AM30 Power Other VCC AJ9 Power Other YCC AM8 Power Other VCC AK11 Power Other Vcc AM9 Power Other VCC AK12 Power Other WCC AN11 Power Other VCC AK14 Power Other Vcc AN12 Power Other VCC AK15 Power Other VCC AN14 Power Other VCC AK18 Power Other VCC AN15 Power Other VCC AK19 Power Other VCC AN18 Power Other VCC AK21 Power Other vcc AN19 Power Other VCC AK22 Power Other VCC AN21 Power Other VEC AK25 Power Other WEC AN22 Power Other VCC AK26 Power Other Vcc AN25 Power Other VCC AK8 Power Other WCC AN26 Power Other VCC AK9 Power Other VCC AN29 Power Other VCC AL11 Power Other Vcc AN30 Power Other VCC AL12 Power Other VCC AN8 Power Other VCC AL14 Power Other YCC AN9 Power Other VCC AL15 Power Other VCC J10 Power Other VCC AL18 Power Other VCC Jii Power Other VCC AL19 Power Other Vcc J12 Power Other VCC AL21 Power Other Vcc J13 Power Other VCC AL22 Power Other Vcc J14 Power Other VCC AL25 Power Other VCC J15 Power Other VCC AL26 Power Other VCC J18 Power Other VCC AL29 Power Other YCC J19 Power Other VCC AL30 Power Other Vcc J20 Power Other VCC AL8 Power Other VCC J21 Power Other VCC AL9 Power Other VCC J22 Power Other VCC AM11 Power Other Vcc J23 Power Other VCC AM12 Power
50. MHz BCLK 1 0 frequency Individual processors will only operate at their specified FSB frequency For more information about these signals refer to Section 4 2 BSEL 2 0 Frequency Table for BCLK 1 0 BSEL2 BSEL1 BSELO FSB Frequency L L L 266 MHz L L H Reserved L H H Reserved L H L Reserved H H L Reserved H H H Reserved H L H Reserved H L L 333 MHz Phase Lock Loop PLL and Filter An on die PLL filter solution will be implemented on the processor The VCCPLL input is used for the PLL Refer to Table 4 for DC specifications BCLK 1 0 Specifications Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes VL Input Low Voltage 0 30 N A N A V 4 Vu Input High Voltage N A N A 1 15 4 VcRoss abs Absolute Crossing Point 0 300 N A 0 550 V 4 2 AVcross_ Range of Crossing Points N A N A 0 140 V 4 Vos Overshoot N A N A 1 4 V 4 3 Vus Undershoot 0 300 N A N A V 4 3 Vswinc Differential Output Swing 0 300 N A N A V 5 4 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 25 Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLKO equals the falling edge of BCLK1 3 Steady state voltage not including overshoot or undershoot Datasheet m e Electrical Specifications n t e 4 Overshoot is defined a
51. MP Resistance 24 65 24 90 25 15 Q NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 GTLREF is to be generated from V by a voltage divider of 1 resistors If an Adjustable GTLREF circuit is used on the board for Quad Core processors compatibility the two GTLREF lands connected to the Adjustable GTLREF circuit require the following GTLREF PU 50 Q GTLREF PD 100 Q 3 Rrr is the on die termination resistance measured at Vrr 3 of the GTL output driver 4 COMP resistance must be provided on the system board with 196 resistors COMP 3 0 and COMPS resistors are to Vss Datasheet Electrical Specifications 2 8 2 8 1 Table 16 Datasheet Clock Specifications intel Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the processor core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier will be set at its default ratio during manufacturing The processor supports Half Ratios between 7 5 and 13 5 refer to Table 16 for the processor supported ratios The processor uses a differential clocking implementation For more information on the processor clocking contact your Intel field representative Core Frequency to FSB Multiplier Configuration
52. Machine eesesessesseseseesesnsan senken nane nasus anna nasus aka nana 88 20 Mechanical Representation of the Boxed Processor 93 21 Space Requirements for the Boxed Processor Side View sess 94 22 Space Requirements for the Boxed Processor Top View r 94 23 Overall View Space Requirements for the Boxed Processor 95 24 Boxed Processor Fan Heatsink Power Cable Connector Description 96 25 Baseboard Power Header Placement Relative to Processor Socket Y 97 26 Boxed Processor Fan Heatsink Airspace Keepout Requirements E 1 ea ERE 98 27 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 2 view 98 28 Boxed Processor Fan Heatsink Set Points eese eene 99 Datasheet 5 Tables REN Ice MS 2 Voltage Identification Definition u u a aa sssas sss khe nenne ned haha khen h span sa sua iau ann 3 Absolute Maximum and Minimum Ratings r rr emen 4 Voltage and Current Speciflceati fS uu cer awpa sorte credence ea sa sawa sasa pisa shewe cle venia teens 5 Intel Core 2 Duo Processor E8000 Series Vcc Static and Transient Tolerance 6 Intel Core 2 Duo Processor E7000 Series Vcc Static and Transient Tolerance 7 Vcc Overshoot Spe ifiCationiSi u LU aaa assaka mmn y
53. OOO _ N Socket 775 Quadrants Top View AN AM AL AK AJ AH pogo Q99Z z 225 r raozzoaovecorouwuaoom 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211109 8 7 6 54 3 2 Data V_ Clocks 41 Datasheet 42 Package Mechanical Specifications Datasheet m Land Listing and Signal Descriptions n tel 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions 4 1 Processor Land Assignments This section contains the land listings for the processor The land out footprint is shown in Figure 12 and Figure 13 These figures represent the land out arranged by land number and they show the physical location of each signal on the package land array top view Table 24 lists the processor lands ordered alphabetically by land signal name Table 25 lists the processor lands ordered numerically by land number Datasheet 43 intel Land Listing and Signal Descriptions Figure 12 land out Diagram Top View Left Side 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 N vcc vec vss vss vec vec vss vss vec vec vss vec vec vss vss vec AM vcc vcc vss vss vcc vcc vss vss vcc vcc vss vcc vcc vss vs
54. Power Other AJ15 Vcc Power Other AK24 VSS Power Other AJ16 VSS Power Other AK25 VCC Power Other AJ17 VSS Power Other AK26 VCC Power Other AJ18 VCC Power Other AK27 VSS Power Other AJ19 VEC Power Other AK28 VSS Power Other AJ20 VSS Power Other AK29 VSS Power Other AJ21 VCC Power Other AK30 VSS Power Other AJ22 Vcc Power Other AL1 FC25 Power Other AJ23 VSS Power Other AL2 PROCHOT Asynch CMOS Input Output AJ24 VSS Power Other AL3 VRDSEL Power Other AJ25 VCC Power Other AL4 VID5 Asynch CMOS Output AJ26 VCC Power Other AL5 VID1 Asynch CMOS Output AJ27 VSS Power Other AL6 VID3 Asynch CMOS Output AJ28 VSS Power Other AL7 VSS Power Other AJ29 VSS Power Other AL8 VCC Power Other AJ30 VSS Power Other AL9 VCC Power Other AK1 FC24 Power Other AL10 VSS Power Other AK2 VSS Power Other AL11 VCC Power Other AK3 ITP_CLKO TAP Input AL12 VCC Power Other AK4 VID4 Asynch CMOS Output AL13 VSS Power Other AK5 VSS Power Other AL14 VCC Power Other AK6 FC8 Power Other AL15 VCC Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 25 Numerical Land Table 25 Numerical Land Assignment Assignment Land Land Name EX cx Direction Land Z Land Name TE T Direction AL16 VSS Power Other AM25 VCC Power Othe
55. R RR A OL Ron 81 5 2 Processor Thermal Feat reS insisi viniani aiea o sa sa aycu ero ARA NA a esci Esa EASE 81 5 2 1 Thermal MOhitOr iiie gr rop ener atr na ugar egeo p Ra dax isa ara NEC grau ERE 81 5 2 2 Thermal Monitor 2 eere ox ente Suasana Wandi ya Cau SERES Chie AERUA Mm E EE 82 5 2 3 On Demand MOde ul rhe uu ssp s ERR SEXE RRUE E ATEREA VAA EE tainai TEN 83 5 2 4 PROCHOT Signal cerise ra ssaneaesvadadeveehesetredea saa sasa aqa a XR a Nin eaa ne aaa aie 84 5 2 5 THERMTRIPZ Signal erii extis nsa son iaaea rica ru ail ka SR EE YR ERA Sx di 84 5 3 Platform Environment Control Interface PECI ssssssesssesee mmn 85 5 9 0 IntrOQUCtlODn sirs So uuu tme Ern dee candid mehr bises eain anra aai ped ndis e de ae RR NE AE 85 5 3 1 1 TCONTROL and TCC activation on PECI Based Systems 85 5 3 2 PECI Specifications sieut there pru heau ka a zB FR a RR RRR YER anes RR C apaq se 86 5 3 2 1 PECI Device Address srren iranicus aaa saan ansa d anna saka 86 Datasheet 3 5 3 2 2 PECI Command SUppoOLt iiie soiree cepa u usss a E RU RAAE ADEE 86 5 3 2 3 PECI Fault Handling Requirements sess 86 5 3 2 4 PECI GetTempO Error Code Support 86 6 FS BCU RSS E 87 6 1 Power On Configuration Options cecece cece eee eee eee eee eee eee aa aia 87 6 2 Clock Control and Low Power States u a eee e eect eee eee qawa neta eene m
56. R thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on bi directional PROCHOT only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power With a properly designed and characterized thermal solution it is anticipated that bi directional PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Refer to the Voltage Regulator Design Guide for details on implementing the bi directional PROCHOT feature THERMTRIP Signal Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 26 At this point the FSB signal THERMTRIPZ will go active and stay active as described in Table 26 THERMTRIP activation is independent of processor activity and does not generate any bus cycles If THERMTRIP is asserted processor core voltage Vcc must be removed within the ti
57. S Power Other AM21 VCC Power Other AN29 VCC Power Other AM22 VCC Power Other AN30 VCC Power Other AM23 VSS Power Other AM24 VSS Power Other 65 intel Land Listing and Signal Descriptions 4 2 Alphabetical Signals Reference Table 26 Signal Description Sheet 1 of 10 Name Type Description A 35 3 Input Output A 35 3 Address define a 239 byte physical memory address space In sub phase 1 of the address phase these signals transmit the address of a transaction In sub phase 2 these signals transmit transaction type information These signals must connect the appropriate pins lands of all agents on the processor FSB A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processor samples a subset of the A 35 3 signals to determine power on configuration See Section 6 1 for more details A20M Input If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion
58. SS AJ28 Power Other VSS AM4 Power Other VSS AJ29 Power Other VSS AN1 Power Other VSS AJ30 Power Other VSS AN10 Power Other VSS AJ4 Power Other VSS AN13 Power Other VSS AJ7 Power Other VSS AN16 Power Other VSS AK10 Power Other VSS AN17 Power Other VSS AK13 Power Other VSS AN2 Power Other VSS AK16 Power Other VSS AN20 Power Other VSS AK17 Power Other VSS AN23 Power Other Datasheet 53 54 intel Land Listing and Signal Descriptions Table 24 Alphabetical Land Table 24 Alphabetical Land Assignments Assignments Land Name e ci c dad Direction Land Name Did bol odis Direction VSS AN24 Power Other VSS H12 Power Other VSS AN27 Power Other VSS H13 Power Other VSS AN28 Power Other VSS H14 Power Other VSS C10 Power Other VSS H17 Power Other VSS C13 Power Other VSS H18 Power Other VSS C16 Power Other VSS H19 Power Other VSS C19 Power Other VSS H20 Power Other VSS C22 Power Other VSS H21 Power Other VSS C24 Power Other VSS H22 Power Other VSS C4 Power Other VSS H23 Power Other VSS C7 Power Other VSS H24 Power Other VSS D12 Power Other VSS H25 Power Other VSS D15 Power Other VSS H26 Power Other VSS D18 Power Other VSS H27 Power Other VSS D21 Power Other VSS H28 Power Other VSS D24 Power Other VSS H3 Power Other VSS D3 Power Other VSS H6 P
59. T all FSB agents will de assert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 6 1 This signal does not have on die termination and must be terminated on the system board RESERVED All RESERVED lands must remain unconnected Connection of these lands to Vcc Vss Vr or to any other signal including each other can result in component malfunction or incompatibility with future processors RS 2 0 Input RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins lands of all processor FSB agents SKTOCC Output SKTOCC Socket Occupied will be pulled to ground by the processor System board designers may use this signal to determine if the processor is present Datasheet Land Listing and Signal Descriptions intel Table 26 Signal Description Sheet 8 of 10 Name Type Description SLP Input SLP Sleep when asserted in Extended Stop Grant or Stop Grant state causes the processor to enter the Sleep state In the Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL st
60. Typical Voltage Minimum Voltage 1 40 mo 1 48 mo 1 55 mo 0 0 000 0 019 0 038 5 0 007 0 026 0 046 10 0 014 0 034 0 054 15 0 021 0 041 0 061 20 0 028 0 049 0 069 25 0 035 0 056 0 077 30 0 042 0 063 0 085 35 0 049 0 071 0 092 40 0 056 0 078 0 100 45 0 063 0 085 0 108 50 0 070 0 093 0 116 55 0 077 0 100 0 123 60 0 084 0 108 0 131 65 0 091 0 115 0 139 70 0 098 0 122 0 147 75 0 105 0 130 0 154 NOTES 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 6 3 2 This table is intended to aid in reading discrete points on Figure 1 3 The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details 4 Adherence to this loadline specification is required to ensure reliable processor operation Datasheet Electrical Specifications intel Figure 1 Intel Core 2 Duo Processor E8000 Series Vcc Static and Transient Tolerance VI VI VI VI VI Vcc V lt lt VI VI VI VI VI VI Icc A 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 D 0 000 D 0 013 4 ia Vcc Maximum D 0 038 4 D 0 050 4 D 0 063 4 D 0 075 4 D 0 088 4 D 0
61. UT LEFT and VIT OUT RIGHT per 580 mA land Icc 18 Datasheet Electrical Specifications intel Table 4 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 10 ia Icc for Vrr supply before Vcc stable ex 4 5 A l9 Icc for Vrr supply after Vcc stable 4 6 Icc_vCCPLL Icc for PLL land 130 mA ICC_GTLREF Icc for GTLREF 200 HA Datasheet NOTES 1 O 10 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and can not be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep technology or Extended HALT State Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be updated with characterized data from silicon measurements at a later date These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 3 and Table 2 for more information The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscil
62. Updated Table 2 1 April 2008 Added the PSI signal io Added Intel Core 2 Duo processor E8600 and E7300 K suse Sud Updated FSB termination voltage in Table 2 3 004 Added Intel Core 2 Duo processor E7400 October 2008 005 Added Intel Core 2 Duo processor E7500 January 2009 006 Added Intel Core 2 Duo processor E7600 June 2009 88 8 Datasheet Introduction 1 Note Note Note Datasheet intel Introduction The Intel Core 2 Duo processor E8000 and E7000 series is based on the Enhanced Intel Core microarchitecture The Intel Enhanced Core microarchitecture combines the performance of previous generation Desktop products with the power efficiencies of a low power microarchitecture to enable smaller quieter systems The Intel Core 2 Duo processor E8000 and E7000 series are 64 bit processors that maintain compatibility with IA 32 software In this document the Intel Core 2 Duo processor E8000 and E7000 series may be referred to as the processor In this document unless t otherwise specified the Intel Core 2 Duo processor E8000 series refers to the Intel Core 2 Duo processors E8600 E8500 E8400 E8300 E8200 and E8190 In this document unless t otherwise specified the Intel Core 2 Duo processor E7000 series refers to the Intel Core 2 Duo processors E7600 E7500 E7400 E7300 and E7200 The processors use Flip Chip Land Grid Array FC LGA8 package technology a
63. VSS Power Other J23 VCC Power Other M1 VSS Power Other J24 VCC Power Other SEEHNTEIB J25 vcc Power Other me Asynch CMOS Output J26 vcc Power Other M3 STPCLK Asynch CMOS Input J27 VCC Power Other M4 A073 Source Synch Input Output J28 VCC Power Other M5 A053 Source Synch Input Output J29 VCC Power Other M6 REQ2 Source Synch _ Input Output J30 VCC Power Other M7 VSS Power Other K1 LINTO Asynch CMOS Input M8 VCC Power Other K2 VSS Power Other M23 VCC Power Other K3 A20M Asynch CMOS Input M24 VCC Power Other K4 REQO Source Synch _ Input Output M25 VCC Power Other K5 VSS Power Other M26 VCC Power Other K6 REQ3 Source Synch _ Input Output M27 VCC Power Other K7 VSS Power Other M28 VCC Power Other 59 60 intel Land Listing and Signal Descriptions Table 25 Numerical Land Table 25 Numerical Land Assignment Assignment Land Land Name is da Direction Land Land Name lot did Direction M29 VCC Power Other R6 ADSTBO Source Synch _ Input Output M30 VCC Power Other R7 VSS Power Other N1 PWRGOOD Power Other Input R8 VCC Power Other N2 IGNNE Asynch CMOS Input R23 VSS Power Other N3 VSS Power Other R24 VSS Power Other N4 RESERVED R25 VSS Power Other N5 RESERVED R26 VSS Power Other N6 VSS Power Other R27 VSS Power Other N7 VSS Power Other R28 VSS Power Othe
64. WaVvefOEtm 2 u eiue doe varese vacuo kuda Waqasaq Fee oa weekends cue LEAD qawa yq 34 5 Measurement Points for Differential Clock Waveforms rr 34 6 Processor Package Assembly Sketch a sassswssaasusasasasnnasaaassasssaasa sassa sawaswaana 35 7 Processor Package Drawing Sheet 1 Of 3 a eee eee eee eee eee ene enna tas 36 8 Processor Package Drawing Sheet 2 Of 3 ccceceeeee cece ee eee eee eee eee ee eee e nena eee eee nnns 37 9 Processor Package Drawing Sheet 3 Of 3 eee eee eee ener e eaten seen nnne 38 10 Processor Top Side Markings Example ccsccee cece eee eee eee eee meme eee 40 11 Processor Land Coordinates and Quadrants Top View 41 12 land out Diagram Top View Left Side r rr 44 13 land out Diagram Top View Right Side eee ee eee eee nena tees eee eae eeneee 45 14 Intel Core 2 Duo Processor E8000 Series Thermal Profile 79 15 Intel Core 2 Duo Processor E7000 Series Thermal Profile sss 80 16 Case Temperature TC Measurement Location nemen emen 81 17 Thermal Monitor 2 Frequency and Voltage Ordering esses 83 18 Conceptual Fan Control Diagram on PECI Based Platforms 85 19 Processor Low Power State
65. age 0 0 20 V Ig Output Low Current 16 50 mA 2 Ilo Output Leakage Current N A 200 HA 3 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Measured at V m 0 2 V 3 For Vin between 0 and Voy Datasheet 27 intel Electrical Specifications Table 13 CMOS Signal Group DC Specifications T Parameter Min Max Unit Notes VIL Input Low Voltage 0 10 Vr 0 30 V 3 6 Vin Input High Voltage Vr 0 70 Vr 0 10 V 4 5 6 VoL Output Low Voltage 0 10 Vor 0 10 V VoH Output High Voltage 0 90 Vir Vr 0 10 V 2 5 6 Io Output Low Current Vor 0 10 67 Vy 0 10 27 A 6 7 Tou Output Low Current Vor 0 10 67 Vz 0 10 27 A 6 7 Ij Input Leakage Current N A 100 HA 8 ILo Output Leakage Current N A 100 HA 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 All outputs are open drain 3 Vr is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 4 Vip is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 5 Vin and Voy may experience excursions above V7 6 The V referred to in these specifications refers to instantaneous V 7 Ig is measured at 0 10 Vr Ig is measured at 0 90 Vr 8 Leakage to Vss with land held at Vr 9 Leakage to Vr with land held at 300 mV 28 D
66. ai 8 FSB Signal GFOUDS 2er nonet ya randia rh ER AEEA EED EENE REREN EEE 9 Signal CharacteristiCs III i oet raesent exer E kon Ua A EOE E dale cise a EEE 10 Signal Reference Voltages iecore hern a ae ian ge xtn e xen PRESE eEaRARM PK UNE u nue ne a RR ade 11 GTL Signal Group DC Specifications usa a aaa eee eee eee eee eee eene nennen 12 Open Drain and TAP Output Signal Group DC Specifications 13 CMOS Signal Group DC Specifications c cece cece eee eee ee eee eee eee nemen emen enne 14 PECI DC Electrical Limits uuu A sien cn trae rent akawa qe awamassnqa ar RR phe UE RO MERE RA Nae dO 15 GTL Bus Voltage Definitions esed ah dariana niniin paqan sk sa DA P eR gag sa Fia cites Nga veunie 16 Core Frequency to FSB Multiplier Configuration nemen 17 BSEL 2 0 Frequency Table for BCLK 1 0 r 18 Front Side Bus Differential BCLK Specifications eee eee eee eee nnne 19 FSB Differential Clock Specifications 1333 MHz FSB tees eee e eens memes 20 FSB Differential Clock Specifications 1066 MHz FSB rr 21 Processor Loading SpecIfications uu u us aaa eee eee ne sara eee een 22 Package Handling Guidelines cccceceeceeeneeeeeseenecneeaeeeeneeeaeeseesaeseseeseeaneeenaaeaseseanaenta 23 Processor Materials uuu asas akanq
67. as reached a level beyond where permanent silicon damage may occur Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRIP Driving of the THERMTRIP signal is enabled within 10 us of the assertion of PWRGOOD provided V and Vcc are asserted and is disabled on de assertion of PWRGOOD if VrTr or Vcc are not valid THERMTRIP may also be disabled Once activated THERMTRIP remains latched until PWRGOOD V or Vec is de asserted While the de assertion of the PWRGOOD V or Vec signal will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 us of the assertion of PWRGOOD provided Vr and Vcc are valid THERMTRIP Output TMS Test Mode Select is a JTAG specification support signal used Te Input by debug tools TRDY Target Ready is asserted by the target to indicate that it is TRDY Input ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins lands of all FSB agents TRST Test Reset resets the Test Access Port TAP logic TRST TRE Input must be driven low during power on Reset VCC are the power pins for the processor The voltage supplied to VCC Input th
68. at the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep Technology e Voltage Frequency selection is software controlled by writing to processor MSR s Model Specific Registers thus eliminating chipset dependency If the target frequency is higher than the current frequency Vcc is incriminated in steps 12 5 mV by placing a new value on the VID signals after which the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded If the target frequency is lower than the current frequency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals Processor Power Status Indicator PSI Signal The processor incorporates the PSI signal that is asserted when the processor is in a reduced power consumption state PSI can be used to improve efficiency of the voltage regulator resulting in platform power savings PSI may be asserted only when the processor is in the Deeper Sleep state 8 Datasheet m e Boxed Processor Specifications n t el 7 7 1 Note Note Figure 20 Datasheet Boxed Processor Specifications Introduction The processor will also be offered as an Intel boxed processor Inte
69. atasheet Electrical Specifications 2 7 3 1 Table 14 Datasheet intel Platform Environment Control Interface PECI DC Specifications PECI is an Intel proprietary one wire interface that provides a communication channel between Intel processors chipsets and external thermal monitoring devices The processor contains Digital Thermal Sensors DTS distributed throughout die These sensors are implemented as analog to digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal fan speed control More detailed information may be found in the Platform Environment Control Interface PECI Specification PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes Vin Input Voltage Range 0 15 Vor V Vhysteresis Hysteresis 0 1 Vqr V 2 Vn Negative edge threshold voltage 0 275 Vr 0 500 Vr V Vp Positive edge threshold voltage 0 550 Vr 0 725 Vir V High level output source I 6 0 N A mA source Voy 0 75 Vr Low level output sink Isi 0 5 1 0 mA sink VoL 0 25 Vrr Tleak High impedance state leakage to Vy N A 50 HA 3 Ileak High impedance leakage to GND N A 10 HA Cous Bus capacitance per node N A 10 pF 4 Signal noise immunity above
70. atching applies to rising edge rate for Clock and falling edge rate for Clock It is measured using a 75 mV window centered on the average cross point where Clock rising meets Clock falling The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations 6 Duty Cycle High time Period must be between 40 and 60 Table 20 FSB Differential Clock Specifications 1066 MHz FSB T Parameter Min Nom Max Unit Figure Notes BCLK 1 0 Frequency 265 307 266 693 MHz 6 T1 BCLK 1 0 Period 3 74963 3 76922 ns 4 2 T2 BCLK 1 0 Period Stability 150 ps 4 3 T5 BCLK 1 0 Rise and Fall Slew Rate 2 5 8 V ns 5 4 Slew Rate Matching N A N A 20 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor core frequencies based on a 266 MHz BCLK 1 0 2 The period specified here is the average period A given period may vary from this specification as governed by the period stability specification T2 The Min period specification is based on 300 PPM deviation from a 3 75 ns period The Max period specification is based on the summation of 300 PPM deviation from a 3 75 ns period and a 0 5 maximum variance due to spread spectrum clocking 3 In this context period stability is defined as the worst case timing difference between successive crossover voltages In other words the largest absol
71. ation on the die In addition some of the high frequency capacitance required for the FSB is included on the processor package However additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus Bulk decoupling must also be provided by the motherboard for proper A GTL bus operation Voltage Identification The Voltage Identification VID specification for the processor is defined by the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC lands see Chapter 2 6 3 for Vcc overshoot specifications Refer to Table 13 for the DC specifications for these signals Voltages for each processor frequency is provided in Table 4 To support the Deeper Sleep State the platform must use a VRD 11 1 compliant solution The Deeper Sleep State also requires additional platform support Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings This is reflected by the VID Range values provided in Table 4 Refer to the Intel Core 2 Duo Processor E8000 and E7000 Series Specification Update for further details on specific valid core frequency and VID values of the processor Note that this differs from the VID employed by the proces
72. awauyakuq Ea a CARE ERR RRIRE RIA EPUM AD aE 24 Alphabetical Land AssignmmentS UU esa nessun Ruta une nu naa n RR R3R XR GGG GR R4 Ra Ra RRR aa ga Rag 25 Numerical Land Assignment enirn rne ek Sa irn elle nn xn code e RUN E EE EE Hr Fa ei Iud xa na santas 26 Signal Descriptio ssim m EmmTEPMST 27 Processor Thermal Specifications eir ese haer enki hana Dea Eua age ga sin ac sake eade ka RR 28 Intel Core 2 Duo Processor E8000 Series Thermal Profile cccccccccceeeesssseeeeeeeeeceeseeees 29 Intel Core 2 Duo Processor E7000 Series Thermal Profile cccccccccseecsssesseeeeeeececeeeesess 30 GetTemp0 Error Codes uu uuu u tke ether e exte no net de nba nma ains SA sek Ea come naa a a and d 31 Power On Configuration Option Signals jau 32 Fan Heatsink Power and Signal Specifications sss 33 Fan Heatsink Power and Signal Specifications rr 6 Datasheet intel Intel Core 2 Duo Processor E8000 and E7000 Series Features Available at 3 33 GHz 3 16 GHz 3 00 GHz 2 83 GHz and 2 66 GHz for the Intel Core 2 Duo processor E8000 series Available at 3 06 GHz 2 93 GHz 2 80 GHz 2 66 GHz and 2 53 GHz for the Intel Core 2 Duo processor E7000 series Enhanced Intel Speedstep Technology Supports Intel 64 architecture Supports Intel Virtualization Technology Intel VT Intel Core 2 Duo processors
73. awing Sheet 2 of 3 2 eum D e u w l 21m C88285 p te 0 021 F SCALE 60 1 DETAIL a hy I s OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO Al 0000000000 6000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 OOOO0O000000000000900000000000000000 OOOOOOOOOOOOOOOOQOOCOOOOOOOOOOOOOO 000000000 000000000 000000000 ooooooooo 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000005000 000000060 000000000 000000000 000000000 i 000000000 000000000 000000000 000000000 000000000 000000000 o 000000000 000000000 000000000 O00000000000000000000000000000000 O00000000000000000000000000000000 OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 00000000060 QOO BOTTOM VIEW a 1 NC 4 1X T Eg F 4 oemat C SCALE 20 1 om D SCALE 20 1 COMMENTS NAX MILLIMETERS RI 4 BASIC MIN SYMBOL
74. binations of power and Tc 5 775_VR_CONFIG_06 guidelines provide a design target for meeting future thermal requirements 78 Datasheet Thermal Specifications and Design Considerations Table 28 Intel Core 2 Duo Processor E8000 Series Thermal Profile intel Figure 14 Intel Core 2 Duo Processor E8000 Series Thermal Profile Power Maximum Tc Power Maximum Tc Power Maximum Tc W C W C W C 0 45 1 24 55 2 48 65 3 2 45 9 26 56 0 50 66 1 4 46 8 28 56 9 52 66 9 6 47 6 30 57 7 54 67 8 8 48 5 32 58 5 56 68 6 10 49 3 34 59 4 58 69 5 12 50 1 36 60 2 60 70 3 14 51 0 38 61 1 62 71 1 16 51 8 40 61 9 64 72 0 18 52 7 42 62 7 65 72 4 20 53 5 44 63 6 22 54 3 46 64 4 72 0 68 0 64 0 o y 0 42x 45 1 Tcase C a D o 52 0 48 0 44 0 30 40 Power W 50 60 Datasheet 79 e n tel Thermal Specifications and Design Considerations Table 29 Intel Core 2 Duo Processor E7000 Series Thermal Profile Power W e bis Power s Te Power dier Ig 0 44 9 24 55 7 48 66 5 2 45 8 26 56 6 50 67 4 4 46 7 28 57 5 52 68 3 6 47 6 30 58 4 54 69 2 8 48 5 32 59 3 56 70 1 10 49 4 34 60 2 58 71 0 12 50 3 36 61 1 60 71 9 14 51 2 38 620 62 72 8 16 52 1 40 62 9 64 73 7 18 53 0 42 63 8 65 74 1 20 53 9 44 647 22 54 8 4
75. connected to a 4 pin motherboard header and the motherboard is designed with a fan speed controller with PWM output CONTROL see Table 32 and remote thermal diode measurement capability the boxed processor will operate as follows As processor power has increased the required thermal solutions have generated increasingly more noise Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage The 4th wire PWM solution provides better control over chassis acoustics This is achieved by more accurate measurement of processor die temperature through the processor s Digital Thermal Sensors DTS and PECI Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures If the new 4 pin active fan heat sink solution is connected to an older 3 pin baseboard processor fan header it will default back to a thermistor controlled mode allowing compatibility with existing 3 pin baseboard designs Under thermistor controlled mode the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet For more details on specific motherboard requirements for 4 wire based fan speed control refer to the appropriate Thermal and Mechanical Design
76. dinates The coordinates are referred to throughout the document to identify processor lands Processor Land Coordinates and Quadrants Top View Figure 11 Voc Vss 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Q L uj z lt lt lt AH EREE Address Common Clock Async Q92o Z z225 wvrozzoxorouwuoomc pepecsesecoces 000000000 OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO 09990020 OOOOOOQOO OOOO0000 OOOOOOOOO OOOOOOOOO OOOOOOOOO 900000000 OOOO00000 OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO 200000000 OOOOOOOO0O0 OOOQQOQ000 Net A OK ouf A 2 Wal SN OOOOOOOOO 2900000000 OOOOOOOO00 OOOOOOO000 OOOOOQO0O0QQ NA NA NA NA NA VA O OO CO OG O D OC 300000000 OOOOOOOO00 OOOOOOO00 OOOOOOOO00 OOOOOO0000 Nul OOOO0O00000000000000 ooo Y OOOOO0O0000000000000000000 OOOOOOOOOOOOOOOOCOOCOOOCOOQPf OO00000000000000000000Q9 OOOOOOOOOOOOOOOOOOOOO QODO r r Xd QOO Qo pOooQeooo OOOOCOOOOCOOOCOOOCOQOQ OOOO O000000000000000097000000 OOOOOOOOO OOOOOOOOO 0100101010101010 0100101010101010 0100101010101010 OOOOOOOOO OQOOOoNOoOoOoo OQOOOOOOO OOOOOOOOO OOQIOOOOOOO OQOOOOOOO OOOOOO0000 OOIOOOOOOO OOOOO0000 OoooooooooooooooO0O0000000 OOOO00000000000000000000 OOOOOO0000000000000000000 OOOOOOOOOOO0O000000000000C 0O0000000000000000 0000000 OOOO000000000000000000000 OOO0O00000000000000O0000000 OOO0000000000000000 O
77. e NE cxx Direction Land Land Name E T Direction AF10 VSS Power Other AG19 VCC Power Other AF11 VCC Power Other AG20 VSS Power Other AF12 VCC Power Other AG21 VCC Power Other AF13 VSS Power Other AG22 VCC Power Other AF14 VCC Power Other AG23 VSS Power Other AF15 VCC Power Other AG24 VSS Power Other AF16 VSS Power Other AG25 VCC Power Other AF17 VSS Power Other AG26 VCC Power Other AF18 Vcc Power Other AG27 VCC Power Other AF19 VCC Power Other AG28 VCC Power Other AF20 VSS Power Other AG29 VCC Power Other AF21 VCC Power Other AG30 VCC Power Other AF22 VCC Power Other AH1 VSS Power Other AF23 VSS Power Other AH2 RESERVED AF24 VSS Power Other AH3 VSS Power Other AF25 VSS Power Other AH4 A32 Source Synch _ Input Output AF26 VSS Power Other AH5 A333 Source Synch Input Output AF27 VSS Power Other AH6 VSS Power Other AF28 VSS Power Other AH7 VSS Power Other AF29 VSS Power Other AH8 VCC Power Other AF30 VSS Power Other AH9 VCC Power Other AG1 TRST TAP Input AH10 VSS Power Other AG2 BPM3 Common Clock Input Output AH11 VCC Power Other AG3 BPM5 Common Clock Input Output AH12 VCC Power Other AG4 A30 Source Synch Input Output AH13 VSS Power Other AG5 A31 Source Synch _ Input Output AH14 VCC Power Other AG6 A29 Source Synch Input Output AH15 VCC Power Other AG7 VSS Power Other AH16 VSS Power Other AG8 amp VCC Power Other AH17 VSS Power Other AG9 VCC Power Other AH18 VCC Power Other AG10 VSS Power Other AH19 VCC Power Other AG11 VCC Power O
78. e that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides 8 101 n t el Debug Tools Specifications 102 Datasheet
79. ec vee vec vec vec vec vec Fea FCM vec H psEui rci5 vss vss vss vss vss vss vss vss vss vss vss vss FC33 FC32 G BSEL2 BsELo BCLK1 rEsTHM TESTHIS TESTHI3 TESTHIG RESET D47 D44 DSTBN2 DSTBP2 D35 D36 D32 D31 F RSVD BCLKO VTT_SEL TESTHIO TESTHI2 TESTHI7 RSVD vss D43 D41 vss D38 D37 vss D30 E Fc26 vss vss vss vss FC10 RSVD D45 amp D42 vss D40 D39 vss D34 D33 D wr VIT wt VTT vm vr vss VCCPLL D46 vss pass DBI2 vss pao RSVD vss c vi vit vm vr wt vit vss n vss D58 amp DBI3 vss D54 DSTBP3R vss D51 B VIT VIT VIT VIT vr vr vss vss pest pss vss poo D57 vss D55 D53 vr vit vr wt vr vr F3 VCCA D62 vss rsvp pew vss D56 amp DSTBN3 VSS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 44 Datasheet Land Listing and Signal Descriptions Figure 13 land out Diagram Top View Right Side 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VID SEL VSS MB RE vcc MB vss vcc VOG j TXSS MOG wees i ss m Nee ECT GULATION REGULATION SENSE SENSE m vee vec vss vcc vcc vss VCC vec VID7 FC40 VID6 VSS VID2 VIDO VSS vec vss vcc vcc vss VCC VCC VSS VID3 VID
80. ed specifications Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor number for details PIntel 64 requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 Processor will not operate including 32 bit operation without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations See http developer intel com technology intel64 for more information including details on which processors support Intel 64 or consult with your system vendor for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Intel virtualization Technology requires a computer system with a processor chipset BIOS virtual machine m
81. emes 87 2 1 Normal State ya M undone rinso EEE ERO E A E E EA Aei 88 6 2 2 HALT and Extended HALT Powerdown States r 88 6 2 2 1 HALT Powerdown Stat ex u riren nena enn hein aa nin er xa na ea pia aa 88 6 2 2 2 Extended HALT Powerdown State r 89 6 2 3 Stop Grant and Extended Stop Grant States r 89 6 2 3 1 Stop Grant State i i eiecit anre nena casa wakpa waq payaa seeder akaw makas 89 6 2 3 2 Extended Stop Grant State ua aswaa ssssarasssssa qas nennen 90 6 2 4 Extended HALT Snoop State HALT Snoop State Extended Stop Grant Snoop State and Stop Grant Snoop State 6 2 4 1 HALT Snoop State Stop Grant Snoop State 6 2 4 2 Extended HALT Snoop State Extended Stop Grant Snoop State 6 2 5 Sleep State uuu a iiie aaa decia akaqa qasay ds PU saga iso pda da ERR walau 6 2 6 Deep Sleep State rere te eres pb uwa Esso reseipe ima d an apasqa huwa 6 2 7 Deeper Sleep State a sasaw asha nh kan haha AR ankas ERR NAR Ra REX Eaa aiiin 91 6 2 8 Enhanced Intel SpeedStep Technology MS 92 6 3 Processor Power Status Indicator PSI Signal este eee eee mmn 92 7 Boxed Processor Specifications rr eee eee eee eee ea nnns 93 ri INtrOMUCHON Em 93 7 2 Mechanical Specifications iuis ce outer eese suse pne ten NND gea ev da RR PARA REN D
82. en drain type pulse width modulated 3 Fan will have pull up resistor for this signal to maximum of 5 25 V Datasheet m Boxed Processor Specifications n t el Figure 25 Baseboard Power Header Placement Relative to Processor Socket R110 4 33 ue 7 4 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor 7 4 1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink However meeting the processor s temperature specification is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is provided in Chapter 5 The boxed processor fan heatsink is able to keep the processor temperature within the specifications see Table 27 in chassis that provide good thermal management For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life Figure 26 and Figure 27 illustrate an acceptable airspace clearance for the fan heatsink The air temperature enteri
83. eported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT see Section 5 2 Systems that implement fan speed control must be designed to take these conditions in to account Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications To determine a processor s case temperature specification based on the thermal profile it is necessary to accurately measure processor power dissipation Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 for the details of this methodology 77 Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 27 instead of the maximum processor power consumption The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time For more details on the usage of this feature refer to Sect
84. ese pins is determined by the VID 7 0 pins VCCA provides isolated power for internal PLLs on previous VCCA Input generation processors It may be left as a No Connect on boards supporting the processor VCCIOPLL provides isolated power for internal processor FSB PLLs VCCIOPLL Input on previous generation processors It may be left as a No Connect on boards supporting the processor VCCPLL Input VCCPLL provides isolated power for internal processor FSB PLLs VCC_SENSE is an isolated low impedance connection to processor VCC_SENSE Output core power Vcc It can be used to sense or measure voltage near the silicon with little noise This land is provided as a voltage regulator feedback sense point for Vcc It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator Design Guide VCC_MB_ REGULATION Output 74 Datasheet Table 26 75 intel Land Listing and Signal Descriptions Signal Description Sheet 10 of 10 Name Type Description VID 7 0 Output The VID Voltage ID signals are used to support automatic selection of power supply voltages Vcc Refer to the Voltage Regulator Design Guide for more information The voltage supply for these signals must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID signals becomes valid
85. etention mechanism that is independent of the socket FSB Front Side Bus The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Datasheet Introduction Datasheet intel Storage conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Functional operation Refers to normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied Execute Disable Bit Execute Disable Bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and
86. event occurs When the processor exits the Extended Stop Grant state it will resume operation at the lower frequency transition the VID to the original value and then change the bus ratio back to the original value Extended HALT Snoop State HALT Snoop State Extended Stop Grant Snoop State and Stop Grant Snoop State The Extended HALT Snoop State is used in conjunction with the Extended HALT state If Extended HALT state is not enabled in the BIOS the default Snoop State entered will be the HALT Snoop State Refer to the sections below for details on HALT Snoop State Stop Grant Snoop State Extended HALT Snoop State Extended Stop Grant Snoop State HALT Snoop State Stop Grant Snoop State The processor will respond to snoop transactions on the FSB while in Stop Grant state or in HALT powerdown state During a snoop transaction the processor enters the HALT Snoop State Stop Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB After the snoop is serviced the processor will return to the Stop Grant state or HALT powerdown state as appropriate Extended HALT Snoop State Extended Stop Grant Snoop State The processor will remain in the lower bus ratio and VID operating point of the Extended HALT state or Extended Stop Grant state While in the Extended HALT Snoop State or Extended Stop Grant Snoop State snoops are handled the same
87. g surface for thermal and mechanical solution The minimum loading specification must be maintained by any thermal and mechanical solutions Processor Loading Specifications Parameter Minimum Maximum Notes Static 80 N 17 Ibf 311 N 70 Ibf 1 2 3 Dynamic 756 N 170 Ibf 1 3 4 NOTES 1 These specifications apply to uniform compressive loading in a direction normal to the processor IHS 2 This is the maximum force that can be applied by a heatsink retention clip The clip must also provide the minimum specified load on the processor package 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement Package Handling Guidelines Table 22 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Notes Shear 311 N 70 Ibf 1 4 Tensile 111 N 25 Ibf 2 4 Torque 3 95 N m 35 Ibf in 3 4 NOTES 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 A tensile load is defined as a pulling load applied to
88. ge supply for some signals that require termination to Vtr on the motherboard VTT SEL Output The VTT SEL signal is used to select the correct Vr voltage level for the processor This land is connected internally in the package to Vss Datasheet 76 Land Listing and Signal Descriptions Datasheet m e Thermal Specifications and Design Considerations n t el 5 5 1 Note 5 1 1 Datasheet Thermal Specifications and Design Considerations Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5 1 1 Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete thermal solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting For more information on designing a component level thermal solution refer to the appropriate Thermal and Mechan
89. gs cesses 17 2 6 2 DC Voltage and Current Specification rr 18 2 6 3 NCC OVershoot uuu asus vii cewes va saxa sue ger FEREXERE PER AAE RUE ROREM RE REOERA APO EVER 23 2 6 4 Die Voltage Validation wiv 24 2 7 Signaling Specifications eiie reser engin aa aa gea ER ge aa es gen evade FEAR DETEN 24 2 7 1 FSB Signal GroupS win ies eene eor cesthen sadness sedate rgben tas anise mechs thai ned ARRA R ARENA Mm Une Si 25 2 7 2 CMOS and Open Drain Signals ccceceeeee ee eee eee eee eee ee eaten eee eee 26 2 7 3 Processor DC Specifications uu u usa asqa penas negari ku a Eua ka RR a Ra aa xy misa 27 2 7 3 1 Platform Environment Control Interface PECI DC Specifications 29 2 7 3 2 GTL Front Side Bus Specifications a 30 2 8 Clock Specifications iuter aes eaae errore seque eda axe nisu meat edat nC ut a RICE E RE REGE as 31 2 8 1 Front Side Bus Clock BCLK 1 0 and Processor Clocking reo even 31 2 8 2 FSB Frequency Select Signals BSEL 2 0 r 32 2 8 3 Phase Lock Loop PLL and Filter esses 32 2 8 4 BCLK 1 0 Specifications ceci rosis oe core ren nce re Ink DURS E cR kam ORE aM E DENM MUS 32 3 Package Mechanical Specifications rr 35 3 1 Package Mechanical DraWing u a ua etina asas hannah naui nnne sana ha nana su un 35 3 2 Processor Com
90. her VSS P25 Power Other VSS MB REGULATION AN6 Power Other Output VSS P26 Power Other VSS SENSE ANA Power Other Output VSS P27 Power Other VSSA B23 Power Other VSS P28 Power Other VTT B25 Power Other VSS P29 Power Other VTT B26 Power Other VSS P30 Power Other VTT B27 Power Other VSS P4 Power Other VTT B28 Power Other VSS P7 Power Other VTT B29 Power Other VSS R2 Power Other VTT B30 Power Other VSS R23 Power Other VTT A25 Power Other VSS R24 Power Other VTT A26 Power Other VSS R25 Power Other VTT A27 Power Other VSS R26 Power Other VTT A28 Power Other VSS R27 Power Other VTT A29 Power Other VSS R28 Power Other VTT A30 Power Other VSS R29 Power Other VTT C25 Power Other VSS R30 Power Other VTT C26 Power Other VSS R5 Power Other VTT C27 Power Other VSS R7 Power Other VTT C28 Power Other VSS T3 Power Other VTT C29 Power Other VSS T6 Power Other VTT C30 Power Other VSS T7 Power Other VTT D25 Power Other VSS U7 Power Other VTT D26 Power Other VSS V23 Power Other VTT D27 Power Other VSS V24 Power Other VTT D28 Power Other VSS V25 Power Other VTT D29 Power Other VSS V26 Power Other VTT D30 Power Other VSS V27 Power Other VTT_OUT_LEFT Ji Power Other Output VSS V28 Power Other VTT_OUT_RIG vss V29 Power Other Tur AA1 Power Other Output VSS v3 Power Other VIT SEL F27 Power Other Output VSS v30 Power Other VSS V6 Power Other VSS V7 Power Other VSS W4 Power Other Datasheet 55 intel Land Listi
91. her AE14 VCC Power Other AC8 VCC Power Other AE15 VCC Power Other AC23 VCC Power Other AE16 VSS Power Other AC24 VCC Power Other AE17 VSS Power Other AC25 vcc Power Other AE18 VCC Power Other AC26 VCC Power Other AE19 VCC Power Other AC27 VCC Power Other AE20 VSS Power Other AC28 VCC Power Other AE21 VCC Power Other AC29 VEC Power Other AE22 VCC Power Other AC30 VCC Power Other AE23 VCC Power Other AD1 TDI TAP Input AE24 VSS Power Other AD2 BPM2 Common Clock Input Output AE25 VSS Power Other AD3 FC36 Power Other AE26 VSS Power Other AD4 VSS Power Other AE27 VSS Power Other AD5 ADSTB1 Source Synch _ Input Output AE28 VSS Power Other AD6 A22 Source Synch Input Output AE29 VSS Power Other AD7 VSS Power Other AE30 VSS Power Other AD8 VCC Power Other AF1 TDO TAP Output AD23 VCC Power Other AF2 BPM4 Common Clock Input Output AD24 VCC Power Other AF3 VSS Power Other AD25 VCC Power Other AF4 A28 Source Synch _ Input Output AD26 VCC Power Other AF5 A27 Source Synch Input Output AD27 vcc Power Other AF6 VSS Power Other AD28 VCC Power Other AF7 VSS Power Other AD29 VCC Power Other AF8 VCC Power Other AD30 Vcc Power Other AF9 VCC Power Other 62 Datasheet Land Listing and Signal Descriptions Datasheet intel Table 25 Numerical Land Table 25 Numerical Land Assignment Assignment Land Land Nam
92. her RESERVED D16 FC36 AD3 Power Other RESERVED E23 FC37 AB3 Power Other RESERVED E6 FC38 G10 Power Other RESERVED E7 FC39 AA2 Power Other RESERVED F23 FC40 AM6 Power Other RESERVED F29 FC41 C9 Power Other RESERVED G6 FERR PBE R3 Asynch CMOS Output RESERVED N4 GTLREF0 H1 Power Other Input RESERVED N5 GTLREF1 H2 Power Other Input RESERVED P5 HIT D4 Common Clock Input Output RESET G23 Common Clock Input HITM E4 Common Clock Input Output RSO B3 Common Clock Input IERR AB2 Asynch CMOS Output RS1 F5 Common Clock Input IGNNE N2 Asynch CMOS Input RS2 A3 Common Clock Input INIT P3 Asynch CMOS Input SKTOCC AE8 Power Other Output ITP_CLKO AK3 TAP Input SLP L2 Asynch CMOS Input ITP_CLK1 AJ3 TAP Input SMI P2 Asynch CMOS Input LINTO K1 Asynch CMOS Input STPCLK M3 Asynch CMOS Input LINT1 L1 Asynch CMOS Input TCK AE1 TAP Input LOCK C3 Common Clock Input Output TDI AD1 TAP Input MSIDO wi Power Other Output TDO AF1 TAP Output MSID1 Vi Power Other Output TESTHIO F26 Power Other Input PECI G5 Power Other Input Output TESTHI1 w3 Power Other Input PROCHOT AL2 Asynch CMOS Input Output TESTHI10 H5 Power Other Input PSI Y3 Asynch CMOS Output d w2 Power Other Input PWRGOOD N1 Power Other Input TESTHI2 F25 Power Other Input REQO K4 Source Synch Input Output TESTHI3 G25 Power Other Input REQ1 J5 Source Synch Input Output TESTHI4 G27 Power Other Input REQ2 M6 Source Synch Input Output TESTHI5 G26 Power
93. her VCC ws Power Other Vcc N23 Power Other VCC Y23 Power Other Vcc N24 Power Other VCC Y24 Power Other VCC N25 Power Other VCC Y25 Power Other VCC N26 Power Other VCC Y26 Power Other VCC N27 Power Other VCC Y27 Power Other VCC N28 Power Other VCC Y28 Power Other Vcc N29 Power Other VCC Y29 Power Other Vcc N30 Power Other VCC Y30 Power Other Vcc N8 Power Other VCC Y8 Power Other aa rr RECULANION AN5 Power Other Output VEE 75 Power Other VCC SENSE AN3 Power Other Output WES F Power Other VCCA A23 Power Other WEG TE PoWer Other VCCIOPLL C23 Power Other T7 Tun Power Other VCCPLL D23 Power Other VID SELECT AN7 Power Other Output 51 52 intel Land Listing and Signal Descriptions Table 24 Alphabetical Land Table 24 Alphabetical Land Assignments Assignments Land Name sare ici oc d Direction Land Name e Tet Direction VIDO AM2 Asynch CMOS Output VSS AB26 Power Other VID1 ALS Asynch CMOS Output VSS AB27 Power Other VID2 AM3 Asynch CMOS Output VSS AB28 Power Other VID3 AL6 Asynch CMOS Output VSS AB29 Power Other VID4 AK4 Asynch CMOS Output VSS AB30 Power Other VID5 AL4 Asynch CMOS Output VSS AB7 Power Other VID6 AM5 Asynch CMOS Output VSS AC3 Power Other VID7 AM7 Asynch CMOS Output VSS AC6 Power Other VRDSEL AL3 Power Other VSS AC7 Power Other VSS B1 Power O
94. hermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and in some cases may result in a Tc that exceeds the specified maximum temperature and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Thermal Monitor 2 The processor also supports an additional power reduction capability known as Thermal Monitor 2 This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor When Thermal Monitor 2 is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated The TCC causes the processor to adjust its operating frequency using the bus multiplier and input voltage using the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption A processor enabled for Thermal M
95. ical Design Guidelines see Section 1 2 The boxed processor will ship with a component thermal solution Refer to Chapter 7 for details on the boxed processor Thermal Specifications To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature Tc specifications when operating at or below the Thermal Design Power TDP value listed per frequency in Table 27 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Platform Environment Control Interface PECI bus as described in Section 5 3 If the value reported using PECI is less than Tcowrao then the case temperature is permitted to exceed the Thermal Profile If the value reported using PECI is greater than or equal to TcontroL then the processor case temperature must remain at or below the temperature as specified by the thermal profile The temperature r
96. ications in Table 7 when measured across the VCC SENSE and VSS SENSE lands Overshoot events that are lt 10 ns in duration may be ignored These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic GTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates Platforms implement a termination voltage level for GTL signals defined as V m Because platforms implement separate power planes for each processor and chipset separate Vcc and V supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families The GTL inputs require a reference voltage GTLREF which is used by the receivers to determine if a signal is a logical O or a logical 1 GTLREF must be generated on the motherboard see Table 15 for GTLREF specifications Termination resistors R77 for GTL signals are provided on the processor silicon and are terminated to Vy Intel chipsets will also provide on die termination thus eliminating the need to terminate the bus on the
97. ill operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertion of the RESET signal de assertion of SLP and removal of the BCLK input while in Sleep state If SLP is de asserted the processor exits Sleep state and returns to Extended Stop Grant or Stop Grant state restarting its internal clock signals to the bus and processor core units If DPSLP is asserted while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state Use of the SLP pin and corresponding low power state requires chipset support and may not be available on all platforms NOTE Some processors may not have the Sleep State enabled refer to the Specification Update for specific processor and stepping guidance SMI Input SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the de assertion of RESET the processor will tri state its outputs STPCLK TCK Input Input STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to al
98. ion that logical processor is halted however the other processor continues normal operation The Extended HALT powerdown state must be enabled using the BIOS for the processor to remain within its specification The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor will first switch to the lower bus ratio and then transition to the lower VID While in Extended HALT state the processor will process bus snoops The processor exits the Extended HALT state when a break event occurs When the processor exits the Extended HALT state it will resume operation at the lower frequency transition the VID to the original value and then change the bus ratio back to the original value Stop Grant and Extended Stop Grant States The processor supports the Stop Grant and Extended Stop Grant states The Extended Stop Grant state is a feature that must be configured and enabled using the BIOS Refer to the sections below for details about the Stop Grant and Extended Stop Grant states Stop Grant State When the STPCLK signal is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Since the GTL signals receive power f
99. ion 5 2 In all cases the Thermal Monitor or Thermal Monitor 2 feature must be enabled for the processor to remain within specification Table 27 Processor Thermal Specifications Thermal Extended Deeper Processor Core Design HALT Sleep 775_VR_ Minimum Maximum Frequency CONFIG 06 Notes Number GHz Power Power Power Guidance Tc C Tc C w 4 w w E8600 3 33 65 0 8 6 5 E8500 3 16 65 0 8 6 5 See 775 MR E8400 3 65 0 8 6 CONFIG 06 5 Table 28 E8300 2 83 65 0 8 6 65 W 5 and E8200 2 66 65 0 8 6 5 Figure 14 E8190 2 66 65 0 8 6 5 E7600 3 06 GHz 65 0 8 6 5 See E7500 2 93 65 0 8 6 775 VR CONFIG 5 Table 29 E7400 2 80 65 0 8 6 _06 5 and E7300 2 66 65 0 8 6 65 W 5 Figure 15 E7200 2 53 65 0 8 6 5 9 NOTES 1 Specification is at 36 C Tc and minimum voltage loadline Specification is ensured by design characterization and not 100 tested 25 Specification is at 34 C Tc and minimum voltage loadline Specification is ensured by design characterization and not 100 tested 3 Thermal Design Power TDP should be used for processor thermal solution design targets The TDP is not the maximum power that the processor can dissipate 4 This table shows the maximum TDP for a given frequency range Individual processors may have a lower TDP Therefore the maximum Tc will vary depending on the TDP of the individual processor Refer to thermal profile figure and associated table for the allowed com
100. iption Sheet 4 of 10 Name Type Description DEFER is asserted by an agent to indicate that a transaction cannot be ensured in order completion Assertion of DEFER is DEFER Input normally the responsibility of the addressed memory or input output agent This signal must connect the appropriate pins lands of all processor FSB agents DPRSTP when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep state To return to the Deep Sleep State DPRSTP must be de asserted Use of the DPRSTP pin and corresponding low power state requires chipset support and may not be available on all platforms NOTE Some processors may not have the Deeper Sleep State enabled refer to the Specification Update for specific sku and stepping guidance DPRSTP Input DPSLP when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state To return to the Sleep State DPSLP must be de asserted Use of the DPSLP pin and corresponding low power state requires chipset support and may not be available on all platforms NOTE Some processors may not have the Deep Sleep State enabled refer to the Specification Update for specific processor and stepping guidance DPSLP Input DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY
101. l boxed processors are intended for system integrators who build systems from baseboards and standard components The boxed processor will be supplied with a cooling solution This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor This chapter is particularly important for OEMs that manufacture baseboards for system integrators Unless otherwise noted all figures in this chapter are dimensioned in millimeters and inches in brackets Figure 20 shows a mechanical representation of a boxed processor Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designers responsibility to consider their proprietary cooling solution when designing to the required keep out zone on their system platforms and chassis Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 for further guidance Contact your local Intel Sales Representative for this document Mechanical Representation of the Boxed Processor NOTE The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink 93 m n t el Boxed Processor Specifications 7 2 Mechanical Specifications 7 2 1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specificatio
102. l control circuit TCC activation as indicated by PROCHOT assertions As the temperature approaches TCC activation the PECI value approaches zero TCC activates at a PECI count of zero Conceptual Fan Control Diagram on PECI Based Platforms TcoNTRoL TCC Activation Setting Temperature I Max PECI 0 Fan Speed RPM Temperature not intended to depict actual implementation 85 im e n tel Thermal Specifications and Design Considerations 5 3 2 5 3 2 1 5 3 2 2 5 3 2 3 5 3 2 4 Table 30 86 PECI Specifications PECI Device Address The PECI register resides at address 30h PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification Refer to this document for details on supported PECI command function and codes PECI Fault Handling Requirements PECI is largely a fault tolerant interface including noise immunity and error checking improvements over other comparable industry standard interfaces The PECI client is as reliable as the device that it is embedded in and thus given operating conditions that fall under the specification the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures There are however certain scenarios where the PECI is know to be unresponsive Prior to a power on RESET and during RESET assertion PECI is not assured to provide re
103. l processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is de asserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI Input TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO Output TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TESTHI 12 10 0 Input The TESTHI 12 10 0 lands must be connected to the processor s appropriate power source refer to VIT OUT LEFT and VTT OUT RIGHT signal description through a resistor for proper processor operation See Section 2 4 for more details Datasheet 73 m e n tel Land Listing and Signal Descriptions Table 26 Signal Description Sheet 9 of 10 Name Type Description In the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature approximately 20 C above the maximum Ty Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature h
104. liable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available using PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host controller should take action to protect the system from possible damage It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive GetTemp s or for a one second time interval The host controller may also implement an alert to software in the event of a critical or continuous fault condition PECI GetTempO Error Code Support The error codes supported for the processor GetTemp command are listed in Table 30 GetTempO Error Codes Error Code Description 8000h General sensor error Sensor is operational but has detected a temperature below its operational 8002h range underflow ss Datasheet Features 6 6 1 Table 31 6 2 Datasheet intel Features Power On Configuration Options Several configuration options can be configured by hardware The processor samples the hardware configuration at reset on the active to inactive transition of RESET For specifications on these options refer to Table 31 The sampled information configures the processor for s
105. loscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe Refer to Table 5 Figure 1 Table 6 and Figure 2 for the minimum typical and maximum Vcc allowed for a given current The processor should not be subjected to any Vcc and Icc combination wherein Vcc exceeds Vcc max for a given current Icc max Specification is based on Vcc max loadline Refer to Figure 1 for details Vr must be provided using a separate voltage source and not be connected to Vec This specification is measured at the land Baseboard bandwidth is limited to 20 MHz This is the maximum total current drawn from the V plane by only the processor This specification does not include the current coming from on board termination Rrr through the signal line Refer to the Voltage Regulator Design Guide to determine the total Irr drawn by the system This parameter is based on design characterization and is not tested Adherence to the voltage specifications for the processor are required to ensure reliable processor operation 19 intel Table 5 20 Electrical Specifications Intel Core 2 Duo Processor E8000 Series Vcc Static and Transient Tolerance Voltage Deviation from VID Setting V gt 3 4 Icc A Maximum Voltage
106. may be de asserted to insert idle clocks This signal must connect the appropriate pins lands of all processor FSB agents Input DREDY Output DSTBN 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBNO DSTBN 3 0 ae 15 0 utput pr31 16 4 DBI1 DSTBN1 D 47 32 DBI2 DSTBN2 D 63 48 DBI3 DSTBN3 DSTBP 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBPO DSTBP 3 0 en 45 0 utput pr31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48 DBI3 DSTBP3 FCO BOOTSELECT is not used by the processor When this land is FCO BOOTSELECT Other tied to Vas previous processors based on the Intel NetBurst microarchitecture should be disabled and prevented from booting FC signals are signals that are available for compatibility with other FCx Other processors Datasheet 69 intel Land Listing and Signal Descriptions Table 26 Signal Description Sheet 5 of 10 Name Type Description FERR PBE Output FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 c
107. meframe defined in Table 11 Datasheet m e Thermal Specifications and Design Considerations n t el 5 3 5 3 1 5 3 1 1 Figure 18 Datasheet Platform Environment Control Interface PECI Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components It uses a single wire thus alleviating routing congestion issues PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices Also data transfer speeds across the PECI interface are negotiable within a wide range 2 Kbps to 2 Mbps The PECI interface on the processor is disabled by default and must be enabled through BIOS More information can be found in the Platform Environment Control Interface PECI Specification TcoNTRoL and TCC activation on PECI Based Systems Fan speed control solutions based on PECI utilize a TcontroL Value stored in the processor IA32 TEMPERATURE TARGET MSR The TcowrRo MSR uses the same offset temperature format as PECI though it contains no sign bit Thermal management devices should infer the Tcowrao Value as negative Thermal management algorithms should utilize the relative temperature value delivered over PECI in conjunction with the TcontroL MSR value to control or optimize fan speeds Figure 18 shows a conceptual fan control diagram using PECI temperatures The relative temperature value reported over PECI represents the delta below the onset of therma
108. minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes 2 Vec Core voltage with respect to Vss 0 3 1 45 V FSB termination voltage with Vit respect to Vss 0 3 1 45 V See See TcASE Processor case temperature Section 5 Section 5 C TsrORAGE Processor storage temperature 40 85 C 3 4 5 NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation refer to the processor case temperature specifications 4 This rating applies to
109. n The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 4 Failure to do so can result in timing violations or reduced lifetime of the component Vcc Decoupling Vcc regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications This includes bulk capacitance with low effective series resistance ESR to keep the voltage rail within specifications during large swings in load current In addition ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity Consult the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further information Contact your Intel field representative for additional information Vr Decoupling Decoupling must be provided on the motherboard Decoupling solutions must be sized to meet the expected load To ensure compliance with the specifications various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors 13 m e n tel Electrical Specifications 2 2 3 Note 14 FSB Decoupling The processor integrates signal termin
110. nal Descriptions Signal Description Sheet 7 of 10 Name Type Description PWRGOOD Input PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 Input Output REQ 4 0 Request Command must connect the appropriate pins lands of all processor FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTBO RESET Input Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after Vcc and BCLK have reached their proper specifications On observing active RESE
111. nch CMOS Output F21 D43 Source Synch _ Input Output G30 BSEL2 Asynch CMOS Output F22 VSS Power Other H1 GTLREFO Power Other Input F23 RESERVED H2 GTLREF1 Power Other Input F24 TESTHI7 Power Other Input H3 VSS Power Other F25 TESTHI2 Power Other Input H4 FC35 Power Other F26 TESTHIO Power Other Input H5 TESTHI10 Power Other Input F27 VTT SEL Power Other Output H6 VSS Power Other F28 BCLKO Clock Input H7 VSS Power Other F29 RESERVED H8 VSS Power Other G1 FC27 Power Other H9 VSS Power Other G2 COMP2 Power Other Input H10 VSS Power Other G3 ee Power Other Input H11 VSS Power Other H12 VSS Power Other G4 TESTES Power Other Input H13 VSS Power Other G5 PECI Power Other Input Output H14 VSS Power Other G6 RESERVED H15 FC32 Power Other G7 DEFER Common Clock Input H16 FC33 Power Other G8 BPRI Common Clock Input H17 VSS Power Other G9 D164 Source Synch Input Output H18 VSS Power Other G10 FC38 Power Other H19 VSS Power Other G11 DBI1 Source Synch Input Output H20 VSS Power Other G12 DSTBN1 Source Synch Input Output H21 VSS Power Other G13 D27 Source Synch _ Input Output H22 VSS Power Other G14 D29 Source Synch Input Output H23 VSS Power Other G15 D31 Source Synch Input Output H24 VSS Power Other G16 D32 Source Synch _ Input Output H25 VSS Power Other G17 D36 Source Synch Input Output H26 VSS Power Other G18 D35 Source Synch Input Output H27 VSS Power Other G19 DSTBP2 Source Synch Input Output H28 VSS Power Other Datasheet
112. nd plugs into a 775 land surface mount Land Grid Array LGA socket referred to as the LGA775 socket The processors are based on 45 nm process technology The processors feature the Intel Advanced Smart Cache a shared multi core optimized cache that significantly reduces latency to frequently used data The Intel Core 2 Duo processor E8000 series features a 1333 MHz front side bus FSB and 6 MB of L2 cache The Intel Core 2 Duo processor E7000 series features a 1333 MHz and 1066 MHz front side bus FSB and 3 MB of L2 cache The processors support all the existing Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 Supplemental Streaming SIMD Extension 3 SSSE3 and the Streaming SIMD Extensions 4 1 SSE4 1 The processors support several Advanced Technologies Execute Disable Bit Intel 64 architecture and Enhanced Intel SpeedStep Technology The Intel Core 2 Duo processor E8600 E8500 E8400 E8300 and E8200 support Intel Trusted Execution Technology Intel TXT and Intel Virtualization Technology Intel VT The Intel Core 2 Duo processor E7600 supports Intel Virtualization Technology Intel VT The processor s front side bus FSB use a split transaction deferred reply protocol The FSB uses Source Synchronous Transfer of address and data to improve performance by transferring data four times per bus clock 4X data transfer rate Along with the 4X data bus the address bus can deliver addresses two times per
113. ng and Signal Descriptions Table 25 Numerical Land Table 25 Numerical Land Assignment Assignment Land Land Name Mi ii Direction Land Land Name ls dd Direction A2 VSS Power Other Bil VSS Power Other A3 RS2 Common Clock Input B12 D13 Source Synch _ Input Output A4 DO2 Source Synch _ Input Output B13 COMP8 Power Other Input A5 DO4 Source Synch _ Input Output B14 VSS Power Other A6 VSS Power Other B15 D53 Source Synch _ Input Output A7 DO7 Source Synch _ Input Output B16 D55 Source Synch Input Output A8 DBIO Source Synch Input Output B17 VSS Power Other A9 VSS Power Other B18 D57 Source Synch Input Output A10 DO8 Source Synch _ Input Output B19 D60 Source Synch _ Input Output A11 DO9 Source Synch _ Input Output B20 VSS Power Other A12 VSS Power Other B21 D59 Source Synch _ Input Output A13 COMPO Power Other Input B22 D63 Source Synch Input Output A14 D50 Source Synch Input Output B23 VSSA Power Other A15 VSS Power Other B24 VSS Power Other A16 DSTBN3 Source Synch Input Output B25 VTT Power Other A17 D56 Source Synch _ Input Output B26 VIT Power Other A18 VSS Power Other B27 VTT Power Other A19 D61 Source Synch _ Input Output B28 VIT Power Other A20 RESERVED B29 VTT Power Other A21 VSS Power Other B30 VTT Power Other A22 D62 Source Synch _ Input Output Ci DRDY Common Clock Input Ou
114. ng the fan should be kept below 38 9C Again meeting the processor s temperature specification is the responsibility of the system integrator Datasheet 97 B n tel Boxed Processor Specifications Figure 26 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 1 view Figure 27 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 2 view 81 3 3 2 98 Datasheet e Boxed Processor Specifications n t e 7 4 2 Variable Speed Fan If the boxed processor fan heatsink 4 pin connector is connected to a 3 pin motherboard header it will operate as follows The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures This allows the processor fan to operate at a lower speed and noise level while internal chassis temperatures are low If internal chassis temperature increases beyond a lower set point the fan speed will rise linearly with the internal temperature until the higher set point is reached At that point the fan speed is at its maximum As fan speed increases so does fan noise levels Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point These set points represented in Figure 28 and Table 33 can vary by a few degrees from fan heatsink to fan heatsink The internal chassis temperature should be kept below 38 C Meeting the
115. ns of the boxed processor The boxed processor will be shipped with an unattached fan heatsink Figure 20 shows a mechanical representation of the boxed processor Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 21 Side View and Figure 22 Top View The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs Airspace requirements are shown in Figure 26 and Figure 27 Note that some figures have centerlines shown marked with alphabetic designations to clarify relative dimensioning Figure 21 Space Requirements for the Boxed Processor Side View 95 0 I _ 3 74 81 3 3 2 10 0 25 0 0 39 0 98 Figure 22 Space Requirements for the Boxed Processor Top View 95 0 lt gt 3 74 95 0 3 74 NOTES 1 Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation 94 Datasheet m e Boxed Processor Specifications n t e Figure 23 7 2 2 7 2 3 7 3 7 3 1 Datasheet Overall View Space Requirements for the Boxed Processor Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams See Chapter 5 and the appro
116. o reduce system level power consumption Systems using the processor must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the ACPI P CNT Control Register located in the processor IA32 THERM CONTROL MSR is written to a 1 the processor will immediately reduce its power consumption using modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable using bits 3 1 of the same ACPI P CNT Control Register In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On Demand mode may be used in conjunction with the Thermal Monitor If the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode 83 m e n tel Thermal Specifications and Design Considerations 5 2 4 Note 5 2 5 84 PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor core temperature has reached its maximum operating temperature If the Thermal Monitor is enabled note that the Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the
117. of the corresponding Input Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 signals All bus agents observe the ADS activation to begin protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 Input Output Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO A 35 17 ADSTB1 BCLK 1 0 Input The differential pair BCLK Bus Clock determines the FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss BNR Input Output BNR Block Next Request is used to assert a bus stall by any bus agent unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions 66 Datasheet Land Listing and Signal Descriptions intel Table 26 Signal Description Sheet 2 of 10 Name Type Description BPM 5 0 Input Output BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the p
118. on in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2008 2009 Intel Corporation All rights reserved 2 Datasheet Contents 1 Introduction uuu U as asua a ire TEE Aaaa E OITA 9 Li Terminology seems eia deseri anietivdnnd demain Rue Na EE E RR ans RR AERE RETE E nU EE DAE d DRE 10 1 1 1 Processor Terminology Definitions rr 10 1 2 References RES 12 2 Electrical Specifications deii te AREE RRA RR aT VAERI IR EU DERE RD INN MER Ennn 13 2 1 Power and Ground Lands u aa aeneus xa tutu sa sects cuideds Madness talks aga ate EEE 13 2 2 Decoupling G id elines u etui urit etant gamed tak quqa e x rag ida xa quae sx Sa dera E a pn 13 2 2 1 VEC Decoupling au uuu sapient seiten ox Ee ma xim eagle CP EAR EO RR LE Ka RES a xxt M DRM Ad 13 2 2 2 VIT Decoupling rriren ieia na E nme kinase mk gna Van Ke BA RU SEA EA mas Waq 13 2 2 3 FSB Decouplihg uiuis cams says quqa ease ntque xc dames sadi enu nice qa yanaq aq E Da E T RR dE 14 2 3 Voltage Identification oiii crine kexe sesenta ra anne AEE TOEN ANEA 14 2 4 Reserved Unused and TESTHI Signals rr 16 2 5 Power Segment Identifier ip XiXvemDAN AQIRESSAS NEA NENIUE ME PI FREE KINUPMNT IRURE UE KERN E EINER 16 2 6 Voltage and Current Specification esses menm emen 17 2 6 1 Absolute Maximum and Minimum Ratin
119. onitor VMM and for some uses certain platform software enabled for it Functionality performance or other benefit will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor See the Processor Spec Finder or contact your Intel representative for more information No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific software for some uses For more information see here Not all specified units of this processor support Thermal Monitor 2 Enhanced HALT State and Enhanced Intel SpeedStep Technology See the Processor Spec Finder at http processorfinder intel com or contact your Intel representative for more information Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Intel Pentium Intel Core Intel SpeedStep and the Intel logo are trademarks of Intel Corporati
120. onitor 2 includes two operating points each consisting of a specific operating frequency and voltage The first operating point represents the normal operating condition for the processor Under this condition the core frequency to FSB multiple used by the processor is that contained in the CLK GEYSIII STAT MSR and the VID is that specified in Table 4 These parameters represent normal system operation The second operating point consists of both a lower operating frequency and voltage When the TCC is activated the processor automatically transitions to the new frequency This transition occurs very rapidly on the order of 5 us During the frequency transition the processor is unable to service any bus requests and consequently all bus traffic is blocked Edge triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2 During the voltage change it will be necessary to transition through multiple VID codes to reach the target operating voltage Each step will likely be one VID table entry see Table 4 The processor continues to execute instructions during the voltage transition Operation at the lower voltage reduces the power consumption of
121. oprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to volume 3 of the Intel Architecture Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note GTLREF 1 0 Input GTLREF 1 0 determine the signal reference level for GTL input signals GTLREF is used by the GTL receivers to determine if a signal is a logical 0 or logical 1 HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR Output IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep
122. ower Other VSS D5 Power Other VSS H7 Power Other vss D6 Power Other VSS H8 Power Other VSS D9 Power Other VSS H9 Power Other VSS E11 Power Other VSS J4 Power Other VSS E14 Power Other VSS J7 Power Other VSS E17 Power Other VSS K2 Power Other VSS E2 Power Other VSS K5 Power Other VSS E20 Power Other VSS K7 Power Other VSS E25 Power Other VSS L23 Power Other VSS E26 Power Other VSS L24 Power Other VSS E27 Power Other VSS L25 Power Other VSS E28 Power Other VSS L26 Power Other VSS E8 Power Other VSS L27 Power Other VSS F10 Power Other VSS L28 Power Other VSS F13 Power Other VSS L29 Power Other VSS F16 Power Other VSS L3 Power Other VSS F19 Power Other VSS L30 Power Other VSS F22 Power Other VSS L6 Power Other VSS F4 Power Other VSS L7 Power Other VSS F7 Power Other VSS M1 Power Other VSS H10 Power Other VSS M7 Power Other VSS Hil Power Other VSS N3 Power Other Datasheet m e Land Listing and Signal Descriptions n t el Table 24 Alphabetical Land Table 24 Alphabetical Land Assignments Assignments Land Name Land Signal Buffer Direction Land Name Land Signal Buffer Direction Type Type VSS N6 Power Other VSS W7 Power Other VSS N7 Power Other VSS Y2 Power Other VSS P23 Power Other VSS Y5 Power Other VSS P24 Power Other VSS Y7 Power Ot
123. pecifications Voltage Identification Definition Table 2 o9 in in in in in in in Ln in in in in in Ln in Ln in Ln Ln Ln in in D A In BS QN feo IN Q IN fay IS I e eo f IRN oo IN IRIN JOIN Q I IN IR Q o Q S Lo IN IN a IN Q lin lu w vlo lZ 409 ia xo OQ m Iq Jo leg W JO Q oo JO O OO JN Jat O ko WO JO Q Jo Ja O Jig S tn I in 2 fle o E I gt l2 lo e lo L 2 1 c 2 J Q JO S IA Joo Z SS JO J J I O Je I O n n c n ID JO JO S Fa o O jo o O jo o O jo o O jo o O jo o O lo o O jo o O jo o O jo o 9 jo a mum o jo Jo Jo lo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo lo Jo Jo Jo Jo Jo Jo Jo lo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo lo Jo Jo lo Jo a ga o la lo la lo la Jo Jo la lo la lo la lo la Jo la lo la lo la lo la lo la lo la lo la lo lo lo lo lo Jo Jo Ja a HA l lo lo l lo Jo la l Jo lo l lo lo l lo Jo lo lo lo Jo Jo Jo la J lo Jo la Jo Jo Jo Jo JH a EM O O JO O n n O JO JO JO m n n n O O JO JO ju O JO JO O f jH O JO jo JO m m n O JO n a EM rd rH O JO JO JO JO O JO O n n n m n n n n O JO O JO JO JO JO JO n n m m m n et et O O O O JO O O O n
124. ponent Keep Out Zones eee eee nee enne 39 3 3 Package Loading Specifications uuu uuu tices cerataetasstenviesdecsessesdatatae sa aasan as kx cu nua 39 3 4 Package Handling Guidelines osea he reni nnn netu aa su ke a nasa nana KEE NANREN 39 3 5 Package Insertion Specifications eee eee eee nemen eee 40 3 6 Processor Mass Specification ccccccccseesecseeeeseeseceeeaeeeeeeecneeseeeeeaenseceanaeeeeseaqaenenes 40 3 7 Processor Materials i e eese eene sana Randa eek en eg wesas ce sse rex ru ra we sa EENE ENEE ASEE 40 3 8 Processor Markings essesi s eee trust santo niea eran yaspa qahaq deed sage ERR EA OM as TR DARE RD saa SERERE R A 40 3 9 Processor Land Coordinates oes eee eret one nen qa esa ine n aie ative Rag n e Rie a m iu ES e 41 4 Land Listing and Signal Descriptions ssssssssssssseemHeneme 43 4 1 Processor Land AssIigniffentS uu uuu aspas duke se denied a nates aka Rada ede ga i iR EAS 43 4 2 X Alphabetical Signals Reference r ssasssssssasssnassaassaassasasssasssassasssnssaa 66 5 Thermal Specifications and Design Considerations r 77 5 1 Processor Thermal Specifications l iie siiis rinin sa ku na nana agna da daa Ra aaa aa aiu 77 5 1 1 Thermal Specifications iiie retener thee n nh math maqa supa n rh EROR x Ea aat E asa 77 5 1 2 Thermal Metrology oro rn retten tan ena ae Urn d Ran Ea EXEC R
125. priate Thermal and Mechanical Design Guidelines see Section 1 2 for details on the processor weight and heatsink requirements Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly The boxed processor thermal solution requires a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket The boxed processor will ship with the heatsink attach clip assembly Electrical Requirements Fan Heatsink Power Supply The boxed processor s fan heatsink requires a 12 V power supply A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard The power cable connector and pinout are shown in Figure 24 Baseboards must provide a matched power header to support the boxed processor Table 32 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal which is an open collector output that pulses at a rate of 2 pulses per fan revolution A baseboard pull up resistor provides Voy to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL 95 Figure 24 Table 32 96 intel Boxed Processor Specifications The boxed processor
126. pt for overshoot allowed as shown in Section 2 6 3 2 This table is intended to aid in reading discrete points on Figure 1 3 The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details 4 Adherence to this loadline specification is required to ensure reliable processor operation Datasheet Electrical Specifications intel Figure 2 Intel Core 2 Duo Processor E7000 Series Vcc Static and Transient Tolerance Icc A 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 VID 0 000 VID 0 013 4 VID 0 025 4 Vcc Maximum VID 0 038 VID 0 050 4 VID 0 063 4 VID 0 075 4 z VID 0 088 4 o VID 0 100 4 VID 0 113 4 p di VID 0 125 4 Vcc Minimum VID 0 138 4 VID 0 150 4 VID 0 163 4 VID 0 175 4 VID 0 188 NOTES 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 6 3 2 This loadline specification shows the deviation from the VID set point 3 The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from p
127. put clock frequency Table 17 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency For more information about these signals including termination recommendations refer to Section 2 8 2 COMP 3 0 COMP8 Analog COMP 3 0 and COMP8 must be terminated to Vss on the system board using precision resistors Datasheet 67 Table 26 68 intel Land Listing and Signal Descriptions Signal Description Sheet 3 of 10 Name Type Description D 63 0 Input Output D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor FSB agents and must connect the appropriate pins lands on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DBI Quad Pumped Signal Groups Data Group DSTBN DSTBP DBI D 15 0 0 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DBI signals determine the polarity of the da
128. r AL17 VSS Power Other AM26 VCC Power Other AL18 VCC Power Other AM27 VSS Power Other AL19 VCC Power Other AM28 VSS Power Other AL20 VSS Power Other AM29 VCC Power Other AL21 VCC Power Other AM30 VCC Power Other AL22 VCC Power Other AN1 vss Power Other AL23 VSS Power Other AN2 VSS Power Other AL24 VSS Power Other AN3 VCC SENSE Power Other Output AL25 VCC Power Other AN4 VSS SENSE Power Other Output n lt er AN5 RSN Power Other Output AL28 VSS Power Other AN6 AS DDR Power Other Output AL29 vcc Power Other AN7 VID SELECT Power Other Output AL30 VCC Power Other AN8 vcc Power Other AM1 VSS Power Other AN9 VCC Power Other AM10 VSS Power Other AN10 vss Power Other AM11 VCC Power Other AN11 vcc Power Other AM12 VCC Power Other AN12 vcc Power Other AM13 VSS Power Other AN13 vss Power Other AM14 VCC Power Other AN14 VCC Power Other AM15 VCC Power Other AN15 VCC Power Other AM16 VSS Power Other AN16 vss Power Other AM17 VSS Power Other AN17 vss Power Other AM18 vcc Power Other AN18 VCC Power Other AM19 VCC Power Other AN19 VCC Power Other AM2 VIDO Asynch CMOS Output AN20 vss Power Other AM3 VID2 Asynch CMOS Output AN21 VCC Power Other AM4 VSS Power Other AN22 VCC Power Other AM5 VID6 Asynch CMOS Output AN23 vss Power Other AM6 FC40 Power Other AN24 VSS Power Other AM7 VID7 Asynch CMOS Output AN25 VCC Power Other AM8 VCC Power Other AN26 VCC Power Other AM9 VCC Power Other AN27 VSS Power Other AM20 VSS Power Other AN28 VS
129. r N8 vcc Power Other R29 VSS Power Other N23 VCC Power Other R30 VSS Power Other N24 vcc Power Other T1 COMP1 Power Other Input N25 VCC Power Other T2 DPRSTP Asynch CMOS Input N26 VCC Power Other T3 VSS Power Other N27 VCC Power Other T4 A11 Source Synch Input Output N28 VCC Power Other T5 A09 Source Synch Input Output N29 VCC Power Other T6 VSS Power Other N30 VCC Power Other T7 VSS Power Other P1 DPSLP Asynch CMOS Input T8 VCC Power Other P2 SMI Asynch CMOS Input T23 VCC Power Other P3 INIT Asynch CMOS Input T24 VCC Power Other P4 VSS Power Other T25 VCC Power Other P5 RESERVED T26 VCC Power Other P6 A043 Source Synch Input Output T27 VCC Power Other P7 VSS Power Other T28 VCC Power Other P8 VCC Power Other T29 VCC Power Other P23 VSS Power Other T30 VCC Power Other P24 VSS Power Other U1 FC28 Power Other P25 VSS Power Other U2 FC29 Power Other P26 VSS Power Other U3 FC30 Power Other P27 VSS Power Other U4 A13 Source Synch _ Input Output P28 VSS Power Other U5 A12 Source Synch Input Output P29 VSS Power Other U6 A10 Source Synch Input Output P30 VSS Power Other U7 VSS Power Other R1 COMP3 Power Other Input U8 WEE Power Other R2 VSS Power Other U23 VCC Power Other R3 FERR PBE Asynch CMOS Output U24 VCC Power Other R4 A08 Source Synch Input Output U25 VCC Power Other R5 VSS Power Other U26 VCC Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel
130. rmal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor feature is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 50 Clocks often will not be off for more than 3 0 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief 81 m e n tel Thermal Specifications and Design Considerations 5 2 2 82 periods of TCC activation is expected to be so minor that it would be immeasurable An under designed t
131. rocessor VCC and VSS lands Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details 2 6 3 Vcc Overshoot The processor can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos wax Vos Max is the maximum allowable overshoot voltage The time duration of the overshoot event must not exceed Tos max Tos wax is the maximum allowable time duration above VID These specifications apply to the processor die voltage as measured across the VCC SENSE and VSS SENSE lands Table 7 Vcc Overshoot Specifications Symbol Parameter Min Max Unit Figure Notes Magnitude of V vershoot V VSS MaX agnitude of Vcc overshoot above 50 mV 3 1 VID Time duration of Vcc overshoot above Tos MAX de 25 us 3 VID NOTES 1 Adherence to these specifications is required to ensure reliable processor operation Datasheet 23 e n tel Electrical Specifications Figure 3 2 6 4 2 7 24 Vcc Overshoot Example Waveform Example Overshoot Waveform VID 0 050 Vos gt o S 9 gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID NOTES 1 Vos is measured overshoot voltage 2 Tos is measured time duration above VID Die Voltage Validation Overshoot events on processor must meet the specif
132. rocessor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins lands of all processor FSB agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processor These signals do not have on die termination Refer to Section 2 6 2 for termination requirements BPRI Input BPRI Bus Priority Request is used to arbitrate for ownership of the processor FSB It must connect the appropriate pins lands of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by de asserting BPRI BRO Input Output BRO drives the BREQO signal in the system and is used by the processor to request the bus During power on configuration this signal is sampled to determine the agent ID 0 This signal does not have on die termination and must be terminated BSEL 2 0 Output The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor in
133. rom the FSB these signals should not be driven allowing the level to return to V44 for minimum power drawn by the termination resistors in this state In addition all other input signals on the FSB should be driven to the inactive state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB see Section 6 2 4 While in the Stop Grant State SMI INIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal State Only one occurrence of each event will be recognized upon return to the Normal state 89 n tel j Features 6 2 3 2 6 2 4 6 2 4 1 6 2 4 2 6 2 5 90 While in Stop Grant state the processor will process a FSB snoop Extended Stop Grant State Extended Stop Grant is a low power state entered when the STPCLK signal is asserted and Extended Stop Grant has been enabled using the BIOS The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state When entering the low power state the processor will first switch to the lower bus ratio and then transition to the lower VID The processor exits the Extended Stop Grant state when a break
134. s vcc AL vcc vcc vss vss vcc vcc vss vss vcc vcc vss vcc vcc vss vss vcc AK vss vss vss vss vcc vcc vss vss vcc vcc vss vcc vcc vss vss vcc AJ vss vss vss vss vcc vcc vss vss vcc vcc vs vcc vcc vss vss voc AH vcc vcc vcc vec voc vec vss vss vcc vec vss vcc vcc vss vss vec AG vcc vcc vcc vcc vec vec vss vss vcc vcc vss vcc vcc vss vss vcc AF vss vss vss vss vss vss vss vss vcc vcc vss vcc vcc vss vss vcc AE vss vss vss vss vss vss vss vcc vcc vcc vss vcc vcc vss vss vcc AD vcc vcc vcc vcc voc voc vcc voc ac vcc vcc vec voc vec vec voc vec AB vss vss vss vss vss vss vss vss AA vss vss vss vss vss vss vss vss Y vec vec vec vec vec vec vec vec w vec vec vec vec vec vec vee vec vss vss vss vss vss vss vss vss vec vec vec vec vec vec voc voc vec vec vec vec vec vec voc voc R vss vss vss vss vss vss vss vss P vss vss vss vss vss vss vss vss vec vec vec vec vec vec voc vec M vec vec vec vec vec vec vee vec vss vss vss vss vss vss vss vss K vcc vec vec voc vec vcc voc vec vec vec vec vec vec vec v
135. s fanheat sink requires a constant 12 V supplied to pin 2 and does not support variable voltage control or 3 pin PWM control The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header iden tification and location should be documented in the platform documentation or on the system board itself Figure 25 shows the location of the fan power connector rela tive to the processor socket The baseboard power header should be positioned within 110 mm 4 33 inches from the center of the processor socket Boxed Processor Fan Heatsink Power Cable Connector Description GND 12V SENSE CONTROL 1 2 3 4 Straight square pin 4 pin terminal housing with polarizing ribs and friction locking ramp 0 100 pitch 0 025 square pin width Match with straight pin friction lock header on mainboard Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit Notes 12 V 12 volt fan power supply 11 4 12 12 6 V IC e Maximum fan steady state current draw 1 2 A Average fan steady state current draw d 0 5 A _ e Maximum fan start up current draw 2 2 A e Fan start up current draw maximum 1 0 Second duration pulses per SENSE SENSE frequency 2 fan 1 revolution CONTROL 21 25 28 kHz 2 3 NOTES 1 Baseboard should pull this pin up to 5 V with a resistor 2 Op
136. s the absolute value of the maximum voltage Undershoot is defined as the absolute value of the minimum voltage 5 Measurement taken from differential waveform Table 19 FSB Differential Clock Specifications 1333 MHz FSB T Parameter Min Nom Max Unit Figure Notes BCLK 1 0 Frequency 331 633 333 367 MHz u 6 T1 BCLK 1 0 Period 2 99970 3 01538 ns 4 2 T2 BCLK 1 0 Period Stability 150 ps 4 3 T5 BCLK 1 0 Rise and Fall Slew 2 5 m 8 V ns 5 4 Rate Slew Rate Matching N A N A 20 9o 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor core frequencies based on a 333 MHz BCLK 1 0 2 The period specified here is the average period A given period may vary from this specification as governed by the period stability specification T2 The Min period specification is based on 300 PPM deviation from a 3 ns period The Max period specification is based on the summation of 300 PPM deviation from a 3 ns period and a 0 5 maximum variance due to spread spectrum clocking 3 In this context period stability is defined as the worst case timing difference between successive crossover voltages In other words the largest absolute difference between adjacent clock periods must be less than the period stability 4 Slew rate is measured through the VSWING voltage range centered about differential zero Measurement taken from differential waveform 5 M
137. see Section 1 2 for guidance on how to ensure PECI thermal data is available when the Deeper Sleep State is enabled 91 n tel i Features 6 3 92 In response to entering Deeper Sleep the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID pins Unlike typical Dynamic VID changes where the steps are single VID steps the processor will perform a VID jump on the order of 100 mV To support the Deeper Sleep State the platform must use a VRD 11 1 compliant solution Enhanced Intel SpeedStep Technology The processor supports Enhanced Intel SpeedStep Technology This technology enables the processor to switch between frequency and voltage points which may result in platform power savings To support this technology the system must support dynamic VID transitions Switching between voltage frequency states is software controlled Enhanced Intel SpeedStep Technology is a technology that creates processor performance states P states P states are power consumption and capability states within the Normal state as shown in Figure 19 Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system Note th
138. sor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep technology or Extended HALT State The processor uses eight voltage identification signals VID 7 0 to support automatic selection of power supply voltages Table 2 specifies the voltage level corresponding to the state of VID 7 0 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty VID 7 0 11111110 or the voltage regulation circuit cannot supply the voltage that is requested it must disable itself The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 4 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 5 Figure 1 Table 6 and Figure 2 as measured across the VCC SENSE and VSS SENSE lands The VRM or VRD utilized must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 4 and Table 5 Refer to the Voltage Regulator Design Guide for further details Datasheet intel Electrical S
139. ta signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 Input Output DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electrically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DBI3 D 63 48 DBI2 D 47 32 DBI1 D 31 16 DBIO D 15 0 DBR Output DBR Debug Reset is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal DBSY Input Output DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is de asserted This signal must connect the appropriate pins lands on all processor FSB agents Datasheet m e Land Listing and Signal Descriptions n t el Table 26 Signal Descr
140. the IHS in a direction normal to the IHS surface 3 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization 39 m l n t el Package Mechanical Specifications 3 5 3 6 3 7 Table 23 3 8 Figure 10 40 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide Processor Mass Specification The typical mass of the processor is 21 5 g 0 76 oz This mass weight includes all the components that are included in the package Processor Materials Table 23 lists some of the package components and associated materials Processor Materials Component Material Integrated Heat Spreader Nickel Plated Copper IHS Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper Processor Markings Figure 10 shows the top side markings on the processor This diagram is to aid in the identification of the processor Processor Top Side Markings Example INTEL 06 E8500 Intel Core 2 Duo SLxxx CO9 3 16GHA 6M 1333 06 EO Datasheet intel Package Mechanical Specifications Processor Land Coordinates 3 9 Figure 11 shows the top view of the processor land coor
141. the Stop Grant state If RESET is driven active while the processor is in the Sleep state the SLP and STPCLK signals should be de asserted immediately after RESET is asserted to ensure the processor correctly executes the Reset sequence While in the Sleep state the processor is capable of entering an even lower power state the Deep Sleep state by asserting the DPSLP pin See Section Section 6 2 6 While the processor is in the Sleep state the SLP pin must be de asserted if another asynchronous FSB event needs to occur PECI is not available and will not respond while in the Sleep State Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 for guidance on how to ensure PECI thermal data is available when the Sleep State is enabled Deep Sleep State The Deep Sleep state is entered through assertion of the DPSLP pin while in the Sleep state BCLK may be stopped during the Deep Sleep state for additional platform level power savings BCLK stop restart timings on appropriate chipset based platforms with the CK505 clock chip are as follows e Deep Sleep entry the system clock chip may stop tristate BCLK within two BCLKs of DPSLP assertion It is permissible to leave BCLK running during Deep Sleep Deep Sleep exit the system clock chip must drive BCLK to differential DC levels within 2 3 ns of DPSLP de assertion and start toggling BCLK within 10 BCLK periods To re enter the Sleep state the
142. the processor and does not include any tray or packaging 5 Failure to adhere to this specification can affect the long term reliability of the processor 17 intel Electrical Specifications 2 6 2 DC Voltage and Current Specification Table 4 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 10 VID Range VID 0 8500 1 3625 V 1 Processor Number Vcc for 6 MB Cache 775 VR CONFIG 06 E8600 3 33 GHz E8500 3 16 GHz i E8400 3 GHz Refer to Table 5 Figure 1 E8300 2 83 GHz E8200 2 66 GHz Core Vcc E8190 2 66 GHz V 3 4 5 Processor Number Vcc for 3 MB Cache 775 VR CONFIG 06 E7600 3 06 GHz E7500 2 93 GHz Refer to Table 6 Figure 2 E7400 2 80 GHz E7300 2 66 GHz E7200 2 53 GHz Vcc Boor Default Vcc voltage for initial power up 1 10 V VccPLL PLL Vcc 5 1 50 5 V Product Number Icc for 6 MB Cache 775 VR CONFIG 06 E8600 3 33 GHz 75 E8500 3 16 GHz 75 x ils E8400 3 GHz B i 75 E8300 2 83 GHz 75 E8200 2 66 GHz 75 Icc E8190 2 66 GHz 75 Processor Number Vcc for 3 MB Cache 775_VR_CONFIG_06 E7600 3 06 GHz 75 E7500 2 93 GHz 75 A E7400 2 80 GHz 75 E7300 2 66 GHz 75 E7200 2 53 GHz 75 FSB termination SHANE celles 1 005 1 1 1 155 voltage Chipset family boards T W DC AC on Intel 4 series ia 1 2 1 26 specifications Chipset family boards i oo DC Current that may be drawn from VIT OUT RIGHT VTT O
143. ther AH20 VSS Power Other AG12 VCC Power Other AH21 VCC Power Other AG13 VSS Power Other AH22 Vcc Power Other AG14 VCC Power Other AH23 VSS Power Other AG15 VCC Power Other AH24 VSS Power Other AG16 VSS Power Other AH25 WCC Power Other AG17 VSS Power Other AH26 WCC Power Other AG18 VCC Power Other AH27 VCC Power Other 63 64 intel Land Listing and Signal Descriptions Table 25 Numerical Land Table 25 Numerical Land Assignment Assignment Land Land Name Mida Direction Land Land Name ds dd Direction AH28 VCC Power Other AK7 VSS Power Other AH29 VCC Power Other AK8 VCC Power Other AH30 VCC Power Other AK9 VCC Power Other AJ1 BPM1 Common Clock Input Output AK10 VSS Power Other AJ2 BPMO Common Clock Input Output AK11 VCC Power Other AJ3 ITP CLK1 TAP Input AK12 VCC Power Other AJ4 VSS Power Other AK13 VSS Power Other AJ5 A343 Source Synch Input Output AK14 VCC Power Other AJ6 A354 Source Synch _ Input Output AK15 VCC Power Other AJ7 VSS Power Other AK16 VSS Power Other AJ8 VCC Power Other AK17 VSS Power Other AJ9 VCC Power Other AK18 VCC Power Other AJ10 VSS Power Other AK19 VCC Power Other AJ11 VCC Power Other AK20 VSS Power Other AJ12 VCC Power Other AK21 VCC Power Other AJ13 VSS Power Other AK22 VCC Power Other AJ14 VCC Power Other AK23 VSS
144. ther VSS AD4 Power Other VSS Bil Power Other VSS AD7 Power Other VSS B14 Power Other VSS AE10 Power Other VSS B17 Power Other VSS AE13 Power Other VSS B20 Power Other VSS AE16 Power Other VSS B24 Power Other VSS AE17 Power Other VSS B5 Power Other VSS AE2 Power Other VSS B8 Power Other VSS AE20 Power Other VSS A12 Power Other VSS AE24 Power Other VSS A15 Power Other VSS AE25 Power Other VSS A18 Power Other VSS AE26 Power Other VSS A2 Power Other VSS AE27 Power Other VSS A21 Power Other VSS AE28 Power Other VSS A6 Power Other VSS AE29 Power Other VSS A9 Power Other VSS AE30 Power Other VSS AA23 Power Other VSS AE5 Power Other VSS AA24 Power Other VSS AE7 Power Other VSS AA25 Power Other VSS AF10 Power Other VSS AA26 Power Other VSS AF13 Power Other VSS AA27 Power Other VSS AF16 Power Other VSS AA28 Power Other VSS AF17 Power Other VSS AA29 Power Other VSS AF20 Power Other VSS AA3 Power Other VSS AF23 Power Other VSS AA30 Power Other VSS AF24 Power Other VSS AA6 Power Other VSS AF25 Power Other VSS AA7 Power Other VSS AF26 Power Other VSS AB1 Power Other VSS AF27 Power Other vss AB23 Power Other VSS AF28 Power Other vss AB24 Power Other VSS AF29 Power Other vss AB25 Power Other VSS AF3 Power Other Datasheet Land Listing and Signal Descriptions intel Table 24
145. tput A23 VCCA Power Other C2 BNR Common Clock Input Output A24 FC23 Power Other C3 LOCK Common Clock Input Output A25 VTT Power Other C4 VSS Power Other A26 VTT Power Other C5 D01 Source Synch Input Output A27 VTT Power Other C6 DO3 Source Synch _ Input Output A28 VTT Power Other C7 VSS Power Other A29 VTT Power Other C8 DSTBNO Source Synch _ Input Output A30 VTT Power Other C9 FC41 Power Other B1 VSS Power Other C10 VSS Power Other B2 DBSY Common Clock Input Output C11 D11 Source Synch _ Input Output B3 RSO Common Clock Input C12 D14 Source Synch _ Input Output B4 D00 Source Synch Input Output C13 VSS Power Other B5 VSS Power Other C14 D52 Source Synch _ Input Output B6 DOS Source Synch _ Input Output C15 D51 Source Synch Input Output B7 DO6 Source Synch _ Input Output C16 vss Power Other B8 vss Power Other C17 DSTBP3 Source Synch _ Input Output B9 DSTBPO Source Synch _ Input Output C18 D54 Source Synch _ Input Output B10 D10 Source Synch _ Input Output C19 VSS Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 25 Numerical Land Table 25 Numerical Land Assignment Assignment Land Land Name X x Direction Land Land Name E Direction C20 DBI3 Source Synch _ Input Output D29 VTT Power Other C21 D58 Source Synch _ Input Output
146. trate for ownership of the processor FSB it will wait until it observes LOCK de asserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock MSID 1 0 Output On the processor these signals are connected on the package to VSS As an alternative to MSID Intel has implemented the Power Segment Identifier PSID to report the maximum Thermal Design Power of the processor Refer to Section 2 5 for additional information regarding PSID PECI Input Output PECI is a proprietary one wire bus interface See Chapter 5 3 for details PROCHOT Input Output As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled The TCC will remain active until the system de asserts PROCHOT See Section 5 2 4 for more details PSI Output Processor Power Status Indicator Signal This signal may be asserted when the processor is in the Deeper Sleep State PSI can be used to improve load efficiency of the voltage regulator resulting in platform power savings Datasheet 71 Table 26 72 intel Land Listing and Sig
147. ubsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for configuration purposes the processor does not distinguish between a warm reset and a power on reset Power On Configuration Option Signals Configuration Option Signal Output tristate SMI Execute BIST A33 Disable dynamic bus parking A25 Symmetric agent arbitration ID BRO RESERVED A 24 4 A 35 26 NOTE 1 Asserting this signal during RESET will select the corresponding option 2 Address signals not identified in this table as configuration options should not be asserted during RESET 3 Disabling of any of the cores within the processors must be handled by configuring the EXT_CONFIG Model Specific Register MSR This MSR will allow for the disabling of a single core per die within the processor package Clock Control and Low Power States The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 19 for a visual representation of the processor low power states 87 im e n te Features Figure 19 Processor Low Power State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated Extended HALT or HALT Normal State INIT INTR NMI SMI RESET State Normal Execution
148. undation that builds on Intel s Virtualization Technology Intel VT to help protect the confidentiality and integrity of data stored created on the client PC Platform Environment Control Interface PECI A proprietary one wire bus interface that provides a communication channel between the processor and chipset components to external monitoring devices 11 Table 1 References Introduction Material and concepts available in the following documents may be beneficial when reading this document References Document Location Intel Core 2 Duo Processor E8000 and E7000 Series Specification Update www intel com design processor specupdt 318733 htm Intel Core 2 Duo Processor E8000 and E7000 Series and Intel Pentium Dual Core Processor E6000 and E5000 Series Thermal and Mechanical Design Guidelines www intel com design processor designex 318734 htm Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket http www intel com design processor applnots 313214 htm LGA775 Socket Mechanical Design Guide http intel com design Pentium4 guides 302666 htm Intel 64 and IA 32 Intel Architecture Software Developer s Manuals Volume 1 Basic Architecture Volume 2A Instruction Set Reference A M Volume 2B Instruction Set Reference N Z Volume 3A System Programming Guide Part 1 Volume 3B System Programming Guide Part 2
149. urce Synch Input Output FC8 AK6 Power Other D47 G22 Source Synch Input Output FC10 E24 Power Other D48 D20 Source Synch Input Output FC15 H29 Power Other D49 D17 Source Synch Input Output FC18 AE3 Power Other D50 A14 Source Synch Input Output FC20 E5 Power Other D51 C15 Source Synch Input Output FC21 F6 Power Other D52 C14 Source Synch Input Output FC22 J3 Power Other D53 B15 Source Synch Input Output FC23 A24 Power Other D54 C18 Source Synch Input Output FC24 AK1 Power Other D55 B16 Source Synch Input Output FC25 AL1 Power Other D56 A17 Source Synch Input Output FC26 E29 Power Other D57 B18 Source Synch Input Output FC27 G1 Power Other D58 C21 Source Synch Input Output FC28 U1 Power Other D59 B21 Source Synch Input Output FC29 U2 Power Other D60 B19 Source Synch Input Output FC30 U3 Power Other 47 48 intel Land Listing and Signal Descriptions Table 24 Alphabetical Land Table 24 Alphabetical Land Assignments Assignments Land Name band Signal Butter Direction Land Name Land Signal Buffer Direction Type Type FC31 J16 Power Other RESERVED AE6 FC32 H15 Power Other RESERVED AH2 FC33 H16 Power Other RESERVED D1 FC34 J17 Power Other RESERVED D14 FC35 H4 Power Ot
150. ute difference between adjacent clock periods must be less than the period stability 4 Slew rate is measured through the VSWING voltage range centered about differential zero Measurement taken from differential waveform Datasheet 33 6 Figure 4 Electrical Specifications Matching applies to rising edge rate for Clock and falling edge rate for Clock It is measured using a 75 mV window centered on the average cross point where Clock rising meets Clock falling The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations Duty Cycle High time Period must be between 40 and 60 Differential Clock Waveform Overshoot BCLK1 I VH Rising Edge Ringback Ringback Margin Threshold Region Falling Edge SORE e SON Isai Ringback BCLKO VL Undershoot Tp T1 BCLK 1 0 period T2 BCLK 1 0 period stability not shown Tph T3 BCLK 1 0 pulse high time Tpl T4 BCLK 1 0 pulse low time T5 BCLK 1 0 rise time through the threshold region T6 BCLK 1 0 fall time through the threshold region Figure 5 Measurement Points for Differential Clock Waveforms Slew rise Slew fall T5 BCLK 1 0 rise and fall time through the swing region 34 88 Datasheet m e Package Mechanical Specifications n t el 3 Figure 6 3 1 Datasheet Package Mechanical Specifications The processor is
151. video image processing video content creation speech 3D CAD games multimedia and multitasking user environments Intel 64 architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture The processor supporting Enhanced Intel Speedstep technology allows tradeoffs to be made between performance and power consumption The Intel Core 2 Duo processor E8000 and E7000 series also includes the Execute Disable Bit capability This feature combined with a supported operating system allows memory to be marked as executable or non executable Virtualization Technology provides silicon based functionality that works together with compatible Virtual Machine Monitor VMM software to improve on software only solutions The Intel Trusted Execution Technology Intel TXT is a key element in Intel s safer computing initiative that defines a set of hardware enhancements that interoperate with an Intel TXT enabled operating system to help protect against software based attacks It creates a hardware foundation that builds on Intel s Virtualization Technology to help protect the confidentiality and integrity of data stored created on the client PC Datasheet 7 intel Revision History dd ead Description Revision Date 001 Initial release January 2008 Added Intel Core 2 Duo processor E8300 and E7200 002 Updated VID information
152. wer Other VCC AG8 Power Other VCC AD28 Power Other VCC AG9 Power Other Vcc AD29 Power Other VCC AH11 Power Other Vcc AD30 Power Other VCC AH1i2 Power Other VCC AD8 Power Other VCC AH14 Power Other YCC AE11 Power Other VCC AH15 Power Other vcc AE12 Power Other VCC AH18 Power Other vcc AE4 Power Other VCC AH19 Power Other Vcc AE15 Power Other VCC AH21 Power Other VCC AE18 Power Other VCC AH22 Power Other VCC AE19 Power Other VCC AH25 Power Other VCC AE21 Power Other VCC AH26 Power Other Vcc AE22 Power Other VCC AH27 Power Other Vcc AE23 Power Other VCC AH28 Power Other VCC AE9 Power Other VCC AH29 Power Other Vcc AF11 Power Other VCC AH30 Power Other VCC AF12 Power Other VCC AH8 Power Other YCC AF14 Power Other VCC AH9 Power Other MOG AF15 Power Other VCC AJ11 Power Other VCC AF18 Power Other VCC AJ12 Power Other Vcc AF19 Power Other VCC AJ14 Power Other VCC AF21 Power Other VCC AJ15 Power Other Datasheet 49 50 intel Land Listing and Signal Descriptions Table 24 Alphabetical Land Table 24 Alphabetical Land Assignments Assignments Land Name a ci c did Direction Land Name e Ter Direction VCC AJ18 Power Other VCC AM19 Power Other VCC AJ19 Power Other Vcc AM21 Power Other VCC A

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