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Intel Pentium D 940

1. 93 0 2 3 Stop Grant State si easier OH 93 6 2 4 Enhanced HALT Snoop or HALT Snoop State Stop Grant SNOOP State iore rox AE RE 94 6 2 4 1 HALT Snoop State Stop Grant Snoop 5 3 94 6 2 4 2 Enhanced HALT Snoop 5 6 94 6 2 5 Enhanced Intel SpeedStep Technology eeee eee 94 7 Boxed Processor Specifications sssssssssssssseesnememenemememe e ener 95 7 1 Mechanical Specifications iie EXE Re ERN 95 7 1 1 Boxed Processor Cooling Solution Dimensions sss 95 7 1 2 Boxed Processor Fan Heatsink Weight ssssssssssmm teenie 97 7 1 3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly irte Dh e ERR RR wie 97 7 2 Electrical Requirements sssesssrsssrserarrtrstrtrtrstran stret rnrn sese eene nee eese enn 97 7 2 1 8 5 5 97 7 3 Thermal Specifications eere tergore tex ph he EN R EEE NEER URINNI EN tr ERR es 99 7 3 1 Boxed Processor Cooling Requirements sssssssssseeeenn mes 99 8 Balanced Technology Extended BTX Boxed Processor Specifications
2. 2 7 4 BCLK 1 0 Specifications Table 19 Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Notes VL Input Low Voltage 0 150 0 000 N A V Vu Input High Voltage 0 660 0 700 0 850 V VcRoss abs Absolute Crossing Point 0 250 N A 0 550 V 2 3 i 0 250 0 550 3 4 5 Relative Crossing Point N A V E Relative Crossing Po 0 5 Vitavg 0 700 MA 0 5 Vhavg 0 700 AVcnoss Range of Crossing Points N A N A 0 140 V Vos Overshoot N A N A 0 3 V 5 Vus Undershoot 0 300 N A N A V I VRBM Ringback Margin 0 200 N A N A V 8 uu Ie DAE A RUE MAO I CS ae eT Vim Threshold Region VcnRoss 0 100 N A VcRoss 0 100 V NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLKO equals the falling edge of BCLK1 3 The crossing point must meet the absolute and relative crossing point specifications simultaneously 4 Vuavg is the statistical average of the Vy measured by the oscilloscope 5 Vuavg Can be measured directly using Vtop on Agilent oscilloscopes and High on Tektronix oscilloscopes 6 Overshoot is defined as the absolute value of the maximum voltage 7 Undershoot is defined as the absolute value of the minimum voltage 8 Ringback Margin is defined as the absolute voltage difference b
3. Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name Ex did Direction Land Name m Direction VSS AK10 Power Other VSS AN1 Power Other VSS AK13 Power Other VSS AN10 Power Other VSS AK16 Power Other VSS AN13 Power Other VSS 17 Power Other VSS Power Other VSS AK2 Power Other VSS AN17 Power Other VSS AK20 Power Other VSS AN2 Power Other VSS 23 Power Other VSS AN20 Power Other VSS 24 Power Other VSS AN23 Power Other VSS AK27 Power Other VSS AN24 Power Other VSS 28 Power Other VSS AN27 Power Other VSS AK29 Power Other VSS AN28 Power Other VSS AK30 Power Other VSS C10 Power Other VSS AK5 Power Other VSS C13 Power Other VSS AK7 Power Other VSS C16 Power Other VSS AL10 Power Other VSS C19 Power Other VSS AL13 Power Other VSS C22 Power Other VSS AL16 Power Other VSS C24 Power Other VSS AL17 Power Other VSS C4 Power Other VSS AL20 Power Other VSS C7 Power Other VSS AL23 Power Other VSS D12 Power Other VSS AL24 Power Other VSS D15 Power Other VSS 271 Power Other VSS D18 Power Other VSS AL28 Power Other VSS D21 Power Other VSS AL3 Power Other VSS D24 Power Other VSS AL7 Power Other VSS D3 Power Other VSS AM1 Power Other VSS D5 Power Other VSS AM10 Power Other VSS D6 Power Other VSS AM13 Power Other VSS D9 Power Other VSS AM16 Power Other VSS E11 Power Other
4. 41 21 Package Handling netted 41 22 Processor Materials ea tto tore Re ERE RR A HERE eee 42 23 Alphabetical Land 5 memes sense nnn 48 24 Numerical Land eee teen EA 59 25 Signal Description Sheet 1 of 9 KERRE EEEE 70 26 Processor Thermal 5 6 ee eee ene sene 82 27 Thermal Profile for 775 VR CONFIG 05B Processors 83 28 Thermal Profile for 775 VR CONFIG 054A Processors Mainstream 84 29 Thermal Diode Parameters using Diode eee cette enn 88 30 Thermal Diode Parameters using Transistor ee 89 31 Thermal Diode Nirim and Diode _Correction_OffSet etcetera nes 90 32 Thermal Diode Interface eres tent nents 90 33 Power On Configuratio
5. s 5 Loooo0Q0QQ 4 L_ 999990999 5 3x5 000000000 000000660 5 z 290000000 1 990000000 8 szs L 2 066000000 1 000000000 ERE o60000000 000000000 000000000 660000000 z OOOOOOOUO 000000000 e OOOoOOOOOOOoOOoOOOO OOOO 000000000000000000000 000000000000000090000 000000000000000060000 W 000000000000060006000000000000000 000000000000000090000000000000000 000000000000000000000000000000000 is era 06000600000000006 0000000000 900 ds Es zt zg 28 5 d I I T J7 m o o 2 1 LX o o E MEER ee eee B 1 p EE t F oo 5 UNE ERG 40 Datasheet Package Mechanical Specifications 3 2 3 3 Table 20 3 4 Table 21 3 5 Datasheet intel Processor Component Keep Out Zones The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out zones Decoupling capacitors are typically mounted to either the topside or land side of the package substrate See Figure 5 and Figure 6 for keep out zones The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep in Package Loading Specifications Table 20 provides dynamic and static load specifications for the
6. 83 14 Thermal Profile for 775 VR CONFIG 054A Processors 84 15 Case Temperature TC Measurement Location emm nns 85 16 Processor Low Power State Machine s sssssssssserrrrstrrrtt nennen nnn nen nnn 92 17 Mechanical Representation of the Boxed Processor sss nnm nne nnns 95 18 Space Requirements for the Boxed Processor Side View applies to all four side views 96 19 Space Requirements for the Boxed Processor Top ViCW cccceeceeeee eet mm 96 20 Space Requirements for the Boxed Processor Overall View 97 21 Boxed Processor Fan Heatsink Power Cable Connector 6 98 22 Baseboard Power Header Placement Relative to Processor Socket ssssssssssss 99 23 Boxed Processor Fan Heatsink Airspace Keep out Requirements Side T VIeW iuste re ib roc c ciens aem Puck aat ba rag MG ne RR qd 100 24 Boxed Processor Fan Heatsink Airspace Keep out Requirements Side 2 VieW PE 100 25 Mechanical Representation of the Boxed Processor with a Type 101 26 Mechanical Representation of the Boxed Processor with a Type II 102 27 Requirements for the Balanced Te
7. CY OO C JO0QOO0OO0QOQO0Q0 ADOC OOOOOOOOO NA NA NAI NA O LW V NN MV NN SP OOOOQC N CV CY Y V 690606 8020 PODS GUE Wa COC k S AVI O AN f ANAD AI 20000000000 aleia C ss Cs ARAA C y OO c Q OO oO a YY OOOOOODO O O Mail NLP Nf od A uf t z imd CSS eS ISI ON OOO0O0000 200 CSI NIS IS 2 O LI O OO lo Seed RO OO OO N PN x o B OO O OO OOC O O JOOO OOO O OOO OOO OOOOOOCO O OOOOOC OOOO0O00000000000000 OOOO Fam AM AG wuoo aXaadaacmz2 2 ccmo ozzolxorou unoom AN AL AK AJ AH Datasheet 1 858 Data 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 VTT Clocks 44 m 8 Land Listing and Signal Descriptions n tel d Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions 4 1 Processor Land Assignments This section contains the land listings for the processor The land out footprint is shown in Figure 11 and Figure 12 These figures represent the land out arranged by la
8. 0000000000000009000000000000000 00000000000000006000000000000000 00000000000000009000000000000000 0000000000000000 90000000000000000 00000000000000006000000000000000 00000000000000009000000000000000 00000000000000009000000000000000 000000000 E 000900000 TO FINISH DATE Wi 606000606 00000000 900000000 1 00000000 E 000000000 00000000 600000000 00000000 000000000 00000000 900000000 4 _ L 99996060 i 000000000 Q OOOO0 906000000 1 1 00000000 o O00000000 00000000 990000000 000000000 OO000000 900000000 00000000 000000000 00000000 60000000000000000000000000000000 00600000000000000000000000000000 55555555555555559555559555665555 DESIGNED BY DRAN BY CHECIED BY APPROVED BY MATERIAL BOTTON VIEW g 3 5 ASME 114 SM 1994 s 5 a HE 0 203 C E AHS 11 77 0 05 00000000000000000000000000000000 00000000000000000000000000000000 6060000000000000690000000000000060 EI 000000000000000 EEEEEUEEECIT aa INTERPRET DIMENS S Lg a ve oema A 1511 SCALE o 2o3 C Z 0 08 IHS SEALANT SECTION E E PACKAGE SUBSTRATE
9. BSEL2 BSEL1 BSELO FSB Frequency L L L 266 MHz L L H RESERVED L H H RESERVED L H L 200 MHz H H L RESERVED H H H RESERVED H L H RESERVED H L L RESERVED Phase Lock Loop PLL and Filter Vcca and are power sources required by the PLL clock generators for the processor silicon Since these PLLs are analog they require low noise power supplies for minimum jitter Jitter is detrimental to the system it degrades external I O timings as well as internal core timings i e maximum frequency To prevent this degradation these supplies must be low pass filtered from Vy The AC low pass requirements with input at V are as follows 0 2 dB gain in pass band 0 5 dB attenuation in pass band lt 1 Hz gt 34 dB attenuation from 1 MHz to 66 MHz gt 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 3 33 m n tel Electrical Specifications Figure 3 Phase Lock Loop PLL Filter Requirements 0 2 dB 0 dB 0 5 dB Forbidden Zone Forbidden 28 dB 34 dB DC 1 Hz fpeak 1MHz 66 MHz fcore Passband High Frequency Band NOTES 1 Diagram not to scale 2 No specification for frequencies beyond fcore core frequency 3 foeak if existent should be less than 0 05 MHz 4 fcore represents the maximum core frequency supported by the platform 34 Datasheet Electrical Specifications
10. 27 9 Signal Reference Voltages vis cceiemeriaeeeds dled sen vintin iu nin ne re Fe pco daa Cete vou n epe 27 10 GTL Signal Group DC Specifications 10 0 0 mmm nen 28 11 GTL Asynchronous Signal Group DC Specifications sess 29 12 TAP Signal Group DC 5 enne 29 13 VIFPWRGD DC Specifications nre nint inet static Rr UR RE TOTA Rad EE 30 14 BSEL 2 0 and VID 5 0 DC 5 mmm nns 30 15 MSID 1 0 and BOOTSELECT DC 5 30 16 GTL Bus Voltage Definitions ccc memes emnes eene nee memes ens 31 17 Core Frequency to FSB Multiplier Configuration sss 32 18 BSEL 2 0 Frequency Table for 0 33 19 Front Side Bus Differential BCLK 5 35 20 Processor Loading 5
11. Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment i ud g Direction o id eg d Direction AJ12 Power Other AK18 Power Other AJ 13 VSS Power Other AK19 VCC Power Other AJ 14 VCC Power Other AK2 VSS Power Other AJ15 VCC Power Other AK20 VSS Power Other AJ16 VSS Power Other AK21 VCC Power Other AJ17 VSS Power Other AK22 Power Other AJ 18 VCC Power Other AK23 VSS Power Other AJ19 VCC Power Other AK24 VSS Power Other AJ2 BPMO Common Clock Input Output AK25 Power Other AJ20 VSS Power Other AK26 VCC Power Other AJ21 VCC Power Other AK27 VSS Power Other AJ 22 VCC Power Other AK28 VSS Power Other AJ23 VSS Power Other AK29 VSS Power Other AJ24 VSS Power Other AK3 ITP CLKO TAP Input AJ25 VCC Power Other AK30 VSS Power Other AJ26 VCC Power Other AK4 VIDA Power Other Output AJ27 VSS Power Other AK5 VSS Power Other AJ28 VSS Power Other AK6 FORCEPR Asynch GTL Input AJ29 VSS Power Other AK7 VSS Power Other AJ3 CLK1 TAP Input AK8 VCC Power Other AJ 30 VSS Power Other AK9 VCC Power Other AJ4 VSS Power Other AL1 THERMDA Power Other AJ5 A34 Source Synch Input Output AL10 VSS Power Other AJ6 A35 Source Synch Input Output AL11 VCC Power Other AJ7 VSS Power Other AL12 Power Other AJ8 VCC Power Other AL13 VSS Power Other AJ9 VCC Power Other AL14 VCC Power Other AK1 THERMDC Power Other AL15 Power Other AK10 VSS Power O
12. Package Mechanical Drawing The package mechanical drawings are shown in Figure 5 Figure 6 and Figure 7 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include Package reference with tolerances total height length width etc e IHS parallelism and tilt Land dimensions Top side and back side component keep out dimensions Reference datums All drawing dimensions are in mm in Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal Mechanical Design Guidelines 37 te Package Mechanical Specifications Figure 5 Processor Package Drawing Sheet 1 of 3 x o u 5 o m lt E c 1 e o COMNENTS 1 igo 203 c p hid igo ori c ENE bi 2200 MISSION COLLEGE BLVD P 0 BOX 58119 SANTA CLARA CA 95052 6119 rJ con 87313 DO NOT SCALE DRANING ues oF 3 MAY 31 55 31 55 34 1 34 1 2 3 2 3 4 242 2 593 0 82 MILL INETERS 33 93 BASIC 34 88 BASIC 16 965 BASIC 17 44 BASIC 1 17 BASIC 1 09 BASIC DRAWING WONDER MIN 31 45 31 45 3 SYMBOL 5 1 33 8 2 33 9 2 2 2 2 3 806 2 115 jt 1 2 0 74 DEPARTHENT E sur puc 4 1 TRE p E
13. Y1 Power Other Input A18 W6 Source Synch Input Output BPMO AJ2 Common Clock Input Output A195 Y6 Source Synch Input Output BPM1 AJ1 Common Clock Input Output A20 Y4 Source Synch Input Output BPM2 AD2 Common Clock nput Output A20M K3 Asynch GTL Input BPM3 AG2 Common Clock Input Output A21 AAA Source Synch Input Output BPM4 AF2 Common Clock Input Output A224 AD6 Source Synch Input Output BPM5 AG3 Common Clock Input Output A23 AA5 Source Synch Input Output G8 Common Clock Input A24 AB5 Source Synch Input Output BRO F3 Common Clock Input Output A25 AC5 Source Synch Input Output BSELO G29 Power Other Output A26 AB4 Source Synch Input Output BSEL1 H30 Power Other Output A27 AF5 Source Synch Input Output BSEL2 G30 Power Other Output A28 AF4 Source Synch Input Output COMPO A13 Power Other Input A293 AG6 Source Synch Input Output COMP1 T1 Power Other Input A3 L5 Source Synch Input Output COMP2 G2 Power Other Input A30 AG4 Source Synch Input Output COMP3 R1 Power Other Input A31 AG5 Source Synch Input Output COMP4 J2 Power Other Input A324 AH4 Source Synch Input Output COMP5 T2 Power Other Input A33 AH5 Source Synch Input Output COMP6 Y3 Power Other Input A34 AJ5 Source Synch Input Output COMP7 AE3 Power Other Input A35 AJ6 Source Synch Input Output DO B4 Source Synch Input Output A4 P6 Source Synch Input Output D1 C5 S
14. AER 24 2 5 4 Die Voltage eee 25 26 Signaling Specifications scie ore HU RC uei FERRE EE CETER 25 2 6 1 FSB Signal Groups nsira tei EROR E REEREME RI XR RR ARERMDRERRNNEREEME REDUCES NA 26 2 6 2 GTE E Asynchronous Signals icis tmt eek bk EXE E ERR e e ERE 28 2 6 3 Processor DC Spe ificatioN Sasss nene memes 28 2 6 3 1 GTL Front Side Bus 5 31 2 Clock Specifications 32 2 7 1 Front Side Bus Clock BCLK 1 0 and Processor Clocking sss 32 2 7 2 FSB Frequency Select Signals BSEL 2 0 sese 32 2 7 3 Phase Lock Loop PLL and Filter c cece t estes menm 33 2 7 4 BCLK 1 0 5 5 nen nns 35 3 Package Mechanical Specifications sss mene 37 3 1 Package Mechanical Drawing sssssssssssee neat e emnes 37 3 2 Processor Component Keep Out 65 emen 41 3
15. TOP VIEW FRONT VIEW OM ILS xui B SCALE 20 1 f cet 38 Datasheet Package Mechanical Specifications Figure 6 Processor Package Drawing Sheet 2 of 3 e va Lu Y a 2 c87313 d4tc DETAIL SCALE 60 1 RI 4 Ria 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000 0000 0000000000000000 0000000000000000 0000000000000000 000000000000000060000000000000000 000000000000000060000000000000000 0060600000000000060000000000000000 338989998 0888999888 Em 000000000 000000000 000000000 9 000000000 000000000 1 000000000 000000000 606000000 000000000 000000000 000000000 000000000 _ _ 000000000 600000000 600000000 000000000 000000000 000000000 900000000 600000000 000000000 1 000000000 000000000 o 000000000 000000000 000000000 000000000000000080000000000000000 000000000000000000000000000000000 000000000000000090000000000000000 000000000000000060000000000000000 000000000000000060000000000000000 0000000000000000 9000009099000000 00000000000000000000000000 100 prc SE SEE c3 0 23 c TF TH Jer CS 0 23 c e W
16. vera C ou D SCALE 20 1 SCALE 20 1 weet 2 3 C81313 DO NOT SCALE DRAWING sur Al A 95052 8119 2200 MISSION COLLEGE BLVD t CORP DEPARTMENT BOTTOM VIEW COMMENTS F 4 MAX MILLIMETERS RI 4 BASIC RI 4 BASIC 0 2 BASIC 6 215 BASIC 0 2 BASIC 6 215 BASIC SYMBOL M Datasheet 39 ae Figure 7 Processor Package Drawing Sheet 3 of 3 Package Mechanical Spec ifications x 5 w a en lt E e E Ei 5 E 8 24 mz z 3 fe eoi oz zs d 5 ls 000000000d000000000000b0000 0000 s 966600000d000000900000p0600000000 OOOO0O0O0000jQO000000600000poooooooooo 000000000d000000900000b0000000000 Oooooooooogoooooooooooopoooooooooo eu 606600000d000000600000b0000000000 a2 000000000g000000000000p0000000000 Es 9000000004000600p00000P0000000000 MES 3 eeeeooe 1 jo 000000006 8 bo Oooooooooo 000000000 S ox 000000000 000000000 Ses 000000000 000000000 Bee lard
17. CLK 1 0 LINTO INTR LINT1 NMI PWRGOOD RESET SKTOCC SMI STPCLK TDO TESTHI 13 0 THERMDA THERMDC THERMTRIP VID 5 0 VTTPWRGD GTLREF 1 0 TCK TDI TMS TRST Open Drain Signals THERMTRIP FERR PBE IERR BPM 5 0 BRO TDO VIT SEL LL ID 1 0 NOTES 1 These signals have a 500 5000 Q pull up to Vyyrather than on die termination 2 Signals that do not have nor are actively driven to their high voltage level Signal Reference Voltages GTLREF 2 BPM 5 0 LINTO INTR LINT1 NMI RESET BINIT BNR HIT HITM MCERR PROCHOT BRO A 35 0 ADS ADSTB 1 0 AP 1 0 BPRI D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 LOCK REQ 4 0 RS 2 0 RSP TRDY BOOTSELECT VITPWRGD A20M IGNNE INIT MSID 1 0 PWRGOOD SMI STPCLK TCK TDI1 TMS TRST 2 NOTES 1 These signals also have hysteresis added to the reference voltage See Table 12 for more information 27 e n tel Electrical Specifications 2 6 2 GTL Asynchronous Signals Legacy input signals such as 4 IGNNE INIT PWRGOOD SMI and STPCLK use CMOS input buffers All of these signals follow the same DC requirements as GTL signals however the outputs are not actively driven high during a logical 0 1 transition by the processor Th
18. VCC w VCC Vcc VCC VCC VCC vss vss vss vss NSS vss vss vss U VCC VCC VEC VEC VCC VCC T VCC VCC VCC VCC VCC VCC R vss vss vss vss vss vss vss vss P vss vss vss vss vss vss vss vss N VCC VCC VCC VCC VEC VCC VCC VCC M VCC VCC VCC VCC VCC VCC VCC VEC L vss vss vss vss vss vss vss vss K VCC VCC VCC VEC VCC VCC VCC J VCC VCC VCC Vcc VCC VCC VCC VEC VCC VCC VCC VEG DP3 DPO VCC i BSEL1 FC15 vss vss vss vss vss vss vss vss VSS VSS VSS vss DP2 DP1 G BSEL2 BSELO BCLK1 TESTHIA TESTHI5 TESTHI3 TESTHI6 RESET D47 D44 DSTBN2 DSTBP2 D35 D36 D32 D31 F RSVD BCLKO SEL TESTHIO TESTHI2 TESTHI7 RSVD VSS D43 D41 vss D38 D37 VSS D30 E VSS VSS VSS VSS VSS FC10 RSVD D45 D42 VSS D40 D39 vss D34 D33 D VT VT VIT VIT VIT VIT VSS F9 464 VSS D48 DBI2 VSS D49 RSVD VSS VT VT VIT VIT VIT VIT VSS oris VSS D58 DBI3 VSS D54 DSTBP3 55 D51 B VT VT VIT VIT VIT VIT VSS VSSA D63 D59 VSS D60 D57 VSS D55 D53 A VT VT VTT VIT VIT VIT VSS VCCA D62 VSS RSVD D61 VSS D56 DSTBN3 VSS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 46 Datasheet Land Listing and Signal Descriptions Figure 12 land out Diagram Top View Right Side 14 13 12 11 10 9
19. 101 8 1 Mechanical Specifications sssessssssssssee emm ene sese sienne 102 8 1 1 Balanced Technology Extended BTX Type and Type Boxed Processor Cooling Solution Dimensions memes 102 8 1 2 Boxed Processor Thermal Module Assembly 104 8 1 3 Boxed Processor Support and Retention Module SRM 104 8 2 Electrical Requirements cece nee eee e eser 105 8 2 1 Thermal Module Assembly Power 5 105 8 3 Thermal Specifications marie nutcase I X ERE tree ea ener IE RE eins 107 8 3 1 Boxed Processor Cooling 107 8 3 2 Variable Speed nennen seen memes sese 108 9 Debug Tools Specifications ttri ruttu ttnn meme nemen nens 111 9 1 Logic Analyzer Interface 1 mee 111 9 1 1 Mechanical Considerations sss mmm meme 111 9 1 2 Electrical Considerations ssssssssssssseee mme meme 111 4 Datasheet Figures 1 Vcc Static and Transient Tolerance for 775 VR CONFIG 05A Mainstream
20. Direction ud Magia Direction M8 vcc Power Other R24 VSS Power Other N1 PWRGOOD Power Other Input R25 VSS Power Other N2 IGNNE Asynch GTL Input R26 VSS Power Other N23 VCC Power Other R27 VSS Power Other N24 VCC Power Other R28 VSS Power Other N25 vcc Power Other R29 VSS Power Other N26 VCC Power Other R3 Asynch GTL Output N27 VCC Power Other N28 vcc Power Other ven D Powe orner N29 VCC Power Other R4 A08 Source Synch Input Output N3 vss Power Other R5 VSS Power Other N30 VCC Power Other R6 ADSTBO Source Synch Input Output N4 RESERVED R7 VSS Power Other N5 RESERVED R8 Power Other N6 vss Power Other T1 COMP1 Power Other Input N7 vss Power Other T2 COMP5 Power Other Input NB VCC Power Other T23 VCC Power Other P1 TESTHI11 Power Other Input Te MED Other P2 SMI AsynchGIL Input T23 VOC Power Oter P23 VSS Power Other T26 VCC Power Other P24 vss Power Other T27 VCC Power Other P25 vss Powar Other T28 Power Other P26 vss Power Other T29 VCC Power Other P27 vss Power Other T3 5 Power other P28 vss Power Other T30 VCC Power Other P29 vss Power Other T4 A113 Source Synch Input Output P3 INIT Asynch GTL Input T5 A09 Source Synch Input Output P30 VSS Power Other TS v35 Fowen omer PA vss Power Other T7 VSS Power Other P5 RESERVED T8 Power Other P6 A04 Source Synch Input Output ls bis P7 VSS Power Other U2 APO Common Clock
21. Datasheet 107 m n tel Balanced Technology Extended BTX Boxed Processor Specifications 8 3 2 Note Figure 32 108 In addition Type TMA must be used with Type I chassis only and Type TMA with Type II chassis only Type TMA will not fit in a Type chassis due to the height difference In the event a Type II TMA is installed in a Type chassis the gasket on the chassis will not seal against the Type TMA and poor acoustic performance will occur as a result Variable Speed Fan The boxed processor fan will operate at different speeds over a short range of temperatures based on a thermistor located in the fan hub area This allows the boxed processor fan to operate at a lower speed and noise level while thermistor temperatures are low If the thermistor senses a temperatures increase beyond a lower set point the fan speed will rise linearly with the temperature until the higher set point is reached At that point the fan speed is at its maximum As fan speed increases so do fan noise levels These set points are represented in Figure 32 and Table 36 The internal chassis temperature should be kept below 35 59C Meeting the processor s temperature specification see Chapter 5 is the responsibility of the system integrator The motherboard must supply a constant 12 V to the processor s power header to ensure proper operation of the variable speed fan for the boxed processor refer to Table 36 for the sp
22. 1 i i i 242 57 oe 550 um pq uu GE RE S 14x 0306 005 2 ES o Ln Oo 2 0 03 m 0002 0 156 0 001 0 20 ei 158 325 12 0 25 OQ 020l0 008T ATBTG yh wm pes mu ias l 40 T 0 062 0 005 8 3 Thermal Specifications This section describes the cooling requirements of the thermal module assembly solution used by the boxed processor 8 3 1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a TMA However meeting the processor s temperature specification is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor case temperature specification is in Chapter 5 The boxed processor TMA is able to keep the processor temperature within the specifications in Table 26 for chassis that provide good thermal management For the boxed processor TMA to operate properly it is critical that the airflow provided to the TMA is unimpeded Airflow of the TMA is into the duct and out of the rear of the duct in a linear flow Blocking the airflow to the TMA inlet reduces the cooling efficiency and decreases fan life Filters will reduce or impede airflow which will result in a reduced performance of the TMA The air temperature entering the fan should be kept below 35 5 C Again meeting the processor s temperature specification is the responsibility of the system integrator
23. 8 Note Note Figure 25 Datasheet Balanced Technology Extended BTX Boxed Processor Specifications The Intel Pentium D processor 900 sequence and the Intel Pentium processor Extreme Edition 955 965 will be offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from largely standard components The boxed processor will be supplied with a cooling solution known as the Thermal Module Assembly TMA Each processor will be supplied with one of the two available types of TMAs Type I or Type This chapter documents motherboard and system requirements for both the TMAs that will be supplied with the boxed processor in the 775 land LGA package This chapter is particularly important for OEMs that manufacture motherboards for system integrators Figure 25 shows a mechanical representation of a boxed processor in the 775 land LGA package with a Type TMA Figure 26 illustrates a mechanical representation of a boxed processor in the 775 land LGA package with Type TMA Unless otherwise noted all figures in this chapter are dimensioned in millimeters and inches in brackets Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designers responsibility to consider their proprietary cooling solution when designing to the r
24. D 63 0 Input Output D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor FSB agents and must connect the appropriate pins lands on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DBI Quad Pumped Signal Groups DSTBN DSTBP vere Data Group D 15 0 D 31 16 D 47 32 0 1 2 D 63 48 3 WN e O Furthermore the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 Input Output DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electrically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment To Data Bus Data Bus Signal
25. DEFER RSVD FC7 TESTHI9 TESTHI8 COMP2 VSS D28 VSS D24 D23 VSS D18 D17 VSS IMPSEL RS1 VSS BRO FC5 VSS D26 DSTBP1Z VSS D21 D19 VSS RSVD RSVD FC20 HITM TRDY VSS RSVD D25 VSS D15 D22 VSS D12 D20 VSS VSS HIT VSS ADS RSVD D52 VSS D14 D11 VSS RSVD DSTBNO VSS D3 D1l vss LOCK BNR DRDY VSS FC19 D13 VSS D10 DSTBPO VSS D6 558 VSS DO RSO DBSY VSS D50 COMPO VSS D9 D8 VSS DBIO D7 VSS D4 D2 RS2 VSS 14 13 12 T1 10 9 8 7 6 5 4 3 2 1 Datasheet 47 AN AM AL AK AJ AH AG AF AE AD AC AB 2D g x Z v U m m 48 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name 2 d rd Direction Land Name es Direction A10 U6 Source Synch Input Output ADSTB1 AD5 Source Synch Input Output All T4 Source Synch Input Output APO U2 Common Clock Input Output A123 U5 Source Synch Input Output AP1 U3 Common Clock Input Output A133 U4 Source Synch Input Output BCLKO F28 Clock Input Al4 V5 Source Synch Input Output BCLK1 G28 Clock Input A153 V4 Source Synch Input Output BINIT AD3 Common Clock nput Output Al6 W5 Source Synch Input Output BNR C2 Common Clock Input Output A174 Source Synch Input Output
26. SENSE P AREE li 4 CONTROL Match with straight pin friction lock header on mainboard Table 34 Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit Notes 12V 12 volt fan power supply 10 2 12 13 8 V IC Peak Fan current draw 1 1 1 5 A Fan start up current draw 2 2 A Fan start up current draw maximum duration 1 0 Second pulses per SENSE SENSE frequency 2 fan 1 revolution CONTROL 21 25 28 kHz 2 3 NOTES 1 Baseboard should pull this pin up to 5 V with a resistor 2 Open Drain Type Pulse Width Modulated 3 Fan will have a pull up resistor to 4 75 V maximum is 5 25 V 98 Datasheet m 8 Boxed Processor Specifications n tel Figure 22 7 3 7 3 1 Note Datasheet Baseboard Power Header Placement Relative to Processor Socket R110 4 33 4 33 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink However meeting the processor s temperature specification is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is found in Chapter 5 of this document The boxed processor fan heatsink is able to keep the processor temperature within the specifications see Table 26
27. TCK Datasheet Electrical Specifications Table 7 Table 8 Table 9 Datasheet FSB Signal Groups Sheet 2 of 2 Signal Group Type Signals Synchronous to TAP Output TCK TDO FSB Clock Clock BCLK 1 0 ITP CLK 1 0 VCC VTT VCCA VCCIOPLL VID 5 0 VSS VSSA GTLREF 1 0 COMP 7 6 5 4 3 2 1 0 RESERVED TESTHI 13 0 THERMDA THERMDC VCC SENSE VCC MB REGULATION VSS SENSE Power other VSS MB REGULATION BSEL 2 0 SKTOCC DBR 2 VTTPWRGD BOOTSELECT VIT OUT LEFT VTT OUT RIGHT VIT SEL LL ID 1 0 MSID 1 0 FCx IMPSEL NOTES Refer to Section 4 2 for signal descriptions 2 In processor systems where no debug port is implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects 3 The value of these signals during the active to inactive edge of RESET defines the processor configuration options See Section 6 1 for details Signal Characteristics Signals with Signals with No A 35 3 ADS ADSTB 1 0 AP 1 0 BINIT BNR BOOTSELECT BPRI 4 D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FROCEPR HIT HITM LOCK MCERR MSID 1 0 PROCHOT REQ 4 0 RS 2 0 RSP TRDY IMPSEL A20M BCLK 1 0 BPM 5 0 BSEL 2 0 COMP 7 6 5 4 3 2 1 0 FERR PBE IERR IGNNE INIT
28. m 8 Debug Tools Specifications n tel 9 9 1 9 1 1 9 1 2 Datasheet Debug Tools Specifications Logic Analyzer I nterface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging processor systems Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of the processor systems the LAI is critical in providing the ability to probe and capture FSB signals There are two sets of considerations to keep in mind when designing a processor system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI lands plug into the processor socket while the processor lands plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally
29. VSS AM17 Power Other VSS E14 Power Other VSS AM20 Power Other VSS E17 Power Other VSS AM23 Power Other VSS E2 Power Other VSS AM24 Power Other VSS E20 Power Other VSS AM27 Power Other VSS E25 Power Other VSS AM28 Power Other VSS E26 Power Other VSS AM4 Power Other VSS E27 Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name wu E Direction Land Name xcd uud Direction VSS E28 Power Other VSS K5 Power Other VSS E29 Power Other VSS K7 Power Other VSS E8 Power Other VSS L23 Power Other VSS F10 Power Other VSS L24 Power Other VSS F13 Power Other VSS L25 Power Other VSS F16 Power Other VSS L26 Power Other VSS F19 Power Other VSS L27 Power Other VSS F22 Power Other VSS L28 Power Other VSS F4 Power Other VSS L29 Power Other VSS F7 Power Other VSS L3 Power Other VSS G1 Power Other VSS L30 Power Other VSS H10 Power Other VSS L6 Power Other VSS H11 Power Other vss L7 Power Other VSS H12 Power Other VSS M1 Power Other VSS H13 Power Other VSS M7 Power Other VSS H14 Power Other VSS N3 Power Other VSS H17 Power Other VSS N6 Power Other VSS H18 Power Other VSS N7 Power Other VSS H19 Power Other
30. and 775 CONFIG 05B Performance Processors ssssssssssseeeennmeme nemen 24 2 Vcc Overshoot Example Waveform 0c senes 25 3 Phase Lock Loop PLL Filter 34 4 Processor Package Assembly Sketch sss emen eene 37 5 Processor Package Drawing Sheet 1 of 3 38 6 Processor Package Drawing Sheet 2 3 een eaters 39 7 Processor Package Drawing Sheet 3 of 3 cece cee eee ee eee eaters 40 8 Processor Top Side Markings Example Intel Pentium D Processor 900 Sequence 42 9 Processor Top Side Markings Example Intel Pentium Processor Extreme Edition 955 Ee ur FREUD TUER Y sian iad MUR FOE 43 10 Processor Land Coordinates and Quadrants Top View eee teeta ee teenie tae 44 11 land out Diagram Top View Left Side mmm nnn 46 12 land out Diagram Top View Right Side ccc memes 47 13 Thermal Profile for 775 VR CONFIG 05B Processors Performance
31. 3 Package Loading Specifications scrvir nnen an ee rere 41 3 4 Package Handling Guidelines ssssssssse emen meses 41 3 5 Package Insertion 5 ens 41 3 6 Processor Mass Specification lessen see enemies 42 3 7 Processor Materials cri pt e Ont V Pr E E DURER SUE 42 3 8 Processor Markings E E Y EXERTRA RATER ERRARE nga ees RUE a 42 3 9 Processor Land 0 0 8 665 eee messes 43 4 Land Listing and Signal Descriptions ssssssssssssssseme mne 45 4 1 Processor Land mememesi e meses nns 45 4 2 Alphabetical Signals Reference sss memememe sene enne 70 5 Thermal Specifications and Design 81 5 1 Processor Thermal Specifications cece eee emen 81 5 1 1 Thermal Specifications eorr tees eer pedis eere neben ror der d erbe ga 81 5 1 2 Thermal Metrology sssssssssssseseneemmm
32. 30 0 045 0 066 0 086 35 0 053 0 073 0 094 40 0 060 0 081 0 102 45 0 068 0 089 0 110 50 0 075 0 097 0 118 55 0 083 0 104 0 126 60 0 090 0 112 0 134 65 0 098 0 120 0 142 70 0 105 0 128 0 150 75 0 113 0 135 0 158 80 0 117 0 140 0 163 85 0 128 0 151 0 174 90 0 135 0 159 0 182 95 0 143 0 166 0 190 100 0 150 0 174 0 198 105 0 158 0 182 0 206 110 0 165 0 190 0 214 115 0 173 0 197 0 222 120 0 180 0 205 0 230 125 0 188 0 213 0 238 NOTES 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 5 3 2 3 This table is intended to aid in reading discrete points on Figure 1 The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop and Transportable LGA775 Socket for socket loadline guidelines and VR implementation details 4 Adherence to this loadline specification for the processor is required to ensure reliable processor operation Datasheet 23 intel Figure 1 2 5 3 Table 6 24 Electrical Specifications Vcc Static and Transient Tolerance for 775 VR CONFIG 05A Mainstream and 775 VR CONFIG 05B Performance Processors Icc A 0 10 20 30 40 50 60 70 80 90 100 110 120 VID
33. 8 y 6 5 4 3 2 1 VSS MB VCC MB VSS VCC VCC VSS vcc VCC vss YGE VCC FC16 REGULATION REGULATION SENSE SENSE vss vss VCC VSS VCC VCC VSS VCC VCC FC12 VTTPWRGD FC11 vss VID2 VIDO VSS VCC VSS VCC VCC VSS VCC VCC VSS VI D3 VID1 VID5 VSS PROCHOT THERMDA VCC VSS VCC VCC VSS VCC VCC VSS FORCEPR VSS 4 ITP CLKO VSS THERMDC VCC VSS VCC vcc VSS VCC VSS A35 A34 VSS ITP CLK1 BPMO BPM1 VCC VSS vcc VCC vss VCC VCC VSS VSS A33 A32 vss RSVD vss VCC VSS VCC VEC VSS YOC VCC VSS A29 A31 A30 BPM5 BPM3 TRST VCC VSS VCC vss VCC VCC VSS VSS A27 A28 VSS BPM4 TDO VCC VSS vcc VCC VSS VCC SKTOCC VSS RSVD VSS RSVD COMP7 VSS TCK VCC VSS A22 ADSTB1 VSS BINIT BPM2 TDI VCC VSS VSS A25 RSVD VSS DBR TMS VCC VSS A173 A243 A263 MCERR IERR VSS VIT OUT VCC VSS VSS A23 A21 VSS LL ID1 R GHT BOOT VEG vss A19 vss A20 COMP6 vss SELECT VCC VSS A18 A163 VSS TESTHI1 TESTHI12 MSIDO VCC VSS VSS Al4 154 VSS LL IDO MSID1 VCC VSS A10 A12 A13 AP1 APO VSS VCC VSS VSS A9 All vss COMP5 COMP1 vec vss ADSTBO vss COMP3 VCC VSS A4 RSVD VSS INIT SMI TESTHI11 VCC VSS VSS RSVD RSVD VSS IGNNE PWRGOOD VEC VSS REQ2 A5 74 STPCLK THERMTRI P VSS VCC VSS VSS A3 A6 vss TESTHI13 VCC VSS REQ3 VSS REQO A20M VSS LINTO VTT OUT VCC VEC VCC VCC VEG VEC VCC vss REQ4 REQ1 VSS FC22 COMP4 LEFT VSS VSS VSS VSS VSS VSS VSS VSS VSS TESTHI 10 RSP VSS GTLREF1 GTLREFO D29 D27 DSTBN1 DBI1 RSVD D16 BPRI
34. AE1 TCK TAP Input AF15 VCC Power Other AE10 VSS Power Other AF16 VSS Power Other AE11 VCC Power Other AF17 VSS Power Other AE12 Power Other AF18 Power Other AE13 VSS Power Other AF19 VCC Power Other AE14 VCC Power Other AF2 BPM4 Common Clock Input Output AE15 Power Other AF20 VSS Power Other AE16 VSS Power Other AF21 VCC Power Other AE17 vss Power Other AF22 VCC Power Other AE18 VCC Power Other AF23 VSS Power Other AE19 VCC Power Other AF24 VSS Power Other AE2 VSS Power Other AF25 VSS Power Other AE20 VSS Power Other AF26 VSS Power Other AE21 VCC Power Other AF27 VSS Power Other AE22 Power Other AF28 VSS Power Other Datasheet Land Listing and Signal Descriptions intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment m E Direction ges Direction AF29 VSS Power Other AG7 VSS Power Other AF3 VSS Power Other AG8 Power Other AF30 VSS Power Other AG9 Power Other AF4 A28 Source Synch Input Output AH1 VSS Power Other AF5 A27 Source Synch Input Output AH10 VSS Power Other AF6 VSS Power Other AH11 Power Other AF7 VSS Power Other AH12 Power Other AF8 VCC Power Other AH13 VSS Power Other AF9 Power Other AH14 Power Other AG1 TRST TAP Input AH15 VCC Power Other AG10 VSS Power Other AH16 VSS Power Other AG11
35. H15 Common Clock Input Output D42 E21 Source Synch Input Output DP2 H16 Common Clock Input Output D43 F21 Source Synch Input Output DP3 117 Common Clock Input Output D44 G21 Source Synch Input Output DRDY C1 Common Clock Input Output D45 E22 Source Synch Input Output DSTBNO C8 Source Synch Input Output D46 D22 Source Synch Input Output DSTBN1 G12 Source Synch Input Output D47 G22 Source Synch Input Output DSTBN2 G20 Source Synch Input Output D48 D20 Source Synch Input Output DSTBN3 A16 Source Synch Input Output D49 D17 Source Synch Input Output DSTBPO B9 Source Synch Input Output 49 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name du rd Direction Land Name py Direction DSTBP1 E12 Source Synch Input Output REQO K4 Source Synch Input Output DSTBP2 G19 Source Synch Input Output REQ1 J5 Source Synch Input Output DSTBP3 C17 Source Synch Input Output REQ2 Source Synch Input Output FC11 AM5 Power Other Output REQ3 K6 Source Synch Input Output FC12 AM7 Power Other Output REQ4 J6 Source Synch Input Output FC15 H29 Power Other Output RESERVED A20 FC16 AN7 Power Other Output RESERVED ACA FC10 E24 Power Other Output RESERVED AE4 FC5 F2 P
36. Input Output P8 VCC Power Other U23 VCC Power Other R1 COMP3 Power Other Input DET MEE POWERS R2 vss Power Other U25 Power Other R23 VSS Power Other ee U27 VCC Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment p il iuis Direction gs Direction U28 Power Other WA VSS Power Other U29 VCC Power Other W5 A163 Source Synch Input Output U3 AP1 Common Clock Input Output W6 A185 Source Synch Input Output U30 Power Other W7 VSS Power Other UA A13s Source Synch Input Output W8 Power Other U5 A124 Source Synch Input Output Y1 EM Power Other Input U6 A10 Source Synch Input Output U7 vss Power Other Y2 VSS Power Other U8 VCC Power Other Y23 VCC Power Other V1 MSID1 Power Other Output Power Other V2 LLIDO Power Other Output Xx VEC V23 VSS Power Other Y26 VCC Power Other V24 VSS Power Other Y27 VCC Power Other 25 VSS Power Other Y28 VCC Power Other V26 VSS Power Other Y29 VCC Power Other V27 VSS Power Other Ys COMPS V28 VSS Power Other Y30 VCC Power Other V29 VSS Power Other Y4 A20 Source Synch Input Output v3 vss Power Other Y5 VSS Power Other V30 VSS Power Other Y6 A19 Sou
37. Retention mechanism RM Since the LGA775 socket does not include any mechanical features for heatsink attach a retention mechanism is required Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket FSB Front Side Bus The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Storage conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Functional operation Refers to normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied References Material and concepts available in the following documents may be beneficial when reading this document References Document Location http www intel com design
38. Streaming SIMD Extensions 3 SSE3 are 13 additional instructions that further extend the capabilities of Intel processor technology These new instructions enhance the performance of optimized applications for the digital home such as video image processing and media compression technology The processor supports the Intel 64 architecture as an enhancement to Intel s 32 architecture This enhancement allows the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture Further details on the 64 bit extension architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at http developer intel com technology 64bitextensions The processor s Intel NetBurst microarchitecture front side bus FSB uses a split transaction deferred reply protocol like the Intel Pentium 4 processor The Intel NetBurst microarchitecture FSB uses Source Synchronous Transfer SST of address and data to improve performance by transferring data four times per bus clock 4X data transfer rate as in AGP AX Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or 2X address bus Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 6 4 GB s 800 MHz FSB or 8 5 GB s 1066 MHz FSB Intel will enable support components for the processor in
39. V24 Power Other VTT A29 Power Other VSS V25 Power Other VTT A30 Power Other VSS V26 Power Other VTT C25 Power Other VSS V27 Power Other VTT C26 Power Other VSS V28 Power Other VTT C27 Power Other VSS V29 Power Other VTT C28 Power Other VSS V3 Power Other VTT C29 Power Other VSS V30 Power Other VTT C30 Power Other VSS V6 Power Other VTT D25 Power Other VSS V7 Power Other VTT D26 Power Other VSS W4 Power Other VTT D27 Power Other VSS W7 Power Other VTT D28 Power Other VSS Y2 Power Other VTT D29 Power Other VSS Y5 Power Other VTT D30 Power Other VSS Y7 Power Other VTT OUT LE Jl Power Other Output V55 MB AN6 Power Other Output REGULATION M AA1 Power Other Output VSS SENSE AN4 Power Other Output VSSA B23 Power Other VTT SEL F27 Power Other Output VIT B25 Power Other VTTPWRGD AM6 Power Other Input Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment ce panied Direction FEN 1 oe Direction A10 DO8 Source Synch Input Output AA28 vss Power Other All DO9 Source Synch Input Output AA29 vss Power Other A12 VSS Power Other AA3 VSS Power Other A13 COMPO Power Other Input AA30 VSS Power Other A14 D50 Source Synch Input Output AA4 A21 Source Synch Inp
40. VCC Power Other AH17 VSS Power Other AG12 VCC Power Other AH18 Power Other AG13 VSS Power Other AH19 Power Other AG14 VCC Power Other AH2 RESERVED AG15 VCC Power Other AH20 VSS Power Other AG16 VSS Power Other AH21 Power Other AG17 VSS Power Other AH22 Power Other AG18 VCC Power Other AH23 VSS Power Other AG19 Power Other AH24 VSS Power Other AG2 BPM3 Common Clock Input Output AH25 Power Other AG20 VSS Power Other AH26 Power Other AG21 Power Other AH27 Power Other AG22 VCC Power Other AH28 Power Other AG23 VSS Power Other AH29 Power Other AG24 VSS Power Other AH3 VSS Power Other AG25 VCC Power Other AH30 Power Other AG26 Power Other AH4 A32 Source Synch Input Output AG27 VCC Power Other AH5 A33 Source Synch Input Output AG28 VCC Power Other AH6 VSS Power Other AG29 Power Other AH7 VSS Power Other AG3 BPM5 Common Clock nput Output AH8 Power Other AG30 VCC Power Other AH9 Power Other AG4 A30 Source Synch Input Output AJ1 BPM1 Common Clock Input Output AG5 A31 Source Synch Input Output 10 vss Power Other AG6 A29 Source Synch Input Output AJ11 Power Other Datasheet 61 62 intel Land Listing and Signal Descriptions
41. VI D5 VI D4 VI D3 VI D2 VID1 VIDO VID 0 0 1 0 1 0 0 8375 0 1 1 0 1 0 1 2125 1 0 1 0 0 1 0 8500 1 1 1 0 0 1 1 2250 0 0 1 0 0 1 0 8625 0 1 1 0 0 1 1 2375 1 0 1 0 0 0 0 8750 1 1 1 0 0 0 1 2500 0 0 1 0 0 0 0 8875 0 1 1 0 0 0 1 2625 1 0 0 1 1 1 0 9000 1 1 0 1 1 1 1 2750 0 0 0 1 1 1 0 9125 0 1 0 1 1 1 1 2875 1 0 0 1 1 0 0 9250 1 1 0 1 1 0 1 3000 0 0 0 1 1 0 0 9375 0 1 0 1 1 0 1 3125 1 0 0 1 0 1 0 9500 1 1 0 1 0 1 1 3250 0 0 0 1 0 1 0 9625 0 1 0 1 0 1 1 3375 1 0 0 1 0 0 0 9750 1 1 0 1 0 0 1 3500 0 0 0 1 0 0 0 9875 0 1 0 1 0 0 1 3625 1 0 0 0 1 1 1 0000 1 1 0 0 1 1 1 3750 0 0 0 0 1 1 1 0125 0 1 0 0 1 1 1 3875 1 0 0 0 1 0 1 0250 1 1 0 0 1 0 1 4000 0 0 0 0 1 0 1 0375 0 1 0 0 1 0 1 4125 1 0 0 0 0 1 1 0500 1 1 0 0 0 1 1 4250 0 0 0 0 0 1 1 0625 0 1 0 0 0 1 1 4375 1 0 0 0 0 0 1 0750 1 1 0 0 0 0 1 4500 0 0 0 0 0 0 1 0875 0 1 0 0 0 0 1 4625 1 1 1 1 1 1 VR output off 1 0 1 1 1 1 1 4750 0 1 1 1 1 1 VR output off 0 0 1 1 1 1 1 4875 1 1 1 1 1 0 1 1000 1 0 1 1 1 0 1 5000 0 1 1 1 1 0 1 1125 0 0 1 1 1 0 1 5125 1 1 1 1 0 1 1 1250 1 0 1 1 0 1 1 5250 0 1 1 1 0 1 1 1375 0 0 1 1 0 1 1 5375 1 1 1 1 0 0 1 1500 1 0 1 1 0 0 1 5500 0 1 1 1 0 0 1 1625 0 0 1 1 0 0 1 5625 1 1 1 0 1 1 1 1750 1 0 1 0 1 1 1 5750 0 1 1 0 1 1 1 1875 0 0 1 0 1 1 1 5875 1 1 1 0 1 0 1 2000 1 0 1 0 1 0 1 6000 Datasheet 17 m n tel Electrical Specifications 18 Reserved Unused and TESTHI Signals All RESERVED lands must rem
42. VSS AC7 Power Other VSS AG16 Power Other VSS AD4 Power Other VSS AG17 Power Other VSS AD7 Power Other VSS AG20 Power Other VSS AE10 Power Other VSS AG23 Power Other VSS AE13 Power Other VSS AG24 Power Other VSS AE16 Power Other VSS AG7 Power Other VSS AE17 Power Other VSS AH1 Power Other VSS AE2 Power Other VSS AH10 Power Other VSS AE20 Power Other VSS AH13 Power Other VSS AE24 Power Other VSS AH16 Power Other VSS AE25 Power Other VSS AH17 Power Other VSS AE26 Power Other VSS AH20 Power Other VSS 27 Power Other VSS AH23 Power Other VSS AE28 Power Other VSS AH24 Power Other VSS 29 Power Other VSS AH3 Power Other VSS AE30 Power Other VSS AH6 Power Other VSS AE5 Power Other VSS AH7 Power Other VSS AE7 Power Other VSS AJ10 Power Other VSS AF10 Power Other VSS AJ13 Power Other VSS AF13 Power Other VSS AJ16 Power Other VSS AF16 Power Other VSS AJ17 Power Other VSS AF17 Power Other VSS AJ20 Power Other VSS AF20 Power Other VSS AJ23 Power Other VSS AF23 Power Other VSS AJ24 Power Other VSS AF24 Power Other VSS AJ27 Power Other VSS AF25 Power Other VSS AJ28 Power Other VSS AF26 Power Other vss AJ29 Power Other VSS AF27 Power Other vss AJ 30 Power Other VSS AF28 Power Other VSS AJ4 Power Other VSS AF29 Power Other VSS AJ7 Power Other 55 56 intel Land Listing and Signal Descriptions
43. aid in the identification of the processor Processor Top Side Markings Example Intel Pentium D Processor 900 Sequence Brand Processor Number S Spec Country of Assy INTEL 05 Frequency L2 Cache Bus PENTIUM D 775_VR_CONFIG_05x 960 SLxxx COO FPO 3 60GHZ 4M 800 05B Pb free 2LI Symbol d Unit 2 D Matrix Mark be om Datasheet m Package Mechanical Specifications n tel Figure 9 Processor Top Side Markings Example Intel Pentium Processor Extreme Edition 955 965 Brand Processor Number S Spec Country of Assy INTEL 05 Frequency L2 Cache Bus SLxxx COO 5 NE_LGONPIG 99x 3 73GHZ 4M 1066 05B FPO Pb free 2LI Symbol Unique Unit Identifier 2 D Matrix Mark ATPO Serial 3 9 Processor Land Coordinates Figure 10 shows the top view of the processor land coordinates The coordinates are referred to throughout the document to identify processor lands Datasheet 43 1 Package Mechanical Specifications 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Processor Land Coordinates and Quadrants Top View VCONSS intel Figure 10 Address Common Clocl Async AM AG C B AA z 2r mcrcazz oax orcouuoom AN AL AK AJ AH AF AE AD A A Y Y Y 000 890080 OOOOOOOOCN OOOO Y Y YO 60C CO 0900 90000
44. as a logical high value 5 Vip and Voy may experience excursions above Vyr However input signal drivers must comply with the signal quality specifications 6 Leakage to Vss with land held at Vr 7 Leakage to V7 with land held at 300 mV 28 Datasheet Electrical Specifications Table 11 GTL Asynchronous Signal Group DC Specifications Symbol Parameter Min Max Unit Notes ViL Input Low Voltage 0 0 2 0 10 V 2 3 Vie Input High Voltage 2 0 10 Vir y 55 93 Vou Output High Voltage 0 90 Vr Vu V 7 5 B 8 l Output Low Current A als Mio 0 50 Rrz lu Input Leakage Current N A 200 pA 3 Output Leakage 10 lio 200 uA Ron Buffer On Resistance 6 12 WwW NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vi is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3 LINTO INTR and LINT1 NMI use GTLREF as a reference voltage For these two signals Vi GTLREF 0 10 and Vip 5 GTLREF 0 10 uus specifications Pio the test load 9 Leakage to Vss with land held at Vr 10 Leakage to V with land held at 300 mV The V referred to in these specifications refers to instantaneous All outputs are open drain The maximum output current is based on maximum current han
45. before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding I nput Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 signals All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 Input Output Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO A 35 17 ADSTB1 AP 1 0 Input Output AP 1 0 Address Parity are driven by the request initiator along with ADS A 35 3 and the transaction type on the REQ 4 0 A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins lands of all process
46. in chassis that provide good thermal management For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life Figure 23 and Figure 24 illustrate an acceptable airspace clearance for the fan heatsink The air temperature entering the fan should be kept below 38 C A Thermally Advantaged Chassis with an Air Guide 1 1 is recommended to meet the 38 C requirement Again meeting the processor s temperature specification is the responsibility of the system integrator The processor fan is the primary source of airflow for cooling the Vcc voltage regulator Dedicated voltage regulator cooling components may be necessary if the selected fan is not capable of keeping regulator components below maximum rated temperatures 99 8 n tel Boxed Processor Specifications Figure 23 Boxed Processor Fan Heatsink Airspace Keep out Requirements Side 1 View Figure 24 Boxed Processor Fan Heatsink Airspace Keep out Requirements Side 2 View 81 3 Aa 858 100 Datasheet m 8 Balanced Technology Extended Boxed Processor Specifications n tel
47. of others Copyright 2005 2007 Intel Corporation 2 Datasheet ContentsContents 1 EE 11 Fi Terminology sirio 12 1 1 1 Processor Packaging Terminology essem 12 1 2 References rera e i ada sa bets bep end ag d 13 2 Electrical Specifications ooo vera TEA EA eA RE E E EEEE etnias 15 2 1 Power and Ground Lands oec t e e REEF da LE A ER PER RR Rd 15 2 2 Decoupling iter deed rema nita x leen Re i RR Ke ERU NES x i RR 15 2 2 1 Voc Deco plinig sii oe ERR RR RA E ULHEX crates 15 2 2 2 Nag DECOUPLING cert Rte Een ph Ex ence MEER ER KR RnUENE 15 2 2 3 FSB Decoupling 55 eie ener bt mre Por e deii rio FEE plv eM ca eer eni 16 2 3 Voltage IdentificatilOni eerte tne e Re bt deti xe Ext Rio eR pci RR d 16 2 4 Reserved Unused and TESTHI Signals es 18 2 5 Voltage and Current 5 ccc eee eater tae 19 2 5 1 Absolute Maximum and Minimum Ratings ssssesese Hee 19 2 5 2 DC Voltage and Current Specification ene 20 2 5 3 ekee eret Exe
48. output or a bi directional signal As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled for both cores The TCC will remain active until the system de asserts PROCHOT If PROCHOT is configured as an output only the FORCEPR signal can be driven from an external source to activate the TCC This will prevent one core from asserting the PROCHOT signal of the other core and unnecessarily activating the TCC of that core Refer to Chapter 5 2 4 for details on the FORCEPR signal Datasheet m 8 Thermal Specifications and Design Considerations n tel 5 2 4 Datasheet As a bi directional signal PROCHOT allows for some protection of various components from over temperature situations The PROCHOT signal is bi directional in that it can either signal when the processor either core has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components Bi directional PROCHOT if enabled can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should
49. pentiumXE specupdt 310307 htm Intel Pentium D Processor 900 Sequence and Intel Pentium Processor Extreme Edition 955 965 Specification Update Intel Pentium D Processor Intel Pentium Processor Extreme http www intel com Edition and Intel Pentium 4 Processor Thermal and Mechanical design pentiumXE Design Guidelines designex 306830 htm http intel com design Pentium4 guides 302356 htm Voltage Regulator Down VRD 10 1 Design Guide For Desktop and Transportable LGA775 Socket http www intel com technology computing vptech index htm Intel virtualization Technology Specification for the 32 Intel Architecture http intel com design LGA775 Socket Mechanical Design Guide Pentium4 guides 302666 htm Balanced Technology Extended BTX System Design Guide www formfactors org i n tel Introduction Table 1 References Document Location Intel 64 and 32 Intel Architecture Software Developer s Manual Volume 1 Basic Architecture Volume 2A Instruction Set Reference A M Volume 2B Instruction Set Reference N Z products processor Volume 3A System Programming Guide manuals Volume 3B System Programming Guide 55 14 Datasheet m 8 Electrical Specifications n tel 2 2 1 2 2 2 2 1 2 2 2 Datasheet Electrical Specifications This chapter describes the electrical characteristics of the processor interf
50. processor package These mechanical maximum load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solution The minimum loading specification must be maintained by any thermal and mechanical solutions Processor Loading Specifications Parameter Minimum Maximum Notes Static 80 N 17 Ibf 311 N 70 Ibf L2 3 Dynamic 756 N 170 Ibf 13 4 NOTES These specifications apply to uniform compressive loading in a direction normal to the processor IHS 1 2 This is the maximum force that can be applied by a heatsink retention clip The clip must also provide the minimum specified load on the processor package 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement Package Handling Guidelines Table 21 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handl
51. signals are used to select the correct loadline slope for the processor LL ID 1 0 00 for the Pentium D processor LOCK Input Output LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins lands of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK de asserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock MCERR Input Output MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor FSB agents MCERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled e Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the 1A 32 Software Developer s Manual Volume 3 System Programming Guide 75 Table 25
52. still provide proper cooling for the VR and rely on bi directional PROCHOT only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power With a properly designed and characterized thermal solution it is anticipated that bi directional PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Refer to the Voltage Regulator Down VRD 10 1 Design Guide for Desktop Socket 775 for details on implementing the bi directional PROCHOT feature FORCEPR Signal The FORCEPR force power reduction input can be used by the platform to cause the processor both cores to activate the TCC If the Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal The TCC will remain active until the system deasserts FORCEPR FORCEPR is an asynchronous input FORCEPR can be used to thermally protect other system components To use the VR as an example when the FORCEPR pin is asserted the TCC circuit in the processor both cores will activate reducing the current consumption of the processor and the corresponding temperature
53. the individual processor Refer to thermal profile figure and associated table for the allowed combinations of power and Tc 82 Datasheet Thermal Specifications and Design Considerations Pentium Processor Extreme Edition and Intel Pentium 4 Processor Thermal and Mechanical Design Guidelines and the Processor Power Characterization Methodology for the details of this methodology The case temperature is defined at the geometric top center of the processor Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 26 instead of the maximum processor power consumption The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time For more details on the usage of this feature refer to Section 5 2 In all cases the Thermal Monitor feature must be enabled for the processor to remain within specification Thermal Specifications and Design Considerations Table 27 Figure 13 Datasheet intel Thermal Profile for 775 VR CONFIG 05B Processors Performance Power Maximum Power Ma
54. 0 000 VID 0 019 Vcc Maximum d VID 0 038 VID 0 057 4 VID 0 076 4 VID 0 095 4 Vcc Typical VID 0 114 4 VID 0 133 4 p d Vcc Minimum Vcc V VID 0 152 4 VID 0 171 4 VID 0 190 4 VID 0 209 4 VID 0 228 NOTES 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 5 3 2 This loadline specification shows the deviation from the VID set point 3 The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop and Transportable LGA775 Socket for socket loadline guidelines and VR implementation details Vcc Overshoot The processor can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot voltage The time duration of the overshoot event must not exceed Tos max Tos max is the maximum allowable time duration above VID These specifications apply to the processor die voltage as measured across the VCC SENSE and VSS SENSE lands Overshoot Specifications Symbol Parameter Min Max
55. 3 73 GHz Intel Pentium processor Extreme Edition 955 965 only Available at 3 60 GHz 3 40 GHz 3 20 GHz 3 GHz and 2 80 GHz Intel Pentium D processor 900 sequence only Enhanced Intel Speedstep Technology Intel Pentium D processor 900 sequence only Supports Intel 643 architecture Supports Intel virtualization Technology Not on Pentium D processors 945 925 and 915 Supports Execute Disable Bit capability Binary compatible with applications running on previous members of the Intel microprocessor line Intel NetBurst microarchitecture FSB frequency at 800 MHz Pentium D processor 900 sequence only FSB frequency at 1066 MHz Pentium processor Extreme Edition 955 965 only Pentium Processor Extreme Edition 955 965 Features Enhanced branch prediction Optimized for 32 bit applications running on advanced 32 bit operating systems Two 16 KB Level 1 data caches Two 2 MB Advanced Transfer Caches on die full speed Level 2 L2 cache with 8 way associativity and Error Correcting Code ECC 144 Streaming SIMD Extensions 2 SSE2 instructions 13 Streaming SIMD Extensions 3 SSE3 instructions Enhanced floating point and multimedia unit for enhanced video audio encryption and 3D performance Power Management capabilities System Management mode Multiple low power states 8 way cache associativity provides improved cache hit rate on load store operations 775 land Package Hyper Pipeline
56. 56 92 627 26 48 9 60 56 0 94 63 1 28 49 3 62 56 4 95 63 4 30 49 7 64 56 8 32 50 1 66 57 3 Figure 14 Thermal Profile for 775 VR CONFIG 054A Processors Mainstream 65 0 60 0 e o Tcase C y 0 21x 43 4 50 0 45 0 40 0 H H 4 H 0 10 20 30 40 50 60 70 80 90 Power W 84 Datasheet m 8 Thermal Specifications and Design Considerations n tel 5 1 2 Figure 15 5 2 5 2 1 Datasheet Thermal Metrology The maximum and minimum case temperatures Tc for the processor is specified in Table 26 This temperature specification is meant to help ensure proper operation of the processor Figure 15 illustrates where Intel recommends Tc thermal measurements should be made For detailed guidelines on temperature measurement methodology refer to the Intel Pentium D Processor Intel Pentium Processor Extreme Edition and Intel Pentium 4 Processor Thermal and Mechanical Design Guidelines Case Temperature Tc Measurement Location 5 Measure at this point 1 geo metric center of the package 37 5 mm 37 5 mm Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption by
57. 76 intel Land Listing and Signal Descriptions Signal Description Sheet 1 of 9 Name MSID 1 0 Type Input Description MSID 1 0 input MSIDO is used to indicate to the processor whether the platform supports 775 VR CONFIG 05B processors A 775 CONFIG 05B processor will only boot if its MSIDO pin is electrically low A 775 VR CONFIG 054A processor will ignore this input MSID1 must be electrically low for the processor to boot PROCHOT Output or Input Output For the processor PROCHOT can be configured via BIOS as an output or a bi directional signal As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As a bi directional signal assertion of PROCHOT by the system will activate the TCC if enabled for both cores The TCC will remain active until the system de asserts PROCHOT See Section 5 2 3 for more details PWRGOOD Input PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on
58. CC 128 Power Other 24 Power Other 129 Power Other 25 Power Other VCC J30 Power Other VCC T26 Power Other VCC J8 Power Other 27 Power Other VCC J9 Power Other 28 Power Other VCC K23 Power Other 29 Power Other K24 Power Other 30 Power Other 53 54 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name x e Direction Land Name pou k Direction VCC T8 Power Other VI D3 AL6 Power Other Output VCC U23 Power Other VIDA AK4 Power Other Output VCC U24 Power Other VI D5 AL4 Power Other Output U25 Power Other VSS B1 Power Other VCC U26 Power Other VSS B11 Power Other U27 Power Other VSS B14 Power Other VCC U28 Power Other VSS B17 Power Other VCC U29 Power Other VSS B20 Power Other vcc U30 Power Other VSS B24 Power Other VCC U8 Power Other VSS B5 Power Other VCC V8 Power Other VSS B8 Power Other VCC W23 Power Other VSS A12 Power Other VCC W24 Power Other VSS A15 Power Other VCC W25 Power Other VSS A18 Power Other VCC W26 Power Other VSS A2 Power Other VCC W27 Power Other VSS A21 Power Other VCC W28 Power Other VSS A24 Power Other VCC W29 Power Ot
59. Cable Connector Description GND 12 V SENSE CONTROL 5 Straight square pin 4 pin terminal housing with polarizing ribs and friction locking ramp 0 100 pitch 0 025 square pin width Match with straight pin friction lock header on mainboard Table 35 TMA Power and Signal Specifications Description Min Typ Max Unit Notes 12V 12 volt fan power supply 10 2 12 13 8 V IC Peak Fan current draw 1 0 1 5 A Fan start up current draw 2 0 A Fan start up current draw maximum duration 1 0 Second pulses per SENSE SENSE frequency 2 fan 1 revolution CONTROL 21 25 28 KHz 2 3 NOTES 1 Baseboard should pull this pin up to 5 V with a resistor 2 Open Drain Type Pulse Width Modulated 3 Fan will have a pull up resistor to 4 75 V maximum 5 25 V 106 Datasheet m 8 Balanced Technology Extended BTX Boxed Processor Specifications n tel Figure 31 Balanced Technology Extended BTX Mainboard Power Header Placement Hatched Area oe Q p gt al 288 Rear Panel 1 0 Example PCI Express 6 35 0 13 iod Connectors 0 250 0 005 J 0000 SS Y X I L 266 70 0 25 l 10 500 0 010 124 00 4 882 1 i i Example PCI Connectors 14657 5 770 1
60. Common Clock Input G27 TESTHI4 Power Other Input H5 TESTHI10 Power Other Input G28 BCLK1 Clock Input H6 VSS Power Other G29 BSELO Power Other Output H7 VSS Power Other G3 TESTHI8 Power Other Input H8 VSS Power Other G30 BSEL2 Power Other Output H9 VSS Power Other G4 TESTHI9 Power Other Input ji MEE Power Other Output G5 FC7 Source Synch Output G6 RESERVED J10 VCC Power Other G7 DEFER Common Clock Input itt me Pawel ORIG G8 Common Clock Input Ls VER POWI 113 VCC Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment po il iuis Direction e diui de Direction 114 Power Other K4 REQO Source Synch Input Output 115 VCC Power Other K5 VSS Power Other 116 DPO Common Clock Input Output K6 REQ3 Source Synch Input Output 117 DP3 Common Clock Input Output K7 VSS Power Other J18 VCC Power Other K8 Power Other J19 VCC Power Other L1 LINTI Asynch GTL Input 12 COMP4 Power Other Input L2 TESTHI13 Asynch GTL Input 120 VCC Power Other L23 vss Power Other 121 VCC Power Other L24 VSS Power Other 122 Power Other L25 VSS Power Other 123 VCC Power Other L26 VSS Power Other 124 Power Other L27 VSS Power Other 125 VCC Power Oth
61. Intel Pentium D Processor 900 Sequence and Intel Pentium Processor Extreme Edition 955 965 Datasheet On 65 nm Process in the 775 land LGA Package supporting Intel 64 Architecture and supporting Intel Virtualization Technology January 2007 Document Number 310306 007 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATI NG TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILI TY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL LIFE SAVING OR LIFE SUSTAINING APPLICATIONS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Pentium D processor 900 sequence and Intel Pentium processor Extreme Edition 955 965 may contain design
62. Power Other D30 VIT Power Other F11 D23 Source Synch Input Output D4 HIT Common Clock Input Output F12 D24 Source Synch Input Output D5 VSS Power Other F13 VSS Power Other D6 VSS Power Other F14 D28 Source Synch Input Output D7 D20 Source Synch Input Output F15 D30 Source Synch Input Output D8 D12 Source Synch Input Output F16 VSS Power Other D9 VSS Power Other F17 D37 Source Synch Input Output E10 D21 Source Synch Input Output F18 D38 Source Synch Input Output Ell VSS Power Other F19 VSS Power Other E12 DSTBP1 Source Synch Input Output F2 FC5 Common Clock Input E13 D26 Source Synch Input Output F20 D41 Source Synch Input Output E14 VSS Power Other F21 D43 Source Synch Input Output E15 D33 Source Synch Input Output F22 vss Power Other E16 D34 Source Synch Input Output F23 RESERVED E17 VSS Power Other F24 TESTHI7 Power Other Input E18 D39 Source Synch Input Output F25 TESTHI2 Power Other Input E19 D40 Source Synch Input Output F26 TESTHIO Power Other Input E2 VSS Power Other F27 VIT_SEL Power Other Output E20 VSS Power Other F28 BCLKO Clock Input E21 D42 Source Synch Input Output F29 RESERVED 65 66 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Ec ud Dir
63. RESERVED B5 vss Power Other D10 D22 Source Synch Input Output B6 DO54 Source Synch Input Output D11 D15 Source Synch Input Output B7 DO6 Source Synch Input Output D12 iis Power other B8 VSS Power Other D13 D25 Source Synch Input Output B9 DSTBPO Source Synch Input Output C1 DRDY Common Clock Input Output s iii Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment pr ad Direction Direction D16 RESERVED E22 D45 Source Synch Input Output D17 D49 Source Synch Input Output E23 RESERVED D18 VSS Power Other E24 FC10 Power Other Output D19 DBI2 Source Synch Input Output E25 vss Power Other D2 ADS Common Clock Input Output E26 VSS Power Other D20 D48 Source Synch Input Output E27 vss Power Other D21 VSS Power Other E28 VSS Power Other D22 D46 Source Synch Input Output E29 vss Power Other D23 FC9 Power Other Output E3 TRDY Common Clock Input D24 VSS Power Other E4 HITM Common Clock Input Output D25 VIT Power Other E5 FC20 Power Other Output D26 VTT Power Other E6 RESERVED D27 VTT Power Other E7 RESERVED D28 Power Other E8 VSS Power Other D29 VIT Power Other E9 D19 Source Synch Input Output D3 VSS Power Other F10 VSS
64. SS Power Other AC3 Power Other pret Vas iPower eter AC30 VCC Power Other AA27 VSS Power Other 59 60 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment uid ES Direction ud id eg d Direction ACA RESERVED AE23 VCC Power Other AC5 A25 Source Synch Input Output AE24 VSS Power Other AC6 vss Power Other AE25 VSS Power Other AC7 VSS Power Other AE26 VSS Power Other AC8 VCC Power Other AE27 VSS Power Other AD1 TDI TAP Input AE28 VSS Power Other AD2 BPM2 Common Clock Input Output AE29 VSS Power Other AD23 Power Other AE3 COMP7 Power Other Input AD24 VCC Power Other AE30 VSS Power Other AD25 VCC Power Other AE4 RESERVED AD26 Power Other AE5 VSS Power Other AD27 VCC Power Other AE6 RESERVED AD28 VCC Power Other AE7 VSS Power Other AD29 VCC Power Other AE8 SKTOCC Power Other Output AD3 BINIT Common Clock Input Output AE9 VCC Power Other AD30 VCC Power Other AF1 TDO TAP Output AD4 vss Power Other AF10 VSS Power Other AD5 ADSTB1 Source Synch Input Output AF11 VCC Power Other AD6 A22 Source Synch Input Output AF12 VCC Power Other AD7 vss Power Other AF13 VSS Power Other AD8 VCC Power Other AF14 VCC Power Other
65. Unit Figure Note Vos Max Magnitude of Vcc overshoot above VID 0 050 V 2 Time duration of Vcc overshoot above Tos MAX ce E 25 us 2 VID NOTES 1 Adherence to these specifications for the processor is required to ensure reliable processor operation 2 Consult the Voltage Regulator Down VRD 10 1 Design Guide For Desktop and Transportable LGA775 Socket for proper application of the overshoot specification Datasheet m 8 Electrical Specifications n tel Figure 2 2 5 4 2 6 Datasheet Vcc Overshoot Example Waveform Example Overshoot Waveform VID 0 050 VID o o 5 G gt Time Tos Overshoot time above VID Vos Overshoot above VID NOTES 1 Vos is measured overshoot voltage 2 Tos s measured time duration above VID Die Voltage Validation Overshoot events on processor must meet the specifications in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands Overshoot events that are lt 10 ns in duration may be ignored These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic GTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates Platforms implement a termination voltage
66. VSS P23 Power Other VSS H20 Power Other VSS P24 Power Other VSS H21 Power Other VSS P25 Power Other VSS H22 Power Other VSS P26 Power Other VSS H23 Power Other VSS P27 Power Other VSS H24 Power Other VSS P28 Power Other VSS H25 Power Other VSS P29 Power Other VSS H26 Power Other VSS P30 Power Other VSS H27 Power Other VSS P4 Power Other VSS H28 Power Other VSS P7 Power Other VSS H3 Power Other VSS R2 Power Other VSS H6 Power Other VSS R23 Power Other VSS H7 Power Other VSS R24 Power Other VSS H8 Power Other VSS R25 Power Other VSS H9 Power Other VSS R26 Power Other VSS 14 Power Other VSS R27 Power Other VSS 17 Power Other VSS R28 Power Other VSS K2 Power Other VSS R29 Power Other 57 58 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name e Direction Land Name go i Direction VSS R30 Power Other VTT B26 Power Other VSS R5 Power Other VTT B27 Power Other VSS R7 Power Other VTT B28 Power Other VSS T3 Power Other VTT B29 Power Other VSS T6 Power Other VTT B30 Power Other VSS T7 Power Other VTT A25 Power Other VSS U1 Power Other VTT A26 Power Other VSS U7 Power Other VTT A27 Power Other VSS V23 Power Other VTT A28 Power Other VSS
67. WRGD Vr and are asserted TMS Input TMS Test Mode Select is a J TAG specification support signal used by debug tools TRDY Input TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins lands of all FSB agents TRST Input TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset Input VCC are the power pins for the processor The voltage supplied to these pins is determined by the VID 5 0 pins VCCA Input VCCA provides isolated power for the internal processor core PLLs VCCI OPLL Input VCCIOPLL provides isolated power for internal processor FSB PLLs VCC SENSE Output VCC SENSE is an isolated low impedance connection to processor core power Vcc It can be used to sense or measure voltage near the silicon with little noise VCC REGULATI ON Output This land is provided as a voltage regulator feedback sense point for Vcc It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator Down VRD 10 1 Design Guide for Desktop Socket 775 VID 5 0 Output VID 5 0 Voltage ID signals are used to support automatic selection of power supply voltages Vcc Refer to the Voltage Regulator Down VRD 10 1 Design Guide for D
68. able refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty VID 5 0 x11111 or the voltage regulation circuit cannot supply the voltage that is requested it must disable itself See the Voltage Regulator Down VRD 10 1 Design Guide For Desktop and Transportable LGA775 Socket for further details The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 4 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 5 and Figure 1 as measured across the VCC SENSE and VSS SENSE lands The VRM or VRD used must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 4 and Table 5 Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop and Transportable LGA775 Socket for further details Datasheet Electrical Specifications Table 2 Voltage Identification Definition VI D5 VIDA VID3 VID2 VID1 VIDO VID
69. aces and signals DC electrical characteristics are provided Power and Ground Lands The processor has 226 VCC power 24 VIT and 273 VSS ground inputs for on chip power distribution All power lands must be connected to Vcc while all VSS lands must be connected to a system ground plane The processor VCC lands must be supplied by the voltage determined by the Voltage I Dentification VID lands Twenty four 24 signals are denoted as VTT that provide termination for the front side bus and power to the I O buffers A separate supply must be implemented for these lands that meets the Vr specifications outlined in Table 4 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate Larger bulk storage Cgyj y such as electrolytic or aluminum polymer capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 4 Failure to do so can result in timing violations or reduced lifetime of the component Vcc Decoupling V
70. actual Nirim as defined in the temperature sensor manufacturers datasheet The Diode Base value and Nirim used to calculate the Diode Correction Offset are listed in Table 31 Thermal Diode Nirim and Diode Correction Offset Symbol Parameter Unit trim Diode ideality used to calculate Diode Offset 1 008 Diode Base Diode Base 0 C Thermal Diode I nterface r Signal Signal Name Land Number Description THERMDA AL1 diode anode THERMDC AK1 diode cathode 8 88 Datasheet Features 6 6 1 Table 33 6 2 Datasheet intel Features Power On Configuration Options Several configuration options can be configured by hardware The processor samples the hardware configuration at reset on the active to inactive transition of RESET For specifications on these options please refer to Table 33 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset purposes the processor does not distinguish between a warm reset and a power on reset Power On Configuration Option Signals Configuration Option Signal Output tristate SMI 4 Execute BIST INIT In Order Queue pipelining set depth AT to 1 Disable MCERR observation A9 Disable BINIT observation A10 APIC Cluster ID 0 3 A 12 11 D
71. ails on which GTL signals do not include on die termination Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF Table 16 lists the GTLREF specifications The GTL reference voltage GTLREF should be generated on the system board using high precision voltage divider circuits Table 16 GTL Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes GTLREF PU GTLREF pull up resistor 124 0 99 124 124 1 01 J GTLREF PD GTLREF pull down resistor 210 0 99 210 210 1 01 Ww On die pull up for 3 RPULLUP BOOTSELECT signal aug 3000 w 60 o Platform Termination 51 60 66 w 4 Resistance RIT 0 Q Platform Terminati 5 atform Termination 39 50 55 w 3 Resistance 60 Q Platform Termination 9 5 COMP Resistance SB 60 4 E w POEM 50 Q Platf T inati atform Termination 49 9 0 9 49 49 9 1 01 Ww 7 COMP Resistance 1 9 3 v 60 Q Platform Termination 5 COMP Resistance 23 8 60 4 ol w iii 50 Q Platf T inati atform Termination 49 9 0 9 49 49 9 1 01 Ww 5 COMP Resistance 2 3 uid 3 9 60 Q Platform Termination 9 3 COMP Resistance 33 8 60 4 6l W RBS 50 Q Platf T inati 49 9 0 99 49 9 49 9 L01 w 5 COMP Resistance 60 Q Platform Termination 9 4 1 Ww 5 COMP Resistance 33 8 ne COMP 1 0 50 Q Platf
72. ain unconnected Connection of these lands to Vcc Vr or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 4 for a land listing of the processor and the location of all RESERVED lands In a system level design on die termination has been included by the processor to allow signals to be terminated within the processor silicon Most unused GTL inputs should be left as no connects as GTL termination is provided on the processor silicon However see Table 7 for details on GTL signals that do not include on die termination Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the motherboard trace for front side bus signals For unused GTL input or I O signals use pull up resistors of the same value as the on die termination resistors Rrr For details see Table 16 TAP GTL Asynchronous inputs and GTL Asynchronous outputs do not include on die termination Inputs and utilized outputs must be terminated on the motherboard Unused outputs may be termin
73. al Land Assignments Assignments Land Name n iud o id Direction Land Name d Te T Direction AN12 Power Other K25 Power Other VCC AN14 Power Other 26 Power Other VCC AN15 Power Other K27 Power Other AN18 Power Other K28 Power Other VCC AN19 Power Other K29 Power Other VCC AN21 Power Other 30 Power Other AN22 Power Other K8 Power Other VCC AN25 Power Other L8 Power Other AN26 Power Other M23 Power Other AN29 Power Other M24 Power Other VCC AN30 Power Other M25 Power Other AN8 Power Other M26 Power Other VCC AN9 Power Other VCC M27 Power Other VCC J10 Power Other M28 Power Other VCC J11 Power Other M29 Power Other VCC J12 Power Other M30 Power Other 113 Power Other M8 Power Other VCC 114 Power Other N23 Power Other VCC 115 Power Other vcc N24 Power Other 118 Power Other N25 Power Other VCC J19 Power Other N26 Power Other VCC 120 Power Other vcc N27 Power Other VCC 121 Power Other N28 Power Other VCC 122 Power Other vcc N29 Power Other 123 Power Other N30 Power Other VCC 124 Power Other N8 Power Other VCC 125 Power Other P8 Power Other 126 Power Other R8 Power Other VCC 127 Power Other 23 Power Other V
74. andling capability of the buffer and is not specified into the test load m Datasheet Leakage to Vss with land held at 29 Table 13 Table 14 Table 15 30 VTTPWRGD DC Specifications Electrical Specifications Symbol Parameter Min Typ Max Unit ViL Input Low Voltage E 0 3 V Vin Input High Voltage 0 9 V BSEL 2 0 and VID 5 0 DC Specifications Symbol Parameter Max Unit Notes Ron BSEL 2 VID 5 0 Buffer On Resistance 120 Ww 2 loL Max Land Current 2 4 mA 2 3 lou Output High Current 460 pA 23 Voltage Tolerance 1 05 4 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 These parameters are not tested and are based on design simulations 3 loi is measured at 0 10 V r lop is measured at 0 90 V 4 Refer to the appropriate platform design guide for implementation details MSI D 1 0 and BOOTSELECT DC Specifications Symbol Parameter Min Typ Max Unit Notes Vu Input Low Voltage 0 24 V Vin Input High Voltage 0 96 V NOTES 1 These parameters are not tested and are based on design simulations Datasheet m 8 Electrical Specifications n tel 2 6 3 1 GTL Front Side Bus Specifications In most cases termination resistors are not required as these are integrated into the processor silicon See Table 8 for det
75. ase emitter junction is used as a thermal diode with its collector shorted to Ground A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control Table 29 Table 30 Table 31 and Table 32 provide the diode parameter and interface specifications Two different sets of diode parameters are listed in Table 29 and 30 The Diode Model parameters Table 29 apply to traditional thermal sensors that use the Diode Equation to determine the processor temperature Transistor Model parameters Table 30 have been added to support thermal sensors that use the transistor equation method The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits This thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor Thermal Diode Parameters using Diode Model Symbol Parameter Min Typ Max Unit Notes lew Forward Bias Current 5 200 pA 1 n Diode Ideality Factor 1 000 1 009 1 050 2 3 4 Rr Series Resistance 2 79 4 52 6 24 Q 2 3 5 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Characterized across a range of 50 80 C 3 Not 100 tested Specified by design characterization 4 The ideality factor n represents the deviation
76. ated fan and will plug into the 4 wire fan header on the baseboard The power cable connector and pinout are shown in Figure 30 Baseboards must provide a compatible power header to support the boxed processor Table 35contains specifications for the input and output signals at the TMA The TMA outputs a SENSE signal which is an open collector output that pulses at a rate of 2 pulses per fan revolution A baseboard pull up resistor provides VOH to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The TMA receives a Pulse Width Modulation PWM signal from the motherboard from the 4 pin of the connector labeled as CONTROL 105 m n tel Balanced Technology Extended BTX Boxed Processor Specifications Note The boxed processor s TMA requires a constant 12 V supplied to pin 2 and does not support variable voltage control or 3 pin PWM control The power header on the baseboard must be positioned to allow the TMA power cable to reach it The power header identification and location should be documented in the platform documentation or on the system board itself Figure 31 shows the location of the fan power connector relative to the processor socket The baseboard power header should be positioned within 4 33 inches from the center of the processor socket Figure 30 Boxed Processor TMA Power
77. ated on the motherboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing All TESTHI 13 0 lands should be individually connected to Vy via a pull up resistor that matches the nominal trace impedance The TESTHI signals may use individual pull up resistors or be grouped together as detailed below A matched resistor must be used for each group TESTHI 1 0 TESTHI 7 2 TESTHI8 cannot be grouped with other TESTHI signals TESTHI9 cannot be grouped with other TESTHI signals TESTHI10 cannot be grouped with other TESTHI signals TESTHI11 cannot be grouped with other TESTHI signals TESTHI12 cannot be grouped with other TESTHI signals TESTHI13 cannot be grouped with other TESTHI signals However using boundary scan test will not be functional if these lands are connected together For optimum noise margin all pull up resistor values used for TESTHI 13 0 lands should have a resistance value within 20 of the impedance of the board transmission line traces For example if the nominal trace impedance is 50 O then a value between 40 Q and 60 Q should be used Datasheet Electrical Specifications n tel 2 5 2 5 1 Table 3 Datasheet Voltage and Current Specification Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings Within functional ope
78. board VIT SEL Output The VIT SEL signal is used to select the correct V voltage level for B the processor VTTPWRGD Input The processor requires this input to determine that the Vr voltages are stable and within specification Datasheet 8 79 80 Land Listing and Signal Descriptions Datasheet m 8 Thermal Specifications and Design Considerations n tel 5 5 1 Note 5 1 1 Datasheet Thermal Specifications and Design Considerations Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5 1 1 Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete thermal solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting For more information on designing a component level thermal solution refer to the Intel Pentium D Processor Intel Penti
79. cc regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications This includes bulk capacitance with low effective series resistance ESR to keep the voltage rail within specifications during large swings in load current In addition ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity Additionally a sufficient quantity of low ESR ceramic capacitors are required in the socket cavity to ensure proper high frequency noise suppression Consult the Voltage Regulator Down VRD 10 1 Design Guide For Desktop and Transportable LGA775 Socket for further information Vr Decoupling Decoupling must be provided on the motherboard Decoupling solutions must be sized to meet the expected load To insure compliance with the specifications various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors 15 m n tel Electrical Specifications 16 FSB Decoupling The processor integrates signal termination on the die In addition some of the high frequency capacitance required for the FSB is included on the processor package However additional high frequency capacitance must be added to the
80. ch Input Output D24 F12 Source Synch Input Output D57 B18 Source Synch Input Output D25 D13 Source Synch Input Output D58 C21 Source Synch Input Output D26 E13 Source Synch Input Output D59 B21 Source Synch Input Output D27 G13 Source Synch Input Output D6o B7 Source Synch Input Output D28 F14 Source Synch Input Output D60 B19 Source Synch Input Output D29 G14 Source Synch Input Output D61 A19 Source Synch Input Output D3 C6 Source Synch Input Output D62 A22 Source Synch Input Output D30 F15 Source Synch Input Output D63 B22 Source Synch Input Output D31 615 Source Synch Input Output D7 A7 Source Synch Input Output D32 G16 Source Synch Input Output D8 A10 Source Synch Input Output D33 E15 Source Synch Input Output D9 A11 Source Synch Input Output D34 E16 Source Synch Input Output DBI 0 A8 Source Synch Input Output D35 G18 Source Synch Input Output DBI 1 G11 Source Synch Input Output D36 G17 Source Synch Input Output DBI 2 D19 Source Synch Input Output D37 F17 Source Synch Input Output DBI 3 C20 Source Synch Input Output D38 F18 Source Synch Input Output DBR AC2 Power Other Output D39 E18 Source Synch Input Output DBSY B2 Common Clock Input Output D4 A5 Source Synch Input Output DEFER G7 Common Clock Input D40 E19 Source Synch Input Output DPO 116 Common Clock Input Output D41 F20 Source Synch Input Output DP1
81. chnology Extended BTX Type Keep out Volumes 103 28 Requirements for the Balanced Technology Extended BTX Type II Keep out Volume 104 29 Assembly Stack Including the Support and Retention Module sese 105 30 Boxed Processor TMA Power Cable Connector Description sssee 106 31 Balanced Technology Extended BTX Mainboard Power Header Placement Hatched Area net A pane next Cr dva e Fen 107 32 Boxed Processor TMA Set 5 mene nennen nnn 108 Datasheet 5 Tables T References Eure Am IINE 13 2 Voltage Identification mene ne nnne 17 3 Absolute Maximum and Minimum Ratings sss emen meme 19 4 Voltage and Current Specifications ssssssssssssssnmmeme nemen e eene nnn 20 5 Vcc Static and Transient Tolerance for 775 CONFIG 05A Mainstream and 775 CONFIG 05B Performance Processors ssessssssse emen 23 6 Vcc Overshoot Specifications e ne xa eg cages dk kac 3 ke YR GG Ga Fc s Fa dua eben 24 7 FSB Signal Groups nee erc terere os ber d Reuse tes Few kd ebur ad etr Ee ee Dee e ERU 26 8 Signal Characteristics eo ee teu agate be
82. cluding heatsink heatsink retention mechanism and socket Manufacturability is a high priority hence mechanical assembly may be completed from the top of the baseboard and should not require any special tooling The processor also includes the Execute Disable Bit capability This feature combined with a supported operating system allows memory to be marked as executable or non executable If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system See the Intel Architecture Software Developer s Manual for more detailed information 11 i n tel Introduction 1 1 1 1 1 The Intel Pentium D processor 900 sequence supports Enhanced Intel SpeedStep technology that allows trade offs to be made between performance and power consumptions This may lower average power consumption in conjunction with OS support The Pentium D processors 960 950 940 930 and 920 and the Pentium processor Extreme Edition 955 965 support Intel Virtualization Technology Intel Virtualization Technology provides silicon based functionality that works together with compatible Virtual Machine Monitor VMM software to improve upon software only solutions Because this virtualization hardware provides a new architecture upon which the operating sys
83. ction 5 2 7 THERMDC Other Thermal Diode Cathode See Section 5 2 7 77 Table 25 78 intel Land Listing and Signal Descriptions Signal Description Sheet 1 of 9 Name THERMTRI P Type Output Description In the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature approximately 15 C above the maximum Te Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRIP Driving of the THERMTRIP signal is enabled within 10 us of the assertion of PWRGOOD provided VTTPWRGD Vr and Vcc are asserted and is disabled on de assertion of PWRGOOD if VTTPWRGD or Vcc are not valid THERMTRIP may also be disabled Once activated THERMTRI P remains latched until PWRGOOD VTTPWRGD V or Vcc is de asserted While the de assertion of the PWRGOOD VITPWRGD VTT or VCC signal will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 us of the assertion of PWRGOOD provided VTTP
84. d BTX Boxed Processor Specifications n tel Figure 27 Requirements for the Balanced Technology Extended BTX Type I Keep out Volumes 5 4 3 2 Bw Ow MSTORY DESCRIPTION T me INITIAL RELEASE 04 05 04 F F jo 114 E D D T H 91 74 3 848 1 B B LGA775 VOLUMETRIC BTX A is TITTEN ku 0 5 00 wrsutouwm perio 6 4 2 NOTE Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation Datasheet 103 intel Figure 28 Balanced Technology Extended BTX Boxed Processor Specifications Requirements for the Balanced Technology Extended BTX Type II Keep out Volume 8 1 2 8 1 3 104 NOTE Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation Boxed Processor Thermal Module Assembly Weight The boxed processor thermal module assembly for Type BTX will not weigh more than 1200 grams The boxed processor thermal module assembly for Type BTX will not weigh more than 1200 grams See Chapter 5 and the Intel Pentium D Processor Intel Pentium Processor Extreme Edition and Intel Pentium 4 Processor Thermal and Mechanical Design Guidelines for details on the processor weight and thermal module assembly require
85. d Signal Descriptions Datasheet intel Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name i Direction Land Name d uu id Direction TESTHI1 W3 Power Other Input AD29 Power Other TESTHI 10 H5 Power Other Input AD30 Power Other TESTHI 11 P1 Power Other Input AD8 Power Other TESTHI12 W2 Power Other Input 1 Power Other TESTHI 13 L2 Asynch GTL Input AE12 Power Other TESTHI2 F25 Power Other Input AE14 Power Other TESTHI3 G25 Power Other Input AE15 Power Other TESTHI4 G27 Power Other Input AE18 Power Other TESTHI5 G26 Power Other Input VCC AE19 Power Other TESTHI6 G24 Power Other Input 21 Power Other TESTHI7 F24 Power Other Input 22 Power Other TESTHI8 G3 Power Other Input AE23 Power Other TESTHI9 G4 Power Other Input 9 Power Other THERMDA AL1 Power Other AF11 Power Other THERMDC Power Other AF12 Power Other THERMTRIPZ M2 Asynch GTL Output VCC AF14 Power Other TMS AC1 TAP Input AF15 Power Other TRDY E3 Common Clock Input 18 Power Other TRST AG1 TAP Input VCC AF19 Power Other AA8 Power Other AF21 Power Other 8 Power Other 22 Power O
86. d Technology Advance Dynamic Execution Very deep out of order execution The Intel Pentium D processor 900 sequence and Intel Pentium processor Extreme Edition 955 965 deliver Intel s advanced powerful processors for desktop PCs that are based on the Intel NetBurst microarchitecture The processor is designed to deliver performance across applications and usages where end users can truly appreciate and experience the performance These applications include Internet audio and streaming video image processing video content creation speech 3D CAD games multimedia and multitasking user environments Intel 64 architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture The processor supporting Enhanced Intel Speedstep technology allows tradeoffs to be made between performance and power consumption The Pentium D processor 900 sequence and Pentium processor Extreme Edition 955 965 also include the Execute Disable Bit capability This feature combined with a supported operating system allows memory to be marked as executable or non executable The Pentium D processors 960 950 940 930 and 920 and Pentium processor Extreme Edition 955 965 support Intel virtualization Technology Virtualization Technology provides silicon based functionality that works together with compatible Virtual Machine Monitor VMM software to improve on software only solut
87. defects or errors known as errata which may cause the product to deviate from published specifications Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor number for details Hyper Threading Technology requires a computer system with an Intel Pentium processor Extreme Edition supporting Hyper Threading Technology and an HT Technology enabled chipset BIOS and an operating system Performance will vary depending on the specific hardware and software you use See http www intel com products ht hyperthreading more htm for information including details on which processors support HT Technology 9Intel 64 requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 Processor will not operate including 32 bit opera
88. details on HALT Snoop State Grant Snoop State and Enhanced HALT Snoop State HALT Snoop State Stop Grant Snoop State The processor will respond to snoop transactions on the FSB while in Stop Grant state or in HALT Power Down state During a snoop transaction the processor enters the HALT Snoop State Stop Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB After the snoop is serviced the processor will return to the Stop Grant state or HALT Power Down state as appropriate Enhanced HALT Snoop State The Enhanced HALT Snoop State is the default Snoop State when the Enhanced HALT state is enabled via the BIOS The processor will remain in the lower bus ratio and VID operating point of the Enhanced HALT state While in the Enhanced HALT Snoop State snoops are handled the same way as in the HALT Snoop State After the snoop is serviced the processor will return to the Enhanced HALT state Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep technology enables the processor to switch between frequency and voltage points which may result in platform power savings To support this technology the system must support dynamic VID transitions Switching between voltage frequency states is software controlled Not all processors are capable of supporting Enhanced Intel SpeedStep technology More details on which processor frequ
89. dling capability of the buffer and is not specified into Vin is defined as the voltage range at a receiving agent that will be interpreted as a logical high value Vin and Voy may experience excursions above Vr However input signal drivers must comply with the signal quality Table 12 TAP Signal Group DC Specifications Symbol Parameter Min Max Unit Notes 2 Vuys Input Hysteresis 120 396 mV 3 4 a 0 5 Vrr Vuvs 0 53 Vrr e Vuvs max y 5 6 0 24 0 24 L2 voltage TAP Input low to high threshold voltage 0 5 Vrr Viys_min 0 5 rr Viys_max V i PWRGOOD Input high 5 to low threshold voltage BAT v T TAP Input high to low M x 5 threshold voltage 0 5 Vrr 0 5 Vrr Vus ww V Vou Output High Voltage N A Vor V 2 Output Low Current 22 2 mA 7 lo Input Leakage Current x 200 HA 8 lio Output Leakage Current 200 pA 3 Ron Buffer On Resistance 6 12 Ww NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 All outputs are open drain 3 Leakage to Vr with land held at 300 mV 4 Vuys represents the amount of hysteresis nominally centered about 0 5 for all TAP inputs 5 The Vr referred to in these specifications refers to instantaneous V 6 0 24 V is defined at 20 of nominal Vm of 1 2 V 7 The maximum output current is based on maximum current h
90. e need to specify two sets of timing parameters One set is for common clock signals which are dependent upon the rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asychronous signals are still present A20M z IGNNE etc and can become active at any time during the clock cycle Table 7 identifies which signals are common clock source synchronous and asynchronous FSB Signal Groups Sheet 1 of 2 Signal Group Type Signals GTL Common Synchronous to Clock Input BCLK 1 0 BPRI DEFER RESET RS 2 0 RSP TRDY AP 1 0 ADS BINIT BNR BPM 5 0 BRO Ed pet ONES to pBsY DP 3 0 DRDY HIT HITM LOCK MCERR Signals Associated Strobe REQ 4 0 A 16 3 3 ADSTBO GTL Source Synchronous to A 35 17 4 ADSTB1 Synchronous I O assoc strobe D 15 0 DBIO DSTBPO DSTBNO D 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 Synchronous to GTL Strobes ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 BCLK 1 0 GTL Asynchronous A20M FORCEPR IGNNE INIT LINTO INTR Input LINT1 NMI SMI STPCLK PWRGOOD CT E Cy ncnrencus FERR PBE IERR THERMTRIP Output GTL Asynchronous Input Output PROCHOT TAP Input Synchronous to TCK TDI TMS TRST
91. ecific requirements Boxed Processor TMA Set Points Higher Set Point Highest Noise Level Increasing Fan Speed amp Noise Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature Degrees C Datasheet Balanced Technology Extended Boxed Processor Specifications tel Table 36 Datasheet TMA Set Points for 3 wire operation of BTX Type and Type ll Boxed Processors Boxed Processor TMA Set Point Boxed Processor Fan Speed Notes 9C When the internal chassis temperature is below or equal to this X 23 set point the fan operates at its lowest speed Recommended 1 E maximum internal chassis temperature for nominal operating environment When the internal chassis temperature is at this point the fan operates between its lowest and highest speeds Y 29 Recommended maximum internal chassis temperature for worst case operating environment 2235 5 When the internal chassis temperature is above or equal to this 1 set point the fan operates at its highest speed NOTES 1 Set point variance is approximately 1 C from Thermal Module Assembly to Thermal Module Assembly If the boxed processor TMA 4 pin connector is connected to a 4 pin motherboard header and the motherboard is designed with a fan speed controller with PWM output see CONTROL in Table 35 and remote thermal diode measurement capability the boxed processor will opera
92. ection d siad us co d Direction F3 BRO Common Clock Input Output G9 D16 Source Synch Input Output F4 vss Power Other H1 GTLREFO Power Other Input F5 RS1 Common Clock Input H10 VSS Power Other F6 IMPSEL Power Other Input H11 VSS Power Other F7 VSS Power Other H12 VSS Power Other F8 D17 Source Synch Input Output H13 VSS Power Other F9 D18 Source Synch Input Output H14 VSS Power Other G1 VSS Power Other H15 DP1 Common Clock Input Output G10 RESERVED H16 DP2 Common Clock Input Output G11 DBI1 Source Synch Input Output H17 VSS Power Other G12 DSTBN1 Source Synch Input Output H18 VSS Power Other G13 D27 Source Synch Input Output H19 VSS Power Other G14 D29 Source Synch Input Output H2 GTLREF1 Power Other Input G15 D31 Source Synch Input Output H20 VSS Power Other G16 D32 Source Synch Input Output H21 VSS Power Other G17 D36 Source Synch Input Output H22 VSS Power Other G18 D35 Source Synch Input Output H23 VSS Power Other G19 DSTBP2 Source Synch Input Output H24 VSS Power Other G2 COMP2 Power Other Input H25 VSS Power Other G20 DSTBN2 Source Synch Input Output H26 VSS Power Other G21 D44 Source Synch Input Output H27 VSS Power Other G22 D47 Source Synch Input Output H28 VSS Power Other G23 RESET Common Clock Input H29 FC15 Power Other Output G24 TESTHI6 Power Other Input H3 VSS Power Other G25 TESTHI3 Power Other Input H30 BSEL1 Power Other Output G26 TESTHI5 Power Other Input H4 RSP
93. encies will support this feature will be provided in future releases of the Intel Pentium D Processor 900 Sequence and Intel Pentium Processor Extreme Edition 955 965 Specification Update Enhanced Intel SpeedStep technology is a technology that creates processor performance states P states P states are power consumption and capability states within the Normal state as shown in Figure 16 Enhanced Intel SpeedStep technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system Note that the front side bus is not altered only the internal core frequency is changed To run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep technology Voltage Frequency selection is software controlled by writing to processor MSRs Model Specific Registers thus eliminating chipset dependency f the target frequency is higher than the current frequency Vcc is incriminated in steps 12 5 mV by placing a new value on the VID signals and the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded If the target frequency is lower than the cu
94. equired keep out zone on their system platforms and chassis Refer to the Intel Pentium D Processor Intel Pentium Processor Extreme Edition and Intel Pentium 4 Processor Thermal and Mechanical Design Guidelines for further guidance Mechanical Representation of the Boxed Processor with a Type TMA NOTE The duct clip heatsink and fan can differ from this drawing representation but the basic shape and size will remain the same 101 m n tel Balanced Technology Extended BTX Boxed Processor Specifications Figure 26 8 1 8 1 1 102 Mechanical Representation of the Boxed Processor with a Type TMA NOTE The duct clip heatsink and fan can differ from this drawing representation but the basic shape and size will remain the same Mechanical Specifications Balanced Technology Extended BTX Type I and Type II Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Intel processor TMA The boxed processor will be shipped with an unattached TMA Figure 27 shows a mechanical representation of the boxed processor in the 775 land LGA package for Type TMA Figure 28 shows a mechanical representation of the boxed processor in the 775 land LGA package for Type TMA The physical space requirements and dimensions for the boxed processor with assembled fan thermal module are shown Datasheet Balanced Technology Extende
95. er Other AM10 VSS Power Other AN16 VSS Power Other AM11 VCC Power Other AN17 VSS Power Other AM12 VCC Power Other AN18 Power Other AM13 VSS Power Other AN19 Power Other AM14 VCC Power Other AN2 vss Power Other AM15 Power Other AN20 VSS Power Other AM16 VSS Power Other AN21 Power Other AM17 VSS Power Other AN22 Power Other AM18 Power Other AN23 VSS Power Other AM19 VCC Power Other AN24 VSS Power Other AM2 VIDO Power Other Output AN25 Power Other AM20 VSS Power Other AN26 Power Other AM21 VCC Power Other AN27 VSS Power Other AM22 VCC Power Other AN28 VSS Power Other AM23 VSS Power Other AN29 Power Other AM24 VSS Power Other AN3 VCC SENSE Power Other Output AM25 VCC Power Other AN30 Power Other AM26 Power Other AN4 VSS SENSE Power Other Output AM27 VSS Power Other VCC MB AM28 VSS Power Other AN5 E Power Other Output 63 64 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Signal Buffer Land Land Signal Buffer Name Type Direction Name Type Direction VSS MB C10 VSS Power Other ANG Power einer Output C11 D11 Source Synch Input Output AN7 FC16 Power Oth
96. er L28 vss Power Other 126 VCC Power Other L29 vss Power Other 127 VCC Power Other L3 VSS Power Other 128 VCC Power Other L30 vss Power Other 129 VCC Power Other L4 A06 Source Synch Input Output 13 FC22 Power Other Output L5 A03 Source Synch Input Output 130 VCC Power Other L6 VSS Power Other 14 VSS Power Other L7 VSS Power Other 15 REQ1 Source Synch Input Output L8 Power Other J6 REQ4 Source Synch Input Output M1 VSS Power Other J7 yos POM Her M2 MoN Asynch GTL Output J8 VCC Power Other J9 Power Other M23 VCC Power Other K1 LINTO Asynch GTL Input Mes Ven ORIEL K2 vss Power Other M25 VCC Power Other K23 Vcc Power Other M26 VCC Power Other K24 VCC Power Other M27 VCC Power Other K25 VCC Power Other M28 VCC Power Other K26 VCC Power Other M29 VCC Power Other K27 Vcc Power Other M3 STPCLK Asynch GTL Input K28 VCC Power Other M30 Power Other K29 VCC Power Other M4 A07 st Source Synch Input Output K3 A20M Asynch GTL Input M5 A05 Source Synch Input Output K30 VCC Power Other M6 REQ2 Source Synch Input Output M7 vss Power Other 67 68 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment m
97. er Output C12 D14 Source Synch Input Output AN8 VCC Power Other SIS NSS a AN9 VCC Power Other C14 D52 Source Synch Input Output B1 vss Power Other C15 D51 Source Synch Input Output B10 D10 Source Synch Input Output cie is Een B11 VSS Power Other C17 DSTBP3 Source Synch Input Output B12 D13 Source Synch Input Output ctg DA Source Synch jinput Output B13 FC19 Power Other Output c13 PONITUR B14 VSS Power Other C2 BNR Common Clock Input Output B15 D53 Source Synch Input Output C20 DBI3 Source Synch Input Output B16 D55 Source Synch Input Output cal Source Synch jInput Output B17 VSS Power Other eer Ves Power orner B18 D57 Source Synch Input Output ee PONET OMER B19 D60 Source Synch Input Output ot Power Other B2 DBSY Common Clock Input Output c23 VIT POWE ONET B20 VSS Power Other Spo c SE et B21 D59 Source Synch Input Output a Rowen B22 D63 Source Synch Input Output EAk VIT Power otner B23 VSSA Power Other SET MIT j Powerotner B24 VSS Power Other C3 LOCK Common Clock Input Output B25 VIT Power Other SEMI Power other B26 VIT Power Other ET yes ERWEITERT B27 VIT Power Other C5 DO1 Source Synch Input Output B28 VIT Power Other C6 034 Source Synch Input Output B29 VIT Power Other ves Fowerother B3 RSO Common Clock Input C8 DSTBNO Source Synch Input Output B30 VTT Power Other ERU RESERVED B4 DOO Source Synch Input Output DT
98. ese brief 85 m n tel Thermal Specifications and Design Considerations 5 2 2 5 2 3 86 periods of TCC activation is expected to be so minor that it would be immeasurable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and in some cases may result in a Tc that exceeds the specified maximum temperature and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the Intel Pentium D Processor Intel Pentium Processor Extreme Edition and Intel Pentium 4 Processor Thermal and Mechanical Design Guidelines for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems using the processor must not rely
99. ese signals do not have setup or hold time specifications in relation to BCLK 1 0 All of the GTL Asynchronous signals are required to be asserted deasserted for at least six BCLKs in order for the processor to recognize the proper signal state See Section 2 6 3 for the DC specifications for the GTL Asynchronous signal groups See Section 6 2 for additional timing requirements for entering and leaving the low power states 2 6 3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless otherwise stated All specifications apply to all frequencies and cache sizes unless otherwise stated Table 10 GTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Input Low Voltage 0 0 GTLREF 0 10 V 23 Vin Input High Voltage GTLREF 0 10 V m Vit V 453 Vou Output High Voltage Vit V 5 3 MAX l tput L t N A A OL Output Low Curren 0 50 Rr np Ron min Input Leakage 6 lu inca N A 200 Output Leakage 7 lio Currant N A 200 pA Buffer On Ron Resistance a 12 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vj is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3 The V referred to in these specifications is the instantaneous V 4 Vig is defined as the voltage range at a receiving agent that will be interpreted
100. esktop Socket 775 for more information The voltage supply for these signals must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID signals becomes valid The VID signals are needed to support the processor voltage specification variations See Table 2 for definitions of these signals The VR must supply the voltage that is requested by the signals or disable itself VSS Input VSS are the ground pins for the processor and should be connected to the system ground plane VSSA Input VSSA is the isolated ground for internal PLLs Datasheet Land Listing and Signal Descriptions intel Table 25 Signal Description Sheet 1 of 9 Name Type Description VSS SENSE is an isolated low impedance connection to processor VSS SENSE Output core Vss It can be used to sense or measure ground near the silicon with little noise This land is provided as a voltage regulator feedback sense point for VSS MB Output Vss Itis connected internally in the processor package to the sense REGULATION P point land V27 as described in the Voltage Regulator Down VRD 10 1 Design Guide for Desktop Socket 775 VTT Miscellaneous voltage supply VTT_OUT_LEFT The OUT LEFT and VTT_OUT_RIGHT signals are included to Output provide a voltage supply for some signals that require termination OUT RIGHT to Vg on the mother
101. essor number lcc Enhanced Auto Halt for 775 CONFIG 05B Performance Extreme Edition 965 3 73 GHz 68 Extreme Edition 955 3 46 GHz 68 960 3 60 GHz 60 950 3 40 GHz 60 ENHANCED_ AQ 3 20 GHZ 99 A 1011 AUTO HALT Processor number I cc Enhanced Auto Halt for 775 CONFIG 05A Mainstream 960 3 60 GHz _ _ 48 950 945 3 40 GHz 48 940 935 3 20 GHz 48 930 925 3 00 GHz 48 920 915 2 80 GHz 48 Itec Icc TCC active lec A FSB termination voltage Vor 1 14 1 20 1 26 y 1914 DC AC specifications VIT OUT LEFT and DC Current that may be drawn from OUT LEFT and VIT OUT OUT RIGHT per pin ZEE M RIGHT Icc Ir Steady state FSB termination current 4 5 A 1516 power up Power up FSB termination current 7 5 A1 oe to vccA Icc for PLL lands x 70 mA lec for 1 0 PLL land 52 mA lec ctirer cc for GTLREF 200 NOTES 1 Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These 2 3 o Qc M specifications will be updated with characterized data from silicon measurements at a later date Adherence to the voltage specifications for the processor are required to ensure reliable processor operation Each processor is programmed with a maximum valid voltage identification value VID which is set at man
102. etween the maximum Rising Edge Ringback and the maximum Falling Edge Ringback 9 Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches It includes input threshold hysteresis Datasheet 8 35 36 Electrical Specifications Datasheet m 8 Package Mechanical Specifications n tel 3 Figure 4 3 1 Datasheet Package Mechanical Specifications The processor is packaged in a Flip Chip Land Grid Array FC LGA6 package that interfaces with the motherboard via an LGA775 socket The package consists of a processor core mounted on a substrate land carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 4 shows a sketch of the processor package components and how they are assembled together Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket The package components shown in Figure 4 include the following e Integrated Heat Spreader IHS Thermal Interface Material TI M Processor core die Package substrate Capacitors Processor Package Assembly Sketch Core die TIM IHS Substrate Capacitors LGA775 Socket 4 Syste Board NO TE 1 Socket and motherboard are included for reference and are not part of processor package
103. from ideal diode behavior as exemplified by the diode equation lew ls e qVpb nkT 1 where ls saturation current q electronic charge Vp voltage across the diode k Boltzmann Constant and T absolute temperature Kelvin Datasheet m 8 Thermal Specifications and Design Considerations n tel Table 30 Datasheet 5 The series resistance Rr is provided to allow for a more accurate measurement of the junction temperature Ry as defined includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation Terror Rr N 1 lfwminl nk q In N where Terror sensor temperature error N sensor current ratio k Boltzmann Constant q electronic charge Thermal Diode Parameters using Transistor Model Symbol Parameter Min Typ Max Unit Notes lew Forward Bias Current 5 200 pA 1 2 lg Emitter Current 5 200 no Transistor Ideality 0 997 1 001 1 005 3 4 5 Beta 0 391 0 760 3 4 RT Series Resistance 2 79 4 52 6 24 Q 3 6 NOTES 1 Intel does not support or
104. g power on configuration a central agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR Input Output BNR Block Next Request is used to assert a bus stall by any bus agent unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions BOOTSELECT Input This input is required to determine whether the processor is installed in a platform that supports the processor The processor will not operate if this signal is low This input has a weak internal pull up to Vcc BPM 5 0 Input Output BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins lands of all processor FSB agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processor These signals do not have on die termination Refer to Section 2 5 2 for termination requirements BPRI Input Bus Priority Request is used to arbitrate for ownership of the processor FSB It must connec
105. her VCC AH21 Power Other VCC AL14 Power Other VCC AH22 Power Other VCC AL15 Power Other VCC AH25 Power Other VCC AL18 Power Other VCC AH26 Power Other VCC AL19 Power Other VCC AH27 Power Other VCC AL21 Power Other VCC AH28 Power Other VCC AL22 Power Other VCC AH29 Power Other VCC AL25 Power Other VCC AH30 Power Other VCC AL26 Power Other VCC AH8 Power Other VCC AL29 Power Other VCC AH9 Power Other VCC AL30 Power Other vcc AJ11 Power Other VCC AL8 Power Other VCC AJ12 Power Other VCC AL9 Power Other VCC AJ14 Power Other VCC AM11 Power Other VCC AJ15 Power Other VCC AM12 Power Other VCC 18 Power Other VCC AM14 Power Other VCC AJ19 Power Other VCC AM15 Power Other VCC AJ21 Power Other VCC AM18 Power Other VCC AJ 22 Power Other VCC AM19 Power Other AJ25 Power Other AM21 Power Other VCC AJ 26 Power Other VCC AM22 Power Other VCC AJ8 Power Other VCC AM25 Power Other VCC AJ9 Power Other VCC AM26 Power Other VCC AK11 Power Other VCC AM29 Power Other VCC AK12 Power Other AM30 Power Other VCC AK14 Power Other VCC AM8 Power Other VCC AK15 Power Other VCC AM9 Power Other vcc AK18 Power Other AN11 Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 23 Alphabetical Land Table 23 Alphabetic
106. her VSS A6 Power Other VCC W30 Power Other VSS AQ Power Other VCC W8 Power Other VSS AA23 Power Other VCC Y23 Power Other VSS AA24 Power Other VCC Y24 Power Other VSS AA25 Power Other VCC Y25 Power Other VSS AA26 Power Other VCC Y26 Power Other VSS AA27 Power Other VCC Y27 Power Other VSS AA28 Power Other VCC Y28 Power Other VSS AA29 Power Other VCC Y29 Power Other VSS AA3 Power Other VCC Y30 Power Other VSS AA30 Power Other VCC Y8 Power Other VSS AA6 Power Other E LUN AN5 Power Other Output iin BAT FOWET ONET VSS AB1 Power Other VCC SENSE AN3 Power Other Output vss B23 Power Other VERA qoe VSS AB24 Power Other VCCIOPLL C23 Power Other VSS AB25 Power Other VIDO AM2 Power Other Output vss AB26 Power Other VID1 AL5 Power Other Output vss AB27 Power Other VID2 AM3 Power Other Output Datasheet Land Listing and Signal Descriptions Datasheet intel Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name xu iu id Direction Land Name pde und Direction VSS 28 Power Other VSS AF3 Power Other VSS 29 Power Other vss AF30 Power Other VSS AB30 Power Other VSS AF6 Power Other VSS AB7 Power Other VSS AF7 Power Other VSS AC3 Power Other VSS AG10 Power Other VSS AC6 Power Other VSS AG13 Power Other
107. in the processor If the processors diode ideality deviates from that of ntrim each calculated temperature will be offset by a fixed amount This temperature offset can be calculated with the equation Terror nf T measured X 1 Dactua Dtrim Where Terror nf is the offset in degrees C Tmeasurea is in Kelvin Nactual is the measured ideality of the diode and Nirim is the diode ideality assumed by the temperature sensing device To improve the accuracy of diode based temperature measurements a new register containing Thermal Diode Offset data has been added to the processor During manufacturing each processor thermal diode will be evaluated for its behavior relative to a theoretical diode Using the equation above the temperature error created by the difference between Mirim and the actual ideality of the particular processor will be 89 m n tel Thermal Specifications and Design Considerations Table 31 Table 32 90 calculated This Thermal Diode Offset value will be programmed into the new diode correction MSR and when added to the Thermal Diode Base value can be used to correct temperatures read by diode based temperature sensing devices If the Nirim value used to calculate the Thermal Diode Offset differs from the Nirim value used in a temperature sensing device the Terror nf may not be accurate If desired the Thermal Diode Offset can be adjusted by calculating Nactuai and then recalculating the offset using the
108. ing Guidelines Parameter Maximum Recommended Notes Shear 311 N 70 Ibf L2 Tensile 111 N 25 Ibf 2 3 Torque 3 95 N m 35 Ibf in 24 NOTES 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 These guidelines are based on limited testing for design characterization 3 A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface 4 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide 41 m n tel Package Mechanical Specifications 3 6 3 7 Table 22 3 8 Figure 8 42 Processor Mass Specification The typical mass of the processor is 21 5 g 0 76 oz This mass weight includes all the components that are included in the package Processor Materials Table 22 lists some of the package components and associated materials Processor Materials Component Material Integrated Heat Spreader Nickel Plated Copper IHS Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper Processor Markings Figure 8 and Figure 9 show the topside markings on the processor This diagram is to
109. ion and are not tested The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT is the same as the maximum Icc for the processor Vr must be provided via a separate voltage source and not be connected to Vcc This specification is measured at the land Baseboard bandwidth is limited to 20 MHz Datasheet Electrical Specifications intel 15 This is maximum total current drawn from V plane by only the processor This specification does not include the current coming from through the signal line Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop and Transportable LGA775 Socket to determine the total drawn by the system 16 This is a steady state current specification which is applicable when both V and Vec are high 17 This is a power up peak current specification which is applicable when V is high and is low Table 5 Vcc Static and Transient Tolerance for 775 VR CONFIG 05A Mainstream and 775 VR CONFIG 05B Performance Processors Voltage Deviation from VID Setting V 2 3 4 Icc A Maximum Voltage Typical Voltage Minimum Voltage 1 5 mo 1 55 mo 1 6 mo 0 000 0 019 0 038 5 0 008 0 027 0 046 10 0 015 0 035 0 054 15 0 023 0 042 0 062 20 0 030 0 050 0 070 25 0 038 0 058 0 078
110. ions 58 Datasheet 9 Introduction 1 Note Note Datasheet intel Introduction The Intel Pentium D processor 900 sequence and Intel Pentium processor Extreme Edition 955 965 are Intel s first desktop dual core products on the 65 nm process The processors use Flip Chip Land Grid Array FC LGA6 package technology and plug into the LGA775 socket The Pentium D processor 900 sequence and Pentium processor Extreme Edition 955 965 like the Intel Pentium D processor on 90 nm process in the 775 land LGA package use the Intel NetBurst microarchitecture and maintains the tradition of compatibly with A 32 software In this document unless otherwise specified the Intel Pentium D processor 900 sequence refers to Intel Pentium D processors 960 950 945 940 935 930 925 920 and 915 In this document the Intel Pentium D processor 900 sequence on 65 nm process in the 775 land LGA package and the Intel Pentium processor Extreme Edition 955 965 on 65 nm process in the 775 land LGA package are referred to simply as processor The processor functions as two physical processors in one package This allows a duplication of execution resources to provide increased system responsiveness in multitasking environments and headroom for next generation multithreaded applications and new usages The processor supports all the existing Streaming SIMD Extensions 2 SSE2 and Streaming SIMD Extensions 3 SSE3
111. isable bus parking A15 Single Logical Processor Mode 3143 Symmetric agent arbitration ID BRO RESERVED A 6 3 A8 A 14 13 16 35 4 NOTES 1 Asserting this signal during RESET will select the corresponding option 2 Address signals not identified in this table as configuration options should not be asserted during RESET 3 This mode is not tested Clock Control and Low Power States The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 16 for a visual representation of the processor low power states 91 intel crm Figure 16 6 2 1 6 2 2 6 2 2 1 92 Processor Low Power State Machine HALT or MWAIT Instruction and HALT Bi N I Stat us Cycle Generated Enhanced HALT or HALT State f NM INIT BINIT INTR NMI SMI BCLK running orma execution e FSB interrupts Snoops and interrupts allowed X A E Snoop Snoop STPCLK STPCLK Event Event Asserted De asserted 9 o Occurs Serviced Se d Y Enhanced HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Y Stop Grant State Event Sosurs Stop Grant Snoop State BCLK running BCLK running Snoops and interrupts allowed Snoop Event Serviced Service snoops to caches Normal S
112. level for GTL signals defined as Vy Because platforms implement separate power planes for each processor and chipset separate Vcc and V m supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families The GTL inputs require a reference voltage GTLREF that is used by the receivers to determine if a signal is a logical O or a logical 1 GTLREF must be generated on the motherboard see Table 16 for GTLREF specifications Termination resistors Rrr for GTL signals are provided on the processor silicon and are terminated to V7 Intel chipsets will also provide on die termination thus eliminating the need to terminate the bus on the motherboard for most GTL signals 25 m n tel Electrical Specifications 2 6 1 Table 7 26 FSB Signal Groups The front side bus signals have been combined into groups by buffer type GTL input signals have differential input buffers that use GTLREF 1 0 as a reference level In this document the term GTL Input refers to the GTL input group as well as the GTL group when receiving Similarly GTL Output refers to the GTL output group as well as the GTL I O group when driving With the implementation of a source synchronous data bus comes th
113. m mensem nene meme enean 85 5 2 Processor Thermal Features cc cece eee eee eee esee eee see meses ens 85 5 2 1 Thermal MODnItOr ca a RR eo Rd pince tana 85 5 2 2 8 46 1 86 5 2 3 PROGHOTSZ Signaler hee E E ae EE EH Rte ee Iu 86 5 2 4 FORCEPR 5 menn nn nnn nnn 87 Datasheet 3 5 2 5 THERMTRIP Sigrial i eset E RR GARE SERE cated ea PUR RA 88 5 2 6 and Fan Speed Reduction sss mene 88 5 2 7 Thermal Diode sna ra CER WR E C RAN BUT UE X ERI TU 88 6 Featutes op Ea 91 6 1 Power On Configuration Options ccc 91 6 2 Clock Control and Low Power 5 5 eee ee een ened 91 6 2 1 Normal State resi ohare ERRAT CU ERE TK AIT ERR TE ERE RC NE 92 6 2 2 HALT and Enhanced HALT Powerdown States sssssssssseem 92 6 2 2 1 HALT Powerdown 5 92 6 2 2 2 Enhanced HALT Powerdown 5
114. ments Boxed Processor Support and Retention Module SRM The boxed processor TMA requires an SRM assembly provided by the chassis manufacturer The SRM provides the attach points for the TMA and provides structural support for the board by distributing the shock and vibration loads to the chassis base pan The boxed processor TMA will ship with the heatsink attach clip assembly duct and screws for attachment The SRM must be supplied by the chassis hardware vendor Datasheet m 8 Balanced Technology Extended Boxed Processor Specifications n tel Figure 29 8 2 8 2 1 Datasheet See the Support and Retention Module SRM External Design Requirements Document Balanced Technology Extended BTX System Design Guide and the Intel Pentium D Processor Intel Pentium Processor Extreme Edition and Intel Pentium 4 Processor Thermal and Mechanical Design Guidelines for more detailed information regarding the support and retention module and chassis interface and keepout zones Figure 29 illustrates the assembly stack including the SRM Assembly Stack I ncluding the Support and Retention Module Thermal Module Assembly Heatsink amp Fan Clip Structural Duct Motherboard Chassis Pan Electrical Requirements Thermal Module Assembly Power Supply The boxed processor s Thermal Module Assembly TMA requires a 12 V power supply The TMA will include power cable to power the integr
115. mination and must be terminated on the system board RS 2 0 Input RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins lands of all processor FSB agents Datasheet Land Listing and Signal Descriptions Table 25 Datasheet intel Signal Description Sheet 1 of 9 Name RSP Type Input Description RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins lands of all processor FSB agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent ensuring correct parity SKTOCC Output SKTOCC Socket Occupied will be pulled to ground by the processor System board designers may use this signal to determine if the processor is present SMI Input SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begin
116. modulating starting and stopping the internal processor core clocks The Thermal Monitor feature must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor feature is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 5096 Clocks often will not be off for more than 3 0 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to th
117. motherboard to properly decouple the return currents from the front side bus Bulk decoupling must also be provided by the motherboard for proper A GTL bus operation Voltage Identification The Voltage Identification VI D specification for the processor is defined by the Voltage Regulator Down VRD 10 1 Design Guide For Desktop and Transportable LGA775 Socket The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC pins see Chapter 2 5 3 for Vcc overshoot specifications Refer to Table 14 for the DC specifications for these signals A minimum voltage for each processor frequency is provided in Table 4 Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings This is reflected by the VID Range values provided in Table 4 Refer to the Intel Pentium D Processor 900 Sequence and Intel Pentium Processor Extreme Edition 955 965 Specification Update for further details on specific valid core frequency and VID values of the processor Note that this differs from the VID employed by the processor during a power management event Enhanced Intel SpeedStep technology or Enhanced HALT State The processor uses 6 voltage identification signals VID 5 0 to support automatic selection of power supply voltages Table 2 specifies the voltage level corresponding to the state of VID 5 0 A 1 in this t
118. n Option Signals mmm emen 91 34 Fan Heatsink Power and Signal 5 eee eee eee ee eee nee need 98 35 TMA Power and Signal 5 emen memes 106 36 TMA Set Points for 3 wire operation of BTX Type and Type Boxed Processors 109 6 Datasheet Revision HistoryRevision History Revision Number Description Date 001 Initial release December 2005 002 Added specifications for Intel Pentium D processors 950 940 930 and 920 January 2006 Added specifications for Intel Pentium processor Extreme Edition 965 003 Updated Table 2 13 March 2006 Updated Figures 3 5 and 3 6 004 Added specifications for Intel Pentium D processor 960 May 2006 Added specifications for Intel Pentium D processors 945 and 915 005 Added specifications for the Intel Pentium D processors 960 for 775 VR CONFIG 05A July 2006 Mainstream Updated RTT specification in Table 16 GTL Bus Voltage Definitions 006 Added specifications for Intel Pentium D processors 925 September 2006 007 Added specifications for Intel Pentium D processors 935 January 2007 Datasheet 88 intel Intel Pentium D Processor 900 Sequence and Intel Available at 3 46 GHz and
119. n generate a STPCLK while the processor is in the HALT Power Down state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state While in HALT Power Down state the processor will process bus snoops Enhanced HALT Powerdown State Enhanced HALT is a low power state entered when all logical processors have executed the HALT or MWAIT instructions and Enhanced HALT has been enabled via the BIOS When one of the logical processors executes the HALT instruction that logical processor is halted however the other processor continues normal operation The processor will automatically transition to a lower frequency and voltage operating point before entering the Enhanced HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor will first switch to the lower bus ratio and then transition to the lower VID While in Enhanced HALT state the processor will process bus snoops The processor exits the Enhanced HALT state when a break event occurs When the processor exits the Enhanced HALT state it will first transition the VID to the original value and then change the bus ratio back to the original value Stop Grant State When the STPCLK signal is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bu
120. nd number and they show the physical location of each signal on the package land array top view Table 23 is a listing of all processor lands ordered alphabetically by land signal name Table 24 is also a listing of all processor lands the ordering is by land number Datasheet 45 intel Land Listing and Signal Descriptions Figure 11 land out Diagram Top View Left Side 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC 55 55 VEC 55 vss VCC VCC vss VCC VSS vss VCC AM VCC VCC VSS VSS VCC VCC vss vss VCC VCC vss VCC VCC vss vss WEC AL NUG VCC VSS VSS VEC VCC VSS VSS vec vss VCC vcc VSS VSS AK VSS vss vss vss VCC VCC vss vss VCC VCC vss VCC VEG VSS VSS VCC AJ VSS vss vss vss VCC 55 vss VCC VCC vss VCC vss VSS VCC AH VCC VCC VCC VEC VCC VSS vss VEC VCC vss VCC VEC vss VSS VCC AG VCC VCC VCC VEC VCC VSS VSS vcc VCC vss VCC vss VSS VCC AF VSS vss vss vss vss vss vss vss VEC VCC vss VCC VCC VSS VSS VCC AE VSS VSS VSS VSS VSS vss vss VCC VCC VCC vss VCC VEG VSS VSS VCC AD VCC VCC VCC VCC VCC VCC VCC AC VCC VCC VCC VCC VCC VCC VCC VEC AB VSS VSS VSS VSS vss vss vss vss AA VSS vss vss vss VSS vss vss vss Y vcc VCC VCC VCC VCC
121. ns for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal which is an open collector output that pulses at a rate of two pulses per fan revolution A baseboard pull up resistor provides Voy to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The fan heatsink receives a PWM signal from the motherboard from the fourth pin of the connector labeled as CONTROL The boxed processor s fan heatsink requires a constant 12 V supplied to pin 2 and does not support variable voltage control or 3 pin PWM control 97 intel Boxed Processor Specifications The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header identification and location should be documented in the platform documentation or on the system board itself Figure 22 shows the location of the fan power connector relative to the processor socket The baseboard power header should be positioned within 4 33 inches from the center of the processor Socket Figure 21 Boxed Processor Fan Heatsink Power Cable Connector Description Straight square pin 4 pin terminal housing with 1 GND polarizing ribs and friction locking ramp 2 12V ere 0 100 pitch 0 025 square pin width 3
122. occupied by the processor heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides 8 111 112 Debug Tools Specifications Datasheet
123. ocessor Top View 95 0 I gt 3 74 a 95 0 3 74 w NOTES 1 Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation Datasheet m 8 Boxed Processor Specifications n tel Figure 20 7 1 2 7 1 3 7 2 7 2 1 Note Datasheet Space Requirements for the Boxed Processor Overall View Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams See Chapter 5 and the Intel Pentium D Processor Intel Pentium Processor Extreme Edition and Intel Pentium 4 Processor Thermal and Mechanical Design Guidelines for details on the processor weight and heatsink requirements Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly The boxed processor thermal solution requires a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket The boxed processor will ship with the heatsink attach clip assembly Electrical Requirements Fan Heatsink Power Supply The boxed processor s fan heatsink requires a 12 V power supply A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard The power cable connector and pinout are shown in Figure 21 Baseboards must provide a matched power header to support the boxed processor Table 34 contains specificatio
124. ocessor Extreme Edition 955 965 on 65 nm process in the 775 land LGA package Processor in the FC LGA6 package with two 2 MB L2 caches Intel Pentium D processor 900 sequence on 65 nm process in the 775 land LGA package Processor in the FC LGA6 package with two 2 MB L2 caches Processor For this document the term processor is the generic term for the Intel Pentium D processor 900 sequence and Intel Pentium processor Extreme Edition 955 965 Keep out zone The area on or near the processor that system design can not use Intel 945G 945GZ 945P 945PL Express chipsets Chipset that supports DDR2 memory technology for the processor Intel 955X Express chipset Chipset that supports DDR2 memory technology for the processor 1 Total accessible size of L2 caches may vary by one cache line pair 128 bytes depending on usage and operating environment 12 Datasheet Introduction 1 2 Table 1 Datasheet intel Intel 975X Express chipset Chipset that supports DDR2 memory technology for the processor Processor core Processor core die with integrated L2 cache LGA775 socket The processor mates with the system board through a surface mount 775 land LGA socket I ntegrated heat spreader I HS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface
125. of the VR Note that assertion of the FORCEPR does not automatically assert PROCHOT As mentioned previously the PROCHOTZ signal is asserted when a high temperature situation is detected A minimum pulse width of 500 us is recommend when the FORCEPR is asserted by the system Sustained activation of the FORCEPR pin may cause noticeable platform performance degradation One application is the thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting FORCEPRZ pulled low and activating the TCC the VR can cool down as a result of reduced processor power consumption FORCEPR can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on FORCEPR only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power With a properly designed and characterized thermal solution it is anticipated that FORCEPR would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of FORCEPR in the anticipated ambient environment may cause a no
126. on at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins lands of all processor FSB agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST ITP CLK 1 0 Input ITP CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board ITP CLK 1 0 are used as BCLK 1 0 references for a debug port implemented on an interposer If a debug port is implemented in the system CLK 1 0 are no connects in the system These are not processor signals LINT 1 0 Input LINT 1 0 Local APIC Interrupt must connect the appropriate pins lands of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the previous Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these signals as LINT 1 0 is the default configuration LL ID 1 0 Output The LL ID 1 0
127. on software usage of this mechanism to limit the processor temperature If bit 4 of the ACPI P_CNT Control Register located in the processor 1A32_THERM_CONTROL MSR is written to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same ACPI CNT Control Register In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 596 increments On Demand mode may be used in conjunction with the Thermal Monitor If the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor core temperature has reached its maximum operating temperature If the Thermal Monitor is enabled note that the Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the Intel Architecture Software Developer s Manuals for specific register and programming details PROCHOT can be configured via BIOS as an
128. or FSB agents The following table defines the coverage model of these signals Request Signals Subphase 1 Subphase 2 A 35 24 APO AP1 A 23 3 AP1 APO REQ 4 0 AP1 APO Datasheet Land Listing and Signal Descriptions Table 25 Datasheet intel Signal Description Sheet 1 of 9 Name BCLK 1 0 Type Input Description The differential pair BCLK Bus Clock determines the FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss BINIT Input Output BINIT Bus Initialization may be observed and driven by all processor FSB agents and if used must connect the appropriate pins lands of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT activation Once the BINIT assertion has been observed the bus agents will re arbitrate for the FSB and attempt completion of their bus queue and I OQ entries If BINIT observation is disabled durin
129. orm Termination 49 9 0 99 49 9 49 9 1 01 W 5 COMP Resistance i i NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 GTLREF is to be generated from by a voltage divider of 1 resistors one divider for each GTLREF land Refer to the applicable platform design guide for additional implementation details 3 These pull ups are to Vr 4 Ry is the on die termination resistance measured at 2 of the GTL output driver The IMPSEL pin is used to select a 50 Q or 60 Q buffer and Ry value 5 COMP resistance must be provided on the system board with 1 resistors COMP 3 0 resistors are to Vss COMP 7 4 resistors are to Datasheet 31 intel 2 7 Clock Specifications Electrical Specifications 2 7 1 Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the processor core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier will be set at its default ratio during manufacturing Refer to Table 17 for the processor supported ratios The processor uses a differential clocking implementation For more information on the processor clocking contact your Intel field representative Table 17 Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB F
130. orting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to volume 3 of the Intel Architecture Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note FORCEPR Input The FORCEPR input can be used by the platform to force the processor both cores to activate the Thermal Control Circuit TCC The TCC will remain active until the system deasserts FORCEPR GTLREF 1 0 Input GTLREF 1 0 determine the signal reference level for GTL input signals GTLREF is used by the GTL receivers to determine if a signal is a logical 0 or logical 1 HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR Output IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transac
131. ource Synch Input Output A5 M5 Source Synch Input Output D10 B10 Source Synch Input Output A6 LA Source Synch Input Output D11 C11 Source Synch Input Output 74 M4 Source Synch Input Output D12 D8 Source Synch Input Output A8 R4 Source Synch Input Output D13 B12 Source Synch Input Output A9 T5 Source Synch Input Output D14 C12 Source Synch Input Output ADS D2 Common Clock Input Output D15 D11 Source Synch Input Output ADSTBO Source Synch Input Output 164 G9 Source Synch Input Output Datasheet Land Listing and Signal Descriptions Datasheet intel Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name xd ii odia Direction Land Name pede Direction D17 F8 Source Synch Input Output D5 Source Synch Input Output D18 F9 Source Synch Input Output D50 A14 Source Synch Input Output D19 E9 Source Synch Input Output D51 C15 Source Synch Input Output D2 A4 Source Synch Input Output D52 C14 Source Synch Input Output D20 D7 Source Synch Input Output D53 B15 Source Synch Input Output D21 E10 Source Synch Input Output D54 C18 Source Synch Input Output D22 D10 Source Synch Input Output D55 B16 Source Synch Input Output D23 F11 Source Synch Input Output D56 A17 Source Syn
132. ower Other Output RESERVED AE6 FC19 B13 Power Other Output RESERVED AH2 FC22 13 Power Other Output RESERVED C9 FC9 D23 Power Other Output RESERVED D1 FC7 G5 Power Other Output RESERVED D14 FC20 E5 Power Other Output RESERVED D16 FORCEPR AK6 Asynch GTL Input RESERVED E23 FERRZ PBEZ R3 Asynch GTL Output RESERVED E6 GTLREFO H1 Power Other Input RESERVED E7 GTLREF1 H2 Power Other Input RESERVED F23 HIT D4 Common Clock Input Output RESERVED F29 HITM E4 Common Clock Input Output RESERVED G10 IERR AB2 Asynch GTL Output RESERVED G6 IGNNEZ N2 Asynch GTL Input RESERVED N4 IMPSEL F6 Power Other Input RESERVED N5 INIT P3 Asynch GTL Input RESERVED P5 ITP_CLKO AK3 TAP Input RESET G23 Common Clock Input ITP CLK1 AJ3 TAP Input RSO B3 Common Clock Input LINTO K1 Asynch GTL Input RS1 F5 Common Clock Input LINT1 L1 Asynch GTL Input RS2 A3 Common Clock Input LL IDO V2 Power Other Output RSP H4 Common Clock Input LL ID1 AA2 Power Other Output SKTOCC AE8 Power Other Output LOCK C3 Common Clock Input Output SMI 4 P2 Asynch GTL Input MCERR AB3 Common Clock Input Output STPCLK M3 Asynch GTL Input MSIDO W1 Power Other Output TCK AE1 TAP Input MSID1 V1 Power Other Output TDI AD1 TAP Input PROCHOT AL2 Asynch GTL Input Output TDO AF1 TAP Output PWRGOOD N1 Power Other Input TESTHIO F26 Power Other Input Datasheet Land Listing an
133. ration limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes Vcc Core voltage with respect to Vss 0 3 1 55 V FSB termination voltage with VIE respect to Vss ie 133 LEG See See 7 Tc Processor case temperature Chapter 5 Chapter 5 C l Tstorace Processor storage temperatu
134. rce Synch Input Output V4 A153 Source Synch Input Output Li v35 EOWEH GERE V5 A143 Source Synch Input Output X8 VER Power Other V6 VSS Power Other V7 VSS Power Other V8 Power Other W1 MSIDO Power Other Output W2 TESTHI12 Power Other Input W23 Power Other W24 VCC Power Other W25 VCC Power Other W26 Power Other W27 VCC Power Other W28 VCC Power Other W29 VCC Power Other W3 TESTHI1 Power Other Input W30 Power Other 69 Table 25 70 Land Listing and Signal Descriptions Alphabetical Signals Reference Signal Description Sheet 1 of 9 Name Type Description A 35 3 Input Output A 35 3 Address define a 238 pyte physical memory address space In sub phase 1 of the address phase these signals transmit the address of a transaction In sub phase 2 these signals transmit transaction type information These signals must connect the appropriate pins lands of all agents on the processor FSB A 35 3 are protected by parity signals AP 1 0 A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processor samples a subset of the A 35 3 signals to determine power on configuration See Section 6 1 for more details A20M Input If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and
135. re 40 85 oCo ideo NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any tray or packaging 5 Failure to adhere to this specification can affect the long term reliability of the processor 19 m n tel Electrical Specifications 2 5 2 DC Voltage and Current Specification Table 4 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 2 VID Range VID 1200 13375 V Processor number VCC for 775 VR CONFIG 05B Performance Extreme Edition 965 3 73 GHz Extreme Edition 955 3 46 GHz 960 3 60 GHz 950 3 40 GHz V 940 3 20 GHz Refer to Table 5 and y 4 5 6 25 Processor number Vcc for 775 VR CONFIG 05A Figure 1 Mainstream 960 3 60 GHz 950 945 3 40 GHz 940 935 3 20 GHz 930 925 3 00 GHz 920 915 2 80 GHz Processor number Icc for 775 VR CONFIG 05B Performance Extreme Edition 965 3 73 GHz 125 Ex
136. recommend operation of the thermal diode under reverse bias 2 Same as Irwin Table 29 3 Characterizedacross a range of 50 80 C 4 Not 10096 tested Specified by design characterization 5 The ideality factor nQ represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current Ic Ig e 9Vse nokT _ 7 Where ls saturation current q electronic charge Vgg voltage across the transistor base emitter junction same nodes as VD k Boltzmann Constant and T absolute temperature Kelvin 6 The series resistance Ry provided in the Diode Model Table Table 29 can be used for more accurate readings as needed When calculating a temperature based on thermal diode measurements a number of parameters must be either measured or assumed Most devices measure the diode ideality and assume a series resistance and ideality trim value although some are capable of also measuring the series resistance Calculating the temperature is then accomplished using the equations listed under Table 29 In most temperature sensing devices an expected value for the diode ideality is designed in to the temperature calculation equation If the designer of the temperature sensing device assumes a perfect diode the ideality value also called Nirim will be 1 000 Given that most diodes are not perfect the designers usually select an Nirim value that more closely matches the behavior of the diodes
137. requency Core Frequency 200 MHz BCLK 800 MHz FSB Core Frequency 266 MHz BCLK 1066 MHz FSB Notes 1 12 2 40 GHz 3 20 GHz 1 13 2 60 GHz 3 46 GHz 1 14 2 80 GHz 3 73 GHz 1 15 3 GHz 4 GHz 1 16 3 20 GHz 4 26 GHz 1 17 3 40 GHz 4 53 GHz 1 18 3 60 GHz 4 80 GHz 1 19 3 80 5 06 GHz 1 20 4 GHz RESERVED 1 21 4 20 GHz RESERVED 1 22 4 40 GHz RESERVED 1 23 4 60 GHz RESERVED 1 24 4 80 GHz RESERVED 1 25 5 GHz RESERVED NOTES 1 Individual processors operate on y at or below the rated frequency 2 Listed frequencies are not necessarily committed production frequencies 2 7 2 FSB Frequency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 Table 18 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency The Pentium D processor 900 sequence operates at 800 MHz FSB frequency selected by a 200 MHz BCLK 1 0 frequency The Pentium processor Extreme Edition 955 965 operate at 1066 MHz FSB frequency selected by a 266 MHz BCLK 1 0 frequency 32 Datasheet 8 Electrical Specifications n tel Table 18 2 7 3 Datasheet BSEL 2 0 Frequency Table for BCLK 1 0
138. rocessor Extreme Edition and Intel Pentium 4 Processor Thermal and Mechanical Design Guidelines for further guidance Mechanical Representation of the Boxed Processor S le NOTE The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Mechanical Specifications Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor The boxed processor will be shipped with an unattached fan heatsink Figure 17 shows a mechanical representation of the boxed processor 95 m n tel Boxed Processor Specifications Figure 18 Figure 19 96 Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 18 Side View and Figure 19 Top View The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs Airspace requirements are shown in Figure 23 and Figure 24 Note that some figures have centerlines shown marked with alphabetic designations to clarify relative dimensioning Space Requirements for the Boxed Processor Side View applies to all four side views 95 0 I B A 81 3 3 2 10 0 25 0 y 0 39 0 98 v A Space Requirements for the Boxed Pr
139. rrent frequency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals 55 Datasheet m 8 Boxed Processor Specifications n tel 7 Note Figure 17 7 1 7 1 1 Datasheet Boxed Processor Specifications The Intel Pentium D processor 900 sequence and the Intel Pentium processor Extreme Edition 955 965 will also be offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from baseboards and standard components The boxed processor will be supplied with a cooling solution This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor This chapter is particularly important for OEMs that manufacture baseboards for system integrators Unless otherwise noted all figures in this chapter are dimensioned in millimeters and inches in brackets Figure 17 shows a mechanical representation of a boxed processor Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designers responsibility to consider their proprietary cooling solution when designing to the required keep out zone on their system platforms and chassis Refer to the Intel Pentium D Processor Intel Pentium P
140. s Bus Signal DBI3 D 63 48 DBI2 D 47 32 DBI1 D 31 16 DBIO D 15 0 Datasheet Land Listing and Signal Descriptions intel Table 25 Signal Description Sheet 1 of 9 Name DBR Type Output Description DBR Debug Reset is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal DBSY Input Output DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is de asserted This signal must connect the appropriate pins lands on all processor FSB agents DEFER DP 3 0 Input Input Output DEFER is asserted by an agent to indicate that a transaction cannot be ensured in order completion Assertion of DEFER is normally the responsibility of the addressed memory or input output agent This signal must connect the appropriate pins lands of all processor FSB agents DP 3 0 Data parity provide parity protection for the D 63 0 signals They are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins lands of all processor FSB agents DRDY Input Output DRDY Data Ready is asser
141. s cycle Since the GTL signals receive power from the FSB these signals should not be driven allowing the level to return to V for minimum power drawn by the termination resistors in this state In addition all other input signals on the FSB should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the Stop Grant state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB see Section 6 2 4 While in the Stop Grant State SMI 4 INIT BINIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal State Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process a FSB snoop 93 intel DS 6 2 4 1 6 2 4 2 6 2 5 Note 94 Enhanced HALT Snoop or HALT Snoop State Stop Grant Snoop State The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state If Enhanced HALT state is not enabled in the BIOS the default Snoop State entered will be the HALT Snoop State Refer to the following sections for
142. s permitted to exceed the thermal profile but the diode temperature must remain at or below Systems that implement fan speed control must be designed to take these conditions in to account Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications To determine a processor s case temperature specification based on the thermal profile it is necessary to accurately measure processor power dissipation Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions Refer to the Intel Pentium D Processor Intel 81 Table 26 Processor Thermal Specifications Core Thermal M Processor Number Frequency Design erty d a Te Notes GHz Power W c Extreme Edition 965 3 73 GHz 130 5 l 2 Extreme Edition 955 3 46 GHz 130 5 des 960 3 60 GHz 130 5 sec Table 27 be and Figure 13 950 3 40 GHz 130 5 1 2 940 3 20 GHz 130 5 ds 960 3 60 GHz 95 5 a2 950 945 3 40 GHz 95 5 Ay See Table 28 940 935 3 20 GHz 95 5 and Figure 14 930 925 3 GHz 95 5 te 920 915 2 80 GHz 95 5 1 2 NOTES 1 Thermal Design Power TDP should be used for processor thermal solution design targets The TDP is not the maximum power that the processor can dissipate 2 This table shows the maximum TDP for a given frequency range Individual processors may have a lower TDP Therefore the maximum Tc will vary depending on the TDP of
143. s program execution from the SMM handler If SMI is asserted during the de assertion of RESET the processor will tri state its outputs STPCLK Input STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is de asserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK Input TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDO Input Output TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for J TAG specification support TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support TESTHI 13 0 Input TESTHI 13 0 must be connected to the processor s appropriate power source refer to OUT LEFT and VIT OUT RIGHT signal description through a resistor for proper processor operation See Section 2 4 for more details THERMDA Other Thermal Diode Anode See Se
144. t the appropriate pins lands of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps 4 asserted until all of its requests are completed then releases the bus by de asserting BPRI 4 BRO Input Output BRO drives the BREQO signal in the system and is used by the processor to request the bus During power on configuration this signal is sampled to determine the agent ID 0 This signal does not have on die termination and must be terminated 71 Table 25 72 intel Land Listing and Signal Descriptions Signal Description Sheet 1 of 9 Name BSEL 2 0 Type Output Description The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor input clock frequency Table 18 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency For more information about these signals including termination recommendations refer to Section 2 7 2 Analog COMP 3 2 1 0 must be terminated to Vss on the system board using precision resistors COMP 7 6 5 4 must be terminated to on the system board using precision resistors
145. tate This is the normal operating state for the processor HALT and Enhanced HALT Powerdown States The processor supports the HALT or Enhanced HALT powerdown state The Enhanced HALT Powerdown state is configured and enabled via the BIOS The Enhanced HALT state must be enabled via the BI OS for the processor to remain within its specifications The Enhanced HALT state is a lower power state as compared to the Stop Grant State HALT Powerdown State HALT is a low power state entered when all the logical processors have executed the HALT or MWAIT instructions When one of the logical processors executes the HALT instruction that logical processor is halted however the other processor continues normal operation The processor will transition to the Normal state upon the occurrence of SMI BINITZ INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the Intel Architecture Software Developer s Manual Volume III System Programmer s Guide for more information Datasheet Features 6 2 2 2 6 2 3 Datasheet intel The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the Intel Architecture Software Developer s Manual Volume IIl System Programmer s Guide for more information The system ca
146. te as described in the following paragraphs As processor power has increased the required thermal solutions have generated increasingly more noise Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage The 4 wire PWM controlled fan in the TMA solution provides better control over chassis acoustics It allows better granularity of fan speed and lowers overall fan speed than a voltage controlled fan Fan RPM is modulated through the use ef an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL The fan speed is based on a combination of actual processor temperature and thermistor temperature If the 4 wire PWM controlled fan in the TMA solution is connected to a 3 pin baseboard processor fan header it will default back to a thermistor controlled mode allowing compatibility with existing 3 pin baseboard designs Under thermistor controlled mode the fan RPM is automatically varied based on the Tinie temperature measured by a thermistor located at the fan inlet For more details on specific motherboard requirements for 4 wire based fan speed control see the Intel Pentium D Processor Intel Pentium Processor Extreme Edition and Intel Pentium 4 Processor Thermal and Mechanical Design Guidelines 58 109 8 n tel Balanced Technology Extended BTX Boxed Processor Specifications 110 Datasheet
147. ted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be de asserted to insert idle clocks This signal must connect the appropriate pins lands of all processor FSB agents DSTBN 3 0 Input Output DSTBN 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBNO D 31 16 DBI1 DSTBN1 D 47 32 DBI2 DSTBN2 D 63 48 34 DSTBN3 DSTBP 3 0 Input Output DSTBP 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48 DBI3 DSTBP3 FCx Other FC signals are signals that are available for compatibility with other processors Datasheet 73 intel Land Listing and Signal Descriptions Table 25 Signal Description Sheet 1 of 9 Name FERR PBE Type Output Description FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error rep
148. tem can run directly it removes the need for binary translation Thus it helps eliminate associated performance overhead and vastly simplifies the design of the VMM in turn allowing VMMs to be written to common standards and to be more robust See the Intel Virtualization Technology Specification for the 32 Intel Architecture for more details The processor includes an address bus powerdown capability which removes power from the address and data signals when the FSB is not in use This feature is always enabled on the processor Terminology A 3t symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Front Side Bus refers to the interface between the processor and system core logic a k a the chipset components The FSB is a multiprocessing interface to processors memory and I O Processor Packaging Terminology Commonly used terms are explained here for clarification Intel Pentium pr
149. ther AC23 Power Other AF8 Power Other AC24 Power Other AF9 Power Other VCC AC25 Power Other AG11 Power Other 26 Power Other AG12 Power Other VCC AC27 Power Other AG14 Power Other VCC AC28 Power Other AG15 Power Other AC29 Power Other AG18 Power Other VCC 30 Power Other AG19 Power Other VCC AC8 Power Other AG21 Power Other AD23 Power Other AG22 Power Other VCC AD24 Power Other AG25 Power Other VCC AD25 Power Other AG26 Power Other VCC AD26 Power Other 27 Power Other AD27 Power Other AG28 Power Other AD28 Power Other AG29 Power Other 51 52 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name dr dd Direction Land Name pc a Direction VCC AG30 Power Other VCC AK19 Power Other VCC AG8 Power Other VCC AK21 Power Other VCC AG9 Power Other VCC AK22 Power Other VCC AH11 Power Other VCC 25 Power Other VCC AH12 Power Other VCC AK26 Power Other VCC AH14 Power Other VCC AK8 Power Other VCC AH15 Power Other VCC AK9 Power Other VCC AH18 Power Other VCC AL11 Power Other VCC AH19 Power Other VCC AL12 Power Ot
150. ther AL16 VSS Power Other AK11 VCC Power Other AL17 VSS Power Other AK12 VCC Power Other AL18 VCC Power Other AK13 vss Power Other AL19 VCC Power Other AK14 Power Other AL2 PROCHOT Asynch GTL Input Output AK15 VCC Power Other AL20 VSS Power Other AK16 VSS Power Other AL21 VCC Power Other AK17 VSS Power Other AL22 Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Signal Buffer Direction Land Land Signal Buffer Direction Name Type d Name Type AL23 VSS Power Other AM29 Power Other AL24 VSS Power Other AM3 VID2 Power Other Output AL25 VCC Power Other AM30 Power Other AL26 VCC Power Other AMA VSS Power Other AL27 VSS Power Other AM5 FC11 Power Other Output AL28 VSS Power Other AM6 VITPWRGD Power Other Input AL29 VCC Power Other AM7 FC12 Power Other Output AL3 VSS Power Other AM8 Power Other AL30 Power Other AM9 Power Other ALA VID5 Power Other Output AN1 VSS Power Other AL5 VID1 Power Other Output AN10 VSS Power Other AL6 VID3 Power Other Output AN11 Power Other AL7 VSS Power Other AN12 Power Other AL8 VCC Power Other AN13 VSS Power Other AL9 VCC Power Other AN14 Power Other AM1 VSS Power Other AN15 Pow
151. ticeable performance loss Refer to the Voltage Regulator Down VRD 10 1 Design Guide for Desktop Socket 775 for details on implementing the FORCEPR feature 87 m n tel Thermal Specifications and Design Considerations 5 2 5 5 2 6 5 2 7 Table 29 88 THERMTRI P Signal Regardless of whether or not Thermal Monitor is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 25 At this point the FSB signal THERMTRIP will go active and stay active as described in Table 25 THERMTRIP activation is independent of processor activity and does not generate any bus cycles and Fan Speed Reduction is a temperature specification based on a temperature reading from the thermal diode The value for TcontRo Will be calibrated in manufacturing and configured for each processor When Tpiope is above then Tc must be at or below Tc wax as defined by the thermal profile in Table 27 and Figure 13 otherwise the processor temperature can be maintained at TconTtroL or lower as measured by the thermal diode The purpose of this feature is to support acoustic optimization through fan speed control Contact your Intel representative for further details and documentation Thermal Diode The processor incorporates an on die PNP transistor whose b
152. tion without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations See http www intel com technology intel64 index htm for more information including details on which processors support Intel 64 or consult with your system vendor for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality ntel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Not all specified units of this processor support Enhanced HALT State and Enhanced Intel SpeedStep Technology See the Processor Spec Finder at http processorfinder intel com or contact your Intel representative for more information Intel Pentium Intel NetBurst Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property
153. tion may optionally be converted to an external error signal e g NMI by system core logic The processor will keep ERR asserted until the assertion of RESET This signal does not have on die termination Refer to Section 2 5 2 for termination requirements 4 Input IGNNEZ Ignore Numeric Error is asserted to the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is de asserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error GNNE has no effect when the NE bit in control register 0 CRO is set IGNNEZ is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction IMPSEL Input IMPSEL input will determine whether the processor uses a 50 Q or 60 Q buffer This pin must be tied to GND on 500 platforms and left as NC on 60 Q platforms 74 Datasheet Land Listing and Signal Descriptions Table 25 Datasheet intel Signal Description Sheet 1 of 9 Name INIT Type Input Description INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins executi
154. treme Edition 955 3 46 GHz sd m 125 960 3 60 GHz 125 950 3 40 GHz 125 940 3 20 GHz 125 lec A Processor number lcc for 775 VR CONFIG 05A Mainstream 960 3 60 GHz 100 950 945 3 40 GHz m d 100 940 935 3 20 GHz 100 930 925 3 00 GHz 100 920 915 2 80 GHz 100 20 Datasheet Electrical Specifications n tel Table 4 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 2 Processor number Icc when PWRGOOD and RESET are active for 775 CONFIG 05B Performance Extreme Edition 965 3 73 GHz m 125 Extreme Edition 955 3 46 GHz 125 960 3 60 GHz 125 950 3 40 GHz 125 940 3 20 GHz 125 3 l A EC RESET Processor number Icc when PWRGOOD and RESET are active for 775 CONFIG 05A Mainstream 960 3 60 GHz zs 100 950 945 3 40 GHz 100 940 935 3 20 GHz 100 930 925 3 00 GHz 100 920 915 2 80 GHz 100 Processor number Icc Stop Grant for 775_VR_CONFIG_05B Performance Extreme Edition 965 3 73 GHz 70 Extreme Edition 955 3 46 GHz 70 960 3 60 GHz 70 950 3 40 GHz 70 940 3 20 GHz 70 A 191011 Processor number Icc Stop Grant for 775 CONFIG 05A Mainstream 960 3 60 GHz En 50 950 945 3 40 GHz 50 940 935 3 20 GHz 50 930 925 3 00 GHz 50 920 915 2 80 GHz 50 Datasheet 21 m n tel Electrical Specifications Table 4 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 2 Proc
155. ufacturing and can not be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Enhanced Intel SpeedStep technology or Enhanced HALT State These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 3 and Table 2 for more information The voltage specification requirements are measured across VCC SENSE and VSS SENSE lands at the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe Refer to Table 5 and Figure 1 for the minimum typical and maximum Vec allowed for a given current The processor should not be subjected to any Vcc and I cc combination wherein Vcc exceeds Vcc max for a given current Icc max Specification is based on Vcc Maximum loadline Refer to Figure 1 for details lcc iS specified while RESET is active The current specified is also for AutoHALT State 10 1 and ENHANCED_AUTO_HALT 316 Specified at and Tc 50 C 11 12 13 14 22 These parameters are based on design characterizat
156. um Processor Extreme Edition and Intel Pentium 4 Processor Thermal and Mechanical Design Guidelines The boxed processor will ship with a component thermal solution Refer to Chapter 7 for details on the boxed processor Thermal Specifications To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature Tc specifications when operating at or below the Thermal Design Power TDP value listed per frequency in Table 26 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the Intel Pentium D Processor Intel Pentium Processor Extreme Edition and Intel Pentium 4 Processor Thermal and Mechanical Design Guidelines The processor uses a methodology for managing processor temperatures that is intended to support acoustic noise reduction through fan speed control Selection of the appropriate fan speed will be based on the temperature reported by the processor s Thermal Diode If the diode temperature is greater than or equal to then the processor case temperature must remain at or below the temperature as specified by the thermal profile If the diode temperature is less than Tcowrao then the case temperature i
157. until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 Input Output REQ 4 0 Request Command must connect the appropriate pins lands of all processor FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTBO Refer to the AP 1 0 signal description for a details on parity checking of these signals RESET Input Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after Vcc and BCLK have reached their proper specifications On observing active RESET all FSB agents will de assert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 6 1 This signal does not have on die ter
158. ut Output A15 VSS Power Other AA5 A23 Source Synch Input Output A16 DSTBN3 Source Synch Input Output AA6 VSS Power Other A17 D56 Source Synch Input Output AA7 VSS Power Other A18 VSS Power Other AA8 Power Other A19 D61 Source Synch Input Output AB1 VSS Power Other A2 VSS Power Other AB2 IERR Asynch GTL Output A20 RESERVED AB23 VSS Power Other A21 VSS Power Other AB24 VSS Power Other A22 D62 Source Synch Input Output AB25 VSS Power Other A23 VCCA Power Other AB26 VSS Power Other A24 VSS Power Other AB27 VSS Power Other A25 VIT Power Other AB28 VSS Power Other A26 Power Other AB29 VSS Power Other A27 VIT Power Other AB3 MCERR Common Clock Input Output A28 VIT Power Other AB30 VSS Power Other A29 VIT Power Other ABA A26 Source Synch Input Output A3 RS2 Common Clock Input AB5 A24 Source Synch Input Output A30 VIT Power Other AB6 17 Source Synch Input Output 4 DO2 Source Synch Input Output AB7 VSS Power Other A5 DO4 Source Synch Input Output AB8 Power Other A6 VSS Power Other AC1 TMS TAP Input A7 DO7 Source Synch Input Output AC2 DBR Power Other Output A8 DBIO Source Synch Input Output AC23 Power Other A9 VSS Power Other AC24 Power Other AAI HEU Powar Other Output AC25 Power Other AC26 Power Other AA2 LL ID1 Power Other Output AC27 Power Other BA Sess AC28 Power Other Ane uw Jj AC29 VCC Power Other AA25 V
159. ximum Power Maximum Power Maximum W Tc C W Tc C W Tc C W Tc C 0 43 9 34 50 4 68 56 8 102 63 3 2 44 3 36 50 7 70 57 2 104 63 7 4 44 7 38 51 1 72 57 6 106 64 0 6 45 0 40 51 5 74 58 0 108 64 4 8 45 4 42 51 9 76 58 3 110 64 8 10 45 8 44 52 3 78 58 7 112 65 2 12 46 2 46 52 6 80 59 1 114 65 6 14 46 6 48 53 0 82 59 5 116 65 9 16 46 9 50 53 4 84 59 9 118 66 3 18 47 3 52 53 8 86 60 2 120 66 7 20 47 7 54 54 2 88 60 6 122 67 1 22 48 1 56 54 5 90 61 0 124 67 5 24 48 5 58 54 9 92 61 4 126 67 8 26 48 8 60 55 3 94 61 8 128 68 2 28 49 2 62 55 7 96 62 1 130 68 6 30 49 6 64 56 1 98 62 5 32 50 0 66 56 4 100 62 9 Thermal Profile for 775 VR CONFIG 05B Processors Performance 65 0 60 0 e o y 0 19x 43 9 Tcase C 50 0 45 0 20 30 40 50 60 70 80 Power W 90 100 110 120 130 83 a n tel Thermal Specifications and Design Considerations Table 28 Thermal Profile for 775 VR CONFIG 054A Processors Mainstream Power W Tu Power W joie Power W 0 43 4 34 50 5 68 57 7 2 43 8 36 51 0 70 58 1 4 44 2 38 51 4 72 58 5 6 44 7 40 51 8 74 58 9 8 45 1 42 52 2 76 59 4 10 45 5 44 52 6 78 59 8 12 45 9 46 53 1 80 60 2 14 46 3 48 53 5 82 60 6 16 46 8 50 53 9 84 61 0 is 472 52 543 86 615 20 47 6 54 54 7 88 61 9 22 48 0 56 55 2 90 62 3 24 484 58 5

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