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Intel Xeon X3370

1. Land Name Land ee M Direction Land Name Land T Direction VCC AC25 Power Other VCC AG18 Power Other VCC AC26 Power Other VCC AG19 Power Other VCC AC27 Power Other VCC AG21 Power Other VCC AC28 Power Other VCC AG22 Power Other VCC AC29 Power Other VCC AG25 Power Other VCC AC30 Power Other VCC AG26 Power Other VCC AC8 Power Other VCC AG27 Power Other VCC AD23 Power Other VCC AG28 Power Other VCC AD24 Power Other VCC AG29 Power Other VCC AD25 Power Other VCC AG30 Power Other VCC AD26 Power Other VCC AG8 Power Other VCC AD27 Power Other VCC AG9 Power Other VCC AD28 Power Other VCC AH11 Power Other VCC AD29 Power Other VCC AH12 Power Other VCC AD30 Power Other VCC AH14 Power Other VCC AD8 Power Other VCC AH15 Power Other VCC AE11 Power Other VCC AH18 Power Other VCC AE12 Power Other VCC AH19 Power Other VCC AE14 Power Other VCC AH21 Power Other VCC AE15 Power Other VCC AH22 Power Other VCC AE18 Power Other VCC AH25 Power Other VCC AE19 Power Other VCC AH26 Power Other VCC AE21 Power Other VCC AH27 Power Other VCC AE22 Power Other VCC AH28 Power Other VCC AE23 Power Other VCC AH29 Power Other VCC AE9 Power Other VCC AH30 Power Other VCC AF11 Power Other VCC AH8 Power Other VCC AF12 Power Other VCC AH9 Power Other VCC AF14 Power Other VCC AJ11 Power Other VCC AF15 Power Ot
2. Land Name Land signal Butter Direction Land Name Land Signal Buffer Direction Type Type VCC K28 Power Other VCC U29 Power Other VCC K29 Power Other VCC U30 Power Other VCC K30 Power Other VCC U8 Power Other VCC K8 Power Other VCC V8 Power Other VCC L8 Power Other VCC W23 Power Other VCC M23 Power Other VCC W24 Power Other VCC M24 Power Other VCC W25 Power Other VCC M25 Power Other VCC W26 Power Other VCC M26 Power Other VCC W27 Power Other VCC M27 Power Other VCC W28 Power Other VCC M28 Power Other VCC W29 Power Other VCC M29 Power Other VCC w30 Power Other VCC M30 Power Other VCC w8 Power Other VCC M8 Power Other VCC Y23 Power Other VCC N23 Power Other VCC Y24 Power Other VCC N24 Power Other VCC Y25 Power Other VCC N25 Power Other VCC Y26 Power Other VCC N26 Power Other VCC Y27 Power Other VCC N27 Power Other VCC Y28 Power Other VCC N28 Power Other VCC Y29 Power Other VCC N29 Power Other VCC Y30 Power Other VCC N30 Power Other VCC Y8 Power Other VCC N8 Power Other VCC_MB_ AN5 Power Other Output REGULATION VCC P8 Power Other VCC_SENSE AN3 Power Other Output VCC R8 Power Other B VCCA A23 Power Other VCC T23 Power Other VCCIOPLL C23 Power Other VCC T24 Power Other VCCPLL D23 Power Other VCC T25 Power Other VID_SELECT AN7 Power Other Output VCC T26 Power Other VIDO AM2 Power Other Output VCC T27 Power Other VID1 AL5 Power Other Output VCC T28 Power Other VI D2
3. 62 Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions intel Table 4 2 Numerical Land Assignment Table 4 2 Numerical Land Assignment Sheet 11 of 20 Sheet 12 of 20 Hana Land Name Signal Buffer Direction rand Land Name Signal Buffer Direction Type Type V8 VCC Power Other Y30 VCC Power Other V23 VSS Power Other AA1 VIT OUT RIGHT Power Other Output V24 VSS Power Other AA2 FC39 Power Other V25 VSS Power Other AA3 VSS Power Other V26 VSS Power Other AA4 A21 Source Synch Input Output V27 VSS Power Other AA5 A23 Source Synch Input Output V28 VSS Power Other AA6 VSS Power Other V29 VSS Power Other AAT VSS Power Other v30 VSS Power Other AAB8 VCC Power Other W1 MSIDO Power Other Output AA23 VSS Power Other W2 TESTHI12 FC44 Power Other Input AA24 VSS Power Other w3 TESTHI1 Power Other Input AA25 VSS Power Other wa VSS Power Other AA26 VSS Power Other w5 Al6 Source Synch Input Output AA27 VSS Power Other W6 A18 Source Synch Input Output AA28 VSS Power Other W7 VSS Power Other AA29 VSS Power Other w8 VCC Power Other AA30 VSS Power Other w23 VCC Power Other AB1 VSS Power Other W24 VCC Power Other AB2 IERR Asynch CMOS Output w25 VCC Power Other AB3 FC37 Power Other W26 VCC Power Other ABA A26 Source Synch Input Output W27 VCC Power Other AB5 A24 Source Synch Input
4. MSID1 MSI DO Description 0 0 Dual Core Intel Xeon processor 3000 series 0 1 Reserved 1 0 Reserved 1 1 Reserved Notes 1 The MSID 1 0 signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying Circuitry on the motherboard may use these signals to identify the processor installed These signals are not connected to the processor die A logic 0 is achieved by pulling the signal to ground on the package A logic 1 is achieved by leaving the signal as a no connect on the package RUN Reserved Unused and TESTHI Signals All RESERVED lands must remain unconnected Connection of these lands to Vcc Vss Vr or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 4 for a land listing of the processor and the location of all RESERVED lands In a system level design on die termination has been included by the processor to allow signals to be terminated within the processor silicon Most unused GTL inputs should be left as no connects as GTL termination is provided on the processor silicon However see Table 2 8 for details on GTL signals that do not include on die termination Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing
5. UNLESS OTHERWISE SPECIFIED zs a COMMENTS do 203 C D E mm WAX 0 82 SECTION E E 37 55 37 55 34 34 2 3 2 3 4 242 2 593 MILLIMETERS MIN 33 93 BASIC 34 88 BASIC 16 965 BASIC 17 44 BASIC 1 17 BASIC 1 09 BASIC 31 45 31 45 33 9 33 9 2 2 3 806 2 115 0 74 SYMBOL 1 M 1 j j I j j TOP VIEW FRONT VIEW E E oman B SCALE 50 1 IHS LID Dual Core Intel Xeon Processor 3000 Series Datasheet m n te Package Mechanical Specifications Figure 3 3 Processor Package Drawing Sheet 2 of 3 Li 2v HEET 2 or 3 C88285 1 C88285 DO NOT SCALE DRAWING pev SITE T BRATS NER Al SANTA CLARA CA 95052 8119 Ecne 6 1 om C SCALE 20 1 p te 0 021 p 2200 MISSION COLLEGE BLVD P 0 BOX 58 inte 3 4 F SCALE 60 1 DETAIL DEPARTMENT ATD wma D SCALE 20 1 AA l A ek un I t gt
6. 0g000000000000000 00000000008 4000 OO0O0O0O0000000000009QO0O000000000000000 OOOOOOOOOOOOOOOOQOOOOOOOOOOOO0O0O000 OOOOOOOOOOOO0O0O0O0OQOOOOOOOOOOOOOOOO0 OOO0000000000000090000000000000000 2 E z 5 gz z E g 000000000000000000000000000000000 Fa 000000000000000000000000000000000 S 000000000000000090000000000000000 E 000000000 990000000 S 000000000 000000000 E z 000000000 000000000 000000000 000000000 z P 000000000 000000000 3 000000000 000000000 z o 2 9990909900 i 000000000 amp a 600000000 000000660 z 2 000000000 000000000 E 000000000 000000000 u 000000000 000000000 PERAN 000000000 000000000 s l2l2 3 2 3 2 000000000 o 000000000 2H 2 8 2 600000000 000000000 2ldili 3 s 3 s 000000000000000060000000000000000 M R 000000000000000000000000000000000 OOOOOOOOOOOOOOOOQOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOQOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOQOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOQOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOQOOOOOOOOOOOOOOOO OOOOOO00000000009000000000 X QOO NA i E SYMBOL 2 l 2 DISPLAYED OR MODIFIED WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION MAY NOT BE DISCLOSED REPRODUCED 38 Dual Core Intel Xeon Processor 3000 Series Datasheet Package Mechanical
7. Figure 7 5 Boxed Processor Fan Heatsink Power Cable Connector Description Table 7 1 98 Pin Signal GND 12 V SENSE CONTROL om Straight square pin 4 pin terminal housing with polarizing ribs and friction locking ramp 0 100 pitch 0 025 square pin width Match with straight pin friction lock header on mainboard Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit Notes 12 V 12 volt fan power supply 11 4 12 12 6 V IC Peak fan steady state current draw 3 0 A Average fan steady state current draw 2 0 A Max fan start up current draw 3 0 A Fan start up current draw maximum duration 1 0 Second SENSE SENSE frequency 2 pulses per fan 1 revolution CONTROL 21 25 28 Hz 2 3 Notes 1 Baseboard should pull this pin up to 5 V with a resistor 2 Open drain type pulse width modulated 3 The fan will have a pull up resistor for this signal maximum of 5 25 V Dual Core Intel Xeon Processor 3000 Series Datasheet e Boxed Processor Specifications n tel Figure 7 6 Baseboard Power Header Placement Relative to Processor Socket R110 4 33 4 33 7 3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor 7 3 1 Boxed Processor Cooling Requirements The boxed processor m
8. Table 7 5 4 5 4 1 Thermal Diode Parameters using Transistor Model Symbol Parameter Min Typ Max Unit Notes lew Forward Bias Current 5 200 HA 1 2 lg Emitter Current 5 200 no Transistor deality 0 997 1 001 1 005 3 4 5 Beta 0 391 0 760 3 4 Rr Series Resistance 2 79 4 52 6 24 Q 3 6 NOTES Intel does not support or recommend operation of the thermal diode under reverse bias Same as lpw in Table 5 5 Preliminary data Will be characterized across a temperature range of 50 80 C Not 10096 tested Specified by design characterization The ideality factor nQ represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current lc ls e qVag nakT 4 Where ls saturation current q electronic charge Vgg voltage across the transistor base emitter junction same nodes as VD k Boltzmann Constant and T absolute temperature Kelvin 6 The series resistance R provided in the Diode Model Table Table 5 5 can be used for more accurate readings as needed OB WN ES The Intel Core2 Extreme processor X6800 and Intel Core2 Duo desktop processor E6000 and E4000 sequences do not support the diode correction offset that exists on other Intel processors Thermal Diode Interface Signal Signal Name Land Number Description THERMDA AL1 diode anode THERMDC AK1 diode cathode Platform
9. 5 Specification is at 35 C Tc and typical voltage loadline 6 Specification is at 50 C Tc and typical voltage loadline 76 Dual Core Intel Xeon Processor 3000 Series Datasheet Thermal Specifications and Design Considerations Table 5 2 Thermal Profile Dual Core I ntel amp Xeon Processor 3000 Series with 4 MB L2 Cache ntel Figure 5 1 Thermal Profile Dual Core Intel Xeon Processor 3000 Series with 4 MB L2 Cache Power W ar Tc Power uc Tc Bower aa mi Tc 0 44 7 24 54 8 48 64 9 2 45 5 26 55 6 50 65 7 4 46 4 28 56 5 52 66 5 6 47 2 30 57 3 54 67 4 8 48 1 32 58 1 56 68 2 10 48 9 34 59 0 58 69 1 12 49 7 36 59 8 60 69 9 14 50 6 38 60 7 62 70 7 16 51 4 40 61 5 64 71 6 18 52 3 42 62 3 65 72 0 20 53 1 44 63 2 22 53 9 46 64 0 75 0 Tease C y 0 42x 447 30 40 Power W Dual Core Intel Xeon Processor 3000 Series Datasheet 77 m n tel Thermal Specifications and Design Considerations Table 5 3 Thermal Profile Dual Core Intel Xeon 3070 3060 Processor with 4 MB L2 Cache Power W e Power ww Power pi be 0 43 2 24 49 4 48 55 7 2 43 7 26 50 0 50 56 2 4 44 2 28 50 5 52 56 7 6 44 8 30 51 0 54 57 2 8 45 3 32 51 5 56 57 8 10 45 8 34 52 0 58 58 3 12 46 3 36 52 6 60 58 8 14 46 8 38 53 1 62 59 3 16 47 4 40 53 6 64 5
10. 82 voltage transition back to the normal system operating point Transition of the VID code will occur first to insure proper operation once the processor reaches its normal operating frequency Refer to Figure 5 5 for an illustration of this ordering Thermal Monitor 2 Frequency and Voltage Ordering Temperature Frequency PROCHOT The PROCHOT signal is asserted when a high temperature situation is detected regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode The Thermal Monitor TCC however can be activated through the use of the on demand mode On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems using the processor must not rely on software usage of this mechanism to limit the processor temperature The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor and Thermal Monitor 2 features On Demand mode is intended as a means to reduce system le
11. Clock 1 0 BCLK 1 0 LOCK GTL Source Synchronous to Synchronous O assoc strobe Signals Associated Strobe REQ 4 0 A 16 3 3 ADSTBO A 35 17 3 ADSTB1 D 15 0 DBIO DSTBPO DSTBNO D 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 Dual Core Intel Xeon Processor 3000 Series Datasheet 25 intel Electrical Specifications Table 2 8 FSB Signal Groups Sheet 2 of 2 Signal Group Type Signals GTL Strobes Synchronous to ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 BCLK 1 0 CMOS A20M IGNNE INIT LINTO INTR LINT1 NMI SMI STPCLK PWRGOOD TCK TDI TMS TRST BSEL 2 0 VID 6 1 Open Drain Output FERR PBE IERR THERMTRIP TDO Open Drain PROCHOT 4 Input Output FSB Clock Clock BCLK 1 0 1 TP_CLK 1 0 2 Power Other VCC VTT VCCA VCCIOPLL VCCPLL VSS VSSA GTLREF 1 0 COMP 8 3 0 RESERVED TESTHI 13 0 VCC_SENSE VCC MB REGULATION VSS SENSE VSS MB REGULATION DBR 2 VTT OUT LEFT VIT OUT RIGHT VTT SEL FCx PECI MSID 1 0 Notes 1 Refer to Section 4 2 for signal descriptions 2 n processor systems where no debug port is implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects 3 The value of these signals during the active to inactive edge of RESET defines the
12. Input Output ADSTBO R6 Source Synch Input Output ADSTB1 AD5 Source Synch Input Output BCLKO F28 Clock Input BCLK1 G28 Clock Input BNR C2 Common Clock Input Output 48 Table 4 1 Land Listing and Signal Descriptions Alphabetical Land Assignments Sheet 2 of 20 Land Name Land T Direction BPMO AJ2 Common Clock Input Output BPM1 AJ1 Common Clock Input Output BPM2 AD2 Common Clock Input Output BPM3 AG2 Common Clock Input Output BPM4 AF2 Common Clock Input Output BPM5 AG3 Common Clock Input Output BPRI G8 Common Clock Input BRO F3 Common Clock Input Output BSELO G29 Power Other Output BSEL1 H30 Power Other Output BSEL2 G30 Power Other Output COMPO A13 Power Other Input COMP1 T1 Power Other Input COMP2 G2 Power Other Input COMP3 R1 Power Other Input COMP8 B13 Power Other Input DO B4 Source Synch Input Output D1 C5 Source Synch Input Output D2 A4 Source Synch Input Output D3 C6 Source Synch Input Output D4 A5 Source Synch Input Output D5 B6 Source Synch Input Output D6 B7 Source Synch Input Output D7 A7 Source Synch Input Output D8 A10 Source Synch Input Output D93 A11 Source Synch Input Output D10 B10 Source Synch Input Output D11 C11 Source Synch Input Output D12 D8 Source Synch Input Output D13 B12 Source Synch Input Output D14 C12 Source S
13. Table 5 5 apply to traditional thermal sensors that use the Diode Equation to determine the processor temperature Transistor Model parameters Table 5 6 have been added to support thermal sensors that use the transistor equation method The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits This thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor TcoNTROL is a temperature specification based on a temperature reading from the thermal diode The value for Tcontrot Will be calibrated in manufacturing and configured for each processor The Tcontro temperature for a given processor can be obtained by reading a MSR in the processor The Tcontro Value that is read from the MSR needs to be converted from Hexadecimal to Decimal and added to a base value of 50 C The value of Tcontrot may vary from 00 h to 1E h 0 to 30 C When Tp ope is above Tcontrot then Tc must be at or below Tc max as defined by the thermal profile in Table 5 2 otherwise the processor temperature can be maintained at Tcontro or lower as measured by the thermal diode Thermal Diode Parameters using Diode Model Symbol Parameter Min Typ Max Unit Notes lew Forward Bias Current 5 zx 200 HA 1 n Diode Ideality Factor 1 000 1 009 1 050 2 3 4 Ry Series Resi
14. Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary series such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level The phrase Front Side Bus refers to the interface between the processor and system core logic a k a the chipset components The FSB is a multiprocessing interface to processors memory and 1 0 Dual Core Intel Xeon Processor 3000 Series Datasheet 11 intel Introduction 1 1 1 Processor Terminology Commonly used terms are explained here for clarification 12 Dual Core Intel Xeon Processor 3085 3075 3070 3065 and 3060 Dual core processor in the FC LGA package with a 4 MB L2 cache Dual Core Intel Xeon Processor 3050 and 3040 Dual core processor in the FC LGA package with a 2 MB L2 cache Processor For this document the term processor is the generic form of the Dual Core Intel Xeon processor 3000 series The processor is a single package that contains one or more execution units Keep
15. This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 2 4 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 5 and Figure 2 1 as measured across the VCC SENSE and VSS SENSE lands The VRM or VRD used must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 2 4 and Table 2 5 Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further details Dual Core Intel Xeon Processor 3000 Series Datasheet Electrical Specifications Table 2 1 Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 VID V VID6 VID5 VID4 VID3 VID2 VID1 VID V 1 1 1 1 0 1 0 8500 0 1 1 1 1 0 1 2375 1 1 1 1 0 0 0 8625 0 1 1 1 0 1 1 2500 1 1 1 0 1 1 0 8750 0 1 1 1 0 0 1 2625 1 1 1 0 1 0 0 8875 0 1 1 0 1 1 1 2750 1 1 1 0 0 1 0 9000 0 1 1 0 1 0 1 2875 1 1 1 0 0 0 0 9125 0 1 1 0 0 1 1 3000 1 1 0 1
16. Z 0 05 o 23 c DO NOT SCALE DRAWING E T 1 90000000000000000000000000 _ 0009 w 989999899999999099990909900090008 DANING Winoen OOO0O0O0000000000000000000000000000 OoOoOOOOOOOOOOOOOO OOOOOOOOOOOOOOO 000000000000000000000000000000006 DEPARTMENT TD TIRE SITE bue 5 1 OOOOOO0O00000000009000000000000000 O00000000000000000O000000000000000 O0000000000000000000000000000000 900000000 p n 15 1 900000000 00000000 9090000000 1 O0000000 ko O00000000 OOO000000 xm A 02 23 05 DATE DATE FINISH SCALE DATE 02 23 05 DATE QO0000000 OOOOOOOO O00000000 1 00000000 900000000 1 990090000 i 000000000 00000000 000000000 OOOOOOOO Oooooooooo OOOOOOOO 000000000 90000000 BOTTOH VIEW E DESIGNED BY DRAWN BY N WALSH CHECKED BY APPROVED BY WATERTAL 0 203 900000000 00000000 O00000000 O0000000 000000000 000000000 3 c2 Z Uz RANCES M MANUSHARON 4 5H 1994 7 0 08 OO0000000000000000000000000000000 OO0000000000000000000000000000000 OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOO0OOOO0O0O0O000000000 OOOOOOOOOOOOOOOOQOOOOOOOOOOOOOOO QOOOOOOOOOOOOOOO 00O0O0O0O00000000000 6009009009 GO6000906 GG eo b T IHS SEALANT 3 2 HE PACKAGE SUBSTRATE
17. BPM2 TDI vcc vss vss A253 RSVD vss DBR TMS VCC vss A17 A24 A26 FC37 IERR amp vss vcc vss vss A234 A214 vss FC39 VIT OUT RIGHT vcc vss A193 vss A204 FC17 vss FCO VCC vss A183 Al6 VSS TESTHI1 TESTHI12 MSIDO FC44 vcc vss vss Al4 A155 vss RSVD MSID1 vcc vss A103 A123 A13 FC30 FC29 FC28 Vcc vss vss A93 All vss FC4 COMP1 vcc VSS ADSTBO vss A84 FERR P VSS COMP3 BE vcc vss A4 RSVD vss INIT SMI TESTHI11 VCC vss vss RSVD RSVD VSS IGNNE PWRGOOD vcc vss REQ2 A5 A7 STPCLK THERMTAI vss vcc vss vss A33 A63 vss TESTHI13 LINTI VCC vss REQ3 vss REQO A20M amp vss LINTO vec vcc vec vec vec vec vcc vss REQ4 REQI vss FC22 FC3 VIT OUT LEFT vss vss vss vss vss vss vss vss vss TESTHI10 FC35 VSS GTLREF1 GTLREFO D29 D27 DSTBN1 DBI1 FC38 D16 BPRI DEFER RSVD PECI TESTHI9 TESTHI8 COMP2 FC27 FC43 FC42 D28 vss D244 p23 vss Dis pD r vss FC21 RS1 vss BRO FC5 vss D264 DSTBPl vss D21 D194 vss RSVD RSVD FC20 HITM amp TRDY vss rsvp D25 vss D15 amp D22 4 vss D124 D20 vss vss HIT vss ADS RSVD D524 vss D14 p11 vss FC38 DSTBNO vss D3 D1 vss Lock BNR DRDY vss comps Di3 amp vss D10 DSTBPO vss D6 D5 vss Do Rso DBSY vss D50 compo vss po ps vss DBIO D7 VSS D4 D2 RS2 vss 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Dual Core Intel Xeon Processor 3000 Series Datasheet AK AJ AH AG A
18. CO Q0 3 f 08S CV CN Cy AF OOOOOO k2 Z21 ku OOOOO Lu 5 e 2 OO CHOC 3 DOOD O AE O00000 KARANA NU kuz ul AA OOOOO U CO 0 00 Wey AD OOOOOO O La e d lll a aT O3 Ta AC OOOOOO eS P EYA AB OOOOOO kd O 5 CV OWE HC Y 3 O AA OOOOOO O kk FOSC f F Cy Y O O O O O O O i VELEN OC OO a C Ww O VU O WU 2 VN O kuz rn r a an V 200000 Socket 775 O O WY Cy 4 S C U OOOOOO O o6 OO C T 060060 Quadrants O Nan HOY gt R O vZ O hu gt O VU P 2900000 l op View O O FN f82 lt OI N kA IRA AEA k D 6 f M OOOOOO O U CN CN eO S 4S L OOOOOO O O K Ot O O f AAAADAADAD VON J O 20000000000 O O H G 0O000000O00O0O00X O OO x LQQQQQQQY 9290 00 00000 G OC OQOOQOOQOQOOQO OO OOOOO CV y Oy 8 OV S CV V C CY CV CY CV C CN XN ON CN VN ON F WI CA OU UU OQ Au O A O Ae ae ON Q O PANI atela T ODIO OS C f CY OW 0 y 0S DO E Qe O0006000600600 0O C O O O0O 0O D O000000000000000000000000 R amp 00000 J A haz d u cad J J AUD LL SSCY SEIS Tal a CO OG OO 00 00 GO O8 000 C OOOOOO OOOOOOOOOOOOOCO AAA AA OT y Y CYCSC NC YY Y Ti 79 7 y Y 0 B O O OC O O O OC0O0006006060 00 0 OC O O0 OC O O GSGGANOGGAGGOGGGOGGOAOGGOGGGGOC A C O A OOOO0O00O0O0O0O000000000000000000N00 4 T 4 LY 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 V_ Clocks Data 98765432 1 FERPSZ gt g o 0 m
19. D33 VTT VTT VT VT VT VIT VSS VCCPLL D46 VSS D48 DBI2 vss D49 RSVD VSS c VIT VIT VT VT VT VIT VSS VCCIO VSS D58 DBI3 VSS D54 DSTBP3 VSS D51 PLL B VIT VIT VT VT VT VIT VSS VSSA D63 D59 VSS D60 D57 VSS D55 D53 VTT VTT VT VT VT VIT FC23 VCCA D62 VSS RSVD D61 vss D56 DSTBN3 VSS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 46 Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions Figure 4 2 land out Diagram Top View Right Side 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vec vss vec vec vss vec vcc viD sEL vss MB VCC MB vss vcc_ vss vss ECT REGULATION REGULATION SENSE SENSE vec vss vec vec vss vec vcc VID7 FC40 VID6 vss VID2 VIDO vss vec vss vec vec vss vec VCC vss VID3 VID1 VID5 VRDSEL PROCHOT THERMDA vec vss vec vec vss vec vcc vss FC8 vss VID4 ITP CLKO vss THERMDC vec vss vec vec vss vec vcc vss A353 A343 vss ITP_CLK1 BPMO BPM1 vec vss vec vec vss vec VCC vss vss A334 A323 vss RSVD vss vec vss vec vec vss vec vcc vss A29 A31 A30 BPM5 BPM3 TRST vec vss vec vec vss vec vcc vss vss A275 A284 vss BPM4 TDO vec vss vec vec vss vcc sktocc vss RSVD vss RSVD FC18 vss TCK vcc vss A223 ADSTB1 VSS FC36
20. Dual Core Intel Xeon Processor 3000 Series Datasheet m Electrical Specifications n tel Notes Unless otherwise noted all specifications in this table apply to all processor frequencies Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLKO equals the falling edge of BCLK1 The crossing point must meet the absolute and relative crossing point specifications simultaneously Vuavg is the statistical average of the Vi measured by the oscilloscope Vuavg Can be measured directly using Vtop on Agilent oscilloscopes and High on Tektronix oscilloscopes Overshoot is defined as the absolute value of the maximum voltage Undershoot is defined as the absolute value of the minimum voltage Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches It includes input threshold hysteresis er SE ON Urs CO NES Figure 2 7 Differential Clock Crosspoint Specification 650 600 550 500 255 550 0 5 VHavg 700 400 250 4 0 5 VHavg 700 350 Crossing Point mV 300 250 NS 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg mV 2 8 PECI DC Specifi
21. HALT Snoop State Stop Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB After the snoop is serviced the processor returns to the Stop Grant state or HALT Power Down state as appropriate Extended HALT Snoop State Extended Stop Grant Snoop State The Extended HALT Sneep State is the default 5neop State when the Extended HALT state dis enabled via the BFOS The processor will remain in the lower bus ratio and VID operating point of the Extended HALT state or Extended Stop Grant state While in the Extended HALT Snoop State or Extended Stop Grant Snoop State snoops are handled the same way as in the HALT Snoop State or Stop Grant Snoop State After the snoop is serviced the processor will return to the Extended HALT state or Extended Stop Grant state Dual Core Intel Xeon Processor 3000 Series Datasheet Features 6 3 Note intel Enhanced Intel SpeedStep Technology The processor supports Enhanced Intel SpeedStep Technology This technology enables the processor to switch between multiple frequency and voltage points which results in platform power savings Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform Switching between voltage frequency states is software controlled Not all processors are capable of supporting Enhanced Intel SpeedStep Technology More d
22. Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings This is reflected by the VID Range values provided in Table 2 4 Refer to the Dual Core Intel Xeon processor 3000 Series Specification Update for further details on specific valid core frequency and VID values of the processor Note this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Extended HALT State The processor uses six voltage identification signals VID 6 1 to support automatic selection of power supply voltages Table 2 1 specifies the voltage level corresponding to the state of VID 6 1 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty VID 6 1 111111 or the voltage regulation circuit cannot supply the voltage that is requested it must disable itself The Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket defines VID 7 0 VID7 and VIDO are not used on the processor VIDO and VID7 are strapped to Vss on the processor package VIDO and VID7 must be connected to the VR controller for compatibility with future processors The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc
23. Table 4 3 Signal Description Sheet 6 intel of 7 Name Type Description THERMTRI P Output In the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature approximately 20 C above the maximum Tce Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRIP Driving of the THERMTRIP signal is enabled within 10 us of the assertion of PWRGOOD provided Vr and Vcc are valid and is disabled on de assertion of PWRGOOD if Vr or Vcc are not valid THERMTRIP may also be disabled Once activated THERMTRIP remains latched until PWRGOOD Vr or Vcc is de asserted While the de assertion of the PWRGOOD V7 or Vcc will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 us of the assertion of PWRGOOD provided V and Vec are valid TMS Input TMS Test Mode Select is a J TAG specification support signal used by debug tools TRDY Input TRDY Target Ready is asserted by the target to
24. indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins lands of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK de asserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock MSID 1 0 Output These signals indicate the Market Segment for the processor Refer to Table 2 2 for additional information PECI Input Output PECI is a proprietary one wire bus interface See Section 5 4 for details PROCHOT Input Output As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled The TCC will remain active until the system de asserts PROCHOT See Section 5 2 4 for more details PWRGOOD Dual Core Intel Xeon Processor 3000 Series Datasheet Input PWRGOOD Power Good is a processor input The processor requires this signal to
25. n tel 2 7 8 BCLK 1 0 Specifications CK505 based Platforms Table 2 18 Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes VL Input Low Voltage 0 30 N A N A V 2 4 2 Vu Input High Voltage N A N A 1 15 V 2 4 2 Vcross abs Absolute Crossing Point 0 300 N A 0 550 V 2 4 2 5 3 45 AVcross Range of Crossing Points N A N A 0 140 V 2 4 2 5 4 Vos Overshoot N A N A 1 4 V 2 4 6 Vus Undershoot 0 300 N A N A V 2 4 6 Vsw NG Differential Output Swing 0 300 N A N A V 2 6 7 lu Input Leakage Current 5 N A 5 HA Cpad Pad Capacitance 95 1 2 1 45 pF 8 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Steady state voltage not including overshoot or undershoot 3 Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLKO equals the falling edge of BCLK1 4 Vuavg is the statistical average of the Vy measured by the oscilloscope 5 The crossing point must meet the absolute and relative crossing point specifications simultaneously 6 Overshoot is defined as the absolute value of the maximum voltage Undershoot is defined as the absolute value of the minimum voltage 7 Measurement taken from differential waveform 8 Cpad includes die capacitance only No package parasitics are included Figure 2 4 Differential Clock Waveform CLK 0 Vcnoss Median
26. 1 I 0 9250 0 1 1 0 0 0 1 3125 1 1 0 1 1 0 0 9375 0 1 0 1 1 1 1 3250 1 1 0 1 0 1 0 9500 0 1 0 1 1 0 1 3375 1 1 0 1 0 0 0 9625 0 1 0 1 0 1 1 3500 1 1 0 0 1 1 0 9750 0 1 0 1 0 0 1 3625 1 1 0 0 1 0 0 9875 0 1 0 0 1 1 1 3750 1 1 0 0 0 1 1 0000 0 1 0 0 1 0 1 3875 1 1 0 0 0 0 1 0125 0 1 0 0 0 1 1 4000 1 0 1 1 1 1 1 0250 0 1 0 0 0 0 1 4125 1 0 1 1 1 0 1 0375 0 0 1 1 1 1 1 4250 1 0 1 1 0 1 1 0500 0 0 1 1 1 0 1 4375 1 0 1 1 0 0 1 0625 0 0 1 1 0 1 1 4500 1 0 1 0 1 1 1 0750 0 0 1 1 0 0 1 4625 1 0 1 0 1 0 1 0875 0 0 1 0 1 1 1 4750 1 0 1 0 0 1 1 1000 0 0 1 0 1 0 1 4875 1 0 1 0 0 0 1 1125 0 0 1 0 0 1 1 5000 1 0 0 1 1 1 1 1250 0 0 1 0 0 0 1 5125 1 0 0 1 1 0 1 1375 0 0 0 1 1 1 1 5250 1 0 0 1 0 1 1 1500 0 0 0 1 1 0 1 5375 1 0 0 1 0 0 1 1625 0 0 0 1 0 1 1 5500 1 0 0 0 1 1 1 1750 0 0 0 1 0 0 1 5625 1 0 0 0 1 0 1 1875 0 0 0 0 1 1 1 5750 1 0 0 0 0 1 1 2000 0 0 0 0 1 0 1 5875 1 0 0 0 0 0 1 2125 0 0 0 0 0 1 1 6000 0 1 1 1 1 1 1 2250 0 0 0 0 0 0 OFF Dual Core Intel Xeon Processor 3000 Series Datasheet 17 E n tel Electrical Specifications 2 4 Table 2 2 2 5 18 Market Segment dentification MSI D The MSID 1 0 signals may be used as outputs to determine the Market Segment of the processor Table 2 2 provides details regarding the state of MSID 1 0 A circuit can be used to prevent 130 W TDP processors from booting on boards optimized for 65 W TDP Market Segment Selection Truth Table for MSI D 1 0 1 2 3 4
27. 12 FC44 cannot be grouped with other TESTHI signals TESTHI 13 cannot be grouped with other TESTHI signals However utilization of boundary scan test will not be functional if these lands are connected together For optimum noise margin all pull up resistor values used for TESTHI 13 0 lands should have a resistance value within 2096 of the impedance of the board transmission line traces For example if the nominal trace impedance is 50 Q then a value between 40 Q and 60 Q should be used Voltage and Current Specification Absolute Maximum and Minimum Ratings Table 2 3 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to th
28. 2 This table is intended to aid in reading discrete points on Figure 2 2 3 The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details 4 Adherence to this loadline specification is required to ensure reliable processor operation Figure 2 2 Vcc Static and Transient Tolerance for Processors with 2 MB L2 Cache Icc A 0 10 20 30 40 50 60 70 VID 0 000 VID 0 013 4 VID 0 025 4 Vcc Maximum VID 0 038 VID 0 050 4 VID 0 063 4 VID 0 075 4 0 088 4 Vcc V lt iw VID 0 100 4 VID 0 113 4 Vcc Minimum P di VID 0 125 4 VID 0 138 4 VID 0 150 4 VID 0 163 4 VID 0 175 Notes 1 2 3 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 6 3 This loadline specification shows the deviation from the VID set point The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 11 0 Processor Power D
29. 3 o Eo cos 0 Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be updated with characterized data from silicon measurements at a later date Adherence to the voltage specifications for the processor are required to ensure reliable processor operation Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and can not be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Extended HALT State These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 3 and Table 2 1 for more information The voltage specification requirements are measured across VCC SENSE and VSS SENSE lands at the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe Refer to Table 2 5 and Figure 2 1 for the minimum typical and maximum Vcc allowed for a given current Th
30. 75 mV CROSS median 550 mV uus TN eggs V CROSS 7 X A V CROSS In Median 75 mV 300 mV CLK 1 Period Dual Core Intel Xeon Processor 3000 Series Datasheet 31 intel Figure 2 5 Differential Clock Crosspoint Specification Electrical Specifications 650 600 550 0 5 VHavg 700 300 0 5 VHavg 700 Crossing Point mV 250 200 __ _ L VHavg mV 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 Figure 2 6 Differential Measurements Slew rise Slew fall 150 mV seeceee evsesve 4150mV 0 0 V eee eveve 00V 150 mV eevee 150mV Diff 2 7 9 BCLK 1 0 Specifications CK410 based Platforms Table 2 19 Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes VL Input Low Voltage 0 150 0 000 N A V 2 4 Vu Input High Voltage 0 660 0 700 0 850 V 2 4 Veross abs Absolute Crossing 0 250 N A 0 550 V 2 4 2 5 2 3 Point Veross rel Relative Crossing Point 0 250 N A 0 550 V 2 4 2 5 4 3 5 0 5 VHavg 0 700 0 5 VHavg 0 700 AVcross Range of Crossing N A N A 0 140 V 2 4 2 5 Points Vos Overshoot N A N A Vy 0 3 V 2 4 6 Vus Undershoot 0 300 N A N A V 2 4 7 VnBM Ringback Margin 0 200 N A N A V 2 4 8 Vim Threshold Region Vcnoss 0 100 N A Vcnoss 0 100 V 2 4 9 32
31. AF27 Power Other VSS AB1 Power Other VSS AF28 Power Other VSS AB23 Power Other VSS AF29 Power Other VSS AB24 Power Other VSS AF3 Power Other VSS AB25 Power Other VSS AF30 Power Other VSS AB26 Power Other VSS AF6 Power Other VSS AB27 Power Other VSS AF7 Power Other VSS AB28 Power Other VSS AG10 Power Other VSS AB29 Power Other VSS AG13 Power Other VSS AB30 Power Other VSS AG16 Power Other VSS AB7 Power Other VSS AG17 Power Other VSS AC3 Power Other VSS AG20 Power Other VSS AC6 Power Other VSS AG23 Power Other VSS AC7 Power Other VSS AG24 Power Other VSS AD4 Power Other VSS AG7 Power Other VSS AD7 Power Other VSS AH1 Power Other VSS AE10 Power Other VSS AH10 Power Other VSS AE13 Power Other VSS AH13 Power Other VSS AE16 Power Other VSS AH16 Power Other VSS AE17 Power Other VSS AH17 Power Other VSS AE2 Power Other VSS AH20 Power Other VSS AE20 Power Other VSS AH23 Power Other VSS AE24 Power Other VSS AH24 Power Other vss AE25 Power Other VSS AH3 Power Other VSS AE26 Power Other VSS AH6 Power Other VSS AE27 Power Other VSS AH7 Power Other 54 Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Assignments Sheet 15 of 20 Table 4 1 Alphabetical Land Assignments Sheet 16 of 20 intel Land
32. AM3 Power Other Output VCC T29 Power Other VI D3 AL6 Power Other Output VCC T30 Power Other VIDA AKA Power Other Output VEC T8 Power Other VID5 AL4 Power Other Output VCC U23 Power Other VI D6 AM5 Power Other Output VCC U24 Power Other VID7 AM7 Power Other Output VCC U25 Power Other VRDSEL AL3 Power Other VCC U26 Power Other VSS A12 Power Other VCC U27 Power Other VSS A15 Power Other VCC U28 Power Other VSS A18 Power Other Dual Core Intel Xeon Processor 3000 Series Datasheet 53 m n tel Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Table 4 1 Alphabetical Land Assignments Sheet 13 of 20 Assignments Sheet 14 of 20 Land Name Land Gu Direction Land Name Land kuz Sa Direction VSS A2 Power Other VSS AE28 Power Other VSS A21 Power Other VSS AE29 Power Other VSS A6 Power Other VSS AE30 Power Other VSS A9 Power Other VSS AE5 Power Other vss AA23 Power Other VSS AE7 Power Other VSS AA24 Power Other vss AF10 Power Other VSS AA25 Power Other VSS AF13 Power Other VSS AA26 Power Other VSS AF16 Power Other VSS AA27 Power Other VSS AF17 Power Other vss AA28 Power Other VSS AF20 Power Other vss AA29 Power Other VSS AF23 Power Other VSS AA3 Power Other VSS AF24 Power Other VSS AA30 Power Other VSS AF25 Power Other VSS AA6 Power Other VSS AF26 Power Other VSS AAT Power Other VSS
33. B22 D63 Source Synch Input Output B23 VSSA Power Other B24 VSS Power Other B25 VIT Power Other B26 VIT Power Other B27 VIT Power Other B28 VIT Power Other B29 VIT Power Other B30 VIT Power Other C DRDY Common Clock Input Output C2 BNR Common Clock Input Output C3 LOCK Common Clock Input Output C4 VSS Power Other C5 DO1 Source Synch Input Output C6 DO3 Source Synch Input Output C7 VSS Power Other C8 DSTBNO Source Synch Input Output C9 FC38 Power Other C10 VSS Power Other C11 D11 Source Synch Input Output C12 D14 Source Synch Input Output C13 VSS Power Other C14 D52 Source Synch Input Output cis D51 Source Synch Input Output C16 VSS Power Other C17 DSTBP3 Source Synch Input Output C18 D54 Source Synch Input Output C19 VSS Power Other C20 DBI 34 Source Synch Input Output C21 D58 Source Synch Input Output Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions intel Table 4 2 Numerical Land Assignment Table 4 2 Numerical Land Assignment Sheet 3 of 20 Sheet 4 of 20 p Land Name Bo v duel Direction M Land Name uz dn Direction C22 VSS Power Other E3 TRDY Common Clock Input C23 VCCIOPLL Power Other E4 HITM Common Clock Input Output C24 VSS Power Other E5 FC20 Power Other C25 VIT Power Other E6 RESERVED C26 VTT Power Other E7 RESERVED C27 VI
34. Intel Xeon Processor 3000 Series Datasheet m Boxed Processor Specifications n tel 7 3 2 Variable Speed Fan If the boxed processor fan heatsink 4 pin connector is connected to a 3 pin motherboard header it will operate as follows The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures This allows the processor fan to operate at a lower speed and noise level while internal chassis temperatures are low If internal chassis temperature increases beyond a lower set point the fan speed will rise linearly with the internal temperature until the higher set point is reached At that point the fan speed is at its maximum As fan speed increases so does fan noise levels Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point These set points represented in Figure 7 9 and Table 7 2 can vary by a few degrees from fan heatsink to fan heatsink The internal chassis temperature should be kept below 38 2C Meeting the processor s temperature specification see Chapter 5 is the responsibility of the system integrator The motherboard must supply a constant 12 V to the processor s power header to ensure proper operation of the variable speed fan for the boxed processor Refer to Table 7 1 for the specific requirements Figure 7 9 Boxed Processor Fan Heatsink Set Points Higher Set Point Highest Noise
35. Other M7 vss Power Other J30 VCC Power Other M8 VCC Power Other K1 LI NTO Asynch CMOS Input M23 VCC Power Other K2 VSS Power Other M24 VCC Power Other K3 A20M Asynch CMOS Input M25 VCC Power Other K4 REQO Source Synch Input Output M26 VCC Power Other K5 VSS Power Other M27 VCC Power Other K6 REQ3 Source Synch Input Output M28 VCC Power Other K7 VSS Power Other M29 VCC Power Other K8 VCC Power Other M30 VCC Power Other K23 VCC Power Other N1 PWRGOOD Power Other Input K24 VCC Power Other N2 IGNNE Asynch CMOS Input K25 VCC Power Other N3 VSS Power Other K26 VCC Power Other N4 RESERVED K27 VCC Power Other N5 RESERVED K28 VCC Power Other N6 VSS Power Other K29 VCC Power Other N7 VSS Power Other Dual Core Intel Xeon Processor 3000 Series Datasheet 61 intel Land Listing and Signal Descriptions Table 4 2 Numerical Land Assignment Table 4 2 Numerical Land Assignment Sheet 9 of 20 Sheet 10 of 20 tand Land Name Signal Buter Direction tana Land Name Signal Buffer Direction Type Type N8 VCC Power Other R30 VSS Power Other N23 VCC Power Other T1 COMP1 Power Other Input N24 VCC Power Other T2 FC4 Power Other N25 VCC Power Other T3 VSS Power Other N26 VCC Power Other T4 All Source Synch Input Output N27 VCC Power Other T5 A09 Source Synch Input Output N28 VCC Power Other T6 VSS Power Other N29 VCC Power Other T
36. Specifications n te Figure 3 4 Processor Package Drawing Sheet 3 of 3 u w o ES lt E ll E r z 8 az EE 5 Sz ez cs S 2 E Z 0000000000000000900000000000 9000 z OOOOOOOOOQOOOOOOQOOOOODOOOOOOOOO0O 00000000040000000000000b0000000000 i ieu OOoOOOOOOOQOOOOOOQOOOOODOOOOOOOOOO OOOOOOOOOQOOOOOOQOOOOODOOOOOOO0O0O0O0 OOOOOOOOOQOOOOOOQOOOOODOOOOOOOO0O0O OoOoOoOOOOOOQOOOOOOO0OOOOODOOOOOOOOOO 6000000000000000900000 0000000000 i t 000000000 E o 000000000 200 MISSION COLLEGE BLVD SANTA CLARA CA 95052 8 1 000000000 B 000000000 000000000 600000000 600000000 3 000000000 660000000 z E 600000000 000000000 ei T r 8888888881777r 88888888811 L 600660006 000000000 906990999 960000000 e T H 5 6600000000 600000000 am x oed y a ES 000000000 OOOOOOOOOOOOOOOOQOOOOOOOCOOOOOBnOQOO OOOOOOOOOOOOOOOO0OOOOOOOOOOOOO OOOOOOOOOOOOOOOOQOOOOOOOOOOOOOCOG OO0OOOOOOOOOOOOOOQOOOOOOOCOOOOOOOOO OOOOO0O0000000000090000000000000000 OOOOO00000000000090000000000 000 1 5 MAX ALLOWABLE COMPONENT HEIGHT il I I I J 3 2 ao ge az Se De eS ES ez ZE ut g SS 2c Faw EL 8
37. Synch Input Output D26 VIT Power Other F9 D18 Source Synch Input Output D27 VIT Power Other F10 VSS Power Other D28 VIT Power Other F11 D23 Source Synch Input Output D29 VIT Power Other F12 D243 Source Synch Input Output D30 VIT Power Other F13 VSS Power Other E2 VSS Power Other F14 D28 Source Synch Input Output Dual Core Intel Xeon Processor 3000 Series Datasheet 59 intel Land Listing and Signal Descriptions Table 4 2 Numerical Land Assignment Table 4 2 Numerical Land Assignment Sheet 5 of 20 Sheet 6 of 20 aeria Land Name ss dal Direction EE Land Name Signal Buffer Direction Type Type F15 D30 Source Synch Input Output G26 TESTHI5 Power Other Input F16 VSS Power Other G27 TESTHI4 Power Other Input F17 D37 Source Synch Input Output G28 BCLK1 Clock Input F18 D38 Source Synch Input Output G29 BSELO Power Other Output F19 VSS Power Other G30 BSEL2 Power Other Output F20 D41 Source Synch Input Output H1 GTLREFO Power Other Input F21 D43 Source Synch Input Output H2 GTLREF1 Power Other Input F22 VSS Power Other H3 VSS Power Other F23 RESERVED HA FC35 Power Other F24 TESTHI7 Power Other Input H5 TESTHI 10 Power Other Input F25 TESTHI2 Power Other Input H6 VSS Power Other F26 TESTHIO Power Other Input H7 VSS Power Other F27 VIT SEL Power Other Output H8 VSS Power Other F28 BCLKO Cloc
38. VIT A30 Power Other VSS T6 Power Other VIT B25 Power Other VSS T7 Power Other VIT B26 Power Other VSS U7 Power Other VIT B27 Power Other VSS V23 Power Other VIT B28 Power Other VSS V24 Power Other VIT B29 Power Other VSS V25 Power Other VIT B30 Power Other VSS V26 Power Other VIT C25 Power Other VSS V27 Power Other VIT C26 Power Other VSS V28 Power Other VIT C27 Power Other VSS V29 Power Other VIT C28 Power Other VSS v3 Power Other VIT C29 Power Other VSS v30 Power Other VIT C30 Power Other VSS V6 Power Other VIT D25 Power Other VSS V7 Power Other VIT D26 Power Other VSS wa Power Other VIT D27 Power Other VSS W7 Power Other VIT D28 Power Other VSS Y2 Power Other VIT D29 Power Other VSS Y5 Power Other VIT D30 Power Other VSS Y7 Power Other VTT_OUT_LEFT jl Power Other Output VSS_MB_ AN6 Power Other Output VIT OUT RIGHT AA1 Power Other Output REGULATION VTT_SEL F27 Power Other Output VSS_SENSE AN4 Power Other Output VSSA B23 Power Other Dual Core Intel Xeon Processor 3000 Series Datasheet 57 intel Table 4 2 Numerical Land Assignment Sheet 1 of 20 Bane Land Name Am Direction A2 VSS Power Other A3 RS2 Common Clock Input A4 DO2 Source Synch Input Output A5 DO4 Source Synch Input Output A6 VSS Power Other A7 DO7 Source Synch Input Output A8 DBIO Source Sy
39. and voltage When the TCC is activated the processor automatically transitions to the new frequency This transition occurs very rapidly on the order of 5 us During the frequency transition the processor is unable to service any bus requests and consequently all bus traffic is blocked Edge triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps to support Thermal Monitor 2 During the voltage change it will be necessary to transition through multiple VID codes to reach the target operating voltage Each step will likely be one VID table entry see Table 2 4 The processor continues to execute instructions during the voltage transition Operation at the lower voltage reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and Dual Core Intel Xeon Processor 3000 Series Datasheet 81 m n tel Thermal Specifications and Design Considerations Figure 5 5 5 2 3
40. applied to the IHS in a direction normal to the IHS surface 4 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times The Socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide Dual Core Intel Xeon Processor 3000 Series Datasheet m Package Mechanical Specifications n te 3 1 5 3 1 6 Table 3 3 3 2 Figure 3 5 Processor Mass Specification The typical mass of the processor is 21 5 g 0 76 oz This mass weight includes all the components that are included in the package Processor Materials Table 3 3 lists some of the package components and associated materials Processor Materials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper Processor Markings Figure 3 5 Figure 3 6 and Figure 3 7 how the topside markings on the processors These diagrams aid in the identification of the processor Processor Top Side Markings Example for the Dual Core Intel Xeon Processor 3000 Series with 2MB L2 Cache with 1066 MHz FSB 2 13GHZ 2M 1066 06 INTEL XEON SOS OMS lion OO 1 05 FPO Dual Core Intel Xeon Processor 3000 Series Datasheet 41 m e n te
41. boxed processor to draw power from a power header on the baseboard The power cable connector and pinout are shown in Figure 7 5 Baseboards must provide a matched power header to support the boxed processor Table 7 1 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal that is an open collector output that pulses at a rate of 2 pulses per fan revolution A baseboard pull up resistor provides Vo to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL Dual Core Intel Xeon Processor 3000 Series Datasheet 97 Boxed Processor Specifications The boxed processor s fanheat sink requires a constant 12 V supplied to pin 2 and does not support variable voltage control or 3 pin PWM control The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header identification and location should be documented in the platform documentation or on the system board itself Figure 7 6 shows the location of the fan power connector relative to the processor socket The baseboard power header should be positioned within 110 mm 4 33 inches from the center of the processor socket
42. experience excursions above Vr 6 Leakage to Vss with land held at Vr 7 Leakage to Vy with land held at 300 mV Open Drain and TAP Output Signal Group DC Specifications Symbol Parameter Min Max Unit Notes VoL Output Low Voltage 0 0 20 V Vou Output High Voltage pu Pus V 2 l oL Output Low Current 16 50 mA 3 lio Output Leakage Current N A x 200 HA 4 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Von is determined by the value of the external pull up resister to Vr Refer to theappropriate platform design guide for details 3 Measured at V 0 2 4 For Vin between 0 and Voy Dual Core Intel Xeon Processor 3000 Series Datasheet 27 intel Table 2 13 CMOS Signal Group DC Specifications Electrical Specifications Symbol Parameter Min Max Unit Notes Vit Input Low Voltage 0 10 Vr 0 30 V 2 3 Vin Input High Voltage Vr 0 70 Vr 0 10 V 3 4 5 VoL Output Low Voltage 0 10 Vor 0 10 V 3 Vou Output High Voltage 0 90 Vir Vr 0 10 V 3 6 5 l oL Output Low Current 1 70 4 70 mA 3 7 loH Output High Current 1 70 4 70 mA 3 7 lu Input Leakage Current N A 100 HA 8 lio Output Leakage Current N A 100 HA 9 Notes io cosrorur B wp Table 2 14 PECI DC Electrical Limits Unless otherwise noted all specifications in this table apply to all processor frequencies Vi
43. indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins lands of all FSB agents TRST Input TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset VCC Input VCC are the power pins for the processor The voltage supplied to these pins is determined by the VID 7 0 pins VCCPLL Input VCCPLL provides isolated power for internal processor FSB PLLs VCC_SENSE Output VCC_SENSE is an isolated low impedance connection to processor core power Vcc It can be used to sense or measure voltage near the silicon with little noise VCC MB REGULATI ON Output This land is provided as a voltage regulator feedback sense point for Vec It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket VID 7 0 Output VI D 7 0 Voltage ID signals are used to support automatic selection of power supply voltages Vcc Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information The voltage supply for these signals must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID signals becomes valid T
44. is defined as the voltage range at a receiving agent that will be interpreted as a logical low value The V referred to in these specifications refers to instantaneous Vyr Vin is defined as the voltage range at a receiving agent that will be interpreted as a logical high value Vin and Voy may experience excursions above Vr All outputs are open drain loi is measured at 0 10 Vyr lopis measured at 0 90 Vr Leakage to Vss with land held at V7 Leakage to Vr with land held at 300 mV Symbol Definition and Conditions Min Max Units Notes Vin Input Voltage Range 0 15 Vat 0 15 V Vnysteresis Hysteresis 0 1 Vr V 3 Vn Negative edge threshold voltage 0 275 V 0 500 Vz V Vp Positive edge threshold voltage 0 550 V 0 725 Vr V I source High level output source 6 0 N A mA Von 0 75 Vr I sink Low level output sink 0 5 1 0 mA VoL 0 25 Vr lieak High impedance state leakage to Vr N A 50 HA 2 lleak High impedance leakage to GND N A 10 HA 2 Chus Bus capacitance 10 pF Vnoise Signal noise immunity above 300 MHz 0 1 Vr Vp p Note 1 V supplies the PECI interface PECI behavior does not affect V r min max specifications 2 The leakage specification applies to powered devices on the PECI bus 3 The input buffers use a Schmitt triggered input design for improved noise immunity 28 Dual Core Intel Xeon Processor 3000 Series Datas
45. m 0c X rE zt 05 c lt sz lt 33B8B 8B B28 B5 Address Common Clock Async Dual Core Intel Xeon Processor 3000 Series Datasheet 43 44 Package Mechanical Specifications Dual Core Intel Xeon Processor 3000 Series Datasheet n Land Listing and Signal Descriptions n te Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions 4 1 Processor Land Assignments This section contains the land listings for the processor The land out footprint is shown in Figure 4 1 and Figure 4 2 These figures represent the land out arranged by land number and they show the physical location of each signal on the package land array top view Table 4 1 provides a listing of all processor lands ordered alphabetically by land signal name Table 4 2 provides a listing of all processor lands ordered by land number Dual Core Intel Xeon Processor 3000 Series Datasheet 45 m n tel Land Listing and Signal Descriptions Figure 4 1 land out Diagram Top View Left Side 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AM vcc VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC vcc VSS VSS VCC AL VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AK VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AJ VSS VSS VSS VSS VCC VCC VSS VSS VCC VC
46. one divider for each GTLEREF land Refer to the applicable platform design guide for implementation details 3 Ry is the on die termination resistance measured at V77 3 of the GTL output driver Refer to the appropriate platform design guide for the board impedance Refer to processor I O buffer models for I V characteristics 4 COMP resistance must be provided on the system board with 1 resistors See the applicable platform design guide for implementation details COMP 3 0 and COMPS resistors are to Vss Clock Specifications Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the processor s core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier will be set at its default ratio during manufacturing Refer to Table 2 16 for the processor supported ratios The processor uses a differential clocking implementation For more information on the processor clocking contact your Intel Field representative Platforms using a CK505 Clock Synthesizer Driver should comply with the specifications in Section 2 7 8 Platforms using a CK410 Clock Synthesizer Driver should comply with the specifications in Section 2 7 9 Dual Core Intel Xeon Processor 3000 Series Datasheet 29 E n tel Electrical Specifications Table 2 16 Core Frequency to FSB Multiplier Configu
47. out zone The area on or near the processor that system design can not use Processor core Processor core die with integrated L2 cache LGA775 socket The processors mate with the system board through a surface mount 775 land LGA socket I ntegrated heat spreader I HS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Retention mechanism RM Since the LGA775 socket does not include any mechanical features for heatsink attach a retention mechanism is required Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket FSB Front Side Bus The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Storage conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with
48. provided on the motherboard Decoupling solutions must be sized to meet the expected load To insure compliance with the specifications various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors Dual Core Intel Xeon Processor 3000 Series Datasheet 15 e n tel Electrical Specifications 2 3 16 FSB Decoupling The processor integrates signal termination on the die In addition some of the high frequency capacitance required for the FSB is included on the processor package However additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus Bulk decoupling must also be provided by the motherboard for proper A GTL bus operation Voltage I dentification The Voltage Identification VID specification for the processor is defined by the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor Vcc pins see Chapter 2 6 3 for Vcc overshoot specifications Refer to Table 2 13 for the DC specifications for these signals Voltages for each processor frequency is provided in Table 2 4
49. refer to Section 5 2 In all cases the Thermal Monitor and Thermal Monitor 2 feature must be enabled for the processor to remain within specification Table 5 1 Processor Thermal Specifications Processor Pore Thermal R ark Minimum T Maximum T Number Frequency Design HALT CONFIG 06 C c C Notes GHz Power W Power w 1 Guidance 3085 3 00 65 0 8 0 5 5 3075 2 66 65 0 8 0 See lane 5 775_VR_CONFIG_0 Figure 5 1 3065 2 33 65 0 8 0 6 5 5 3070 2 66 65 0 22 0 775_VR_CONFIG_0 5 See Table 5 3 6 6 and Figure 5 3 3060 2 40 65 0 22 0 5 6 3050 2 13 65 0 22 0 775_VR_CONFIG_0 5 See Table 5 4 6 6 and Figure 5 3 3040 1 86 65 0 22 0 5 6 Notes 1 Thermal Design Power TDP should be used for processor thermal solution design targets The TDP is not the maximum power that the processor can dissipate 2 This table shows the maximum TDP for a given frequency range Individual processors may have a lower TDP Therefore the maximum T will vary depending on the TDP of the individual processor Refer to thermal profile figure and associated table for the allowed combinations of power and Tc 3Refer to the Component Identification Information section of the Dual Core Intel Xeon Processor 3000 Series Specification Update for processor specific Idle power 4 775_VR_CONFIG_06 775_VR_CONFIG_05B guidelines provide a design target for meeting future thermal requirements
50. y Rd LE Eba n Bun gale EE AER j 99 Debug Tools Specifications LLL Lak emen nenne 101 8 1 Logic Analyzer Interface LAI MKKMh K Kh h kh k k kk kk kk kk kk kk kk kk kk kk kk kk kk kk nn nnne 101 8 1 1 Mechanical Considerations hL LLkEC khkhkk kk ene eene 101 8 1 2 Electrical Considerations esses ee ee eee eee 101 Dual Core Intel Xeon Processor 3000 Series Datasheet Figures 2 1 Vcc Static and Transient Tolerance for Processors with 4 MB L2 Cache h lhkj 22 2 2 Vcc Static and Transient Tolerance for Processors with 2 MB L2 Cache ssssssss 23 2 3 Vcc Overshoot Example Waveform oo eene n kanan nen 24 2 4 Differential Clock Waveform k kK KK KKkk kk kk kk kk kk kk kk kk kk EERE DEDEDE nnn nnn 31 2 5 Differential Clock Crosspoint Specification L hWkk khkkkkk kk kk kk 32 2 6 Differential Measurements c cece cee ee emen enn ak kak kak ka kak kk kk a kk kk 32 2 7 Differential Clock Crosspoint Specification L khkWhk khkkkkk kk kk 33 3 1 Processor Package Assembly Sketch ccc cect kk kk kk kk k enne 35 3 2 Processor Package Drawing Sheet 1 Of 3 hK KA k hlkk kk kk kk kak kk kk ke 37 3 3 Processor Package Drawing Sheet 2 Of 3 0 0 cece nemen emnes 38 3 4 Processor Package Drawing Sheet 3 Of 3 enm 39 3 5 Processor Top Side Markings Example for the Dual Core Intel Xeon Processor 3000 Series with 2MB L2 Cache with 1066 MHz FSB cceee
51. 16 Source Synch Input Output DSTBN2 G20 Source Synch Input Output D35 G18 Source Synch Input Output DSTBN3 A16 Source Synch Input Output D36 G17 Source Synch Input Output DSTBPO B9 Source Synch Input Output D37 F17 Source Synch Input Output DSTBP1 E12 Source Synch Input Output D38 F18 Source Synch Input Output DSTBP2 G19 Source Synch Input Output D39 E18 Source Synch Input Output DSTBP3 C17 Source Synch Input Output D40 E19 Source Synch Input Output FCO Y1 Power Other D41 F20 Source Synch Input Output FC3 J2 Power Other D42 E21 Source Synch Input Output FC4 T2 Power Other D43 F21 Source Synch Input Output FC5 F2 Power Other D44 G21 Source Synch Input Output FC8 AK6 Power Other D45 E22 Source Synch Input Output FC10 E24 Power Other D46 D22 Source Synch Input Output FC15 H29 Power Other D47 G22 Source Synch Input Output FC17 Y3 Power Other D48 D20 Source Synch Input Output FC18 AE3 Power Other D49 D17 Source Synch Input Output FC20 E5 Power Other D50 Al4 Source Synch Input Output FC21 F6 Power Other D51 C15 Source Synch Input Output FC22 J3 Power Other D52 C14 Source Synch Input Output FC23 A24 Power Other D53 B15 Source Synch Input Output FC26 E29 Power Other D54 C18 Source Synch Input Output FC27 G1 Power Other D55 B16 Source Synch Input Output FC28 U1 Power Other D56 A17 Source Synch Input Output FC29 U2 Power Other D57 B18 Source Synch Input Output FC30 U3 Power Other D58 C21 Source Synch Input Output FC31 J16 P
52. 2 28 en o Be L N Se B Zs f re zc 65 28 zE rie z an ER El ze g GE KEN A a BAN i EI s dg 2s i ge 8 zo ba Ee zs 2 lt EE Sa ag za za OQO zd O 83 o UT TT ge eo a E zc 2g zz EX e Ww CJ Oo aa Dual Core Intel Xeon Processor 3000 Series Datasheet 3 1 2 Table 3 1 3 1 3 Table 3 2 3 1 4 40 e n tel Package Mechanical Specifications Processor Component Keep Out Zones The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out zones Decoupling capacitors are typically mounted to either the topside or land side of the package substrate See Figure 3 2 and Figure 3 3 for keep out zones The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep in Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package These mechanical maximum load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solution The minimum loading specifi
53. 40 3 1 3 Package Handling Guidelines sss 40 3 1 4 Package Insertion Specifications ssesssssssssssseeenmmm mme 40 3 1 5 Processor Mass Specification MkkL Wk k k k kk mmm 41 31 6 Processor Materials eer ttr tc tp xaza xakan kik ara S er Ra urpate ea nA a w b hna S 41 3 2 Processor Markihgs iere ernn add Aled eU E erri kan dent uet e bea vr etre kar 41 3 2 1 Processor Land Coordinates ssssssssssssssseemeemenemememe mene 43 4 Land Listing and Signal Descriptions LL Lak ka 45 4 1 Processor Land AsS i hm mtS si xasi s ayan inasin kaz kaka ak kra ayas a al kn aa kla ka messes 45 4 2 Alphabetical Signals Reference LMh k MWQlJ LL kk aka kk kk yak ak kak aa 68 5 Thermal Specifications and Design Considerations L L LK LC L E L LEE 75 5 1 Processor Thermal Specifications cece kk ee kk kk kk kk aka 75 5 1 1 Thermal Specifications rrr 3 ka Rte nr dan nak nan k r ieee A RAW M ER R FER XEN CERTES RYE 75 5 1 2 Thermal Metrology ceres tren B DR ERR ka k Wara win Ya WW nab k RED senda 80 5 2 Processor Thermal FeaturesS 00 k la kill sakal ee eee memes ag xa aa memes ens 80 Dual Core Intel Xeon Processor 3000 Series Datasheet 3 ntel 5 2 1 Thermal Monitor i i e REA RECO RHRAR EN RA d h k n a d D ka k d dikek d yan 80 5 2 2 Thermal Monit fF 2 src eter Rr kam cak EAA rE
54. 5 3060 3050 and 3040 Unless otherwise specified the Dual Core Intel Xeon processor 3000 series is referred to as processor The processors support several Advanced Technologies including the Execute Disable Bit Intel 64 and Enhanced Intel SpeedStep Technology In addition the Dual Core Intel Xeon processor 3000 series supports Intel Virtualization Technology Intel VT and Intel Trusted Execution Technology Intel TXT The processor s front side bus FSB uses a split transaction deferred reply protocol like the Intel Pentium 4 processor The FSB uses Source Synchronous Transfer SST of address and data to improve performance by transferring data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or 2X address bus Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 8 5 10 7 GB s Intel has enabled support components for the processor including heatsink heatsink retention mechanism and socket Manufacturability is a high priority hence mechanical assembly may be completed from the top of the baseboard and should not require any special tooling The processor includes an address bus power down capability which removes power from the address and data signals when the FSB is not in use This feature is always enabled on the processor
55. 7 VSS Power Other N30 VCC Power Other T8 VCC Power Other P1 TESTHI 11 Power Other Input T23 VCC Power Other P2 SMI Asynch CMOS Input T24 VCC Power Other P3 INIT Asynch CMOS Input T25 VCC Power Other P4 VSS Power Other T26 VCC Power Other P5 RESERVED T27 VCC Power Other P6 A04 Source Synch Input Output T28 VCC Power Other P7 VSS Power Other T29 VCC Power Other P8 VCC Power Other T30 VCC Power Other P23 VSS Power Other U1 FC28 Power Other P24 VSS Power Other U2 FC29 Power Other P25 VSS Power Other U3 FC30 Power Other P26 VSS Power Other U4 A13 Source Synch Input Output P27 VSS Power Other U5 A125 Source Synch Input Output P28 VSS Power Other U6 A10 Source Synch Input Output P29 VSS Power Other U7 VSS Power Other P30 VSS Power Other U8 VCC Power Other R1 COMP3 Power Other Input U23 VCC Power Other R2 VSS Power Other U24 VCC Power Other R3 FERR PBE Asynch CMOS Output U25 VCC Power Other R4 A08 Source Synch Input Output U26 VCC Power Other R5 VSS Power Other U27 VCC Power Other R6 ADSTBO Source Synch Input Output U28 VCC Power Other R7 VSS Power Other U29 VCC Power Other R8 VCC Power Other U30 VCC Power Other R23 VSS Power Other V1 MSI D1 Power Other Output R24 VSS Power Other V2 RESERVED R25 VSS Power Other V3 VSS Power Other R26 VSS Power Other v4 A15 Source Synch Input Output R27 VSS Power Other V5 Al4 Source Synch Input Output R28 VSS Power Other V6 vss Power Other R29 VSS Power Other V7 vss Power Other
56. 9 8 18 47 9 42 54 1 65 60 1 20 48 4 44 54 6 l Figure 5 2 Thermal Profile Dual Core Intel Xeon 3070 3060 Processor with 4 MB L2 Cache 65 0 60 0 a e o y 0 26x 43 2 Tcase C 50 0 0 10 20 30 40 50 60 Power W 78 Dual Core Intel Xeon Processor 3000 Series Datasheet Thermal Specifications and Design Considerations Table 5 4 hermal Profile Dual Core Intel Xeon Processor 3000 Series with 2 MB L2 Cache intel Figure 5 3 Thermal Profile Dual Core Intel Xeon Processor 3000 Series with 2 MB L2 Cache Power W LATA Tc Power Tc Power lou Tc 0 43 2 24 49 9 48 56 6 2 43 8 26 50 5 50 57 2 4 44 3 28 51 0 52 57 8 6 44 9 30 51 6 54 58 3 8 45 4 32 52 2 56 58 9 10 46 0 34 52 7 58 59 4 12 46 6 36 53 3 60 60 0 14 47 1 38 53 8 62 60 6 16 47 7 40 54 4 64 61 1 18 48 2 42 55 0 65 61 4 20 48 8 44 55 5 22 49 4 46 56 1 65 0 60 0 55 0 y 0 28x 43 2 Tcase C 50 0 45 0 20 30 40 Power W 50 60 Dual Core Intel Xeon Processor 3000 Series Datasheet 79 m n tel Thermal Specifications and Design Considerations 5 1 2 Figure 5 4 5 2 5 2 1 80 Thermal Metrology The maximum and minimum case temperatures Tc for the processor is specified in Table 5 1 This temperature specifi
57. C VSS VCC VCC VSS VSS VCC AH VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AG vcc VCC VCC VCC VCC VCC VSS VSS VEC VCC VSS VCC vcc VSS VSS VCC AF VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AE VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VCC VEC VSS VSS VCC AD VCC VCC VCC VCC VCC VCC VCC VCC AC VCC VCC VEC VCC VCC VCC VCC VCC AB VSS VSS VSS VSS VSS VSS VSS VSS AA VSS VSS VSS vss VSS VSS VSS VSS Y VCC VCC VCC VCC VCC VCC VCC VCC Ww VCC VCC VCC VCC VCC VCC vcc VCC v VSS VSS VSS VSS VSS VSS VSS VSS U VCC VCC VCC VCC VCC VCC VCC VCC T VCC VCC VCC VCC VCC VCC VCC VCC R VSS VSS VSS VSS VSS VSS VSS VSS P VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VCC VCC VCC VCC vcc VCC VCC VCC VCC VCC VCC VCC vcc L VSS VSS VSS VSS VSS VSS VSS VSS K VCC VCC VCC VCC VCC VCC VCC VCC J VCC VCC VCC VEC VEC VCC VCC vcc VCC VCC VCC VCC VCC FC34 FC31 vcc H BSEL1 FC15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS FC33 FC32 G BSEL2 BSELO BCLK1 TESTHI4 TESTHI TESTHI TESTHI RESET D47 D44 DSTBN2 DSTBP2 D35 D36 D32 D31 5 3 6 F RSVD BCLKO VIT SEL TESTHI TESTHI TESTHI RSVD VSS D43 D41 VSS D38 D37 VSS D30 0 2 7 E FC26 VSS VSS VSS VSS FC10 RSVD D45 D42 VSS D40 D39 VSS D34
58. C24 Power Other VSS AL24 Power Other VSS C4 Power Other VSS AL27 Power Other VSS C7 Power Other VSS AL28 Power Other VSS D12 Power Other VSS AL7 Power Other VSS D15 Power Other VSS AM1 Power Other VSS D18 Power Other VSS AM10 Power Other VSS D21 Power Other VSS AM13 Power Other VSS D24 Power Other Dual Core Intel Xeon Processor 3000 Series Datasheet 55 m n tel Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Table 4 1 Alphabetical Land Assignments Sheet 17 of 20 Assignments Sheet 18 of 20 Land Name Land T Direction Land Name Land ku rd Direction VSS D3 Power Other VSS H7 Power Other VSS D5 Power Other VSS H8 Power Other VSS D6 Power Other VSS H9 Power Other VSS D9 Power Other VSS J4 Power Other VSS E11 Power Other VSS J7 Power Other vss E14 Power Other vss K2 Power Other vss E17 Power Other VSS K5 Power Other VSS E2 Power Other VSS K7 Power Other vss E20 Power Other VSS L23 Power Other VSS E25 Power Other VSS L24 Power Other VSS E26 Power Other VSS L25 Power Other VSS E27 Power Other VSS L26 Power Other VSS E28 Power Other VSS L27 Power Other VSS E8 Power Other VSS L28 Power Other VSS F10 Power Other VSS L29 Power Other vss F13 Power Other VSS L3 Power Other VSS F16 Power Other VSS L30 Power Other VSS F19 Power Other VSS L6 Power Other VSS F22 Power Other VSS L7 Power Other VSS
59. Dual Core Intel Xeon Processor 30004 Series Datasheet on 65 nm Process in the 775 land LGA Package November 2007 Document Number 314915 002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLI ED WARRANTY RELATI NG TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL LIFE SAVING OR LIFE SUSTAINING APPLICATIONS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Alntel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details Over time processor num
60. Environment Control I nterface PECI Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components It uses a single wire thus alleviating routing congestion issues Figure 5 6 shows an example of the PECI topology in a system PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices Also data transfer speeds across the PECI interface are negotiable within a wide range 2 Kbps to 2 Mbps The PECI interface on the processor is disabled by default and must be enabled through BIOS More information on this can be found in the Conroe BIOS Writer s Guide Dual Core Intel Xeon Processor 3000 Series Datasheet 85 intel Figure 5 6 Processor PECI Topology 5 4 1 1 Figure 7 86 PECI Host Controller Thermal Specifications and Design Considerations Eum Domain 0 rn Key Difference with Legacy Diode Based Thermal Management Fan speed control solutions based on PECI uses a Tcontro value stored in the processor A32_TEMPERATURE_TARGET MSR The TcontroL MSR uses the same offset temperature format as PECI though it contains no sign bit Thermal management devices should infer the Tcontro value as negative Thermal management algorithms should use the relative temperature value delivered over PECI in conjunction with the TcoNTROL MSR value to control or optimize fan speeds Figure 7 shows a conceptual fan control diagram using PECI temp
61. F AE AD AC AB AA lt za Hc lt v Oo OU m m 47 intel Table 4 1 Alphabetical Land Assignments Sheet 1 of 20 Land Name Land m Direction A3 L5 Source Synch Input Output A4 P6 Source Synch Input Output A5 M5 Source Synch Input Output A6 L4 Source Synch Input Output ATH M4 Source Synch Input Output A8 R4 Source Synch Input Output A9 T5 Source Synch Input Output A10 U6 Source Synch Input Output A1l11 T4 Source Synch Input Output Al2 U5 Source Synch Input Output A13 U4 Source Synch Input Output Al4 V5 Source Synch Input Output A15 v4 Source Synch Input Output Al6 W5 Source Synch Input Output Al7 AB6 Source Synch Input Output A18 W6 Source Synch Input Output A19 Y6 Source Synch Input Output A20 Y4 Source Synch Input Output A20M K3 Asynch CMOS Input A21 AA4 Source Synch Input Output A22 AD6 Source Synch Input Output A23 AA5 Source Synch Input Output A24 AB5 Source Synch Input Output A25 AC5 Source Synch Input Output A26 AB4 Source Synch Input Output A27 AF5 Source Synch Input Output A28 AF4 Source Synch Input Output A29 AG6 Source Synch Input Output A30 AG4 Source Synch Input Output A31 AG5 Source Synch Input Output A32 AH4 Source Synch Input Output A334 AH5 Source Synch Input Output A34 AJ5 Source Synch Input Output A35 AJ6 Source Synch Input Output ADS D2 Common Clock
62. F4 Power Other VSS M1 Power Other VSS F7 Power Other VSS M7 Power Other vss H10 Power Other VSS N3 Power Other VSS H11 Power Other VSS N6 Power Other VSS H12 Power Other VSS N7 Power Other vss H13 Power Other VSS P23 Power Other VSS H14 Power Other VSS P24 Power Other VSS H17 Power Other VSS P25 Power Other VSS H18 Power Other VSS P26 Power Other VSS H19 Power Other VSS P27 Power Other VSS H20 Power Other VSS P28 Power Other VSS H21 Power Other VSS P29 Power Other vss H22 Power Other VSS P30 Power Other vss H23 Power Other VSS P4 Power Other VSS H24 Power Other VSS P7 Power Other vss H25 Power Other VSS R2 Power Other vss H26 Power Other VSS R23 Power Other VSS H27 Power Other VSS R24 Power Other vss H28 Power Other VSS R25 Power Other VSS H3 Power Other VSS R26 Power Other VSS H6 Power Other VSS R27 Power Other 56 Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions intel Table 4 1 Alphabetical Land Table 4 1 Alphabetical Land Assignments Sheet 19 of 20 Assignments Sheet 20 of 20 Land Name Land ee Direction Land Name Land ur cod Direction VSS R28 Power Other VIT A25 Power Other VSS R29 Power Other VIT A26 Power Other VSS R30 Power Other VIT A27 Power Other VSS R5 Power Other VIT A28 Power Other VSS R7 Power Other VIT A29 Power Other VSS T3 Power Other
63. Intel Xeon Processor 3000 Series Thermal Design Guidelines for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Thermal Monitor 2 The processor also supports an additional power reduction capability known as Thermal Monitor 2 This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor When Thermal Monitor 2 is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated The TCC causes the processor to adjust its operating frequency via the bus multiplier and input voltage via the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption A processor enabled for Thermal Monitor 2 includes two operating points each consisting of a specific operating frequency and voltage The first operating point represents the normal operating condition for the processor Under this condition the core frequency to FSB multiple used by the processor is that contained in the appropriate MSR and the VID is that specified in Table 2 4 These parameters represent normal system operation The second operating point consists of both a lower operating frequency
64. J 18 VCC Power Other AK28 VSS Power Other AJ 19 VCC Power Other AK29 VSS Power Other AJ 20 VSS Power Other AK30 VSS Power Other AJ 21 VCC Power Other AL1 THERMDA Power Other AJ22 VCC Power Other AL2 PROCHOT Asynch CMOS Input Output AJ 23 VSS Power Other AL3 VRDSEL Power Other AJ 24 VSS Power Other AL4 VID5 Power Other Output AJ25 VCC Power Other AL5 VID1 Power Other Output AJ26 VCC Power Other AL6 VID3 Power Other Output AJ27 VSS Power Other AL7 VSS Power Other AJ28 VSS Power Other AL8 VCC Power Other AJ 29 VSS Power Other AL9 VCC Power Other AJ 30 VSS Power Other AL10 VSS Power Other AK1 THERMDC Power Other AL11 VCC Power Other AK2 VSS Power Other AL12 VCC Power Other AK3 ITP_CLKO TAP Input AL13 VSS Power Other AK4 VIDA Power Other Output AL14 VCC Power Other AK5 VSS Power Other AL15 VCC Power Other AK6 FC8 Power Other AL16 VSS Power Other AK7 VSS Power Other AL17 VSS Power Other AK8 VCC Power Other AL18 VCC Power Other AK9 VCC Power Other AL19 VCC Power Other AK10 VSS Power Other AL20 VSS Power Other AK11 VCC Power Other AL21 VCC Power Other AK12 VCC Power Other AL22 VCC Power Other AK13 VSS Power Other AL23 VSS Power Other AK14 VCC Power Other AL24 VSS Power Other AK15 VCC Power Other AL25 VCC Power Other AK16 VSS Power Other AL26 vcc Power Other AK17 VSS Power Other AL27 VSS Power Other AK18 VCC Power Other AL28 VSS Power Other AK19 VCC Power Other AL29 vcc Power Other AK20 VSS Power Other AL30 VCC Power Other AK21 VCC Power Other AM1 V
65. Level Increasing Fan Speed amp Noise Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature Degrees C Dual Core Intel Xeon Processor 3000 Series Datasheet 101 intel Table 7 2 102 Boxed Processor Specifications Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point C Boxed Processor Fan Speed Notes X lt 30 When the internal chassis temperature is below or equal to this set 1 point the fan operates at its lowest speed Recommended maximum internal chassis temperature for nominal operating environment Y 35 When the internal chassis temperature is at this point the fan operates between its lowest and highest speeds Recommended maximum internal chassis temperature for worst case operating environment 2238 When the internal chassis temperature is above or equal to this set point the fan operates at its highest speed Notes 1 Set point variance is approximately 1 C from fan heatsink to fan heatsink If the boxed processor fan heatsink 4 pin connector is connected to a 4 pin motherboard header and the motherboard is designed with a fan speed controller with PWM output CONTROL see Table 7 1 and remote thermal diode measurement capability the boxed processor will operate as follows As processor power has increased the required thermal solutions have generated increasingly more noise Inte
66. Model Specific Registers thus eliminating chipset dependency If the target frequency is higher than the current frequency Vcc is incremented in steps 12 5 mV by placing a new value on the VID signals and the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded If the target frequency is lower than the current frequency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals Dual Core Intel Xeon Processor 3000 Series Datasheet m e Boxed Processor Specifications n tel 7 Note Note Figure 7 1 Boxed Processor Specifications The processor is also offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from baseboards and standard components The boxed processor will be supplied with a cooling solution This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor This chapter is particularly important for OEMs that manufacture baseboards for system integrators Figure 7 1 shows a mechanical representation of a boxed processor Unless otherwise noted all figures in this chapter are dimensioned in millimeters and inches in brackets Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions
67. Name Land ee M Direction Land Name Land T Direction VSS AJ 10 Power Other VSS AM16 Power Other VSS AJ 13 Power Other VSS AM17 Power Other VSS AJ16 Power Other VSS AM20 Power Other VSS AJ17 Power Other VSS AM23 Power Other VSS AJ 20 Power Other VSS AM24 Power Other VSS AJ 23 Power Other VSS AM27 Power Other VSS AJ 24 Power Other VSS AM28 Power Other VSS AJ 27 Power Other VSS AMA Power Other VSS AJ28 Power Other VSS AN1 Power Other VSS AJ 29 Power Other VSS AN10 Power Other vss AJ 30 Power Other VSS AN13 Power Other VSS AJ4 Power Other VSS AN16 Power Other VSS AJ7 Power Other VSS AN17 Power Other VSS AK10 Power Other VSS AN2 Power Other VSS AK13 Power Other VSS AN20 Power Other VSS AK16 Power Other VSS AN23 Power Other VSS AK17 Power Other VSS AN24 Power Other VSS AK2 Power Other VSS AN27 Power Other VSS AK20 Power Other VSS AN28 Power Other VSS AK23 Power Other VSS Bl Power Other VSS AK24 Power Other VSS B11 Power Other VSS AK27 Power Other VSS B14 Power Other VSS AK28 Power Other VSS B17 Power Other VSS AK29 Power Other VSS B20 Power Other VSS AK30 Power Other VSS B24 Power Other VSS AK5 Power Other VSS B5 Power Other VSS AK7 Power Other VSS B8 Power Other VSS AL10 Power Other VSS C10 Power Other VSS AL13 Power Other VSS C13 Power Other VSS AL16 Power Other VSS C16 Power Other VSS AL17 Power Other VSS C19 Power Other VSS AL20 Power Other VSS C22 Power Other VSS AL23 Power Other VSS
68. Output W28 VCC Power Other AB6 A175 Source Synch Input Output w29 VCC Power Other AB7 VSS Power Other w30 VCC Power Other AB8 VCC Power Other Y1 FCO Power Other AB23 VSS Power Other Y2 VSS Power Other AB24 VSS Power Other Y3 FC17 Power Other AB25 VSS Power Other Y4 A20 Source Synch Input Output AB26 VSS Power Other Y5 VSS Power Other AB27 VSS Power Other Y6 A195 Source Synch Input Output AB28 VSS Power Other Y7 VSS Power Other AB29 VSS Power Other Y8 VCC Power Other AB30 VSS Power Other Y23 VCC Power Other AC1 TMS TAP Input Y24 VCC Power Other AC2 DBR Power Other Output Y25 VCC Power Other AC3 VSS Power Other Y26 VCC Power Other ACA RESERVED Y27 VCC Power Other AC5 A25 Source Synch Input Output Y28 VCC Power Other AC6 VSS Power Other Y29 VCC Power Other AC7 VSS Power Other Dual Core Intel Xeon Processor 3000 Series Datasheet 63 intel Land Listing and Signal Descriptions Table 4 2 Numerical Land Assignment Table 4 2 Numerical Land Assignment Sheet 13 of 20 Sheet 14 of 20 Cand Land Name Signal Butter Direction tand Land Name Signal Buffer Direction Type Type AC8 VCC Power Other AE16 VSS Power Other AC23 VCC Power Other AE17 VSS Power Other AC24 VCC Power Other AE18 VCC Power Other AC25 VCC Power Other AE19 VCC Power Other AC26 VCC Power Other AE20 VSS Power Other AC27 VCC
69. P Output LINT1 L1 Asynch CMOS Input TESTHIO F26 Power Other Input LOCK C3 Common Clock Input Output TESTHI1 W3 Power Other Input MSIDO W1 Power Other Output TESTHI10 H5 Power Other Input MSI D1 V1 Power Other Output TESTHI11 P1 Power Other Input PECI G5 Power Other Input Output TESTHI 12 FC44 W2 Power Other Input PROCHOT AL2 Asynch CMOS Input Output TESTHI13 L2 Power Other Input PWRGOOD N1 Power Other Input TESTHI2 F25 Power Other Input REQO K4 Source Synch Input Output TESTHI3 G25 Power Other Input REQ1 J5 Source Synch Input Output TESTHI4 G27 Power Other Input REQ2 M6 Source Synch Input Output TESTHI5 G26 Power Other Input REQ3 K6 Source Synch Input Output TESTHI6 G24 Power Other Input REQ4 J6 Source Synch Input Output TESTHI7 F24 Power Other Input RESERVED A20 TESTHI8 FC42 G3 Power Other Input RESERVED AC4 TESTHI9 FC43 G4 Power Other Input RESERVED AE4 THERMDA AL1 Power Other RESERVED AE6 THERMDC AK1 Power Other RESERVED AH2 THERMTRI P M2 Asynch CMOS Output RESERVED D1 TMS AC1 TAP Input RESERVED D14 TRDY E3 Common Clock Input RESERVED D16 TRST AG1 TAP Input RESERVED E23 VCC AA8 Power Other RESERVED E6 VCC AB8 Power Other RESERVED E7 VCC AC23 Power Other RESERVED F23 VCC AC24 Power Other 50 Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Assignments Sheet 7 of 20 Table 4 1 Alphabetical Land Assignments Sheet 8 of 20 intel
70. Power Other AE21 VCC Power Other AC28 VCC Power Other AE22 VCC Power Other AC29 VCC Power Other AE23 VCC Power Other AC30 VCC Power Other AE24 VSS Power Other AD1 TDI TAP Input AE25 VSS Power Other AD2 BPM2 Common Clock Input Output AE26 VSS Power Other AD3 FC36 Power Other AE27 VSS Power Other AD4 VSS Power Other AE28 VSS Power Other AD5 ADSTB1 Source Synch Input Output AE29 VSS Power Other AD6 A22 Source Synch Input Output AE30 VSS Power Other AD7 VSS Power Other AF1 TDO TAP Output AD8 VCC Power Other AF2 BPM4 Common Clock Input Output AD23 VCC Power Other AF3 VSS Power Other AD24 VCC Power Other AF4 A28 Source Synch Input Output AD25 VCC Power Other AF5 A27 Source Synch Input Output AD26 VCC Power Other AF6 VSS Power Other AD27 VCC Power Other AF7 VSS Power Other AD28 VCC Power Other AF8 VCC Power Other AD29 VCC Power Other AF9 VCC Power Other AD30 VCC Power Other AF10 VSS Power Other AE1 TCK TAP Input AF11 VCC Power Other AE2 VSS Power Other AF12 VCC Power Other AE3 FC18 Power Other AF13 VSS Power Other AE4 RESERVED AF14 VCC Power Other AE5 VSS Power Other AF15 VCC Power Other AE6 RESERVED AF16 vss Power Other AE7 VSS Power Other AF17 VSS Power Other AE8 SKTOCC Power Other Output AF18 VCC Power Other AE9 VCC Power Other AF19 VCC Power Other AE10 VSS Power Other AF20 VSS Power Other AE11 VCC Power Other AF21 VCC Power Other AE12 VCC Power Other AF22 VCC Power Other AE13 VSS Power Other AF23 VSS Power Other AE14 VCC Power Othe
71. S gna S hk h hk kkk kk kk kk kk kk k kk k kak ka 89 7 1 Fan Heatsink Power and Signal Specifications Lk hk KhKk kk kk 98 7 2 Fan Heatsink Power and Signal Specifications Lhk hk kWkL kkll kk kk kk 102 6 Dual Core Intel Xeon Processor 3000 Series Datasheet Revision History Revision Number Description Date 001 Initial release September 2006 Updated Features Page Updated Table 2 4 2 15 Added Section 2 8 PECI DC Specifications Updated Figure 3 5 3 6 3 7 002 Updated Section 5 4 Platform Environment Control Interface PECI November 2007 Updated Figure 6 6 1 Added specificaitons for Dual Core Intel Xeon 3065 3075 3085 processors Added specifications for 1333 MHz FSB Added support for Extended Stop Grant State Extended Stop Grant Snoop States Added new thermal profile table and figure Dual Core Intel Xeon Processor 3000 Series Datasheet intel Dual Core I ntel Xeon Processor 3000 Series Features Available at 2 66 GHz 2 40 GHz 2 13 GHz Enhanced branch prediction and 1 86 GHz Dual Core Intel Xeon Optimized for 32 bit applications running on processors 3070 3060 3050 and 3040 advanced 32 bit operating systems eniy Two 16 KB Level 1 data caches Rp a E E A 4 MB Advanced Smart Cache Dual Core processors 3085 3075 3070 3065 and Intel Xeon processors 3070 and 3060 3060 only only 2 MB Advanced Smart Cache Dual Core Enh
72. SS Power Other AK22 VCC Power Other AM2 VIDO Power Other Output AK23 VSS Power Other AM3 VID2 Power Other Output AK24 VSS Power Other AMA VSS Power Other AK25 VCC Power Other AM5 VID6 Power Other Output 66 Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions intel Table 4 2 Numerical Land Assignment Table 4 2 Numerical Land Assignment Sheet 19 of 20 Sheet 20 of 20 p Land Name Naz Buffer Direction Fona Land Name signa Buiter Direction ype ype AM6 FC40 Power Other AN4 VSS_SENSE Power Other Output AM7 VID7 Power Other Output AN5 VCC MB Power Other Output AM8 vcc Power Other REGUPATION 288 UE Power Other AN6 ATE EYAN Power Other Output AM10 vss Power Other AN7 VID_SELECT Power Other Output AM11 VCC Power Other AN8 vcc Power Other AM12 VCC Power Other AN9 VCC Power Other AM13 vss Power Other AN10 VSS Power Other AM14 VCC Power Other AN11 VCC Power Other AM15 VCC Power Other AN12 VCC Power Other AM16 vss Power Other AN13 VSS Power Other AM17 VSS Power Other AN14 vcc Power Other AM18 vec Power Other AN15 VCC Power Other AM19 VCC Power Other AN16 VSS Power Other AM20 VSS Power Other AN17 VSS Power Other AM21 VCC Power Other AN18 VCC Power Other AM22 VCC Power Other AN19 VCC Power Other AM23 VSS Power Other AN20 VSS Powe
73. SS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details Table 2 6 Vcc Static and Transient Tolerance for Processors with 2 MB L2 Cache Sheet 1 of 2 Voltage Deviation from VID Setting V 2 3 4 Icc A Maximum Voltage Typical Voltage Minimum Voltage 1 40 mo 1 53 mo 1 65 mo 0 000 0 019 0 038 0 007 0 027 0 046 10 0 014 0 034 0 055 15 0 021 0 042 0 063 20 0 028 0 050 0 071 25 0 035 0 057 0 079 30 0 042 0 065 0 088 35 0 049 0 072 0 096 40 0 056 0 080 0 104 45 0 063 0 088 0 112 50 0 070 0 095 0 121 55 0 077 0 103 0 129 60 0 084 0 111 0 137 22 Dual Core Intel Xeon Processor 3000 Series Datasheet n Electrical Specifications n tel Table 2 6 Vcc Static and Transient Tolerance for Processors with 2 MB L2 Cache Sheet 2 of 2 Voltage Deviation from VID Setting V 2 3 4 Icc A Maximum Voltage Typical Voltage Minimum Voltage 1 40 mo 1 53 mo 1 65 mo 65 0 091 0 118 0 145 70 0 098 0 126 0 154 75 0 105 0 133 0 162 Notes 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 6 3
74. ST DBI D 15 0 0 D 31 16 1 D 47 32 2 D 63 48 3 w NI o Furthermore the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 Input Output DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electrically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DBI3 D 63 48 DBI2 D 47 32 DBI1 D 31 16 DBIO D 15 0 DBR Output DBR Debug Reset is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal DBSY Input Output DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is
75. T Power Other E8 VSS Power Other C28 VIT Power Other E9 D19 Source Synch Input Output C29 VIT Power Other E10 D21 Source Synch Input Output C30 VIT Power Other E11 VSS Power Other D1 RESERVED E12 DSTBP1 Source Synch Input Output D2 ADS Common Clock Input Output E13 D26 Source Synch Input Output D3 VSS Power Other E14 VSS Power Other D4 HIT Common Clock Input Output E15 D33 Source Synch Input Output D5 VSS Power Other E16 D34 Source Synch Input Output D6 VSS Power Other E17 VSS Power Other D7 D20 Source Synch Input Output E18 D39 Source Synch Input Output D8 D12 Source Synch Input Output E19 D40 Source Synch Input Output D9 VSS Power Other E20 VSS Power Other D10 D22 Source Synch Input Output E21 D42 Source Synch Input Output D11 D15 Source Synch Input Output E22 D45 Source Synch Input Output D12 VSS Power Other E23 RESERVED D13 D25 Source Synch Input Output E24 FC10 Power Other D14 RESERVED E25 VSS Power Other D15 VSS Power Other E26 VSS Power Other D16 RESERVED E27 VSS Power Other D17 D49 Source Synch Input Output E28 VSS Power Other D18 VSS Power Other E29 FC26 Power Other D19 DBI 2 Source Synch Input Output F2 FCS Power Other D20 D48 Source Synch Input Output F3 BRO Common Clock Input Output D21 VSS Power Other F4 VSS Power Other D22 D46 Source Synch Input Output F5 RS1 Common Clock Input D23 VCCPLL Power Other F6 FC21 Power Other D24 VSS Power Other F7 VSS Power Other D25 VIT Power Other F8 D17 Source
76. Units Notes lleak High impedance leakage to GND N A 10 HA 3 Cpus Bus capacitance per node N A 10 pF 4 Vnoise Signal noise immunity above 300 MHz 0 1 Vr Vp p Notes 1 V supplies the PECI interface PECI behavior does not affect V7 min max specifications Refer to Table 2 3 for Vr specifications 2 The input buffers use a Schmitt triggered input design for improved noise immunity 3 The leakage specification applies to powered devices on the PECI bus 4 One node is counted for each client and one node for the system host Extended trace lengths might appear as additional nodes Dual Core Intel Xeon Processor 3000 Series Datasheet n Package Mechanical Specifications n te 3 Figure 3 1 Package Mechanical Specifications The processor is packaged in a Flip Chip Land Grid Array FC LGA6 package that interfaces with the motherboard via an LGA775 socket The package consists of a processor core mounted on a substrate land carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket The package components shown in Figure 3 1 include the following e Integrated Heat Spreader IHS e Thermal Interfac
77. VCC J10 Power Other VCC AL15 Power Other VCC J11 Power Other VCC AL18 Power Other VCC J12 Power Other VCC AL19 Power Other VCC J13 Power Other VCC AL21 Power Other VCC J14 Power Other VCC AL22 Power Other VCC J15 Power Other VCC AL25 Power Other VCC J18 Power Other VCC AL26 Power Other VCC j19 Power Other VCC AL29 Power Other VCC J20 Power Other VCC AL30 Power Other VCC J21 Power Other VCC AL8 Power Other VCC J22 Power Other VCC ALY Power Other VCC J23 Power Other VCC AM11 Power Other VCC J24 Power Other VCC AM12 Power Other VCC 25 Power Other VCC AM14 Power Other VCC J26 Power Other VCC AM15 Power Other VCC J27 Power Other VCC AM18 Power Other VCC J28 Power Other VCC AM19 Power Other VCC J29 Power Other VCC AM21 Power Other VCC J30 Power Other VCC AM22 Power Other VCC J8 Power Other VCC AM25 Power Other VCC J9 Power Other VCC AM26 Power Other VCC K23 Power Other VCC AM29 Power Other VCC K24 Power Other VCC AM30 Power Other VCC K25 Power Other VCC AM8 Power Other VCC K26 Power Other VCC AM9 Power Other VCC K27 Power Other 52 Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Assignments Sheet 11 of 20 Table 4 1 Alphabetical Land Assignments Sheet 12 of 20 intel
78. VCC Power Other AG17 VSS Power Other AH27 VCC Power Other AG18 VCC Power Other AH28 VCC Power Other AG19 VCC Power Other AH29 VCC Power Other AG20 VSS Power Other AH30 VCC Power Other AG21 VCC Power Other AJ1 BPM1 Common Clock Input Output AG22 VCC Power Other AJ2 BPMO Common Clock Input Output AG23 VSS Power Other AJ3 ITP CLK1 TAP Input AG24 VSS Power Other AJ4 VSS Power Other AG25 VCC Power Other AJ5 A34 Source Synch Input Output AG26 VCC Power Other AJ6 A35 Source Synch Input Output AG27 VCC Power Other AJ7 VSS Power Other AG28 VCC Power Other AJ8 VCC Power Other AG29 VCC Power Other AJ9 VCC Power Other AG30 VCC Power Other AJ10 VSS Power Other AH1 VSS Power Other AJ11 VCC Power Other AH2 RESERVED AJ12 VCC Power Other AH3 VSS Power Other AJ13 VSS Power Other AH4 A32 Source Synch Input Output AJ14 VCC Power Other AH5 A33 Source Synch Input Output AJ15 VCC Power Other Dual Core Intel Xeon Processor 3000 Series Datasheet 65 intel Land Listing and Signal Descriptions Table 4 2 Numerical Land Assignment Table 4 2 Numerical Land Assignment Sheet 17 of 20 Sheet 18 of 20 ee Land Name signal Butter Direction tana Land Name Signal Buffer Direction Type Type AJ 16 VSS Power Other AK26 VCC Power Other AJ 17 VSS Power Other AK27 VSS Power Other A
79. Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality The Dual Core Intel Xeon processor 3000 series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Intel Pentium Xeon Intel Inside Intel Leap ahead Intel Trusted Execution Technology Intel SpeedStep Intel Virtualization Technology and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2006 2007 Intel Corporation 2 Dual Core Intel Xeon Processor 3000 Series Datasheet Contents 1 dipped EMT 11 lol Term
80. anced Intel Speedstep Technology Intel Xeon processors 3050 and 3040 Supports Intel 649 only Supports Intel amp Virtualization Technology Advanced Digital Media Boost Supports Intel amp Trusted Execution Enhanced floating point and multimedia unit Technology Intel amp TXT for enhanced video audio encryption and Supports Intel Virtualization Technol phu hei a Supports Intel Virtualization Technology T Dual Core Intel Xeon processor 3000 Power Management capabilities series System Management mode e Multiple low power states i oe gt e 8 way cache associativity provides improved Binary compatible with applications running cache hit rate on load store operations on previous members of the Intel microprocessor line 775 land Package FSB frequency at 1066 1333 MHz Advance Dynamic Execution Supports Execute Disable Bit capability Very deep out of order execution The Dual Core Intel Xeon processor 3000 series deliver Intel s advanced powerful processors for unit processor servers The processor is designed to deliver performance across applications and usages where end users can truly appreciate and experience the performance Intel 64 enables the processor to execute operating systems and applications written to take advantage of the Intel 64 The processor supporting Enhanced Intel Speedstep technology allows tradeoffs to be made between performance and power consumpti
81. and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the motherboard trace for front side bus signals For unused GTL input or I O signals use pull up resistors of the same value as the on die termination resistors Rrr For details see Table 2 15 TAP and CMOS signals do not include on die termination Inputs and used outputs must be terminated on the motherboard Unused outputs may be terminated on the motherboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing All TESTHI 13 0 lands should be individually connected to Vy via a pull up resistor that matches the nominal trace impedance Dual Core Intel Xeon Processor 3000 Series Datasheet m Electrical Specifications n tel 2 6 2 6 1 The TESTHI signals may use individual pull up resistors or be grouped together as detailed below A matched resistor must be used for each group TESTHI 1 0 TESTHI 7 2 TESTHI8 FC42 cannot be grouped with other TESTHI signals TESTHI9 FC43 cannot be grouped with other TESTHI signals TESTHI 10 cannot be grouped with other TESTHI signals TESTHI 11 cannot be grouped with other TESTHI signals TESTHI
82. asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins lands of all processor FSB agents ITP_CLK 1 0 Input ITP_CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board ITP_CLK 1 0 are used as BCLK 1 0 references for a debug port implemented on an interposer If a debug port is implemented in the system TP_CLK 1 0 are no connects in the system These are not processor signals LINT 1 0 Input LINT 1 0 Local APIC Interrupt must connect the appropriate pins lands of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these signals as LINT 1 0 is the default configuration LOCK Input Output LOCK
83. ay be directly cooled with a fan heatsink However meeting the processor s temperature specification is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is listed in Chapter 5 The boxed processor fan heatsink is able to keep the processor temperature within the specifications see Table 5 1 in chassis that provide good thermal management For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life Figure 7 7 and Figure 7 8 illustrate an acceptable airspace clearance for the fan heatsink The air temperature entering the fan should be kept below 38 9C Again meeting the processor s temperature specification is the responsibility of the system integrator Dual Core Intel Xeon Processor 3000 Series Datasheet 99 m n tel Boxed Processor Specifications Figure 7 7 Boxed Processor Fan Heatsink Airspace Keepout Requirements Side 1 View R55 2 2 17 Figure 7 8 Boxed Processor Fan Heatsink Airspace Keepout Requirements Side 2 View 100 Dual Core
84. basis 24 2 7 4 Die Voltage Validation ccececece eee e reenter meme memes 24 2 8 Signaling Specificato Sisirin rin n yes pA E ORARE n ka Aa hana R NA wani w na Geran n k n kn 25 2 8 1 FSB Signal Groups sax nu k ka ER rawa Nana n xu n U Xan e na WD Ga E n waa KE YE Deka aA tad 25 2 8 2 CMOS and Open Drain Signals MLMhk kKkWlh llk k h ll kk kk kk kk kk kk kk kak 27 2 8 3 Processor DC Specifications i a al cece k Nabeee hana ENa E kana n na memes 27 2 8 3 1 GTL Front Side Bus Specifications Lh k W kL LCxkkkkk kk 29 2 8 4 Clock Specifications ineo nee Cote tere t bad hr ux ir ra nak edu s Seata benk 29 2 8 5 Front Side Bus Clock BCLK 1 0 and Processor Clocking 29 2 8 6 FSB Frequency Select Signals BSEL 2 0 sess 30 2 8 7 Phase Lock Loop PLL and Filter sess mmm nnns 30 2 8 8 BCLK 1 0 Specifications CK505 based Platforms hkh kh Wk k Ek kk 30 2 8 9 BCLK 1 0 Specifications CK410 based Platforms hhkh kk k kEk kk 32 2 9 PEC DC Specifications ccs nuna sen nnn a 2na da ter h ra I En wn D ND n aa na ENDE ERE TR OE 33 3 Package Mechanical Specifications sss menn 35 3 1 Package Mechanical Drawing sssssssssese meme senem ener 36 3 1 1 Processor Component Keep Out ZONES cece eee eee emm 40 3 1 2 Package Loading Specifications cece eee eee teeta teeta natn
85. be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation 71 intel Table 4 3 Signal Description Sheet 5 Land Listing and Signal Descriptions of 7 Name Type Description REQ 4 0 Input Output REQ 4 0 Request Command must connect the appropriate pins lands of all processor FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTBO RESET Input Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after Vcc and BCLK have reached their proper specifications On observing active RESET all FSB agents will de assert their outputs
86. bers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor number for details intel9 64 requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 Processor will not operate including 32 bit operation without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations See http www intel com info em64t for more information including details on which processors support Intel 64 or consult with your system vendor for more information No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT is a security technology under development by Intel and requires for operation a computer system with Intel Virtualization Technology a Intel Trusted Execution Technology enabled Intel processor chipset BIOS Authenticated Code Modules and an Intel or other Intel Trusted Execution Technology compatible measured virtual machine monitor In addition Intel Trusted Execution Technology requires the system to contain a TPMv1 2 as defined by the Trusted Computing Group and specific software for some uses Intel
87. cate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR Output IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not have on die termination Refer to Section 2 6 2 for termination requirements Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions intel Table 4 3 Signal Description Sheet 4 of 7 Name Type Description IGNNE Input IGNNEZ Ignore Numeric Error is asserted to the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is de asserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error GNNE has no effect when the NE bit in control register 0 CRO is set IGNNEZ is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT Input INIT Initialization when
88. cation includes both static and transient limits except for overshoot allowed as shown in Section 2 6 3 2 This table is intended to aid in reading discrete points on Figure 2 1 3 The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details 4 Adherence to this loadline specification is required to ensure reliable processor operation Dual Core Intel Xeon Processor 3000 Series Datasheet 21 E n tel Electrical Specifications Figure 2 1 Vcc Static and Transient Tolerance for Processors with 4 MB L2 Cache Icc A 0 10 20 30 40 50 60 70 VID 0 000 VID 0 013 4 VID 0 025 4 Vcc Maximum VID 0 038 VID 0 050 4 VID 0 063 4 VID 0 075 4 Vcc V VID 0 088 4 VID 0 100 4 Vcc Minimum VID 0 113 4 VID 0 125 4 VID 0 138 4 VID 0 150 4 VID 0 163 4 Notes 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 6 3 2 This loadline specification shows the deviation from the VID set point 3 Theloadlines specify voltage limits at the die measured at the VCC SENSE and V
89. cation is meant to help ensure proper operation of the processor Figure 5 4 illustrates where Intel recommends Tc thermal measurements should be made For detailed guidelines on temperature measurement methodology refer to the Dual Core Intel Xeon Processor 3000 Series Thermal and Mechanical Design Guidelines Case Temperature Tc Measurement Location Measure Te at this point j geometric center of the package 37 5 mm 37 5 mm Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption by modulating starting and stopping the internal processor core clocks The Thermal Monitor feature must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor feature is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 5096 Clocks oft
90. cation must be maintained by any thermal and mechanical solutions Processor Loading Specifications Parameter Minimum Maximum Notes Static 80 N 17 Ibf 311N 70 Ibf 12 3 Dynamic 756 N 170 Ibf 1 3 4 Notes 1 These specifications apply to uniform compressive loading in a direction normal to the processor IHS 2 This is the maximum force that can be applied by a heatsink retention clip The clip must also provide the minimum specified load on the processor package 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement Package Handling Guidelines Table 3 2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Notes Shear 311 N 70 Ibf 1 2 Tensile 111 N 25 Ibf 2 3 Torque 3 95 N m 35 Ibf in 2 4 Notes 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 These guidelines are based on limited testing for design characterization 3 A tensile load is defined as a pulling load
91. cations PECI is an Intel proprietary one wire interface that provides a communication channel between Intel processors may also include chipset components in the future and external thermal monitoring devices The processor contains Digital Thermal Sensors DTS distributed throughout die These sensors are implemented as analog to digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal fan speed control More detailed information is available in the Platform Environment Control Interface PECI Specification Table 20 PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes Vin Input Voltage Range 0 15 Vit Vhysteresis Hysteresis 0 1 Vr V 2 Vn Negative edge threshold voltage 0 275 V r 0 500 Vr V Vp Positive edge threshold voltage 0 550 V4 0 725 Var V High level output source 6 0 N A mA source Von 0 75 Vg Low level output sink lsi 0 5 1 0 A sink VoL 0 25 V x lleak High impedance state leakage to Vy N A 50 HA 3 Dual Core Intel Xeon Processor 3000 Series Datasheet 33 intel Table 20 34 PECI DC Electrical Limits Electrical Specifications Symbol Definition and Conditions Min Max
92. cessor is in the HALT powerdown state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state While in HALT powerdown state the processor will process bus snoops Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS When one of the processor cores executes the HALT instruction that logical processor is halted however the other processor continues normal operation The Extended HALT Powerdown state must be enabled via the BIOS for the processor to remain within its specification The processor automatically transitions to a lower frequency and voltage operating point before entering the Extended HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor first switches to the lower bus ratio and then transitions to the lower VID While in Extended HALT state the processor processes bus snoops The processor exits the Extended HALT state when a break event occurs When the processor exits the Extended HALT state it will resume operation at the lower frequency first transition the VID to the original value and then change the bus ratio back to the original value Stop Grant and Extended Stop Grant States The processor supports the Stop Grant and Extend
93. cription Sheet 7 Land Listing and Signal Descriptions of 7 Name Type Description VIT Input Miscellaneous voltage supply VTT OUT LEFT Output The VTT OUT LEFT and VIT OUT RIGHT signals are included to provide a voltage supply for some signals that require termination to VIT OUT RIGHT Vr on the motherboard VTT SEL Output The VTT SEL signal is used to select the correct Vy voltage level for the processor This land is connected internally in the package to V 8 Dual Core Intel Xeon Processor 3000 Series Datasheet m e Thermal Specifications and Design Considerations n tel 5 Thermal Specifications and Design Considerations 5 1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as described in Section 5 1 1 Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete thermal solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader IHS Typical system level
94. de asserted This signal must connect the appropriate pins lands on all processor FSB agents Dual Core Intel Xeon Processor 3000 Series Datasheet 69 intel Table 4 3 70 Land Listing and Signal Descriptions Signal Description Sheet 3 of 7 Name Type Description DEFER Input DEFER is asserted by an agent to indicate that a transaction cannot be ensured in order completion Assertion of DEFER is normally the responsibility of the addressed memory or input output agent This signal must connect the appropriate pins lands of all processor FSB agents DRDY Input Output DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be de asserted to insert idle clocks This signal must connect the appropriate pins lands of all processor FSB agents DSTBN 3 0 Input Output DSTBN 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBNO D 31 16 DBI1 DSTBN1 D 47 32 DBI2 DSTBN2 D 63 48 DBI3 DSTBN3 DSTBP 3 0 Input Output DSTBP 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48 DBI3 DSTBP3 FCx Other FC signals are signals that are available f
95. e Material TI M Processor core die Package substrate Capacitors Processor Package Assembly Sketch Core die TIM R n IHS Substrate io Capacitors LGA775 Socket 4 Syste Board DS Note 1 Socket and System Board are included for reference and are not part of processor package Dual Core Intel Xeon Processor 3000 Series Datasheet 35 intel 3 1 36 Package Mechanical Specifications Package Mechanical Drawing The package mechanical drawings are shown in Figure 3 2 and Figure 3 3 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include Package reference with tolerances total height length width etc IHS parallelism and tilt Land dimensions Top side and back side component keep out dimensions Reference datums All drawing dimensions are in mm in Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal Mechanical Design Guidelines Dual Core Intel Xeon Processor 3000 Series Datasheet Package Mechanical Specifications n te Figure 3 2 Processor Package Drawing Sheet 1 of 3 x l HEET oF 3 88285 2200 MISSION COLLEGE BLVD P O BOX 58119 SANTA CLARA CA 95052 8119 core 2 1 rure MODEL LJ WHS LID
96. e processor should not be subjected to any Vcc and Icc combination wherein Vcc exceeds Vcc max for a given current Icc Max Specification is based on the Vcc max loadline Refer to Figure 2 1 for details V r must be provided via a separate voltage source and not be connected to Vcc This specification is measured at the land Baseboard bandwidth is limited to 20 MHz This is maximum total current drawn from V plane by only the processor This specification does not include the current coming from RTT through the signal line Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total Iz drawn by the system This parameter is based on design characterization and is not tested Table 2 5 Vcc Static and Transient Tolerance for Processors with 4 MB L2 Cache Voltage Deviation from VID Setting V 2 3 4 lec A Maximum Voltage Typical Voltage Minimum Voltage 1 30 mo 1 425 mo 1 55 mo 0 000 0 019 0 038 5 0 007 0 026 0 046 10 0 013 0 033 0 054 15 0 020 0 040 0 061 20 0 026 0 048 0 069 25 0 033 0 055 0 077 30 0 039 0 062 0 085 35 0 046 0 069 0 092 40 0 052 0 076 0 100 45 0 059 0 083 0 108 50 0 065 0 090 0 116 55 0 072 0 097 0 123 60 0 078 0 105 0 131 65 0 085 0 112 0 139 70 0 091 0 119 0 147 75 0 098 0 126 0 154 Notes 1 The loadline specifi
97. ed Stop Grant states The Extended Stop Grant state is a feature that must be configured and enabled via the BIOS Refer to the BIOS Writer s Guide for Extended Stop Grant configuration information Refer to the following sections for details about the Stop Grant and Extended Stop Grant states Stop Grant State When the STPCLK signal is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Since the GTL signals receive power from the FSB these signals should not be driven allowing the level to return to V for minimum power drawn by the termination resistors in this state In addition all other input signals on the FSB should be driven to the inactive state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal Dual Core Intel Xeon Processor 3000 Series Datasheet 91 intel Dro 6 2 3 2 6 2 4 6 2 4 1 6 2 4 2 92 A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB see Section 6 2 4 While in the Stop Grant State SMI INIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal State Only one occurrence of each event will be recognized upon return to the No
98. eeee teeta ee eee 41 3 6 Processor Top Side Markings Example for the Dual Core Intel Xeon Processor 3000 Series with 4 MB L2 Cache with 1066 MHZ FSB cceceeeee eee eee eee 42 3 7 Processor Top Side Markings Example for the Dual Core Intel Xeon Processor 3000 Series with 4 MB L2 Cache with 1333 MHz FSB assesseer 42 3 8 Processor Land Coordinates and Quadrants Top VieW cceceeee eee ee eee kk kk 43 4 1 land out Diagram Top View Left Side h KGL K KAK KC KW Stsk kk kk kk kk kk mmn nns 46 4 2 land out Diagram Top View Right Side sssssssssseeeem mene 47 5 1 Thermal Profile Dual Core Intel Xeon Processor 3000 Series with 4 MB L2 Cache MKKAKhKA b KkhK k kk kk kk kk aka kaka kaka aka kaka kaka kak aka aka kak ka aka kaka aka kak kk kaka 77 5 2 Thermal Profile Dual Core Intel Xeon 3070 3060 Processor With 4 MB L2 Gaclie iiis eic cene eno a wes coe PERRO r rp ym 78 5 3 Thermal Profile Dual Core Intel Xeon Processor 3000 Series With 2 MB L2 Cache i iier erc too oe Pucci a a era W V a e d b Eq Er e PA REN 79 5 4 Case Temperature TC Measurement LOCatiION ccccceceee ects tence eee kk kk kk kk 80 5 5 Thermal Monitor 2 Frequency and Voltage Ordering c cc ceeeeee eee eee ee eee ee kk 82 5 6 Processor PECI TODOLO ya k s xani un bi d 44 ha e ene a ra karok aya ses eee nena enna 86 7 Conceptual Fan Control on PECI Based Platforms ssssss
99. elivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details Dual Core Intel Xeon Processor 3000 Series Datasheet 23 Table 2 7 Figure 2 3 2 6 4 24 Electrical Specifications Vcc Overshoot The processor can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot voltage The time duration of the overshoot event must not exceed Tos max Tos max is the maximum allowable time duration above VID These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_ SENSE lands Vcc Overshoot Specifications Symbol Parameter Min Max Unit Figure Notes Vos_max Magnitude of Vcc overshoot above VID 50 mV 2 3 1 Tos Max Time duration of Vcc overshoot above VID 25 us 2 3 1 Notes 1 Adherence to these specifications is required to ensure reliable processor operation Vcc Overshoot Example Waveform Example Overshoot Waveform VID 0 050 Vos co o S o gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID Notes 1 Vos is measured overshoot voltage 2 Tos is measured time duration above VID Die Voltage Validation Overshoot events on processo
100. ems Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of systems the LAI is critical in providing the ability to probe and capture FSB signals There are two sets of considerations to keep in mind when designing a system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI lands plug into the processor socket while the processor lands plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor s heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the FSB therefore it is critical to obtain electrical load models from each of
101. en will not be off for more than 3 0 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases Dual Core Intel Xeon Processor 3000 Series Datasheet m e Thermal Specifications and Design Considerations n tel 5 2 2 With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and in some cases may result in a Tc that exceeds the specified maximum temperature and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the Dual Core
102. eratures The relative temperature value reported over PECI represents the delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT assertions As the temperature approaches TCC activation the PECI value approaches zero TCC activates at a PECI count of zero Conceptual Fan Control on PECI Based Platforms Fan Speed RPM TcoNTROL TCC Activation Setting Temperature l l Max PECI 0 PECI 10 Temperature Note Not intended to depict actual implementation Dual Core Intel Xeon Processor 3000 Series Datasheet Thermal Specifications and Design Considerations intel Figure 8 Conceptual Fan Control on Thermal Diode Based Platforms Fan Speed RPM TcontROL Setting Tp ope 70 C Temperature TCC Activation Max Tpiope 80 C Temperature Torone 90 C Dual Core Intel Xeon Processor 3000 Series Datasheet 87 n tel Thermal Specifications and Design Considerations 5 4 2 5 4 2 1 5 4 2 2 5 4 2 3 5 4 2 4 Table 8 88 PECI Specifications PECI Device Address The PECI device address for socket 0 is 30h and socket 1 resides at 31h Note that each address also supports two domains Domain 0 and Domain 1 For more information on PECI domains refer to the Platform Environment Control Interface Specification PECI Command Support PECI comma
103. es shown marked with alphabetic designations to clarify relative dimensioning Space Requirements for the Boxed Processor Side View 95 0 IM 3 74 Po J 81 3 3 2 10 0 25 0 y 0 39 0 98 Y p 4 Space Requirements for the Boxed Processor Top View R55 2 2 17 Notes 1 Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation Dual Core Intel Xeon Processor 3000 Series Datasheet m e Boxed Processor Specifications n tel Figure 7 4 Space Requirements for the Boxed Processor Overall View 7 1 2 7 1 3 7 2 7 2 1 Diwar Donn kara aa Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams See Chapter 5 and the Dual Core Intel Xeon Processor 3000 Series Thermal and Mechanical Design Guidelines for details on the processor weight and heatsink requirements Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly The boxed processor thermal solution requires a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket The boxed processor will ship with the heatsink attach clip assembly Electrical Requirements Fan Heatsink Power Supply The boxed processor s fan heatsink requires a 12 V power supply A fan power cable will be shipped with the
104. ese conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Dual Core Intel Xeon Processor 3000 Series Datasheet 19 E n tel Electrical Specifications Table 2 3 Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes 2 Vcc Core voltage with respect to Vss 0 3 1 55 V Vir FSB termination voltage with respect to 0 3 1 55 V Vss Tc Processor case temperature See See C Chapter 5 Chapter 5 TsTORAGE Processor storage temperature 40 85 C 3 4 5 Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation refer to the processor case temperature specifications 4 This rating applies to the process
105. etails on which processor frequencies support this feature is provided in the Dual Core Intel Xeon Processor 3000 Series Specification Update Enhanced Intel SpeedStep Technology creates processor performance states P states or voltage frequency operating points P states are lower power capability states within the Normal state as shown in Figure 6 1 Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system The processor has hardware logic that coordinates the requested voltage VID between the processor cores The highest voltage that is requested for either of the processor cores is selected for that processor package Note that the front side bus is not altered only the internal core frequency is changed To run at reduced power consumption the voltage is altered in step with the bus ratio Dual Core Intel Xeon Processor 3000 Series Datasheet 93 intel iiis 94 The following are key features of Enhanced Intel SpeedStep Technology Multiple voltage frequency operating points provide optimal performance at reduced power consumption Voltage frequency selection is software controlled by writing to processor MSRs
106. f this document 2 This document may not be released as of the publication of this document 3 Thermal models of the processor will be provided by Intel These models are password protected The password is Thrm amp Md 6 05 Contact your field sales representative for delivery of these models 4 The Enabled Components files are in ProE format and are password protected with the password Thrm amp Md 05 Contact your field sales representative for delivery of these models 5 The I O Buffer Models are in IBIS format Both models and the overshoot checker tool are password protected The password is Bf41rz amp d Contact your field sales representative for delivery of these models Dual Core Intel Xeon Processor 3000 Series Datasheet m Electrical Specifications n tel 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals DC and AC electrical characteristics are provided 2 1 Power and Ground Lands The processor has VCC power VIT and VSS ground inputs for on chip power distribution All power lands must be connected to Vcc while all Vss lands must be connected to a system ground plane The processor Vcc lands must be supplied the voltage determined by the Voltage I Dentification VID lands The signals denoted as V provide termination for the front side bus and power to the I O buffers A separate supply must be implemented for these lands that meets
107. h DAEURREFRPRKREPERRREU Dak a ia 81 5 2 3 On Demand Mod sx a cres Naka makina XR RIA ERG WEE AA n r y w D W ra A w a W ra E Wa han 82 52 4 PROCHOU Signal ertet nan h n esee biki a b heban n bek Uta su aed hela Yaa 83 5 25 THERMTRIP Signal iier cese dik le nana a len persa ARR RE REYE 83 5 3 Platform Environment Control Interface PECI ccccccccec cece sees Henn 84 arl INCrODUCUION scat occidit aw tcr Dani gam nescire d helle aO cate uada ra 84 5 3 1 1 Key Difference with Legacy Diode Based Thermal Management 84 5 3 2 PECI Specifications oe eei ina oce bala nena nan en n n e mor ea b Wad Dan mars 86 5 3 2 1 PECI Device Address ote nin b wa ra n Dek a d eae 86 5 3 2 2 PECI Command SUPON a e erit layan nya ran nayan EAD FEARE E sk wa kiya n Ra Wa 86 5 3 2 3 PECI Fault Handling Requirements eeen 86 5 3 2 4 PECI GetTemp0 Error Code Support sssssseeses 86 PO Qture i cicsi sec uL a E EA E A E E E E A NA aa 87 6 1 Power On Configuration Options ccc m Hmmm sese memes nens 87 6 2 Clock Control and Low Power States sssssssssssssseeenemememe n enemies enn 87 6 2 1 Normal State wo cece nenne mene nne nennen nnn nennen nnn nenne nnn 88 6 2 2 HALT and Extended HALT Powerdown States ssssssseseseee 88 6 2 2 1 HALT Powerdown State 4 L KhK Kk A3kk lh kk kk kk nennen nennen nn 88 6 2 2 2 Extended HALT Powerdow
108. he VID signals are needed to support the processor voltage specification variations See Table 2 1 for definitions of these signals The VR must supply the voltage that is requested by the signals or disable itself VID SELECT Output This land is tied high on the processor package and is used by the VR to choose the proper VID table Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information VRDSEL Input This input should be left as a no connect in order for the processor to boot The processor will not boot on legacy platforms where this land is connected to Vss VSS Input VSS are the ground pins for the processor and should be connected to the system ground plane VSSA Input VSSA is the isolated ground for internal PLLs VSS SENSE Output VSS SENSE is an isolated low impedance connection to processor core Vss It can be used to sense or measure ground near the silicon with little noise VSS MB REGULATI ON Output This land is provided as a voltage regulator feedback sense point for Vss It is connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket Dual Core Intel Xeon Processor 3000 Series Datasheet 73 intel Table 4 3 74 Signal Des
109. heet Electrical Specifications 2 7 3 1 Table 2 15 2 7 4 2 7 5 intel GTL Front Side Bus Specifications In most cases termination resistors are not required as these are integrated into the processor silicon See Table 2 9 for details on which GTL signals do not include on die termination Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF Table 2 15 lists the GTLREF specifications The GTL reference voltage GTLREF should be generated on the system board using high precision voltage divider circuits GTL Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes GTLREF_PU GTLREF pull up resistor on 124 0 99 124 124 1 01 Q 2 Mukilteo 2 3000 3010 chipset family boards GTLREF_PD GTLREF pull down resistor on 210 0 99 210 210 1 01 Q 2 Mukilteo 2 3000 3010 chipset family boards GTLREF PU GTLREF pull up resistor on 100 0 99 100 100 1 01 Q 2 Bearlake chipset family boards GTLREF_PD GTLREF pull down resistor on 200 0 99 200 200 1 01 Q 2 Bearlake chipset family boards Rr Termination Resistance 45 50 55 Q 3 COMP 3 0 COMP Resistance 49 40 49 90 50 40 Q 4 COMP8 COMP Resistance 24 65 24 90 25 15 Q 4 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 GTLREF is to be generated from V by a voltage divider of 1 resistors
110. hen asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is de asserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK Input TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI Input TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for J TAG specification support TDO Output TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TESTHI 13 0 Input TESTHI 13 0 must be connected to the processor s appropriate power source refer to VIT OUT LEFT and VTT OUT RIGHT signal description through a resistor for proper processor operation See Section 2 5 for more details THERMDA Other Thermal Diode Anode See Section 5 3 THERMDC Other Thermal Diode Cathode See Section 5 3 72 Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions
111. her VCC AJ12 Power Other VCC AF18 Power Other VCC AJ14 Power Other VCC AF19 Power Other VCC AJ15 Power Other VCC AF21 Power Other VCC AJ18 Power Other VEC AF22 Power Other VCC AJ19 Power Other VCC AF8 Power Other VCC AJ21 Power Other VCC AF9 Power Other VCC AJ 22 Power Other VCC AG11 Power Other VCC AJ25 Power Other VCC AG12 Power Other VCC AJ26 Power Other VCC AG14 Power Other VCC AJ8 Power Other VCC AG15 Power Other VCC AJ9 Power Other Dual Core Intel Xeon Processor 3000 Series Datasheet 51 m n tel Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Table 4 1 Alphabetical Land Assignments Sheet 9 of 20 Assignments Sheet 10 of 20 Land Name Land m Direction Land Name Land k u Direction VCC AK11 Power Other VCC AN11 Power Other VCC AK12 Power Other VCC AN12 Power Other VCC AK14 Power Other VCC AN14 Power Other VCC AK15 Power Other VCC AN15 Power Other VCC AK18 Power Other VCC AN18 Power Other VCC AK19 Power Other VCC AN19 Power Other VCC AK21 Power Other VCC AN21 Power Other VCC AK22 Power Other VCC AN22 Power Other VCC AK25 Power Other VCC AN25 Power Other VCC AK26 Power Other VCC AN26 Power Other VCC AK8 Power Other VCC AN29 Power Other VCC AK9 Power Other VCC AN30 Power Other VCC AL11 Power Other VCC AN8 Power Other VCC AL12 Power Other VCC AN9 Power Other VCC AL14 Power Other
112. ily BIOS Writer s Guide BWG Dual Core Intel Xeon Processor 3000 Series Thermal and Mechanical Design Guidelines Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket CK505 Clock Synthesizer Driver Specification LGA775 Socket Mechanical Design Guide 1A 32 Intel Architecture Software Developer s Manuals Intel 64 and IA 32 Architecture Software Developer s Manual Volume 1 Basic Architecture Intel 64 and 1A 32 Architecture Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architecture Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architecture Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architecture Software Developer s Manual Volume 3B System Programming Guide http www intel com products processor manuals Conroe Processor Thermal Models Dual Core Intel Xeon Processor 3000 Series Datasheet 13 Introduction Document Location Notes Conroe Processor Enabled Components Drawings 1 2 4 Conroe Processor O Buffer Models 1 2 5 1 2 5 Conroe Processor Overshoot Checker Debug Port Design Guide for Intel 975X 3000 3010 Bearlake and Bigby 1 Family Chipset Systems Notes 1 Contact your Intel representative for the latest revision and order number o
113. inology eere ire bana ten re eere bed se me n n b layen Ure kan kab n en Pe ern ci ead aus 11 LLI Processor Terminology retenir aerea ie cete a sus adek Ab n nean na Wa xan aaa I Rd 12 1 2 References e gt gt e rDNDN IP AA e o op nerreeeJJ m m 13 2 Electrical Specifications oot wak n narik nad nan n banke ne nbn siete Rr wand n bak aw bka MU EE 15 2 1 Power and Ground Lands s i sas suc sanl tosses e wa n nad ka Yan riha eerie 15 2 2 Decoupling G idelln s ioter retenti ek ree h a wan IER rk Bala Wa K nika k na kax aie nda RR 15 2 2 1 VCC Decoupling srn n ieee RUANDA FEM en a ae Sa n d r Sada 15 2 2 2 Vtt DECOUPLING oit nn alan nanan d n nn kar n kkin D n b n W h ran D kan V ma DN p ya Mak v dayan a 15 2 2 3 FSB Decouplingi tific cx or rte i eer ees pre ee rer adios wale bk na Lege Poe diens 16 2 3 Voltage Identification iie rhet RI Rx R ux pr EIRERR Aag XR PRG aa ed Spada 16 2 4 Market Segment Identification MSID ssssssssssee mme 18 2 5 Reserved Unused and TESTHI Signals esses 18 LACE 19 2 7 Voltage and Current Specification Lh hW_ kk kk kk nemen memes 19 2 7 1 Absolute Maximum and Minimum Ratings sssssee Hee 19 2 7 2 DC Voltage and Current Specification sssssssssseenn mne 20 2 7 3 NEG OVersliOO0E iere tei ba kana en er EX ERE ERE RTAYRR EATER EXER T EXKRERK A nenn Ma EE
114. k Input H9 VSS Power Other F29 RESERVED H10 VSS Power Other G1 FC27 Power Other H11 VSS Power Other G2 COMP2 Power Other Input H12 VSS Power Other G3 TESTHI8 FC42 Power Other Input H13 VSS Power Other G4 TESTHI9 FC43 Power Other Input H14 VSS Power Other G5 PECI Power Other Input Output H15 FC32 Power Other G6 RESERVED H16 FC33 Power Other G7 DEFER Common Clock Input H17 VSS Power Other G8 BPRI Common Clock Input H18 VSS Power Other G9 D16 Source Synch Input Output H19 VSS Power Other G10 FC38 Power Other H20 VSS Power Other G11 DBI1 Source Synch Input Output H21 VSS Power Other G12 DSTBN1 Source Synch Input Output H22 VSS Power Other G13 D27 Source Synch Input Output H23 VSS Power Other G14 D29 Source Synch Input Output H24 VSS Power Other G15 D31 Source Synch Input Output H25 VSS Power Other G16 D32 Source Synch Input Output H26 VSS Power Other G17 D36 Source Synch Input Output H27 VSS Power Other G18 D35 Source Synch Input Output H28 VSS Power Other G19 DSTBP2 Source Synch Input Output H29 FCS Power Other G20 DSTBN2 Source Synch Input Output H30 BSEL1 Power Other Output G21 D44 Source Synch Input Output jl VTT_OUT_LEFT Power Other Output G22 D47 Source Synch Input Output J2 FC3 Power Other G23 RESET Common Clock Input J3 FC22 Power Other G24 TESTHI6 Power Other Input J4 VSS Power Other G25 TESTHI3 Power Other Input J5 REQ1 Source Synch Input Output 60 Dual Core Intel Xeon Processor 3000 Se
115. kk kk ka ene 40 3 2 Package Handling Guidelines sse ale kla a kd nnn 40 3 3 Processor Materials errare ana han Wana Din opea nanna b n ur Wi bare Da wa b na re DER b d EEE D 41 4 1 Alphabetical Land ASS gnm entS kk kk kk kk kk kak kk kak ie esses 48 4 2 Numerical Land Assignment k k lhKkkkkl kk kk kk emen kk kaka ka ka kaka kak 58 4 3 Signal Sale e ERREUR 68 5 1 Processor Thermal Specifications ccc cece eee eee eee eee nena tad 76 5 2 Thermal Profile Dual Core Intel Xeon Processor 3000 Series With 4 MB L2 Cache a xa saya ay eor cia xir ike En be EVER EEEFYRRE na dk Aka a an a a aran aka ab kak 43 TE XA EENAA 77 5 3 Thermal Profile Dual Core Intel Xeon 3070 3060 Processor With 4 MB LZ CAG O s 2 sxa sana nana nma nan n kab Y es aan canes CRF n hak n d ka ER ERE hal k r k ka n Eagle aa eade 78 5 4 hermal Profile Dual Core Intel Xeon Processor 3000 Series With 2 MB E2 Cache orenian caxtnsauaeiahovvatgacnnts unen XE ber EE PEN M AD TRE e 79 5 5 Thermal Diode Parameters using Diode Model csssssssee mme 84 5 6 Thermal Diode Parameters using Transistor Model sssssmee 85 7 Thermal Diode Interface irre nan bi beken n diana nana Wae br rre recess EEE se E N DEK b r b 85 8 GetTempO Error O d Sl kk dise cla a k lll ee eee eese eee 88 6 1 Power On Configuration Option
116. l Package Mechanical Specifications Figure 3 6 Processor Top Side Markings Example for the Dual Core I ntel Xeon Processor 3000 Series with 4 MB L2 Cache with 1066 MHz FSB 2 40GHZ2 4M 1066 06 INTELG XEONG 3060 Sls CO0 ieo 05 FPO amp Figure 3 7 Processor Top Side Markings Example for the Dual Core I ntel Xeon Processor 3000 Series with 4 MB L2 Cache with 1333 MHz FSB INTEL 05 3065 INTEL XEON Sue COO 2 o 83GHZ 4713337 06 FPO 42 Dual Core Intel Xeon Processor 3000 Series Datasheet Package Mechanical Speci 3 2 1 cations Processor Land Coordinates intel Figure 3 8 shows the top view of the processor land coordinates The coordinates are referred to throughout the document to identify processor lands Figure 3 8 Processor Land Coordinates and Quadrants Top View Voc Vas 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7 65 4 21 O00000 OOOO0O00 AN kuz Az O V O J ENS WU O A CN CON 08 CN ES XN D PY SCC ic AM OO OC O O O zur kuz WOW O ON CS CS 0 0 S000 00 ODOT Y AL OOOOOO OOOOOOOO uw O 0O 0060 000000C O AK OOOOOO00 00000000 Aw NON 6 0 0 i CY OY 000000 nr ant AJ O O O O O O OOOOOOOOOOOO00 ACE SITSERS ESSI CY 9 00 9090 0 OOO a AH A O O QUU DAD MDA DAD ED DIP IID kuz Beat ave Ei CYC Cr ACY OAD OLY CY Y y AG OOOOOOQC OOOOOOOOOOO000 I f
117. l has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage The 4th wire PWM solution provides better control over chassis acoustics This is achieved by more accurate measurement of processor die temperature through the processor s temperature diode T diode Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures If the new 4 pin active fan heat sink solution is connected to an older 3 pin baseboard processor fan header it will default back to a thermistor controlled mode allowing compatibility with existing 3 pin baseboard designs Under thermistor controlled mode the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet For more details on specific motherboard requirements for 4 wire based fan speed control see the Dual Core Intel Xeon Processor 3000 Series Thermal and Mechanical Design Guide Dual Core Intel Xeon Processor 3000 Series Datasheet m e Debug Tools Specifications n tel 8 8 1 8 1 1 8 1 2 Debug Tools Specifications Logic Analyzer I nterface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging syst
118. l operating state for the processor HALT and Extended HALT Powerdown States The processor supports the HALT or Extended HALT powerdown state The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification Refer to the Conroe Processor Family BIOS Writer s Guide BWG for Extended HALT configuration information The Extended HALT state is a lower power state as compared to the Stop Grant State f Extended HALT is not enabled the default Powerdown state entered will be HALT Refer to the following sections for details about the HALT and Extended HALT states HALT Powerdown State HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions When one of the processor cores executes the HALT instruction that processor core is halted however the other processor continues normal operation The processor transitions to the Normal state upon the occurrence of SMI INIT or LINT 1 0 NMI INTR RESET causes the processor to immediately initialize itself Dual Core Intel Xeon Processor 3000 Series Datasheet Features 6 2 2 2 6 2 3 6 2 3 1 intel The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the IA 32 Intel Architecture Software Developer s Manual Volume 3 System Programmer s Guide for more information The system can generate a STPCLK while the pro
119. m and is used by the processor to request the bus During power on configuration this signal is sampled to determine the agent ID 0 This signal does not have on die termination and must be terminated BSEL 2 0 Output The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor input clock frequency Table 2 17 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency For more information about these signals including termination recommendations refer to Section 2 7 6 COMP8 COMP 3 0 Analog COMP 3 0 and COMP8 must be terminated to Vss on the system board using precision resistors D 63 0 Input Output D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor FSB agents and must connect the appropriate pins lands on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DBI Quad Pumped Signal Groups Data Group cs D
120. moisture sensitivity labeling MSL as indicated on the packaging material Functional operation Refers to normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system See the Intel Architecture Software Developer s Manual for more detailed information Dual Core Intel Xeon Processor 3000 Series Datasheet Introduction 1 2 intel Intel 64 Architecture An enhancement to Intel s A 32 architecture allowing the processor to execute operating systems and applications written to take advantage of Intel 64 Further details on Intel 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at http developer intel com technology 64bitextensions Enhanced Intel SpeedStep Technology Enhanced Intel Speedstep Technology allows trade offs to be made between performance and power consumptions based on processor utilization This may lower average power cons
121. n State kMhK KA K kk kk kk kk kk kk kk kk k 89 6 2 3 Stop Grant and Extended Stop Grant States Mk Kk hANWS kK nrn 89 6 2 3 1 Stop Grant State crecer ana la nia kab bla ke ben back ca ele kan b a b 89 6 2 3 2 Extended Stop Grant State ML K M L NJkkkK kk kk 90 6 2 4 Extended HALT Snoop State HALT Snoop State Extended Stop Grant Snoop State and Stop Grant Snoop State 2 0 0 cece eee ee kk kk teenies 90 6 2 4 1 HALT Snoop State Stop Grant Snoop State cece ee een eee eee 90 6 2 4 2 Extended HALT Snoop State Extended Stop Grant Snoop State 90 6 3 Enhanced Intel SpeedStep Technology cececeeeee eee kk kk kk kk 90 Boxed Processor Specifications c ccc etn emnes 93 7 1 Mechanical Specifications creer enter awiran e RR ced nan bakan hak EXE EROR A Rare Wan a Z na 94 7 1 1 Boxed Processor Cooling Solution Dimensions see 94 7 1 2 Boxed Processor Fan Heatsink Weight ssssssssseenmm ka 95 7 1 3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly 95 7 2 Electrical Requirements cect Eee nene memes ens 95 7 2 1 Fan Heatsink Power Supply sssssssssseee memes 95 7 3 Thermal Specifications ceo rr re tee euet xa eed ela b l ec LA Re aaa E ERE RERTK RE 97 7 3 1 Boxed Processor Cooling Requirements ssssssssseenn mms 97 Taz VMariable Speed Fax sl den eterni enitn nanan
122. nch Input Output AQ VSS Power Other A10 DO8 Source Synch Input Output All D09 Source Synch Input Output A12 VSS Power Other A13 COMPO Power Other Input A14 D50 Source Synch Input Output A15 VSS Power Other A16 DSTBN3 Source Synch Input Output A17 D56 Source Synch Input Output A18 VSS Power Other A19 D61 Source Synch Input Output A20 RESERVED A21 VSS Power Other A22 D62 Source Synch Input Output A23 VCCA Power Other A24 FC23 Power Other A25 VIT Power Other A26 VIT Power Other A27 VIT Power Other A28 VIT Power Other A29 VIT Power Other A30 VIT Power Other B1 VSS Power Other B2 DBSY Common Clock Input Output B3 RSO Common Clock Input B4 DOO Source Synch Input Output B5 VSS Power Other B6 DO5 Source Synch Input Output B7 D06 Source Synch Input Output B8 VSS Power Other B9 DSTBPO Source Synch Input Output B10 D10 Source Synch Input Output B11 VSS Power Other 58 Land Listing and Signal Descriptions Table 4 2 Numerical Land Assignment Sheet 2 of 20 tana Land Name signal Buffer Direction Type B12 D13 Source Synch Input Output B13 COMP8 Power Other Input B14 VSS Power Other B15 D53 Source Synch Input Output B16 D55 Source Synch Input Output B17 VSS Power Other B18 D57 Source Synch Input Output B19 D60 Source Synch Input Output B20 VSS Power Other B21 D59 Source Synch Input Output
123. nd support is covered in detail in the Platform Environment Control Interface Specification Refer to this document for details on supported PECI command function and codes PECI Fault Handling Requirements PECI is largely a fault tolerant interface including noise immunity and error checking improvements over other comparable industry standard interfaces The PECI client is as reliable as the device that it is embedded in and thus given operating conditions that fall under the specification the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures There are however certain scenarios where the PECI is know to be unresponsive Prior to a power on RESET and during RESET assertion PECI is not ensured to provide reliable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host controller should take action to protect the system from possible damaging states It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive gettemp s or for a one second time interval The host controller may also implement an alert to sof
124. ned thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for details on implementing the bi directional PROCHOT feature THERMTRI P Signal Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 4 3 At this point the FSB signal THERMTRIP will go active and stay active as described in Table 4 3 THERMTRIP activation is independent of processor activity and does not generate any bus cycles Thermal Diode The processor incorporates an on die PNP transistor where the base emitter junction is used as a thermal diode with its collector shorted to ground A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control Table 5 5 Table 5 6 and Table 7 provide Dual Core Intel Xeon Processor 3000 Series Datasheet 83 Table 5 5 84 Thermal Specifications and Design Considerations the diode parameter and interface specifications Two different sets of diode parameters are listed in Table 5 5 and Table 5 6 The Diode Model parameters
125. not be asserted during RESET 3 Disabling of any of the cores within the processor must be handled by configuring the EXT_CONFIG Model Specific Register MSR This MSR will allow for the disabling of a single core Clock Control and Low Power States The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 6 1 for a visual representation of the processor low power states Dual Core Intel Xeon Processor 3000 Series Datasheet 89 intel icd Figure 6 1 Processor Low Power State Machine 6 2 1 6 2 2 6 2 2 1 90 HALT or MWAIT Instruction and HALT Bus Cycle Generated Extended HALT or HALT Normal State INIT INTR NMI SMI RESET State Normal Execution FSB interrupts BCLK running Snoops and interrupts allowed Snoop Snoop Event Event STPCLK Occurs Serviced Asserted STPCLK STPCLK STPCLK Asserted De asserted De asserted Extended HALT Snoop or HALT Snoop State BCLK running Service Snoops to caches v Extended Stop Grant Extended Stop Grant State or Stop Grant State Snoop Event Occurs Snoop or Stop Grant BCLK running Snoops and interrupts allowed Snoop State BCLK running Service Snoops to caches Snoop Event Serviced Normal State This is the norma
126. on The Dual Core Intel Xeon processor 3000 series also include the Execute Disable Bit capability This feature combined with a supported operating system allows memory to be marked as executable or non executable The Dual Core Intel Xeon processor 3000 series support Intel Virtualization Technology Virtualization Technology provides silicon based functionality that works together with compatible Virtual Machine Monitor VMM software to improve on software only solutions The Dual Core Intel Xeon processor 3000 series support Intel Trusted Execution Technology Intel TXT Intel Trusted Execution Technology Intel TXT is a security technology 8 Dual Core Intel Xeon Processor 3000 Series Datasheet Introduction 1 Note 1 1 intel Introduction The Dual Core Intel Xeon processor 3000 series combines the performance of previous generation products with the power efficiencies of a low power microarchitecture to enable smaller quieter systems These processors are 64 bit processors that maintain compatibility with A 32 software The Dual Core Intel Xeon processor 3000 series uses Flip Chip Land Grid Array FC LGA6 package technology and plugs into a 775 land surface mount Land Grid Array LGA socket referred to as the LGA775 socket In this document unless otherwise specified the Dual Core Intel Xeon processor 3000 series refers to Dual Core Intel Xeon processors 3085 3075 3070 306
127. on the processor silicon and are terminated to V7 Intel chipsets will also provide on die termination thus eliminating the need to terminate the bus on the motherboard for most GTL signals FSB Signal Groups The front side bus signals have been combined into groups by buffer type GTL input signals have differential input buffers which use GTLREF 1 0 as a reference level In this document the term GTL Input refers to the GTL input group as well as the GTL I O group when receiving Similarly GTL Output refers to the GTL output group as well as the GTL I O group when driving With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals which are dependent upon the rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asychronous signals are still present A20M IGNNEZ etc and can become active at any time during the clock cycle Table 2 8 identifies which signals are common clock source synchronous and asynchronous FSB Signal Groups Sheet 1 of 2 Signal Group Type Signals GTL Common Synchronous to BPRI DEFER RESET RS 2 0 TRDY Clock Input BCLK 1 0 GTL Common Synchronous to ADS BNR BPM 5 0 BRO DBSY DRDY HIT HITM
128. or and does not include any tray or packaging 5 Failure to adhere to this specification can affect the long term reliability of the processor 2 6 2 DC Voltage and Current Specification Table 2 4 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 2 VID Range VID 0 8500 1 5 V 3 Vec Processor Number Vcc for Refer to Table 2 5 and V 4 5 6 4 MB L2 Cache 775 VR CONFIG 06 Figure 2 1 3085 3 00 GHz 3075 2 66 GHz 3070 2 66 GHz 3065 2 33 GHz 3060 2 40 GHz Processor Number Vcc for Refer to Table 2 6 and 2 MB L2 Cache 775 VR CONFIG 06 Figure 2 2 3050 2 13 GHz 3040 1 86 GHz Vcc Boot Default Vcc voltage for initial power up 1 10 V VcceLL PLL Vcc 596 1 50 596 lec Processor Number Icc for A 7 775 VR CONFIG 06 3085 3 00 GHz 75 3075 2 66 GHz 75 3070 2 66 GHz 75 3065 2 33 GHz 75 3060 2 40 GHz 75 3050 2 13 GHz 75 3040 1 86 GHz 75 Vr FSB termination voltage 1 14 1 20 1 26 V 8 DC AC specifications VTT OUT LEFT and DC Current that may be drawn from 580 mA 9 VIT OUT RIGHT Icc VIT OUT LEFT and VIT OUT RIGHT per pin ltr Icc for V supply before Vcc stable 4 5 A 10 Icc for Vr supply after Vcc stable 4 6 lcc vccPLL lec for PLL land 130 mA Icc GTLREF Icc for GTLREF 200 HA 20 Dual Core Intel Xeon Processor 3000 Series Datasheet m Electrical Specifications n tel Notes 1 2
129. or compatibility with other processors FERR PBE Output FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to volume 3 of the Intel Architecture Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note GTLREF 1 0 Input GTLREF 1 0 determine the signal reference level for GTL input signals GTLREF is used by the GTL receivers to determine if a signal is a logical O or logical 1 HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indi
130. output PROCHOTZ Processor Hot will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT Z by the system will activate the TCC if enabled for both cores The TCC will remain active until the system de asserts PROCHOT PROCHOT allows for some protection of various components from over temperature situations The PROCHOTZ signal is bi directional in that it can either signal when the processor either core has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components PROCHOT can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on PROCHOTZ only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power With a properly designed and characterized thermal solution it is anticipated that PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under desig
131. ower Other D59 B21 Source Synch Input Output FC32 H15 Power Other D60 B19 Source Synch Input Output FC33 H16 Power Other D61 A19 Source Synch Input Output FC34 J17 Power Other D62 A22 Source Synch Input Output FC35 H4 Power Other D63 B22 Source Synch Input Output FC36 AD3 Power Other Dual Core Intel Xeon Processor 3000 Series Datasheet 49 intel Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Table 4 1 Assignments Sheet 5 of 20 Alphabetical Land Assignments Sheet 6 of 20 Land Name Land Gu Direction Land Name Land Tu Direction FC37 AB3 Power Other RESERVED F29 FC38 G10 Power Other RESERVED G6 FC38 C9 Power Other RESERVED NA FC39 AA2 Power Other RESERVED N5 FC40 AM6 Power Other RESERVED P5 FERR PBE R3 Asynch CMOS Output RESERVED v2 GTLREFO H1 Power Other Input RESET G23 Common Clock Input GTLREF1 H2 Power Other Input RSO B3 Common Clock Input HIT D4 Common Clock Input Output RS1 F5 Common Clock Input HITM E4 Common Clock Input Output RS2 A3 Common Clock Input IERR AB2 Asynch CMOS Output SKTOCC AE8 Power Other Output IGNNE Z N2 Asynch CMOS Input SMI P2 Asynch CMOS Input INIT P3 Asynch CMOS Input STPCLK M3 Asynch CMOS Input ITP CLKO AK3 TAP Input TCK AE1 TAP Input ITP CLK1 AJ3 TAP Input TDI AD1 TAP Input LINTO K1 Asynch CMOS Input TDO AF1 TA
132. processor configuration options See Section 6 1 for details 4 PROCHOT signal type is open drain output and CMOS input Table 2 9 Signal Characteristics Signals with RTT Signals with No R t PROCHOT REQ 4 0 RS 2 0 TRDY A 35 3 ADS ADSTB 1 0 BNR BPRI D 63 0 DBI 3 0 DBSY DEFER DRDY DSTBN 3 0 DSTBP 3 0 HIT HITM LOCK A20M BCLK 1 0 BSEL 2 0 COMP 8 3 0 IGNNE INIT ITP CLK 1 0 LINTO INTR LINT1 NMI MSID 1 0 PWRGOOD RESET SMI STPCLK TESTHI 13 0 VID 6 1 GTLREF 1 0 TCK TDI TMS TRST VTT_SEL Open Drain Signals TDO FCx THERMTRIP FERR PBE ERR BPM 5 0 BRO Notes 1 Signals that do not have Ry nor are actively driven to their high voltage level Table 2 10 Signal Reference Voltages GTLREF Vui 2 BPM 5 0 RESET BNR HIT HITM BRO A 35 0 ADS ADSTB 1 0 BPRI D 63 0 DBI 3 0 DBSY DEFER DRDY DSTBN 3 0 DSTBP 3 0 LOCK REQ 4 0 RS 2 0 TRDY A20M LINTO INTR LINTI NMI IGNNE INIT PROCHOT PWRGOOD SMI STPCLK TCK1 TDI1 TMS TRST 1 Notes 1 These signals also have hysteresis added to the reference voltage See Table 2 12 for more information 26 Dual Core Intel Xeon Processor 3000 Series Datasheet Electrical Specifications 2 7 2 2 7 3 Table 2 11 Table 2 12 intel CMOS and Open Drain Signals Legacy inp
133. r AF24 VSS Power Other AE15 VCC Power Other AF25 VSS Power Other 64 Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions intel Table 4 2 Numerical Land Assignment Table 4 2 Numerical Land Assignment Sheet 15 of 20 Sheet 16 of 20 Hand Land Name Signal Buffer Direction rang Land Name Signal Buffer Direction Type Type AF26 VSS Power Other AH6 VSS Power Other AF27 VSS Power Other AH7 VSS Power Other AF28 VSS Power Other AH8 VCC Power Other AF29 VSS Power Other AH9 VCC Power Other AF30 VSS Power Other AH10 VSS Power Other AG1 TRST TAP Input AH11 VCC Power Other AG2 BPM3 Common Clock Input Output AH12 VCC Power Other AG3 BPM5 Common Clock Input Output AH13 VSS Power Other AG4 A30 Source Synch Input Output AH14 VCC Power Other AG5 A31 Source Synch Input Output AH15 VCC Power Other AG6 A29 Source Synch Input Output AH16 VSS Power Other AG7 VSS Power Other AH17 VSS Power Other AG8 VCC Power Other AH18 VCC Power Other AG9 VCC Power Other AH19 VCC Power Other AG10 VSS Power Other AH20 VSS Power Other AG11 VCC Power Other AH21 VCC Power Other AG12 VCC Power Other AH22 VCC Power Other AG13 VSS Power Other AH23 VSS Power Other AG14 VCC Power Other AH24 VSS Power Other AG15 VCC Power Other AH25 VCC Power Other AG16 VSS Power Other AH26
134. r Other AM24 VSS Power Other AN21 VCC Power Other AM25 vcc Power Other AN22 VCC Power Other AM26 VCC Power Other AN23 vss Power Other AM27 VSS Power Other AN24 VSS Power Other AM28 vss Power Other AN25 VCC Power Other AM29 VCC Power Other AN26 VCC Power Other AM30 vcc Power Other AN27 VSS Power Other AN1 vss Power Other AN28 VSS Power Other AN2 VSS Power Other AN29 VCC Power Other AN3 VCC_SENSE Power Other Output AN30 VCC Power Other Dual Core Intel Xeon Processor 3000 Series Datasheet 67 m n tel Land Listing and Signal Descriptions 4 2 Alphabetical Signals Reference Table 4 3 Signal Description Sheet 1 of 7 Name Type Description A 35 3 Input Output A 35 3 Address define a 236 byte physical memory address space In sub phase 1 of the address phase these signals transmit the address of a transaction In sub phase 2 these signals transmit transaction type information These signals must connect the appropriate pins lands of all agents on the processor FSB A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processor samples a subset of the A 35 3 signals to determine power on configuration See Section 6 1 for more details A20M Input If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a
135. r cannot issue any new transactions BPM 5 0 Input Output BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins lands of all processor FSB agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processor These signals do not have on die termination BPRI Input BPRI Bus Priority Request is used to arbitrate for ownership of the processor FSB It must connect the appropriate pins lands of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by de asserting BPRI 68 Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions Table 4 3 Signal Description Sheet 2 intel of 7 Name Type Description BRO Input Output BRO drives the BREQO signal in the syste
136. r must meet the specifications in Table 2 7 when measured across the VCC_SENSE and VSS_ SENSE lands Overshoot events that are lt 10 ns in duration may be ignored These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit Dual Core Intel Xeon Processor 3000 Series Datasheet m Electrical Specifications n tel 2 7 2 7 1 Table 2 8 Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic GTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates Platforms implement a termination voltage level for GTL signals defined as Vr Because platforms implement separate power planes for each processor and chipset separate Vcc and Vr supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families The GTL inputs require a reference voltage GTLREF which is used by the receivers to determine if a signal is a logical O or a logical 1 GTLREF must be generated on the motherboard see Table 2 15 for GTLREF specifications Termination resistors Rrr for GTL signals are provided
137. ration i rw core Frequency Crete fo UE BCLK 1066 MHz FSB dm ve MHz 1 6 1 60 GHz 2 00 GHz 1 7 1 87 GHz 2 33 GHz 1 8 2 13 GHz 2 66 GHz 1 9 2 40 GHz 3 00 GHz 1 10 2 66 GHz na 1 11 2 93 GHz na Notes 1 Individual processors operate only at or below the rated frequency 2 Listed frequencies are not necessarily committed production frequencies 2 7 6 FSB Frequency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 Table 2 17 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency The Dual Core Intel Xeon processor 3000 series operates at a 1066 MHz FSB frequency selected by a 266 MHz BCLK 1 0 frequency Table 2 17 BSEL 2 0 Frequency Table for BCLK 1 0 BSEL2 BSEL1 BSELO FSB Frequency L L L 266 MHz L L H RESERVED L H H RESERVED L H L RESERVED H H L RESERVED H H H RESERVED H L H RESERVED H L L 333 MHz 2 7 7 Phase Lock Loop PLL and Filter An on die PLL filter solution will be implemented on the processor The VCCPLL input is used for the PLL Refer to Table 2 4 for DC specifications 30 Dual Core Intel Xeon Processor 3000 Series Datasheet Electrical Specifications
138. read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 signals All bus agents observe the ADS activation to begin protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 Input Output Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO A 35 17 ADSTB1 BCLK 1 0 Input The differential pair BCLK Bus Clock determines the FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss BNR Input Output BNR Block Next Request is used to assert a bus stall by any bus agent unable to accept new bus transactions During a bus stall the current bus owne
139. ries Datasheet Land Listing and Signal Descriptions intel Table 4 2 Numerical Land Assignment Table 4 2 Numerical Land Assignment Sheet 7 of 20 Sheet 8 of 20 band Land Name Signal Buffer Direction rang Land Name Signal Buffer Direction Type Type J6 REQ4 Source Synch Input Output K30 VCC Power Other J7 VSS Power Other L1 LINT1 Asynch CMOS Input J8 VCC Power Other L2 TESTHI 13 Power Other Input J9 VCC Power Other L3 VSS Power Other J10 VCC Power Other L4 A06 Source Synch Input Output J11 VCC Power Other L5 A03 Source Synch Input Output J12 VCC Power Other L6 vss Power Other J13 VCC Power Other L7 VSS Power Other J14 VCC Power Other L8 VCC Power Other J15 VCC Power Other L23 VSS Power Other J16 FC31 Power Other L24 vss Power Other J17 FC34 Power Other L25 VSS Power Other J18 VCC Power Other L26 VSS Power Other J19 VCC Power Other L27 VSS Power Other J20 VCC Power Other L28 VSS Power Other J21 VCC Power Other L29 VSS Power Other J22 VCC Power Other L30 VSS Power Other J23 VCC Power Other M1 VSS Power Other J24 VCC Power Other M2 THERMTRI P Asynch CMOS Output j25 VCC Power Other M3 STPCLK Asynch CMOS Input J26 VCC Power Other M4 AO7 Source Synch Input Output J27 VCC Power Other M5 A05 Source Synch Input Output J28 VCC Power Other M6 REQ2 Source Synch Input Output J29 VCC Power
140. rmal state While in Stop Grant state the processor will process a FSB snoop Extended Stop Grant State Extended Stop Grant is a low power state entered when the STPCLK signal is asserted and Extended Stop Grant has been enabled via the BIOS The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state When entering the low power state the processor will first switch to the lower bus ratio and then transition to the lower VID The processor exits the Extended Stop Grant state when a break event occurs When the processor exits the Extended Stop Grant state it will resume operation at the lower frequency transition the VID to the original value and then change the bus ratio back to the original value Extended HALT Snoop State HALT Snoop State Extended Stop Grant Snoop State and Stop Grant Snoop State The Extended HALT Snoop State is used in conjunction with the new Extended HALT state If Extended HALT state is not enabled in the BIOS the default Snoop State entered will be the HALT Snoop State Refer to the sections below for details on HALT Snoop State Stop Grant Snoop State and Extended HALT Snoop State and Extended Stop Grant Snoop State HALT Snoop State Stop Grant Snoop State The processor will respond to snoop transactions on the FSB while in Stop Grant state or in HALT Power Down state During a snoop transaction the processor enters the
141. rs with 4 MB L2 Cache cence 21 2 6 Vcc Static and Transient Tolerance for Processors with 2 MB L2 Cache l Ejj 22 2 7 Vee Overshoot Specifications eese mener nemen nennen nnn 24 2 8 FSB Signal Groups ERR ards sada h n b r RON M S dn E B kew ba d Tn d n da Sad a B a 25 2 9 Signal Characteristics i cisn akan n karane haa duan Aa ni RA han t RM darina a UNUS A ha kana ERE r kn 26 2 10 Signal Reference Voltages sse nennen e eee k eese 26 2 11 GTL Signal Group DC Specifications 2 0 0 emen meme nnn 27 2 12 Open Drain and TAP Output Signal Group DC Specifications ccecce 27 2 13 CMOS Signal Group DC Specifications cece kk kk kk kak kk kake 28 2 14 PECI DC Electrical Limits rere o nl vie Fe ni Zan fre cen Hu daa yar as al da Kare re ied br Wana kra 28 2 15 GTL Bus Voltage Definitions memes messe meme kak k ka kya 29 2 16 Core Frequency to FSB Multiplier Configuration cece cece eee e 30 2 17 BSEL 2 0 Frequency Table for BCLK 1 0 sse 30 2 18 Front Side Bus Differential BCLK Specifications sssssssssseeee me 31 2 19 Front Side Bus Differential BCLK Specifications cece eee eee ee ee mne 32 20 PECI DC Electrical Limits iter rent Rack Rabe n n Ah a eR Rand wa d ya kaw Daka Dn eaters een 33 3 1 Processor Loading Specificat OnS k Kk hk k k k rp kk kk kk nemen
142. should not be used as a generic keep out zone for all cooling solutions It is the system designers responsibility to consider their proprietary cooling solution when designing to the required keep out zone on their system platforms and chassis Refer to the Dual Core Intel Xeon Processor 3000 Series Thermal and Mechanical Design Guidelines for further guidance Mechanical Representation of the Boxed Processor Note The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Dual Core Intel Xeon Processor 3000 Series Datasheet 95 m n tel Boxed Processor Specifications 7 1 ZILGI Figure 7 2 Figure 7 3 96 Mechanical Specifications Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor The boxed processor will be shipped with an unattached fan heatsink Figure 7 1 shows a mechanical representation of the boxed processor Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 7 2 Side View and Figure 7 3 Top View The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs Airspace requirements are shown in Figure 7 7 and Figure 7 8 Note that some figures have centerlin
143. sssesee kk 86 8 Conceptual Fan Control on Thermal Diode Based Platforms ccccccceeeeeeee eee eeeeeeeeeenens 87 6 1 Processor Low Power State MaChine cccccecee tee eee ee eene 90 7 1 Mechanical Representation of the Boxed Processor esssssssssssseen nemen 95 7 2 Space Requirements for the Boxed Processor Side View hkhWkkkk kk kk kk kk kk kk 96 7 3 Space Requirements for the Boxed Processor Top View khk kkkk kk mmn 96 7 4 Space Requirements for the Boxed Processor Overall View h h h l k 97 7 5 Boxed Processor Fan Heatsink Power Cable Connector Description sseeesssssss 98 7 6 Baseboard Power Header Placement Relative to Processor Socket ssessssss 99 7 7 Boxed Processor Fan Heatsink Airspace Keepout Requirements Side 1 View 100 7 8 Boxed Processor Fan Heatsink Airspace Keepout Requirements Side 2 View 100 7 9 Boxed Processor Fan Heatsink Set POINtS cccceccceee eee kk eee e kk kk eat eeeae ent eateeeaeentaas 101 Dual Core Intel Xeon Processor 3000 Series Datasheet 5 Tables 2 1 Voltage Identification Definition ssssssssssssssese m memes nennen enne nnn 17 2 2 Market Segment Selection Truth Table for MSID 1 0 3 2 3 4LL EEE 18 2 3 Absolute Maximum and Minimum Ratings sss nemen enn 20 2 4 Voltage and Current Specifications cnet enne 20 2 5 Vcc Static and Transient Tolerance for Processo
144. stance 2 79 4 52 6 24 Q 2 3 5 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Preliminary data Will be characterized across a temperature range of 50 80 C 3 Not 100 tested Specified by design characterization 4 The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation lew lg e aVb nkT 1 where Is saturation current q electronic charge Vp voltage across the diode k Boltzmann Constant and T absolute temperature Kelvin 5 The series resistance Rz is provided to allow for a more accurate measurement of the junction temperature Ry as defined includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor Ry can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation Terror Rr N71 Igwmin nK q In N where Terror sensor temperature error N sensor current ratio k Boltzmann Constant q electronic charge Dual Core Intel Xeon Processor 3000 Series Datasheet Thermal Specifications and Design Considerations n tel Table 5 6
145. the Viz specifications outlined in Table 2 4 2 2 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate Larger bulk storage Cgy x such as electrolytic or aluminum polymer capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 2 4 Failure to do so can result in timing violations or reduced lifetime of the component 2 2 1 Vcc Decoupling Vcc regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications This includes bulk capacitance with low effective series resistance ESR to keep the voltage rail within specifications during large swings in load current In addition ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity Consult the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket 2 2 2 V Decoupling Decoupling must be
146. the logic analyzers to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides Dual Core Intel Xeon Processor 3000 Series Datasheet 103 e n tel Debug Tools Specifications 104 Dual Core Intel Xeon Processor 3000 Series Datasheet
147. thermal solutions may consist of system fans combined with ducting and venting For more information on designing a component level thermal solution refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 Note The boxed processor will ship with a component thermal solution Refer to Chapter 7 for details on the boxed processor 5 1 1 Thermal Specifications To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature Tc specifications when operating at or below the Thermal Design Power TDP value listed per frequency in Table 5 1 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Platform Environment Control Interface PECI bus as described in Section 5 4 1 1 The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal con
148. trol circuit TCC activation as indicated by PROCHOT see Section 5 2 Systems that implement fan speed control must be designed to take these conditions in to account Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications To determine a processor s case temperature specification based on the thermal profile it is necessary to accurately measure processor power dissipation Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 and the Processor Power Characterization Methodology for the details of this methodology Dual Core Intel Xeon Processor 3000 Series Datasheet 75 Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 5 1 instead of the maximum processor power consumption The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time For more details on the usage of this feature
149. tware in the event of a critical or continuous fault condition PECI GetTempO Error Code Support The error codes supported for the processor GetTemp command are listed in Table 8 GetTempO Error Codes Error Code Description 8000h General sensor error Sensor is operational but has detected a temperature below its operational GEL range underflow Dual Core Intel Xeon Processor 3000 Series Datasheet Features 6 6 1 Table 6 1 6 2 Features Power On Configuration Options Several configuration options can be configured by hardware The processor samples the hardware configuration at reset on the active to inactive transition of RESET For specifications on these options refer to Table 6 1 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset purposes the processor does not distinguish between a warm reset and a power on reset Power On Configuration Option Signals Configuration Option Signal1 2 3 Output tristate SMI Execute BIST A3 Disable dynamic bus parking A25 Symmetric agent arbitration ID BRO RESERVED A 8 5 A 24 11 A 35 26 Notes 1 Asserting this signal during RESET will select the corresponding option 2 Address signals not identified in this table as configuration options should
150. umption in conjunction with OS support Intel Virtualization Technology Intel VT Intel Virtualization Technology provides silicon based functionality that works together with compatible Virtual Machine Monitor VMM software to improve upon software only solutions Because this virtualization hardware provides a new architecture upon which the operating system can run directly it removes the need for binary translation Thus it helps eliminate associated performance overhead and vastly simplifies the design of the VMM in turn allowing VMMs to be written to common standards and to be more robust See the Intel Virtualization Technology Specification for the A 32 Intel Architecture for more details Intel Trusted Execution Technology Intel TXT A key element in Intel s safer computing initiative which defines a set of hardware enhancements that interoperate with an Intel TXT enabled OS to help protect against software based attacks Intel TXT creates a hardware foundation that builds on Intel s Virtualization Technology VT to help protect the confidentiality and integrity of data stored created on the client PC References Material and concepts available in the following documents may be beneficial when reading this document Document Location Intel amp 3000 and 3010 Chipset Platform Design Guide Intel amp 3000 and 3010 Chipset Platform Design Guide Supplement Conroe and Woodcrest Processor Fam
151. ut signals such as A20M IGNNE INIT SMI and STPCLK use CMOS input buffers All of the CMOS and Open Drain signals are required to be asserted de asserted for at least four BCLKs in order for the processor to recognize the proper signal state See Section 2 7 3 for the DC See Section 6 2 for additional timing requirements for entering and leaving the low power states Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless otherwise stated All specifications apply to all frequencies and cache sizes unless otherwise stated GTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes ViL Input Low Voltage 0 10 GTLREF 0 10 V 2 3 Viu Input High Voltage GTLREF 0 10 Vr 0 10 V 45 3 Von Output High Voltage Vr 0 10 Vr V 5 3 lot Output Low Current N A Vrr max Rrr in 2 Row A min lu Input Leakage Current N A 100 HA 6 lio Output Leakage Current N A 100 HA 7 RoN Buffer On Resistance 10 13 Q Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Mi is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3 The Vr referred to in these specifications is the instantaneous V 4 Viu is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 5 Vip and Voy may
152. vel power consumption Systems must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the A32_ CLOCK MODULATION MSR is set to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same A32_CLOCK_MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On Demand mode may be used in conjunction with the Thermal Monitor Dual Core Intel Xeon Processor 3000 Series Datasheet m e Thermal Specifications and Design Considerations n tel 5 2 4 5 2 5 5 3 however if the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor core temperature has reached its maximum operating temperature If the Thermal Monitor is enabled note that the Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT As an
153. within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 6 1 This signal does not have on die termination and must be terminated on the system board RESERVED All RESERVED lands must remain unconnected Connection of these lands to Vcc Vss Vr or to any other signal including each other can result in component malfunction or incompatibility with future processors RS 2 0 Input RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins lands of all processor FSB agents SKTOCC Output SKTOCC Socket Occupied will be pulled to ground by the processor System board designers may use this signal to determine if the processor is present SMI Input SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the de assertion of RESET the processor will tri state its outputs STPCLK Input STPCLK Stop Clock w
154. ynch Input Output D15 D11 Source Synch Input Output D16 G9 Source Synch Input Output D17 F8 Source Synch Input Output D18 F9 Source Synch Input Output D19 E9 Source Synch Input Output D20 D7 Source Synch Input Output D21 E10 Source Synch Input Output D22 D10 Source Synch Input Output D23 F11 Source Synch Input Output Dual Core Intel Xeon Processor 3000 Series Datasheet Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Assignments Sheet 3 of 20 Table 4 1 Alphabetical Land Assignments Sheet 4 of 20 intel Land Name Land e M Direction Land Name Land cd Direction D24 F12 Source Synch Input Output DBIO A8 Source Synch Input Output D25 D13 Source Synch Input Output DBI1 G11 Source Synch Input Output D26 E13 Source Synch Input Output DBI2 D19 Source Synch Input Output D27 G13 Source Synch Input Output DBI3 C20 Source Synch Input Output D28 F14 Source Synch Input Output DBR AC2 Power Other Output D29 G14 Source Synch Input Output DBSY B2 Common Clock Input Output D30 F15 Source Synch Input Output DEFER G7 Common Clock Input D31 G15 Source Synch Input Output DRDY CI Common Clock Input Output D32 G16 Source Synch Input Output DSTBNO C8 Source Synch Input Output D33 E15 Source Synch Input Output DSTBN1 G12 Source Synch Input Output D34 E

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