ADATA Extreme Edition DDR2 800G 2GB-kit
Contents
1. Pe Wa TEAC RRMA NTT 1 63 002 480 4 00 lt 0 1 97 Note A a 1 00 8 039 L8 Deb tl Oo C 50t0 20 0 098 0 008 0 80 905 0 01 002 Salo Detail A HYQVEI1A08 DDR2 800G CL 5 1GB 128Mx8 Pb free EEE EERE gt C 1 64 165 120 121 184 185 240 gt C gt 4 55 00 2 165 3 3 00 0 118 gt Detail B Rev 0 0 50 0 020 min 4 00 CQ 15 7 min l e t0 10 CHOD 000489 10 00C0 394 17 8000 70 1 Tolerance 0 127mm 0 005 Inches 4 000 157 2 0000 098 0 2 0MM Ma x 0 05MMC Mind 1 50 40 10 0 059 0 004 0 20MMCM ax 0 05MMC Min X VIEW C L CUptionald 2009 02 12 Page 7 of 72. DQ3 DQ4 DOS DO6 DQ7 DOSI ___ DOSI DMI DO DOSS DOSS DMS DM CS DQS DOS DQ8 roo DO9 WH T D1 DQ10 DQ11 DQ12 DQ13 DQ14 N DQ15 DQS6 DQS6 DM6 DQS2 DQS2 DM2 _ DQ16 W DQ17 D2 DQ18 DQ19 DQ20 DQ 1 DQ22 DQ23 DQS7 DQS7 DM7 DM CS DQS DQS roo Vol D3 VO2 I O 3 I O 4 I O 5 I O 6 1 O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DO61 DQ62 DQ63 DQ24 M DQ25 DQ26 DQ27 DQ28 M DQ29 M DQ30 DQ31 Serial PD lt gt SDA BAO BA2 BA0 BA2 SDRAMs DO D7 AO A15 A0 A15 SDRAMs DO D7 RAS SDRAMs DO D7 SPD VDD VDDQ DO D8 a DO D8 RAS W__ gt CAS W D CAS SDRAMs DO D7 CKEO CKE SDRAMSs DO D7 WE SDRAMs DO D7 ODT SDRAMs D0 D7 WE ODTO HYQVEIA08 DDR2 800G CL 5 1GB 128Mx8 Pb free Rev 0 2009 02 12 DATA vicios ser DM CS DQS DQS L O 0 VO 1 D4 DM CS DQS DQS Loo VO 1 D5 LO 2 L O 3 roO 4 ros5 LO 6 DM CS DQS DQS Loo lol r02 LO 3 TO 4 ros5 rO 6 D6 DM CS DQS DQS 100 D7 Clock Wiring Clock Input DDR2 SDRAMs CKO CKO 2 DDR2 SDRAMs CK1 CK1 3 DDR2 SDRAMs CK2 CK2 3 DDR2 SDRAMs Wire per Clock Loading Table WViring Diagrams Notes 1 DQx DMx DOSx DQSx resistors 22 Q 5 2 BAx Ax RAS CAS AVE resistors 10 Q 5 Page 5 of 7 PONTA oa Absolute Maximum Ratings Voltage on VDD supply relative to Vss VDD 1 0 2 3 V Voltage on VDD
3. 6 vss tre an 216 vss ir vss s an e vss r ek mr a 217 pos te n ss mw pas 138 ext 178 voo 218 pass to nc se vo se pass 9 vss as 219 vss 20 vss so a 10 ves mof pon 180 as 20 c 21 caw ot a ror sa tay pos 181 vooa 221 se DQ11 VDDQ 102 NC TEST 142 182 222 Ca ves 18 wo vs 16 om m nm me ce 24 pate sa voo 194 mase t4 par 184 voo 2a ne 25 par 6 vss 105 pas 14s vss 185 cko 225 vss vss so vss 106 vss 146 pm 186 ico 226 pasa 27 masz 67 vo tor paso tar No 187 voo 227 pass 28 ase os noo 108 past 148 vss 188 ao 228 vss vss ee vo 109 vss__ 149 voz 189 voo 22 paso 30 pate 70 atop io Dass 150 pas 190 Bai 230 past st co hr sao im pas ist vss 191 vooa 231 vss 32 vss f vwa n vss 182 pas 192 mas 232 om 33 ooze 73 me 113 masz 153 paz 193 so 238 ne 34 pas za icas ta past 154 vss 194 voa 234 vss s vss 75 voa 115 vss__ 155 pm 195 opto 235 pas mass 76 s 6 pass ts Nc 196 as 236 Das s7 pass 77 oom 17 pass ist vss 197 voo 237 vss 38 vss 78 vooa 118 vss 188 paso 198 vss 238 voosro poz 70 vss 119 soa__ 159 Dast 19
4. 9 pose 239 smo 40 caer so paz wo sco to vss 20 paz 20 sat HYQVE1A08 DDR2 800G CL 5 1GB 128Mx8 Pb free Rev 0 2009 02 12 Page 3 of 7 PONTA ooi Pin Description CKO CK2 FUNCTION System Clock Active on the positive and negative edge to sample all inputs ICK0 CK2 Clock Enable ISO Chip Select Banks Select DQ0 DQ63 Data Data and check bit inputs outputs are multiplexed on the same pins Masks system clock to freeze operation from the next clock cycle CKE should be enabled at least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and L U DQM Row Column address are multiplexed on the same pins Row Address AO A13 Column Address A0 A9 Auto precharge A10 AP Selects bank to be activated during row address latch time Selects bank for read write during column address latch time DQS0 DQS Data Strobe Bi directional Data Strobe DQS0 DQS7 When high termination resistance is enabled for all DQ DQ and DM pins assuming the ODTO On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left No Connection on the device HYQVEIA08 DDR2 800G CL 5 1GB 128Mx8 Pb free Rev 0 2009 02 12 Page 4 of 7 Block Diagram DOSO DI DOSO 4 DMO DQS4 DQS4 DNA DM CS DQS DQS DQ0 DQI DQ
5. Chip Driver OCD Impedance Adjustment On Die Termination ODT Lead free products are RoHS compliant e EEPROM VDDSPD 3 3V Typical e PCB Height 30 00mm 1 181 Single sided component e Clock Cycle Time tCK DDR2 800 tCK 2 5ns Refresh to Active Refresh Command Time tRFC 127 5ns HYQVEIA08 DDR2 800G CL 5 1GB 128Mx8 Pb free Rev 0 2009 02 12 Page 2 of 7 PONTA Pin assignment Front Front Front Back Back Back Gila el ee lial mT e 2 vss 42 no cpo s2 vss 122 pas 162 nc ces 202 oma cao 4 ncc 83 masa 1s pas 163 vss 203 nec a por a vss 84 pasa ta vss 164 nc oms 204 ves s vss 4 no mass ss vss 125 ovo 165 nc 205 pass 6 maso 46 nc pass se pass 126 Nc 166 vss 206 Das z paso 7 vss 87 pas v7 vss__ 167 no ces 207 vss e vss 46 Nocez2 s vss 18 pas 168 nc cer 208 pos e paz 4 noces s paso 19 par 169 vss 209 pas to oa 50 vs pas 10 vss 170 vooa 210 vss n vss s va o vss ist pare n cker 21 oms 12 pas se creo se mass 132 pas 172 woo a ne s a ss vo o pass 13 vss 18 oms 213 vss ta vss sa Baz 04 vss 14 om 174 an ata pae ts most ss nc 9 pae 15 ne urs voa 215 par 16 past se vooa se pass 13
6. Q supply relative to Vss 0 5 2 3 a ae Voltage on VDDL supply relative to Vss 0 5 2 3 pv Voltage on any pin relative to Vss 0 5 2 3 pv Note DDR2 SDRAM component specification Operation Temperature Condition Soi vow unt a Note 1 If the DRAM case temperature is above 85 C the Auto Refresh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 8V 0 1V Tc 0 to 85 C Parameter Symbol Min Max Unit Note Supply Voltage VDD 1 7 V Input Reference Voltage 0 49 x VDDQ 0 51 x VDDQ pov 1 2 Termination Voltage VTT VREF 0 04 VREF 0 04 v 3 Note 1 There is no specific device VDD supply voltage requirement for SSTL_1 8 compliance However under all conditions VDDQ must be less than or equal to VDD 2 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 3 Peak to peak ac noise on VREF may not exceed 2 VREF ac 4 VTT of transmitting device must track VREF of receiving device 5 VDDQ tracks with VDD VDDL tracks with VDD AC parameters are measured with VDD VDDQ and VDDL tied together HYQVEIA08 DDR2 800G CL 5 1GB 128Mx8 Pb free Rev 0 2009 02 12 Page 6 of 7 Package Dimensions e r DA A A Wondertul Memory i eG Fw fm
7. ra r DA A A Wonderful Memory DATA Memory Module Data Sheet A Wonderful Memory HYQVE1A08 DDR2 800G CL5 240 Pin O C U DIMM 1GB 128M x 64 bits General Description The ADATA s HYQVE1A08 is a 128Mx64 bits 1GB DDR2 800 CL5 SDRAM over clocking memory module The SPD is programmed to JEDEC standard latency 800Mbps timing of 5 5 5 18 at 1 8V The module is composed of eight 128Mx8 bits CMOS DDR2 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TSSOP TSOP package on a 240pin glass epoxy printed circuit board The HYQVE1A08 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features Power supply Normal VDD amp VDDQ 1 8V 0 1V e 1 8V SSTL_18 compatible I O e Timing Reference DDR2 800 CL5 5 5 18 at 1 8V DDR2 800 CL5 5 5 12 at 2 0V Burst Length 4 8 Programmable Additive Latency 0 1 2 3 4 Bi directional differential data strobe DQS and DQS e Differential clock input CK CK operation e DLL aligns DQ and DOS transition with CK transition e Double data rate architecture Auto amp Self refresh e Average Refresh period 7 8us Off
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