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Intel Celeron E1400

1. r rr nn 16 2 5 Reserved Unused and TESTHI Signals sss mms 16 2 6 Voltage and Current Specification rr nemen memes 17 2 6 1 Absolute Maximum and Minimum Ratings Hee 17 2 6 2 DC Voltage and Current Specification sss 19 2 6 3 VcC Oversho0t meun e ie rad a E HE YER uha WA Weka Gur W ran eee WA n 21 2 6 4 Die Voltage Validation i cies la sael nalin na n anka ia eene r dan REM AX NR EMEN daln n dan 22 2 7 Signaling Specifications metere XR RR RR RR ERE RE aasawa Re Ra RR Re d 22 2 4 L TSB Signal GFoUpS ucu ees eere eti xe ER uS Ex dor n n kn wanin UE E Ere ERREUR 23 2 7 2 CMOS and Open Drain Signals r rr 24 2 7 3 Processor DC Specifications ee nena nemen 25 2 7 3 1 GTL Front Side Bus Specifications r 26 2 8 Clock Specifications e u nnn a nynn n Kin mamayi n a aqa nue naw qua awakusqa da buna 28 2 8 1 Front Side Bus Clock BCLK 1 0 and Processor Clocking 28 2 8 2 FSB Frequency Select Signals BSEL 2 0 28 2 8 3 Phase Lock Loop PLL and Filter sese 29 2 8 4 BCLK 1 0 Specifications CK505 based Platforms 29 2 8 5 BCLK I1 0 Specifications CK410 based Platforms
2. Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name n ux Direction Land Name 272 s Direction TRDY E3 Common Clock Input VCC AF22 Power Other TRST AG1 TAP Input VCC AF8 Power Other VCC AA8 Power Other VCC AF9 Power Other VCC AB8 Power Other VCC AG11 Power Other VCC AC23 Power Other VCC AG12 Power Other VCC AC24 Power Other VCC AG14 Power Other VCC AC25 Power Other VCC AG15 Power Other VCC AC26 Power Other VCC AG18 Power Other VCC AC27 Power Other VCC AG19 Power Other VCC AC28 Power Other VCC AG21 Power Other VCC AC29 Power Other VCC AG22 Power Other VCC AC30 Power Other VCC AG25 Power Other VCC AC8 Power Other VCC AG26 Power Other VCC AD23 Power Other VCC AG27 Power Other VCC AD24 Power Other VCC AG28 Power Other VCC AD25 Power Other VCC AG29 Power Other VCC AD26 Power Other VCC AG30 Power Other VCC AD27 Power Other VCC AG8 Power Other VCC AD28 Power Other VCC AG9 Power Other VCC AD29 Power Other VCC AH11 Power Other VCC AD30 Power Other VCC AH12 Power Other VCC AD8 Power Other VCC AH14 Power Other VCC AE11 Power Other VCC AH15 Power Other VCC AE12 Power Other VCC AH18 Power Other VCC AE14 Power Other VCC AH19 Power Other VCC AE15 Power Other VCC AH21 Power Other VCC AE18 Power Other VCC AH22 Power Other VCC AE19 Power Other VCC AH25 Power Other VCC AE21 Power Other VCC
3. 92 24 Space Requirements for the Boxed Processor Top View sss mm 93 25 Space Requirements for the Boxed Processor Overall View ssss n 93 26 Boxed Processor Fan Heatsink Power Cable Connector Description 95 27 Baseboard Power Header Placement Relative to Processor Socket sssssssssss 96 28 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 1 view 97 29 Boxed Processor Fan Heatsink Airspace Keepout Requirements Side 2 View 97 30 Boxed Processor Fan Heatsink Set Points eee nemen memes 98 Datasheet 5 Tables MEM chasse ULIS 11 2 Voltage Identification Definition 0 0 mm meHmemememe sese emen nne nnn 15 3 Market Segment Selection Truth Table for MSID 1 0 ssssmm 16 4 Absolute Maximum and Minimum Ratings isssssssssssemmemememememe kak kk kake 18 5 Voltage and Current Specifications ssssssssssssssssesesnse memes enne 19 6 Vcc Static and Transient Tolerance for ProCessors een 20 7 Nec Overshoot Specifications ence nn 2n 600k kiyan bn kk sahiy a akak na a dn gambe per Ra EEIN dne daa 21 8 FSB Signal Groups a aa aihn Dente W n dayineke nan n l n bane ca seni ba d cies le pure kak 23 9 Signal Characteristics users er rte tpa nekrine Yeki nan E E ur n en s ne bar dud E l n ry ae unes 24 10 Signal Referen
4. ss Datasheet Features l n te j 6 Features 6 1 Power On Configuration Options Several configuration options can be configured by hardware The processor samples the hardware configuration at reset on the active to inactive transition of RESET For specifications on these options refer to Table 32 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset purposes the processor does not distinguish between a warm reset and a power on reset Table 32 Power On Configuration Option Signals Configuration Option Signal 23 Output tristate SMI Execute BIST A3 Disable dynamic bus parking A25 Symmetric agent arbitration ID BRO RESERVED A 8 5 A 24 11 A 35 26 NOTES 1 Asserting this signal during RESET will select the corresponding option 2 Address signals not identified in this table as configuration options should not be asserted during RESET 3 Disabling of any of the cores within the processor must be handled by configuring the EXT_CONFIG Model Specific Register MSR This MSR will allow for the disabling of a single core Datasheet 85 intel aem 6 2 Clock Control and Low Power States The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections
5. BSEL2 BSEL1 BSELO FSB Frequency L L L RESERVED L L H RESERVED L H H RESERVED L H L 200 MHz H H L RESERVED H H H RESERVED H L H RESERVED H L L RESERVED 2 8 3 Phase Lock Loop PLL and Filter An on die PLL filter solution will be implemented on the processor The VCCPLL input is used for the PLL Refer to Table 5 for DC specifications 2 8 4 BCLK 1 0 Specifications CK505 based Platforms Table 17 Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes VL Input Low Voltage 0 30 N A N A V 3 2 Vu Input High Voltage WA NA 1 15 V 3 2 Veross abs Absolute Crossing Point 0 300 N A 0 550 V 3 4 345 AVcnoss Range of Crossing Points N A N A 0 140 V 3 4 Vos Overshoot N A N A 1 4 V 6 Vus Undersoot 0300 NA NA V 3 VswiNG Differential Output Swing 0 300 N A N A V lu Input Leakage Current 5 N A 5 HA Cpad Pad Capacitance 95 1 2 1 45 pF 8 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Steady state voltage not including overshoot or undershoot 3 Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLKO equals the falling edge of BCLK1 4 VHavg is the statistical average of the Vy measured by the oscilloscope The crossing point must meet the absolute and relative c
6. 31 2 9 PEGI DC SpeciflCatloris ei eb ha V d na Gi wad HM REM NR SED DARA Ser UA MIU ERE ERAN EDNDPTLMUNE 32 3 Package Mechanical Specifications sss 33 3 1 Package Mechanical Drawing ssssssssseem memes mememe sene 33 3 2 Processor Component Keep Out Zones emnes mener 37 3 3 Package Loading Specifications kk kk kk kk kak a 37 3 4 Package Handling Guidelines kek kkk eee eee meme memes 37 3 5 Package Insertion Specifications ene kk kk ak a 38 3 6 Processor Mass Specification i ya kass kk aran lk wa akan kaka wasu rana kumandan ke nk bna aia xalk dina n n ns 38 3 7 Processor Materials u EOD ERO G bad san D n hn RI DO W a d dr da 38 3 8 Processor Mal Kil St xun ekra nizan kan ora nA n n WAA A kan az hd Dek C ER harin A An nA ye RR ya Va nk AU ER 38 3 9 Processor Land Coordinates recederet kn Vente ce daa ceded ela n ead Ventile ced 39 4 Land Listing and Signal Descriptions sssssssssssssseme m 41 4 1 Processor Land Assignments mnes mememe ses ees nnns 41 4 2 Alphabetical Signals Reference eee eee eee emen memes 64 5 Thermal Specifications and Design Considerations ee eee eee eens 73 5 1 Processor Thermal Specifications eee e
7. 56 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction Lana Land Name Signal Buffer Direction Type Type F11 D23 Source Synch Input Output G21 D44 Source Synch Input Output F12 D24 Source Synch Input Output G22 D47 Source Synch Input Output F13 VSS Power Other G23 RESET Common Clock Input F14 D28 Source Synch I nput Output G24 TESTHI6 Power Other Input F15 D30 Source Synch Input Output G25 TESTHI3 Power Other Input F16 VSS Power Other G26 TESTHI5 Power Other Input F17 D37 Source Synch Input Output G27 TESTHI4 Power Other Input F18 D38 Source Synch Input Output G28 BCLK1 Clock Input F19 VSS Power Other G29 BSELO Power Other Output F20 D41 Source Synch Input Output G30 BSEL2 Power Other Output F21 D43 Source Synch Input Output H1 GTLREFO Power Other Input F22 VSS Power Other H2 GTLREF1 Power Other Input F23 RESERVED H3 vss Power Other F24 TESTHI7 Power Other Input H4 FC35 Power Other F25 TESTHI2 Power Other Input H5 TESTHI10 Power Other Input F26 TESTHIO Power Other Input H6 VSS Power Other F27 VIT SEL Power Other Output H7 VSS Power Other F28 BCLKO Clock Input H8 VSS Power Other F29 RESERVED H9 vss Power Other G1 FC27 Power Other H10 VSS Power Other G2 COMP2
8. Dual core processor in the FC LGA6 package with a 512 KB L2 cache Processor For this document the term processor is the generic form of the Intel Celeron Dual Core processor E1000 series The processor is a single package that contains one or more execution units Keep out zone The area on or near the processor that system design can not use Processor core Processor core die with integrated L2 cache LGA775 socket The processors mate with the system board through a surface mount 775 land LGA socket I ntegrated heat spreader I HS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Retention mechanism RM Since the LGA775 socket does not include any mechanical features for heatsink attach a retention mechanism is required Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket FSB Front Side Bus The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Storage conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to
9. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor will first switch to the lower bus ratio and then transition to the lower VID While in Extended HALT state the processor will process bus snoops The processor exits the Extended HALT state when a break event occurs When the processor exits the Extended HALT state it will resume operation at the lower frequency transition the VID to the original value and then change the bus ratio back to the original value Stop Grant and Extended Stop Grant States The processor supports the Stop Grant and Extended Stop Grant states The Extended Stop Grant state is a feature that must be configured and enabled via the BIOS Refer to the following sections for details about the Stop Grant and Extended Stop Grant states 87 intel Dro 6 2 3 1 6 2 3 2 6 2 4 6 2 4 1 88 Stop Grant State When the STPCLK signal is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Since the GTL signals receive power from the FSB these signals should not be driven allowing the level to return to V r for minimum power drawn by the termination resistors in this
10. VCC_SENSE is an isolated low impedance connection to processor core power Vcc It can be used to sense or measure voltage near the silicon with little noise This land is provided as a voltage regulator feedback sense point for Vcc It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket VID 7 0 Output VID 7 0 Voltage ID signals are used to support automatic selection of power supply voltages Vcc Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information The voltage supply for these signals must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID signals becomes valid The VID signals are needed to support the processor voltage specification variations See Table 2 for definitions of these signals The VR must supply the voltage that is requested by the signals or disable itself VID SELECT Output This land is tied high on the processor package and is used by the VR to choose the proper VID table Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for more information 71 intel Table 25 72 Land Listing and Signal Des
11. sssssssssssmmeem kk ka 31 7 Processor Package Assembly Sketch enne seen memes 33 8 Processor Package Drawing Sheet 1 of 3 sssssssssssssseeee k y memes 34 9 Processor Package Drawing Sheet 2 of 3 MKhK K K Klk kk kk kk kk memes emen 35 10 Processor Package Drawing Sheet 3 Of 3 0 0 cece meme enemies 36 11 Processor Top Side Markings Example ssssssssmmemmemememe seems 38 12 Processor Land Coordinates and Quadrants Top View rr 39 13 land out Diagram Top View Left Side mme nnn 42 14 land out Diagram Top View Right Side r memes 43 15 Thermal Profile crier trc REA CORR ERAS TERREA EID RAN ERANT YE dete aya 1 E Yada 4 aa 75 16 Case Temperature TC Measurement Location kk mm nen 76 17 Thermal Monitor 2 Frequency and Voltage Ordering rr 78 I8 Processor PECI TOpoOlogy oye eee egre Rt t E DERE ERRRRCODGRRUEE Dee ERU ka aa 82 19 Conceptual Fan Control on PECI Based Platforms rr 83 20 Conceptual Fan Control on Thermal Diode Based Platforms 83 21 Processor Low Power State Machine sssssssssseseeee ennemis 86 22 Mechanical Representation of the Boxed Processor ssessssssssseeme mme 91 23 Space Requirements for the Boxed Processor Side View
12. 2 3 4 R Series Resistance 2 79 4 52 6 24 Q 2 3 5 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Preliminary data Will be characterized across a temperature range of 50 80 C 3 Not 100 tested Specified by design characterization 4 The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation lew Ig e qVp nkT 1 where ls saturation current q electronic charge Vp voltage across the diode k Boltzmann Constant and T absolute temperature Kelvin 5 The series resistance Ry is provided to allow for a more accurate measurement of the junction temperature Rz as defined includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor Ry can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation Terror Rr N 1 I wmin nk q In N where Terror sensor temperature error N sensor current ratio k Boltzmann Constant q electronic charge Datasheet Thermal Specifications and Design Considerations Table 29 Table 30 Datasheet Thermal
13. Diode Parameters using Transistor Model ntel Symbol Parameter Min Typ Max Unit Notes lew Forward Bias Current 5 200 HA 1 2 lg Emitter Current 5 200 Ng Transistor deality 0 997 1 001 1 005 3 4 5 Beta 0 391 0 760 3 4 Rr Series Resistance 2 79 4 52 6 24 Q 3 6 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Same as Irwin Table 28 3 Preliminary data Will be characterized across a temperature range of 50 80 C 4 Not 100 tested Specified by design characterization 5 The ideality factor nQ represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current lc a Is e qVgg nokT 1 Where ls saturation current q electronic charge Vgg voltage across the transistor base emitter junction same nodes as VD k Boltzmann Constant and T absolute temperature Kelvin 6 The series resistance Rz provided in the Diode Model Table Table 28 can be used for more accurate readings as needed The Intel Celeron Dual Core processor E1000 series does not support the diode correction offset that exists on other Intel processors Thermal Diode Interface Signal Name Land Number signal Description THERMDA AL1 diode anode THERMDC AK1 diode cathode 81 n tel Thermal Specifications and Design Considerations 5 4 5 4 1 Figur
14. 5 2 1 76 Thermal Metrology The maximum and minimum case temperatures Tc for the processor is specified in Table 26 This temperature specification is meant to help ensure proper operation of the processor Figure 16 illustrates where Intel recommends Tc thermal measurements should be made For detailed guidelines on temperature measurement methodology refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 Case Temperature Tc Measurement Location Measure T at this point geo metric center of the package 37 5 mm Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption by modulating starting and stopping the internal processor core clocks The Thermal Monitor feature must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor feature is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alter
15. 61 62 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction Lana Land Name Signal Buffer Direction Type Type AH30 VCC Power Other AK9 VCC Power Other AJ1 BPM1 Common Clock nput Output AK10 vss Power Other AJ2 BPMO Common Clock nput Output AK11 VCC Power Other AJ3 ITP CLK1 TAP Input AK12 VCC Power Other AJ4 VSS Power Other AK13 vss Power Other AJ5 A343 Source Synch Input Output AK14 VCC Power Other AJ6 A35 Source Synch Input Output AK15 VCC Power Other AJ7 VSS Power Other AK16 VSS Power Other AJ 8 VCC Power Other AK17 VSS Power Other AJ9 VCC Power Other AK18 VCC Power Other AJ 10 VSS Power Other AK19 VCC Power Other AJ11 VCC Power Other AK20 VSS Power Other AJ 12 VCC Power Other AK21 VCC Power Other AJ 13 VSS Power Other AK22 VCC Power Other Aj 14 VCC Power Other AK23 VSS Power Other AJ15 VCC Power Other AK24 VSS Power Other AJ 16 VSS Power Other AK25 VCC Power Other AJ17 VSS Power Other AK26 VCC Power Other AJ18 VCC Power Other AK27 VSS Power Other AJ19 VCC Power Other AK28 VSS Power Other AJ20 VSS Power Other AK29 VSS Power Other AJ21 VCC Power Other AK30 VSS Power Other AJ 22 VCC Power Other AL1 THERMDA Power Other AJ 23 VSS Power Other AL2 PROCHOT Asyn
16. 96 Baseboard Power Header Placement Relative to Processor Socket R110 4 33 4 33 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink However meeting the processor s temperature specification is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is listed in Chapter 5 The boxed processor fan heatsink is able to keep the processor temperature within the specifications see Table 26 in chassis that provide good thermal management For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life Figure 28 and Figure 29 illustrate an acceptable airspace clearance for the fan heatsink The air temperature entering the fan should be kept below 38 9C Again meeting the processor s temperature specification is the responsibility of the system integrator Datasheet e Boxed Processor Speci
17. BOX 58119 o intel SANTA CLARA CA 95052 8119 CORP EY l HEET or 3 MODEL C88285 DO NOT SCALE DRAWING DEPARTMENT ATD TITLE DRAWING NUMBER SITE A bue 5 1 DATE 02 23 05 DATE 02 23 05 DATE DATE FINISH DESIGNED BY M MANUSHAROW DRAWN BY N WALSH CHECKED BY APPROVED BY MATERIAL UNLESS OTHERWISE SPECIFIED INTERPRET DIMENSIONS AND TOLERANCES THIRD ANGLE PROJECTION COMMENTS go 203 C DJE WAX 31 55 37 55 2 3 2 3 4 242 2 593 MILLIMETERS MIN 31 45 31 45 33 9 33 9 2 2 2 2 3 806 33 93 BASIC 34 88 BASIC 16 965 BASIC 17 44 BASIC 0 82 1 17 BASIC 1 09 BASIC 0 14 SYMBOL 8 8 Sa I f FRONT VIEW M oma B SCALE 50 1 34 Datasheet Package Mechanical Specifications n te Figure 9 Processor Package Drawing Sheet 2 of 3 e rra ui l a o a lt 2T 88285 w C88285 DO NOT SCALE DRAWING fucer 2 oF 3 SITE DRAWING WONDER lt lt vera C SCALE 20 1 0 021 2200 MISSION COLLEGE BLVD P 0 BOX 58119 e cole intel
18. Design Considerations Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as described in Section 5 1 1 Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete thermal solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting For more information on designing a component level thermal solution refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 The boxed processor will ship with a component thermal solution Refer to Chapter 7 for details on the boxed processor Thermal Specifications To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature Tc specifications when operating at or below th
19. factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors Datasheet 13 m n tel Electrical Specifications 14 FSB Decoupling The processor integrates signal termination on the die In addition some of the high frequency capacitance required for the FSB is included on the processor package However additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus Bulk decoupling must also be provided by the motherboard for proper A GTL bus operation Voltage Identification The Voltage Identification VI D specification for the processor is defined by the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC pins see Chapter 2 6 3 for Vcc overshoot specifications Refer to Table 13 for the DC specifications for these signals Voltages for each processor frequency is provided in Table 5 Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings This is reflected by the VID Range value
20. r 84 Features 22gz_22 m222gmmmmgmmmmmmm 85 6 1 Power On Configuration Options rr ene tenant ata kak aa 85 6 2 Clock Control and Low Power States r nee enm ened 86 6 2 1 Normal State rris n wae px ten rnt am Kad EIU d Kan wana MERE lawn ek N eres 86 6 2 2 HALT and Extended HALT Powerdown States r kk 86 6 2 2 1 HALT Powerdown State kk kk kk kak kk k aka 87 6 2 2 2 Extended HALT Powerdown State kMhK K W llkkkk kk teen eee eaten natn 87 6 2 3 Stop Grant and Extended Stop Grant States r 87 6 2 2 1 Stop Grant State a pa sap aa Bar o ala kla OR Ra C bal ERR B 88 6 2 3 2 Extended Stop Grant State rn 88 6 2 4 Extended HALT Snoop State HALT Snoop State Extended Stop Grant Snoop State and Stop Grant Snoop State 88 6 2 4 1 HALT Snoop State Stop Grant Snoop State 88 6 2 4 2 Extended HALT Snoop State Extended Stop Grant Snoop State 89 6 3 Enhanced Intel SpeedStep Technology rr 89 Boxed Processor Specifications sss meme eene 91 7 1 Mechanical Specifications cicer u orent e ER RR RR nak bakan hak Men kada Waw Rae ug iA 92 7 1 1 Boxed Processor Cooling Solution Dimensions sse 92 7 1 2 Boxed Processor Fan Heatsink Weight rr rr 94 7 1 3 Boxed Proc
21. 1 0 1 1 0500 0 0 1 1 1 0 1 4375 1 0 1 1 0 0 1 0625 0 0 1 1 0 1 1 4500 1 0 1 0 1 1 1 0750 0 0 1 1 0 0 1 4625 1 0 1 0 1 0 1 0875 0 0 1 0 1 1 1 4750 1 0 1 0 0 1 1 1000 0 0 1 0 1 0 1 4875 1 0 1 0 0 0 1 1125 0 0 1 0 0 1 1 5000 1 0 0 1 1 1 1 1250 0 0 1 0 0 0 1 5125 1 0 0 1 1 0 1 1375 0 0 0 1 1 1 1 5250 1 0 0 1 0 1 1 1500 0 0 0 1 1 0 1 5375 1 0 0 1 0 0 1 1625 0 0 0 1 0 1 1 5500 1 0 0 0 1 1 1 1750 0 0 0 1 0 0 1 5625 1 0 0 0 1 0 1 1875 0 0 0 0 1 1 1 5750 1 0 0 0 0 1 1 2000 0 0 0 0 1 0 1 5875 1 0 0 0 0 0 1 2125 0 0 0 0 0 1 1 6000 0 1 1 1 1 1 1 2250 0 0 0 0 0 0 OFF Datasheet 15 m n tel Electrical Specifications Table 3 2 5 16 Market Segment I dentification MSI D The MSID 1 0 signals may be used as outputs to determine the Market Segment of the processor Table 3 provides details regarding the state of MSID 1 0 A circuit can be used to prevent 130 W TDP processors from booting on boards optimized for 65 W TDP Market Segment Selection Truth Table for MSID 1 0 2 3 4 MSID1 MSIDO Description 0 0 Intel Celeron Dual Core processor E1000 series 0 1 Reserved 1 0 Reserved 1 1 Reserved NOTES 1 The MSID 1 0 signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying Circuitry on the motherboard may use these signals to identify the processor installed 2 These sign
22. 2 1 6 2 2 2 6 2 3 Datasheet intel HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions When one of the processor cores executes the HALT instruction that processor core is halted however the other processor continues normal operation The processor will transition to the Normal state upon the occurrence of SMI INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself HALT Powerdown State The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the Intel Architecture Software Developer s Manual Volume IIl System Programmer s Guide for more information The system can generate a STPCLK while the processor is in the HALT powerdown state When the system de asserts the STPCLK interrupt the processor will return execution to the HALT state While in HALT powerdown state the processor will process bus snoops Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS When one of the processor cores executes the HALT instruction that logical processor is halted however the other processor continues normal operation The Extended HALT powerdown state must be enabled via the BIOS for the processor to remain within its specification
23. A 100 HA 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vi is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3 The Vy referred to in these specifications refers to instantaneous Vy 4 Vig is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 5 Vin and Voy may experience excursions above Vrr However input signal drivers must comply with the signal quality specifications 6 All outputs are open drain 7 lo is measured at 0 10 Vrr loy is measured at 0 90 V 8 Leakage to Vss with land held at Vy 9 Leakage to V with land held at 306 mv GTL Front Side Bus Specifications In most cases termination resistors are not required as these are integrated into the processor silicon See Table 9 for details on which GTL signals do not include on die termination Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF Table 14 lists the GTLREF specifications The GTL reference voltage GTLREF should be generated on the system board using high precision voltage divider circuits Datasheet Electrical Specifications Table 14 Datasheet GTL Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes GTLREF pull up resistor on GTLREF_PU 97
24. Clock Input B12 D13 Source Synch Input Output A4 D02 Source Synch Input Output B13 COMP8 Power Other Input A5 D04 Source Synch Input Output B14 VSS Power Other A6 VSS Power Other B15 D53 Source Synch Input Output A7 DO7 Source Synch Input Output B16 D55 Source Synch Input Output A8 DBIO Source Synch Input Output B17 VSS Power Other A9 VSS Power Other B18 D57 Source Synch Input Output A10 DO8 Source Synch Input Output B19 D60 Source Synch Input Output All D09 Source Synch Input Output B20 VSS Power Other A12 VSS Power Other B21 D59 Source Synch Input Output A13 COMPO Power Other Input B22 D63 Source Synch Input Output Al4 D50 Source Synch Input Output B23 VSSA Power Other A15 VSS Power Other B24 VSS Power Other A16 DSTBN3 Source Synch Input Output B25 VIT Power Other A17 D56 Source Synch Input Output B26 VIT Power Other A18 VSS Power Other B27 VIT Power Other A19 D61 Source Synch Input Output B28 VIT Power Other A20 RESERVED B29 VTT Power Other A21 VSS Power Other B30 VIT Power Other A22 D62 Source Synch Input Output CI DRDY Common Clock Input Output A23 VCCA Power Other C2 BNR Common Clock Input Output A24 FC23 Power Other c3 LOCK Common Clock Input Output A25 VIT Power Other C4 VSS Power Other A26 VIT Power Other C5 D01 Source Synch Input Output A27 VTT Power Other C6 D03 Source Synch Input Output A28 VTT Power Other C7 VSS Power Other A29 VIT Power Other C8 DSTBNO Source Synch Input Output A30
25. D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electrically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DBI 3 D 63 48 DBI2 D 47 32 DBI1 D 31 16 DBIO D 15 0 DBR Output DBR Debug Reset is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal DBSY Input Output DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is de asserted This signal must connect the appropriate pins lands on all processor FSB agents Datasheet Land Listing and Signal Descriptions Table 25 Datasheet intel Signal Description Sheet 4 of 9 Name DEFER Type Input Description DEFER is asserted by an agent to indicate that a transaction cannot be ensured in order completion Assertion of DEFER is normally the responsibility of the addressed memory or input output agent This signal must conn
26. Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep technology allows trade offs to be made between performance and power consumptions based on processor utilization This may lower average power consumption in conjunction with OS support Datasheet Introduction 1 2 Table 1 Datasheet References intel Material and concepts available in the following documents may be beneficial when reading this document References Document Location Intel Celeron Dual Core Processor E1000 Series Specificaiton Update www intel com design processor specupdt 318925 htm Intel Core 2 Duo Processor Intel Pentium Dual Core and Intel Celeron Dual Core Processor Thermal and Mechanical Design Guidelines http www intel com design processor designex 317804 htm Intel Pentium D Processor Intel Pentium Processor Extreme Edition Intel Pentium 4 Processor and Intel Core 2 Duo Extreme Processor Thermal and Mechanical Design Guidelines http www intel com design pentiumXE designex 306830 htm Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket http www intel com design processor applnots 313214 htm LGA775 Socket Mechanical Design Guide http intel com design Pentium4 guides 302666 htm Intel 64 and 1A 32 Architecture Software Developer s Manuals Intel 64 and IA 32 Architecture S
27. Hysteresis 0 1 Vr V Vn Negative edge threshold voltage 0 275 V r 0 500 Vr1 V Vp Positive edge threshold voltage 0 550 Vr1 0 762 Vr V E s ue so na ma I sink apud a 0 5 1 0 mA lleak High impedance state leakage to V r N A 50 HA 3 lleak High impedance leakage to GND N A 10 HA Cbus Bus capacitance per node N A 10 pF 4 Vnoise Signal noise immunity above 300 MHz 0 1 Vr Vp p NOTES 1 2 3 4 Vr supplies the PECI interface PECI behavior does not affect V min max specifications Refer to Table 4 for V specifications might appear as additional nodes The input buffers use a Schmitt triggered input design for improved noise immunity The leakage specification applies to powered devices on the PECI bus One node is counted for each client and one node for the system host Extended trace lengths Datasheet m e Package Mechanical Specifications n tel 3 Figure 7 3 1 Datasheet Package Mechanical Specifications The processor is packaged in a Flip Chip Land Grid Array FC LGA6 package that interfaces with the motherboard via an LGA775 socket The package consists of a processor core mounted on a substrate land carrier An integrated heat spreader I HS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 7 shows a sketch of the processor package components and how they are assembl
28. Power Other Input H11 VSS Power Other G3 TESTHI8 FC42 Power Other Input H12 VSS Power Other G4 TESTHI9 FC43 Power Other Input H13 VSS Power Other G5 PECI Power Other Input Output H14 VSS Power Other G6 RESERVED H15 FC32 Power Other G7 DEFER Common Clock Input H16 FC33 Power Other G8 BPRI Common Clock Input H17 VSS Power Other G9 D16 Source Synch Input Output H18 VSS Power Other G10 FC38 Power Other H19 VSS Power Other G11 DBI1 Source Synch Input Output H20 vss Power Other G12 DSTBN1 Source Synch Input Output H21 VSS Power Other G13 D27 Source Synch I nput Output H22 vss Power Other G14 D29 Source Synch Input Output H23 VSS Power Other G15 D31 Source Synch Input Output H24 VSS Power Other G16 D32 Source Synch Input Output H25 VSS Power Other G17 D36 Source Synch I nput Output H26 VSS Power Other G18 D35 Source Synch Input Output H27 VSS Power Other G19 DSTBP2 Source Synch Input Output H28 VSS Power Other G20 DSTBN2 Source Synch Input Output H29 FC15 Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Name sane Buter Direction tand Land Name signal Butten Direction Type Type H30 BSEL1 Power Other Output K23 VCC Power Other jl VTT_OUT_LEFT Power Other Outpu
29. Specifications Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging systems Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of systems the LAI is critical in providing the ability to probe and capture FSB signals There are two sets of considerations to keep in mind when designing a system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI lands plug into the processor socket while the processor lands plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor s heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LA
30. The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 Request Command must connect the appropriate pins lands of all processor FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTBO RESET Input Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after Vcc and BCLK have reached their proper specifications On observing active RESET all FSB agents will de assert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 6 1 This signal does not have on die termination and must be terminated on the system board RESERVED All RESERVED lands must remain unconnected Connection of these lands to Vcc Vss VTT or to any other signal including each other can result in component malfunction or incompatibility with future processors 69 Table 25 70 intel Land Listing and Signal De
31. V4 Source Synch Input Output COMPO A13 Power Other Input Al6 W5 Source Synch Input Output COMP1 T1 Power Other Input Al7 AB6 Source Synch Input Output COMP2 G2 Power Other Input A18 W6 Source Synch Input Output COMP3 R1 Power Other Input A195 Y6 Source Synch Input Output COMP8 B13 Power Other Input A20 Y4 Source Synch nput Output DO B4 Source Synch Input Output A20M K3 Asynch CMOS Input D1 C5 Source Synch Input Output A21 AAA Source Synch Input Output D2 A4 Source Synch Input Output A22 AD6 Source Synch Input Output D3 C6 Source Synch Input Output A23 AA5 Source Synch Input Output D4 A5 Source Synch Input Output A24 AB5 Source Synch Input Output D5 B6 Source Synch Input Output A25 AC5 Source Synch Input Output D6 B7 Source Synch Input Output A26 ABA Source Synch Input Output D7 A7 Source Synch Input Output A27 AF5 Source Synch Input Output D8 A10 Source Synch Input Output A28 AF4 Source Synch Input Output D9 A11 Source Synch Input Output A29 AG6 Source Synch Input Output D10 B10 Source Synch Input Output A30 AG4 Source Synch Input Output D11 C11 Source Synch Input Output A31 AG5 Source Synch Input Output D12 D8 Source Synch Input Output A32 AH4 Source Synch Input Output D134 B12 Source Synch Input Output A33 AH5 Source Synch Input Output D14 C12 Source Synch Input Output A34 AJ5 Source Synch Input Output D15 D11 Source Synch Input Out
32. VCC Power Other v4 A15 Source Synch Input Output Y25 VCC Power Other V5 Al4 Source Synch Input Output Y26 VCC Power Other V6 VSS Power Other Y27 VCC Power Other V7 VSS Power Other Y28 VCC Power Other V8 VCC Power Other Y29 VCC Power Other V23 vss Power Other Y30 VCC Power Other V24 VSS Power Other AA1 VTT_OUT_RIGHT Power Other Output V25 VSS Power Other AA2 FC39 Power Other V26 VSS Power Other AA3 VSS Power Other V27 VSS Power Other AA4 A21 Source Synch Input Output V28 VSS Power Other AA5 A23 Source Synch Input Output V29 VSS Power Other AA6 VSS Power Other v30 VSS Power Other AA7 VSS Power Other W1 MSI DO Power Other Output AA8 VCC Power Other W2 TESTHI12 FC44 Power Other Input AA23 VSS Power Other W3 TESTHI1 Power Other Input AA24 VSS Power Other wa VSS Power Other AA25 VSS Power Other W5 Al6 Source Synch Input Output AA26 VSS Power Other W6 A18 Source Synch Input Output AA27 vss Power Other w7 vss Power Other AA28 vss Power Other w8 VCC Power Other AA29 VSS Power Other W23 VCC Power Other AA30 VSS Power Other W24 VCC Power Other AB1 VSS Power Other W25 VCC Power Other AB2 IERR Asynch CMOS Output W26 VCC Power Other AB3 FC37 Power Other W27 VCC Power Other AB4 A26 Source Synch Input Output W28 VCC Power Other AB5 A24 Source Synch Input Output W29 VCC Power Other AB6 A17 Source Synch Input Output W30 VCC Power Other AB7 VSS Power Other Y1 FCO Power Other AB8 VCC Power Other Y2 VSS
33. VIT Power Other C9 FC38 Power Other Bl VSS Power Other C10 VSS Power Other B2 DBSY Common Clock nput Output C11 D11 Source Synch Input Output B3 RSO Common Clock Input C12 D14 Source Synch Input Output B4 DOO Source Synch Input Output C13 VSS Power Other B5 VSS Power Other C14 D52 Source Synch Input Output B6 DO5 Source Synch Input Output C15 D51 Source Synch Input Output B7 D06 Source Synch Input Output C16 VSS Power Other B8 VSS Power Other C17 DSTBP3 Source Synch Input Output B9 DSTBPO Source Synch Input Output C18 D54 Source Synch Input Output B10 D10 Source Synch Input Output C19 VSS Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment rane Land Name oe Direction E Land Name M oe Direction C20 DBI 3 Source Synch Input Output D29 VTT Power Other C21 D58 Source Synch Input Output D30 VTT Power Other C22 VSS Power Other E2 VSS Power Other C23 VCCIOPLL Power Other E3 TRDY Common Clock Input C24 VSS Power Other E4 HITM Common Clock Input Output C25 VIT Power Other E5 FC20 Power Other C26 VIT Power Other E6 RESERVED C27 VIT Power Other E7 RESERVED C28 VIT Power Other E8 VSS Power Other C29 VIT Power Other E9 D19 Source Synch Input Output C30 VIT Power Other E10 D21 Source Sync
34. Z N2 Asynch CMOS Input SKTOCC AE8 Power Other Output INIT P3 Asynch CMOS Input SMI P2 Asynch CMOS Input ITP CLKO AK3 TAP Input STPCLK M3 Asynch CMOS Input ITP CLK1 AJ3 TAP Input TCK AE1 TAP Input LINTO K1 Asynch CMOS Input TDI AD1 TAP Input LINT1 L1 Asynch CMOS Input TDO AF1 TAP Output LOCK C3 Common Clock Input Output TESTHIO F26 Power Other Input MSIDO W1 Power Other Output TESTHI1 W3 Power Other Input MSID1 V1 Power Other Output TESTHI 10 H5 Power Other Input PECI G5 Power Other Input Output TESTHI 11 P1 Power Other Input PROCHOT AL2 Asynch CMOS Input Output ae w2 Power Other Input PWRGOOD N1 Power Other Input TESTHI13 L2 Power Other Input REQO K4 Source Synch Input Output TESTHI2 F25 Power Other Input REQ1 j5 Source Synch Input Output TESTHI3 G25 Power Other Input REQ2 M6 Source Synch Input Output TESTHI4 G27 Power Other Input REQ3 K6 Source Synch Input Output TESTHI5 G26 Power Other Input REQ4 J6 Source Synch I nput Output TESTHI6 G24 Power Other Input RESERVED A20 TESTHI7 F24 Power Other Input RESERVED AC4 TESTHI8 FC42 G3 Power Other Input RESERVED AE4 TESTHI9 FC43 G4 Power Other Input RESERVED AE6 THERMDA AL1 Power Other RESERVED AH2 THERMDC AK1 Power Other RESERVED D1 THERMTRIP M2 Asynch CMOS Output RESERVED D14 TMS AC1 TAP Input Datasheet Land Listing and Signal Descriptions intel
35. applied by a heatsink retention clip The clip must also provide the minimum specified load on the processor package 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement Package Handling Guidelines Table 21 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Notes Shear 311 N 70 Ibf L2 Tensile 111 N 25 Ibf 2 3 Torque 3 95 N m 35 Ibf in 2 4 NOTES 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 These guidelines are based on limited testing for design characterization 3 A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface 4 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 37 m n tel Package Mechanical Specifications 3 7 Table 22 3 8 Figure 11 38 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15
36. are still present A20M IGNNEZ etc and can become active at any time during the clock cycle Table 8 identifies which signals are common clock source synchronous and asynchronous Table 8 FSB Signal Groups Signal Group Type Signals GTL Common Synchronous to Clock Input BCLK 1 0 BPRI DEFER RESET RS 2 0 TRDY GTL Common Synchronous to ADS BNR BPM 5 0 BRO DBSY DRDY HIT Clock 1 0 BCLK 1 0 HITM LOCK Signals Associated Strobe REQ 4 0 A 16 3 3 ADSTBO GTL Source Synchronous to A 35 17 3 ADSTB1 synchronous THO J ass Strone D 15 0 DBIO DSTBPO DSTBNO D 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 Synchronous to j GTL Strobes BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 A20M IGNNEZ INIT LINTO INTR LINT1 NMI SMI CMOS STPCLK PWRGOOD TCK TDI TMS TRST BSEL 2 0 VID 6 1 Open Drain FERR PBE IERR THERMTRIP TDO Output Open Drain 4 Input Output PROCHOLZ FSB Clock Clock BCLK 1 0 ITP CLK 1 0 VCC VTT VCCA VCCIOPLL VCCPLL VSS VSSA GTLREF 1 0 COMP 8 3 0 RESERVED TESTHI 13 0 Power Other VCC SENSE VCC MB REGULATION VSS SENSE VSS MB REGULATION DBR 2 VTT OUT LEFT VTT OUT RIGHT VIT SEL FCx PECI MSID 1 0 NOTES 1 Refer to Section 4 2 for signal descriptions 2 In processor systems where no debug port is implemented on the system board these signals are used to support a debug
37. as the on die termination resistors Rrr For details see Table 14 TAP and CMOS signals do not include on die termination Inputs and used outputs must be terminated on the motherboard Unused outputs may be terminated on the motherboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing All TESTHI 13 0 lands should be individually connected to V m via a pull up resistor that matches the nominal trace impedance Datasheet m e Electrical Specifications n tel The TESTHI signals may use individual pull up resistors or be grouped together as detailed below A matched resistor must be used for each group TESTHI 1 0 TESTHI 7 2 TESTHI8 FC42 cannot be grouped with other TESTHI signals TESTHI9 FC43 cannot be grouped with other TESTHI signals TESTHI 10 cannot be grouped with other TESTHI signals TESTHI 11 cannot be grouped with other TESTHI signals TESTHI 12 FC44 cannot be grouped with other TESTHI signals TESTHI 13 cannot be grouped with other TESTHI signals However use of boundary scan test will not be functional if these lands are connected together For optimum noise margin all pull up resistor values used for TESTHI 13 0 lands should have a resistance value within x 2096 of the impedance of the board transmission line traces For example if the nominal trace impedance is 50 O then
38. current generation of desktop products with the power efficiencies of a low power microarchitecture to enable smaller quieter systems These dual core processors are based on 65 nm process technology They are 64 bit processors that maintain compatibility with A 32 software The Intel Celeron Dual Core processor E1000 series uses Flip Chip Land Grid Array FC LGA6 package technology and plugs into a 775 land surface mount Land Grid Array LGA socket referred to as the LGA775 socket In this document unless otherwise specified the Intel Celeron Dual Core processor E1000 series refers to Intel Celeron Dual Core processor E1200 In this document unless otherwise specified the Intel Celeron Dual Core processor E1000 series is referred to as processor The processor supports advanced technologies including Execute Disable Bit Intel 64 architecture and Enhanced Intel SpeedStep technology The processor s front side bus FSB uses a split transaction deferred reply protocol like the Intel Pentium 4 processor The FSB uses Source Synchronous Transfer SST of address and data to improve performance by transferring data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or 2X address bus Working together the 4X data bus and 2X address bus provide a data bus bandwidth
39. of the processor depending on each particular state See Figure 21 for a visual representation of the processor low power states Figure 21 Processor Low Power State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated Extended HALT or HALT Normal State INIT BINIT INTR NMI SMI State Normal Execution RESET FSB interrupts BCLK running Snoops and interrupts allowed A A Snoop Snoop STPCLK STPCLK vans Even Occurs Serviced Asserted De asserted STPCLK Asserted STPCLK De asserted Extended HALT Snoop or HALT Snoop State BCLK running Service Snoops to cahces Y Stop Grant Stat S Event O SP ME AER NOOP E Vene e e edt Stop Grant Snoop State BOLK running BCLK running SB06pS and interrupts Snoop Event Serviced Service Snoops to cahces allowed la 6 2 1 Normal State This is the normal operating state for the processor 6 2 2 HALT and Extended HALT Powerdown States The processor supports the HALT or Extended HALT powerdown state The Extended HALT powerdown must be enabled via the BIOS for the processor to remain within its specification The Extended HALT state is a lower power state as compared to the Stop Grant State If Extended HALT is not enabled the default powerdown state entered will be HALT Refer to the sections below for details about the HALT and Extended HALT states 86 Datasheet Features 6 2
40. state In addition all other input signals on the FSB should be driven to the inactive state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB see Section 6 2 4 While in the Stop Grant State SMI INIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal State Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process a FSB snoop Extended Stop Grant State Extended Stop Grant is a low power state entered when the STPCLK signal is asserted and Extended Stop Grant has been enabled via the BIOS The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state When entering the low power state the processor will first switch to the lower bus ratio and then transition to the lower VID The processor exits the Extended Stop Grant state when a break event occurs When the processor exits the Extended Stop Grant state it will resume operation at the lower frequency transition the VID to the original value and then change the bus ratio back to the original value Extended HA
41. times The Socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide Processor Mass Specification The typical mass of the processor is 21 5 g 0 76 oz This mass weight includes all the components that are included in the package Processor Materials Table 22 lists some of the package components and associated materials Processor Materials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper Processor Markings Figure 11 shows the topside markings on the processors This diagram aids in the identification of the processor Processor Top Side Markings Example INTELOO 06 E1200 Celeron DUAL CORE Silke COO 1 60GHZ 512 800 06 Eo Datasheet intel Voc Vss 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 12 shows the top view of the processor land coordinates The coordinates are referred to throughout the document to identify processor lands Processor Land Coordinates Processor Land Coordinates and Quadrants Top View Package Mechanical Specifications Figure 12 3 9 gt o ze O 9 Oc SOB 2 amp lt lt E Q O ZZa24X219u54Uu99g9zZ z 2 o5 cazzoaeorowunoomc SADC OOOO QO Q SOSO y OOOO Q O C
42. 0000000000000000000 0009 OOOOOOOOOOOOOOO 0O000000000000000Q0 OOOO0000000000000p000000000000000 OOOO00000000000060000000000000000 O00000000000000000000000000000006 OO00O00000000000009po000000000000000 QO0000000000000000000000000000000 QO0000000000000000000000000000000 O00000000 Q00000000 000000000 OQ00000000 O00000000 OOOOOOOOO 600060060 OOOOOOOOQ 90000000 9090909009 00000000 00000000 00000000 0900000060 O00000000 OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOOOOOOOOOQOOOOOOOOOOOOOOOOQ OO0000000000000000000000000000000 t aa OOOOOOOOQ OOOOOOOO OO b O0000000 00000000 OOOOOOOO O00000000 O000000000000000 OOo OO OO00000000000000006000000000000000 OOOOOOO0O0000O000000000000000000000 QOO000000000000000000000000000000 0 BOTTOM VIEW QOOOOOOOCOOOOOOOOQ 9968008909 Q0000000000000 GO960090990 eoe See i 5 o I L SECTION E E G 8 I IHS LID TOP VIEW c IHS LID Z7 0 05 o 203 4 C 0 203 7 o 08 Z IHS SEALANT PACKAGE SUBSTRATE j x j I vetat A SCALE 15 1 2200 MISSION COLLEGE BLVD P O
43. 20 30 40 50 60 70 Vcc Maximum Vcc V NOTES 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 6 3 2 This loadline specification shows the deviation from the VID set point 3 The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details Vcc Overshoot The processor can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos wax is the maximum allowable overshoot voltage The time duration of the overshoot event must not exceed Tos max Tos max is the maximum allowable time duration above VID These specifications apply to the processor die voltage as measured across the VCC SENSE and VSS SENSE lands Vcc Overshoot Specifications Symbol Parameter Min Max Unit Figure Notes Vos MAX Magnitude of Vcc overshoot above _ 50 mV 2 1 VID Time duration of Vcc overshoot above Tos_MAX ce 25 us 2 VID NOTES 1 Adherence to these specifications is required to ensure relia
44. 29 The Diode Model parameters Table 28 apply to traditional thermal sensors that use the Diode Equation to determine the processor temperature Transistor Model parameters Table 29 have been added to support thermal sensors that use the transistor equation method The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits This thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor TcoNTROL is a temperature specification based on a temperature reading from the thermal diode The value for Tcontrot Will be calibrated in manufacturing and configured for each processor The TcontroL temperature for a given processor can be obtained by reading a MSR in the processor The Tcontro value that is read from the MSR needs to be converted from Hexadecimal to Decimal and added to a base value of 50 C The value of Tcontrot may vary from 00 h to 1E h 0 to 30 C When Tpiope is above TcowrRoL then Tc must be at or below Tc max as defined by the thermal profile in Table 28 otherwise the processor temperature can be maintained at TcowrRo or lower as measured by the thermal diode Thermal Diode Parameters using Diode Model Symbol Parameter Min Typ Max Unit Notes lew Forward Bias Current 5 200 HA T n Diode Ideality Factor 1 000 1 009 1 050
45. 5 7 65 25 OOOOOOOOOQOOOOOO OOOOOOOCOOQOOOOOO 0000000000000000 OOOOOOOOOQOOOOOO OOOOOOOOOQOOOOOO OOOOOOOOOQOOOOOO 0000000000000000 o0006999Q L 000000000 000000000 000000000 000000000 000000000 99099999909 OOOOOOOOOQOOOOOOO0OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO 2000 0000 0000000000 0000000000 0000000000 0000000000 0000000000 0000000000 0000050000000000 4 000000000 le 660066000 000000000 000000000 000000000 000000000 900000000 13 7 195 7 0 115 000000000 000000000 000000000 000000000 000000000 000000000 0000000000000000 0000000000000000 0000000000000000 OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO lk a asas y salk 000000000 s 3 000000000 000000000 000000000 OOOOOOOOO OOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOO 000 O O 1 5 MAX ALLOWABLE COMPONENT HEIGHT BOTTOM VIEW SIDE VIEW TOP VIEW REY C88285 DO NOT SCALE DRAWING fuEer 3 or 3 6 SIE 0ANING NUNBER 2200 MISSION COLLEGE BLVD P O BOX 581 SANTA CLARA o cone intel DEPARTMENT ATD 36 Datasheet Package Mechanical Specifications 3 2 3 3
46. 5X and 96x Express 124 0 99 124 124 1 01 Q 2 Chipset family boards GTLREF pull down resistor GTLREF_PD on 975X and 96x Express 210 0 99 210 210 1 01 Q E Chipset family boards GTLREF pull up resistor on GTLREF PU Intel Series 3 Express 100 0 99 100 100 1 01 Q 2 Chipset family boards GTLREF pull down resistor GTLREF_pp 9n Intel Series 3 Express 200 0 9 200 200 LOl o 2 Chipset chipset family boards Rr Termination Resistance 45 50 55 Q 3 COMP 3 0 COMP Resistance 49 40 49 90 50 40 Q 4 COMP8 COMP Resistance 24 65 24 90 25 15 Q 2i NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 GTLREF is to be generated from V m by a voltage divider of 1 resistors one divider for each GTLEREF land 3 Rrr is the on die termination resistance measured at V rr 3 of the GTL output driver 4 COMP resistance must be provided on the system board with 196 resistors COMP 3 0 and COMPS resistors are to Vss 27 2 8 2 8 1 Table 15 2 8 2 28 Clock Specifications Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the processor s core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier will be set at its default ratio during manufacturing Refer to Table 15 for the processor support
47. AG28 VCC Power Other AF20 VSS Power Other AG29 VCC Power Other AF21 VCC Power Other AG30 VCC Power Other AF22 VCC Power Other AH1 VSS Power Other AF23 VSS Power Other AH2 RESERVED AF24 VSS Power Other AH3 VSS Power Other AF25 VSS Power Other AH4 A32 Source Synch Input Output AF26 VSS Power Other AH5 A33 Source Synch Input Output AF27 VSS Power Other AH6 VSS Power Other AF28 VSS Power Other AH7 VSS Power Other AF29 VSS Power Other AH8 VCC Power Other AF30 VSS Power Other AH9 VCC Power Other AG1 TRST TAP Input AH10 VSS Power Other AG2 BPM3 Common Clock Input Output AH11 VCC Power Other AG3 BPM5 Common Clock Input Output AH12 VCC Power Other AG4 A30 Source Synch Input Output AH13 vss Power Other AG5 A31 Source Synch Input Output AH14 VCC Power Other AG6 A29 Source Synch Input Output AH15 VCC Power Other AG7 VSS Power Other AH16 VSS Power Other AG8 VCC Power Other AH17 VSS Power Other AG9 VCC Power Other AH18 VCC Power Other AG10 VSS Power Other AH19 VCC Power Other AG11 VCC Power Other AH20 VSS Power Other AG12 VCC Power Other AH21 VCC Power Other AG13 VSS Power Other AH22 VCC Power Other AG14 VCC Power Other AH23 VSS Power Other AG15 VCC Power Other AH24 VSS Power Other AG16 VSS Power Other AH25 VCC Power Other AG17 VSS Power Other AH26 VCC Power Other AG18 VCC Power Other AH27 VCC Power Other AG19 VCC Power Other AH28 VCC Power Other AG20 VSS Power Other AH29 VCC Power Other
48. AH26 Power Other VCC AE22 Power Other VCC AH27 Power Other VCC AE23 Power Other VCC AH28 Power Other VCC AE9 Power Other VCC AH29 Power Other VCC AF11 Power Other VCC AH30 Power Other VCC AF12 Power Other VCC AH8 Power Other VCC AF14 Power Other VCC AH9 Power Other VCC AF15 Power Other VCC AJ11 Power Other VCC AF18 Power Other VCC AJ12 Power Other VCC AF19 Power Other VCC AJ14 Power Other VCC AF21 Power Other VCC AJ15 Power Other 47 48 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name P s Sa Direction Land Name 2 Te Direction VCC AJ18 Power Other VCC AM19 Power Other VCC AJ19 Power Other VCC AM21 Power Other VEC AJ21 Power Other VCC AM22 Power Other VCC AJ22 Power Other VCC AM25 Power Other VCC AJ25 Power Other VCC AM26 Power Other VCC AJ26 Power Other VCC AM29 Power Other VCC AJ8 Power Other VCC AM30 Power Other VCC AJ9 Power Other VCC AM8 Power Other VCC AK11 Power Other VCC AM9 Power Other VCC AK12 Power Other VCC AN11 Power Other VCC AK14 Power Other VCC AN12 Power Other VCC AK15 Power Other VCC AN14 Power Other VCC AK18 Power Other VCC AN15 Power Other VCC AK19 Power Other VCC AN18 Power Other VCC AK21 Power Othe
49. CMOS Input M24 VCC Power Other K4 REQO Source Synch Input Output M25 VCC Power Other K5 VSS Power Other M26 VCC Power Other K6 REQ3 Source Synch Input Output M27 vcc Power Other K7 vss Power Other M28 VCC Power Other K8 VCC Power Other M29 VCC Power Other 57 58 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction Lana Land Name Signal Buffer Direction Type Type M30 VCC Power Other R7 VSS Power Other N1 PWRGOOD Power Other Input R8 VCC Power Other N2 IGNNE Z Asynch CMOS Input R23 VSS Power Other N3 VSS Power Other R24 VSS Power Other NA RESERVED R25 vss Power Other N5 RESERVED R26 vss Power Other N6 VSS Power Other R27 VSS Power Other N7 VSS Power Other R28 VSS Power Other N8 VCC Power Other R29 VSS Power Other N23 VCC Power Other R30 VSS Power Other N24 VCC Power Other T1 COMP1 Power Other Input N25 VCC Power Other T2 FC4 Power Other N26 VCC Power Other T3 VSS Power Other N27 VCC Power Other T4 A11 Source Synch Input Output N28 VCC Power Other T5 A09 Source Synch Input Output N29 VCC Power Other T6 VSS Power Other N30 VCC Power Other T7 VSS Power Other P1 TESTHI11 Power Other Input T8 VCC Power Other P2 SMI Asynch CMOS Input T23 VCC Power Other P3 INIT Asynch CMOS In
50. I Electrical Considerations The LAI will also affect the electrical performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides S 101 e n tel Debug Tools Specifications 102 Datasheet
51. Intel Celeron Dual Core Processor E1000 Series Datasheet January 2008 Document Number 318924 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLI ED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL LIFE SAVING OR LIFE SUSTAINING APPLICATIONS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Alntel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details Over time processor numbers will increment based on changes in c
52. L20 Power Other VSS AH17 Power Other VSS AL23 Power Other VSS AH20 Power Other VSS AL24 Power Other VSS AH23 Power Other VSS AL27 Power Other VSS AH24 Power Other VSS AL28 Power Other VSS AH3 Power Other VSS AL7 Power Other vss AH6 Power Other VSS AM1 Power Other VSS AH7 Power Other VSS AM10 Power Other VSS AJ10 Power Other VSS AM13 Power Other VSS AJ13 Power Other VSS AM16 Power Other VSS AJ16 Power Other vss AM17 Power Other VSS AJ17 Power Other vss AM20 Power Other VSS AJ20 Power Other VSS AM23 Power Other VSS AJ23 Power Other vss AM24 Power Other VSS AJ24 Power Other VSS AM27 Power Other VSS AJ27 Power Other VSS AM28 Power Other VSS AJ28 Power Other VSS AM4 Power Other VSS AJ29 Power Other vss AN1 Power Other VSS AJ30 Power Other vss AN10 Power Other VSS AJ4 Power Other VSS AN13 Power Other VSS AJ7 Power Other VSS AN16 Power Other VSS AK10 Power Other vss AN17 Power Other VSS AK13 Power Other VSS AN2 Power Other VSS AK16 Power Other VSS AN20 Power Other VSS AK17 Power Other VSS AN23 Power Other VSS AK2 Power Other VSS AN24 Power Other VSS AK20 Power Other VSS AN27 Power Other VSS AK23 Power Other VSS AN28 Power Other VSS AK24 Power Other VSS B1 Power Other VSS AK27 Power Other VSS B11 Power Other VSS AK28 Power Other VSS B14 Power Other VSS AK29 Power Other VSS B17 Power Other VSS AK30 Power Other vss B20 Power Other Datas
53. LT Snoop State HALT Snoop State Extended Stop Grant Snoop State and Stop Grant Snoop State The Extended HALT Snoop State is used in conjunction with the new Extended HALT state If Extended HALT state is not enabled in the BIOS the default Snoop State entered will be the HALT Snoop State Refer to the following sections for details on HALT Snoop State Stop Grant Snoop State Extended HALT Snoop State and Extended Stop Grant Snoop State HALT Snoop State Stop Grant Snoop State The processor will respond to snoop transactions on the FSB while in Stop Grant state or in HALT powerdown state During a snoop transaction the processor enters the HALT Snoop State Stop Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB After the snoop is serviced the processor will return to the Stop Grant state or HALT powerdown state as appropriate Datasheet Features 6 2 4 2 6 3 Note Datasheet intel Extended HALT Snoop State Extended Stop Grant Snoop State The processor will remain in the lower bus ratio and VID operating point of the Extended HALT state or Extended Stop Grant state While in the Extended HALT Snoop State or Extended Stop Grant Snoop State snoops are handled the same way as in the HALT Snoop State or Stop Grant Snoop State After the snoop is serviced the processor will return to the Extended HALT state or Exten
54. Power Other AB23 VSS Power Other Y3 FC17 Power Other AB24 VSS Power Other Y4 A20 Source Synch Input Output AB25 VSS Power Other Datasheet 59 60 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction Lana Land Name Signal Buffer Direction Type Type AB26 vss Power Other AE3 FC18 Power Other AB27 vss Power Other AE4 RESERVED AB28 VSS Power Other AE5 VSS Power Other AB29 vss Power Other AE6 RESERVED AB30 VSS Power Other AE7 VSS Power Other AC1 TMS TAP Input AE8 SKTOCC Power Other Output AC2 DBR Power Other Output AE9 VCC Power Other AC3 VSS Power Other AE10 VSS Power Other AC4 RESERVED AE11 VCC Power Other AC5 A25 Source Synch Input Output AE12 VCC Power Other AC6 VSS Power Other AE13 VSS Power Other AC7 VSS Power Other AE14 VCC Power Other AC8 VCC Power Other AE15 VCC Power Other AC23 VCC Power Other AE16 VSS Power Other AC24 VCC Power Other AE17 VSS Power Other AC25 VCC Power Other AE18 VCC Power Other AC26 VCC Power Other AE19 VCC Power Other AC27 VCC Power Other AE20 VSS Power Other AC28 VCC Power Other AE21 VCC Power Other AC29 VCC Power Other AE22 VCC Power Other AC30 VCC Power Other AE23 vcc Power Other AD1 TDI TAP I
55. Refer ES Lem 6 and V 4 5 6 E1200 1 6 GHz 3 Vcc Boor Default Vcc voltage for initial power up B 1 10 _ V VccPLL PLL Vcc 5 1 50 5 Processor Number VCC for lec 775_VR_CONFIG_06 A 7 E1200 1 6 GHz 75 FSB termination voltage 8 V 1 14 1 20 1 26 V H DC AC specifications VTT OUT LEFT and DC Current that may be drawn from VTT OUT RIGHT VTT OUT LEFT and VTT OUT RIGHT per 580 mA 9 lec pin Icc for V supply before Vcc stable 4 5 A 10 TE lI cc for Vr supply after Vcc stable 4 6 l cc_VCCPLL lec for PLL land 130 mA lcc GTLREF lec for GTLREF 200 HA NOTES 1 2 3 9 Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be updated with characterized data from silicon measurements at a later date Adherence to the voltage specifications for the processor are required to ensure reliable processor operation Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and can not be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep technology or Extended HALT State These voltages are targets only A variable voltage sour
56. SAAC OOOO IO O C DAOC O ES OOOO Oo O Q DOOD z C308 Teta KALANA WO Oo OO i OQ OC lan Pad amp YS DOOD 06060 OOOO GOO OO Iw UC D 3 Q 200 OOo O OOO O E O 500000 LO dq SOOO gt ry QO O N c o O Or O OOO O e O OOO t ox O K M NL N S D ash OOO O O OOD V Q SEGA Xy is O Q O O ee e gt A C C O O Oo O O AOD JOGO K zd 39 S Data 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16151413121110 9 8 7 6 5 4 3 2 1 C O OOO OOO OOOOOO 2900000000 D o OOO OO e ra 20000000 O o OOQOCK OO O O E Z24 2205U9993 z22 uazz2vorouunom gt Datasheet 40 Package Mechanical Specifications Datasheet e Land Listing and Signal Descriptions n tel d Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions 4 1 Processor Land Assignments This section contains the land listings for the processor The land out footprint is shown in Figure 13 and Figure 14 These figures represent the land out arranged by land number and they show the physical location of each signal on the package land array top view Table 23 provides a list of processor lands ordered alphabetically by land signal name Table 24 provides a list of processor lands ordered by land number Datasheet 41 m n te Land Listing and Signal De
57. Table 20 3 4 Table 21 Datasheet intel Processor Component Keep Out Zones The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out zones Decoupling capacitors are typically mounted to either the topside or land side of the package substrate See Figure 8 and Figure 9 for keep out zones The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep in Package Loading Specifications Table 20 provides dynamic and static load specifications for the processor package These mechanical maximum load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solution The minimum loading specification must be maintained by any thermal and mechanical solutions Processor Loading Specifications Parameter Minimum Maximum Notes Static 80 N 17 Ibf 311N 70 Ibf 12 3 Dynamic 756 N 170 Ibf 1 3 4 NOTES These specifications apply to uniform compressive loading in a direction normal to the processor IHS 2 This is the maximum force that can be
58. VCC J28 Power Other VCC T27 Power Other VCC J29 Power Other VCC T28 Power Other VCC J30 Power Other VCC T29 Power Other VCC J8 Power Other VCC T30 Power Other VCC J9 Power Other VCC T8 Power Other VCC K23 Power Other VCC U23 Power Other VCC K24 Power Other VCC U24 Power Other VCC K25 Power Other VCC U25 Power Other VCC K26 Power Other VCC U26 Power Other VCC K27 Power Other VCC U27 Power Other VCC K28 Power Other VCC U28 Power Other VCC K29 Power Other VCC U29 Power Other VCC K30 Power Other VCC U30 Power Other VCC K8 Power Other VCC U8 Power Other VCC L8 Power Other VCC V8 Power Other VCC M23 Power Other VCC W23 Power Other VCC M24 Power Other VCC W24 Power Other VCC M25 Power Other VCC W25 Power Other VCC M26 Power Other VCC W26 Power Other VCC M27 Power Other VCC W27 Power Other VCC M28 Power Other VCC W28 Power Other VCC M29 Power Other VCC W29 Power Other VCC M30 Power Other VCC W30 Power Other VCC M8 Power Other VCC ws Power Other VCC N23 Power Other VCC Y23 Power Other VCC N24 Power Other VCC Y24 Power Other VCC N25 Power Other VCC Y25 Power Other VCC N26 Power Other VCC Y26 Power Other VCC N27 Power Other VCC Y27 Power Other VCC N28 Power Other VCC Y28 Power Other VCC N29 Power Other VCC Y29 Power Other VCC N30 Power Other VCC Y30 Power Other VCC N8 Power Other VCC Y8 Power Other e s ae CLEA ON AN5 Power Other Output T m Power Other VCC_SENSE AN3 Powe
59. _SENSE Power Other Output lt AN5 REGULATION Power Other Output AL28 vss Power Other AN6 EEEN Power Other Output AL29 VCC Power Other AN7 VID_SELECT Power Other Output AL30 VCC Power Other AN8 vcc Power Other AMI vss Power Other AN9 VCC Power Other AM2 VIDO Power Other Output AN10 VSS Power Other AM3 VID2 Power Other Output AN11 VCC Power Other AM4 vss Power Other AN12 vcc Power Other AM5 VID6 Power Other Output AN13 VSS Power Other AM6 FC40 Power Other AN14 VCC Power Other AM7 VID7 Power Other Output AN15 VCC Power Other AM8 VCC Power Other AN16 VSS Power Other AM9 VCC Power Other AN17 vss Power Other AM10 vss Power Other AN18 vcc Power Other AM11 VCC Power Other AN19 VCC Power Other AM12 VCC Power Other AN20 VSS Power Other AM13 vss Power Other AN21 VCC Power Other AM14 VCC Power Other AN22 VCC Power Other AM15 VCC Power Other AN23 VSS Power Other AM16 vss Power Other AN24 VSS Power Other AM17 VSS Power Other AN25 VCC Power Other AM18 VCC Power Other AN26 VCC Power Other AM19 VCC Power Other AN27 VSS Power Other AM20 VSS Power Other AN28 VSS Power Other AM21 VCC Power Other AN29 VCC Power Other AM22 VCC Power Other AN30 VCC Power Other AM23 VSS Power Other AM24 vss Power Other AM25 VCC Power Other AM26 VCC Power Other Datasheet 63 intel Land Listing and Signal Descriptions 4 2 Alphabetical Signals Reference Table 25 Signal Description Sheet 1 of 9 Name Type D
60. a value between 40 Q and 60 Q should be used 2 6 Voltage and Current Specification 2 6 1 Absolute Maximum and Minimum Ratings Table 4 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Datasheet 17 Table 4 18 intel Absolute Maximum
61. age Transitions above the specified VID are not permitted Table 5 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 6 and Figure 1 as measured across the VCC SENSE and VSS SENSE lands The VRM or VRD used must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 5 and Table 6 Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further details Datasheet Electrical Specifications n tel Table 2 Voltage Identification Definition VI D6 VID5 VIDA VID3 VID2 VID1 Vcc MAX VI D6 VID5 VIDA VID3 VID2 VID1 Vcc MAX 1 1 1 1 0 1 0 8500 0 1 1 1 1 0 1 2375 1 1 1 1 0 0 0 8625 0 1 1 1 0 1 1 2500 1 1 1 0 1 1 0 8750 0 1 1 1 0 0 1 2625 1 1 1 0 1 0 0 8875 0 1 1 0 1 1 1 2750 1 1 1 0 0 1 0 9000 0 1 1 0 1 0 1 2875 1 1 1 0 0 0 0 9125 0 1 1 0 0 1 1 3000 1 1 0 1 1 1 0 9250 0 1 1 0 0 0 1 3125 1 1 0 1 1 0 0 9375 0 1 0 1 1 1 1 3250 1 1 0 1 0 1 0 9500 0 1 0 1 1 0 1 3375 1 1 0 1 0 0 0 9625 0 1 0 1 0 1 1 3500 1 1 0 0 1 1 0 9750 0 1 0 1 0 0 1 3625 1 1 0 0 1 0 0 9875 0 1 0 0 1 1 1 3750 1 1 0 0 0 1 1 0000 0 1 0 0 1 0 1 3875 1 1 0 0 0 0 1 0125 0 1 0 0 0 1 1 4000 1 0 1 1 1 1 1 0250 0 1 0 0 0 0 1 4125 1 0 1 1 1 0 1 0375 0 0 1 1 1 1 1 4250 1 0 1
62. als are not connected to the processor die 3 A logic 0 is achieved by pulling the signal to ground on the package 4 A logic 1 is achieved by leaving the signal as a no connect on the package Reserved Unused and TESTHI Signals All RESERVED lands must remain unconnected Connection of these lands to Vcc Vss Vr or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 4 for a land listing of the processor and the location of all RESERVED lands In a system level design on die termination has been included by the processor to allow signals to be terminated within the processor silicon Most unused GTL inputs should be left as no connects as GTL termination is provided on the processor silicon However see Table 8 for details on GTL signals that do not include on die termination Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the motherboard trace for front side bus signals For unused GTL input or I O signals use pull up resistors of the same value
63. amp vss FC38 DsTBNO amp vss D3 D1 vss LOCK BNR DRDY vss comps D13 vss pio pstapo vss D6 D5 vss D0 RS0 DBSY vss D50 COMPO vss po D8 amp vss DBIO D7 vss D4 D2 RS2 vss 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Datasheet AF AE AD AC x lt 5r 32 v qo U m m 43 44 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name P s eed Direction Land Name a dad Direction A3 LS Source Synch Input Output BNR C2 Common Clock Input Output A4 P6 Source Synch Input Output BPMO AJ2 Common Clock Input Output A5 M5 Source Synch Input Output BPM1 AJ1 Common Clock Input Output A6 L4 Source Synch Input Output BPM2 AD2 Common Clock Input Output A7 M4 Source Synch Input Output BPM3 AG2 Common Clock Input Output A8 R4 Source Synch Input Output BPM4 AF2 Common Clock Input Output A9 T5 Source Synch Input Output BPM5 AG3 Common Clock Input Output A10 U6 Source Synch Input Output BPRI G8 Common Clock Input All T4 Source Synch Input Output BRO F3 Common Clock Input Output A125 U5 Source Synch Input Output BSELO G29 Power Other Output A134 U4 Source Synch Input Output BSEL1 H30 Power Other Output Al4 V5 Source Synch Input Output BSEL2 G30 Power Other Output A15
64. and Minimum Ratings Electrical Specifications Symbol Parameter Min Max Unit Notes 2 Vcc Core voltage with respect to Vss 0 3 1 55 V Ver FSB termination voltage with 0 3 1 55 V _ respect to Vss T Processor case temperature ARE EE Se e P Chapter 5 Chapter 5 TsTORAGE Processor storage temperature 40 85 C 3 4 5 NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any tray or packaging 5 Failure to adhere to this specification can affect the long term reliability of the processor Datasheet Electrical Specifications 2 6 2 DC Voltage and Current Specification Table 5 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 2 VID Range VID 0 8500 1 5 V 3 Processor Number Vcc for Vcc 775 VR CONFIG 06
65. ation The second operating point consists of both a lower operating frequency and voltage When the TCC is activated the processor automatically transitions to the new frequency This transition occurs very rapidly on the order of 5 us During the frequency transition the processor is unable to service any bus requests and consequently all bus traffic is blocked Edge triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps to support Thermal Monitor 2 During the voltage change it will be necessary to transition through multiple VID codes to reach the target operating voltage Each step will likely be one VID table entry see Table 5 The processor continues to execute instructions during the voltage transition Operation at the lower voltage reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operating point Transition of t
66. atsink Attach Clip Assembiy The boxed processor thermal solution requires a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket The boxed processor will ship with the heatsink attach clip assembly Electrical Requirements Fan Heatsink Power Supply The processor s fan heatsink requires a 12 V power supply A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard The power cable connector and pinout are shown in Figure 26 Baseboards must provide a matched power header to support the boxed processor Table 33 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal which is an open collector output that pulses at a rate of 2 pulses per fan revolution A baseboard pull up resistor provides Voy to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL The processor s fan heatsink requires a constant 12 V supplied to pin 2 and does not support variable voltage control or 3 pin PWM control The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header identification a
67. be supplied with the boxed processor This chapter is particularly important for OEMs that manufacture baseboards for system integrators Unless otherwise noted all figures in this chapter are dimensioned in millimeters and inches in brackets Figure 22 shows a mechanical representation of a boxed processor Note Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designers responsibility to consider their proprietary cooling solution when designing to the required keep out zone on their system platforms and chassis Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 for further guidance Contact your local Intel Sales Representative for this document Figure 22 Mechanical Representation of the Boxed Processor NOTE The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Datasheet 91 m n tel Boxed Processor Specifications 7 1 Z L 1 Figure 23 92 Mechanical Specifications Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor The boxed processor will be shipped with an unattached fan heatsink Figure 22 shows a mechanical representation of the boxed processor Clearance is required around the fan heatsink to ensur
68. ble processor operation 21 m n tel Electrical Specifications Figure 2 2 6 4 2 7 22 Vcc Overshoot Example Waveform Example Overshoot Waveform VID 0 050 Vos o s gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID NOTES 1 Vos is measured overshoot voltage 2 Tos is measured time duration above VID Die Voltage Validation Overshoot events on processor must meet the specifications in Table 7 when measured across the VCC_SENSE and VSS_ SENSE lands Overshoot events that are lt 10 ns in duration may be ignored These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic GTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates Platforms implement a termination voltage level for GTL signals defined as V r Because platforms implement separate power planes for each processor and chipset separate Vcc and V supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases Speed enhancements to data and address busses have caused signal integrity considerations and platform design
69. c J vcc vcc vcc vec vec vec vec vec vec vec vec vec vec FC34 FC31 vcc H f Bse rcis vss vss vss vss vss vss vss vss vss vss vss vss FC33 FC32 G BSEL2 BSELO BCLK1 TESTHI4 TESTHIS TESTHI3 TESTHIG RESET D47 D44 DSTBN2 DSTBP24 D354 D36 D324 D31 amp F RSVD BCLKO VTT_SEL TESTHIO TesTHI2 TESTHI7 RSVD vss pas D41 vss D38 D374 vss D30 E FC26 vss vss vss vss Fco RsVD D45 amp paz vss D40 D39 vss D34 D334 D VIT VT VIT VTT VTI VT vss vccPLL pas vss pas DBI24 vss D49 RSVD VSS c VTT VTI VTT VIT VTT VTT vss V vss pss DBI3 vss D54 DSTBP34 vss D51 B VIT va VIT vt VIT VTT vss vssa pese pso vss D60 D57 vss D554 D534 A VIT VH VIT vT VIT VTT FC23 vccA D62 vss RsvD D61 amp vss D56 DSTBN3 vss 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 42 Datasheet Land Listing and Signal Descriptions Figure 14 land out Diagram Top View Right Side in 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VID_SELE vss wa VCC MB vss vcc NEC VSS NEC VEC VSS vag yee cr REGULATION REGULATION SENSE SENSE s VSS vec vss vec vec vss vec vec VID7 FC40 VID6 vss VID2 VIDO vss vec vss vec vec vss vec vec vss VID3 VIDI VIDS VRDSEL PROCHOT THERMDA vec vss vec vec vss vec vcc
70. capable of generating large current swings This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate Larger bulk storage Cpuuk such as electrolytic or aluminum polymer capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 5 Failure to do so can result in timing violations or reduced lifetime of the component 2 2 1 Vcc Decoupling Vcc regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications This includes bulk capacitance with low effective series resistance ESR to keep the voltage rail within specifications during large swings in load current In addition ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity Consult the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further information 2 2 2 V Decoupling Decoupling must be provided on the motherboard Decoupling solutions must be sized to meet the expected load To ensure compliance with the specifications various
71. ce Synch Input Output DRDY C1 Common Clock Input Output D33 E15 Source Synch Input Output DSTBNO C8 Source Synch Input Output D34 E16 Source Synch Input Output DSTBN1 G12 Source Synch Input Output D35 G18 Source Synch Input Output DSTBN2 G20 Source Synch Input Output D36 G17 Source Synch Input Output DSTBN3 A16 Source Synch Input Output D37 F17 Source Synch Input Output DSTBPO B9 Source Synch Input Output D38 F18 Source Synch Input Output DSTBP1 E12 Source Synch Input Output D39 E18 Source Synch Input Output DSTBP2 G19 Source Synch Input Output D40 E19 Source Synch Input Output DSTBP3 C17 Source Synch Input Output D41 F20 Source Synch Input Output FCO Y1 Power Other D42 E21 Source Synch Input Output FC3 J2 Power Other D43 F21 Source Synch Input Output FC4 T2 Power Other D44 G21 Source Synch Input Output FCS F2 Power Other D45 E22 Source Synch Input Output FC8 AK6 Power Other D46 D22 Source Synch Input Output FC10 E24 Power Other D47 G22 Source Synch Input Output FC15 H29 Power Other D48 D20 Source Synch Input Output FC17 Y3 Power Other D49 D17 Source Synch Input Output FC18 AE3 Power Other D50 A14 Source Synch Input Output FC20 ES Power Other D51 C15 Source Synch Input Output FC21 F6 Power Other D52 C14 Source Synch Input Output FC22 J3 Power Other D53 B15 Source Synch Input Output FC23 A24 Power Other D54 C18 Source Sy
72. ce Voltages uu aaa e eese e esee reme nene nemen nnns 24 11 GTL Signal Group DC Specifications 10 0 0 mmm kk kak kk kaka kk 25 12 Open Drain and TAP Output Signal Group DC Specifications 25 13 CMOS Signal Group DC Specifications a mme meme nenne 26 14 GTL Bus Voltage Definitions 0 cece meme menses nenne memes nnns 27 15 Core Frequency to FSB Multiplier Configuration sss 28 16 BSEL 2 0 Frequency Table for BCLK 1 0 sss 29 17 Front Side Bus Differential BCLK SpecificationsS eee mmm 29 18 Front Side Bus Differential BCLK Specifications nmm 31 19 PEC DG Electrical WIMMS raksesa rre Errare etes daya hana dad hl bom ccce ied deel Kar eed 32 20 Processor Loading SpecificationS ccc m memes emen 37 21 Package Handling Guidelines lak lak aka lak ka kalak kal wa kala adan ka a al aa a b a emen 37 22 Processor Materl als eet E a a sawa na naba nan t ela dak qasa basque payami pasqa Kai b bana 38 23 Alphabetical Land Assignments kk kk kk kak ka messen 44 24 Numerical Land Assignment ne ene kk kak kk kaka 54 25 Signal DescriptlOLi reote ak xana dar Di An Akan Daka b dikk xal n ha a r h Q n Rn ED UITERRE C EU FARE 64 26 Processor Thermal Specificati
73. ce should exist on systems in the event that a different voltage is required See Section 2 3 and Table 2 for more information The voltage specification requirements are measured across VCC SENSE and VSS SENSE lands at the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and I MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe Refer to Table 6 and Figure 1 for the minimum typical and maximum Vcc allowed for a given current The processor should not be subjected to any Vcc and I cc combination wherein Vcc exceeds Vcc max for a given current lec max Specification is based on the Vcc max loadline Refer to Figure 1 for details ri must pe provided via a separate voltage source and not be connected to Vcc This specification is measured at the lan Baseboard bandwidth is limited to 20 MHz 10 This is maximum total current drawn from V plane by only the processor This specification does not include the current coming from Ry through the signal line Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total I drawn by the system This parameter is based on design characterization and is not tested Datasheet 19 intel Table 6 20 Vcc Static and Transient Tolerance for Processors Electrical Specif
74. ch CMOS Input Output AJ 24 VSS Power Other AL3 VRDSEL Power Other AJ25 VCC Power Other AL4 VID5 Power Other Output AJ26 VCC Power Other AL5 VID1 Power Other Output AJ27 VSS Power Other AL6 VID3 Power Other Output AJ 28 VSS Power Other AL7 VSS Power Other AJ 29 VSS Power Other AL8 VCC Power Other AJ 30 VSS Power Other AL9 VCC Power Other AK1 THERMDC Power Other AL10 VSS Power Other AK2 VSS Power Other AL11 VCC Power Other AK3 ITP CLKO TAP Input AL12 VCC Power Other AK4 VID4 Power Other Output AL13 VSS Power Other AK5 VSS Power Other AL14 VCC Power Other AK6 FC8 Power Other AL15 VCC Power Other AK7 VSS Power Other AL16 VSS Power Other AK8 VCC Power Other AL17 VSS Power Other Datasheet Land Listing and Signal Descriptions intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Name sane Buter Direction tana Land Name signal Butten Direction Type Type AL18 VCC Power Other AM27 vss Power Other AL19 VCC Power Other AM28 vss Power Other AL20 vss Power Other AM29 VCC Power Other AL21 VCC Power Other AM30 VCC Power Other AL22 VCC Power Other AN1 vss Power Other AL23 VSS Power Other AN2 VSS Power Other AL24 VSS Power Other AN3 VCC_SENSE Power Other Output AL25 VCC Power Other AN4 VSS
75. chronous input TCK Input TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI Input TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for J TAG specification support TDO Output TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support TESTHI 13 0 Input TESTHI 13 0 must be connected to the processor s appropriate power source refer to VIT OUT LEFT and VIT OUT RIGHT signal description through a resistor for proper processor operation See Section 2 5 for more details THERMDA Other Thermal Diode Anode See Section 5 3 THERMDC Other Thermal Diode Cathode See Section 5 3 Datasheet Land Listing and Signal Descriptions Table 25 Datasheet intel Signal Description Sheet 8 of 9 Name THERMTRI P Type Output Description In the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature approximately 20 C above the maximum Tc Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program exec
76. criptions Signal Description Sheet 9 of 9 Name Type Description This input should be left as a no connect in order for the processor to VRDSEL Input boot The processor will not boot on legacy platforms where this land is connected to Vss VSS are the ground pins for the processor and should be connected VSS Input to the system ground plane VSSA Input VSSA is the isolated ground for internal PLLs VSS SENSE is an isolated low impedance connection to processor VSS SENSE Output core Vss It can be used to sense or measure ground near the silicon with little noise This land is provided as a voltage regulator feedback sense point for VSS MB Vss It is connected internally in the processor package to the sense REGULATION Output point land V27 as described in the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket VIT Input Miscellaneous voltage supply VIT OUT LEFT The VIT OUT LEFT and VIT OUT RIGHT signals are included to Output provide a voltage supply for some signals that require termination to VTT OUT RIGHT V on the motherboard The VTT_SEL signal is used to select the correct V voltage level for VTT SEL Output the processor This land is connected internally in the package to Vrr Datasheet m e Thermal Specifications and Design Considerations n tel 5 5 1 Note 5 1 1 Datasheet Thermal Specifications and
77. d to in these specifications is the instantaneous Vr 4 Viu is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 5 Vin and Voy may experience excursions above Vr However input signal drivers must comply with the signal quality specifications Leakage to Vss with land held at V Leakage to V with land held at 300 mV e Table 12 Open Drain and TAP Output Signal Group DC Specifications Symbol Parameter Min Max Unit Notes VoL Output Low Voltage 0 0 20 V Vou Output High Voltage Vr 0 05 Vm 0 05 V 2 l oL Output Low Current 16 50 mA 2 lio Output Leakage Current N A 200 HA a NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vox is determined by the value of the external pull up resister to Vr 3 Measured at Vy 0 2 4 For Vin between 0 and Voy Datasheet 25 intel Electrical Specifications CMOS Signal Group DC Specifications Symbol Parameter Min Max Unit Notes ViL Input Low Voltage 0 10 Vr 0 30 V 2 3 Vi Input High Voltage Vr 0 70 Vm 0 10 V 49 VoL Output Low Voltage 0 10 Vr 0 10 V 3 Vou Output High Voltage 0 90 Vz V 0 10 V 5 3 loL Output Low Current 1 70 4 70 mA 3 7 lon Output High Current 1 70 4 70 mA NA lu Input Leakage Current N A 100 HA 8 lio Output Leakage Current N
78. ded Stop Grant state Enhanced Intel SpeedStep Technology The processor supports Enhanced Intel SpeedStep technology This technology enables the processor to switch between multiple frequency and voltage points which results in platform power savings Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform Switching between voltage frequency states is software controlled Not all processors are capable of supporting Enhanced Intel SpeedStep Technology More details on which processor frequencies will support this feature will be provided in future releases of the Intel Celeron Dual Core Processor E1000 series Specification Update when available Enhanced Intel SpeedStep Technology creates processor performance states P states or voltage frequency operating points P states are lower power capability states within the Normal state as shown in Figure 21 Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system The processor has hardware logic that coordinates the requested voltage VID between the processor cores The highest voltage that is requested for either of the processor cores is select
79. ding termination recommendations refer to Section 2 8 2 COMP8 COMP 3 0 Analog COMP 3 0 and COMP8 must be terminated to Vss on the system board using precision resistors Datasheet 65 intel Table 25 66 Land Listing and Signal Descriptions Signal Description Sheet 3 of 9 Name Type Description D 63 0 DBI 3 0 Input Output Input Output D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor FSB agents and must connect the appropriate pins lands on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DBI Quad Pumped Signal Groups DSTBN DSTBP DBI Data Group D 15 0 D 31 16 D 47 32 0 1 2 D 63 48 3 WN e O Furthermore the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the
80. duce system level power consumption Systems must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the IA32 CLOCK MODULATION MSR is set to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same IA32 CLOCK MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 596 on 87 596 off to 87 596 on 12 596 off in 12 596 increments On Demand mode may be used in conjunction with the Thermal Monitor however if the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode Datasheet m e Thermal Specifications and Design Considerations n tel 5 2 4 5 2 5 Datasheet PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor core temperature has reached its maximum operating temperature If the Thermal Monitor is enabled note that the Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT As an output PROCHOT P
81. e Notes 0 00 VL Input Low Voltage 0 150 0 N A V 3 0 70 Vu Input High Voltage 0 660 0 0 850 V 3 Veco ute Crossing 0 250 N A 0 550 v 34 23 Point Relative Crossing 0 250 0 550 4 3 5 Vcrossirel point 0 5 VHavg 0 700 N A 0 5 Vnavg 0 700 4 Range of Crossing AVcRoss Pointe N A N A 0 140 V 3 4 Vos Overshoot N A N A Vu 0 3 V 3 6 E V rn P nYFT n Vus Undershoot 0 300 N A N A V 3 VRBM Ringback Margin 0 200 N A N A V 3 8 Vim Threshold Region VcRoss 0 100 N A Vcross 0 100 V 3 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLKO equals the falling edge of BCLK1 3 The crossing point must meet the absolute and relative crossing point specifications simultaneously 4 Vuavg is the statistical average of the V measured by the oscilloscope 5 Vuavg Can be measured directly using Vtop on Agilent oscilloscopes and High on Tektronix oscilloscopes 6 vershoot is defined as the absolute value of the maximum voltage 7 Undershoot is defined as the absolute value of the minimum voltage 8 Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback 9 Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver swi
82. e 18 5 4 1 1 82 Platform Environment Control I nterface PECI Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components It uses a single wire thus alleviating routing congestion issues Figure 18 shows an example of the PECI topology in a system PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices Also data transfer speeds across the PECI interface are negotiable within a wide range 2 Kbps to 2 Mbps The PECI interface on the processor is disabled by default and must be enabled through BIOS Processor PECI Topology PECI Host Land G5 c D in 0 Controller oman Key Difference with Legacy Diode Based Thermal Management Fan speed control solutions based on PECI uses a Tcontro Value stored in the processor IA32 TEMPERATURE TARGET MSR The TcontroL MSR uses the same offset temperature format as PECI though it contains no sign bit Thermal management devices should infer the TcowrRo value as negative Thermal management algorithms should use the relative temperature value delivered over PECI in conjunction with the TcoNTROL MSR value to control or optimize fan speeds Figure 19 shows a conceptual fan control diagram using PECI temperatures The relative temperature value reported over PECI represents the delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT assertions As the t
83. e Thermal Design Power TDP value listed per frequency in Table 26 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Platform Environment Control Interface PECI bus as described in Section 5 4 1 1 The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT see Section 5 2 Systems that implement fan speed control must be designed to take these conditions in to account Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications To determine a processor s case temperature specification based on the thermal profile it is necessary to accurately measure processor power dissipation Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 and the Proce
84. e unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 23 Side View and Figure 24 Top View The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs Airspace requirements are shown in Figure 28 and Figure 29 Note that some figures have centerlines shown marked with alphabetic designations to clarify relative dimensioning Space Requirements for the Boxed Processor Side View 95 0 K 74 A 81 3 3 2 10 0 25 0 o 39 0 98 v 4 Boxed Proc SideView Datasheet e Boxed Processor Specifications n tel Figure 24 Space Requirements for the Boxed Processor Top View NOTES 1 Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation Figure 25 Space Requirements for the Boxed Processor Overall View Datasheet 93 m n tel Boxed Processor Specifications 7 2 7 2 1 94 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 for details on the processor weight and heatsink requirements Boxed Processor Retention Mechanism and He
85. ect the appropriate pins lands of all processor FSB agents DRDY Input Output DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be de asserted to insert idle clocks This signal must connect the appropriate pins lands of all processor FSB agents DSTBN 3 0 Input Output DSTBN 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBNO D 31 16 DBI1 DSTBN1 D 47 32 DBI2 DSTBN2 D 63 48 DBI3 DSTBN3 DSTBP 3 0 Input Output DSTBP 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48 DBI3 DSTBP3 FCx FERR PBE Other Output FC signals are signals that are available for compatibility with other processors FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an asserti
86. ed for that processor package Note that the front side bus is not altered only the internal core frequency is changed To run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep Technology Multiple voltage frequency operating points provide optimal performance at reduced power consumption Voltage frequency selection is software controlled by writing to processor MSR s Model Specific Registers thus eliminating chipset dependency f the target frequency is higher than the current frequency Vcc is incriminated in steps 12 5 mV by placing a new value on the VID signals and the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded If the target frequency is lower than the current frequency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals S 89 90 Features Datasheet m e Boxed Processor Specifications n tel 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from baseboards and standard components The boxed processor will be supplied with a cooling solution This chapter documents baseboard and system requirements for the cooling solution that will
87. ed ratios The processor uses a differential clocking implementation For more information on the processor clocking contact your Intel field representative Platforms using a CK505 Clock Synthesizer Driver should comply with the specifications in Section 2 8 4 Platforms using a CK410 Clock Synthesizer Driver should comply with the specifications in Section 2 8 5 Core Frequency to FSB Multiplier Configuration Multiplication of System Core Core Frequency Notes 2 Frequency to FSB Frequency 200 MHz BCLK 800 MHz FSB 1 6 1 20 GHz 1 7 1 40 GHz 1 8 1 60 GHz 1 9 1 80 GHz 1 10 2 GHz 1 11 2 2 GHz 1 12 2 4 GHz NOTES 1 Individual processors operate only at or below the rated frequency _ 2 Listed frequencies are not necessarily committed production frequencies FSB Frequency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 Table 16 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency The Intel Celeron Dual Core processor E1000 series operates at a 800 MHz FSB frequency selected by a 200 MHz BCLK 1 0 frequency Datasheet Electrical Specifications n tel Table 16 BSEL 2 0 Frequency Table for BCLK 1 0
88. ed together Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket The package components shown in Figure 7 include the following Integrated Heat Spreader IHS Thermal Interface Material TI M Processor core die Package substrate Capacitors Processor Package Assembly Sketch TIM Core die IHS Substrate io o Capacitors LGA775 Socket 4 Syste Board Processor t Pkg_Assembly 775 NOTE 1 Socket and system board are included for reference and are not part of processor package Package Mechanical Drawing The package mechanical drawings are shown in Figure 8 and Figure 9 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include Package reference with tolerances total height length width etc e IHS parallelism and tilt Land dimensions Top side and back side component keep out dimensions Reference datums All drawing dimensions are in mm in Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines see Section 1 2 33 intel Figure 8 Processor Package Drawing Sheet 1 of 3 e uc ua l ea Package Mechanical Specifications HEV C88285 7 Y E T 000000
89. ee emnes 73 5 1 1 Thermal Spe cificationsS eec nts snina niana bia k ka IU Gd Nd kaq ina 73 5 12 Thermal Metrology zr sua tp ere ARE PRERTREX ER kab n n kn Ru Y ae k sika D n 76 5 2 Processor Thermal FeatureS sssssssrassrssrntrtrstrnrtrne memes seme see memes ens 76 5 2 1 Thermal MONO u nee hmc b ln reni led n a danke pone niente wi er n d y eam 76 Datasheet 3 ntel 5 2 2 Thermal Monitor 2 inco RES RO iM iain MIROR A 77 5 233 On Demand Mode u u u uuu a adan n aa nma nak n r an n n ko Dan R Daka ba k qa kenan d DA 78 5 24 PROCHOT Signal i u meyle en DTE xara w D na I EFE NN R T da W daa n ra k Wik 79 5 2 5 THERMTRIP Sigrial s tiae serda nayn kanal na Wl Wb a na n b h n ada n ner E RI land n 79 5 3 WherMal D Www mm _ vm zz 80 5 4 Platform Environment Control Interface PECI csesssssse Hee kk 82 5 4 1 Jntrodu ctlOh eco oni ceci bane nane na ever bna l bedin bena Une dine dug 82 5 4 1 1 Key Difference with Legacy Diode Based Thermal Management 82 5 4 2 PECI Specifications 3s as cul k n hier eei eae Locis bala nena nen en riz ba more Ae du ears 84 5 4 2 1 PECI Device AQ Q SS am uuu eoe c aia nce bL ob Vas 84 5 4 2 2 PECI Command Support r kk kk kk kk kak ka 84 5 4 2 3 PECI Fault Handling Requirements eeen 84 5 4 2 4 PECI GetTempO Error Code Support
90. emperature approaches TCC activation the PECI value approaches zero TCC activates at a PECI count of zero Datasheet m e Thermal Specifications and Design Considerations n tel Figure 19 Figure 20 Datasheet Conceptual Fan Control on PECI Based Platforms TcoNTROL TCC Activation Setting Temperature Max PECI 0 Fan Speed RPM PECI 10 Temperature Note Not intended to depict actual implementation Conceptual Fan Control on Thermal Diode Based Platforms TcontroL TCC Activation Setting Temperature l I I l I I o Max Toiope 90 C I Fan Speed Torone 80 C RPM I I Tpiopz 70 C Temperature 83 n tel Thermal Specifications and Design Considerations 5 4 2 5 4 2 1 5 4 2 2 5 4 2 3 5 4 2 4 Table 31 84 PECI Specifications PECI Device Address The PECI device address for the socket is 30h For more information on PECI domains refer to the Platform Environment Control Interface Specification PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification Refer to this document for details on supported PECI command function and codes PECI Fault Handling Requirements PECI is largely a fault tolerant interface including noise immunity and error checking improvements over other comparable industry standard interfaces The PECI client is a
91. er VSS R23 Power Other VIT B25 Power Other VSS R24 Power Other VIT B26 Power Other VSS R25 Power Other VIT B27 Power Other VSS R26 Power Other VIT B28 Power Other VSS R27 Power Other VIT B29 Power Other VSS R28 Power Other VIT B30 Power Other VSS R29 Power Other VIT C25 Power Other VSS R30 Power Other VIT C26 Power Other VSS R5 Power Other VIT C27 Power Other VSS R7 Power Other VIT C28 Power Other VSS T3 Power Other VIT C29 Power Other VSS T6 Power Other VIT C30 Power Other VSS T7 Power Other VTT D25 Power Other VSS U7 Power Other VTT D26 Power Other VSS V23 Power Other VTT D27 Power Other VSS V24 Power Other VTT D28 Power Other VSS V25 Power Other VIT D29 Power Other VSS V26 Power Other VTT D30 Power Other vss V27 Power Other VIT OUT LEFT J1 Power Other Output VSS V28 Power Other VTT_OUT_RIG VSS V29 Power Other HTT AA1 Power Other Output vss v3 Power Other VTT_SEL F27 Power Other Output VSS v30 Power Other VSS V6 Power Other VSS V7 Power Other VSS WA Power Other Datasheet 53 54 intel Land Listing and Signal Descriptions Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction Lana Land Name Signal Buffer Direction Type Type A2 vss Power Other B11 vss Power Other A3 RS2 Common
92. escription A 35 3 Input Output A 35 3 Address define a 238 byte physical memory address space In sub phase 1 of the address phase these signals transmit the address of a transaction In sub phase 2 these signals transmit transaction type information These signals must connect the appropriate pins lands of all agents on the processor FSB A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processor samples a subset of the A 35 3 signals to determine power on configuration See Section 6 1 for more details A20M Input If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 signals All bus agents observe the ADS activation to begin protocol checking address decode inte
93. essor Retention Mechanism and Heatsink Attach Clip Assembly idest ester dudes d enu bxn 94 7 2 Electrical Requirements rere endo n ba na Wa na kaba yan n orgy eben e beret d W n n Fa doe 94 7 2 1 Fan Heatsink Power Supply rr kk kak k kaka 94 4 3 Thermal Specification essee er ebrei ree vig Deben o d n Pee dx VE daba gadan W4 96 7 3 1 Boxed Processor Cooling Requirements kk ka 96 7 3 2 Fan Speed Control Operation Intel Pentium Dual Core Desktop Processor E2 T60 ker amu PR Sak naa A uc E IR Rd Sasan tend A pus ELO Ed oc 98 Debug Tools Specifications LL kk meme nemen nens 101 8 1 Logic Analyzer Interface LAI sss nemen nnn nnn 101 8 1 1 Mechanical Considerations u u uuu aaa sana sasawa maswasyawawaukananwasaaapawawhiqa 101 8 1 2 Electrical Considerations u uu aka kbk ka kl ka khal ala R n Wa Wa Sk Aa W n a kayi h ua 101 Datasheet Figures 1 Vcc Static and Transient Tolerance for Processors r e 21 2 Vcc Overshoot Example Waveform Hmmm meme eene mene 22 3 Differential Clock Waveform ici retten rent kann b n p Din V n Ar h n Ain ERR kud nak W y Aw am 30 4 Differential Clock Crosspoint Specification kk kk k 30 5 Differential Measurements u uuu u uu a aus nal emen nensem sie sese e eme ad Kira Wan sens 30 6 Differential Clock Crosspoint Specification
94. fications n tel Figure 28 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 1 view R55 2 2 17 Figure 29 Boxed Processor Fan Heatsink Airspace Keepout Requirements Side 2 View Datasheet 97 m n tel Boxed Processor Specifications 7 3 2 Figure 30 98 Fan Speed Control Operation If the boxed processor fan heatsink 4 pin connector is connected to a 3 pin motherboard header it will operate as follows The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures This allows the processor fan to operate at a lower speed and noise level while internal chassis temperatures are low If internal chassis temperature increases beyond a lower set point the fan speed will rise linearly with the internal temperature until the higher set point is reached At that point the fan speed is at its maximum As fan speed increases so does fan noise levels Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler than a lower set point These set points represented in Figure 30 and Table 34 can vary by a few degrees from fan heatsink to fan heatsink The internal chassis temperature should be kept below 38 9C Meeting the processor s temperature specification see Chapter 5 is the responsibility of the system integrator The motherboard must supply a constant 12 V to the processor s power
95. formance Power Management capabilities System Management mode Multiple low power states 8 way cache associativity provides improved cache hit rate on load store operations 775 land Package The Intel Celeron Dual Core processor E1000 series deliver Intel s advanced powerful processors for desktop PCs The processor is designed to deliver performance across applications and usages where end users can truly appreciate and experience the performance These applications include Internet audio and streaming video image processing video content creation speech 3D CAD games multimedia and multitasking user environments Intel 64 architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture The processor supporting Enhanced Intel SpeedStep technology allows tradeoffs to be made between performance and power consumption The Intel Celeron Dual Core processor E1000 series also includes the Execute Disable Bit capability This feature combined with a supported operating system allows memory to be marked as executable or non executable Datasheet Revision History Revision Number Description Date 001 Initial release January 2008 ss Datasheet Introduction 1 Note Note 1 1 Datasheet intel Introduction The Intel Celeron Dual Core processor E1000 series combines the performance of the
96. free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Functional operation Refers to normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system See the Intel Architecture Software Developer s Manual for more detailed information Intel 64 Architecture An enhancement to Intel s A 32 architecture allowing the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture Further details on Intel 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at http developer intel com technology 64bitextensions
97. h Input Output D1 RESERVED Ell vss Power Other D2 ADS Common Clock Input Output E12 DSTBP1 Source Synch Input Output D3 vss Power Other E13 D26 Source Synch Input Output D4 HIT Common Clock Input Output E14 vss Power Other D5 VSS Power Other E15 D33 Source Synch Input Output D6 VSS Power Other E16 D34 Source Synch Input Output D7 D20 Source Synch Input Output E17 VSS Power Other D8 D12 Source Synch Input Output E18 D39 Source Synch Input Output D9 VSS Power Other E19 D40 Source Synch Input Output D10 D22 Source Synch Input Output E20 VSS Power Other D11 D15 Source Synch Input Output E21 D42 Source Synch Input Output D12 VSS Power Other E22 D45 Source Synch Input Output D13 D25 Source Synch Input Output E23 RESERVED D14 RESERVED E24 FC10 Power Other D15 VSS Power Other E25 VSS Power Other D16 RESERVED E26 VSS Power Other D17 D49 Source Synch Input Output E27 VSS Power Other D18 VSS Power Other E28 VSS Power Other D19 DBI2 Source Synch Input Output E29 FC26 Power Other D20 D48 Source Synch Input Output F2 FCS Power Other D21 VSS Power Other F3 BRO Common Clock Input Output D22 D46 Source Synch Input Output F4 vss Power Other D23 VCCPLL Power Other F5 RS1 Common Clock Input D24 VSS Power Other F6 FC21 Power Other D25 VIT Power Other F7 VSS Power Other D26 VTT Power Other F8 D17 Source Synch Input Output D27 VIT Power Other F9 D18 Source Synch Input Output D28 VIT Power Other F10 VSS Power Other 55
98. he VID code will occur first to ensure proper operation once the processor reaches its normal operating frequency Refer to Figure 17 for an illustration of this ordering 77 n tel Thermal Specifications and Design Considerations Figure 17 5 2 3 78 Thermal Monitor 2 Frequency and Voltage Ordering Temperature Frequency PROCHOT The PROCHOT signal is asserted when a high temperature situation is detected regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode The Thermal Monitor TCC however can be activated through the use of the on demand mode On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems using the processor must not rely on software usage of this mechanism to limit the processor temperature The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor and Thermal Monitor 2 features On Demand mode is intended as a means to re
99. header to ensure proper operation of the variable speed fan for the boxed processor Refer to Table 34 for the specific requirements Boxed Processor Fan Heatsink Set Points Higher Set Point Highest Noise Level Increasing Fan Speed amp Noise Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature Degrees C Datasheet Boxed Processor Specifications n tel Table 34 Datasheet Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point C Boxed Processor Fan Speed Notes When the internal chassis temperature is below or equal to this set point the fan operates at its lowest speed 1 Recommended maximum internal chassis temperature for nominal operating environment X lt 30 When the internal chassis temperature is at this point the fan operates between its lowest and highest speeds Recommended maximum internal chassis temperature for worst case operating environment 2238 When the internal chassis temperature is above or equal to _ B this set point the fan operates at its highest speed NOTES 1 Set point variance is approximately 1 C from fan heatsink to fan heatsink If the boxed processor fan heatsink 4 pin connector is connected to a 4 pin motherboard header and the motherboard is designed with a fan speed controller with PWM output CONTROL see Table 33 and remote thermal diode measurement capabili
100. heet 51 52 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name p z Sa Direction Land Name Te Direction VSS B24 Power Other VSS H12 Power Other VSS B5 Power Other VSS H13 Power Other VSS B8 Power Other vss H14 Power Other VSS C10 Power Other vss H17 Power Other VSS C13 Power Other VSS H18 Power Other VSS C16 Power Other VSS H19 Power Other VSS C19 Power Other vss H20 Power Other VSS C22 Power Other VSS H21 Power Other VSS C24 Power Other VSS H22 Power Other VSS C4 Power Other VSS H23 Power Other VSS C7 Power Other VSS H24 Power Other VSS D12 Power Other VSS H25 Power Other VSS D15 Power Other VSS H26 Power Other VSS D18 Power Other VSS H27 Power Other VSS D21 Power Other VSS H28 Power Other VSS D24 Power Other VSS H3 Power Other VSS D3 Power Other VSS H6 Power Other VSS D5 Power Other VSS H7 Power Other VSS D6 Power Other VSS H8 Power Other VSS D9 Power Other VSS H9 Power Other VSS E11 Power Other VSS J4 Power Other VSS E14 Power Other VSS J7 Power Other VSS E17 Power Other VSS K2 Power Other VSS E2 Power Other VSS K5 Power Other VSS E20 Power Other VSS K7 Power Other VSS E25 Power Other VSS L23 Power Other VSS E26 Power Other VSS L24 Power Other VSS E27 P
101. her VSS AA28 Power Other VSS AF17 Power Other VSS AA29 Power Other VSS AF20 Power Other VSS AA3 Power Other VSS AF23 Power Other VSS AA30 Power Other VSS AF24 Power Other VSS AA6 Power Other VSS AF25 Power Other VSS AA7 Power Other VSS AF26 Power Other VSS AB1 Power Other VSS AF27 Power Other VSS AB23 Power Other VSS AF28 Power Other VSS AB24 Power Other VSS AF29 Power Other VSS AB25 Power Other VSS AF3 Power Other VSS AB26 Power Other VSS AF30 Power Other VSS AB27 Power Other VSS AF6 Power Other VSS AB28 Power Other VSS AF7 Power Other VSS AB29 Power Other VSS AG10 Power Other VSS AB30 Power Other VSS AG13 Power Other VSS AB7 Power Other VSS AG16 Power Other VSS AC3 Power Other VSS AG17 Power Other VSS AC6 Power Other VSS AG20 Power Other Datasheet Land Listing and Signal Descriptions intel Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name cong bx nd Direction Land Name 23 s Direction VSS AG23 Power Other VSS AK5 Power Other VSS AG24 Power Other VSS AK7 Power Other VSS AG7 Power Other vss AL10 Power Other VSS AH1 Power Other vss AL13 Power Other VSS AH10 Power Other vss AL16 Power Other VSS AH13 Power Other vss AL17 Power Other VSS AH16 Power Other VSS A
102. ications Voltage Deviation from VID Setting V 2 3 4 Icc A Maximum Voltage Typical Voltage Minimum Voltage 1 30 mo 1 425 mo 1 55 mo 0 000 0 019 0 038 5 0 007 0 026 0 046 10 0 013 0 033 0 054 15 0 020 0 040 0 061 20 0 026 0 048 0 069 25 0 033 0 055 0 077 30 0 039 0 062 0 085 35 0 046 0 069 0 092 40 0 052 0 076 0 100 45 0 059 0 083 0 108 50 0 065 0 090 0 116 55 0 072 0 097 0 123 60 0 078 0 105 0 131 65 0 085 0 112 0 139 70 0 091 0 119 0 147 75 0 098 0 126 0 154 NOTES 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 6 3 2 This table is intended to aid in reading discrete points on Figure 1 3 The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket implementation details 4 Adherence to this loadline specification is required to ensure reliable processor operation loadline guidelines and VR Datasheet m e Electrical Specifications n tel Figure 1 2 6 3 Table 7 Datasheet Vcc Static and Transient Tolerance for Processors Icc A 0 10
103. ill keep IERR asserted until the assertion of RESET This signal does not have on die termination Refer to Section 2 6 2 for termination requirements IGNNE Input IGNNE Ignore Numeric Error is asserted to the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If GNNE is de asserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error GNNE has no effect when the NE bit in control register 0 CRO is set IGNNEZ is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT Input INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins lands of all processor FSB agents ITP CLK 1 0 Input ITP CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board ITP CLK 1 0 are used as BCLK 1 0 references for a debug p
104. information 2 7 2 CMOS and Open Drain Signals reference voltage See Table 12 for more Legacy input signals such as A20M IGNNEZ INIT SMI and STPCLK use CMOS input buffers All of the CMOS and Open Drain signals are required to be asserted de asserted for at least four BCLKs in order for the processor to recognize the proper signal state See Section 2 7 3 for the DC specifications See Section 6 2 for additional timing requirements for entering and leaving the low power states 24 Datasheet m e Electrical Specifications n tel 2 7 3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless otherwise stated All specifications apply to all frequencies and cache sizes unless otherwise stated Table 11 GTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes V L Input Low Voltage 0 10 GTLREF 0 10 V 2 3 Vin Input High Voltage GTLREF 0 10 Vr 0 10 V 4 9 3 Vou Output High Voltage Vr 0 10 Vr V 5 3 lot Output Low Current N A Rr EU rae T A z lu Input Leakage Current N A 100 HA 6 lio Output Leakage Current N A 100 HA 7 Ron Buffer On Resistance 10 13 Q NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vi is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3 The V referre
105. it F SCALE 60 1 DETAIL DEPARTMENT ATD DETAIL D SCALE 20 1 NU 000000000000000000000000000 0000 000000000000000000000000000000000 000000000000000000000000000000000 00000000000000000 0000000000000000 000000000000000000000000000000000 000000000000000000000000000000000 O00000000000000060000000000000000 0000000000000000090000000000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 99099099990 000000000 000000000 O00000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 5 j 000000000 000000000 000000000 0000000000000000060000000000000000 000000000000000000000000000000000 000000000000000000000000000000000 000000000000000060000000000000000 000000000000000060000000000000000 000000000000000000000000000000000 00000000000000000900000000000000000 000000000000000009000000000 QOO VS A COMMENTS BOTTOM VIEW MAX MILLIMETERS WIN RI 4 BASIC RI 4 BASIC 0 2 BASIC 6 215 BASIC 0 2 BASIC 6 215 BASIC SYMBOL Ri id T T Y C l he Datasheet 35 intel Figure 10 Processor Package Drawing Sheet 3 of 3 e uL ul l a o Package Mechanical Specifications 3p C8828
106. lock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor number for details Intel 64 requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 Processor will not operate including 32 bit operation without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations See http www intel com technology intel64 index htm for more information including details on which processors support Intel 64 or consult with your system vendor for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality The Intel Celeron Dual Core processor E1000 series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Not all specified units of this processor support Thermal Monitor 2 Enhanced HALT State and Enhanced Intel SpeedStep Technology See the Processor Spec Finder at http processorfinder intel com or contact your Intel representative for more inf
107. methods to become even more critical than with previous processor families The GTL inputs require a reference voltage GTLREF which is used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF must be generated on the motherboard see Table 14 for GTLREF specifications Termination resistors R77 for GTL signals are provided on the processor silicon and are terminated to Vy Intel chipsets will also provide on die termination thus eliminating the need to terminate the bus on the motherboard for most GTL signals Datasheet Electrical Specifications intel 2 7 1 FSB Signal Groups The front side bus signals have been combined into groups by buffer type GTL input signals have differential input buffers which use GTLREF 1 0 as a reference level In this document the term GTL Input refers to the GTL input group as well as the GTL I O group when receiving Similarly GTL Output refers to the GTL output group as well as the GTL I O group when driving With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals which are dependent upon the rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asychronous signals
108. n that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Refer to the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for details on implementing the bi directional PROCHOT feature THERMTRI P Signal Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 25 At this point the FSB signal THERMTRIP will go active and stay active as described in Table 25 THERMTRIP activation is independent of processor activity and does not generate any bus cycles If THERMTRIP is asserted processor core voltage Vcc must be removed within the timeframe defined in Table 11 79 Table 28 80 Thermal Specifications and Design Considerations Thermal Diode The processor incorporates an on die PNP transistor where the base emitter junction is used as a thermal diode with its collector shorted to ground A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control Table 28 Table 29 and Table 30 provide the diode parameter and interface specifications Two different sets of diode parameters are listed in Table 28 and Table
109. nately turning the clocks off and on at a duty cycle specific to the processor typically 30 5096 Clocks often will not be off for more than 3 0 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable An Datasheet m e Thermal Specifications and Design Considerations n tel 5 2 2 Datasheet under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and in some cases may result in a Tc that exceeds the specified maximum temperature and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling
110. nch Input Output FC26 E29 Power Other D55 B16 Source Synch Input Output FC27 G1 Power Other D56 A17 Source Synch Input Output FC28 U1 Power Other D57 B18 Source Synch Input Output FC29 U2 Power Other D58 C21 Source Synch Input Output FC30 U3 Power Other D59 B21 Source Synch Input Output FC31 J16 Power Other D60 B19 Source Synch Input Output FC32 H15 Power Other 45 46 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name Land Signal Buffer Direction Land Name Land Signal Buffer Direction Type Type FC33 H16 Power Other RESERVED D16 FC34 J17 Power Other RESERVED E23 FC35 H4 Power Other RESERVED E6 FC36 AD3 Power Other RESERVED E7 FC37 AB3 Power Other RESERVED F23 FC38 G10 Power Other RESERVED F29 FC38 C9 Power Other RESERVED G6 FC39 AA2 Power Other RESERVED N4 FC40 AM6 Power Other RESERVED N5 FERR PBE R3 Asynch CMOS Output RESERVED P5 GTLREFO H1 Power Other Input RESERVED v2 GTLREF1 H2 Power Other Input RESET G23 Common Clock Input HIT D4 Common Clock Input Output RSO B3 Common Clock Input HITM E4 Common Clock Input Output RS1 F5 Common Clock Input ERR AB2 Asynch CMOS Output RS2 A3 Common Clock Input IGNNE
111. nd location should be documented in the platform documentation or on the system board itself Figure 27 shows the location of the fan power connector relative to the processor socket The baseboard power header should be positioned within 110 mm 4 33 inches from the center of the processor socket Datasheet Boxed Processor Specifications intel Figure 26 Boxed Processor Fan Heatsink Power Cable Connector Description GND 12 V SENSE CONTROL G N Straight square pin 4 pin terminal housing with polarizing ribs and friction locking ramp 0 100 pitch 0 025 square pin width Match with straight pin friction lock header on mainboard Table 33 Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit Notes 12 V 12 volt fan power supply 11 4 12 12 6 V IC Maximum fan steady state current draw 1 2 A Average fan steady state current draw 0 5 A _ Maximum fan start up current draw 2 2 A Fan start up current draw maximum 1 0 B Second duration pulses per SENSE SENSE frequency 2 fan 1 revolution CONTROL 21 25 28 kHz 2 3 NOTES 1 Baseboard should pull this pin up to 5V with a resistor 2 Open drain type pulse width modulated 3 Fan will have pull up resistor for this signal to maximum of 5 25 V Datasheet 95 m n tel Boxed Processor Specifications Figure 27 7 3 ZG
112. nput AE24 VSS Power Other AD2 BPM2 Common Clock Input Output AE25 VSS Power Other AD3 FC36 Power Other AE26 VSS Power Other AD4 VSS Power Other AE27 VSS Power Other AD5 ADSTB1 Source Synch Input Output AE28 VSS Power Other AD6 A22 Source Synch Input Output AE29 VSS Power Other AD7 VSS Power Other AE30 VSS Power Other AD8 VCC Power Other AF1 TDO TAP Output AD23 VCC Power Other AF2 BPM4 Common Clock Input Output AD24 VCC Power Other AF3 VSS Power Other AD25 VCC Power Other AF4 A28 Source Synch Input Output AD26 VCC Power Other AF5 A27 Source Synch Input Output AD27 VCC Power Other AF6 VSS Power Other AD28 VCC Power Other AF7 VSS Power Other AD29 VCC Power Other AF8 VCC Power Other AD30 VCC Power Other AF9 VCC Power Other AE1 TCK TAP Input AF10 VSS Power Other AE2 VSS Power Other AF11 VCC Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment rana Land Name Direction sene Land Name Nu e Direction AF12 VCC Power Other AG21 VCC Power Other AF13 VSS Power Other AG22 VCC Power Other AF14 VCC Power Other AG23 VSS Power Other AF15 VCC Power Other AG24 VSS Power Other AF16 VSS Power Other AG25 VCC Power Other AF17 VSS Power Other AG26 VCC Power Other AF18 VCC Power Other AG27 VCC Power Other AF19 VCC Power Other
113. of up to 6 4 GB s Intel will enable support components for the processor including heatsink heatsink retention mechanism and socket Manufacturability is a high priority hence mechanical assembly may be completed from the top of the baseboard and should not require any special tooling The processor includes an address bus power down capability which removes power from the address and data signals when the FSB is not in use This feature is always enabled on the processor Terminology A 3t symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Front Side Bus refers to the interface between the processor and system core logic a k a the chipset components The FSB is a multiprocessing interface to processors memory and I O 10 intel 1 1 1 Introduction Processor Terminology Commonly used terms are explained here for clarification Intel Celeron Dual Core processor E1000 series
114. oftware Developer s Manual Volume 1 Basic Architecture Intel 64 and IA 32 Architecture Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architecture Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architecture Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architecture Software Developer s Manual Volume 3B System Programming Guide http www intel com products processor manuals 5 11 12 Introduction Datasheet m e Electrical Specifications n tel 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals DC electrical characteristics are provided 2 1 Power and Ground Lands The processor has VCC power VIT and VSS ground inputs for on chip power distribution All power lands must be connected to Vcc while all VSS lands must be connected to a system ground plane The processor VCC lands must be supplied the voltage determined by the Voltage I Dentification VID lands The signals denoted as Vr provide termination for the front side bus and power to the I O buffers A separate supply must be implemented for these lands that meets the Vr specifications outlined in Table 5 2 2 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is
115. on of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to volume 3 of the Intel Architecture Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note GTLREF 1 0 Input GTLREF 1 0 determine the signal reference level for GTL input signals GTLREF is used by the GTL receivers to determine if a signal is a logical 0 or logical 1 67 Table 25 68 intel Land Listing and Signal Descriptions Signal Description Sheet 5 of 9 Name Type Description HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR Output IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor w
116. ons kh hk k hlkk kk kk kk kk kk eene 74 27 Thenmal PhOfll yiy ya nezan kana aer Kala man nara ova pa koa dadiya n hon D a ren Ra San n E bna EE an Mm REIHE UIS 75 28 Thermal Diode Parameters using Diode Model cssssssssseee menn 80 29 Thermal Diode Parameters using Transistor Model sss 81 30 Thermal Diode Interface ooi ien eese heccre been PT ee let ed rak was n n Deb ea eu 81 31 GetTempO Error Codes un 84 32 Power On Configuration Option Signals kk kk kk mmm kk kk kak kya 85 33 Fan Heatsink Power and Signal SpecificationS r rr 95 34 Fan Heatsink Power and Signal SpecificationsS rr nene 99 6 Datasheet intel Intel Celeron Dual Core Processor E1000 Series Available at 1 60 GHz Enhanced Intel SpeedStep Technology Supports Intel 64 architecture Supports Execute Disable Bit capability Binary compatible with applications running on previous members of the Intel microprocessor line FSB frequency at 800 MHz Advance Dynamic Execution Very deep out of order execution Enhanced branch prediction Optimized for 32 bit applications running on advanced 32 bit operating systems Two 32 KB Level 1 data caches 512 KB Advanced Smart Cache Advanced Digital Media Boost Enhanced floating point and multimedia unit for enhanced video audio encryption and 3D per
117. ormation Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Intel Pentium Celeron Intel SpeedStep Intel Core and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2008 Intel Corporation 2 Datasheet Contents 1 Introductio yi c ak ena dan kana naman danka dt kann da D Qa anin S riyan d bada n an ek Kl n d k n a an n k r na 9 Fi Terminology uc 9 LLI Processor Terminology retenir aeterni E E manana Wa xan E RR I Rd 10 PEE Voces 11 2 Electrical Specifications sula nalin wak n narik nal nan n banke me nbn Exe b Wa nand n b k nw bka MUERE 13 2 1 Power and Ground Lands u sanl cla han eet a Yan E E k nen ERA Xua ka eee 13 2 2 Decoupling GUuIdeliNGS uu uu uuu sakal rex ree qe remi Eun Ex kani nl dade ayka supay K niba k na a x aie i e n 13 2 2 1 VCC Decoupling srr n u u s ee h na ha ees dads aa aan a a adele 13 2 2 2 Vtt DECOUPLING ote timere atas Vn PANE ERERNPERER anasssapanaasuiaypawkuqmupaqwsasqaqa 13 2 2 3 FSB Decouplingi anu n belke k ier even pre ee rer PAN EESE crm rl ese Poder d nin 14 2 3 Voltage Identification easet re eee ph I RYE y k aya YR PERRG ened neds a ava L 14 2 4 Market Segment Identification MSID
118. ort implemented on an interposer If a debug port is implemented in the system ITP CLK 1 0 are no connects in the system These are not processor signals LINT 1 0 Input LINT 1 0 Local APIC Interrupt must connect the appropriate pins lands of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these signals as LINT 1 0 is the default configuration Datasheet Land Listing and Signal Descriptions Table 25 Datasheet intel Signal Description Sheet 6 of 9 Name LOCK Type I nput Output Description LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins lands of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK de asserted This enables symmetric agent
119. ower Other vss L25 Power Other VSS E28 Power Other VSS L26 Power Other VSS E8 Power Other vss L27 Power Other VSS F10 Power Other VSS L28 Power Other VSS F13 Power Other VSS L29 Power Other VSS F16 Power Other VSS L3 Power Other VSS F19 Power Other VSS L30 Power Other VSS F22 Power Other VSS L6 Power Other VSS F4 Power Other VSS L7 Power Other VSS F7 Power Other VSS M1 Power Other VSS H10 Power Other VSS M7 Power Other VSS H11 Power Other VSS N3 Power Other Datasheet e Land Listing and Signal Descriptions n tel Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name Land Signal Buffer Direction Land Name Land Signal Buffer Direction Type Type VSS N6 Power Other vss W7 Power Other VSS N7 Power Other VSS Y2 Power Other VSS P23 Power Other VSS Y5 Power Other VSS P24 Power Other VSS Y7 Power Other VSS P25 Power Other VSS_MB_ REGULATION AN6 Power Other Output VSS P26 Power Other VSS_SENSE AN4 Power Other Output vss P27 Power Other VSSA B23 Power Other VSS P28 Power Other VIT A25 Power Other VSS P29 Power Other VIT A26 Power Other VSS P30 Power Other VIT A27 Power Other VSS P4 Power Other VIT A28 Power Other VSS P7 Power Other VIT A29 Power Other VSS R2 Power Other VIT A30 Power Oth
120. port interposer In systems with the debug port implemented on the system board these signals are no connects Datasheet 23 intel Electrical Specifications 3 The value of these signals during the active to inactive edge of RESET defines the processor configuration options See Section 6 1 for details 4 PROCHOT signal type is open drain output and CMOS input Table 9 Signal Characteristics Signals with RTT Signals with No RTT A 35 3 ADS ADSTB 1 0 BNR BPRI D 63 0 DBI 3 0 DBSY DEFER DRDY DSTBN 3 0 DSTBP 3 0 HIT HITM LOCK PROCHOT REQ 4 0 RS 2 0 TRDY A20M BCLK 1 0 BSEL 2 0 COMP 8 3 0 IGNNE INIT ITP CLK 1 0 LINTO INTR LINT1 NMI PWRGOOD RESET SMI STPCLK TESTHI 13 0 VID 6 1 GTLREF 1 0 TCK TDI TMS TRST VIT SEL MSID 1 0 Open Drain Signals THERMTRIP FERR PBE IERR BPM 5 0 BRO TDO FCx NOTES 1 Signals that do not have Ry nor are actively driven to their high voltage level Table 10 Signal Reference Voltages GTLREF Vr 2 BPM 5 0 RESET BNR HIT HITM BRO A 35 0 ADS ADSTB 1 0 BPRI D 63 0 DBI 3 0 DBSY DEFER DRDY DSTBN 3 0 DSTBP 3 0 LOCK REQ 4 0 RS 2 0 TRDY A20M LINTO INTR LINT1 NMI IGNNE INIT PROCHOT PWRGOOD SMI STPCLK TCK TDI TMS TRST 2 NOTES 1 These signals also have hysteresis added to the
121. put A35 AJ6 Source Synch Input Output D16 G9 Source Synch Input Output ADS D2 Common Clock Input Output D17 F8 Source Synch Input Output ADSTBO R6 Source Synch Input Output D18 F9 Source Synch Input Output ADSTB1 AD5 Source Synch Input Output D19 E9 Source Synch Input Output BCLKO F28 Clock Input D20 D7 Source Synch Input Output BCLK1 G28 Clock Input D21 E10 Source Synch Input Output Datasheet Land Listing and Signal Descriptions intel Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name p FEX d Direction Land Name 23 c o Direction D22 D10 Source Synch Input Output D61 A19 Source Synch Input Output D23 F11 Source Synch Input Output D62 A22 Source Synch Input Output D24 F12 Source Synch Input Output D63 B22 Source Synch Input Output D25 D13 Source Synch Input Output DBIO A8 Source Synch Input Output D26 E13 Source Synch Input Output DBI1 G11 Source Synch Input Output D27 G13 Source Synch Input Output DBI2 D19 Source Synch Input Output D28 F14 Source Synch Input Output DBI3 C20 Source Synch Input Output D29 G14 Source Synch Input Output DBR AC2 Power Other Output D30 F15 Source Synch Input Output DBSY B2 Common Clock Input Output D31 G15 Source Synch Input Output DEFER G7 Common Clock Input D32 G16 Sour
122. put T24 VCC Power Other P4 VSS Power Other T25 vcc Power Other P5 RESERVED T26 VCC Power Other P6 A04 Source Synch Input Output T27 VCC Power Other P7 VSS Power Other T28 VCC Power Other P8 VCC Power Other T29 VCC Power Other P23 VSS Power Other T30 VCC Power Other P24 VSS Power Other U1 FC28 Power Other P25 VSS Power Other U2 FC29 Power Other P26 VSS Power Other U3 FC30 Power Other P27 VSS Power Other U4 A13 Source Synch Input Output P28 vss Power Other U5 Al2 Source Synch Input Output P29 VSS Power Other U6 A10 Source Synch Input Output P30 VSS Power Other U7 VSS Power Other R1 COMP3 Power Other Input U8 VCC Power Other R2 VSS Power Other U23 VCC Power Other R3 FERR PBE Asynch CMOS Output U24 VCC Power Other R4 A08 Source Synch Input Output U25 VCC Power Other R5 VSS Power Other U26 VCC Power Other R6 ADSTBO Source Synch Input Output U27 VCC Power Other Datasheet Land Listing and Signal Descriptions intel Table 24 Numerical Land Table 24 Numerical Land Assignment Assignment cand Land Name Signal Butter Direction tang Land Name Signal DENISE Direction Type Type U28 VCC Power Other Y5 VSS Power Other U29 VCC Power Other Y6 A195 Source Synch Input Output U30 VCC Power Other Y7 VSS Power Other V1 MSID1 Power Other Output Y8 VCC Power Other v2 RESERVED Y23 VCC Power Other V3 VSS Power Other Y24
123. r Other Output Yu TA Power Other VCCA A23 Power Other UE T25 Power Other VCCIOPLL C23 Power Other VER SUE Power Other VCCPLL D23 Power Other VID SELECT AN7 Power Other Output 49 50 intel Land Listing and Signal Descriptions Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name p Wes gt dd Direction Land Name a s Te Direction VIDO AM2 Power Other Output VSS AC7 Power Other VID1 AL5 Power Other Output VSS AD4 Power Other VID2 AM3 Power Other Output VSS AD7 Power Other VID3 AL6 Power Other Output VSS AE10 Power Other VIDA AKA Power Other Output VSS AE13 Power Other VID5 AL4 Power Other Output VSS AE16 Power Other VID6 AM5 Power Other Output VSS AE17 Power Other VID7 AM7 Power Other Output VSS AE2 Power Other VRDSEL AL3 Power Other VSS AE20 Power Other VSS A12 Power Other VSS AE24 Power Other VSS A15 Power Other VSS AE25 Power Other VSS A18 Power Other VSS AE26 Power Other VSS A2 Power Other VSS AE27 Power Other VSS A21 Power Other VSS AE28 Power Other VSS A6 Power Other VSS AE29 Power Other VSS A9 Power Other VSS AE30 Power Other VSS AA23 Power Other VSS AE5 Power Other VSS AA24 Power Other VSS AE7 Power Other VSS AA25 Power Other VSS AF10 Power Other VSS AA26 Power Other VSS AF13 Power Other VSS AA27 Power Other VSS AF16 Power Ot
124. r VCC AN19 Power Other VCC AK22 Power Other VCC AN21 Power Other VCC AK25 Power Other VCC AN22 Power Other VCC AK26 Power Other VCC AN25 Power Other VCC AK8 Power Other VCC AN26 Power Other VCC AK9 Power Other VCC AN29 Power Other VCC AL11 Power Other VCC AN30 Power Other VCC AL12 Power Other VCC AN8 Power Other VCC AL14 Power Other VCC AN9 Power Other VCC AL15 Power Other VCC J10 Power Other VCC AL18 Power Other VCC J11 Power Other VCC AL19 Power Other VCC J12 Power Other VCC AL21 Power Other VCC J13 Power Other VCC AL22 Power Other VCC J14 Power Other VCC AL25 Power Other VCC J15 Power Other VCC AL26 Power Other VCC J18 Power Other VCC AL29 Power Other VCC J19 Power Other VCC AL30 Power Other VCC J20 Power Other VCC AL8 Power Other VCC J21 Power Other VCC ALY Power Other VCC J22 Power Other VCC AM11 Power Other VCC J23 Power Other VCC AM12 Power Other VCC J24 Power Other VCC AM14 Power Other VCC J25 Power Other VCC AM15 Power Other VCC J26 Power Other VCC AM18 Power Other VCC J27 Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 23 Alphabetical Land Table 23 Alphabetical Land Assignments Assignments Land Name un ur al Direction Land Name 2 E T Direction
125. rnal snoop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 Input Output Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO A 35 17 ADSTB1 BCLK 1 0 Input The differential pair BCLK Bus Clock determines the FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss BNR Input Output BNR Block Next Request is used to assert a bus stall by any bus agent unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions 64 Datasheet Land Listing and Signal Descriptions intel Table 25 Signal Description Sheet 2 of 9 Name BPM 5 0 Type Input Output Description BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins lands of all processor FSB agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug
126. rocessor Hot will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum Safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled for both cores The TCC will remain active until the system de asserts PROCHOT PROCHOT allows for some protection of various components from over temperature situations The PROCHOT signal is bi directional in that it can either signal when the processor either core has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components PROCHOT can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on PROCHOTZ only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power With a properly designed and characterized thermal solution it is anticipated that PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solutio
127. rossing point specifications simultaneously 6 Overshoot is defined as the absolute value of the maximum voltage Undershoot is defined as the absolute value of the minimum voltage Measurement taken from differential waveform Cpad includes die capacitance only No package parasitics are included Com Datasheet 29 m n tel Electrical Specifications Figure 3 Differential Clock Waveform CLK 0 CROSS x f b X Nenne Median 75 mV X 7 MAI 550 mV Vcnoss V median CROSS ROSS Hus Ah dasan sanan danazan A S M Min median Median 399 Be Joon i vx EE E ih Te CROSS CLK 1 300 mV High Time Low Time Period Figure 4 Differential Clock Crosspoint Specification 650 a 600 m __ s 550 0 5 VHavg 700 300 0 5 VHavg 700 Crossing Point mV 200 T T T T T T T T T T T T T T T T T T 1 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg mV Figure 5 Differential Measurements Slew_rise Slew _fall 30 Datasheet m e Electrical Specifications n tel 2 8 5 BCLK 1 0 Specifications CK410 based Platforms Table 18 Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figur
128. s provided in Table 5 Refer to the Intel Celeron Dual Core Processor E1000 Series Specification Update for further details on specific valid core frequency and VID values of the processor Note this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Enhanced HALT State The processor uses six voltage identification signals VID 6 1 to support automatic selection of power supply voltages Table 2 specifies the voltage level corresponding to the state of VID 6 1 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty VID 6 1 111111 or the voltage regulation circuit cannot supply the voltage that is requested it must disable itself The Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket defines VID 7 0 VID7 and VIDO are not used on the processor VIDO and VID7 are strapped to Vss on the processor package VIDO and VID7 must be connected to the VR controller for compatibility with future processors The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core volt
129. s reliable as the device that it is embedded in and thus given operating conditions that fall under the specification the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures There are however certain scenarios where the PECI is know to be unresponsive Prior to a power on RESET and during RESET assertion PECI is not ensured to provide reliable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host controller should take action to protect the system from possible damaging states It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive gettemp s or for a one second time interval The host controller may also implement an alert to software in the event of a critical or continuous fault condition PECI GetTempO Error Code Support The error codes supported for the processor GetTemp command are listed in Table 31 GetTempO Error Codes Error Code Description 8000h General sensor error Sensor is operational but has detected a temperature below its operational goazan range underflow
130. s to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock MSID 1 0 Output These signals indicate the Market Segment for the processor Refer to Table 3 for additional information PECI Input Output PECI is a proprietary one wire bus interface See Section 5 4 for details PROCHOT Input Output As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled The TCC will remain active until the system de asserts PROCHOT See Section 5 2 4 for more details PWRGOOD REQ 4 0 Input Input Output PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD
131. scriptions Figure 13 land out Diagram Top View Left Side 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN vcc vcc vss vss vec vec vss vss vec vec vss vec vec vss vss vec AM vcc vec vss vss vec vec vss vss vec vec vss vec vec vss vss vec AL vcc vec vss vss vcc vcc vss vss vcc vcc vss vcc vec vss vss vec AK vss vss vss vss vcc vcc vss vss vcc vcc vss vec vec vss vss vec AJ vss vss vss vss vec vec vss vss vec vec vss vec vec vss vss vec AH vcc vcc vcc vcc vcc vec vss vss vec vec vss vec vec vss vss vec AG vcc vec vec vec vec vec vss vss vec vec vss vec vec vss vss vec AF vss vss vss vss vss vss vss vss vec vec vss vec vec vss vss vec AE vss vss vss vss vss vss vss vec vec vec vss vec vec vss vss vec AD vcc vec vec vec vec vcc vec vec AC vcc vec vec vec vec vcc vec vec AB vss vss vss vss vss vss vss vss AA vss vss vss vss vss vss vss vss Y vcc vec vec vec vec vec vec vec w vec vec vec vec vec vcc vec vec v vss vss vss vss vss vss vss vss U vcc vcc vcc vec vec vec vec vcc T vcc vec vec vec vec vcc vec vec R vss vss vss vss vss vss vss vss P vss vss vss vss vss vss vss vss N vec vec vec vec vec vec vec vec M vec vec vec vec vec vec vec vec vss vss vss vss vss vss vss vss K vec vec vec vec vcc vcc vec vc
132. scriptions Signal Description Sheet 7 of 9 Name RS 2 0 Type Input Description RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins lands of all processor FSB agents SKTOCC Output SKTOCC Socket Occupied will be pulled to ground by the processor System board designers may use this signal to determine if the processor is present SMI STPCLK Input Input SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the de assertion of RESET the processor will tri state its outputs STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is de asserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asyn
133. sor thermal solution design targets The TDP is not the maximum power that the processor can dissipate 2 This table shows the maximum TDP for a given frequency range Individual processors may have a lower TDP Therefore the maximum Tc will vary depending on the TDP of the individual processor Refer to thermal profile figure and associated table for the allowed combinations of power and Tc 3 Specification is at 35 C Tc and typical voltage loadline Specification is ensured by design characterization and not 100 tested 4 775 VR CONFIG 06 guidelines provide a design target for meeting future thermal requirements 74 Datasheet Thermal Specifications and Design Considerations Table 27 Thermal Profile Maximum Maximum Maximum Power W Tc C Power Tc C Power Tc C 0 45 3 24 55 6 48 65 9 2 46 2 26 56 5 50 66 8 4 47 0 28 57 3 52 67 7 6 47 9 30 58 2 54 68 5 8 48 7 32 59 1 56 69 4 10 49 6 34 59 9 58 70 2 12 50 5 36 60 8 60 71 1 14 51 3 38 61 6 62 72 0 16 52 2 40 62 5 64 72 8 18 53 0 42 63 4 65 73 3 20 53 9 44 64 2 22 54 8 46 65 1 Figure 15 Thermal Profile 75 0 70 0 4 650 i y 0 43x 45 3 a o Tease C mb tn m o m 50 0 40 0 30 Power W 40 50 60 Datasheet 75 n tel Thermal Specifications and Design Considerations 5 1 2 Figure 16 5 2
134. ssor Power Characterization Methodology for the details of this methodology 73 Thermal Specifications and Design Considerations intel The case temperature is defined at the geometric top center of the processor Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 26 instead of the maximum processor power consumption The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time For more details on the usage of this feature refer to Section 5 2 To ensure maximum flexibility for future requirements systems should be designed to the 775 VR CONFIG 06 guidelines even if a processor with a lower thermal dissipation is currently planned In all cases the Thermal Monitor and Thermal Monitor 2 feature must be enabled for the processor to remain within specification Table 26 Processor Thermal Specifications Processor Core Thermal Extended 775 MR Minimum Maximum T Number Frequency Design HALT CONFIG 06 Tc C C Notes GHz Power W 2 Power w Guidance c 775 VR E1200 1 6 65 0 8 CONFIG 06 5 Me Figure 15 Guidance NOTES 1 Thermal Design Power TDP should be used for proces
135. t K24 VCC Power Other J2 FC3 Power Other K25 VCC Power Other J3 FC22 Power Other K26 VCC Power Other J4 VSS Power Other K27 VCC Power Other 18 REQ1 Source Synch Input Output K28 VCC Power Other J6 REQ4 Source Synch Input Output K29 VCC Power Other J7 VSS Power Other K30 VCC Power Other J8 VCC Power Other L1 LINT1 Asynch CMOS Input J9 VCC Power Other L2 TESTHI 13 Power Other Input J10 VCC Power Other L3 VSS Power Other J11 VCC Power Other L4 A06 Source Synch Input Output J12 VCC Power Other L5 A03 Source Synch Input Output J13 VCC Power Other L6 VSS Power Other J14 VCC Power Other L7 VSS Power Other J15 VCC Power Other L8 VCC Power Other J16 FC31 Power Other L23 VSS Power Other J17 FC34 Power Other L24 VSS Power Other J18 VCC Power Other L25 VSS Power Other j19 VCC Power Other L26 VSS Power Other J20 VCC Power Other L27 vss Power Other J21 VCC Power Other L28 vss Power Other J22 VCC Power Other L29 vss Power Other J23 VCC Power Other L30 VSS Power Other J24 VCC Power Other M1 VSS Power Other j25 VCC Power Other M2 THERMTRIP Asynch CMOS Output J26 VCC Power Other M3 STPCLK Asynch CMOS Input J27 VCC Power Other M4 AO7 Source Synch Input Output J28 VCC Power Other M5 A05 Source Synch Input Output J29 VCC Power Other M6 REQ2 Source Synch Input Output J30 VCC Power Other M7 VSS Power Other K1 LINTO Asynch CMOS Input M8 VCC Power Other K2 VSS Power Other M23 VCC Power Other K3 A20M Asynch
136. tches It includes input threshold hysteresis Figure 6 Differential Clock Crosspoint Specification 650 600 a i lt _ _ 550 500 550 0 5 VHavg 700 450 400 250 0 5 VHavg 700 350 Crossing Point mV 300 250 N 200 T T T T i i j T K T T T T T T T T T 1 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg mV Datasheet 31 Table 19 32 PECI DC Specifications PECI is an Intel proprietary one wire interface that provides a communication channel between Intel processors may also include chipset components in the future and external thermal monitoring devices The processor contains Digital Thermal Sensors DTS distributed throughout die These sensors are implemented as analog to digital converters calibrated at the factory for reasonable accuracy to provide a digital Electrical Specifications representation of relative processor temperature PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal fan speed control More detailed information is available in the Platform Environment Control Interface PECI Specification PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes Vin Input Voltage Range 0 15 VTT Vhysteresis
137. the processor even when the TCC is active continuously Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Thermal Monitor 2 The processor also supports an additional power reduction capability known as Thermal Monitor 2 This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor When Thermal Monitor 2 is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated The TCC causes the processor to adjust its operating frequency via the bus multiplier and input voltage via the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption A processor enabled for Thermal Monitor 2 includes two operating points each consisting of a specific operating frequency and voltage The first operating point represents the normal operating condition for the processor Under this condition the core frequency to FSB multiple used by the processor is that contained in the CLOCK FLEX MAX MSR and the VID is that specified in Table 5 These parameters represent normal system oper
138. tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processor These signals do not have on die termination Refer to Section 2 6 2 for termination requirements BPRI Input BPRI Bus Priority Request is used to arbitrate for ownership of the processor FSB It must connect the appropriate pins lands of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by de asserting BPRI BRO Input Output BRO drives the BREQO signal in the system and is used by the processor to request the bus During power on configuration this signal is sampled to determine the agent ID 0 This signal does not have on die termination and must be terminated BSEL 2 0 Output The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor input clock frequency Table 16 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency For more information about these signals inclu
139. ty the boxed processor will operate as follows As processor power has increased the required thermal solutions have generated increasingly more noise Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage The 4th wire PWM solution provides better control over chassis acoustics This is achieved by more accurate measurement of processor die temperature through the processor s temperature diode T diode Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures If the new 4 pin active fan heat sink solution is connected to an older 3 pin baseboard CPU fan header it will default back to a thermistor controlled mode allowing compatibility with existing 3 pin baseboard designs Under thermistor controlled mode the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet For more details on specific motherboard requirements for 4 wire based fan speed control see the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 8 88 99 e n tel Boxed Processor Specifications 100 Datasheet m e Debug Tools Specifications n tel 8 8 1 8 1 1 8 1 2 Datasheet Debug Tools
140. ution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vec must be removed following the assertion of THERMTRIP Driving of the THERMTRIP signal is enabled within 10 us of the assertion of PWRGOOD provided V and Vcc are valid and is disabled on de assertion of PWRGOOD if Vr or Vcc are not valid THERMTRIP may also be disabled Once activated THERMTRIP remains latched until PWRGOOD V or Vee is de asserted While the de assertion of the PWRGOOD Vr or Vcc will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 us of the assertion of PWRGOOD provided Vrr and Vcc are valid TMS Input TMS Test Mode Select is a J TAG specification support signal used by debug tools TRDY Input TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins lands of all FSB agents TRST Input TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset VCC Input VCC are the power pins for the processor The voltage supplied to these pins is determined by the VID 7 0 pins VCCPLL Input VCCPLL provides isolated power for internal processor FSB PLLs VCC_SENSE VCC_MB_ REGULATION Output Output
141. vss FC8 vss VIDA ITP CLKO vss THERMDC vec vss vec vec vss vec vec vss A35 A34 vss ITP_CLK1 BPMO BPM1 vcc vss vcc vcc vss vcc vcc vss vss A33 A32 vss RSVD vss vec vss vec vec vss vec vec vss A29 A31 A30 BPM5 BPM3 TRST vcc vss vcc vcc vss vcc vcc vss vss A27 A28 vss BPM4 TDO vcc vss vcc vcc vss vec skrocce vss RSVD vss RSVD FC18 vss TCK vcc vss A22 ADSTB1 vss FC36 BPM2 TDI vec vss vss A25 RSVD vss DBR TMS vcc vss A17 A24 A26 FC37 IERR vss VIT OUT vec vss vss A23 A21 vss FC39 Ar vec vss A19 vss A20 FC17 vss FCO vcc vss A184 A164 vss TestHi1 UFU Msipo vec vss vss A14 A15 vss RSVD MSID1 vcc vss A10 A12 A13 FC30 FC29 FC28 vcc vss vss A9 A11 vss FCA COMP1 vec vss ADSTBO vss A8 red vss COMP3 vec vss mm RSVD vss INIT SMI TESTHI11 vcc vss vss RSVD RSVD vss IGNNE PWRGOOD vcc vss REQ2 AS a7 sTPCLK THERMTRIP amp vss vcc vss vss A3 AG vss TESTHI13 LINTL vec vss REQ3 vss REQO A20M amp vss LINTO vec vcc vec vec vec vec vec vss REQ4 REQ1 vss FC22 FC3 ee vss vss vss vss vss vss vss vss vss TESTHI10 FC35 vss GTLREF1 GTLREFO D29 D274 DSTBN1 DBI1 FC38 Dl6 BPRI DEFER amp RSVD PECI eg crease GOMPA FC27 D284 vss D244 D23 vss D18 amp D17 vss FC21 RS1 vss BRO FCS vss D26 DsTBPl amp vss D21 amp D19 amp vss RSVD RSVD FC20 HiTM amp TRDY vss rsvp D25 vss pis D22 vss D12 D20 vss vss HIT vss ADS RSVD D524 vss D 4 Dll

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