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IBM Intel Xeon X7350

1. 1 of 14 2 of 14 Pin No Pin Name Bune ae Direction Pin No Pin Name Buro yas Direction Al VID5 Power Other Output B12 Vr Power Other A2 VTT_SEL Power Other Output B13 A13 Source Sync Input Output A3 SKTOCC amp Power Other Output B14 A12 Source Sync Input Output A4 Vir Power Other B15 Vss Power Other A5 Vss Power Other B16 A11 Source Sync Input Output A6 A32 Source Sync Input Output B17 Vss Power Other A7 A33 Source Sync Input Output B18 A54 Source Sync Input Output A8 Vcc Power Other B19 REQO Common Clk Input Output A9 A26 Source Sync Input Output B20 Vcc Power Other A10 A20 Source Sync Input Output B21 REQ1 Common Clk Input Output A11 Vss Power Other B22 REQ4 Common Clk Input Output A12 A14 Source Sync Input Output B23 Vss Power Other A13 A10 Source Sync Input Output B24 LINTO Async GTL Input A14 Vcc Power Other B25 PROCHOT Async GTL Output A15 FORCEPR Async GTL Input B26 Vss sENsE2 Power Other Output A16 TESTHIO Power Other Input B27 Vcc SENSE Power Other Output A17 LOCK Common Clk Input Output B31 LL_IDO Power Other Output A18 Vcc Power Other B29 PROC ID1 Power Other Output A19 A7 Source Sync Input Output B30 Reserved A20 A4 Source Sy
2. Document Number 318080 002 an mn Jann BER TELS y vido DAME H 152070 059070 XvHS9 0H d XWH 260 19 90 0FE0 2 li NAIA 18084 r2 3LVULSONS 29017 INGE HI 2 h I HUME see res 2 S mm aly 114 see res ly Y d 1WW3S SHI mes OK Za mr vts I DI NIN Y 020 M ligu TS BARAN SE aa ALIUV1O IVNSIA 804 3A0N38 AYLINOID 1NVIV3S SHI q AJIA dOL GIA WOLLOB SIS Ip AJIA 3018 E 017 SHI i tp D a H a N O J e EE 7p 2970 I 5 ES A i Ze j i P SHI ELM P y 1 J i ECKER NIXIH UN NOI LO 5 E q lg H Zoll us r6 p mli as raw a r A intel Figure 3 2 Processor Package Drawing Sheet 1 of 2 58 Au Tr um RETTEN intel Ue 3W28 lis JWS MAIA M01108 MBIA dOL 189138 1N3NOdHO2 V3uv Q3H21VHS S082 1H913H 1N3NOdHO2 E XVW SI AJIA 301S 1004339 ININOdNOD 318VA0T V XVN 072 Va 3 WE Lj 7 Q I x O Z DN eeeeeeeeeeeeeoeo O 000000000000000 i 000000000000000 000000000000000 f 000000090000 000 QO OOO0OO 0000000 000000000 k eeee
3. 3 of 14 4 of 14 Pin No Pin Name Signal Direction Pin No Pin Name Signal Direction Buffer Type Buffer Type C23 DEFER Common Clk Input E5 IERR Async GTL Output C24 TDI TAP Input E6 Vcc Power Other C25 Vss Power Other Input E7 BPM2 Common Clk Input Output C26 IGNNE Async GTL Input E8 BPM4 Common Clk Input Output C27 SMI Async GTL Input E9 Vss Power Other C28 PECI Power Other Input Output E10 AP0 Common Clk Input Output C29 Vss Power Other E11 Ver Power Other C30 Vcc Power Other E12 Ver Power Other C31 Reserved E13 A28 Source Sync Input Output D1 TESTIN1 Power Other Input E14 A24 Source Sync Input Output D2 Vss Power Other E15 Vss Power Other D3 VID2 Power Other Output E16 COMP1 Power Other Input D4 STPCLK Async GTL Input E17 Vss Power Other D5 Vss Power Other E18 DRDY Common Clk Input Output D6 INIT Async GTL Input E19 TRDY Common Clk Input D7 MCERR Common Clk Input Output E20 Vcc Power Other D8 Vcc Power Other E21 RS0 Common Clk Input D9 AP1 Common Clk Input Output E22 HIT Common Clk Input Output D10 Ver Power Other E23 Vss Power Other D11 Vss Power Other E24 TCK TAP Input D12 A29 Source Sync Input Output E25 TDO TAP Output D13 A25 Source Sync Input Output E26 Vcc Power Other D14 Vcc Power Other E27 FERR PBE Async GTL Output D15 A18 Source Sync Input Output E28 Vcc Power Other D16
4. 310H ONILNNOW 3053208d AINO 32N383438 X04 NMOHS INI TINO QYVOG Mari 109 o Poor NUJLLWA 310H jO 31007 HOYA NU3LIVA 3108 40D Inge 2 061 NZ 90 61 NOI1VNOdHOD 131N HL LNOHLIM uo Q34V1dS10 039 035019510 38 LON AVN SINJLNOD SLI ONY 3 NOLLVNUO SNIVLNOD ONIMVEO SIHL 301 4NOD NOIlV80480 L af ag a am T 9 L 8 intel Figure 3 7 Board Mounting Hole Keepout Zones Document Number 318080 002 64 Mechanical Specifications n tel Figure 3 8 Volumetric Height Keep Ins a e L m lt 3 227 ey I Y gt ra wo wm a Li o tat gt a eo Ly _ 23 o gu tE Lu 3 p l o gt oo e o m lt Document Number 318080 002 Table 3 1 66 Mechanical Specifications Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package These mechanical load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not b
5. Symbol Parameter Min Typ Max Unit Notes lo Icc for Ver supply before Vcc stable 8 0 A 15 Icc for Ver supply after Vcc stable 7 0 lec TDC Thermal Design Current TDC Quad 50 A 6 14 E Core Intel Xeon L7345 Processor Launch FMB lec TDC Thermal Design Current TDC Dual 75 A 6 14 i Core Intel amp Xeon Processor 7200 Series Launch FMB lec TDC Thermal Design Current TDC Intel 75 A 6 14 i Xeon Processor 7200 Series and 7300 Series Launch FMB lec toc Thermal Design Current TDC Intel 110 A 6 14 u Xeon X7350 Processor Launch FMB Icc vrr oUT DC current that may be drawn from 580 mA 16 Var our Per pin lec GTLREF Icc for 200 HA 7 GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END lec vCCPLL lec for PLL supply 260 mA 12 Itcc Icc for Quad Core Intel Xeon L7345 60 A Processor during active thermal control circuit TCC Itcc Icc for Dual Core Intel Xeon 90 A Processor 7200 Series during active thermal control circuit TCC Itcc Icc for Dual Core Intel Xeon 90 A Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series during active thermal control circuit TCC Itcc Icc for Intel Xeon X7350 Processor 130 A during active thermal control circuit TCC Notes 1 Unless otherwise noted all specifications in this table apply to all processors and are based on estimates and simulations not empirical data These specificatio
6. Symbol Parameter Min Typ Max Units Notes GTLREF DATA MID Data Bus Reference 0 98 0 67 V 0 67 Vir 1 02 0 67 Vr V 2 3 GTLREF DATA END Voltage GTLREF ADD MID Address Bus 0 98 0 67 V 0 67 Vi 1 02 0 67 Var V 2 3 GTLREF ADD END Reference Voltage Rot Termination 45 50 55 Q 4 Resistance pull up COMP COMP Resistance 49 4 49 9 50 4 5 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values across the range of V 3 GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END is generated from Vrr on the baseboard by a voltage divider of 196 resistors The minimum and maximum specifications account for this resistor tolerance Refer to the appropriate platform design guidelines for implementation details The Vor referred to in these specifications is the instantaneous Vrr 4 Rrristhe on die termination resistance measured at Vo of the AGTL output driver Measured at 0 31 Vr r Rr is connected to Vz on die Refer to processor I O Buffer Models for I V characteristics 5 COMP resistance must be provided on the system board with 1 resistors See the applicable platform design guide for implementation details Table 2 18 FSB Differential BCLK Specifications
7. Symbol Parameter Min Typ Max Unit Figure Notes Vu Single ended Input 0 150 0 0 0 15 V 2 13 Low Voltage Vin Single ended Input 0 660 0 710 0 850 V 2 13 High Voltage Vcross abs Absolute Crossing 0 250 0 350 0 550 V 2 13 2 8 Point 2 14 Vcross rel Relative Crossing 0 250 N A 0 550 V 2 13 3 8 9 11 Point 0 5 VHavg 0 700 0 5 Vuavg 0 700 2 14 Vcnoss Vcross variation N A N A 0 140 V 2 13 2 14 VMAX Absolute Single ended N A N A 1 15 V 2 13 4 Overshoot maximum voltage VMIN Absolute Single ended 0 300 N A N A V 2 13 5 Undershoot minimum voltage VRBM Single ended 0 200 N A N A V 2 13 6 Ringback Margin VTR Single ended VcRoss 0 100 N A Veross 0 100 V 2 13 7 Threshold Region lu Input Leakage N A N A 100 uA 10 Current Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLKO is equal to the falling edge of BCLK1 3 Vhava is the statistical average of the Vi measured by the oscilloscope 4 Overshoot is defined as the absolute value of the maximum voltage 5 Undershoot is defined as the absolute value of the minimum voltage 6 Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback 7 Threshold Region is defined as a region entered around the crossin
8. HALT Bus Cycle Generated Normal State Extended HALT or HALT State N i uti INIT BINIT INTR NMI SMI BCLK running SC RESCH le RESET FSB interrupts Snoops and interrupts allowed A Snoop Snoop STPCLK STPCLK lt Event Event Asserted De asserted A Occurs Serviced IS d lt Extended HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Y Stop Grant State SE Stop Grant Snoop State BCLK running BCLK running Snoops and interrupts allowed Snoop Event Serviced Service snoops to caches Stop Grant State When the STPCLK pin is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Once the STPCLK pin has been asserted it may only be deasserted once the processor is in the Stop Grant state All processor cores will enter the Stop Grant state once the STPCLK pin is asserted Additionally all processor cores must be in the Stop Grant state before the deassertion of STPCLK Since the AGTL signal pins receive power from the front side bus these pins should not be driven allowing the level to return to Ver for minimum power drawn by the termination resistors in this state In addition all other input pins on the front side bus should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant
9. T Parameter Min Max Unit Figure Notes FSB Clock Frequency 265 247 266 745 MHz 2 T1 BCLK 1 0 Period 3 7489 3 7700 ns 2 13 3 T2 BCLK 1 0 Period Stability N A 150 ps 4 T3 BCLK 1 0 Rise Time 175 700 ps 5 T4 BCLK 1 0 Fall Time 175 700 ps 5 Differential Rising and Falling Edge Rates 0 6 4 V ns Z Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The processor core clock frequency is derived from BCLK The bus clock to processor core clock ratio is determined during initialization as described in Section 2 3 Table 2 1 includes core frequency to FSB multipliers 3 The period specified here is the average period A given period may vary from this specification as governed by the period stability specification T2 4 Inthis context period stability is defined as the worst case timing difference between successive crossover voltages In other words the largest absolute difference between adjacent clock periods must be less than the period stability 5 Rise and fall times are measured single ended between 245 mV and 455 mV of the clock swing 6 Measured from 200 mV to 200 mV The signal must be monotonic through the measurement region for rise and fall time The 400 mV measurement window is centered on the differential zero Front Side Bus Common Clock AC Specifications T Parameter Min Max Unit Figure Notes 2 3 T10 Common Cloc
10. rr memes eminens 45 3 Mechanical Specifications oe terere aps A 57 3 1 Package Mechanical Drawing meme seme emen 57 3 2 Processor Component Keepout Zones 60 3 3 Package Loading Specifications cece r memes memes 66 3 4 Package Handling Guidelines rr emmememe nemen 67 3 5 Package Insertion Gpechflcations r mnes 67 3 6 Processor Mass Specifications rus rakurarkssashasscyerastasaycananakkuycapayaayapanyaqqaqwqasa 67 3 7 Processor Materlals iioii ette Or err ene sia A nib re eese bp rm ro ed Fa ate bene erri 67 3 8 Processor Markings s tee ele eg ZE eegene litis 68 3 9 Processor Pin Out Coordinates rr emnes nemen nnns 69 4 PIMNLIStNO ss rm 71 SE PirncAssigntments ucc e eim A oa 71 4 3 1 Pin Listing Dy Pin Name eiie ene erat rmx rea cia 71 41 2 Pin Listing by Pin Number een mete encierra Xa a Canna pa DR 79 5 Signal E d LEE 87 5l Signal Definitions s Poo UE A KEE EE 87 6 Thermal Specifications oe ea oe eid dig wedge eer we E aU Y LE ELE UP d 95 6 1 Package Thermal Gpecflcations r rr e memememen memes 95 6 1 1 Thermal Specifications uu u uuu ass itr NEE EE NEE ieri EE 95 6 1 2 Thermal Metrology sssssssssee mme RREN ENAN UREE 102 6 2 Processor Thermal Features 103 6 2 1 Thermal Monitor Features 103 6 22 Thermal Mertes t Eed REENERT 103 Document Number 318080 002 3 ntel 60 2 3 Th
11. T Parameter Min Max Unit Figure Notes 2 3 4 T20 Source Sync Output Valid Delay 0 00 1 10 ns 2 17 5 first data address only 2 18 T21 Tygp Source Sync Data Output 0 270 ns 2 18 5 8 Valid Before Data Strobe T22 Tyap Source Sync Data Output 0 270 ns 2 18 5 9 Valid After Data Strobe T23 Tyga Source Sync Address Output 0 660 ns 2 17 5 8 Valid Before Address Strobe T24 Tyaa Source Sync Address Output 0 660 ns 2 17 5 9 Valid After Address Strobe T25 Tsuss Data Input Setup Time 0 190 ns 2 17 2 18 6 T25 Tsuss Address Input Setup Time 0 300 ns 2 17 6 2 18 T26 Thss Data Input Hold Time 0 190 ns 2 17 6 2 18 T26 Thss Address Input Hold Time 0 300 ns 2 17 6 2 18 T27 Source Synchronous Address 3 5 ns 2 17 12 14 15 Strobe Setup Time to BCLK 1 0 1 875 n T28 Source Synchronous Data Strobe 4 15 ns 2 18 11 14 Setup Time to BCLK 1 0 0 9375 n T30 Data Strobe mn DSTBN Output 3 28 4 38 ns 2 18 13 Valid Delay T31 Address Strobe Output Valid Delay 2 81 3 91 ns 2 17 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Not 100 tested Specified by design characterization 3 All source synchronous AC timings are referenced to their associated strobe at nominal GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END Source synchronous data signals are referenced to the falling edge of their associated data strobe Source synchron
12. Sustained Current A 75 70 65 60 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than lec TDC 2 Not 100 tested Specified by design characterization 28 Document Number 318080 002 Electrical Specifications intel Figure 2 4 Quad Core Intel Xeon X7350 Processor Load Current versus Time 130 125 120 115 110 Sustained Current A 105 100 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than Icc TDC 2 Not 10096 tested Specified by design characterization Document Number 318080 002 29 e n tel Electrical Specifications Table 2 10 Vcc Static and Transient Tolerance Icc A Vcc Max V Vcc ren V Vcc we V Notes 0 VID 0 000 VID 0 015 VID 0 030 1 2 3 5 VID 0 006 VID 0 021 VID 0 036 1 2 10 VID 0 013 VID 0 028 VID 0 043 1 2 3 15 VID 0 019 VID 0 034 VID 0 049 1 2 20 VID 0 025 VID 0 040 VID 0 055 1 2 3 25 VID 0 031 VID 0 046 VID 0 061 1 2 30 VID 0 038 VID 0 053 VID 0 068 1 2 3 35 VID 0 044 VID 0 059 VID 0 074 1 2 3 40 VID 0 050 VID 0 065 VID 0 080 1
13. AINO 32N343438 401 002 92 18 AYVONNOG 133208 v09v9qu l z v y S 9 L 8 3 30 1 Dau 31639 10N OU INON 31v09 H PITE LI e6261V X qd T 3M011V SININOdNOD QuVOGH3HLION ON 100d33Y YIONIS QuYOG ONIUdS 439 Ade dew ontaveo 3002 39vo lis m Ak pp juu x DOEN 1nods3 292 zoe Swa r l ROLES JON OMINI NOILOI81S38 1H913H LNINOdNOD GYVOGYIHLOW XVW HAP ISG 3ivo 48 0342349 GH 31111 20 20 01 NIIN CN rer E Lo m 3ivo 18 wavaa V au no sin Ai dell cm ROO A 03N071V 1N3H32V1d LN3NOdWOD QYYOBYIHLOW ON NOI 1918138 1H913H LNINOdWOD XVW WW 9278 G2C V3uv AT18W1SSVS IQ XNISIV3H NOI12INIS3H 1H9 3H LNINOdNOD XVN WW 9279 EE V3uv WNISIV3H NOI1V8OdUO2 TILNI jO 1N3SNOO NJLLIYM YOIYd FHL INOHLIM 0313100 HO Q3AV1dSIQ 0IINIOUAFS 0ISOTISIO 38 LON AYN 5009986 NOI 19181538 18513H l1SS NOILOIYLS3Y 1H913H LNINOdNOD XVN WNIG C OGI T 0N3931 o 7 g m N0112181S38 D BEER J 1H913H G2 M I BEE 0000000000000000000000000 GE BIN 00000
14. d 9 L 8 3 30 2 11 ouravad avas 10N 09 INOW m Mm HE A Zum 3002 Jov bzis oor 2 9608 t00 2 30S AYYNIHd TIRES YWYT5 VINYS 1195 x00 O op mm 3931102 en 0022 e S31OH NYHL ONILNNOW u05 320 d 3 an 20 0 g 0991 OID Xr Q3N011V SIN3NOdWO2 QuVOGUIHION ON 1n0d31W YIONI4 GUVOG ONIUdS 412 N0112181S38 1H913H IN3NOdNO2 OBVOGUJHIOM XVH MH ISS C3MOTIV 1N3432V1d 1N3NOdWOO QYVOGYIHLON ON NO1I12181S38 1H9 3H LNINOdNOD XYW WW 928 G2t V38V AT8N3SSVS IQ XNISIV3H NOILOIYLSIY 1H913H LNINOdNOD XVW WW 9279 G2t V3uV ANISLVIH NO 12181S38 1H913H LNINOdNOD XYW WHIg C OSI 3009596 2v 86 000 2 ER 9281 oe or 810711 S 00071 WH 005 DW 20 Fr 1000 ISIE 2t 92 100 4 008 2 02 006 ERD a o 39N343438 YOF NMOHS QUVOG 1931 tog2 SCH ei 18 1 90 6 000 t 9071 DM WEN HI SI HKH SL 0S 20671 86611 1878 21 IO pre 21 EEN I ei ei 69 61 WER 198 28
15. VID n n 1 m mai Vcc max EE EE lt Ta Tb lt Td V min Ta T84 VID Down to Valid V max Tb T82 VID Down to Valid V min Tc T85 VID Up to Valid V max Td T83 VID Up to Valid Vcc min 54 Document Number 318080 002 Electrical Specifications Figure 2 27 VID Step Times and Vcc Waveforms VID Voc max Document Number 318080 002 Ta Tb Tc Td Te Tf Voc min Td V min n 3 T80 VID Step Time T81 Thermal Monitor 2 Dwell Time T84 VID Down to Valid V max T82 VID Down to Valid V min T85 VID Up to Valid V max T83 VID Up to Valid V min Note This waveform illustrates an example of an Intel Thermal Monitor 2 transition or an Intel Enhanced SpeedStep Technology transition that is six VID steps down from the current state and six steps back up Any arbitrary up or down transition can be generalized from this waveform Voc max n 4 55 56 Electrical Specifications Document Number 318080 002 5 Mechanical Specifications n tel 3 Figure 3 1 Note 3 1 Mechanical Specifications The Intel Xeon Processor 7200 Series and 7300 Series is packaged in a FC mPGA6 package that interfaces with the motherboard via a mPGA604 socket The package consists of two processor dies mounted on a substrate pin carrier An IHS is attached to the pa
16. 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vu is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low 3 Vii is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high 4 Vin and Voy may experience excursions above V However input signal drivers must comply with the signal quality specifications 5 This is the pull down driver resistance Refer to processor O Buffer Models for I V characteristics Measured at 0 31 V Ron min 0 225 R rr Ron typ 0 250 R7 Ron max 0 275 R r 6 GTLREF should be generated from Ver with a 1 tolerance resistor divider The Vr referred to in these specifications is the instantaneous Vr 7 Specified when on die Rz and Roy are turned off ViN between 0 and Ver 8 This is the measurement at the pin Document Number 318080 002 Electrical Specifications Table 2 12 CMOS Signal Input Output Group DC Specifications Symbol Parameter Min Typ Max Units Notes Vu Input Low Voltage 0 10 0 00 0 3 Vrr V 2 3 Vin Input High Voltage 0 7 V V Vrr 0 1 V 2 VoL Output Low Voltage 0 10 0 0 1 V V 2 Vou Output High Voltage 0 9 V V Vrr 0 1 V 2 lo Output Low Current 1 70 N A 4 70 mA 4 lou Output High Current 1 70 N A 4 70 mA 5 lu Input L
17. Document Number 318080 002 Electrical Specifications Figure 2 17 FSB Source Synchronous 2X Address Timing Waveform BCLK1 BCLK0 ADSTB driver A driver ADSTB receiver Adt receiver TO TJA T 2 3T 4 Ti E Tk valid Tp T1 BCLK 1 0 Period Ty T23 Source Sync Address Output Valid Before Address Strobe Ty T24 Source Sync Address Output Valid After Address Strobe Tk T27 Source Sync Address Strobe Setup Time to BCLK Tu T25 Source Sync Input Setup Time Tn T26 Source Sync Input Hold Time Ts T20 Source Sync Output Valid Delay Tr 131 Address Strobe Output Valid Delay Document Number 318080 002 49 50 intel Electrical Specifications Figure 2 18 FSB Source Synchronous 4X Data Timing Waveform To T 4 TJ2 3T 4 Ti T2 BCLK1 BCLKO DSTBp driver DSTBn driver D driver gt DSTBp O receiver DSTBn O receiver D receiver Tp T1 BCLK 1 0 Period Ta T21 Source Sync Data Output Valid Delay Before Data Strobe Ts T22 Source Sync Data Output Valid Delay After Data Strobe Tc T28 Source Sync Data Strobe Setup Time to BCLK Tp T30 Data Strobe n DSTBN Output Valid Delay Te T25 Source Sync Input Setup Time Te T26 Source Sync Input Hold Time Ty T20 Source Sync Data Output Val
18. During the voltage change it will be necessary to transition through multiple VID codes Document Number 318080 002 m Thermal Specifications n tel Figure 6 6 6 2 4 to reach the target operating voltage Each step will be one VID table entry see Table 2 3 The processor continues to execute instructions during the voltage transition Operation at the lower voltage reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operating point Transition of the VID code will occur first in order to ensure proper operation once the processor reaches its normal operating frequency Refer to Figure 6 6 for an illustration of this ordering Thermal Monitor 2 Frequency and Voltage Ordering True Temperature Frequency Vcc Y Time lt T T hysterisis m gt The PROCHOT signal is asserted when a high temperature situation is detected regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its powe
19. Figure 2 11 Electrical Test Circuit Vtt Vtt Rtt 50 ohms 48 ohms 169 ps in 1200 mils L 1 475nH sal E NNN C 0 85pF Buffer Long Package Rload AC Timings specified at this point Buffer pad TCK Tp T T55 Period V1 V2 For rise and fall times TCK is measured between 20 and 80 points on the waveform V3 TCK is referenced to 0 5 V Document Number 318080 002 Electrical Specifications intel Figure 2 13 Differential Clock Waveform A E A da Ee Overshoot BCLK1 00 wW Rising Edge E A O DE Ringback E N DE Crossing Crossing Ringback Threshold Voltage Voltage Margin Region i PN Pre ee NTE Falling Edge O S de WD ci gi Wik Vds eno Sob aot cad Ringback BCLK0 RENE PIPER M AAA ONE AAN ak GENEE Undershoot T k p Tp T1 BCLK 1 0 period Figure 2 14 Differential Clock Crosspoint Specification Crossing Point mV 650 TR 500 Aen 550 0 5 VHavg 700 400 250 0 5 VHavg 700 350 300 250 200 T T T T T T T T T T T T T T T T T T 1 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg mV Document Number 318080 002 47 intel Electrical Specifications Figure 2 15 BCLK Waveform at Processor Pad and Pin 08 Black is the simulated waveform at the bottom sde o
20. PECI Ground Minimum Hysteresis gt Valid Input Signal Range 2 11 3 Mee Overshoot Specification Processors can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC SENSE and VSS_SENSE pins and across the VCC_SENSE2 and VSS SENSE2 pins Table 2 16 Vcc Overshoot Specifications Symbol Parameter Min Max Units Figure Notes Vos_MAX Magnitude of Vcc overshoot above VI D 50 mV 2 10 Tos MAX Time duration of Vcc overshoot above VID 25 us 2 10 Document Number 318080 002 37 e n tel Electrical Specifications Figure 2 10 Vcc Overshoot Example Waveform 2 11 3 1 2 11 4 38 Example Overshoot Waveform Vi VID 0 050 GE o E o gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID Notes 1 VOS is the measured overshoot voltage 2 TOS is the measured time duration above VID Die Voltage Validation Core voltage VCC overshoot events at the processor must meet the specifications in Table 2 16 when measured across the VCC SENSE and VSS SENSE pins and across the VCC_SENSE2 and VSS_SENSEZ2 pins Overshoot e
21. Priority Agent The priority agent is the host bridge to the processor and is typically known as the chipset Symmetric Agent A symmetric agent is a processor which shares the same I O subsystem and memory array and runs the same operating system as another processor in a system Systems using symmetric agents are known as Symmetric Multiprocessing SMP systems Integrated Heat Spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Thermal Design Power Processor thermal solutions should be designed to meet this target It is the highest expected sustainable power while running known power intensive real applications TDP is not the maximum power that the processor can dissipate Intel 64 Instruction set architecture and programming environment of Intel s 64 bit processors which are a superset of and compatible with A 32 This 64 bit instruction set architecture was formerly known as IA 32 with EM64T or Intel EM64T Platform Environment Control Interface PECI A proprietary one wire bus interface that provides a communication channel between Intel processor and chipset components to external thermal monitoring devices for use in fan speed control PECI communicates readings from the processor s Digital Thermal Sensors DTS The DTS replaces the thermal diode available in previous processors
22. 7 4 3 7 2 RES9 Reserved 9 This location is reserved Writes to this register have no effect Offset 71h 72h Bit Description 15 0 RESERVED 9 7 4 3 7 3 TRDCKS Thermal Reference Data Checksum This location provides the checksum of the Thermal Reference Data Section Writes to this register have no effect Offset 73h Bit Description 7 0 Thermal Reference Data Checksum One Byte Checksum of the Thermal Reference Section 00h FFh See Section 7 4 4 for calculation of the value 134 Document Number 318080 002 Features 7 4 3 8 7 4 3 8 1 7 4 3 8 2 Note 7 4 3 8 3 intel Feature Data This section provides information on key features that the platform may need to understand without powering on the processor Processor Core Feature Flags This location contains a copy of results in EDX 31 0 from Function 1 of the CPUID instruction These details provide instruction and feature support by product family A decode of these bits is found in the AP 485 Intel Processor Identification and CPUID Instruction application note Writes to this register have no effect Example A value of BFEBFBFFh can be found at offset 74 77h Offset 74h 77h Bit Description 31 0 Processor Core Feature Flags 0000h FFFFF Feature Flags Processor Feature Flags This location contains additional feature information from the processor Writes to this registe
23. Launch FMB Figure 2 6 and Figure 2 7 9 Vec poor Default Vcc Voltage for initial power up 1 10 V 2 VVID_STEP VID step size during a transition 12 5 mV Vun SHIFT Total allowable DC load line shift from 450 mV 10 i VID steps Ver FSB termination voltage DC AC 1 14 1 20 1 26 V B 13 specification VccPLL PLL supply voltage DC AC 1 425 1 50 1 605 V specification SM VCC SMBus supply voltage 3 135 3 300 3 465 lec Icc for Quad Core Intel Xeon L7345 60 4 5 6 9 Processor with multiple VID Launch FMB lec RESET lec RESET for Quad Core Intel Xeon 60 A 17 L7345 Processor with multiple VID Launch FMB lec Icc for Dual Core Intel Xeon 90 A 4 5 6 9 Processor 7200 Series with multiple VID Launch FMB lec RESET lec RESET for Dual Core Intel Xeon 90 A 17 i Processor 7200 Series with multiple VID Launch FMB lec Icc for Intel Xeon Processor 7200 90 A 4 5 6 9 Series and 7300 Series with multiple VID Launch FMB lec RESET lec reset for Intel Xeon Processor 90 A 17 gt 7200 Series and 7300 Series with multiple VID Launch FMB lec Icc for Intel Xeon X7350 Processor 130 A 4 5 6 9 with multiple VID Launch FMB lec RESET lec RESET for Intel Xeon X7350 130 A 17 Processor with multiple VID Launch FMB Ism vec Icc for SMBus supply 100 122 5 mA Document Number 318080 002 25 Table 2 9 26 intel Electrical Specifications Voltage and Current Specifications Sheet 2 of 2
24. Die 1 Asserted Not asserted 00 01 Asserted Asserted 10 11 Not asserted Asserted This combination is not supported by the processor Table 6 10 shows how the PECI address is assigned to each of the processors based on the Cluster D 1 0 and Agent D 1 setting at power on PECI Address assigned to processor Cluster ioral APIC wr es icd API C PECI Address 0 0 0x30 0 0 1 0x31 0 1 0 0x32 0 1 1 0x33 1 0 0 0x31 1 0 1 0x30 1 1 0 0x33 1 1 1 0x32 The Intel 7300 Chipset chipset assigns Agent ID Cluster ID as listed below When the Intel Xeon Processor 7200 Series and 7300 Series is used in conjunction with the Intel 7300 Chipset the following PECI device addresses are generated as shown below FSBO Cluster ID 1 0 Agent ID 1 000 PECI address 0x30 FSB1 Cluster ID 1 0 Agent ID 1 010 PECI address 0x32 FSB2 Cluster ID 1 0 Agent ID 1 100 PECI address 0x31 FSB3 Cluster ID 1 0 Agent ID 1 110 PECI address 0x33 The power on configuration POC settings of third party chipsets may produce different PECI addresses than those shown above Thermal designers should consult their third party chipset designers for the correct PECI addresses Please note that each address also supports two domains Domain 0 and Domain 1 PECI Fault Handling Requirements PECI is largely a fault tolerant interface including noise immunity and error checking improvements ove
25. I ntel virtualization Technology Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments inside a single platform VRM Voltage Regulator Module DC DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and current to the processor based on the logic state of the processor VID bits EVRD Enterprise Voltage Regulator Down DC DC converter integrated onto the system board that provides the correct voltage and current to the processor based on the logic state of the processor VID bits Vcc The processor core power supply Vss The processor ground Ver FSB termination voltage Document Number 318080 002 Introduction l n te I 1 2 State of Data This document contains preliminary information on new products in production The specifications are subject to change without notice Verify with your local Intel sales office that you have the latest datasheet before finalizing a design 1 3 References Material and concepts available in the following documents may be beneficial when reading this document Document Document Number Notes AP 485 Intel Processor Identification and the CPUID Instruction 241618 I Intel 64 and IA 32 Architectures Software Developer s Manual 1 Volume 1 Basic Architecture 253665 Volu
26. Output D23 AC23 Source Sync Input Output D63 AB6 Source Sync Input Output D24 AA18 Source Sync Input Output DBIO AC27 Source Sync Input Output D25 AC20 Source Sync Input Output DBI1 AD22 Source Sync Input Output D26 AC21 Source Sync Input Output DBI2 AE12 Source Sync Input Output D27 AE22 Source Sync Input Output DBI3 AB9 Source Sync Input Output D28 AE20 Source Sync Input Output DBSY F18 Common Clk Input Output 72 Document Number 318080 002 Pin Listing Table 4 1 Pin Listing by Pin Name Sheet 5 intel Table 4 1 Pin Listing by Pin Name Sheet 6 of 16 of 16 Pin Name Pin No Signal Direction Pin Name Pin No Signal Direction Buffer Type Buffer Type DEFER C23 Common Clk Input REQ2 C21 Source Sync Input Output DPO AC18 Common Clk Input Output REQ3 C20 Source Sync Input Output DP1 AE19 Common Clk Input Output REQ4 B22 Source Sync Input Output DP2 AC15 Common Clk Input Output Reserved A28 DP3 AE17 Common Clk Input Output Reserved A31 DRDY E18 Common Clk Input Output Reserved B1 DSTBN0 Y21 Source Sync Input Output Reserved B4 DSTBN1 Y18 Source Sync Input Output Reserved B30 DSTBN2 Y15 Source Sync Input Output Reserved C31 DSTBN3 Y12 Source Sync Input Output Reserved D27 DSTBPO Y20 So
27. Quad Core Intel Xeon L7345 Processor Vcc Static and Transient Tolerance Load WINGS EE 33 Dual Core Intel Xeon Processor 7200 Series VCC Static and Transient Tolerance Load Lines u u run ch E ER RRATRERER aia 34 Input Device Hysteresis oocccocccncnccnnonnnnonnnnnnnnncnnnrnrnnnn nr rr r rr rr nr r rr enn memet see senis 37 VCC Overshoot Example VWaveform r rr nennen enn 38 Electrical Test CIECUIE cuiii coit cree ida 46 TEK Clock WaVeto Mii ate 46 Differential Clock Waveform cono nn nennen nnn nn nn nnn 47 Differential Clock Crosspoint Specification eee e 47 BCLK Waveform at Processor Pad and Pin 48 FSB Common Clock Valid Delay Timing Waveform rr 48 FSB Source Synchronous 2X Address Timing Waveform eee 49 FSB Source Synchronous 4X Data Timing Waveform nnn 50 TAP Valid Delay Timing Waveform rr mmemeememememese e enne 51 Test Reset TRST Async GTL Input and PROCHOT Timing Waveform 51 THERMTRIP Power Down Sequence tet ee nner erent neers 51 SMBus Timing Wave Minis pan Eeten a EIEEE EEES E AR EIDER SEE 52 SMBus Valid Delay Timing Waveform r tne ee tetera eter 52 Voltage Sequence Timing Requirements eect eens menn 53 FERR PBE Valid Delay Timing 54 VOS en Lo lu EE 54 VID Step Times and Vcc Waveforms rr nee eme emen nnn 55 Processor Package Assembly Sketch 57 Processor Package Drawing Sheet 1 of2h ns 58 Processor Package
28. Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine the total I7 drawn by the system This parameter is based on design characterization and is not tested lee vrr our iS specified at 1 2 V lec reset is specified while PWRGOOD and RESET are asserted Refer to Table 2 22 for the PWRGOOD to RESET de assertion time specification and Table 2 23 for the RESET Pulse Width specification Figure 2 1 Quad Core Intel Xeon L7345 Processor Load Current versus Time 65 60 55 50 Sustained Current A 45 40 y y 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 2 Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than Icc TDC m ee Not 100 tested Specified by design characterization Document Number 318080 002 27 e n tel Electrical Specifications Figure 2 2 Dual Core Dual Core Intel Xeon Processor 7200 Series Load Current versus Time Sustained Current A 75 70 65 60 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than lec Toc 7 MM 2 Not 10096 tested Specified by design characterization Figure 2 3 Quad Core Intel Xeon Processor 7200 Series and 7300 Series Load Current versus Time
29. ose 60 S8 Cosy 9 18 NOILYMONO 131 40 1N3SNO3 N3LLIUM MOlHd JHI LNOHLIM 035019510 38 LON YW SIN21NOO SLI ONY 3943014802 NI 035079510 S 11 NOLLVMMO NI 1YI1NIQI JNOD NOILVMOQUOD 131 SNIVINOO ONIMYMQ SINL Llaga Zu 262S1V o onol 9 L 8 318080 002 Document Number 62 intel Figure 3 6 Bottom Side Board Keepout Zones Mechanical Specifications y y S 9 L 9 e SWBOJ1Vld NI NOJ NId33M 1H913H IN3NOJWOO XYW NW vG 2 001 SHYO4LYTd 3AO8V NV NZ 303 N1d33M LHOI3H 1N3NOdWO2 XVW WN 90 002 Q3NOT1V 1N3W39V1d 1N3NOdHOO GYVOGYIHLON ON JLYId ONIYdS QZ sr8 99 16 000 2 Pp 8 05 gt y 969 1 T 90 r 8 066 2 DH figg k Z0 8r 000 0 1 66171 I 2 96 611 1 92 81 171 NOISU3A ISS NOILIV2I31234S AVG S21NOHI2313 NIHL JHL NO Q3Sv8 3HV SNOISN3WIQ 3S3Hl 39N343434 804 NMOHS YVO8 1S31 SWYOALV1d NI YOY 1H913H LNINOdWOD XVN WW FS 2 001 SWYOILV 1d 3AO8V NV NZ YOJ NId33N 1H913H IN3NOdWOO XVW WW 80 S 002 q Jadis AYVONOIIS EECHER laa Ea Z6ZSLW al r a S 9 63 Document Number 318080 002 9 30 v 1335 9 LI 262 Am Mechanical Specifications WAU SIHL NI S3JOQNVIS SISSVHD YO S310H ONTLNNOW GYVOE ON 39N343338 801 NMOHS
30. pads All Source synchronous AC timings for AGTL signals are referenced to their associated strobe address or data at nominal GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END Source synchronous data signals are referenced to the falling edge of their associated data strobe Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe All source synchronous AGTL signal timings are referenced at nominal GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END at the processor core pads All AC timings for AGTL strobe signals are referenced to BCLK 1 0 at Vcnoss All AGTL strobe signal timings are referenced at nominal GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END at the processor core pads All AC timings for the TAP signals are referenced to the TCK at 0 5 Vr at the processor pins All TAP signal timings TMS TDI etc are referenced at 0 5 Vy at the processor core pads 5 All CMOS signal timings are referenced at 0 5 Vy at the processor pins 6 All AC timings for the SMBus signals are referenced to the SM_CLK at 0 5 SM_VCC at the processor pins All SMBus signal timings SM_DAT SM_CLK etc are referenced at The circuit used to test the AC specification is shown in Figure 2 11 Document Number 318080 002 45 Figure 2 12 TCK Clock Waveform 46 intel Electrical Specifications
31. socket Processor core Processor core with integrated L1 cache L2 cache and system bus interface are shared between the two cores on the die All AC timing and signal integrity specifications are at the pads of the processor die FSB Front Side Bus The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Multi Independent Bus MIB A front side bus architecture with one processor on each bus rather than a FSB shared between multiple processor agents The MIB architecture provides improved performance by allowing increased FSB speeds and bandwidth Flexible Motherboard Guidelines FMB Are estimates of the maximum values the Intel Xeon Processor 7200 7300 Series will have over certain time periods The values are only estimates and actual specifications for future processors may differ Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC FSB signal quality mechanical and thermal are satisfied Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor pins should not be connected to any supply volt
32. 1 0 frequency The processor bus ratio multiplier is set during manufacturing The default setting is for the maximum speed of the processor The processor core frequency is configured during reset by using values stored internally during manufacturing The stored value sets the highest bus fraction at which the particular processor can operate If lower speeds are desired the appropriate ratio can be configured via the CLOCK FLEX MAX Model Specific Register MSR Clock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK 1 0 input with exceptions for spread spectrum clocking Processor DC and AC specifications for the BCLK 1 0 inputs are provided in Table 2 18 and Table 2 19 respectively These specifications must be met while also meeting signal integrity requirements as outlined in Table 2 18 The processor utilizes differential clocks Table 2 1 contains processor core frequency to FSB multipliers and their corresponding core frequencies Document Number 318080 002 e Electrical Specifications n tel Table 2 1 2 3 1 Table 2 2 2 3 2 2 4 Core Frequency to FSB Multiplier Configuration Core Frequency to FSB Core Frequency with Notes Multiplier 266 MHz FSB Clock 1 6 1 60 GHz 1 2 3 4 1 7 1 86 GHz 1 2 3 1 8 2 13 GHz 1 2 3 1 9 2 40 GHz 1 2 3 1 10 2 66 GHz 1 2 3 1 11 2 93 GHz 1 2 3 Notes 1 Individual p
33. 1 1 1250 10 0 0 1 0 0 0 1 5125 4C 1 0 0 il 1 0 1 1375 OE 0 0 0 1 1 L 1 5250 4A 1 0 0 1 0 1 1 1500 oc 0 0 0 1 1 0 1 5375 48 1 0 0 1 0 0 1 1625 0A 0 0 0 1 0 1 1 5500 46 1 0 0 0 1 il 1 1750 08 0 0 0 1 0 0 1 5625 44 1 0 0 0 1 0 1 1875 06 0 0 0 0 1 L 1 5750 42 il 0 0 0 0 1 1 2000 04 0 0 0 0 1 0 1 5875 40 il 0 0 0 0 0 1 2125 02 0 0 0 0 0 1 1 6000 3E 0 1 1 1 1 1 1 2250 00 0 0 0 0 0 0 OFF Notes 1 When this VID pattern is observed the voltage regulator output should be disabled 2 Shading denotes the expected VID range of the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series 3 The VID range includes VID transitions that may be initiated by thermal events assertion of the FORCEPR signal see Section 6 2 3 Extended HALT state transitions see Section 7 2 2 or Enhanced Intel SpeedStep Technology transitions see Section 7 3 The Extended HALT state must be enabled for the processor to remain within its specifications 4 Once the VRM EVRD is operating after power up if either the Output Enable signal is de asserted or a specific VID off code is received the VRM EVRD must turn off its output the output should go to high impedance within 500 ms and latch off until power is cycled Refer to Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines Document Number 318080 002 19 e n tel Electrical Specifications 2 6 20 Reserved Unus
34. 1 Indicator 2D Matrix FPO Serial Processor Speed Cache Bus TI X7350 2933MP 8M 1066 SLA67 COSTA RICA S Spec C0096109 0021 Country of Assy FPO Serial 13 Characters Notes 1 Character size for laser markings is 21 Point height 1 43 mm 56 mils width 0 95 mm 37 5 mils Document Number 318080 002 Mechanical Specifications 3 9 intel Processor Pin Out Coordinates Figure 3 11 shows the top view of the processor pin coordinates The coordinates are referred to throughout the document to identify processor pins Figure 3 11 Processor Pin Out Coordinates Top View Document Number 318080 002 COMMON ADDRESS COMMON Async CLOCK CLOCK JTAG 1 3 5 7 9 1 13 15 17 19 21 23 25 27 29 3l OOO QOO0 0 oOOe ooOoOm0pOOOg OOe oo leooOeoeeoOoesejA Oeooo0oooeooeooeoecloeooelooooooooO0B oooeeo ooeooeoooocleooeocloeoooeeoc O O O O O Q e O O O O O O O O Oje O O O e e D eocooooooexeooooeoeooeooeoooogeobeE 0000000000000 00000460 000000000060 0F 000000000 O 09 e 0 e o e o eG 000000000 000000000 y 000000000 e 0 e o e o e o 9 J 000000000 000000009 2 000000000 e e n np lt gt 0000 00080 Processor eeoevevenu 8 8 000000000 e0c0e00000N E gt 00000000 e0 00 00P 4 009000000 Top View 000000000R e00000000 0000000007 000000000 ecooeo ne y 000000000 eoceoeoceoey eeoeoiooo00 cCeoeoeoeo0 Ww eoeeoceloeocoeo ooeooe
35. 2 This filtering algorithm is fixed and cannot be changed It is on by default and can be turned off in BIOS Host controllers should utilize the min max sample times to determine the appropriate sample rate based on the controller s fan control algorithm and targeted response rate The key items to take into account when settling on a fan control algorithm are the DTS sample rate whether the temperature filter is enabled how often the PECI host will poll the processor for temperature data and the rate at which fan speed is changed Depending on the designer s specific requirements the DTS sample rate and alpha beta filter may have no effect on the fan control algorithm PECI Specifications PECI Device Address The Intel Xeon Processor 7200 Series and 7300 Series obtains its PECI address based on the processor APIC ID 4 2 at power on APIC ID 4 3 is also known as Cluster ID 1 0 and APIC ID 2 is also known as Agent ID 1 Cluster ID 1 0 is set by the chipset driven power on configuration POC signals A 12 11 Table 6 9 shows how the Agent ID is generated for each of the die based on the BREQ signals asserted during power on for the Intel Xeon Processor 7200 Series and 7300 Series Document Number 318080 002 Thermal Specifications Table 6 9 Table 6 10 6 3 2 2 BREQ signal assertion during power on intel Not asserted Not asserted BREQ0 BREQ1 Agent D 1 0 Die O Agenti D 1 0
36. 2 9 For further information regarding power delivery decoupling and layout guidelines refer to the appropriate platform design guidelines Mo Decoupling Bulk decoupling must be provided on the baseboard Decoupling solutions must be sized to meet the expected load To ensure optimal performance various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution consists of a combination of low ESR bulk capacitors and high frequency ceramic capacitors For further information regarding power delivery decoupling and layout guidelines refer to the appropriate platform design guidelines Front Side Bus AGTL Decoupling The processor integrates signal termination on the die as well as a portion of the required high frequency decoupling capacitance on the processor package However additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the FSB Bulk decoupling must also be provided by the baseboard for proper AGTL bus operation Decoupling guidelines are described in the appropriate platform design guidelines Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous processor generations the processor core frequency is a multiple of the BCLK
37. BPM1 F8 Common Clk Output BPM2 E7 Common Clk Output BPM3 F5 Common Clk Input Output BPM4 E8 Common Clk Output BPM5 E4 Common Clk Input Output BPMb0 AA4 Common Clk Input Output BPMb1 AC1 Common Clk Output BPMb2 AE2 Common Clk Output 71 intel Table 4 1 Pin Listing by Pin Name Sheet 3 Pin Listing Table 4 1 Pin Listing by Pin Name Sheet 4 of 16 of 16 Pin Name Pin No Signal Direction Pin Name Pin No Signal Direction Buffer Type Buffer Type BPMb3 AE3 Common Clk Input Output D29 AD21 Source Sync Input Output BPRI D23 Common Clk Input D30 AD19 Source Sync Input Output BRO D20 Common Clk Input Output D31 AB17 Source Sync Input Output BR1 F12 Common Clk Input Output D32 AB16 Source Sync Input Output BSELO AA3 Power Other Output D33 AA16 Source Sync Input Output BSEL1 AB3 Power Other Output D34 AC17 Source Sync Input Output BSEL2 Y31 Power Other Output D35 AE13 Source Sync Input Output COMP0 D25 Power Other Input D36 AD18 Source Sync Input Output COMP1 E16 Power Other Input D37 AB15 Source Sync Input Output COMP2 AE15 Power Other Input D38 AD13 Source Sync Input Output COMP3 AE16 Power Other Input D39 AD14 Source Sync Input Output DO Y26 Source Sync Input Output D40 AD11 Source Sync Input Output D1 AA27 Source Sync Input Output D41 AC1
38. IA 32 Architectures Software Developer s Manual Volume IIl System Programming Guide for more information The system can generate a STPCLK while the processor is in the HALT state When the system deasserts STPCLK the processor will return execution to the HALT state While in HALT state the processor will process front side bus snoops and interrupts Extended HALT State Extended HALT state is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT state has been enabled via the BIOS When one of the processor cores executes the HALT instruction that processor core is halted however the other processor cores continue normal operation The Extended HALT state is a lower power state than the HALT state or Stop Grant state The Extended HALT state must be enabled for the processor to remain within its specifications Not all Intel Xeon Processor 7200 Series and 7300 Series are capable of supporting Extended HALT State More detail on which processor frequencies will support this feature will be provided in future releases of the Intel Xeon Processor 7200 7300 Series Specification Update when available The processor will automatically transition to a lower core frequency and voltage operating point before entering the Extended HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state th
39. Output A10 A13 Source Sync Input Output A11 B16 Source Sync Input Output A12 B14 Source Sync Input Output A13 B13 Source Sync Input Output A14 A12 Source Sync Input Output A15 C15 Source Sync Input Output A16 C14 Source Sync Input Output A17 D16 Source Sync Input Output A18 D15 Source Sync Input Output A19 F15 Source Sync Input Output A20 A10 Source Sync Input Output A21 B10 Source Sync Input Output A22 B11 Source Sync Input Output A23 C12 Source Sync Input Output A24 E14 Source Sync Input Output A25 D13 Source Sync Input Output A26 A9 Source Sync Input Output A27 B8 Source Sync Input Output A28 E13 Source Sync Input Output A29 D12 Source Sync Input Output A30 C11 Source Sync Input Output of 16 Pin Name Pin No Signal Direction Buffer Type A31 B7 Source Sync Input Output A32 A6 Source Sync Input Output A33 A7 Source Sync Input Output A34 C9 Source Sync Input Output A35 C8 Source Sync Input Output A36 F16 Source Sync Input Output A37 F22 Source Sync Input Output A38 B6 Source Sync Input Output A39 C16 Source Sync Input Output A20M F27 Async GTL Input ADS D19 Common Clk Input Output ADSTB0 F17 Source Sync Input Output ADSTB1 F14 Source Sync Input Output AP0 E10 Common Clk Input Output AP1 D9 Common Clk Input Output BCLKO Y4 FSB Clk Input BCLK1 w5 FSB Clk Input BINI T F11 Common Clk Input Output BNR F20 Common Clk Input Output BPM0 F6 Common Clk Input Output
40. Power Other REQ1 B21 Source Sync Input Output SM VCG e Fower Other Document Number 318080 002 73 intel Table 4 1 Pin Listing by Pin Name Sheet 7 Pin Listing Table 4 1 Pin Listing by Pin Name Sheet 8 of 16 of 16 Pin Name Pin No Signal Direction Pin Name Pin No Signal Direction Buffer Type Buffer Type SM_WP AD29 SMBus Input Vcc G24 Power Other SMI C27 Async GTL Input Vcc G26 Power Other STPCLK D4 Async GTL Input Vcc G28 Power Other TCK E24 TAP Input Vcc G30 Power Other TDI C24 TAP Input Vcc H1 Power Other TDO E25 TAP Output Vcc H3 Power Other TESTHIO A16 Power Other Input Vcc H5 Power Other TESTHI1 w3 Power Other Input Vcc H7 Power Other TESTIN1 D1 Power Other Input Vcc H9 Power Other TESTI N2 C2 Power Other Input Vcc H23 Power Other THERMTRI P F26 Async GTL Output Vcc H25 Power Other TMS A25 TAP Input Vcc H27 Power Other TRDY E19 Common Clk Input Vcc H29 Power Other TRST F24 TAP Input Vcc H31 Power Other Vcc A8 Power Other Vcc J2 Power Other Vcc A14 Power Other Vcc J4 Power Other Vcc A18 Power Other Vcc J6 Power Other Vcc A24 Power Other Vcc J8 Power Other Vcc B20 Power Other Vcc J24 Power Other Vcc C4 Power Other Vcc J26 Power Other Vcc C22 Power Other Vcc J28 Power Other Vcc C30 Power Other Vcc J30 Power Other Vcc D8 Power Other Vcc K1 Power Other Vcc D14 Power O
41. Power Other Vss AE11 Power Other Vss w4 Power Other Vss AE21 Power Other Vss W24 Power Other Vss AE27 Power Other Vss W26 Power Other Vss_SENSE D26 Power Other Output Vss W28 Power Other Vss sENSE2 B26 Power Other Output Vss W30 Power Other Ver A4 Power Other Vss Y1 Power Other Vit B5 Power Other Vss Y3 Power Other Ver B12 Power Other Vss Y5 Power Other Ver C5 Power Other Vss Y7 Power Other Vit C10 Power Other Vss Y13 Power Other Vir D10 Power Other Vss Y19 Power Other Ver E11 Power Other Vss Y25 Power Other Vit E12 Power Other Vss AA2 Power Other Vir F10 Power Other Vss AA9 Power Other Ver W Power Other Vss AA15 Power Other Vit w7 Power Other Vss AA17 Power Other Ver w8 Power Other Vss AA23 Power Other Ver Y6 Power Other Vss AA30 Power Other Ver Y10 Power Other Vss AB1 Power Other Vit AAT Power Other Vss AB5 Power Other Ver AAT 3 Power Other Vss AB11 Power Other Ver AC4 Power Other Vss AB21 Power Other Vit AC10 Power Other Vss AB27 Power Other Ver AD5 Power Other Vss AB31 Power Other Ver AD12 Power Other Vss AC2 Power Other Vit AE4 Power Other Vss AC7 Power Other Ver AE5 Power Other Vss AC13 Power Other VTT_SEL A2 Power Other Output Vss AC19 Power Other Vss AC25 Power Other Document Number 318080 002 intel Pin Listing 4 1 2 Pin Listing by Pin Number Table 4 2 Pin Listing by Pin Number Sheet Table 4 2 Pin Listing by Pin Number Sheet
42. STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to Vol 3 of the lA 32 Intel E Architecture Software Developer s Manual and the AP 485 Intel Processor Identification and the CPUID Instruction application note FORCEPR l The FORCEPR force power reduction input can be used by the platform to cause the Intel Xeon Processor 7200 Series and 7300 Series to activate the Thermal Control Circuit TCC GTLREF_ADD_MID l GTLREF_ADD determines the signal reference level for AGTL address and common GTLREF ADD END clock input pins GTLREF_ADD is used by the AGTL receivers to determine if a signal B B is a logical 0 or a logical 1 Please refer to Table 2 17 and the appropriate platform design guidelines for additional details GTLREF DATA MID l GTLREF_DATA determines the signal reference level for AGTL data input pins GTLREF DATA END GTLREF_DATA is used by the AGTL receivers to determine if a signal is a logical 0 or lt z a logical 1 Please refer to Table 2 17 and the appropriate platform design guidelines for additional details HIT 1 0 HIT Snoop Hit and HITM Hit Modified convey transaction sno
43. Series Thermal Mechanical Design Guide for details on system thermal solution design thermal profiles and environmental considerations For the Quad Core Intel Xeon X7350 Processor Intel has developed a thermal profile which must be met to ensure adherence to Intel reliability requirements The Thermal Profile see Figure 6 2 Table 6 4 is representative of a volumetrically unconstrained thermal solution that is industry enabled 2U heatsink In this scenario it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Intel has developed the thermal profile to allow customers to choose the thermal solution and environmental parameters that best suit their platform implementation Refer to the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series Thermal Mechanical Design Guide for details on system thermal solution design thermal profiles and environmental considerations The upper point of the thermal profile consists of the Thermal Design Power TDP and the associated Tcase value It should be noted that the upper point associated with Quad Core Intel Xeon X7350 Processor Thermal Profile x TDP and y TcASE MAX P TDP represents a thermal solution design point In actuality the processor case temperature will not reach this value due to TCC activation see Figure 6 2 for Quad Core Intel X
44. byte ROM 128 Byte ROM Checksum Values Section Checksum Address Header ODh Processor Data 15h Processor Core Data 24h Cache Data 31h Package Data 37h Part Number Data 6Fh Thermal Ref Data 73h Feature Data 7Fh Checksums are automatically calculated and programmed by Intel The first step in calculating the checksum is to add each byte from the field to the next subsequent byte This result is then negated to provide the checksum Example For a byte string of AA445Ch the resulting checksum will be B6h AA 10101010 44 01000100 5C 0101100 AA 44 5C 01001010 Negate the sum 10110101 1 101101 B6h Scratch EEPROM Also available in the memory component on the processor SMBus is an EEPROM which may be used for other data at the system or processor vendor s discretion The data in this EEPROM once programmed can be write protected by asserting the active high SM WP signal This signal has a weak pull down 10 kQ to allow the EEPROM to be programmed in systems with no implementation of this signal The Scratch EEPROM resides in the upper half of the memory component addresses 80 FFh The lower half comprises the Processor Information ROM addresses 00 7Fh which is permanently write protected by Intel Document Number 318080 002 137 intel 138 Document Number 318080 002 Boxed Processor Specifications n te L 8 8 1 8 2 8 2 1 Boxed Processor Spec
45. details are fully described in the appropriate platform design guidelines refer to Section 1 3 Terminology A 3t symbol after a signal name refers to an active low signal indicating a signal is in the asserted state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Commonly used terms are explained here for clarification Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology is the next generation implementation of the Geyserville technology which extends power management capabilities of servers e FC mPGA6 The Intel Xeon Processor 7200 Series and 7300 Series package is available in a Flip Chip Micro Pin Grid Array 6 package consisting of a processor core mounted on a pinned substrate with an integrated heat spreader IHS This packaging technology employs a 1 27 mm 0 05 in pitch for the substrate pins e mPGA604 The Intel Xeon Processor 7200 Series and 7300 Series package mates with the system board through this surface mount 604 pin zero insertion force ZIF
46. electrical and functional constraints on the debug port that must be followed The mechanical constraint requires the debug port connector to be installed in the system with adequate physical clearance Electrical constraints exist due to the mixed high and low speed signals of the debug port for the processor While the JTAG signals operate at a maximum of 75 MHz the execution signals operate at the common clock FSB frequency The functional constraint requires the debug port to use the JTAG system via a handshake and multiplexing scheme In general the information in this chapter may be used as a basis for including all run control tools in Intel Xeon Processor 7200 Series and 7300 Series based systems designs including tools from vendors other than Intel The debug port and J TAG signal chain must be designed into the processor board to utilize the XDP for debug purposes except for interposer solutions Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Intel Xeon Processor 7200 Series and 7300 Series systems Tektronix and Agilent should be contacted to obtain specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Intel Xeon Processor 7200 Series and 7300 Series based multiprocessor systems
47. recognize the proper signal state See Section 2 11 and Section 2 12 for the DC and AC specifications See Section 7 for additional timing requirements for entering and leaving the low power states Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor s be first in the TAP chain and followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Similar considerations must be made for TCK TMS and TRST Two copies of each signal may be required with each driving a different voltage level Document Number 318080 002 Electrical Specifications 2 9 Note 2 10 Table 2 8 intel Mixing Processors Intel supports and validates multi processor configurations only in which all processors operate with the same FSB frequency core frequency number of cores and have the same internal cache sizes Mixing components operating at different internal clock frequencies or number of cores is not supported and will not be validated by Intel Processors within a system must operate at the same frequency per bits 12 8 of the CLOCK_FLEX_MAX MSR however this does not apply to frequency transitions initiated due to thermal events Extended HALT Enhanced Intel SpeedStep tech
48. same offset temperature format as PECI though it contains no sign bit Thermal management devices should infer the TcontroL value as negative Thermal management algorithms should utilize the relative temperature value delivered over PECI in conjunction with the MSR value to control or optimize fan speeds Figure 6 8 shows a conceptual fan control diagram using PECI temperatures 107 e n tel Thermal Specifications Figure 6 8 Conceptual Fan Control Diagram For a PECI Based Platform 6 3 1 2 6 3 2 6 3 2 1 108 TeontroL TCC Activation Setting Temperature Fan Speed RPM Temperature not intended to depict actual implementation Processor Thermal Data Sample Rate and Filtering The DTS Digital Thermal Sensors provide an improved capability to monitor device hot spots which inherently leads to more varying temperature readings over short time intervals The DTS sample interval range can be modified and a data filtering algorithm can be activated to help moderate this The DTS sample interval range is 82 us default to 20 ms max This value can be set in BIOS To reduce the sample rate requirements on PECI and improve thermal data stability vs time the processor DTS also implements an averaging algorithm that filters the incoming data This is an alpha beta filter with coefficients of 0 5 and is expressed mathematically as Current_filtered_temp Previous_filtered_temp 2 new_sensor_temp
49. the LAI is critical in providing the ability to probe and capture FSB signals There are two sets of considerations to keep in mind when designing a Intel Xeon Processor 7200 Series and 7300 Series based system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI plugs into the socket while the processor plugs into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system In some cases it is known that some of the electrolytic capacitors fall inside of the keepout volume for the LAI In this case it is necessary to move these capacitors to the backside of the board before using the LAI Additionally note that it is possible that the keepout volume reserved for the LAI may include different requirements from the space normally occupied by the heatsink If this is the case the logic analyzer vendor will provide either a cooling solution as part of the LAI or additional hardware to mount the existing cooling solution Document Number 318080 002 141 e n tel Debug Tools Specifications
50. the processor to switch between multiple frequency and voltage points which results in platform power savings Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform Switching between voltage frequency states is software controlled Not all Intel Xeon Processor 7200 Series and 7300 Series may be capable of supporting Enhanced Intel SpeedStep Technology More details on which processor frequencies will support this feature will be provided in future releases of the Intel Xeon Processor 7200 7300 Series Specification Update when available Document Number 318080 002 115 intel 7 4 Note 116 Enhanced Intel SpeedStep Technology creates processor performance states P states or voltage frequency operating points P states are lower power capability states within the Normal state as shown in Figure 7 1 Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system The Intel Xeon Processor 7200 Series and 7300 Series have hardware logic that coordinates the requested voltage VID between the processor cores The highest voltage requested from the four processor cores is selected for th
51. us 2 23 T97 SMBus Input Setup Time 250 N A ns 2 22 T98 SMBus Input Hold Time 300 N A ns 2 22 T99 Bus Free Time 4 7 N A us 2 22 4 5 T100 Hold Time after Repeated Start Condition 4 0 N A us 2 22 T101 Repeated Start Condition Setup Time 4 7 N A us 2 22 T102 Stop Condition Setup Time 4 0 N A us 2 22 Notes 1 These parameters are based on design characterization and are not tested 2 All AC timings for the SMBus signals are referenced at Vu max OF V L min and measured at the processor pins Refer to Figure 2 23 S 7 3 Rise time is measured from Vi max 0 15V to Vig min 0 15V Fall time is measured from 0 9 SM VCC to Vi max 0 15V DC parameters are specified in Table 2 26 4 Minimum time allowed between request cycles 5 Following a write transaction an internal write cycle time of 10ms must be allowed before 44 starting the next transaction Document Number 318080 002 Electrical Specifications n tel 2 13 Note Processor AC Timing Waveforms The following figures are used in conjunction with the AC timing tables Table 2 19 through Table 2 25 For Figure 2 12 through Figure 2 25 the following apply 1 All common clock AC timings for AGTL signals are referenced to the Crossing Voltage Vcnoss of the BCLK 1 0 at rising edge of BCLK0 All common clock AGTL signal timings are referenced at nominal GTLREF_DATA_ MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END at the processor core
52. with or without this feature Updated PROC ID 1 0 Definition 8 Document Number 318080 002 Introduction 1 intel Introduction ALL INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE The Intel Xeon Processor 7200 Series and 7300 Series are multi processor servers utilizing four Intel Core microarchitecture cores These processors are based on Intel s 65 nanometer process technology combining high performance with the power efficiencies of a low power microarchitecture The Quad Core Intel Xeon 7300 Series consists of two die each die containing two processor cores The Dual Core Intel Xeon 7200 Series consists of two die each die containing one processor core All processors maintain the tradition of compatibility with 1A 32 software Some key features include on die 64 KB Level 1 instruction data caches per die and 2x4MB shared Level 2 cache with Advanced Transfer Cache Architecture The processor s Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs resulting in reduced bus cycle penalties and improved performance The 1066 MHz Front Side Bus FSB is a quad pumped bus running off a 266 MHz system clock making 8 5 GBytes per second data transfer rates possible The Quad Core Intel Xeon X7350 processor offers higher clock frequencies than the other Quad Core Intel Xeon Processor 7300 Series for platforms that are targeted for the performance op
53. 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 1 0 DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within within a 16 bit group would have been asserted electronically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment to Data Bus Bus Signal Data Bus Signals DBIO D 15 0 DBI1 D 31 16 DBI2 D 47 32 DBI3 D 63 48 DBSY 1 0 DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor FSB agents DEFER l DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or I O agent This signal must connect the appropriate pins of all processor FSB agents DP 3 0 1 0 DP 3 0 Data Parity provide parity protection for the D 63 0 signals They ar
54. 00000000000000000000 001 000000 000000 P 000000 09909 F C vL 8L ES EH 000000 000000 998999 388899 3 6 996 1 4 GE GE Ge ae 000000 000000 lee IR NI 299999 399999 MW l H BI Besse EEA INIILNO A 18N35SVS10 1000 00000 900000 Ion Cl 000000 O00000 D 000000 000000 90 9 000000 100000 9000001 O00000 000000 100000 H N 000000 1990000 a N O 967 J je A 310H un ONILNNON 305932084 100 pa LI a i 20 0 g 1019 Xp J o 9 0ST 1 Nid 134908 R 22 r 006 311100 WNISLW3H 6 88 4 1N3Wn200 3lv vd3s NO NMOHS 38 TM 1004333 NOILWIN938 39Y110A Q31Y3931N S 32N383438 YOS NWOHS QNVOO 1631 E EE IMOAVT AYM Z ONY 709 134206 NO Q3SY8 SNOISNIWIO Ir Keren S3HONI NI Q31V1S SNOISN3NIG 9690 03132V88 SYJLINITIIN NI Q31VIS SNOISNGMIQ AUVNIYd 661 G P1A ISNV Y3d S32NVH3101 ONY NOISN3MIQ TIV 2 37113 Q311440S H3AO 3283039384 3MV1 ONIMYHO SIHL NO 01441 y S30NV83101 NV SNOISN3AIQ TV 3114 3SY8YlVQ q 03114408 HLIM NOIIN138NOD NI GISA 38 Ol ONIMVWO SIHI 7I JAIS AUVWIUd 318V1 AJY u01 9 39vg 335 w SALON AMOISH NOISIA3H S1N31N02 SLI ONY 32N30 3NOD NI Q3SO12S1Q SI 11 NOIIVWSOJNI 1VI1N301 3NO NOI1VHOdUOO TILNI SNIVINOO ONIMYHO SIHL BESSE Se 3 7 a 61 318080 002 Document Number Mechanical Specifications intel Figure 3 5 Top Side Board Keepout Zones Part 2
55. 0b 111111b Reserved 1 0 Sample Production Sample or Production indictor 00b Sample 01b Production 10b 11b Reserved PDCKS Processor Data Checksum This location provides the checksum of the Processor Data Section Writes to this register have no effect Offset 15h Bit Description 7 0 Processor Data Checksum One Byte Checksum of the of Processor Data Section 00h FFh See Section 7 4 4 for calculation of the value Processor Core Data This section contains core silicon related data CPUI D CPUID This location contains the CPUID Processor Type Family Model and Stepping The CPUID field is a copy of the results in EAX 27 0 from Function 1 of the CPUID instruction The MSB is at location 16h the LSB is at location 19h Writes to this register have no effect The field is not aligned on a byte boundary since the first two bits of the offset are reserved Thus the data must be shifted left by two in order to obtain the same results Example The CPUID of a G 0 stepping Intel Xeon Processor 7200 Series and 7300 Series is O6FBh The value programmed into the PIROM is 00001BECh The first two bits of the PIROM are reserved as highlighted in the example below CPUID instruction results 0000 0110 1111 1011 06F9h PI ROM content 0001 1011 1110 1100 1BECh Document Number 318080 002 Se intel Offset 16h 19h Bit Description 31 30 Reserved 00b 11b Rese
56. 1 3 The AGTL inputs require reference voltages GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END which are used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF_DATA_MID and GTLREF_DATA_END are used for the 4X front side bus signaling group and GTLREF_ADD_MID and GTLREF_ADD_END are used for the 2X and common clock front side bus signaling groups GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END must be generated on the baseboard See Table 2 17 for GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END specifications Refer to the applicable platform design guidelines for details Termination resistors Ry for AGTL signals are provided on the processor silicon and are terminated to VTT The on die termination resistors are always enabled on the processor to control reflections on the transmission line Intel chipsets also provide on die termination thus eliminating the need to terminate the bus on the baseboard for most AGTL signals Some FSB signals do not include on die termination Rrr and must be terminated on the baseboard See Table 2 4 and Table 2 6 for details regarding these signals The AGTL bus depends on incident wave switching Therefore timing calculations for AGTL signals are based on flight time as opposed to capacitive deratings Analog signal simulation of the FSB including trace lengths is highly recommended when designing a system Co
57. 12 of 16 Pin Name Pin No SERA Direction Pin Name Pin No ds Direction Vcc AB14 Power Other Vss D11 Power Other Vcc AB18 Power Other Vss D21 Power Other Vcc AB24 Power Other Vss D28 Power Other Vcc AB30 Power Other Vss D30 Power Other Vcc AC3 Power Other Vss El Power Other Vcc AC16 Power Other Vss E9 Power Other Vcc AC22 Power Other Vss E15 Power Other Vcc AC31 Power Other Vss E17 Power Other Vcc AD2 Power Other Vss E23 Power Other Vcc AD20 Power Other Vss E29 Power Other Vcc AD26 Power Other Vss E31 Power Other Vcc AE14 Power Other Vss F2 Power Other Vcc AE18 Power Other Vss F3 Power Other Vcc AE24 Power Other Vss F7 Power Other VccPLL AD1 Power Other Input Vss F13 Power Other Vcc_sENSE B27 Power Other Output Vss F19 Power Other Vcc sENSE2 A26 Power Other Output Vss F25 Power Other VID1 E3 Power Other Output Vss F28 Power Other VID2 D3 Power Other Output Vss F30 Power Other VID3 C3 Power Other Output Vss G1 Power Other VID4 B3 Power Other Output Vss G3 Power Other VID5 Al Power Other Output Vss G5 Power Other VID6 C1 Power Other Output Vss G7 Power Other Vss A5 Power Other Vss G9 Power Other Vss A11 Power Other Vss G25 Power Other Vss A21 Power Other Vss G27 Power Other Vss A27 Power Other Vss G29 Power Other Vss A29 Power Other Vss G31 Power Other Vss B2 Power Other Vss H2 Power Other Vss B9 Power Other Vss H4 Power Other Vss B15 Power Other Vss H6 Power Other Vss B17 Power Other Vss H8 Power Other Vss B23 Power Other
58. 2 119 intel Table 7 6 120 Features Processor Information ROM Data Sections Sheet 2 of 3 Offset Section edid Function Notes 2 Reserved Reserved for future use 2 Processor Core Type From CPUID 4 Processor Core Family From CPUID 4 Processor Core Model From CPUID 4 Processor Core Stepping From CPUID 2 Reserved Reserved for future use 1A 1Bh 16 Front Side Bus Speed 16 bit binary number in MHz 1Ch 2 Multiprocessor Support 00b UP 01b DP 10b RSVD 11b MP 6 Reserved Reserved 1D 1Eh 16 Maximum Core Frequency 16 bit binary number in MHz 1F 20h 16 Maximum Core VID Maximum Vcc requested by VID outputs in m 21 22h 16 Minimum Core Voltage Minimum processor DC Vcc in mV 23h 8 Tcase Maximum Maximum case temperature spec in C 24h 8 Checksum 1 byte checksum Cache Data 25 26h 16 Reserved Reserved for future use 27 28h 16 L2 Cache Size 16 bit binary number in KB 29 2Ah 16 L3 Cache Size 16 bit binary number in KB 2B 2Ch 16 Maximum Cache CVID Maximum VcacHE requested by CVID outputs in mV 2D 2Eh 16 Minimum Cache Voltage Minimum processor DC VcAcug in mV 2F 30h 16 Reserved Reserved 31h 8 Checksum 1 byte checksum Package Data 32 35h 32 Package Revision Four 8 bit ASCII characters 36h 8 Reserved Reserved for future use 37h 8 Checksum 1 byte checksum Part Number Data 38 3Eh 56 Processor Part Numb
59. 2 3 45 VID 0 056 VID 0 071 VID 0 086 1 2 3 50 VID 0 069 VID 0 084 VID 0 099 1 2 55 VID 0 069 VID 0 077 VID 0 093 1 2 3 60 VID 0 075 VID 0 090 VID 0 105 1 2 65 VID 0 081 VID 0 096 VID 0 111 1 2 3 4 70 VID 0 087 VID 0 103 VID 0 118 1 2 3 4 75 VID 0 094 VID 0 109 VID 0 124 1 2 3 4 80 VID 0 100 VID 0 115 VID 0 130 1 2 3 4 85 VID 0 106 VID 0 121 VID 0 136 1 2 3 4 90 VID 0 113 VID 0 128 VID 0 143 1 2 3 4 95 VID 0 119 VID 0 134 VID 0 149 1 2 3 4 5 100 VID 0 125 VID 0 140 VID 0 155 1 2 3 4 5 105 VID 0 131 VID 0 146 VID 0 161 1 2 3 4 5 110 VID 0 138 VID 0 153 VID 0 168 1 2 3 4 5 115 VID 0 144 VID 0 159 VID 0 174 1 2 3 4 5 120 VID 0 150 VID 0 165 VID 0 180 1 2 3 4 5 125 VID 0 156 VID 0 171 VID 0 186 1 2 3 4 5 130 VID 0 163 VID 0 178 VID 0 193 1 2 3 4 5 Notes 1 The Vcc min and Vec max loadlines represent static and transient limits Please see Section 2 11 3 for Vcc overshoot specifications 2 This table is intended to aid in reading discrete points on Figure 2 5 for Intel Xeon Processor 7200 Series and 7300 Series Figure 2 6 for Intel Xeon X7350 Processor Figure 2 7 for Quad Core Intel Xeon L7345 Processor and Figure 2 8 for Dual Core Intel Xeon Processor 7200 Series 3 The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE pins and across the VCC_SENSE2 and VSS_SENSEZ2 pins Voltage regu
60. 2 Source Sync Input Output D2 Y24 Source Sync Input Output D42 AE10 Source Sync Input Output D3 AA25 Source Sync Input Output D43 AC11 Source Sync Input Output D4 AD27 Source Sync Input Output D44 AE9 Source Sync Input Output D5 Y23 Source Sync Input Output D45 AD10 Source Sync Input Output D6 AA24 Source Sync Input Output D46 AD8 Source Sync Input Output D7 AB26 Source Sync Input Output D47 AC9 Source Sync Input Output D8 AB25 Source Sync Input Output D48 AA13 Source Sync Input Output D9 AB23 Source Sync Input Output D49 AA14 Source Sync Input Output D10 AA22 Source Sync Input Output D50 AC14 Source Sync Input Output D11 AA21 Source Sync Input Output D51 AB12 Source Sync Input Output D12 AB20 Source Sync Input Output D52 AB13 Source Sync Input Output D13 AB22 Source Sync Input Output D53 AA11 Source Sync Input Output D14 AB19 Source Sync Input Output D54 AA10 Source Sync Input Output D15 AA19 Source Sync Input Output D55 AB10 Source Sync Input Output D16 AE26 Source Sync Input Output D56 AC8 Source Sync Input Output D17 AC26 Source Sync Input Output D57 AD7 Source Sync Input Output D18 AD25 Source Sync Input Output D58 AE7 Source Sync Input Output D19 AE25 Source Sync Input Output D59 AC6 Source Sync Input Output D20 AC24 Source Sync Input Output D60 AC5 Source Sync Input Output D21 AD24 Source Sync Input Output D61 AA8 Source Sync Input Output D22 AE23 Source Sync Input Output D62 Y9 Source Sync Input
61. 2 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processors chipset and clock synthesizer All FSB agents must operate at the same frequency For more information about these signals including termination recommendations refer to the appropriate platform design guideline COMP 3 0 l COMP 3 0 must be terminated to VSS on the baseboard using precision resistors These inputs configure the AGTL drivers of the processor Refer to the appropriate platform design guidelines for implementation details 88 Document Number 318080 002 Signal Definitions intel Table 5 1 Signal Definitions Sheet 3 of 8 Name Type Description Notes D 63 0 1 0 D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor FSB agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to strobes and DBI DSTBN Data Group DSTBP DBI D 15 0 0
62. 25 Source Sync Input Output AD29 SM WP SMBus Input AC21 D26 Source Sync Input Output AD30 Reserved AC22 Vcc Power Other AD31 Reserved AC23 D23 Source Sync Input Output AE2 BPMb2 Common Clk Output AC24 D20 Source Sync Input Output AE3 BPMb3 Common Clk Input Output AC25 Vss Power Other AE4 V Power Other AC26 D17 Source Sync Input Output AE5 V Power Other AC27 DBIO Source Sync Input Output AE6 Vss Power Other Input AC28 SM_CLK SMBus Input AE7 D58 Source Sync Input Output AC29 SM_DAT SMBus Output AE8 Reserved AC30 Reserved AE9 D44 Source Sync Input Output AC31 Vcc Power Other AE10 D42 Source Sync Input Output AD1 VccPLL Power Other Input AE11 Vss Power Other AD2 Vcc Power Other AE12 DBI2 Source Sync Input Output AD3 Vss Power Other AE13 D35 Source Sync Input Output AD4 Reserved AE14 Vcc Power Other AD5 Vit Power Other AE15 COMP2 Power Other Input AD6 Reserved AE16 COMP3 Power Other Input AD7 D57 Source Sync Input Output AE17 DP3 Common Clk Input Output AD8 D46 Source Sync Input Output AE18 Vcc Power Other AD9 Vss Power Other AE19 DP1 Common Clk Input Output AD10 D45 Source Sync Input Output AE20 D28 Source Sync Input Output AD11 D40 Source Sync Input Output AE21 Vss Power Other AD12 Vir Power Other AE22 D27 Source Sync Input Output AD13 D38 Source Sync Input Output AE23 D22 Source Sync Input Output AD14 D39 Source Sync Input Ou
63. 4 and 1A 32 Architectures Software Developer s Manual In addition the Intel Xeon Processor 7200 Series and 7300 Series support the Execute Disable Bit functionality When used in conjunction with a supporting operating system Execute Disable allows memory to be marked as executable or non executable This feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system Further details on Execute Disable can be found at http www intel com cd ids developer asmo na eng 149308 htm Document Number 318080 002 9 intel Table 1 1 Table 1 2 10 Introduction The Intel Xeon Processor 7200 Series and 7300 Series support Intel Virtualization Technology for hardware assisted virtualization within the processor Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions Intel Virtualization Technology is used in conjunction with Virtual Machine Monitor software enabling multiple independent software environments inside a single platform Further details on Intel Virtualization Technology can be found at http developer intel com technology vt The Intel Xeon Processor 7200 Series and 7300 Series are intended for high performance multi processor server systems The processors support a Multi Independent Bus MIB architecture with one processor on each bus The MIB architecture provides improved
64. 50 55 60 65 70 75 80 Power W Notes 1 Please refer to Table 6 8 for discrete points that constitute the thermal profile 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation Document Number 318080 002 101 n tel Thermal Specifications 3 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 4 These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 5 Power specifications are defined at all VIDs found in Table 2 3 The Dual Core Intel Xeon Processor 7200 Series may be shipped under multiple VIDs for each frequency 6 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Table 6 8 Dual Core Intel Xeon Processor 7200 Series Thermal Profile Power W Tcase_max C C 0 45 0 10 47 4 20 49 8 30 52 1 40 54 5 50 56 9 60 59 3 70 61 7 80 64 0 6 1 2 Thermal Metrology The mini
65. 6 PDA Package Data Address This location provides the offset to the Package Data Section Writes to this register have no effect Offset 06h Bit Description 7 0 Package Data Address Byte pointer to the Package Data section 00h Package Data section not present 01h 31h Reserved 32h Package Data section pointer value 33h FFh Reserved 7 4 3 1 7 PNDA Part Number Data Address This location provides the offset to the Part Number Data Section Writes to this register have no effect Offset 07h Bit Description 7 0 Part Number Data Address Byte pointer to the Part Number Data section 00h Part Number Data section not present 01h 37h Reserved 38h Part Number Data section pointer value 39h FFh Reserved 7 4 3 1 8 TRDA Thermal Reference Data Address This location provides the offset to the Thermal Reference Data Section Writes to this register have no effect Offset 08h Bit Description 7 0 Thermal Reference Data Address Byte pointer to the Thermal Reference Data section 00h Thermal Reference Data section not present 01h 6Fh Reserved 70h Thermal Reference Data section pointer value 71h FFh Reserved Document Number 318080 002 123 intel 7 4 3 1 9 7 4 3 1 10 7 4 3 1 11 7 4 3 1 12 124 FDA Feature Data Address This location provides the offset to the Feature Data Section Writes to this register have no effect Offs
66. 9 2 2 Electrical Considerations The LAI will also affect the electrical performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide 142 Document Number 318080 002
67. A 35 3 INIT SMI Reset Configuration Signals BR 1 0 RESET AE sepe Tg UM LP ML Vcc Boor Le Ta ie Tb Te gt Td gt LI PP PT LET UD X XXX Th EE MI PP I MITTEN Ta T43 Voc poor stable to VID 6 1 BSEL 2 0 valid Tb T44 VID 6 1 BSEL 2 0 valid to Vcc stable Tc T48 Vr stable to VID 6 1 BSEL 2 0 valid Td T36 PWRGOOD assertion to RESET de assertion Te T41 Voc stable to PWRGOOD assertion Tf T37 BCLK stable to PWRGOOD assertion Tg T49 Vccp stable to PWRGOOD assertion Th T45 Reset Configuration Signals A 35 3 BR 1 0 INIT SMI Setup Time Ti T46 Reset Configuration Signals A 35 3 INIT SMI Hold Time Tj T47 Reset Configuration Signals BR 1 0 Hold Time Document Number 318080 002 e n tel Electrical Specifications Figure 2 25 FERR PBE Valid Delay Timing BCLK STPCLK FERR PBE FERR undefined PBE lt Ta undefined FERR Notes 1 Ta T40 FERR Valid Delay from STPCLK Deassertion 2 FERR PBE is undefined from STPCLK assertion until the Stop Grant acknowledge is driven on the FSB FERR PBE is also undefined for a period of Ta from STPCLK deassertion Inside these undefined regions the PBE signal is driven FERR is driven at all other times Figure 2 26 VID Step Timings
68. A174 Source Sync Input Output E29 Vss Power Other D17 A9 Source Sync Input Output E30 Vcc Power Other D18 Vcc Power Other E31 Vss Power Other D19 ADS Common Clk Input Output F1 Vcc Power Other D20 BRO Common Clk Input Output F2 Vss Power Other D21 Vss Power Other F3 Vss Power Other D22 RS1 Common Clk Input F4 Vcc Power Other D23 BPRI Common Clk Input F5 BPM3 Common Clk Input Output D24 Vcc Power Other F6 BPMO Common Clk Input Output D25 COMPO Power Other Input F7 Vss Power Other D26 Vss SENSE Power Other Output F8 BPM1 Common Clk Input Output D27 Reserved F9 GTLREF ADD END Power Other Input D28 Vss Power Other F10 Ver Power Other D29 Reserved F11 BINIT Common Clk Input Output D30 Vss Power Other F12 BR1 Common Clk Input Output D31 Mee Power Other F13 Vss Power Other EL Vss Power Other F14 ADSTB1 Source Sync Input Output E2 Reserved F15 A195 Source Sync Input Output E3 VID1 Power Other Output F16 A36 Source Sync Input Output EA BPM5 Common Clk Input Output F17 ADSTBO Source Sync Input Output 80 Document Number 318080 002 Pin Listing Table 4 2 Pin Listing by Pin Number Sheet intel Table 4 2 Pin Listing by Pin Number Sheet 5 of 14 6 of 14 Pin No Pin Name Signal Direction Pin No Pin Name Signal Direction Buffer Type
69. ALT state is not enabled in the BIOS the default Snoop state entered will be the HALT Snoop state Refer to the sections below for details on HALT Snoop state Stop Grant Snoop state and Extended HALT Snoop state HALT Snoop State Stop Grant Snoop State The processor will respond to snoop or interrupt transactions on the front side bus while in Stop Grant state or in HALT state During a snoop or interrupt transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus or the interrupt has been latched After the snoop is serviced or the interrupt is latched the processor will return to the Stop Grant state or HALT state as appropriate Extended HALT Snoop State The Extended HALT Snoop state is the default Snoop state when the Extended HALT state is enabled via the BIOS The processor will remain in the lower bus to core frequency ratio and VID operating point of the Extended HALT state While in the Extended HALT Snoop state snoops and interrupt transactions are handled the same way as in the HALT Snoop state After the snoop is serviced or the interrupt is latched the processor will return to the Extended HALT state Enhanced Intel SpeedStep Technology The Intel Xeon Processor 7200 Series and 7300 Series support Enhanced Intel SpeedStep Technology This technology enables
70. Buffer Type F18 DBSY Common Clk Input Output H26 Vss Power Other F19 Vss Power Other H27 Vcc Power Other F20 BNR Common Clk Input Output H28 Vss Power Other F21 RS2 Common Clk Input H29 Mee Power Other F22 A37 Source Sync Input Output H30 Vss Power Other F23 GTLREF ADD MID Power Other Input H31 Vcc Power Other F24 TRST TAP Input jl Vss Power Other F25 Vss Power Other J2 Vcc Power Other F26 THERMTRI P Async GTL Output J3 Vss Power Other F27 A20M Async GTL Input J4 Vcc Power Other F28 Vss Power Other J5 Vss Power Other F29 Vcc Power Other J6 Vcc Power Other F30 Vss Power Other J7 Vss Power Other F31 Vcc Power Other J8 Vcc Power Other G1 Vss Power Other J9 Vss Power Other G2 Vcc Power Other IER Vss Power Other G3 Vss Power Other J24 Vcc Power Other G4 Vcc Power Other J25 Vss Power Other G5 Vss Power Other J26 Vcc Power Other G6 Vcc Power Other J27 Vss Power Other G7 Vss Power Other J28 Vcc Power Other G8 Vcc Power Other J29 Vss Power Other G9 Vss Power Other J30 Vcc Power Other G23 LINT1 Async GTL Input J31 Vss Power Other G24 Vcc Power Other K1 Vcc Power Other G25 Vss Power Other K2 Vss Power Other G26 Vcc Power Other K3 Vcc Power Other G27 Vss Power Other K4 Vss Power Other G28 Vcc Power Other K5 Vcc Power Other G29 Vss Power Other K6 Vss Power Other G30 Vcc Power Other K7 Vcc Power Other G31 Vss Power Other K8 Vss Power Other H1 Vcc Power Other K9 Vcc Power Other H2 Vss Power Other K23 Vcc Power Other H3 Vcc Power O
71. Drawing Sheet 2 of 2 mens 59 Top Side Board Keepout Zones Part 1 61 Top Side Board Keepout Zones Part 2 a mme enemies 62 Bottom Side Board Keepout Zones 63 Board Mounting Hole Keepout Zones eee nemen memes 64 Volumetric Height Keep Ins nis e ene nnn 65 Processor Topside Markings rero eese kai pec ek s dd eee D a 4 68 Processor Bottom Side Markings ssssssssesmemememe n memes 68 Processor Pin Out Coordinates Top View 69 Quad Core Intel Xeon E7300 Processor Thermal Profile 97 Quad Core Intel Xeon X7350 Processor Thermal Profile 98 Quad Core Intel Xeon L7345 Processor Thermal Profile 100 Dual Core Intel Xeon Processor 7200 Series Thermal Profile 101 Case Temperature TCASE Measurement Location 103 Thermal Monitor 2 Frequency and Voltage Ordering cece ee ee eee ee eee ee es 105 SA a A EEEE E AAEE 107 Document Number 318080 002 5 intel 6 8 Conceptual Fan Control Diagram For a PECI Based Platform 108 7 1 Stop Clock State Machine iecit reote kam nte nbus For ERE FERE ipa See AE 114 7 2 Logical Schematic of SMBus Circuit 117 Table 1 1 Quad Core Intel Xeon Processor 7300 Series Processor Features es 10 1 2 Dual Core Intel Xeon Processor 7200 Series Processor Features ocococccccccconononoos 10 2 1 Core Frequency to FSB Multiplier Confi
72. GetTempO and GetTemp1 commands are listed in Table 6 11 below Table 6 11 GetTemp0 and GetTemp1 Error Codes 110 Error Code Description 0x8000 General sensor error 0x8002 Sensor is operational but has detected a temperature below its operational range underflow currently 309C absolute temperature 8 Document Number 318080 002 Features 7 7 1 Table 7 1 7 2 intel Features Power On Configuration Options Several configuration options can be configured by hardware The Intel Xeon Processor 7200 Series and 7300 Series sample its hardware configuration at reset on the active to inactive transition of RESET For specifics on these options please refer to Table 7 1 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset purposes the processor does not distinguish between a warm reset PWRGOOD signal remains asserted and a power on reset Power On Configuration Option pins Configuration Option Pin Name Notes Execute BIST Built In Self Test A3 1 2 Disable MCERR observation AQ 1 2 Disable BINIT observation A103 1 2 Cluster ID APIC ID 4 3 A 12 11 1 2 Disable dynamic bus parking A25 1 2 Symmetric agent arbitration ID BR 1 0 1 2 Output tri state SMI 1 2 3 Notes 1 Assert
73. ROM size provides the size of the device in hex bytes The MSB is at location O1h the LSB is at location 02h 0000h 007Fh Reserved 0080h 128 byte PIROM size 0081 FFFFh Reserved 7 4 3 1 3 PDA Processor Data Address This location provides the offset to the Processor Data Section Writes to this register have no effect Offset 03h Bit Description 7 0 Processor Data Address Byte pointer to the Processor Data section 00h Processor Data section not present 01h ODh Reserved OEh Processor Data section pointer value OFh FFh Reserved 7 4 3 1 4 PCDA Processor Core Data Address This location provides the offset to the Processor Core Data Section Writes to this register have no effect Offset 04h Bit Description 7 0 Processor Core Data Address Byte pointer to the Processor Data section 00h Processor Core Data section not present 01h 15h Reserved 16h Processor Core Data section pointer value 17h FFh Reserved 7 4 3 1 5 L3CDA L3 Cache Data Address This location provides the offset to the L3 Cache Data Section Writes to this register have no effect Offset 05h Bit Description 7 0 L3 Cache Data Address Byte pointer to the L3 Cache Data section 00h L3 Cache Data section not present 01h 24h Reserved 25h L3 Cache Data section pointer value 26h FFh Reserved 122 Document Number 318080 002 ae intel 7 4 3 1
74. Sync Input Output AC3 Vcc Power Other AA22 D10 Source Sync Input Output ACA Ver Power Other AA23 Vss Power Other AC5 D60 Source Sync Input Output AA24 D6 Source Sync Input Output AC6 D59 Source Sync Input Output AA25 D3 Source Sync Input Output AC7 Vss Power Other AA26 Vcc Power Other AC8 D56 Source Sync Input Output AA27 D1 Source Sync Input Output AC9 D47 Source Sync Input Output AA28 Reserved AC10 Mer Power Other AA29 SM_EP_A0 SMBus Input AC11 D43 Source Sync Input Output 84 Document Number 318080 002 Pin Listing Table 4 2 Pin Listing by Pin Number Sheet intel Table 4 2 Pin Listing by Pin Number Sheet 13 of 14 14 of 14 Pin No Pin Name Signal Direction Pin No Pin Name Signal Direction Buffer Type Buffer Type AC12 D41 Source Sync Input Output AD21 D29 Source Sync Input Output AC13 Maes Power Other AD22 DBI1 Source Sync Input Output AC14 D50 Source Sync Input Output AD23 Vss Power Other AC15 DP2 Common CIk Input Output AD24 D21 Source Sync Input Output AC16 Mee Power Other AD25 D18 Source Sync Input Output AC17 D34 Source Sync Input Output AD26 Vcc Power Other AC18 DPO Common CIk Input Output AD27 D4 Source Sync Input Output AC19 Maes Power Other AD28 Reserved AC20 D
75. T assertion has been observed the bus agents will re arbitrate for the FSB and attempt completion of their bus queue and IOQ entries If BINIT observation is disabled during power on configuration a priority agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR 1 0 BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wired OR signal which must connect the appropriate pins of all processor FSB agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges BPM5 1 0 BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals BPM4 O They are outputs from the processor which indicate the status of breakpoints and BPM3 1 0 programmable counters used for monitoring processor performance BPM 5 0 5 6 should connect the appropriate pins of all FSB agents BPM 2 112 BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a BPMO 1 0 processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debu
76. VID Maximum Power is measured at maximum Tease 3 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 4 These specifications are based on pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 5 Power specifications are defined at all VIDs found in Table 2 3 The Quad Core Intel Xeon E7300 Processor may be shipped under multiple VI Ds for each frequency 6 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Document Number 318080 002 Thermal Specifications n tel Figure 6 1 Quad Core I ntel Xeon E7300 Processor Thermal Profile Table 6 2 Thermal Profile 70 0 60 0 50 0 T 4 7 0 263 x Power 45 d g 40 0 o 30 0 20 0 0 10 20 30 40 50 60 70 80 Power W Notes 1 Please refer to Table 6 2 for discrete points that constitute the thermal profile 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Therm
77. Vss H24 Power Other Vss C7 Power Other Vss H26 Power Other Vss C13 Power Other Vss H28 Power Other Vss C19 Power Other Vss H30 Power Other Vss C25 Power Other Vss J1 Power Other Vss C29 Power Other Vss J3 Power Other Vss D2 Power Other Vss J5 Power Other Vss D5 Power Other Vss J7 Power Other 76 Document Number 318080 002 Pin Listing Table 4 1 Pin Listing by Pin Name Sheet intel Table 4 1 Pin Listing by Pin Name Sheet 13 of 16 14 of 16 Pin Name Pin No Signal Direction Pin Name Pin No Signal Direction Buffer Type Buffer Type Vss J9 Power Other Vss P1 Power Other Vss J23 Power Other Vss P3 Power Other Vss J25 Power Other Vss P5 Power Other Vss J27 Power Other Vss P7 Power Other Vss J29 Power Other Vss P9 Power Other Vss J31 Power Other Vss P23 Power Other Vss K2 Power Other Vss P25 Power Other Vss K4 Power Other Vss P27 Power Other Vss K6 Power Other Vss P29 Power Other Vss K8 Power Other Vss P31 Power Other Vss K24 Power Other Vss R2 Power Other Vss K26 Power Other Vss R4 Power Other Vss K28 Power Other Vss R6 Power Other Vss K30 Power Other Vss R8 Power Other Vss L1 Power Other Vss R24 Power Other Vss L3 Power Other Vss R26 Power Other Vss L5 Power Other Vss R28 Power Other Vss L7 Power Other Vss R30 Power Other Vss L9 Power Other Vss T1 Power Other Vss L23 Power Ot
78. Y DSTBN 3 0 DSTBP 3 0 HIT HITM LOCK MCERR REQ 4 0 RS 2 0 RSP TRDY Note 1 Signals that have RTT in the package with 50 Q pullup to Vy Non AGTL Signal Description Table Signals with RTT Signals with no Rer A20M BCLK 1 0 BSEL 2 0 COMP 3 0 FERR PBE FORCEPR GTLREF ADD MID GTLREF ADD END GTLREF DATA MID GTLREF DATA END IERR GNNE INIT LI NTO INTR LINT1 NMI LL ID 1 0 PROC ID 1 0 PECI PROCHOT PWRGOOD SKTOCC SMI STPCLK TCK TDI TDO TESTHI 1 0 TESTIN1 TESTIN2 THERMTRIP TMS TRST VC SENSE VCC SENSE2 VID 6 1 VSS SENSE VSS SENSE2 VIT SEL Signal Reference Voltages GTLREF CMOS A 39 3 ADS ADSTB 1 0 AP 1 0 BINIT A20M LINTO INTR LINT1 NMI IGNNEZ Z INIT BNR BPM 5 0 BPMb 3 0 BPRI BR 1 0 PWRGOOD SMI STPCLK TCK TDI TMS TRST D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FORCEPR HIT HITM LOCK MCERR RESET REQ 4 0 RS 2 0 RSP TRDY CMOS Asynchronous and Open Drain Asynchronous Signals Legacy input signals such as A20M IGNNE INIT SMI and STPCLK utilize CMOS input buffers Legacy output signals such as FERR PBE IERRZ PROCHOT THERMTRIP and TDO utilize open drain output buffers All of the CMOS and Open Drain signals are required to be asserted deasserted for at least eight BCLKs in order for the processor to
79. Y27 Reserved AB9 DBI3 Source Sync Input Output Y28 Reserved AB10 D55 Source Sync Input Output Y29 Reserved AB11 Vss Power Other Y30 Vcc Power Other AB12 D51 Source Sync Input Output Y31 BSEL2 Power Other Output AB13 D52 Source Sync Input Output AAL Mee Power Other AB14 Vcc Power Other AA2 Vss Power Other AB15 D37 Source Sync Input Output AA3 BSELO Power Other Output AB16 D32 Source Sync Input Output AAA BPMb0 Common Clk Input Output AB17 D31 Source Sync Input Output AA5 Reserved AB18 Vcc Power Other AA6 Vcc Power Other AB19 D14 Source Sync Input Output AA7 Vit Power Other AB20 D12 Source Sync Input Output AA8 D61 Source Sync Input Output AB21 Vss Power Other AA9 Vss Power Other AB22 D13 Source Sync Input Output AA10 D54 Source Sync Input Output AB23 D9 Source Sync Input Output AA11 D53 Source Sync Input Output AB24 Vcc Power Other AA12 Vrr Power Other AB25 D8 Source Sync Input Output AA13 D48 Source Sync Input Output AB26 D7 Source Sync Input Output AA14 D49 Source Sync Input Output AB27 Vss Power Other AA15 Vss Power Other AB28 SM EP A2 SMBus Input AA16 D33 Source Sync Input Output AB29 SM EP A1 SMBus Input AA17 Vss Power Other AB30 Vec Power Other AA18 D24 Source Sync Input Output AB31 Vss Power Other AA19 D15 Source Sync Input Output AC1 BPMb1 Common Clk Output AA20 Vcc Power Other AC2 Vss Power Other AA21 D11 Source
80. ability Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Platform Environment Control Interface PECI bus as described in Section 6 3 The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT see Section 6 2 Processor Thermal Features Systems that implement fan speed control should be designed to use this data Systems that do not alter the fan speed also need to guarantee the case temperature meets the thermal profile specifications The Quad Core Intel Xeon Processor E7300 Series see Figure 6 1 Table 6 2 Quad Core Intel Xeon L7345 Processor see Figure 6 3 Table 6 6 and Dual Core Intel Xeon Processor 7200 Series see Figure 6 4 Table 6 8 supports a single Thermal Profile The Thermal Profile is indicative of a constrained thermal environment Ex 1U form factor Because of the reduced cooling capability represented by this solution the probability of TCC activation and performance loss is increased Document Number 318080 002 95 Table 6 1 96 Thermal Specifications Additionally utilization of a thermal solution that does not meet the Thermal Profile will violate the thermal specifications and may result in permanent damage to the processor Refer to the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300
81. act due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable A thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel amp Xeon Processor 7300 Series Thermal Mechanical Design Guide for information on designing a thermal solution The duty cycle for the TCC when activated by the TM1 is factory configured and cannot be modified The TM1 does not require any additional hardware software drivers or interrupt handling routines Thermal Monitor 2 The Intel Xeon Processor 7200 Series and 7300 Series adds supports for an Enhanced Thermal Monitor capability known as Thermal Monitor 2 TM2 This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor The Thermal Monitor or Enhanced Thermal Monitor must be enabled for the processor to be operating within specifications TM2 requires support for dynamic VID transitions in the platform Not all Intel Xeon Processor 7200 Series and 7300 Series are capable of supporting TM2 When Thermal Monitor 2 is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated for all processor cores The TCC causes the processor to adjust its operating frequency via the bus multiplie
82. ages have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Document Number 318080 002 11 12 ntel Introduction Processor Information ROM PIROM A memory device located on the processor and accessible via the System Management Bus SMBus which contains information regarding the processor s features This device is shared with the Scratch EEPROM is programmed during manufacturing and is write protected Scratch EEPROM Electrically Erasable Programmable Read Only Memory A memory device located on the processor and addressable via the SMBus which can be used by the OEM to store information useful for system management SMBus System Management Bus A two wire interface through which simple system and power management related devices can communicate with the rest of the system It is based on the principals of the operation of the 12C two wire serial bus from Phillips Semiconductor Note 12C is a two wire communications bus protocol developed by Phillips SMBus is a subset of the i C bus protocol and was developed by Intel Implementations of the 2C bus protocol or the SMBus bus protocol may require licenses from various entities including Phillips Electronics N V and North American Phillips Corporation
83. al Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Teaser 4 These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 5 Power specifications are defined at all VIDs found in Table 2 3 The Quad Core Intel Xeon E7300 Processor may be shipped under multiple VIDs for each frequency 6 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Quad Core Intel Xeon E7300 Processor Thermal Profile Table Power W Tcase_max C C 0 45 0 10 47 6 20 50 3 30 52 9 20 55 5 50 58 2 60 60 8 70 63 4 80 66 0 Document Number 318080 002 97 e n tel Thermal Specifications Table 6 3 Quad Core Intel Xeon X7350 Processor Thermal Specifications Core Thermal Minimum Maximum Design Power TCASE TCASE Notes Frequency W C C Launch to FMB 130 5 See Figure 6 2 1 2 3 4 5 6 Table 6 4 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified I cc Please refer to the loadline specific
84. at processor package Note that the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep Technology Multiple voltage frequency operating points provide optimal performance at reduced power consumption Voltage frequency selection is software controlled by writing to processor MSR s Model Specific Registers thus eliminating chipset dependency f the target frequency is higher than the current frequency Vcc is incremented in steps 12 5 mV by placing a new value on the VID signals and the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded If the target frequency is lower than the current frequency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals System Management Bus SMBus Interface The Intel Xeon Processor 7200 Series and 7300 Series package includes an SMBus interface which allows access to a memory component with two sections referred to as the Processor Information ROM and the Scratch EEPROM These devices and their features are described below The SMBus on package thermal sensor has been removed and is no longer used Refer to Section 6 3 for details about the new digital thermometer a
85. ation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE2 and VSS SENSE2 pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation Document Number 318080 002 31 intel Electrical Specifications Figure 2 6 Quad Core Intel Xeon X7350 Processor VCC Static and Transient Tolerance Load Lines 32 Icc A 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 VID 0 000 4 Voc Maximum VID 0 050 4 VID 0 100 4 E E VID 0 150 4 Voc Typical Voc VID 0 200 4 Minimum VID 0 250 Notes 1 The Vcc min and Vcc max loadlines represent static and transient limits Please see Section 2 11 3 for VCC overshoot specifications 2 Refer to Table 2 9 for processor VID information 3 Refer to Table 2 10 for V Static and Transient Tolerance 4 The load lines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE pins and the VCC SENSE2 and VSS_SENSE2 pins Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE2 and VSS_SENSE2 pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line guidelines and VR imp
86. ations in Section 2 E 2 Maximum Power is the highest power the processor will dissipate regardless of its VID Maximum Power is measured at maximum Tcase 3 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Teaser 4 These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 5 Power specifications are defined at all VIDs found in Table 2 3 The Intel Xeon X7350 Processor may be shipped under multiple VIDs for each frequency 6 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Figure 6 2 Quad Core I ntel Xeon X7350 Processor Thermal Profile Thermal Profile 70 00 60 00 50 00 T 0 162 x Power 45 case 40 00 Temperature C 30 00 20 00 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Power W Notes 1 Thermal Profile is representative of a volumetrically unconstrained platform Please refer to Table 6 4 for discrete points that constitute the thermal profile 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probab
87. c nominal V levels refer to Table 2 11 Table 2 15 PECI DC Electrical Limits 2 11 2 2 36 Symbol Definition and Conditions Min Max Units Notes Vin Input Voltage Range 0 150 Vor V Vhysteresis Hysteresis 0 1 Vit N A V Vn Negative edge threshold voltage 0 275 Vr 0 500 V r V Vp Positive edge threshold voltage 0 550 Vz 0 762 Vr V I source High level output source Voy 0 75 V 6 0 N A mA I sink Low level output sink VoL 0 25 Vr 0 5 1 0 mA l High i leak igh impedance state leakage to V r N A 50 uA 2 Vieak Vou l High i d leak igh impedance leakage to GND N A 10 uA 2 Vieak Vor Chus Bus capacitance N A 10 pF 3 Vnoise Signal noise immunity above 300 MHz 0 1 Vi N A Vp p Note 1 Vy supplies the PECI interface PECI behavior does not affect V min max specifications 2 The leakage specification applies to powered devices on the PECI bus 3 One node is counted for each client and one node for the system host Extended trace lengths might appear as additional nodes I nput Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 2 9 as a guide for input buffer design Document Number 318080 002 Electrical Specifications Figure 2 9 Input Device Hysteresis Vr Maximum Vp Minimum Vp Maximum Mu Minimum Vy
88. cc U9 Power Other Vcc N3 Power Other Vcc U23 Power Other Vcc N5 Power Other Vcc U25 Power Other Vcc N7 Power Other Vcc U27 Power Other Vcc N9 Power Other Vcc U29 Power Other Vcc N23 Power Other Vcc U31 Power Other Vcc N25 Power Other Vcc V2 Power Other Vcc N27 Power Other Vcc V4 Power Other Vcc N29 Power Other Vcc V6 Power Other Vcc N31 Power Other Vcc V8 Power Other Vcc P2 Power Other Vcc V24 Power Other Vcc P4 Power Other Vcc V26 Power Other Vcc P6 Power Other Vcc V28 Power Other Vcc P8 Power Other Vcc V30 Power Other Vcc P24 Power Other Vcc W1 Power Other Vcc P26 Power Other Vcc W25 Power Other Vcc P28 Power Other Vcc W27 Power Other Vcc P30 Power Other Vcc W29 Power Other Vcc R1 Power Other Vcc W31 Power Other Vcc R3 Power Other Vcc Y2 Power Other Vcc R5 Power Other Vcc Y16 Power Other Vcc R7 Power Other Vcc Y22 Power Other Vcc R9 Power Other Vcc Y30 Power Other Vcc R23 Power Other Vcc AA1 Power Other Vcc R25 Power Other Vcc AA6 Power Other Vcc R27 Power Other Vcc AA20 Power Other Vcc R29 Power Other Vcc AA26 Power Other Vcc R31 Power Other Vcc AA31 Power Other Vcc T2 Power Other Vcc AB2 Power Other Vcc T4 Power Other Vcc AB8 Power Other Document Number 318080 002 75 intel Table 4 1 Pin Listing by Pin Name Sheet Pin Listing Table 4 1 Pin Listing by Pin Name Sheet 11 of 16
89. cessor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes Vcc Core voltage with respect to Vss 0 30 1 55 V Ver FSB termination voltage with respect to 0 30 1 55 V Vss TcASE Processor case temperature See Section 6 See Section 6 C TSTORAGE Storage temperature 40 85 C 2 3 4 Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no pins can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 3 This rating applies to the processor and does not include any tray or packaging 4 Failure to adhere to this specification can affect the long term reliability of the processor Document Number 318080 002 23 e n tel Electrical Specifications 24 Processor DC Specifications The following notes apply The processor DC specifications in this section are defined at the processor die and not at the package pins unless noted otherwise The notes asso
90. ciated with each parameter are part of the specification for that parameter Unless otherwise noted all specifications in the tables apply to all frequencies and cache sizes See Section 5 for the pin signal definitions Most of the signals on the processor FSB are in the AGTL signal group The DC specifications for these signals are listed in Table 2 11 Table 2 9 through Table 2 17 list the DC specifications and are valid only while meeting specifications for case temperature Tcase as specified in Section 6 clock frequency and input voltages Document Number 318080 002 Electrical Specifications 2 11 1 Flexible Motherboard Guidelines FMB The Flexible Motherboard FMB guidelines are estimates of the maximum values the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series will have over certain time periods The values are only intel estimates and actual specifications for future processors may differ Processors may or may not have specifications equal to the FMB value in the foreseeable future System designers should meet the FMB values to ensure their systems will be compatible with future processors Table 2 9 Voltage and Current Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Unit Notes VID VID range 1 0000 1 5000 Vcc Vcc for processor core See Table 2 10 Figure 2 5 V 2 3 4 6
91. ckage substrate and die and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together Refer to the mPGA604 Socket Design Guidelines for complete details on the mPGA604 socket The package components shown in Figure 3 1 include the following 1 IHS Processor die FC mPGA6 package Pin side capacitors N WN Package pin Processor Package Assembly Sketch 4 l 5 Figure 3 1 is not to scale and is for reference only The mPGA604 socket is not shown Package Mechanical Drawing The package mechanical drawings are shown in Figure 3 2 and Figure 3 3 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include 1 Package reference with tolerances total height length width etc 2 IHS parallelism and tilt 3 Pin dimensions 4 Top side and back side component keepout dimensions 5 Reference datums All drawing dimension are in mm in Document Number 318080 002 57 Mechanical Specifications mmm 876870 NW SIN3 am J8 menu am mon
92. ction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction ADS 1 0 ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 39 3 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must be connected to the appropriate pins on all Intel Xeon Processor 7200 Series and 7300 Series FSB agents ADSTB 1 0 1 0 Address strobes are used to latch A 39 3 and REQ 4 0 on their rising and falling edge Strobes are associated with signals as shown below Signals Associated Strobes REQ 4 0 ADSTBO A 37 36 16 3 A 39 38 35 17 ADSTB1 AP 1 0 1 0 AP 1 0 Address Parity are driven by the requestor one common clock after ADS A 39 3 REQ 4 0 are driven A correct parity signal is electrically high if an even number of covered signals are electrically low and electrically low if an odd number of covered signals are electrically low This allows parity to be electrically high w
93. d 0 7 Vrr See Table 2 19 for BCLK specifications Table 2 23 Front Side Bus AC Specifications Reset Conditions T Parameter Min Max Unit Figure Notes T45 Reset Configuration Signals 480 us 2 24 1 A 39 3 BR 1 0 INIT SMI Setup Time T46 A 39 3 INIT SMI Hold Time Reset Configuration Signals 2 20 BCLKs 2 24 2 T47 BR 1 0 Hold Time Reset Configuration Signals 2 2 BCLKs 2 24 2 Notes 1 2 Before the clock that de asserts RESET After the clock that de asserts RESET Table 2 24 TAP Signal Group AC Specifications Sheet 1 of 2 T Parameter Min Max Unit Figure Notes 1 2 8 T55 TCK Period 30 ns 2 12 3 T56 TDI TMS Setup Time 7 5 ns 2 19 4 7 42 Document Number 318080 002 Electrical Specifications Table 2 24 TAP Signal Group AC Specifications Sheet 2 of 2 T Parameter Min Max Unit Figure pn T57 TDI TMS Hold Time 7 5 ns 2 19 4 7 T58 TDO Clock to Output Delay 0 7 5 ns 2 19 5 T59 TRST Assert Time 2 Trck 2 20 6 Notes 1 2 Not 100 tested Specified by design characterization 3 4 Referenced to the rising edge of TCK 5 Referenced to the falling edge of TCK 6 7 0 5 V ns co Document Number 318080 002 It is recommended that TMS be asserted while TRST is being deasserted Unless otherwise noted all specifications in this table apply to all
94. e driven by the agent responsible for driving D 63 0 and must connect the appropriate pins of all processor FSB agents DRDY 1 0 DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor FSB agents Document Number 318080 002 89 m e n tel Signal Definitions Table 5 1 Signal Definitions Sheet 4 of 8 Name Type Description Notes DSTBN 3 0 1 0 Data strobe used to latch in D 63 0 Signals Associated Strobes D 15 0 DBI0 DSTBNO D 31 16 DBI1 DSTBN1 D 47 32 DBI2 DSTBN2 D 63 48 DBI3 DSTBN3 DSTBP 3 0 1 0 Data strobe used to latch in D 63 0 Signals Associated Strobes D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48 DBI3 DSTBP3 FERR PBE O FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When
95. e voltage that is requested the voltage regulator must disable itself See the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details Although the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines defines VID 7 0 VID 7 and VID 0 are not used on the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series The Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 2 10 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 2 and Table 2 3 The VRM or EVRD utilized must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 2 9 and Table 2 10 while AC specifications are included in Table 2 25 Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details Pow
96. e Data Section 00h FFh See Section 7 4 4 for calculation of the value Part Number Data This section provides traceability There are 208 available bytes in this section for future use PPN Processor Part Number This location contains seven ASCII characters reflecting the Intel part number for the processor This information is typically marked on the outside of the processor If the part number is less than 7 characters a leading space is inserted into the value The part number should match the information found in the marking specification found in Section 3 Writes to this register have no effect Example A processor with a part number of 80565KH will have the following at offset 38 3Eh 38h 30h 35h 36h 35h 4Bh 48h Document Number 318080 002 Features Offset 38h 3Eh Bit Description 7 0 Character 7 ASCII character or 20h 00h OFFh ASCII character 15 8 Character 6 ASCII character or 20h 00h OFFh ASCII character 23 16 Character 5 ASCII character or 20h 00h OFFh ASCII character 31 24 Character 4 ASCII character 00h OFFh ASCII character 39 32 Character 3 ASCII character 00h OFFh ASCII character 47 40 Character 2 ASCII character 00h OFFh ASCII character 4F 48 Character 1 ASCII character 00h OFFh ASCII character 7 4 3 6 2 RES6 Reserved 6 This location is reserved Writes to this register ha
97. e processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the Intel 64 and IA 32 Architectures Software Developer s Manual PROCHOT is designed to assert at or a few degrees higher than maximum Tease as specified by Thermal Profile when dissipating TDP power and cannot be interpreted as an indication of processor case temperature This temperature delta accounts for processor package lifetime and manufacturing variations and attempts to ensure the Thermal Control Circuit is not activated below maximum Tcase when dissipating TDP power There is no defined or fixed correlation between the PROCHOT trip temperature or the case temperature Thermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of TcASE or PROCHOT FORCEPR Signal The FORCEPR force power reduction input can be used by the platform to cause the Intel Xeon Processor 7200 Series and 7300 Series to activate the TCC If the Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal Assertion of the FORCEPR signal will activate TCC for all processor cores The TCC will remain active until the system deasserts FORCEPR FORCEPR is an asynchronous input FORCEPR can be used to thermally protect other system component
98. e processor will first switch to the lower bus to core frequency ratio and then transition to the lower voltage VID While in the Extended HALT state the processor will process bus snoops Document Number 318080 002 Features Table 7 2 Extended HALT Maximum Power Symbol Parameter Min Typ Max Unit Notes PExTENDED HALT Quad Extended HALT 34 w 2 3 Core Intel Xeon State Power E7300 Processor PEXTENDED HALT Quad Extended HALT 50 w 2 Core Intel Xeon State Power X7350 Processor PEXTENDED HALT Quad Extended HALT 24 w 1 Core Intel Xeon State Power L7345 Processor Notes 1 The specification is at Tease 50 C and nominal Vcc The VID setting represents the maximum expected VID while running in HALT state 2 This specification is characterized by design 3 Processors running in the lowest bus ratio will enter the HALT state when the processor has executed the HALT and MWAIT instruction since the processor is already in the lowest core frequency and voltage operating point The processor exits the Extended HALT state when a break event occurs When the processor exits the Extended HALT state it will first transition the VID to the original value and then change the bus to core frequency ratio back to the original value Document Number 318080 002 113 intel Figure 7 1 7 2 3 114 Stop Clock State Machine HALT or MWAIT Instruction and
99. e to PWRGOOD assertion 1 ms 2 24 10 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 All AC timings for the Asynchronous GTL signals are referenced to the BCLKO rising edge at Crossing ONG du oo 10 11 12 Voltage Vcross PWRGOOD is referenced to BCLKO rising edge at 0 5 Ver These signals may be driven asynchronously Refer to Section 7 2 for additional timing requirements for entering and leaving low power states A minimum pulse width of 500 us is recommended when FORCEPR is asserted by the system Refer to the PWRGOOD signal definition in Section 5 for more details information on behavior of the signal Length of assertion for PROCHOT does not equal TCC activation time Time is required after the assertion and before the deassertion of PROCHOT for the processor to enable or disable the TCC Intel recommends the Vrr power supply also be removed upon assertion of THERMTRIP This specification requires that the VID and BSEL signals be sampled no earlier than 10 us after Vcc at Vcc poor voltage and Ver are stable Parameter must be measured after applicable voltage level is stable Stable means that the power supply is in regulation as defined by the minimum and maximum DC AC specifications for all components being powered by it The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor Measured between 0 3 V r an
100. e used as a mechanical reference or load bearing surface for thermal and mechanical solutions The minimum loading specification must be maintained by any thermal and mechanical solution Processor Loading Specifications Parameter Minimum Maximum Unit Notes Static Compressive 44 222 N 1234 Load 10 50 bf 44 288 N Leds 10 65 bf Dynamic 222 N 0 45 kg 100 G N 1 3 4 6 7 Compressive Load 50 Ibf static 1 Ibm 100 G bf 288 N 0 45 kg 100G N L35 7 65 Ibf static 1 Ibm 100 G bf Transient 445 N 1 3 8 100 bf Notes 1 These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface 3 These parameters are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 This specification applies for thermal retention solutions that allow baseboard deflection 5 This specification applies either for thermal retention solutions that prevent baseboard deflection or for the Intel enabled reference solution CEK 6 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement 7 Experimentally validated test condition used a heatsink mass of 1 lbm 0 45 kg with 100 G accele
101. eakage Current N A N A 100 uA 6 7 Notes Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Ver referred to in these specifications refers to instantaneous Vy 3 Refer to the pra 1 0 Buffer Models for I V characteristics 4 Measured at 0 1 V 5 Measured at 0 9 V 6 For Vin between 0 V and V Measured when the driver is tristated 7 This is the measurement at the pin Table 2 13 Open Drain Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes VoL Output Low Voltage N A 0 20 V 3 Vou Output High Voltage Vr 5 Vit Vi 5 V loL Output Low Current 16 N A 50 mA 2 lio Leakage Current N A N A 200 uA 4 5 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Measured at 0 2 Vr 3 Voy is determined by value of the external pullup resistor to Vyr Please refer to platform design guide for details 4 For ViN between 0 V and Vor 5 This is the measurement at the pin Table 2 14 SMBus Signal Group DC Specifications Symbol Parameter Min Max Unit Notes 2 Vu Input Low Voltage 0 30 0 30 SM_VCC V Vin Input High Voltage 0 70 SM_VCC 3 465 V VoL Output Low Voltage 0 0 400 V lot Output Low Current N A 3 0 mA lu Input Leakage Current N A 10 HA lio Output Leakage Current N A 10 HA CsMB SMBus Pin Capacitance 15 0 pF 3 Notes 1 These parameters are based on design charac
102. ecksum One Byte Checksum of the Processor Core Data Section 00h FFh See Section 7 4 4 for calculation of the value Cache Data This section contains cache related data Document Number 318080 002 129 intel 7 4 3 4 1 7 4 3 4 2 7 4 3 4 3 7 4 3 4 4 130 RES3 Reserved 3 These locations are reserved Writes to this register have no effect Offset 25h 26h Bit Description 15 0 RESERVED 3 0000h FFFFh Reserved L2SI ZE L2 Cache Size This location contains the size of the level two cache in kilobytes Writes to this register have no effect Example The Intel Xeon Processor 7200 Series and 7300 Series has a 2x4MB 8192 KB L2 cache total Thus offset 27 28h would contain 2000h Offset 27h 28h Bit Description 15 0 L2 Cache Size 0000h FFFFh KB L3SI ZE L3 Cache Size This location contains the size of the level three cache in kilobytes Writes to this register have no effect Example The Intel Xeon Processor 7200 Series and 7300 Series has no L3 cache Thus offset 29 2Ah will contain 0000h 0 decimal Offset 29h 2Ah Bit Description 15 0 L3 Cache Size 0000h FFFFh KB MAXCVI D Maximum Cache VID This location contains the maximum Cache VID Voltage Identification voltage that may be requested via the CVID pins This field rounded to the next thousandth is in mV and is reflected in hex Wri
103. ed or Test Signals All Reserved signals must remain unconnected Connection of these signals to Vcc Ver Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 4 for a pin listing of the processor and the location of all Reserved signals For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the baseboard trace for FSB signals unless otherwise noticed in the appropriate platform design guidelines For unused AGTL input or I O signals use pull up resistors of the same value as the on die termination resistors R r For details see Table 2 24 TAP Asynchronous GTL inputs and Asynchronous GTL outputs do not include on die termination Inputs and utilized outputs must be terminated on the baseboard Unused outputs may be terminated on the baseboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functi
104. eeeee 000000000 TA 000000000 i 000000000 00000000 eeeceeecee A 1 4 000800000 I ee eeeeeee 000000090 000000000 ES 669999990 000000000 sesssesse B ss it ___ ______ esececess _ 000000000 f 000000000 000000000 3 mmm 000000000800 0009000090000000000 P 390004 0000000000000000 C000H0000000000 0000000000000000 00000000000000 06000000000000090000000009000096 OOOOHOQOHOHDOHOHDOOODHOOOHHOOHOHOOOOO 0606960000606000909000000090000000 ex e N Z SS 2 zat p o Le F 9 1 ke 1971 XC Leelee ml ns 1896810 PI P y A 9 l 9 Figure 3 3 Processor Package Drawing Sheet 2 of 2 Mechanical Specifications 59 Document Number 318080 002 60 3 2 Mechanical Specifications Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements A thermal and mechanical solution design must not intrude into the required keepout zones Decoupling capacitors are typically mounted to either the topside or pin side of the package substrate See Figure 3 4 and Figure 3 5 for keepout zones Document Number 318080 002 intel Mechanical Specifications Figure 3 4 Top Side Board Keepout Zones Part 1
105. en Drain Output Synchronous to BCLK 1 0 Asynchronous ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 FERR PBE IERR PROCHOT THERMTRIP TDO CMOS Asynchronous Input Asynchronous A20M FORCEPR IGNNE INIT LINTO INTR LINT1 NMI PWRGOOD SMI STPCLK TCK TDI TMS TRST CMOS Asynchronous Output FSB Clock Asynchronous Clock BSEL 2 0 VID 6 1 BCLK 1 0 SMBus Synchronous to SM_CLK SM_CLK SM_DAT SM_EP_A 2 0 SM_WP Power Other Power Other COMP 3 0 GTLREF_ADD_MID GTLREF_ADD_END GTLREF_DATA_MID GTLREF_DATA_END LL ID 1 0 PROC ID 1 0 PECI RESERVED SKTOCC SM_VCC TESTHI 1 0 TESTI N1 TESTIN2 VCC VCC SENSE VCC_SENSE2 VCCPLL VSS SENSE VSS SENSE2 VSS VTT VIT SEL Notes 1 Refer to Section 5 for signal descriptions 2 These signals may be driven simultaneously by multiple agents Wired OR Document Number 318080 002 21 e n tel Electrical Specifications Table 2 5 Table 2 6 Table 2 7 2 7 2 8 22 Table 2 5 outlines the signals which include on die termination Ber Table 2 6 outlines non AGTL signals including open drain signals Table 2 7 provides signal reference voltages AGTL Signal Description Table AGTL signals with Ry AGTL signals with no Rrr A 39 3 ADS ADSTB 1 0 AP 1 0 BINIT BPM 5 0 BPMb 3 0 RESET BR 1 0 BNR BPRI D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRD
106. ents multi processor operation The Intel Xeon Processor 7200 Series and 7300 Series is an MP processor The remaining six bits in this field are reserved for the future use Writes to this register have no effect Example An MP processor will use COh at offset 1Ch Offset 1Ch Bit Description 7 6 Multiprocessor Support UP DP or MP indictor 00b UP 01b DP 10b Reserved 11b MP 5 0 RESERVED 000000b 111111b Reserved MCF Maximum Core Frequency This location contains the maximum core frequency for the processor Format of this field is in MHz rounded to a whole number and encoded in hex format Writes to this register have no effect Example A 2 666 GHz processor will have a value of 0A6Ah which equates to 2666 decimal Offset 1Dh 1Eh Bit Description 15 0 Maximum Core Frequency 0000h FFFFh MHz MAXVID Maximum Core VID This location contains the maximum Core VID Voltage Identification voltage that may be requested via the VID pins This field rounded to the next thousandth is in mV and is reflected in hex Writes to this register have no effect Example A voltage of 1 350 V maximum core VID would contain 0546h 1350 decimal in Offset 1F 20h Offset 1Fh 20h Bit Description 15 0 Maximum Core VID 0000h FFFFh mV Document Number 318080 002 Features 7 4 3 3 6 Note 7 4 3 3 7 7 4 3 3 8 7 4 3 4 intel Th
107. eon X7350 Processor Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP instead of the maximum processor power consumption The Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more details on this feature refer to Section 6 2 To ensure maximum flexibility for future requirements systems should be designed to the Flexible Motherboard FMB guidelines even if a processor with lower power dissipation is currently planned Thermal Monitor and Thermal Monitor 2 feature must be enabled for the processor to remain within its specifications Quad Core Intel Xeon E7300 Processor Thermal Specifications Core ThermalDesign Minimum Maximum Power TCASE TCASE Notes Frequency w C C Launch to FMB 80 5 See Figure 6 1 1 2 3 4 5 6 Table 6 2 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified I cc Please refer to the loadline specifications in Section 2 T 2 Maximum Power is the highest power the processor will dissipate regardless of its
108. er Seven 8 bit ASCII characters 3F 4Ch 112 Reserved Reserved 4D 54h 64 Processor Electronic 64 bit identification number Signature 55 6Eh 208 Reserved Reserved 6Fh 8 Checksum 1 byte checksum Thermal Ref Data 70h 8 Reserved Reserved 71 72h 16 Reserved Reserved 73h 8 Checksum 1 byte checksum Feature Data 74 77h 32 Processor Core Feature From CPUID function 1 EDX contents Flags Document Number 318080 002 Features Table 7 6 Note 7 4 3 1 7 4 3 1 1 Processor Information ROM Data Sections Sheet 3 of 3 Offset Section of Function Notes Bits 78h 8 Processor Feature Flags 7 Multi Core 6 Serial Signature 5 Electronic Signature Present 4 Thermal Sense Device Present 3 Reserved 2 OEM EEPROM Present 1 Core VID Present 0 L3 Cache Present 79h 8 Processor Thread and Core 7 2 Number of cores Information 1 0 Number of threads per core 7Ah 8 Additional Processor Feature 7 Reserved Flags 6 Intel Cache Safe Technology 5 Extended Halt State C1E 4 Intel Virtualization Technology 3 Execute Disable 2 Intel 64 1 Thermal Monitor TM2 0 Enhanced Intel SpeedStep Technology 7B 7Ch 16 Thermal Adjustment Factors 15 8 Measurement Correction Factor Pending 7 0 Temperature Target 7D 7Eh 16 Reserved Reserved 7Fh 8 Checksum 1 byte checksum Details on each of the
109. er source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable Document Number 318080 002 Electrical Specifications intel Table 2 3 Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 VID6 VID5 VID4 VID3 VID2 VID1 7A 1 1 1 1 0 1 0 8500 3C 0 1 1 il 1 0 1 2375 78 1 1 1 1 0 0 0 8625 3A 0 1 1 1 0 il 1 2500 76 1 1 1 0 d 1 0 8750 38 0 1 1 il 0 0 1 2625 74 1 1 1 0 1 0 0 8875 36 0 1 1 0 il il 1 2750 72 1 1 1 0 0 1 0 9000 34 0 1 1 0 1 0 1 2875 70 1 1 1 0 0 0 0 9125 32 0 il 1 0 0 il 1 3000 6E 1 1 0 1 1 1 0 9250 30 0 il il 0 0 0 1 3125 6C 1 1 0 1 1 0 0 9375 2E 0 1 0 1 1 1 1 3250 6A 1 1 0 1 0 1 0 9500 2C 0 1 0 1 il 0 1 3375 68 1 1 0 1 0 0 0 9625 2A 0 il 0 il 0 1 1 3500 66 1 1 0 0 1 1 0 9750 28 0 il 0 il 0 0 1 3625 64 1 1 0 0 1 0 0 9875 26 0 il 0 0 il 1 1 3750 62 1 1 0 0 0 1 1 0000 24 0 il 0 0 1 0 1 3875 60 il 1 0 0 0 0 1 0125 22 0 1 0 0 0 1 1 4000 5E 1 0 1 1 1 1 1 0250 20 0 1 0 0 0 0 1 4125 5C 1 0 1 1 1 0 1 0375 1E 0 0 il 1 1 il 1 4250 5A 1 0 il il 0 1 1 0500 1C 0 0 il 1 1 0 1 4375 58 1 0 1 il 0 0 1 0625 1A 0 0 1 il 0 il 1 4500 56 1 0 1 0 1 1 1 0750 18 0 0 1 1 0 0 1 4625 54 i 0 1 0 1 0 1 0875 16 0 0 1 0 1 1 1 4750 52 1 0 1 0 0 1 1 1000 14 0 0 1 0 1 0 1 4875 50 1 0 1 0 0 0 1 1125 12 0 0 il 0 0 il 1 5000 4E il 0 0 1 1
110. ermal Monitor 2 iecore ERR EA VRRR DEE TREE RA EAR RARE REN R TUE RR RE 104 6 2 4 On Demand Mode 105 6 2 5 PROCHOT Signal i scettr iia amaya Rire X RUE dee aa 106 6 2 6 FORCEPRY Stone en leo in 106 6 2 7 THERMTRIPZ Signal eon etre erre nn E clases t Fax Re P La e o qhasa 106 6 3 Platform Environment Control Interface PECI nme 107 SE E E Nu ee Tee TEE 107 6 3 2 PECI Specifications l uu m a usr exeant ER KENE EN ERR a Rad 108 Features musun Qu geg ege eege de gege saa asua dd red eee eines 111 7 1 Power On Configuration Options eaten ena 111 7 2 Clock Control and Low Power States 111 7 2 1 Normal State tassi ete dai id 112 7 2 2 HALT or Extended HALT Gtete emen enn 112 7 2 3 Stop Grant State mic o rire ee dc tert ee da lare RERO data GER d Ode ed E es 114 7 2 4 Extended HALT Snoop or HALT Snoop State Stop Grant Snoop EE 115 7 3 Enhanced Intel SpeedStep Technology 115 7 4 System Management Bus SMBus Interface nnns 116 7 4 1 SMBus Device Addressing s sssssrssressrrerersrrarrerernnrirseratsrrerrenernererserere 117 7 4 2 PIROM and Scratch EEPROM Supported SMBus Transactions 118 7 4 3 Processor Information ROM PIROM issssssse emen nna 119 LAA CHECKSUMS as uos caede cer ees rax ce pvc re eto ee zn Fee Frei eo eut RW RERO 137 TAS SceratchrEEPROM ISL e Ee eege ae P RE AR a nara QR Ee at a
111. ess pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple processors To set an SM_EP_A line high a pull up resistor should be used that is no larger than 1 kQ The processor includes a 10 kQ pull down resistor to Vss for each of these signals SM VCC SM VCC provides power to the SMBus components on the Intel Xeon Processor 7200 Series and 7300 Series package SM WP 92 WP Write Protect can be used to write protect the Scratch EEPROM The Scratch EEPROM is write protected when this input is pulled high to SM VCC The processor includes a 10 kQ pull down resistor to Vss for this signal Document Number 318080 002 Signal Definitions Table 5 1 Signal Definitions Sheet 7 of 8 intel Name SMI Type l Description SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the deassertion of RESET the processor will tri state its outputs See Section 7 1 Notes STPCLK STPCLK Stop Clock when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transactio
112. et 09h Bit Description 7 0 Feature Data Address Byte pointer to the Feature Data section 00h Feature Data section not present 01h 73h Reserved 74h Feature Data section pointer value 75h FFh Reserved ODA Other Data Address This location provides the offset to the Other Data Section Writes to this register have no effect Offset OAh Bit Description 7 0 Other Data Address Byte pointer to the Other Data section 00h Other Data section not present 01h 7Dh Reserved 7Eh Other Data section pointer value 7Fh FFh Reserved RES1 Reserved 1 This locations are reserved Writes to this register have no effect Offset OBh OCh Bit Description 15 0 RESERVED 0000h FFFFh Reserved HCKS Header Checksum This location provides the checksum of the Header Section Writes to this register have no effect Offset ODh Bit Description 7 0 Header Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Document Number 318080 002 Features 7 4 3 2 Processor Data This section contains two pieces of data The S spec of the part in ASCII format ntel 1 2 bit field to declare if the part is a pre production sample or a production unit 7 4 3 2 1 SNUM S Spec Number This location provides the S SPec number of the processor The S spec field is six ASCII c
113. f a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLKO ADS HIT HITMZ etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as rising edge of BCLKO Asynchronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 2 4 identifies which signals are common clock source synchronous and asynchronous Document Number 318080 002 Electrical Specifications Table 2 4 FSB Signal Groups intel Signal Group AGTL Common Clock Input Type Synchronous to BCLK 1 0 Signals1 BPRI DEFER RESET RS 2 0 RSP TRDY AGTL Common Clock Output Synchronous to BCLK 1 0 BPM4 BPM 2 1 BPMb 2 1 AGTL Common Clock I O Synchronous to BCLK 1 0 ADS AP 1 0 BINIT 2 BNR 2 BPM5 BPM3 BPMO BPMb3 BPMbO BR 1 0 DBSY DP 3 0 DRDY HIT 2 HITM 2 LOCK MCERR 2 AGTL Source Synchronous 1 0 Synchronous to assoc strobe Signals Associated Strobe REQ 4 0 ADSTBO A 37 36 16 3 A 39 38 35 17 ADSTB1 D 15 0 DBIO D 31 16 DBI1 D 47 32 DBI2 D 63 48 DBI3 DSTBP0 DSTBNO DSTBP1 DSTBN1 DSTBP2 DSTBN2 DSTBP3 DSTBN3 AGTL Strobes I O Op
114. f the via near CPU SK Blue is the simulated waveform aL the CPU PAD j b Fe E 2 06 d Y v Ze LA 4 D l z y D j y GC FJ l g I f l l 04 E 4 py j P Kc if i f l L KL DER al at PAD Fi GEM fall at e l SE DER rise a DAD PP Y Ya Fi ww 262199 j A 4 f lt LA F A iJ i f A l 01 if di e E fi a i Y 4 PY d A f H AA a M 021 q ap ra 1 A T A DER rise at PR fe HL DER fall a PNT Fi f time tO tres den 40 3meg UN kA 1 Ds j Y 3 d MS 4 LON i i WE ag j j N J GA j Was AE W S 7 Ee Note 08 Wavetorm at PIN is non monotonic but not at PAD Waveform at PAD is monotonic DER Differential Edge Rate measured Zeros 200mv g indicates Vins meg ndicates mvns Wavalorm at PAD has faster edge rate than at PIN Notes 1 Waveform at pin is non monotonic Waveform at pad is monotonic 2 Differential Edge Rate DER measured zero 200mv 3 g indicates Vins units and meg indicates mv ns units 4 Waveform at pad has faster edge rate than at pin Figure 2 16 FSB Common Clock Valid Delay Timing Waveform TO T1 BCLK1 BCLKO Common Clock Signal driver T2 Common Clock Signal receiver Tp T10 Common Clock Output Valid Delay Tg T11 Common Clock Input Setup T4 T12 Common Clock Input Hold Time 48
115. ferences EE 13 2 Electrical SpecificationS uu u SEENEN ERR ENEE NEEN EE ERAN NEEN ed XR Rl EEE dE 15 2 1 Front Side Bus and GTLREF ssssssssssese mme e memesese ems sese emen si s esr nnns 15 2 2 Decoupling G ldelines iioi ae n enn nn br en ENEE casas Ead bn 15 242 1 VCGCIDECOUDIING DEET 16 2 2 2 VIT Decoupling uu su e een E EEN EES 16 2 2 3 Front Side Bus AGTL Decoupling sssssssese mme 16 2 3 Front Side Bus Clock BCLK 1 0 and Processor Cocking esee 16 2 3 1 Front Side Bus Frequency Select Signals BSEL 2 0 17 2 3 2 PLL Power SUpply crei aasan ri Ee ege klare 17 2 4 Voltage Identification ID 17 2 5 Reserved Unused or Test Gionals memes 20 2 6 Front Side Bus Signal Groups 20 2 7 CMOS Asynchronous and Open Drain Asynchronous Gionals tena ee es 22 2 8 Test Access Port TAP Connection 22 2 9 Mgr Oe DES uu u an ya Eege EE geleed SES 23 2 10 Absolute Maximum and Minimum Rating 23 2 11 Processor DC Specifications 0c nm enses e emen nnns 24 2 11 1 Flexible Motherboard Guidelines FMB seem 25 2 11 2 Platform Environmental Control Interface PECI DC Specifications 35 2 11 3 VCC Overshoot Specificati ri u u u uuu ananin EATER EA 37 2 11 4 AGTL FSB SpecificationS uuu sedet e RE RR AR E HALO RR D Ro Rd 38 2 12 Front Side Bus AC Specifications 1 0 0 0 ccc e memememene emen nens 40 2 13 Processor AC Timing Waveforms
116. g point voltage in which the differential receiver switches It includes input threshold hysteresis 8 The crossing point must meet the absolute and relative crossing point specifications simultaneously 9 VhHavo can be measured directly using Vtop on Agilent and High on Tektronix oscilloscopes 10 For Vin between 0 V and VyAVeross is defined as the total variation of all crossing voltages as defined in note 2 Document Number 318080 002 39 Note Table 2 19 Table 2 20 40 Electrical Specifications Front Side Bus AC Specifications The processor FSB timings specified in this section are defined at the processor core pads Therefore proper simulation of the FSB is the only means to verify proper timing and signal quality See Table 4 1 for the pin listing and Table 5 1 for signal definitions Table 2 19 through Table 2 24 list the AC specifications associated with the processor FSB All AGTL timings are referenced to GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END for both 0 and 1 logic levels unless otherwise specified The timings specified in this section should be used in conjunction with the processor signal integrity models provided by Intel AGTL layout guidelines are also available in the appropriate platform design guidelines Care should be taken to read all notes associated with a particular timing parameter Front Side Bus Differential Clock AC Specifications
117. g tools to request debug operation of the processors BPM 5 4 must be bussed to all bus agents Please refer to the appropriate platform design guidelines for more detailed information BPMb3 1 0 BPMb 3 0 Breakpoint Monitor are a second set of breakpoint and performance BPMb 2 1 o monitor signals They are additional outputs from the processor which indicate the BPMb0 1 0 status of breakpoints and programmable counters used for monitoring processor performance BPMb 3 0 should connect the appropriate pins of all FSB agents BPRI l BPRI Bus Priority Request is used to arbitrate for ownership of the processor FSB It must connect the appropriate pins of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BR 1 0 1 0 The BR 1 0 signals are sampled on the active to inactive transition of RESET The signal which the agent samples asserted determines its agent ID BRO drives the BREQO signal in the system and is used by the processor to request the bus These signals do not have on die termination and must be terminated BSEL 2 0 O The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor input clock frequency Table 2
118. gnal assertion during power on 109 6 10 PECI Address assigned to processor eee eee eee nemen 109 6 11 GetTemp0 and GetTemp1 Error Codes eee ee eee eereeeeeeeeeeteatenennenieas 110 7 1 Power On Configuration Option pins rr mmm memes 111 6 Document Number 318080 002 7 2 7 3 7 4 7 5 7 6 7 7 Extended HALT Maximum Bower r entered 113 Memory Device SMBus Addressing rr r 118 Read Byte SMBUS Packet us asua e dE REES ERR ERR Ree Ra 118 Write Byte SMBUS Packet cotorra rita cda 118 Processor Information ROM Data Sections sssssssssssese menn 119 128 Byte ROM Checksum Values rn 137 Document Number 318080 002 7 intel Revision History Document Number Revision Description Date 318080 001 Initial Release September 2007 318080 002 Changed Product Name to Intel Xeon Processor 7200 Series and September 2008 7300 Series Updated Power Specifications The character byte ordering was reversed for the following fields SQNUM S Spec QDF Number PREV Package Revision PPN Processor Part Number Updated the Processor Mechanical drawings to add an optional small shallow depression in the top right hand side corner of the integrated heat spreader IHS This feature which supports anti mixing may be Seen on some processor packages There are no major electrical mechanical or thermal differences in the form fit or function of the processors
119. haracters wide and is programmed with the same S spec value as marked on the processor If the value is less than six characters in length leading spaces 20h are programmed in this field Writes to this register have no effect Example A processor with a S Spec mark of SLA67 contains the following in field OE 13h 20h 53h 4Ch 41h 36h 37h This data consists of one blank at OEh followed by the ASCII codes for SLA67 in locations OF 13h Offset OEh 13h Bit Description 7 0 Character 6 S SPEC character or 20h 00h OFFh ASCII character 15 8 Character 5 S SPEC character 00h OFFh ASCII character 23 16 Character 4 S SPEC character 00h OFFh ASCII character 31 24 39 32 Character 3 S SPEC character 00h OFFh ASCII character Character 2 S SPEC character 00h OFFh ASCII character 47 40 Character 1 S SPEC character 00h OFFh ASCII character Document Number 318080 002 125 intel 7 4 3 2 2 7 4 3 2 3 7 4 3 3 7 4 3 3 1 Note Note 126 SAMPROD Sample Production This location contains the sample production field which is a two bit field and is LSB aligned All S spec material will use a value of 01b All other values are reserved Writes to this register have no effect Example A processor with an Sxxxx mark production unit will use O1h at offset 14h Offset 14h Bit Description 7 2 RESERVED 00000
120. he Processor Information ROM PIROM The PIROM consists of the following sections Table 7 6 Header Processor Data Processor Core Data Cache Data Package Data Part Number Data Thermal Reference Data Feature Data Other Data Processor Information ROM Data Sections Sheet 1 of 3 of Offset Section Bits Function Notes Header 00h 8 Data Format Revision Two 4 bit hex digits 01 02h 16 PIROM Size Size in bytes MSB first 03h 8 Processor Data Address Byte pointer 00h if not present 04h 8 Processor Core Data Byte pointer 00h if not present Address 05h 8 L3 Cache Data Address Byte pointer 00h if not present 06h 8 Package Data Address Byte pointer 00h if not present 07h 8 Part Number Data Address Byte pointer 00h if not present 08h 8 Thermal Reference Data Byte pointer 00h if not present Address 09h 8 Feature Data Address Byte pointer 00h if not present 0Ah 8 Other Data Address Byte pointer 00h if not present OB OCh 16 Reserved Reserved ODh 8 Checksum 1 byte checksum Processor Data OE 13h 48 S spec Number Six 8 bit ASCII characters 14h 6 Reserved Reserved most significant bits 2 Sample Production 00b Sample 01b Production 15h 8 Checksum 1 byte checksum Processor Core Data 16 19h 2 Reserved Reserved for future use 8 Extended Family From CPUID 4 Extended Model From CPUID Document Number 318080 00
121. hed a temperature beyond which permanent silicon damage may occur Measurement of the temperature is accomplished through an internal thermal sensor Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRIP See Figure 2 21 and Table 2 22 for the appropriate power down sequence and timing requirements Intel also recommends the removal of Vor when THERMTRIP is asserted Driving of the THERMTRI P signals is enabled within 10 us of the assertion of PWRGOOD and is disabled on de assertion of PWRGOOD Once activated THERMTRIP remains latched until PWRGOOD is de asserted While the de assertion of the PWRGOOD signal will de assert THERMTRI P if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 us of the assertion of PWRGOOD TMS TMS Test Mode Select is a JTAG specification support signal used by debug tools See the XDP Debug Port Design Guide for Intel 7300 Chipset Platforms for further information TRDY TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all FSB agents TRST TRST Test Reset resets the Test Access Po
122. hen all the covered signals are electrically high AP 1 0 should connect the appropriate pins of all Intel Xeon Processor 7200 Series and 7300 Series FSB agents The following table defines the coverage for these signals Request Signals Subphase 1 Subphase 2 A 39 24 APO AP1 A 23 3 AP1 APO REQ 4 0 AP1 AP0 BCLK 1 0 The differential bus clock pair BCLK 1 0 Bus Clock determines the FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLK0 crossing Vcnoss Document Number 318080 002 87 intel Se Table 5 1 Signal Definitions Sheet 2 of 8 Name Type Description Notes BINIT 1 0 BINIT Bus Initialization may be observed and driven by all processor FSB agents and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration see Section 7 1 and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their O Queue 1OQ and transaction tracking state machines upon observation of BINIT assertion Once the BINI
123. her thus all processors are affected in unison When the STPCLK signal is asserted the processor enters the Stop Grant state issuing a Stop Grant Special Bus Cycle SBC for each Document Number 318080 002 111 intel 7 2 2 7 2 2 1 7 2 2 2 Note 112 processor The chipset needs to account for a variable number of processors asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one of the lower processor power states Normal State This is the normal operating state for the processor HALT or Extended HALT State The Extended HALT state CIE is enabled via the BIOS The Extended HALT state must be enabled for the processor to remain within its specifications The Extended HALT state requires support for dynamic VID transitions in the platform HALT State HALT is a low power state entered when the processor has executed the HALT or MWAIT instruction When one of the processor cores executes the HALT or MWAIT instruction that processor core is halted however the other processor cores continue normal operation The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT LINT 1 0 NMI INTR or an interrupt delivered over the front side bus RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT state See the Intel amp 64 and
124. her Vss T3 Power Other Vss L25 Power Other Vss T5 Power Other Vss L27 Power Other Vss T7 Power Other Vss L29 Power Other Vss T9 Power Other Vss L31 Power Other Vss T23 Power Other Vss M2 Power Other Vss T25 Power Other Vss M4 Power Other Vss T27 Power Other Vss M6 Power Other Vss T29 Power Other Vss M8 Power Other Vss T31 Power Other Vss M24 Power Other Vss U2 Power Other Vss M26 Power Other Vss U4 Power Other Vss M28 Power Other Vss U6 Power Other Vss M30 Power Other Vss U8 Power Other Vss N2 Power Other Vss U24 Power Other Vss N4 Power Other Vss U26 Power Other Vss N6 Power Other Vss U28 Power Other Vss N8 Power Other Vss U30 Power Other Vss N24 Power Other Vss V1 Power Other Vss N26 Power Other Vss V3 Power Other Vss N28 Power Other Vss V5 Power Other Vss N30 Power Other Vss V7 Power Other Document Number 318080 002 77 intel Table 4 1 Pin Listing by Pin Name Sheet Pin Listing Table 4 1 Pin Listing by Pin Name Sheet 78 15 of 16 16 of 16 Pin Name Pin No Signal Direction Pin Name Pin No Signal Direction Buffer Type Buffer Type Vss v9 Power Other Vss AD3 Power Other Vss V23 Power Other Vss AD9 Power Other Vss V25 Power Other Vss AD15 Power Other Vss V27 Power Other Vss AD17 Power Other Vss V29 Power Other Vss AD23 Power Other Vss v31 Power Other Vss AE6 Power Other Vss W2
125. id Delay Document Number 318080 002 Electrical Specifications n tel Figure 2 19 TAP Valid Delay Timing Waveform TCK V Valid Signal Tx T58 TDO Clock to Output Delay Ts T56 TDI TMS Setup Time Th T57 TDI TMS Hold Time V 0 5 Vir Note Please refer to Table 2 12 for TAP Signal Group DC specifications and Table 2 24 for TAP Signal Group AC specifications Figure 2 20 Test Reset TRST Async GTL Input and PROCHOT Timing Waveform T T59 TRST Pulse Width V 0 5 V r q T38 PROCHOT Pulse Width V GTLREF Figure 2 21 THERMTRI P Power Down Sequence THERMTRIP Vcc Vir T T39 THERMTRIP to removal of power Document Number 318080 002 51 e n tel Electrical Specifications Figure 2 22 SMBus Timing Waveform 1HD STA Clk t T t HOSTA HD DAT Z Data tLow T93 t HD STA T100 t SU STA T101 THIGH T92 t HD DAT T98 t su sTD T102 R 2794 ou T99 Ir 7e SU DAT T97 Figure 2 23 SMBus Valid Delay Timing Waveform SM_CLK TAA gt man 3 wo NR SMD AT 4 Nest DATA OUTPUT TAA T96 52 Document Number 318080 002 Electrical Specifications Figure 2 24 Voltage Sequence Timing Requirements VID 6 1 BSEL 2 0 Vit VccPLL PWRGOOD BCLK Reset Configuration Signals
126. ies Thermal Specifications Core Thermal Minimum Maximum Frequency aie ib Ko bs Notes Launch to FMB 80 5 See Figure 6 4 1 2 3 4 5 6 Table 6 8 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified Icc Please refer to the loadline specifications in Section 2 i 2 Maximum Power is the highest power the processor will dissipate regardless of its VID Maximum Power is measured at maximum Tcase 3 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 4 These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 5 Power specifications are defined at all VI Ds found in Table 2 3 The Dual Core Intel Xeon Processor 7200 Series may be shipped under multiple VIDs for each frequency 6 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Figure 6 4 Dual Core Intel Xeon Processor 7200 Series Thermal Profile Thermal Profile T 0 238 x Power 45 case Temperature C 0 5 10 15 20 25 30 35 40 45
127. ifications Introduction The Intel Xeon Processor 7200 Series and 7300 Series is also offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from baseboards and standard components The boxed processor will not be supplied with a cooling solution Future revisions may have solutions that differ from those discussed here Thermal Specifications Please see Chapter 6 for the the cooling requirements of the boxed processor Boxed Processor Cooling Requirements A suitable heatsink is required to properly cool the boxed processor However meeting the processor s temperature specifications is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is found in Section 6 1 1 of this document Document Number 318080 002 139 e n tel Boxed Processor Specifications 140 Document Number 318080 002 m e Debug Tools Specifications n tel 9 9 1 Note 9 2 9 2 1 Debug Tools Specifications Debug Port System Requirements The Intel Xeon Processor 7200 Series and 7300 Series debug port is the command and control interface for the In Target Probe ITP debugger The ITP enables run time control of the processors for system debug The debug port which is connected to the FSB is a combination of the system JTAG and execution signals There are several mechanical
128. ility of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Refer to the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series Thermal Mechanical Design Guide for system and environmental implementation details 98 Document Number 318080 002 Thermal Specifications n tel Table 6 4 Quad Core Intel Xeon X7350 Processor Thermal Profile Table Power W TcasE MAX C 0 45 0 10 46 6 20 48 2 30 49 9 40 51 5 50 53 1 60 54 7 70 56 3 80 58 0 90 59 6 100 61 2 110 62 8 120 64 4 130 66 0 Table 6 5 Quad Core Intel Xeon L7345 Processor Thermal Specifications Core Thermal Design Minimum Maximum Frequency Power TCASE TCASE Notes W C C Launch to FMB 50 5 SeeFigure 6 3 1 2 3 4 5 6 Table 6 6 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified Icc Please refer to the loadline specifications in Section 2 E 2 Maximum Power is the highest power the processor will dissipate regardless of its VID Maximum Power is measured at maximum Tease 3 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the max
129. imum power that the processor can dissipate TDP is measured at maximum Tease 4 These specifications are based on initial silicon characterization These specifications may be further updated as more characterization data becomes available 5 Power specifications are defined at all VIDs found in Table 2 3 The Quad Core Intel Xeon L7345 Processor may be shipped under multiple VIDs for each frequency 6 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Document Number 318080 002 99 e n tel Thermal Specifications Figure 6 3 Quad Core Intel Xeon L7345 Processor Thermal Profile Thermal Profile T 0 420 x Power 45 case Temperature C 0 5 10 15 20 25 30 35 40 45 50 Power W Notes 1 Please refer to Table 6 6 for discrete points that constitute the thermal profile 2 Refer to the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series Thermal Mechanical Design Guide for system and environmental implementation details Table 6 6 Quad Core I ntel Xeon L7345 Processor Thermal Profile Power W Tcase Max C 0 45 0 5 47 1 10 49 2 15 51 3 20 53 4 25 55 5 30 57 6 35 59 7 40 61 8 45 63 9 50 66 0 100 Document Number 318080 002 Thermal Specifications intel Table 6 7 Dual Core Intel Xeon Processor 7200 Ser
130. ing this signal during RESET will select the corresponding option 2 Address pins not identified in this table as configuration options should not be asserted during RESET 3 Requires de assertion of PWRGOOD Disabling of any of the cores within the Intel Xeon Processor 7200 Series and 7300 Series must be handled by configuring the EXT_CONFIG Model Specific Register MSR This MSR will allow for the disabling of a single core per die within the Intel Xeon Processor 7200 Series and 7300 Series package Clock Control and Low Power States The Intel Xeon Processor 7200 Series and 7300 Series supports the Extended HALT state also referred to as C1E in addition to the HALT state and Stop Grant state to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 7 1 for a visual representation of the processor low power states The Extended HALT state is a lower power state than the HALT state or Stop Grant state The Extended HALT state must be enabled via the BIOS for the processor to remain within its specifications For processors that are already running at the lowest bus to core frequency ratio for its nominal operating point the processor will transition to the HALT state instead of the Extended HALT state The Stop Grant state requires chipset and BIOS support on multiprocessor systems In a multiprocessor system all the STPCLK signals are bussed toget
131. intel Intel Xeon Processor 7200 Series and 7300 Series Datasheet September 2008 Notice The Intel Xeon Processor 7200 Series and 7300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Document Number 318080 002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Xeon Proces
132. is location contains the minimum Processor Core voltage This field rounded to the next thousandth is in mV and is reflected in hex The minimum Vcc reflected in this field is the minimum allowable voltage assuming the FMB maximum current draw Writes to this register have no effect MI NV Minimum Core Voltage The minimum core voltage value in offset 21 22h is a single value that assumes the FMB maximum current draw Refer to Table 2 10 and Table 2 11 for the minimum core voltage specifications based on actual real time current draw Example A voltage of 1 000 V minimum core voltage would contain 03E8h 1000 decimal in Offset 21 22h Offset 21h 22h Bit Description 15 0 Minimum Core Voltage 0000h FFFFh mV TCASE Tcase Maximum This location provides the maximum Tcase for the processor The field reflects temperature in degrees Celsius in hex format This data can be found in Section 6 The thermal specifications are specified at the case Integrated Heat Spreader IHS Writes to this register have no effect Example A temperature of 66C would contain 42h 66 decimal in Offset 23h Offset 23h Bit Description 7 0 Tcase Maximum 00h FFh Degrees Celsius PCDCKS Processor Core Data Checksum This location provides the checksum of the Processor Core Data Section Writes to this register have no effect Offset 24h Bit Description 7 0 Processor Core Data Ch
133. k Output Valid Delay 0 22 1 10 ns 2 16 4 T11 Common Clock Input Setup Time 0 650 N A ns 2 16 5 T12 Common Clock Input Hold Time 0 150 N A ns 2 16 5 T13 RESET Pulse Width 1 10 ms 2 24 6 7 8 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Not 10096 tested Specified by design characterization 3 All common clock AC timings for AGTL signals are referenced to the Crossing Voltage VCROSS of the BCLK 1 0 at rising edge of BCLKO All common clock AGTL signal timings are referenced at nominal GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END at the processor core pads 4 Valid delay timings for these signals are specified into the test circuit described in Figure 2 11 and with GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END at 0 67 Ver Document Number 318080 002 Electrical Specifications Table 2 21 E eo Eo intel Specification is for a minimum swing is specified into the test circuit described in Figure 2 11 and defined between AGTL Vi max to Vin min This assumes an edge rate of 2 0 V ns to 3 0 V ns RESET can be asserted active asynchronously but must be deasserted synchronously This should be measured after V r and BCLK 1 0 become stable Maximum specification applies only while PNRGOOD is asserted FSB Source Synchronous AC Specifications
134. kay 137 Boxed Processor Spechficattons mmn 139 Gl D ge ere de EE 139 8 2 Thermal Specifications sce A EE 139 8 2 1 Boxed Processor Cooling Requirements rr 139 Debug Tools Specifications eens 141 9 1 Debug Port System Requirements sss meme eee nene 141 9 2 Logic Analyzer Interface LA 141 9 2 1 Mechanical Considerations r rr 141 9 2 2 Electrical ConSiderati0NS ooooccccocccccnconcnrnnonnnnrnnr nennen 142 Document Number 318080 002 Figures 2 1 2 2 2 3 lr gl gr gr gf bP 0 0 0 0 gt Ro zl O LD PS M O IO O Yu QOU N F O DWWWWWWWWWWWNNNNNNNNNNNNNNNNNNN HA a R IO O0 zl OU P UJ N PFE N N NN N N NN I2 EER FE FE PE F F O 6 2 Quad Core Intel Xeon L7345 Processor Load Current versus Time 27 Dual Core Dual Core Intel Xeon Processor 7200 Series Load Current Versus TIMO uuu u See ee tach geed ee de enee 28 Quad Core Intel Xeon Processor 7200 Series and 7300 Series Load Current versus Time28 Quad Core Intel Xeon X7350 Processor Load Current versus Time 29 Quad Core Intel Xeon Processor 7200 Series and 7300 Series VCC Static and Transient Tolerance Load Lines osi et ene e eu ee RR divi R REX A EN inde aor aad 31 Quad Core Intel Xeon X7350 Processor VCC Static and Transient Tolerance Load WINGS tives asua tre hr EE EUREN RT Ur OG PATE MOX ERANT FERRE RUE ACA GERA RU RR RO VR kaqa 32
135. lation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE2 and VSS_SENSE2 pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for Socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation 4 lcc values greater than 60 A are not applicable for the Quad Core Intel Xeon L7345 Processor 5 lec values greater than 90 A are not applicable for the Intel Xeon Processor 7200 Series and 7300 Series and Dual Core Intel Xeon Processor 7200 Series 30 Document Number 318080 002 Electrical Specifications n tel Figure 2 5 Quad Core I ntel Xeon Processor 7200 Series and 7300 Series Vcc Static and Transient Tolerance Load Lines Icc A 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 VID 0 040 VID 0 060 VID 0 080 Vcc V VID 0 100 Vcc Typical VID 0 120 VID 0 140 Voo Minimum VID 0 160 Notes 1 The Vcc min and Vcc max loadlines represent static and transient limits Please see Section 2 11 3 for VCC overshoot specifications 2 Refer to Table 2 9 for processor VID information 3 Refer to Table 2 10 for VccStatic and Transient Tolerance 4 The load lines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE pins and the VCC SENSE2 and VSS SENSE2 pins Voltage regul
136. lementation Please refer to the appropriate platform design guide for details on VR implementation Document Number 318080 002 m Electrical Specifications n tel Figure 2 7 Quad Core Intel Xeon L7345 Processor Vcc Static and Transient Tolerance Load Lines lcc A 0 5 10 15 20 25 30 35 40 45 50 55 60 VID 0 000 VID 0 010 Voc Maximum VID 0 020 VID 0 030 VID 0 040 VID 0 050 Vcc V VID 0 060 VID 0 070 VID 0 080 VID 0 090 Voc Minimum VID 0 100 Notes 1 The Vcc min and Vec max loadlines represent static and transient limits Please see Section 2 11 3 for VCC overshoot specifications 2 Refer to Table 2 9 for processor VID information 3 Refer to Table 2 10 for VccStatic and Transient Tolerance 4 The load lines specify voltage limits at the die measured at the VCC_SENSE and VSS_ SENSE pins and the VCC_SENSE2 and VSS_SENSE2 pins Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE2 and VSS_SENSE2 pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation Document Number 318080 002 33 intel Figure 2 8 Table 2 11 34 Electrical Specifications Dual Core Intel Xeon Processor 7200 Se
137. llows Writes to this register have no effect Offset 7Ah E Description Reserved Intel Cache Safe Technology Extended Halt State C1E Intel Virtualization Tech nology Execute Disable Intel 64 Thermal Monitor 2 O FINI Wi aj O Enhanced Intel Speed Step Technology Bits are set when a feature is present and cleared when they are not Thermal Adjustment Factors This location contains information on thermal adjustment factors for the processor This field and it s details are pending and will be updated in a future revision Writes to this register have no effect Offset 7Bh 7Ch Bit Description 15 8 Measurement Correction Factor 7 0 Temperature Target Other Data These locations are reserved Writes to this register have no effect Offset 7Dh 7Eh Bit Description 15 0 RESERVED FDCKS Feature Data Checksum This location provides the checksum of the Feature Data Section Writes to this register have no effect Document Number 318080 002 Features 7 4 4 Table 7 7 7 4 5 Offset 7Fh Bit Description 7 0 Feature Data Checksum One Byte Checksum of the Feature Data Section 00h FFh See Section 7 4 4 for calculation of the value Checksums The PIROM includes multiple checksums Table 7 7 includes the checksum values for each section defined in the 128
138. mal monitoring of Intel processor and chipset components It uses a single wire thus alleviating routing congestion issues Figure 6 7 shows an example of the PECI topology in a system with Intel Xeon Processor 7200 Series and 7300 Series PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices Also data transfer speeds across the PECI interface are negotiable within a wide range 2 Kbps to 2 Mbps The PECI interface on Intel Xeon Processor 7200 Series and 7300 Series is disabled by default and must be enabled through BIOS PECI Topology 0 3 Domain0 C28 0 Socket 0 Cluster ID 1 0 0 0 x A 3 Domain 0 0 3 Domain0 28 2 Socket 1 o Cluster ID 1 0 1 x T 3 Domain1 2 PECI Host Controller 0 a Domain0 28 1 Socket 2 Cluster ID 1 0 2 0 x 3 Domain1 1 0 3 Domain0 3 Socket 3 Cluster ID 1 0 3 C28 0 x A 3 Domain1 3 Note The power on configuration POC settings of third party chipsets may produce different PECI addresses than those shown in Figure 6 7 Thermal designers should consult their third party chipset designers for the correct PECI addresses TcontTroL and Tec Activation on PECI Based Systems Fan speed control solutions based on PECI utilize a TcowrRo value stored in the processor A32 TEMPERATURE TARGET MSR This MSR uses the
139. me 2A Instruction Set Reference A M 253666 Volume 2B Instruction Set Reference N Z 253667 Volume 3A System Programming Guide Part 1 d 5 Volume 3B System Programming Guide Part 2 IA 32 Intel Architecture and Intel 64 Software Developer s Manual 1 I 252046 Documentation Changes IA 32 Intel Architecture Optimization Reference Manual 248966 1 Intel Extended Memory 64 Technology 1 Volume 300834 Volume 2 300835 Intel virtualization Technology for IA 32 Processors VT x Preliminary C97063 1 Specification Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon 318081 1 Processor 7300 Series Specification Update Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 315889 1 11 0 Design Guidelines EPS12V Power Supply Design Guide A Server system Infrastructure SSI 2 Specification for Entry Chassis Power Supplies Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon 318086 1 Processor 7300 Series Thermal Mechanical Design Guide Intel Xeon Processor 7200 Series and 7300 Series Package Mechanical Models 1 mPGA604 Socket Design Guide 254239 1 Intel Xeon Processor 7200 Series and 7300 Series Enabled Components CEK 1 Thermal Models Intel Xeon Processor 7200 Series and 7300 Series Enabled Components CEK 1 Mechanical Models Intel Xeon Processor 7200 Series and 7300 Series Boundary Scan Descriptive 1 Language BSDL Model N
140. mum and maximum case temperatures TcAsg are specified in Table 6 2 through Table 6 8 and are measured at the geometric top center of the processor integrated heat spreader IHS Figure 6 5 illustrates the location where Tcase temperature measurements should be made For detailed guidelines on temperature measurement methodology refer to the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series Thermal Mechanical Design Guide 102 Document Number 318080 002 m Thermal Specifications n tel Figure 6 5 Case Temperature Tcase Measurement Location 6 2 6 2 1 6 2 2 19 25 mm 0 76 in Measure T yg atthis point geometric center of IHS 19 25 mm 0 76 in Thermal grease should cover entire area of IHS Note Figure is not to scale and is for reference only Processor Thermal Features Thermal Monitor Features The Intel Xeon Processor 7200 Series and 7300 Series provide two thermal monitor features Thermal Monitor TM1 and Enhanced Thermal Monitor TM2 The TM1 and TM2 must both be enabled in BIOS for the processor to be operating within specifications When both are enabled TM2 will be activated first and TM1 will be added if TM2 is not effective Thermal Monitor The Thermal Monitor TM1 feature helps control the processor temperature by activating the Thermal Control Circuit TCC when the processor silicon reaches its maximum operating tempe
141. n and stops providing internal clock signals to all processor core units except the FSB and API C units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDO TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for J TAG specification support TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support TESTHI 1 0 TESTHI 1 0 must be connected to a Vi power source through a resistor for proper processor operation Refer to Section 2 5 for TESTHI grouping restrictions TESTIN1 TESTIN2 TESTIN1 must be connected to a VTT power source through a resistor as well as to the TESTIN2 pin of the same socket for proper processor operation TESTIN2 must be connected to a VTT power source through a resistor as well as to the TESTIN1 pin of the same socket for proper processor operation Refer to Section 2 5 for TESTIN restrictions THERMTRIP Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reac
142. n No Pin Name Signal Direction Buffer Type Buffer Type T1 Vss Power Other v9 Vss Power Other T2 Vcc Power Other V23 Vss Power Other T3 Vss Power Other V24 Vcc Power Other T4 Vec Power Other V25 Vss Power Other T5 Vss Power Other V26 Vcc Power Other T6 Vcc Power Other V27 Vss Power Other T7 Vss Power Other V28 Vcc Power Other T8 Vcc Power Other V29 Vss Power Other T9 Vss Power Other v30 Vcc Power Other T23 Vss Power Other V31 Vss Power Other T24 Vcc Power Other W1 Vcc Power Other T25 Vss Power Other w2 Vss Power Other T26 Vcc Power Other w3 TESTHI1 Power Other Input T27 Vss Power Other WA Vss Power Other T28 Vcc Power Other W5 BCLK1 FSB Clk Input T29 Vss Power Other W V Power Other T30 Vcc Power Other WI V Power Other T31 Vss Power Other W V Power Other U1 Vcc Power Other w9 GTLREF_DATA_END Power Other Input U2 Vss Power Other W23 GTLREF DATA MID Power Other Input U3 Vcc Power Other W24 Vss Power Other U4 Vss Power Other W25 Vcc Power Other U5 Vcc Power Other W26 Vss Power Other U6 Vss Power Other W27 Vcc Power Other U7 Vcc Power Other W28 Vss Power Other U8 Vss Power Other W29 Vcc Power Other u9 Vcc Power Other W30 Vss Power Other U23 Vec Power Other W31 Vcc Power Other U24 Vss Power Other Y1 Vss Power Other U25 Vcc Power Other Y2 Vcc Power Other U26 Vss Power Other Y3 Vss Power Other U27 Vcc Power Other Y4 BCLK0 FSB Clk Input U28 Vss Power Other Y5 Vss Power Other U29 Vcc Power Other Y6 Ver Power Other U30 Vs
143. nc Input Output B28 LL ID1 Power Other Output A21 Vss Power Other C1 VID6 Power Other Output A22 A3 Source Sync Input Output C2 TESTIN2 Power Other Input A23 MHITM Common Clk Input Output c3 VID3 Power Other Output A24 Vcc Power Other C4 Vcc Power Other A25 TMS TAP Input C5 Ver Power Other A26 Vcc sENSE2 Power Other Output C6 RSP Common Clk Input A27 Vss Power Other C7 Vss Power Other A28 Reserved C8 A35 Source Sync Input Output A29 Vss Power Other C9 A34 Source Sync Input Output A30 PROC IDO Power Other Output C10 Wm Power Other A31 Reserved C11 A30 Source Sync Input Output B1 Reserved C12 A23 Source Sync Input Output B2 Vss Power Other C13 Vss Power Other B3 VIDA Power Other Output C14 A163 Source Sync Input Output BA Reserved C15 AI15 Source Sync Input Output B5 Vor Power Other C16 A39 Source Sync Input Output B6 A38 Source Sync Input Output C17 A8 Source Sync Input Output B7 A314 Source Sync Input Output C18 A6 Source Sync Input Output B8 A274 Source Sync Input Output C19 Vss Power Other B9 Vss Power Other C20 REQ3 Common Clk Input Output B10 A21 Source Sync Input Output C21 REQ24 Common Clk Input Output B11 A224 Source Sync Input Output C22 Vcc Power Other Document Number 318080 002 79 intel Table 4 2 Pin Listing by Pin Number Sheet Pin Listing Table 4 2 Pin Listing by Pin Number Sheet
144. nd PECI interface The processor SMBus implementation uses the clock and data signals of the System Management Bus SMBus Specification It does not implement the SMBSUS signal For platforms which do not implement any of the SMBus features found on the processor all of the SMBus connections except SM VCC to the socket pins may be left unconnected SM CLK SM DAT SM EP A 2 0 SM WP Document Number 318080 002 Features Figure 7 2 7 4 1 Logical Schematic of SMBus Circuitry SM_VCC VCC SM_EP_AO DATA SM_EP_A1 Processor 07 Information CLK SM EP A2 ROM and Scratch SM WP EEPROM 1Kbit each vss SM_CLK e SM DAT e Note Actual implementation may vary This figure is provided to offer a general understanding of the architecture All SMBus pull up and pull down resistors are 10 kQ and located on the processor SMBus Device Addressing Of the addresses broadcast across the SMBus the memory component claims those of the form 1010XXXZb The XXX bits are defined by pull up and pull down resistors on the system baseboard These address pins are pulled down weakly 10 kQ on the processor substrate to ensure that the memory components are in a known state in systems which do not support the SMBus or only support a partial implementation The Z bit is the read write bit for the serial bus transaction Note that addresses of the form 0000XXXXb are Reserved a
145. nd should not be generated by an SMBus master The system designer must also ensure that their particular implementation does not add excessive capacitance to the address inputs Excess capacitance at the address inputs may cause address recognition problems Refer to the appropriate platform design guide document Figure 7 2 shows a logical diagram of the pin connections Table 7 3 describe the address pin connections and how they affect the addressing of the devices Document Number 318080 002 117 intel Table 7 3 7 4 2 Table 7 4 Table 7 5 118 Memory Device SMBus Addressing pog Nec Device Select R W SM EP A2 SM EP A1 SM EP AO bits 7 4 bit 3 bit 2 bit 1 bit 0 AOh Alh 1010 0 0 0 x A2h A3h 1010 0 0 1 x A4h A5h 1010 0 1 0 X A6h A7h 1010 0 1 1 X A8h A9h 1010 1 0 0 X AAh ABh 1010 1 0 1 X ACh ADh 1010 1 1 0 X AEh AFh 1010 1 1 1 X Note 1 This addressing scheme will support up to 8 processors on a single SMBus PI ROM and Scratch EEPROM Supported SMBus Transactions The Processor Information ROM PIROM responds to two SMBus packet types Read Byte and Write Byte However since the PIROM is write protected it will acknowledge a Write Byte command but ignore the data The Scratch EEPROM responds to Read Byte and Write Byte commands Table 7 4 diagrams the Read Byte command Table 7 5 diagrams the Write Byte command Following a write cycle to the scratch ROM
146. nology transitions or assertion of the FORCEPR signal See Section 6 Mixing processors of different steppings but the same model as per CPUID instruction is supported Details regarding the CPUID instruction are provided in the AP 485 Intel Processor Identification and the CPUID Instruction application note Absolute Maximum and Minimum Ratings Table 2 8 specifies absolute maximum and minimum ratings only which lie outside the functional limits of the processor Only within specified operation limits can functionality and long term reliability be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the pro
147. ns will be updated with characterized data from silicon measurements at a later date 2 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 4 for more information 3 The voltage specification requirements are measured across the VCC SENSE and VSS SENSE pins and across the VCC SENSE2 and VSS_SENSE2 pins with an oscilloscope set to 100 MHz bandwidth 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 4 The processor must not be subjected to any static Vcc level that exceeds the Vcc max associated with any particular current Failure to adhere to this specification can shorten processor lifetime 5 lec max specification is based on maximum Vcc loadline Refer to Figure 2 10 for details The processor is capable of drawing I cc MAX for up to 10 ms Refer to Figure 2 9 for further details on the average processor current draw over various time durations 6 FMBisthe flexible motherboard guideline These guidelines are for estimation purposes only See Section 2 11 1 for further details on FMB guidelines 7 This specification represents the total current for GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END 8 Vr must be provided via a separate voltage source and must not be connected
148. nside all processors without affecting their internal caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INI T assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor FSB agents LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all FSB agents When the APIC functionality is disabled the LINTO INTR signal becomes INTR a maskable interrupt request signal and LINT1 NMI becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LL ID 1 0 The LL ID 1 0 signals are used to select the correct loadline slope for the processor These signals are not connected to the processor die A logic 0 is pulled to ground and a logic 1 is a no connect on the Intel Xeon Processor 7200 Series and 7300 Series package LOCK 1 0 LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor FSB agents For a locked se
149. ntact your Intel Field Representative to obtain the processor signal integrity models which includes buffer and package models Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage CBULK such as electrolytic capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition Care must be taken in the baseboard design to ensure that the voltage provided to the processor Document Number 318080 002 15 e n tel Electrical Specifications 2 2 2 2 2 3 2 3 16 remains within the specifications listed in Table 2 9 Failure to do so can result in timing violations or reduced lifetime of the component For further information and guidelines refer to the appropriate platform design guidelines Vcc Decoupling Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR Bulk decoupling must be provided on the baseboard to handle large current swings The power delivery solution must ensure the voltage and current specifications are met as defined in Table
150. of system fans combined with ducting and venting This section provides data necessary for developing a complete thermal solution For more information on designing a component level thermal solution refer to the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series Thermal Mechanical Design Guide Thermal Specifications To allow the optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature TCASE specifications as defined by the applicable thermal profile see Table 6 1 and Figure 6 1 for Quad Core Intel Xeon Processor E7300 Series Table 6 3 and Figure 6 2 for Quad Core Intel Xeon X7350 Processor Table 6 5 and Figure 6 3 for Quad Core Intel Xeon L7345 Processor Table 6 7 and Figure 6 4 for Dual Core Intel Xeon Processor 7200 Series Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series Thermal Mechanical Design Guide The Intel Xeon Processor 7200 Series and 7300 Series implement a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and to assure processor reli
151. of the value Package Data This section provides package revision information PREV Package Revision This location tracks the highest level package revision It is provided in ASCII format of four characters 8 bits x 4 characters 32 bits The package is documented as 1 0 2 0 etc If this only consumes three ASCII characters a leading space is provided in the data field Example The Intel Xeon Processor 7200 Series and 7300 Series utilizes the first revision of the FC mPGA6 package Thus at offset 32 35h the data is a space followed by 1 0 In hex this would be 20h 31h 2Eh 30h Document Number 318080 002 131 7 4 3 5 2 7 4 3 5 3 7 4 3 6 7 4 3 6 1 132 Features Offset 32h 35h Bit Description 7 0 Character 4 ASCII character or 20h 00h OFFh ASCII character 15 8 Character 3 ASCII character 00h OFFh ASCII character 23 16 Character 2 ASCII character 00h OFFh ASCII character 31 24 Character 1 ASCII character 00h OFFh ASCII character RES5 Reserved 5 This location is reserved Writes to this register have no effect Offset 36h Bit Description 7 0 RESERVED 5 00h FFh Reserved PDCKS Package Data Checksum This location provides the checksum of the Package Data Section Writes to this register have no effect Offset 37h Bit Description 7 0 Package Data Checksum One Byte Checksum of the Packag
152. ons complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the appropriate platform design guidelines For each processor socket connect the TESTIN1 and TESTIN2 signals together then terminate the net with a 51 Oresistor to V r The TESTHI signal must be tied to the processor Vyr using a matched resistor where a matched resistor has a resistance value within 2096 of the impedance of the board transmission line traces For example if the trace impedance is 50 Q then a value between 40 Q and 60 Q is required The TESTHI signals may use individual pull up resistors or be grouped together as detailed below A matched resistor must be used for each group e TESTHI 1 0 can be grouped together with a single pull up to Vy Front Side Bus Signal Groups The FSB signals have been combined into groups by buffer type AGTL input signals have differential input buffers which use GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END as reference levels In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving AGTL asynchronous outputs can become active anytime and include an active PMOS pull up transistor to assist during the first clock of a low to high voltage transition With the implementation o
153. ooeooeooeo60lo0 90 y Mieeooojeooceooeooeoeooeooeooeolooee ABeeooeooeocoeooeoooeooeooeoo0 OO e AB ACIO e0jo 00060060060006000600900j00 9 9 AC ADOo6 6090000600000606009090090090 0O O O AD AE OOO00l6000Ooeooeoooeooeooeooeooo AE 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 CLOCKS DATA O Signal O VIT e VCC Reserved No Connect Ground 8 69 70 Mechanical Specifications Document Number 318080 002 Pin Listing 4 4 1 4 1 1 Table 4 1 Pin Listing by Pin Name Sheet 1 Pin Listing Pin Assignments Section 2 6 contains the front side bus signal groups for the Intel Xeon Processor 7200 Series and 7300 Series see Table 2 4 This section provides a sorted pin lists in Table 4 1 and Table 4 2 Table 4 1 is a listing of all processor pins ordered alphabetically by pin name Table 4 2 is a listing of all processor pins ordered by pin number Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Sheet 2 Document Number 318080 002 of 16 Pin Name Pin No Signal Direction Buffer Type A3 A22 Source Sync Input Output A4 A20 Source Sync Input Output A5 B18 Source Sync Input Output A6 C18 Source Sync Input Output ATH A19 Source Sync Input Output A8 C17 Source Sync Input Output A9 D17 Source Sync Input
154. op operation HITM 1 0 results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR O IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not have on die termination 90 Document Number 318080 002 Signal Definitions Table 5 1 Signal Definitions Sheet 5 of 8 Name IGNNE Type l Description IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CR0 is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction Notes INIT LINT 1 0 INIT Initialization when asserted resets integer registers i
155. otes 1 Document is available publicly at http developer intel com 2 Document available on www ssiforum org 8 Document Number 318080 002 14 Introduction Document Number 318080 002 m Electrical Specifications n tel 2 2 1 2 2 Electrical Specifications Front Side Bus and GTLREF Most Intel Xeon Processor 7200 Series and 7300 Series FSB signals use Assisted Gunning Transceiver Logic AGTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates AGTL buffers are open drain and require pull up resistors to provide the high logic level and termination AGTL output buffers differ from GTL buffers with the addition of an active PMOS pull up transistor to assist the pull up resistors during the first clock of a low to high voltage transition Platforms implement a termination voltage level for AGTL signals defined as V m Because platforms implement separate power planes for each processor and chipset separate Vcc and V supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases Speed enhancements to data and address buses have made signal integrity considerations and platform design methods even more critical than with previous processor families Design guidelines for the processor FSB are detailed in the appropriate platform design guidelines refer to Section
156. ouration n 17 2 2 BSEL 2 0 Frequency Table 17 2 3 Voltage Identification Definition ssssssssssssssssemmememe nemen ene 19 2 4 FSB Si9tiall Groups EE 21 2 5 AGTL Signal Description Table u cio iio rt eia encode i ASS ate d eu qsqa 22 2 6 Non AGTL Signal Description Table 22 2 7 Signal Reference Voltages essen mnes ne nee eese eren 22 2 8 Processor Absolute Maximum RatingS a mmm emnes 23 2 9 Voltage and Current Specifications sssssssssssssssseseeenememe nemen nene 25 2 10 VCC Static and Transient Tolerance sss nemen nen 30 2 11 AGTL Signal Group DC Specifications sess mme 34 2 12 CMOS Signal Input Output Group DC Gpechfications sss 35 2 13 Open Drain Signal Group DC Specifications rr 35 2 14 SMBus Signal Group DC Specifications r rr 35 2 15 BECH DC Electrical Llfmits i eoi oie ceret ger ref cre eec te ceat tb Ur en reg ge eus 36 2 16 VCC Overshoot Specifications senem meme see memes nnn 37 2 17 AGTL Bus Voltage Definitions ocococnccocococncnnnnnncnnnnnnnnnnnnnnn rn r nr nn nn nemen nnn 39 2 18 FSB Differential BCLK Specifications eene nemen enn 39 2 19 Front Side Bus Differential Clock AC Specifications r r 40 2 20 Front Side Bus Common Clock AC Specifications r 40 2 21 FSB Source Synchronous AC Gpechfications r rr 41 2 22 Miscellaneous GTL AC Gpechfications esses mmm emne
157. ous address signals are referenced to the rising and falling edge of their associated address strobe All source synchronous AGTL signal timings are referenced at nominal GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END at the processor core pads 4 Unless otherwise noted these specifications apply to both data and address timings 5 Valid delay timings for these signals are specified into the test circuit described in Figure 2 11 and with GTLREF_DATA_MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END at 0 67 Vr 6 Specification is for a minimum swing into the test circuit described in Figure 2 11 and defined between AGTL Mut max to Vin ww This assumes an edge rate of 3 0 V ns to 5 5 V ns 7 All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective strobe 8 This specification represents the minimum time the data or address will be valid before its strobe Refer to the appropriate platform design guidelines for more information on the definitions and use of these specifications 9 This specification represents the minimum time the data or address will be valid after its strobe Refer to the appropriate platform design guidelines for more information on the definitions and use of these specifications 10 The rising edge of ADSTB must come approximately 1 2 BCLK period after the falling edge of ADSTB 11 For this timing parameter n 1 2 and 3 for
158. owed by a 1 10 ms RESET pulse The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation Notes REQ 4 0 RESET 1 0 REQ 4 0 Request Command must connect the appropriate pins of all processor FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 1 0 Refer to the AP 1 0 signal description for details on parity checking of these signals Asserting the RESET signal resets all processors to known states and invalidates their internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least 1 ms after VCC and BCLK have reached their proper specifications On observing active RESET all FSB agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 7 1 This signal does not have on die termination and must be terminated on the system board RS 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropria
159. performance by allowing increased FSB speeds and bandwidth All versions of the Intel Xeon Processor 7200 Series and 7300 Series will include manageability features Components of the manageability features include an OEM EEPROM and Processor Information ROM which are accessed through an SMBus interface and contain information relevant to the particular processor and system in which it is installed The Intel Xeon Processor 7200 Series and 7300 Series is packaged in a 604 pin Flip Chip Micro Pin Grid Array FC mPGA6 package and utilizes a surface mount Zero Insertion Force ZIF mPGA604 socket The Intel Xeon Processor 7200 Series and 7300 Series support 40 bit addressing Quad Core Intel Xeon Processor 7300 Series Processor Features of Processor Cores L1 Cache per core L2 Advanced Transfer Cache Front Side Bus Frequency Package 4 32 KB instruction 32 KB data 4M Shared L2 Cache per die 8M Total Cache 1066 MHz FC mPGA6 Dual Core I ntel Xeon Processor 7200 Series Processor Features of Processor Cores L1 Cache per core L2 Advanced Transfer Cache Front Side Bus Frequency Package 2 32 KB instruction 32 KB data 4M L2 Cache per die 8M Total Cache 1066 MHz FC mPGA6 Intel Xeon Processor 7200 Series and 7300 Series based platforms implement independent core voltage Vcc power planes for each processor FSB termination vol
160. processor frequencies This specification is based on the capabilities of the ITP debug port not on processor silicon TRST must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor Specification for a minimum swing defined between TAP V to Vi4 This assumes a minimum edge rate of 43 intel Electrical Specifications Table 2 25 VID Signal Group AC Specifications T Parameter Min Max Unit Figure Notes 2 T80 VID Step Time 5 us 2 27 T81 VID Dwell Time at 266 666 MHz FSB 500 us 2 27 T82 VID Down Transition to Valid Vcc min 0 us 2 26 2 27 T83 VID Up Transition to Valid Vcc min 50 us 2 26 2 27 T84 VID Down Transition to Valid Vcc max 50 us 2 26 2 27 T85 VID Up Transition to Valid Vcc max 0 us 2 26 2 27 Notes 1 See Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for addition information 2 Platform support for VID transitions is required for the processor to operate within specifications Table 2 26 SMBus Signal Group AC Specifications T Parameter Min Max Unit Figure Notes 1 2 T90 SM CLK Frequency 10 100 KHz T91 SM CLK Period 10 100 us T92 SM CLK High Time 4 0 N A us 2 22 T93 SM CLK Low Time 4 7 N A us 2 22 T94 SMBus Rise Time 0 02 1 0 us 2 22 T95 SMBus Fall Time 0 02 0 3 us 2 22 T96 SMBus Output Valid Delay 0 1 4 5
161. quence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock MCERR 1 0 MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor FSB agents MCERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled e Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the Intel amp 64 and IA 32 Architectures Software Developer s Manual Volume 3 System Programming Guide PECI 1 0 PECI is a proprietary one wire bus interface that provides a communication channel between Intel processor and chipset components to external thermal monitoring devices See Section 6 3 Platform Environment Control Interface PECI for more on the PECI interface PROC ID 1 0 PROC ID signals are u
162. r and input voltage via the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption A processor enabled for Thermal Monitor 2 includes two operating points each consisting of a specific operating frequency and voltage which is identical for both processor dies The first operating point represents the normal operating condition for the processor Under this condition the core frequency to system bus multiplier utilized by the processor is that contained in the CLOCK FLEX MAX MSR and the VID that is specified in Table 2 3 The second operating point consists of both a lower operating frequency and voltage The lowest operating frequency is determined by the lowest supported bus ratio 1 6 for the Intel Xeon Processor 7200 Series and 7300 Series When the TCC is activated the processor automatically transitions to the new frequency This transition occurs rapidly on the order of 5 us During the frequency transition the processor is unable to service any bus requests and consequently all bus traffic is blocked Edge triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2
163. r Other M3 Vcc Power Other P24 Vcc Power Other M4 Vss Power Other P25 Vss Power Other M5 Vcc Power Other P26 Vcc Power Other M6 Vss Power Other P27 Vss Power Other M7 Vcc Power Other P28 Vcc Power Other M8 Vss Power Other P29 Vss Power Other M9 Vcc Power Other P30 Vcc Power Other M23 vc Power Other P31 Vss Power Other M24 Vss Power Other R1 Vcc Power Other M25 Vcc Power Other R2 Vss Power Other M26 Vss Power Other R3 Vcc Power Other M27 Vcc Power Other R4 Vss Power Other M28 Vss Power Other R5 Vcc Power Other M29 Vcc Power Other R6 Vss Power Other M30 Vss Power Other R7 Vcc Power Other M31 Vcc Power Other R8 Vss Power Other N1 Vcc Power Other R9 Vcc Power Other N2 Vss Power Other R23 Vcc Power Other N3 Vcc Power Other R24 Vss Power Other N4 Vss Power Other R25 Vcc Power Other N5 Vcc Power Other R26 Vss Power Other N6 Vss Power Other R27 Vcc Power Other N7 Vcc Power Other R28 Vss Power Other N8 Vss Power Other R29 Vcc Power Other N Mer Power Other R30 Vss Power Other N23 vc Powe Othe R31 Vcc Power Other 82 Document Number 318080 002 Pin Listing Table 4 2 Pin Listing by Pin Number Sheet intel Table 4 2 Pin Listing by Pin Number Sheet 9 of 14 10 of 14 Pin No Pin Name Signal Direction Pi
164. r consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor and Thermal Monitor 2 features On Demand mode is intended as a means to reduce system level power consumption Systems utilizing the Intel Xeon Processor 7200 Series and 7300 Series must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the 1A32_CLOCK_MODULATION MSR is set to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same IA32 CLOCK MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On Demand mode may be used in conjunction with the Thermal Monitor however if the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode Document Number 318080 002 105 e n tel Thermal Specifications 6 2 6 6 2 7 106 PROCHOT Signal An external signal PROCHOT processor hot is asserted when the temperature of either processor die has reached its factory configured trip point If Thermal Monitor is enabled note that Thermal Monitor must be enabled for th
165. r have no effect Bit 5 and Bit 6 are mutually exclusive only one bit will be set Offset 78h Bit Description Multi Core set if the processor is a multi core processor Serial signature set if there is a serial signature at offset 4D 54h Electronic signature present set if there is a electronic signature at 4D 54h Thermal Sense Device present set if an SMBus thermal sensor on package Reserved OEM EEPROM present set if there is a scratch ROM at offset 80 FFh Core VID present set if there is a VID provided by the processor O FINI wy AJ OY O L3 Cache present set if there is a level 3 cache on the processor Bits are set when a feature is present and cleared when they are not Example A value of A6h can be found at offset 78h Processor Thread and Core I nformation This location contains information regarding the number of cores and threads on the processor Writes to this register have no effect Example The Intel Xeon Processor 7200 Series and 7300 Series has two or four cores and one thread per core Document Number 318080 002 135 7 4 3 8 4 7 4 3 8 5 7 4 3 9 7 4 3 9 1 136 Features Offset 79h Bit Description 7 2 Number of cores 1 0 Number of threads per core Additional Processor Feature Flags This location contains additional feature information for the processor This field is defined as fo
166. r other comparable industry standard interfaces The PECI client is as reliable as the device that it is embedded in and thus given operating conditions that fall under the specification the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures There are however certain scenarios where the PECI is known to be unresponsive Document Number 318080 002 109 e n tel Thermal Specifications 6 3 2 3 Prior to a power on RESET and during RESET assertion PECI is not guaranteed to provide reliable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host controller should take action to protect the system from possible damaging states If the Host controller cannot complete a valid PECI transactions of GetTempO with a given PECI device over 3 consecutive failed transactions or a one second max specified interval then it should take appropriate actions to protect the corresponding device and or other system components from overheating The host controller may also implement an alert to software in the event of a critical or continuous fault condition PECI GetTempO and GetTemp1 Error Code Support The error codes supported for the processor
167. ration measured at heatsink mass The dynamic portion of this specification in the product application can have flexibility in specific values but the ultimate product of mass times acceleration should not exceed this validated dynamic load 1 Ibm x 100 G 100 Ib 8 Transient loading is defined as a 2 second duration peak load superimposed on the static load requirement representative of loads experienced by the package during heatsink installation Document Number 318080 002 Mechanical Specifications n tel 3 4 Table 3 2 3 5 3 6 3 7 Table 3 3 Package Handling Guidelines Table 3 2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N 80 Ibf 1 Tensile 156 N 35 Ibf 3 2 Torque 8 N m 70 Ibf in 4 2 Notes 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 These guidelines are based on limited testing for design characterization 3 Atensile load is defined as a pulling load applied to the IHS in the direction normal to the IHS surface 4 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface Package Insertion Specifica
168. rature The TCC reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the TM1 is enabled and a high temperature situation exists that is TCC is active the clocks will be modulated by alternately turning the clocks off and on ata duty cycle specific to the processor typically 30 50 Cycle times are processor Document Number 318080 002 103 e n tel Thermal Specifications 6 2 3 Note 104 speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With thermal solutions designed to each of the Intel Xeon Processor 7200 Series and 7300 Series Thermal Profile it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance imp
169. ries Vcc Static and Transient Tolerance Load Lines Icc A 0 5 10 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 VID 0 000 VID 0 020 Voc Maximum VID 0 040 VID 0 060 VID 0 080 Vcc V VID 0 100 Voc VID 0 120 Typical Voc Minimum VID 0 140 VID 0 160 Notes 1 The Vcc min and Vcc max loadlines represent static and transient limits Please see Section 2 11 3 for VCC overshoot specifications Refer to Table 2 9 for processor VID information Refer to Table 2 10 for VccStatic and Transient Tolerance The load lines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE pins and the VCC_SENSE2 and VSS SENSE2 pins Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE2 and VSS SENSE2 pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation 2 3 4 AGTL Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes Vu Input Low Voltage 0 10 0 GTLREF 0 10 V 2 4 6 Vin Input High Voltage GTLREF 0 10 Vit V rr 0 10 V 3 6 Vou Output High Voltage Vr 0 10 N A Vit V 4 6 Ron Buffer On Resistance 10 00 11 50 13 00 Q 5 lu Input Leakage Current N A N A 100 HA 7 8 Notes
170. rocessors operate only at or below the frequency marked on the package 2 Listed frequencies are not necessarily committed production frequencies 3 For valid processor core frequencies refer to the Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor 7300 Series Specification Update 4 The lowest bus ratio supported is 1 6 Front Side Bus Frequency Select Signals BSEL 2 0 Upon power up the FSB frequency is set to the maximum supported by the individual processor BSEL 2 0 are CMOS outputs that are used to select the FSB frequency Please refer to Table 2 11 for DC specifications Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the processor s chipset and clock synthesizer All FSB agents must operate at the same core and FSB frequency See the appropriate platform design guidelines for further details BSEL 2 0 Frequency Table BSEL2 BSEL1 BSELO Bus Clock Frequency 0 0 0 266 MHz 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved PLL Power Supply An on die PLL filter solution is implemented on the processor The Vocp input is used to provide power to the on chip PLL of the processor Please refer to Table 2 9 for DC specifications Refer to the appropriate platform design guidelines for decoupling and rou
171. rt TAP logic TRST must be driven low during power on Reset VccPLL The Intel Xeon Processor 7200 Series and 7300 Series implement an on die PLL filter solution The VccpuL input is used as a PLL supply voltage VCC_SENSE VCC_SENSE2 VCC SENSE and VCC SENSE2 provides an isolated low impedance connection to the processor core power and ground These signals should be used to provide feedback to the voltage regulator signals which ensure the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation details Document Number 318080 002 93 m e n tel Signal Definitions Table 5 1 Signal Definitions Sheet 8 of 8 Name Type Description Notes VID 6 1 O VID 6 1 Voltage ID pins are used to support automatic selection of power supply voltages Vcc These are CMOS signals that are driven by the processor and must be pulled up through a resistor Conversely the voltage regulator output must be disabled prior to the voltage supply for these pins becomes invalid The VID pins are needed to support processor voltage specification variations See Table 2 3 for definitions of these pins The VR must supply the voltage that is requested by these pins or disable itself VSS_SENSE O VSS SENSE and VSS SENSE2 provides an isolated low impedance connection to the VSS SENSE2 processor core power and ground These signals sho
172. rved 29 21 Extended Family 00h OFh Extended Family 21 18 Extended Model Oh Fh Extended Model 17 16 Reserved 00b 11b Reserved 15 14 Processor Type 00b 11b Processor Type 13 10 Processor Family Oh Fh Processor Family 9 6 Processor Model Oh Fh Processor Model 5 2 Processor Stepping Oh Fh Processor Stepping 1 0 Reserved 00b 11b Reserved 7 4 3 3 2 FSB Front Side Bus Speed This location contains the front side bus frequency information Systems may need to read this offset to decide if all installed processors support the same front side bus speed Because the FSB is described as a 4X data bus the frequency given in this field is 1066 MTS The data provided is the speed rounded to a whole number and reflected in hex Writes to this register have no effect Example The Intel Xeon Processor 7200 Series and 7300 Series supports a 1066 MTS front side bus Therefore offset 1A 1Bh has a value of 042Ah Offset 1Ah 1Bh Bit Description 15 0 Front Side Bus Speed 0000h FFFFh MHz Document Number 318080 002 127 intel 7 4 3 3 3 7 4 3 3 4 7 4 3 3 5 128 MPSUP Multiprocessor Support This location contains 2 bits for representing the supported number of physical processors on the bus These two bits are MSB aligned where 00b equates to single processor operation 01b is a dual processor operation and 11b repres
173. s To use the VR as an example when FORCEPR is asserted the TCC circuit in the processor will activate reducing the current consumption of the processor and the corresponding temperature of the VR It should be noted that assertion of FORCEPR does not automatically assert PROCHOT As mentioned previously the PROCHOT signal is asserted when a high temperature situation is detected A minimum pulse width of 500 us is recommended when FORCEPR is asserted by the system Sustained activation of the FORCEPR signal may cause noticeable platform performance degradation THERMTRI P Signal Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when either die has reached an elevated temperature refer to the THERMTRIP definition in Table 5 1 At this point the FSB signal THERMTRIP will go active and stay active as described in Table 5 1 THERMTRIP activation is independent of processor activity and does not generate any bus cycles If THERMTRIP is asserted processor core voltage Vcc must be removed within the time frame defined in Table 2 22 and Figure 2 21 Intel also recommends the removal of Vr Document Number 318080 002 Thermal Specifications 6 3 6 3 1 Figure 6 7 6 3 1 1 Document Number 318080 002 intel Platform Environment Control I nterface PECI Introduction PECI offers an interface for ther
174. s 42 2 23 Front Side Bus AC Specifications Reset Conditions nes 42 2 24 TAP Signal Group AC Specifications cece ete ne nemen ene 42 2 25 VID Signal Group AC Specifications rr nemen emen een 44 2 26 SMBus Signal Group AC Specifications cece mmm 44 3 1 Processor Loading Specifications memes 66 3 2 Package Handling Guidelines nena nemen nnns 67 3 3 Processor Materials 2 onore eco rr petiere ede Ur eric Ep tat erede IERE DENES ER 67 4 1 Pin Listing by Pin Name 71 4 2 Pin Listing by Pin NUMDEF eege Eeer emer e Lr ER EEN rena aka ae Fee esie duda 79 5 L Signal Definitions exe eeepc ee a DAR E TRERE TAMEN E MERE 87 6 1 Quad Core Intel Xeon E7300 Processor Thermal Specifications 96 6 2 Quad Core Intel Xeon E7300 Processor Thermal Profile Table 97 6 3 Quad Core Intel Xeon X7350 Processor Thermal Gpechfications 98 6 4 Quad Core Intel Xeon X7350 Processor Thermal Profile Table 99 6 5 Quad Core Intel Xeon L7345 Processor Thermal Specifications 99 6 6 Quad Core Intel Xeon L7345 Processor Thermal Profile 100 6 7 Dual Core Intel Xeon Processor 7200 Series Thermal Specifications 101 6 8 Dual Core Intel Xeon Processor 7200 Series Thermal Profile 102 6 9 BREQ si
175. s Power Other Y7 Vss Power Other U31 Vcc Power Other Y8 RESET Common Clk Input V1 Vss Power Other Y9 D62 Source Sync Input Output V2 Vcc Power Other Y10 Ver Power Other V3 Vss Power Other Y11 DSTBP3 Source Sync Input Output VA Vcc Power Other Y12 DSTBN3 Source Sync Input Output V5 Vss Power Other Y13 Vss Power Other V6 Vcc Power Other Y14 DSTBP2 Source Sync Input Output V7 Vss Power Other Y15 DSTBN2 Source Sync Input Output V8 Vcc Power Other Y16 Vcc Power Other Document Number 318080 002 83 intel Table 4 2 Pin Listing by Pin Number Sheet Pin Listing Table 4 2 Pin Listing by Pin Number Sheet 11 of 14 12 of 14 Pin No Pin Name Signal Direction Pin No Pin Name Signal Direction Buffer Type Buffer Type Y17 DSTBP1 Source Sync Input Output AA30 Vss Power Other Y18 DSTBN1 Source Sync Input Output AA31 Vcc Power Other Y19 Vss Power Other AB1 Vss Power Other Y20 DSTBPO Source Sync Input Output AB2 Vcc Power Other Y21 DSTBNO Source Sync Input Output AB3 BSEL1 Power Other Output Y22 Vcc Power Other AB4 Reserved Y23 D5 Source Sync Input Output AB5 Vss Power Other Y24 D2 Source Sync Input Output AB6 D63 Source Sync Input Output Y25 Vss Power Other AB7 PWRGOOD Async GTL Input Y26 D0 Source Sync Input Output AB8 Vcc Power Other
176. se sections are described below Reserved fields or bits SHOULD be programmed to zeros However OEMs should not rely on this model Header To maintain backward compatibility the Header defines the starting address for each subsequent section of the PIROM Software should check for the offset before reading data from a particular section of the ROM Example Code looking for the cache data of a processor would read offset 05h to find a value of 25h 25h is the first address within the Cache Data section of the PIROM DFR Data Format Revision This location identifies the data format revision of the PIROM data structure Writes to this register have no effect Offset 00h Bit Description 7 0 Data Format Revision The data format revision is used whenever fields within the PIROM are redefined The initial definition will begin at a value of 1 If a field or bit assignment within a field is changed such that software needs to discern between the old and new definition then the data format revision field will be incremented 00h Reserved 01h Initial definition 02h Second revision 03h Third revision 04h Fourth revision Defined by this document O5h FFh Reserved Document Number 318080 002 121 intel 7 4 3 1 2 PISI ZE PI ROM Size This location identifies the PI ROM size Writes to this register have no effect Offset O1h 02h Bit Description 15 0 PIROM Size The PI
177. sed to identify which processor is installed 00 Intel Xeon Processor 7400 Series 01 Intel Xeon Processor 7200 Series and 7300 Series 10 Reserved 11 Reserved PROCHOT PROCHOT Processor Hot will go active when the processor s temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the Thermal Control Circuit TCC has been activated if enabled The TCC will remain active until shortly after the processor deasserts PROCHOT See Section 6 2 5 for more details Document Number 318080 002 91 intel Table 5 1 Signal Definitions Signal Definitions Sheet 6 of 8 Name PWRGOOD Type l Description PWRGOOD Power Good is an input The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state Figure 2 24 illustrates the relationship of PWRGOOD to the RESET signal PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 2 16 and be foll
178. software must allow a minimum of 10 ms before accessing either ROM of the processor In the tables S represents the SMBus start bit P represents a stop bit R represents a read bit W represents a write bit A represents an acknowledge ACK and represents a negative acknowledge NACK The shaded bits are transmitted by the Processor Information ROM or Scratch EEPROM and the bits that aren t shaded are transmitted by the SMBus host controller In the tables the data addresses indicate 8 bits The SMBus host controller should transmit 8 bits with the most significant bit indicating which section of the EEPROM is to be addressed the Processor Information ROM MSB 0 or the Scratch EEPROM MSB 1 Read Byte SMBus Packet s l Write EN comman Es Slave Read A Data Hl P A d Code Address 1 7 bits 1 1 8 bits mE 7 bits 1 ii 8 bits 1 1 Write Byte SMBus Packet S Slave Address Write A Command Code A Data A P 1 7 bits 1 1 8 bits 1 8 bits 1 1 Document Number 318080 002 Features 7 4 3 Processor Information ROM PIROM intel The lower half 128 bytes of the SMBus memory component is an electrically programmed read only memory with information about the processor This information is permanently write protected Table 7 6 shows the data fields and Section 7 4 3 provides the formats of the data fields included in t
179. sor 7200 Series and 7300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at_http www intel com Intel Pentium Intel Xeon Intel SpeedStep Intel Core and Intel Virtualization Technology are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Intel 64 requires a computer system with a processor chipset BIOS OS device drivers and applications enabled for Intel 64 Processor will not operate including 32 bit operation without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations Intel 64 enabled OS BIOS device drivers and applications may not be available Check with your vendor for more information Other names and brands may be claimed as the property of others Copyright 2006 2008 Intel Corporation 2 Document Number 318080 002 Contents 1 Bi de TT d LEE 9 fu Een ge lu te e Le KEE 11 1 2 State of Data al q singe er see e uay qta ege Ee ege 13 T3 Re
180. state The event will be latched and can be serviced by software upon exit from the Stop Grant state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the Grant Snoop state will occur when the processor detects a snoop on the front side bus see Section 7 2 4 1 Document Number 318080 002 Features 7 2 4 7 2 4 1 7 2 4 2 7 3 Note intel While in the Stop Grant state SMI INIT BINIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus The PBE signal can be driven when the processor is in Stop Grant state PBE will be asserted if there is any pending interrupt latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that it should return the processor to the Normal state Extended HALT Snoop or HALT Snoop State Stop Grant Snoop State The Extended HALT Snoop state is used in conjunction with the Extended HALT state If the Extended H
181. tage Vor is shared and must connect to all FSB agents The processor core voltage utilizes power delivery guidelines specified by VRM EVRD 11 0 and its associated load line see Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details VRM EVRD 11 0 will support the power requirements of all frequencies of the processors including Flexible Motherboard Guidelines FMB see Section 2 11 1 Refer to the appropriate platform design guidelines for implementation details The Intel Xeon Processor 7200 Series and 7300 Series supports 1066 MHz Front Side Bus operation The FSB utilizes a split transaction deferred reply protocol and Source Synchronous Transfer SST of address and data to improve performance The processor transfers data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or a 2X address bus In addition the Request Phase completes in one clock cycle Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 8 5 GBytes per second The FSB is also used to deliver interrupts Document Number 318080 002 Introduction 1 1 intel Signals on the FSB use Assisted Gunning Transceiver Logic AGTL level voltages Section 2 1 contains the electrical specifications of the FSB while implementation
182. te pins of all processor FSB agents RSP SKTOCC RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of all processor FSB agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity SKTOCC Socket occupied will be pulled to ground by the processor to indicate that the processor is present There is no connection to the processor silicon for this signal SM_CLK 1 0 The SM_CLK SMBus Clock signal is an input clock to the system management logic which is required for operation of the system management features of thel ntel Xeon Processor 7200 Series and 7300 Series This clock is driven by the SMBus controller and is asynchronous to other clocks in the processor The processor includes a 10 kQ pull up resistor to SM VCC for this signal SM DAT 1 0 The SM_DAT SMBus Data signal is the data signal for the SMBus This signal provides the single bit mechanism for transferring data between SMBus devices The processor includes a 10 kQ pull up resistor to SM_VCC for this signal SM_EP_A 2 0 The SM_EP_A EEPROM Select Addr
183. terization and are not tested 2 AllDC specifications for the SMBus signal group are measured at the processor pins 3 Platform designers may need this value to calculate the maximum loading of the SMBus and to determine maximum rise and fall times for SMBus signals 2 11 2 Specifications Platform Environmental Control I nterface PECI DC PECI is an Intel proprietary one wire bus interface that provides a communication channel between Intel processor and external thermal monitoring devices The Dual Core Intel Xeon Processor 7200 Series and Quad Core Intel Xeon Processor Document Number 318080 002 35 2 11 2 1 Electrical Specifications 7300 Series contains Digital Thermal Sensors DTS distributed throughout the die These sensors are implemented as analog to digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal fan speed control DC Characteristics A PECI device interface operates at a nominal voltage set by Vrr The set of DC electrical specifications shown in Table 2 15 is used with devices normally operating from a V interface supply Vrr nominal levels will vary between processor families All PECI devices will operate at the Vor level determined by the processor installed in the system For specifi
184. tes to this register have no effect Example The Intel Xeon Processor 7200 Series and 7300 Series does not utilize a Cache VID Offset 2B 2Ch will contain 0000h 0 decimal Offset 2Bh 2Ch Bit Description 15 0 Maximum Cache VID 0000h FFFFh mV Document Number 318080 002 Features 7 4 3 4 5 7 4 3 4 6 7 4 3 4 7 7 4 3 5 7 4 3 5 1 intel This location contains the minimum Cache voltage This field rounded to the next thousandth is in mV and is reflected in hex The minimum Veache reflected in this field is the minimum allowable voltage assuming the FMB maximum current draw for two processors Writes to this register have no effect MINV Minimum Cache Voltage Example The Intel Xeon Processor 7200 Series and 7300 Series does not utilize a Cache VID Offset 2D 2Eh will contain 0000h 0 decimal Offset 2Dh 2Eh Bit Description 15 0 Minimum Cache Voltage 0000h FFFFh mV RES4 Reserved 4 These locations are reserved Writes to this register have no effect Offset 2Fh 30h Bit Description 15 0 RESERVED 4 0000h FFFFh Reserved CDCKS Cache Data Checksum This location provides the checksum of the Cache Data Section Writes to this register have no effect Offset 31h Bit Description 7 0 Cache Data Checksum One Byte Checksum of the Cache Data Section 00h FFh See Section 7 4 4 for calculation
185. the second third and last data strobes respectively 12 The address strobe setup time is measured with respect to T2 Calculation of the setup time is as follows a f T27 BCLK period then the setup time calculated is positive The value calculated indicates setup time before T1 b f T27 lt BCLK period then the setup time calculated is negative The value calculated indicates setup time after T1 Refer to Figure 2 17 13 This specification applies only to DSTBN 3 0 and is measured to the second falling edge of the strobe 14 This specification reflects a typical value not a minimum or maximum 15 For this timing parameter n 0 to 1 Document Number 318080 002 41 intel Electrical Specifications Table 2 22 Miscellaneous GTL AC Specifications T Parameter Min Max Unit Figure toa T35 Asynchronous GTL input pulse width 30 ns 5 T36 PWRGOOD assertion to RESET de assertion 1 10 ms 2 24 T37 BCLK stable to PWRGOOD assertion 10 BCLKs 2 24 6 12 T38 PROCHOT pulse width 500 us 2 20 7 T39 THERMTRIP assertion until Vcc removed 500 ms 2 21 8 T40 FERR valid delay from STPCLK deassertion 0 5 BCLKs 2 25 T41 Vcc stable to PWRGOOD assertion 0 05 500 ms 2 24 10 T42 PWRGOOD rise time 20 ns 11 T43 Vcc goor Stable to VID BSEL valid 10 us 2 24 9 10 T44 VID BSEL valid to Vcc stable 100 us 2 24 10 T48 Vyr stable to VID BSEL valid 10 us 2 24 10 T49 Vccp stabl
186. ther K24 Mes Power Other HA Vss Power Other K25 Vcc Power Other H5 Vcc Power Other K26 Vss Power Other H6 Vss Power Other K27 Vcc Power Other H7 Vcc Power Other K28 Vss Power Other H8 Vss Power Other K29 Vcc Power Other H9 Vcc Power Other K30 Vss Power Other H23 Vcc Power Other K31 Vcc Power Other H24 Vss Power Other L1 Vss Power Other H25 Vcc Power Other L2 Vcc Power Other Document Number 318080 002 81 l n tel Pin Listing Table 4 2 Pin Listing by Pin Number Sheet Table 4 2 Pin Listing by Pin Number Sheet 7 of 14 8 of 14 Pin No Pin Name Signal Direction Pin No Pin Name Signal Direction Buffer Type Buffer Type L3 Vss Power Other N24 Vss Power Other L4 Vcc Power Other N25 Vcc Power Other L5 Vss Power Other N26 Vss Power Other L6 Vcc Power Other N27 Vcc Power Other L7 Vss Power Other N28 Vss Power Other L8 Vcc Power Other N29 Vcc Power Other L9 Vss Power Other N30 Vss Power Other L23 Vss Power Other N31 Vcc Power Other L24 Vcc Power Other P1 Vss Power Other L25 Vss Power Other P2 Vcc Power Other L26 Vcc Power Other P3 Vss Power Other L27 Vss Power Other P4 Vcc Power Other L28 Vcc Power Other P5 Vss Power Other 129 Vs Power Other Pe Vcc Power Other L30 Vcc Power Other P7 Vss Power Other L31 Vss Power Other P8 Vcc Power Other M1 Vcc Power Other P9 Vss Power Other M2 Vss Power Other P23 Vss Powe
187. ther Vcc K3 Power Other Vcc D18 Power Other Vcc K5 Power Other Vcc D24 Power Other Vcc K7 Power Other Vcc D31 Power Other Vcc K9 Power Other Vcc E6 Power Other Vcc K23 Power Other Vcc E20 Power Other Vcc K25 Power Other Vcc E26 Power Other Vcc K27 Power Other Vcc E28 Power Other Vcc K29 Power Other Vcc E30 Power Other Vcc K31 Power Other Vcc F1 Power Other Vcc L2 Power Other Vcc F4 Power Other Vcc L4 Power Other Vcc F29 Power Other Vcc L6 Power Other Vcc F31 Power Other Vcc L8 Power Other Vcc G2 Power Other Vcc L24 Power Other Vcc G4 Power Other Vcc L26 Power Other Vcc G6 Power Other Vcc L28 Power Other Vcc G8 Power Other Vcc L30 Power Other 74 Document Number 318080 002 Pin Listing Table 4 1 Pin Listing by Pin Name Sheet 9 intel Table 4 1 Pin Listing by Pin Name Sheet of 16 10 of 16 Pin Name Pin No Signal Direction Pin Name Pin No Signal Direction Buffer Type Buffer Type Vcc M1 Power Other Vcc T6 Power Other Vcc M3 Power Other Vcc T8 Power Other Vcc M5 Power Other Vcc T24 Power Other Vcc M7 Power Other Vcc T26 Power Other Vcc M9 Power Other Vcc T28 Power Other Vcc M23 Power Other Vcc T30 Power Other Vcc M25 Power Other Vcc U1 Power Other Vcc M27 Power Other Vcc U3 Power Other Vcc M29 Power Other Vcc U5 Power Other Vcc M31 Power Other Vcc U7 Power Other Vcc N1 Power Other V
188. timized segment The Quad Core Intel Xeon L7345 Processor is a lower voltage lower power processor Enhanced thermal and power management capabilities are implemented including Thermal Monitor TM1 Thermal Monitor 2 TM2 and Enhanced Intel SpeedStep Technology TM1 and TM2 provide efficient and effective cooling in high temperature situations Enhanced Intel SpeedStep Technology allows trade offs to be made between performance and power consumption This may lower average power consumption in conjunction with OS support The Intel Xeon Processor 7200 Series and 7300 Series features include Advanced Dynamic Execution enhanced floating point and multi media units Streaming SIMD Extensions 2 SSE2 and Streaming SIMD Extensions 3 SSE3 Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor The floating point and multi media units include 128 bit wide registers and a separate register for data movement SSE3 instructions provide highly efficient double precision floating point SIMD integer and memory management operations The Intel Xeon Processor 7200 Series and 7300 Series support Intel 64 as an enhancement to Intel s IA 32 architecture This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Further details on Intel 64 Technology and its programming model can be found in the Intel 6
189. ting guidelines Voltage Identification VI D The Voltage Identification VID specification for the processor is defined by the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor Vcc pins VID signals are asynchronous CMOS Document Number 318080 002 17 e n tel Electrical Specifications outputs Please refer to Table 2 12 for the DC specifications for these signals A voltage range is provided in Table 2 3 and changes with frequency The specifications have been set such that one voltage regulator can operate with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two devices at the same core frequency may have different default VID settings This is reflected by the VID range values provided in Table 2 3 The processor uses six voltage identification signals VID 6 1 to support automatic selection of power supply voltages Table 2 3 specifies the voltage level corresponding to the state of VID 6 1 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level The definition provided in Table 2 3 is not related in any way to previous Intel Xeon processors or voltage regulator designs If the processor socket is empty VID 6 1 111111 or the voltage regulation circuit cannot supply th
190. tions The Intel Xeon Processor 7200 Series and 7300 Series can be inserted into and removed from a mPGA604 socket 15 times The socket should meet the mPGA604 requirements detailed in the mPGA604 Socket Design Guidelines Processor Mass Specifications The typical mass of the Intel Xeon Processor 7200 Series and 7300 Series is 37 6 g 1 50z This mass weight includes all the components that are included in the package Processor Materials Table 3 3 lists some of the package components and associated materials Processor Materials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Pins Gold Plated Copper Document Number 318080 002 67 m e n tel Mechanical Specifications Figure 3 9 Processor Markings Figure 3 9 shows the topside markings and Figure 3 10 shows the bottom side markings on the processor These diagrams are to aid in the identification of the Intel Xeon Processor 7200 Series and 7300 Series Please note that the figures in this section are not to scale Processor Topside Markings INTEL XEON i M YY PbFree symbol 2D Matrix FPO Serial Tues Pin 1 Indicator Notes 1 Character size for laser markings is 17 Point height 1 27 mm 50 mils width 0 81 mm 32 mils 2 All characters will be in upper case Figure 3 10 Processor Bottom Side Markings 68 Pin
191. to Vcc This specification is measured at the pin Document Number 318080 002 m Electrical Specifications n tel 10 11 12 13 14 15 16 17 Minimum VCC and maximum ICC are specified at the maximum processor case temperature TCASE shown in Figure 6 2 This specification refers to the total reduction of the load line due to VID transitions below the specified VID Individual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings This specification applies to the VCCPLL pin Baseboard bandwidth is limited to 20 MHz Icc toc is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please see the applicable design guidelines for further details The processor is capable of drawing Icc tpc indefinitely Refer to Figure 2 9 for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested This is the maximum total current drawn from the Ver plane by only one processor with Rrr enabled This specification does not include the current coming from on board termination Rrr through the signal line
192. tput AE24 Vcc Power Other AD15 Vss Power Other AE25 D19 Source Sync Input Output AD16 Reserved AE26 D16 Source Sync Input Output AD17 Vss Power Other AE27 Vss Power Other AD18 D36 Source Sync Input Output AE28 SM_VCC Power Other AD19 D30 Source Sync Input Output AE29 SM_VCC Power Other AD20 Vcc Power Other AE30 Reserved Document Number 318080 002 85 86 Pin Listing Document Number 318080 002 Signal Definitions 5 Signal Definitions 5 1 Signal Definitions Table 5 1 Signal Definitions Sheet 1 of 8 Name Type Description Notes A 39 3 1 0 A 39 3 Address define a 24 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the Intel Xeon Processor 7200 Series and 7300 Series FSB A 39 3 are protected by parity signals AP 1 0 A 39 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processors sample a subset of the A 39 3 pins to determine their power on configuration See Section 7 1 A20M If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transa
193. uld be used to provide feedback z to the voltage regulator signals which ensure the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation details VTT P The FSB termination voltage input pins Refer to Table 2 9 for further details VTT_SEL O The VIT SEL signal is used to select the correct V4 voltage level for the processor VIT SEL is a no connect on the Intel Xeon Processor 7200 Series and 7300 Series package 8 94 Document Number 318080 002 Thermal Specifications n tel 6 6 1 6 1 1 Thermal Specifications Package Thermal Specifications The Intel Xeon Processor 7200 Series and 7300 Series requires a thermal solution to maintain temperatures within its operating limits Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader IHS Typical system level thermal solutions may consist
194. urce Sync Input Output Reserved D29 DSTBP1 Y17 Source Sync Input Output Reserved E2 DSTBP2 Y14 Source Sync Input Output Reserved Y27 DSTBP3 Y11 Source Sync Input Output Reserved Y28 FERR PBE E27 Async GTL Output Reserved Y29 FORCEPR A15 Async GTL Input Reserved AA5 GTLREF_ADD_E F9 Power Other Input Reserved AA28 n gt Reserved AB4 e RER ABD MI F23 Power Other Input Reserved SES GTLREF_DATA_E Wa Power Other Input Reserved AD4 NP Reserved AD6 ao DATA_M W23 Power Other Input Reserved AD16 HIT E22 Common Clk Input Output Reserved AD28 HITM A23 Common Clk Input Output Reserved AD30 IERR E5 AsyncGTL Output Reserved AD31 IGNNE C26 AsyncGTL Input Reserved AES INIT D6 AsyncGTL Input Reseed PESO LINTO B24 Async GTL Imput RESET Y8 Common Clk Input ONT G23 AsyncGTL Input RS0 E21 p Common Cik Input LL IDO B31 Power Other Output RS1 Doe Common Elk Input LL_ID1 B28 Power Other Output RS2 Common Cik Input LOCK A17 Common Clk Input Output RSP c6 Conon Gk input MCERR D7 Common Clk Input Output SKTOCC A3 Power Other Output PECI C28 Power Other Input Output AMECA AC28 SMBus Input PROC_ID0 A30 Power Other Output SM DAT AC29 SMBus Input Output PROC_ID1 B29 Power Other Output SM EP_A0 AA29 SMBus Input PROCHOT B25 AsyncGTL Output SM REAL poe SMBus Input PWRGOOD AB7 AsyncGTL Input SMER AZ odii Sus Input REQ0 B19 Source Sync Input Output SM_VCC AE28
195. ve no effect Offset 3Fh 4Ch Bit Description 111 0 RESERVED 6 7 4 3 6 3 Processor Serial Electronic Signature This location contains a 64 bit identification number The value in this field is either a serial signature or an electronic signature Bits 5 amp 6 of the Processor Feature Flags Offset 78h indicates which signature is present Intel does not guarantee that each processor will have a unique value in this field Writes to this register have no effect Offset 4Dh 54h Bit Description 63 0 Processor Serial Electronic Signature 00000000h FFFFFFFFh Electronic Signature Document Number 318080 002 133 intel 7 4 3 6 4 RES7 Reserved 7 This location is reserved Writes to this register have no effect Offset 55h 6Eh Bit Description 207 0 RESERVED 7 7 4 3 6 5 PNDCKS Part Number Data Checksum This location provides the checksum of the Part Number Data Section Writes to this register have no effect Offset 6F Bit Description 7 0 Part Number Data Checksum One Byte Checksum of the Part Number Section 00h FFh See Section 7 4 4 for calculation of the value 7 4 3 7 Thermal Reference Data This section is reserved for future use 7 4 3 7 1 RES8 Reserved 8 This location is reserved Writes to this register have no effect Offset 70h Bit Description 7 0 RESERVED 8
196. vents that are lt 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope AGTL FSB Specifications Routing topologies are dependent on the processors supported and the chipset used in the design Please refer to the appropriate platform design guidelines for specific implementation details In most cases termination resistors are not required as these are integrated into the processor silicon See Table 2 6 for details on which signals do not include on die termination Please refer to Table 2 17 for Ry values Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END GTLREF_DATA_MID and GTLREF_DATA_END are the reference voltage for the FSB 4X data signals GTLREF ADD MID and GTLREF ADD END are the reference voltage for the FSB 2X address signals and common clock signals Table 2 17 lists the GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END specifications The AGTL reference voltages GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END must be generated on the baseboard using high precision voltage divider circuits Refer to the appropriate platform design guidelines for implementation details Document Number 318080 002 Electrical Specifications Table 2 17 AGTL Bus Voltage Definitions

IBM Intel Xeon X7350

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