Transcend JetRam 256MB SDRAM 168pin DIMM
Contents
1. Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the paremeter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend Information Inc 8 JM333S643A 75 256MB 168 PIN PC133 CL3 SDRAM DIMM With 16Mx8 3 3VOLT SIMPLIFIED TRUTH TABLE Register Mode Register Set L L L L OP CODE 1 2 Auto Refresh uto Refres L L L 4 X 3 Refresh Self Entry 3 Refresh L H H H X 3 Exit H X X X 3 Bank Active amp Row Addr L L H H Row Adress i Column Read amp Auto Precharge Disable L H L T L Mis li 4 Column Address Auto Precharge Enable H AoA 45 i i Column Write amp Auto Precharge Disable L H L L L rae i 4 Column Address Auto Precharge Enable H Burst Stop L H H L X 6 Bank Selecti Precharge L L H L X Both Banks H H X X X Clock Suspend or Active Power Entry L V V V X Down X X x x H X X X Precharge Power Entry L H H H X Down Mode H X X X Exit L V V V DOM X X 7 No Operation Command H X X X X L H H Transcend Information Inc V Valid X Don t Care H Logic Hi h L Logic Low 256MB 168 PIN PC133 CL3 JM333S643A 75 SDRAM DIMM2. With 16Mx8 3 3VOLT Serial Presence Detect Specification Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 12 0C 4 of Column Addresses on this Assembly 10 0A 5 of Module Rows on this Assembly 2 rows 02 6 Data Width of this Assembly 64bits 40 Data Width of this Assembly 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time CAS latency of 3 7 5ns 75 10 SDRAM Access Time from Clock CAS latency of 5 4ns 54 11 DIMM configuration type non parity ECC None 00 12 Rate Type 15 625us Self Refresh 80 13 Primary SDRAM Width X8 08 14 _ Error Checking SDRAM Width None 00 15 Min Clock Delay for Back to Back Random Address tCCD 1CLK 01 16 SDRAM Device Attributes Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 SDRAM Device Attributes of banks on SDRAM device 4 bank 04 18 SDRAM Device Attributes CAS Latency 3 04 19 SDRAM Device Attributes CS Latency 0 clock 01 20 SDRAM Device Attributes Write Latency 0 clock 01 Non buffered non registered 21 SDRAM Module Attributes amp redundant addressing 00 10 vo
3. 044 142 0051 17 0013 59 Vcc 101 DQ45 143 Vcc 18 Vcc 60 DQ20 102 Vcc 144 DQ52 19 DQ14 61 NC 103 09046 145 NC 20 0015 62 104 0047 146 21 63 CKE1 105 NC 147 NC 22 NC 64 Vss 106 NC 148 Vss 23 Vss 65 0021 107 Vss 149 0053 24 66 0022 108 150 0054 25 67 0023 109 NC 151 DQ55 26 Vcc 68 Vss 110 Vcc 152 Vss 27 AVE 69 DQ24 111 CAS 153 DQ56 28 DQMO 70 DQ25 112 DQM4 154 0057 29 DQM1 71 DQ26 113 DQM5 155 0058 30 CSO 72 DQ27 114 CSi 156 DQ59 31 NC 73 Vcc 115 RAS 157 Vcc 32 Vss 74 DQ28 116 Vss 158 DQ60 33 AO 75 DQ29 117 A1 159 0961 34 A2 76 DQ30 118 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 Vss 120 A7 162 Vss 37 A8 79 CLK2 121 A9 163 SCLK3 38 A10 80 NC 122 BAO 164 NC 39 BA1 81 NC 123 A11 165 SAO 40 Vcc 82 SDA 124 Vcc 166 SA1 41 Vcc 83 SCL 125 SCLK1 167 SA2 42 CLKO 84 126 NC 168 Vcc Transcend Information Inc 3 256MB 168 PIN PC133 CL3 JM333S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT JM333S643A 75 Block Diagram A0 A11 A0 A11 A0 A11 A0 A11 BAO BA1 BAO BA1 BAO BA1 BAO BA1 SS BE RAS Er IRAS isms IRAS IRAS iis CAS CAS SDRAM CAS CAS SDRAM IWE I WE IWE ri CSO ERE E CS 725 CS2 E LLLI EBENEN 2 p Pes ia en Hr AS TRES SDRAM a CS1 SEMEN CS CS3 WE CS CKE CLK1 CLK3 Serial EEPROM SCL SCL SDA SDA AO Ai A2 SAO SA1 S 2 This technical information is based on industry standard data an
4. 3 3VOLT Pin Identification Symbol Function A0 A11 BAO BA1 Address input Dimensions Side Millimeters Inches A 133 35 0 40 __5 250 0 016 B 65 67 2 585 23 49 0 925 D 8 89 0 350 E 3 00 0 118 F 29 21 0 20 1 150 0 008 G 19 80 0 788 H 15 80 0 622 1 27 0 10 0 050 0 004 Refer Placement Transcend Information Inc DQ0 DQ63 Data Input Output CLKO CLK3 Clock Input CKEO CKE1 Clock Enable Input CS0 CS3 Chip Select Input RAS Row Address Strobe CAS Column Address Strobe ANE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection Refer Block Diagram AND Pinouts 256MB 168 PIN PC133 CL3 JM333S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 Vss 43 Vss 85 Vss 127 Vss 02 DQO 44 NC 86 DQ32 128 03 001 45 CS2 87 DQ33 129 CS3 04 DQ2 46 DQM2 88 DQ34 130 DQM6 05 DQ3 47 DQM3 89 DQ35 131 DQM7 06 Vcc 48 NC 90 Vcc 132 NC 07 DQ4 49 Vcc 91 DQ36 133 Vcc 08 DQ5 50 NC 92 DQ37 134 NC 09 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 NC 94 DQ39 136 NC 11 DQ8 53 NC 95 DQ40 137 NC 12 Vss 54 Vss 96 Vss 138 Vss 13 DQ9 55 DQ16 97 DQ41 139 0048 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 0
5. JM333S643A 75 256MB 168 PIN PC133 CL3 SDRAM DIMM With 16Mx8 3 3VOLT Description The JM333S643A 75 is a 32M bit x 64 Synchronous Dynamic RAM high density for PC 133 The JM333S643A 75 consists of 16pcs CMOS 16Mx8 bits Synchronous DRAMs in TSOP II 400mil packages a 2048 bits serial EEPROM on a 168 pin printed circuit board The JM333S643A 75 is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allows the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 133 e Conformed to JEDEC Standard 4 clocks Burst Mode Operation e Auto and Self Refresh CKE Power Down Mode DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of system clock Transcend Information Inc Placement gt 09 7303 JM333S643A 75 256MB 168 PIN PC133 CL3 SDRAM DIMM With 16Mx8
6. ctive Standby Current Icc3N CKESViH min 52 tcc 10s 480 Input singals are changed one time during 20ns in non power down mode T k Acti One Bans eave IccaNS CKE ViH min CLK lt ViL max tec Input singals are stable 400 loL 0 mA ICcc4 pun Suid 1200 1 2CLKs Refresh Current 5 tRC2tRC min 2320 mA 2 Self Refresh Current Icce CKE lt 0 2V 32 mA Note 1 Measured with outputs open 2 Refresh period is 64ms 3 Unless otherwise noted input swing level is CMOS VIH VIL VDDQ VssaqQ Transcend Information Inc 6 256MB 168 PIN PC133 CL3 JM333S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT AC OPERATING TEST CONDITIONS 3 3V 0 3V 0 to 70 C Parameter Value Unit AC Input levels Vih Vil 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf21 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 ei on 1200 Ohm 50 Ohm Vou DC 2 4V 2 Output 2 4 70 50 e Vou DC 0 4V l 2mA 5 B0pF 870 Ohm Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER 4C operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15
7. d tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 256MB 168 PIN PC133 CL3 JM333S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply relative to Vss VDD VDDQ 1 0 4 6 V Storage temperature TsTG 55 150 Power dissipation PD 16 W Short circuit current los 50 mA Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 Input high voltage VIH 2 0 3 0 VDDQ 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 24 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current 10 10 uA 3 Note 1 max 5 6V AC The oversh
8. ltage tolerance 22 SDRAM Device Attributes General Burst Read Single bit Write OE precharge all auto precharge 23 SDRAM Cycle Time CAS Latency of 2 s 00 24 SDRAM Access Time from Clock GCAS Latency of 2 00 25 SDRAM Cycle Time CAS Latency of 1 00 26 SDRAM Access Time from Clock CAS Latency of 1 00 27 Minimum Row Precharge Time t RP 20ns 14 28 Minimum Row Active to Row Activate RRD 15ns OF 29 Minimum RAS to CAS Delay t RCD 20ns 14 30 Minimum Activate Precharge Time t RAS 45ns 2D 31 Module Row Density 2 rows of 128MB 20 32 Command and Address Signal input Setup Time 1 5ns 15 33 Command and Address Signal input Hold Time 0 8ns 08 34 Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Information 00 62 SPD Data Revision Code JEDEC2 02 63 for Bytes 0 62 9E 64 71 Manufacturers ID Dode per JEP 108E Transcend 72 Manufacturing Location 00 73 90 Manufacturers Part Number 00 91 92 Revision Code 00 93 94 Manufacturing Date 00 95 98 Assembly Serial Number 00 99 125 Manufacturer Specific Data 00 Transcend Information Inc 10 256MB 168 PIN PC133 CL3 JM333S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT 126 Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 3 Clock 0 3 F4 128 Unused Storage Locations Open FF Transce
9. nd Information Inc 11
10. ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time ns 1 tRAS max 100 us Row cycle time tRC min 65 ns 1 Last data in to row precharge tRDL min 2 CLK 2 Last data in to Active precharge tDAL min 2 CLK tRP Last data in to new col address delay tCDL min 1 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay 1 CLK 3 Number of valid output data CAS latency 3 2 dd 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 n case of row precharge interrupt auto precharge and read burst stop Transcend Information Inc 7 256MB 168 PIN PC133 CL3 JM333S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Min Max Unit Note CLK cycle time tcc 7 5 1000 ns ns CLK to valid output delay tSAC 5 4 ns 1 2 Output data hold time tOH 3 0 ns 2 CLK high pulse width tCH 2 5 ns 3 CLK low pulse width tCL 2 5 ns 3 Input setup time tss 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output in Hi Z tSHZ 5 4 ns
11. oot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs CAPACITANCE Voo 3 3V Ta 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Address Ao A11 BAo BA1 CADD 45 85 pF RAS CAS WE CIN 45 85 pF CKE CKEO CKE1 CCKE 25 45 pF Clock CLKO CLK3 CCLK 15 21 pF CS CSO CS3 CC5 15 25 pF DQM DQM7 10 15 pF DQ 000 0063 COUT 13 18 pF Transcend Information Inc 5 256MB 168 PIN PC133 CL3 JM333S643A 75 SDRAM DIMM With 16Mx8 3 3VOLT DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Value Unit Note Operating Current Burst Length 1 nr n 1 One Bank Active VAC RCT lo 0mA Precharge Standby Current CC2P CKEsVIL max tcc 10ns 32 mA in power down mode 2 amp CLK lt ViL max 1 32 CKE ViH min CS2ViH min tcc 10ns Icc2N Input singals are changed one time during 20ns 320 Precharge Standby Current mA in non power down mode p IccoNS min CLKxViL max tcc 160 nput singals are stable Active Standby Current Icc3P lt tcc 10ns 80 mA in power down mode IccaPS CKE amp CLK lt ViL max tcc 80 A
Download Pdf Manuals
Related Search