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Intel Xeon 2.80 GHz

1. Table4 Voltage Identification Definition Sheet 1 of 2 VID5 VID4 VID2 VID1 VIDO Vec max VID5 VIDA VID3 VID2 VID1 VIDO max 0 0 1 0 1 0 0 8375 0 1 1 0 1 0 1 2125 1 0 1 0 0 1 0 8500 1 1 1 0 0 1 1 2250 0 0 1 0 0 1 0 8625 0 1 1 0 0 1 1 2375 1 0 1 0 0 0 0 8750 1 1 1 0 0 0 1 2500 0 0 1 0 0 0 0 8875 0 1 1 0 0 0 1 2625 1 0 0 1 1 1 0 9000 1 1 0 1 1 1 1 2750 0 0 0 1 1 1 0 9125 0 1 0 1 1 1 1 2875 1 0 0 1 1 0 0 9250 1 1 0 1 1 0 1 3000 0 0 0 1 1 0 0 9375 0 1 0 1 1 0 1 3125 1 0 0 1 0 1 0 9500 1 1 0 1 0 1 1 3250 0 0 0 1 0 1 0 9625 0 1 0 1 0 1 1 3375 1 0 0 1 0 0 0 9750 1 1 0 1 0 0 1 3500 0 0 0 1 0 0 0 9875 0 1 0 1 0 0 1 3625 1 0 0 0 1 1 1 0000 1 1 0 0 1 1 1 3750 16 Datasheet intel Intel Xeon Processor with 800 MHz System Bus Table4 Voltage Identification Definition Sheet 2 of 2 VID5 VIDA VID3 VID2 VID1 VIDO Vcc VID5 VIDA VID3 VID2 VID1 VIDO Vcc 0 0 0 0 1 1 1 0125 0 1 0 0 1 1 1 3875 1 0 0 0 1 0 1 0250 1 1 0 0 1 0 1 4000 0 0 0 0 1 0 1 0375 0 1 0 0 1 0 1 4125 1 0 0 0 0 1 1 0500 1 1 0 0 0 1 1 4250 0 0 0 0 0 1 1 0625 0 1 0 0 0 1 1 4375 1 0 0 0 0 0 1 0750 1 1 0 0 0 0 1 4500 0 0 0 0 0 0 1 0875 0 1 0 0 0 0 1 4625 1 1 1 1 1 1 OFF 1 0 1 1 1 1 1 4750 0 1 1 1 1 1 OFF 0 0 1 1 1 1 1 4875 1 1 1 1 1 0 1 1000 1 0 1 1 1 0 1 5000 0 1 1
2. Pin Name E Direction Pin Name ed Direction VCCPLL AD1 Power Other Input VSS E31 Power Other VCCSENSE B27 Power Other Output VSS F2 Power Other VIDO F3 Power Other Output VSS F7 Power Other VID1 E3 Power Other Output VSS F13 Power Other VID2 D3 Power Other Output VSS F19 Power Other VID3 C3 Power Other Output VSS F25 Power Other VID4 B3 Power Other Output VSS F28 Power Other VID5 A1 Power Other Output VSS F30 Power Other VIDPWRGD B1 Power Other Input VSS G1 Power Other VSS A5 Power Other VSS G3 Power Other VSS A11 Power Other VSS G5 Power Other VSS A21 Power Other VSS G9 Power Other VSS A27 Power Other VSS G25 Power Other VSS A29 Power Other VSS G27 Power Other VSS A31 Power Other VSS G29 Power Other VSS B2 Power Other VSS G31 Power Other VSS B9 Power Other VSS H2 Power Other VSS B15 Power Other VSS H4 Power Other VSS B17 Power Other VSS H6 Power Other VSS B23 Power Other VSS H8 Power Other VSS B28 Power Other VSS H24 Power Other VSS B30 Power Other VSS H26 Power Other VSS C7 Power Other VSS H28 Power Other VSS C13 Power Other VSS H30 Power Other VSS C19 Power Other VSS J1 Power Other VSS C25 Power Other VSS J3 Power Other VSS C29 Power Other VSS J5 Power Other VSS C31 Power Other VSS J7 Power Other VSS D2 Power Other VSS J9 Power Other VSS D5 Power Other VSS J23 Power Other VSS D11 Power Other VSS J25 Power Other VSS D21 Power Other VSS J27 Power Other VSS D27
3. 5 1 1 Pin Listing by Pin Name Table 21 Pin Listing by Pin Name Sheet 1 of 8 Pin Name E Direction Pin Name M E Direction 22 Source Sync I O AP1 D9 Common Clk 4 20 Source Sync BCLKO Y4 Sys Bus Input A5 B18 Source Sync BCLK1 W5 Sys Bus Input A6 C18 Source Sync I O BINIT F11 Common A7 A19 Source Sync BNR F20 Common Clk I O A8 C17 Source Sync I O BOOT_SELECT G7 Power Other Input AQ D17 Source Sync I O F6 Common Clk I O A10 A13 Source Sync 1 F8 Common Clk A115 B16 Source Sync 2 E7 Common Clk I O A12 B14 Source Sync I O BPM3 F5 Common Clk I O A13 B13 Source Sync I O BPM4 E8 Common Clk I O 14 12 Source Sync 5 4 Common Clk A15 C15 Source Sync I O BPRI D23 Common Clk Input A16 C14 Source Sync I O BRO D20 Common Clk I O A17 D16 Source Sync I O 1 F12 Common CIk Input 18 015 Source Sync I O 2 E11 Common CIk Input A19 F15 Source Sync BR3 1 D10 Common CIk Input 20 A10 Source Sync BSELO Power Other Output A211 B10 Source Sync BSEL1 Power Other Output 22 B11 Source Sync COMPO AD16 Power Other Input 23 C12 Source Sync 16 Power Other Input A241 E14 Source Sync 00 26 Source Sync I O 25 013 Source Sync I O
4. VID 0 050 Vos gt S o gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Overshoot above VID NOTES 1 Vog is measured overshoot voltage 2 Tog is measured time duration above VID Die Voltage Validation Overshoot events from application testing on processor must meet the specifications in Table 11 when measured across the VCCSENSE and VSSSENSE pins Overshoot events that are 10 ns in duration may be ignored These measurement of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope BSEL 1 0 and VID 5 0 Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes BSEL 1 0 and VID 5 0 N A 60 2 Buffer On Resistance lot Maximum Pin Current N A 8 mA 2 lio Output Leakage Current N A 200 2 3 RPuLL uP Pull Up Resistor 500 VroL Voltage Tolerance 0 95 VIT 1 05 Vr V NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 These parameters are based on design characterization and are not tested 3 Leakage to 5 with pin held at Vrr Datasheet In Table 13 Table 14 Datasheet Intel Xeon Processor with 800 MHz System Bus AGTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Input Low Voltage 0 0 GTLREF 0 10 Vr V 2
5. 09900 7920 04 4 59700 eva germ 5 02 WS AR ASIN SED 00 209071 9992000 z 71071 101071 4 goed 820 E 10507 z 2 192071 E 121 5970 2ISV8 1271 Ir zy B 100971 26071 2101071 9927097 24 GVO 61071 907700 0911 61071 2ISVB 50761 H Y E 100211 t WW 15700 21190071 02 0 JLVYLSENS 39v 2Yd 215 8 1796 E 00 80 0 1NVIV3S SHI 2 411 SHI 191217 gt v reeo 1 1 OE 2 11258071119 ME MILA 14051 1919711 1119711 z gt 5 Srey a 19711 1119711 Sv er XVW NIW SLNAWNOD S3H2NI1 108 15 WOLLO MALA 301 401 2 1 Datasheet 32 Intel Xeon Processor with 800 MHz System Bus Processor Package Drawing Sheet 2 of 2 Figure 8 Y 30 2 133HS Leta Twos T 97025 2 Aga M3HAQN ONIMYNC 3002 39Y2 3721 LNIWLYYdId MILA WOLLOG MILA 3015 MIIA 401 E 650 1 90 5 1H513H LN3NOdNO2 Cone 6271 z 3 8VNOT1Y 571 91 S62 006 210 D i 2 0091 Q3H21VH 5042 90 1104339 1 1921 XZ 168071 _
6. sse eene 35 3 5 Package Insertion 35 3 6 Processor Mass Specifications sse nennen nennen nnns 35 3 7 Processor Materials eie tisse d de iac a ue pa v eua ace Dae ca 35 3 8 Processor MArkinGS 36 3 9 Processor Pinout 37 Signal DefinitlOris 39 4 1 Signal 39 LISE oon csi eI 49 5 1 Intel Xeon Processor with 800 MHz System Bus Pin Assignments 49 5 1 1 Pin Listing by Pin 50 5 1 2 Pin Listing by Pin peccet det 58 Datasheet 3 Intel Xeon Processor with 800 MHz System Bus ntel 6 0 7 0 8 0 9 0 Thermal Specifications ee ede 67 6 1 Package Thermal Specifications 67 6 1 1 Thermal Specifications 67 6 1 2 Thermal 71 6 2 Processor Thermal Features 71 6 2 1 Thermal 71 6 2 2 On Demand Mode nennen nennen nnn nnne enne 72 6 2 3 PROCHOT Signal 72 6 2
7. a 05271 e gt sE 9021 1 E 100073 16907 n 1912 9 19171 8 E 60 amp 140511 E E ast 9661 216 918 21 D Seri teele rg rad Iu 0098 tosy c1 09 19 5 oly 8 S e E E 5 amp _ e 5 5 508 E 3 3 w G00 900 lt Datasheet 83 Intel Xeon Processor with 800 MHz System Bus n Figure 22 Bottom Side Board Keepout Zones 5 5 2 E 3 g5 5 10061 82 18 100921 199 E a gt 75 5 2 ef 38 g a ae F1 2 sS 38 5 m T E 100971 a mo 9 yu E ok e 2 aS 1000 1 9 105271 w SS 5 95 3 MESS SS oly B 5 5 zc 85 m m Ooo Ed zz 2 2 5 2 pee COR atm E 2 m 2 aO Um x S 3 5 ER zz E zc 5 55 8 22 5 gt E S zz e 2 e zz E eu lt 38 ba S XE ss 22 5 SO 84 Datasheet ntel Intel Xeon Processor with 800 MHz System Bus D Figure 23 Board Mounting Hole Keepout Zones O
8. is a wired OR signal which must connect the appropriate pins of all processor front side bus agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers BINIT is activated on specific clock edges and sampled on specific clock edges Vo BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wired OR signal which must connect the appropriate pins of all processor front side bus agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers is activated on specific clock edges and sampled on specific clock edges BOOT_ SELECT The BOOT_SELECT input informs the processor whether the platform supports the Intel Xeon processor with 800 MHz system bus The processor will not operate if this signal is low This input has a weak pull up to Vr 0 Vo 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins of all front side bus agents BPM4 provi
9. heatsink 91 33 Fan Cable Connector Supplier and Part 0 2 91 Datasheet ntel Intel Xeon Processor with 800 MHz System Bus Revision History Date Revision Description June 2004 001 Initial release Datasheet 7 Intel Xeon Processor with 800 MHz System Bus ntel 8 8 Datasheet Intel Xeon Processor with 800 MHz System Bus Introduction Datasheet The Intel Xeon processor with 800 MHz system bus is a 32 bit server workstation processor based on improvements to the Intel NetBurst microarchitecture It maintains the tradition of compatibility with LA 32 software and includes features found in the Intel Xeon processor such as Hyper Pipelined Technology a Rapid Execution Engine and an Execution Trace Cache Hyper Pipelined Technology includes a multi stage pipeline allowing the processor to reach much higher core frequencies The 800 MHz system bus is a quad pumped bus running off a 200 MHz system clock making 6 4 GB per second data transfer rates possible The Execution Trace Cache is a level 1 cache that stores decoded micro operations which removes the decoder from the main execution path thereby increasing performance In addition enhanced thermal and power management capabilities are implemented including Thermal Monitor and Demand Based Switching DBS wi
10. 27 Source Sync I O 26 A9 Source Sync 02 24 Source Sync 27 B8 Source Sync D3 AA25 Source Sync I O A28 E13 Source Sync I O D4 AD27 Source Sync I O 29 012 Source Sync 05 23 Source Sync I O 11 Source Sync 06 24 Source Sync I O 1 7 Source Sync 07 AB26 Source Sync I O 2 A6 Source Sync 08 AB25 Source Sync I O A7 Source Sync 09 AB23 Source Sync I O A34 C9 Source Sync 010 22 Source Sync I O A35 C8 Source Sync I O D11 21 Source Sync I O A20M F27 Async GTL Input D12 AB20 Source Sync I O ADS D19 Common Clk I O D13 AB22 Source Sync I O ADSTBO F17 Source Sync D144 AB19 Source Sync I O ADSTB1 F14 Source Sync 015 19 Source Sync I O E10 Common Clk D16 AE26 Source Sync I O 50 Datasheet ntel Intel Xeon Processor with 800 MHz System Bus D Table 21 Pin Listing by Pin Name Sheet 2 of 8 Pin Name E d EM Direction 017 26 Source Sync 057 AD7 Source Sync I O D18 AD25 Source Sync I O D58 AE7 Source Sync I O D19 AE25 Source Sync I O D59 AC6 Source Sync I O D20 24 Source Sync I O D60 AC5 Source Sync D21
11. 105 100 0 01 0 1 1 10 100 1000 Time Duration s NOTES 1 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than lcc m 2 Not 100 tested Specified by design characterization Datasheet 25 Intel Xeon Processor with 800 MHz System Bus Table 10 26 Static and Transient Tolerance lcc 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 Voltage Deviation from VID Setting V VID 0 000 VID 0 006 VID 0 013 VID 0 019 VID 0 025 VID 0 031 VID 0 038 VID 0 044 VID 0 050 VID 0 056 VID 0 063 VID 0 069 VID 0 075 VID 0 081 VID 0 087 VID 0 094 VID 0 100 VID 0 106 VID 0 113 VID 0 119 VID 0 125 VID 0 131 VID 0 138 VID 0 144 VID 0 150 VID 0 020 VID 0 026 VID 0 033 VID 0 039 VID 0 045 VID 0 051 VID 0 058 VID 0 064 VID 0 070 VID 0 076 VID 0 083 VID 0 089 VID 0 095 VID 0 101 VID 0 108 VID 0 114 VID 0 120 VID 0 126 VID 0 133 VID 0 139 VID 0 145 VID 0 151 VID 0 158 VID 0 164 VID 0 170 1 2 3 Vcc win VID 0 040 VID 0 046 VID 0 052 VID 0 059 VID 0 065 VID 0 071 VID 0 077 VID 0 084 VID 0 090 VID 0 096 VID 0 103 VID 0 109 VID 0 115 VID 0 121 VID 0 128 VID 0 134 VID 0 140 VI
12. 88 27 Fan Cable Connector Pinout 3 pin active heatsink 90 28 Fan Cable Connector Pinout 4 pin active 91 Datasheet 5 Intel Xeon Processor with 800 MHz System Bus ntel Tables 1 Features of the Intel Xeon Processor with 800 MHz System BUS 10 2 Core Frequency to Front Side Bus Multiplier 22022 00 14 3 BSEL 1 0 Frequency 14 4 Voltage Identification Definition 23 16 5 Front Side Bus Signal 19 6 Signal Description Table 20 7 Signal Reference 20 8 Absolute Maximum and Minimum 22 9 Voltage and Current Specifications sss enne nnne nennen 23 10 Static and Transient 26 11 Overshoot 27 12 BSEL 1 0 VID 5 0 Signal Group DC 5 28 13 AGTL Signal Group DC Specifications 29 14 PWRGOOD Input TAP Signal Group DC 29 15 Asynchronous and AGTL Asynchronous Signal Group DC Specificati
13. saturation current 4 electronic charge VD voltage across the diode Boltzmann Constant and T absolute temperature Kelvin The series resistance is provided to allow for a more accurate measurement of the junction temperature as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and external remote diode thermal sensor can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term Another application that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation Terror N 1 lew min nk q Where Terror sensor temperature error sensor current ratio Boltzmann Constant q electronic charge Thermal Diode Interface Pin Name Pin Number Pin Description THERMDA Y27 diode anode THERMDC Y28 diode cathode Datasheet 7 0 Intel Xeon Processor with 800 MHz System Bus Features 7 1 Table 28 7 2 Datasheet Power On Configuration Options Several configuration options can be configured by hardware The Intel Xeon processor with 800 MHz system bus samples its hardware configuration at reset on the active to inactive transition of RESET For specifics on these options please refer to Table
14. Agent 1 Pins BREQO BRO BR1 BREQ1 BR1 BRO BR2 and BR3 must not be used in 2 way platform designs However they must still be terminated During power on configuration the central agent must assert the BRO bus signal All symmetric agents sample their BR 3 0 pins on the active to inactive transition of RESET The pin which the agent samples asserted determines it s agent ID These signals do not have on die termination and must be terminated at the end agent BSEL 1 0 The BCLK 1 0 frequency select signals BSEL 1 0 are used to select the processor input clock frequency Table 3 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processors chipset and clock synthesizer front side bus agents must operate at the same frequency The Intel Xeon processor with 800 MHz system bus currently operates at 800 MHz system bus frequency 200 MHz BCLK 1 0 frequency COMPT 1 0 COMP 1 0 must be terminated to 5 on the baseboard using precision resistors These inputs configure the GTL drivers of the processor 0 63 0 D 63 0 Data are the data signals These signals provide 64 bit data path between 4 the processor front side bus agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 ar
15. If bit 4 of the IA 32 MODULATION MSR is written to a the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the IA 32 CLOCK MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 12 5 off in 12 596 increments On Demand mode may be used in conjunction with the Thermal Monitor If the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT Signal Pin An external signal PROCHOT processor hot is asserted when the processor die temperature has reached its factory configured trip point If Thermal Monitor is enabled note that Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the Intel Architecture Software Developer s Manual s for specific register and programming details is designed to assert at a few degrees higher than maximum as specified by Thermal Profile A when dissipating TDP power and can
16. Input AC16 VCC Power Other AB8 VCC Power Other 17 034 Source Sync I O AB9 DBI3 Source Sync I O AC18 DPO Common Clk I O AB10 D55 Source Sync I O AC19 VSS Power Other AB11 VSS Power Other AC20 D25 Source Sync I O AB12 D51 Source Sync I O AC21 D26 Source Sync I O AB13 D52 Source Sync I O AC22 VCC Power Other AB14 VCC Power Other AC23 D23 Source Sync I O AB15 D37 Source Sync 24 D20 Source Sync AB16 D32 Source Sync I O AC25 VSS Power Other AB17 D31 Source Sync I O AC26 D17 Source Sync I O AB18 VCC Power Other AC27 DBIO Source Sync I O AB19 D14 Source Sync I O AC28 N C N C N C AB20 D12 Source Sync I O AC29 N C N C N C AB21 VSS Power Other AC30 SLEW_CTRL Power Other Input AB22 D13 Source Sync I O AC31 VCC Power Other AB23 09 Source Sync AD1 VCCPLL Power Other Input AB24 VCC Power Other AD2 Power Other AB25 D8 Source Sync I O AD3 VSS Power Other AB26 D7 Source Sync I O AD4 VCCIOPLL Power Other Input AB27 VSS Power Other AD5 TESTHI5 Power Other Input AB28 N C N C N C AD6 VCC Power Other AB29 N C N C N C AD7 D57 Source Sync I O AB30 VCC Power Other AD8 Source Sync 1 VSS Power Other AD9 VSS Power Other AC1 Reserved Reserved Reserved AD10 D45 Source Sync I O AC2 VSS Power Other AD11 D40 Source Sync VCC Power Other AD12 VTT P
17. 1 All characters will be in upper case 2 Drawing is not to scale 36 Datasheet 3 9 Figure 11 Datasheet Intel Xeon Processor with 800 MHz System Bus Processor Pinout Coordinates Figure 11 and Figure 12 show the top and bottom view of the processor pin coordinates respectively The coordinates are referred to throughout the document to identify processor pins Processor Pinout Coordinates Top View Vcc Vss COMMON CLOCK O nje 0 e 0 e o e 4 CLOCKS ADDRESS COMMON CLOCK 7 9 11 13 15 17 19 21 23 25 Qoeo e on oo Q eo e oe Intel amp Processor 800 MHz Top View Oeooeosjeeceeoceooceocccoe eooeoo 0e0o0000 0080800 0100 0 0 JTAG 27 29 31 eooeoo 000000 0000 0 26 28 OO eo OO eooe oe oeoo eo OO oe 6 8 10 12 14 16 18 20 22 24 DATA O Signal GTLREF Power Reserved No Connect Ground 1 30 z cdmuzzraAc cromnmoour SSA 99A 37 COMMON CLOCK COMMON CLOCK ADDRESS 23 21 19 17 15 13 11 25 JTAG 29 27 31 Processor Pinout Coordinates Bottom View 85 lt
18. 1H913H JTGVMOTIV 1272 X 0 33 Datasheet Intel Xeon Processor with 800 MHz System Bus n 3 2 3 3 Table 17 34 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements thermal and mechanical solution design must not intrude into the required keepout zones Decoupling capacitors are typically mounted to either the topside or pin side of the package substrate See Figure 8 for keepout zones Package Loading Specifications Table 17 provides dynamic and static load specifications for the processor package These mechanical load limits should not be exceeded during heatsink assembly mechanical stress testing or standard drop and shipping conditions The heatsink attach solutions must not include continuous stress onto the processor with the exception of a uniform load to maintain the heatsink to processor thermal interface Also any mechanical system or component testing should not exceed these limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal or mechanical solutions Processor Loading Specifications Parameter Min Max Unit Notes Static 44 222 N 1 2 3 4 Compressive Load 10 50 44 288 1 2 3 5 10 65 lbf Dynamic NA 222 0 45 kg 100 G 1 3 4 6 7 Compressive Load NA 50 Ibf static 1 Ibm 100 G Ib
19. 1U Passive CEK Heatsink 1U form factor In the 1U configuration it is assumed that a chassis duct will be implemented to provide 15 CFM of airflow to pass through the heatsink fins The duct should be designed as precisely as possible and should not allow any air to bypass the heatsink 0 bypass and a back pressure of 0 38 in H5O It is assumed that a 40 C is met This requires a superior chassis design to limit the at or below 5 with an external ambient temperature of 35 Following these guidelines will allow the designer to meet thermal profile B and conform to the thermal requirements of the processor 2U Passive CEK Heatsink 2U and above form factor Once again a chassis duct is required for the 2U passive heatsink In this configuration Thermal Profile A see Section 6 0 should be followed by supplying 22 CFM of airflow through the fins of the heatsink with 0 or no duct bypass and a back pressure of 0 14 in H5O The temperature of 40 C should be met This may require the use of superior design techniques to keep at or below 5 based on an ambient external temperature of 35 20 Active Heatsink 20 and above pedestal This heatsink was designed to help pedestal chassis users to meet the thermal processor requirements without the use of chassis ducting It may be necessary to implement some form of chassis air guide or air duct to meet the Tj temperature of 40
20. As mentioned previously the PROCHOT signal is asserted when high temperature situation is detected A minimum pulse width of 500 us is recommend when the FORCEPRE is asserted by the system Sustained activation of the FORCEPR pin may cause noticeable platform performance degradation THERMTRIP Signal Pin Regardless of whether or not Thermal Monitor is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the definition in Table 20 At this point the system bus signal THERMTRIP will go active and stay active as described in Table 20 THERMTRIP activation is independent of processor activity and does not generate any bus cycles and Fan Speed Reduction Tcontrol is a temperature specification based on a temperature reading from the thermal diode The value for Tcontrol will be calibrated in manufacturing and configured for each processor The Tcontrol temperature for a given processor can be obtained by reading the IA 32 TEMPERATURE TARGET MSR in the processor The Tcontrol value that is read from the 32 TEMPERATURE TARGET MSR must be converted from Hexadecimal to Decimal and added to a base value The base value is 50 The value of Tcontrol may vary from 0x00h to Ox 1Eh Systems that support the Intel Xeon processor with 800 MHz system bus must implement BIOS changes to dete
21. Features of the Intel Xeon Processor with 800 MHz System Bus No of Supported L2 Advanced Symmetric Transfer RUNE Package Agents Cache Intel Xeon processor with 604 pin 800 MHz system bus pss TMB 800 MHz FC mPGA4 Intel Xeon processor with 800 MHz system bus based platforms implement independent power planes for each system bus agent As a result the processor core voltage and system bus termination voltage must connect to separate supplies The processor core voltage uses power delivery guidelines denoted by VRM 10 0 or VRM 10 1 and the associated load line see Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines or Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 1 Design Guidelines for further details The Intel Xeon processor with 800 MHz system bus uses a scalable system bus protocol referred to as the system bus in this document The system bus uses a split transaction deferred reply protocol The system bus uses Source Synchronous Transfer SST of address and data to improve performance The processor transfers data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or the 2X address bus In addition the Request Phase completes in one clock cycle
22. I O GTLREF W23 Power Other Input D46 AD8 Source Sync I O GTLREF W9 Power Other Input 047 AC9 Source Sync GTLREF F23 Power Other Input 048 AA13 Source Sync I O GTLREF F9 Power Other Input D49 14 Source Sync I O HIT E22 Common Clk I O D50 14 Source Sync I O HITM A23 Common Clk I O 051 12 Source Sync I O IERR E5 Async GTL Output D52 AB13 Source Sync I O IGNNE C26 Async GTL Input D53 AA11 Source Sync I O INIT D6 Async GTL Input 054 AA10 Source Sync LINTO INTR B24 Async GTL Input D55 AB10 Source Sync I O LINT1 NMI G23 Async GTL Input 056 AC8 Source Sync LOCK A17 Common Clk I O Datasheet 51 Intel Xeon Processor with 800 MHz System Bus Table 21 Pin Listing by Pin Name Sheet 3 of 8 1 Direction Pin Name ud HOME ua Direction MCERR D7 Common Clk I O TCK E24 TAP Input N C Y29 N C N C TDI C24 TAP Input N C AA28 N C N C TDO E25 TAP Output N C AA29 N C N C TEST BUS A16 Power Other I O N C AB28 N C N C TESTHIO W6 Power Other Input N C AB29 N C N C TESTHI1 W7 Power Other Input N C AC28 N C N C TESTHI2 w8 Power Other Input N C AC29 N C N C TESTHIS Y6 Power Other Input N C AD28 N C N C TESTHI4 AA7 Power Other
23. Input N C AD29 N C N C TESTHI5 AD5 Power Other Input N C AE30 N C N C TESTHI6 5 Power Other Input ODTEN B5 Power Other Input THERMDA Y27 Power Other Output OPTIMIZED COMPAT C1 Power Other Input THERMDC Y28 Power Other Output 25 GTL Output THERMTRIP F26 Async GTL Output PWRGOOD AB7 Async GTL Input TMS A25 TAP Input REQO B19 Source Sync I O TRDY E19 Common Clk Input REQ1 B21 Source Sync I O TRST F24 TAP Input REQ2 C21 Source Sync I O VCC A2 Power Other REQ3 C20 Source Sync VCC A8 Power Other 4 B22 Source Sync VCC A14 Power Other Reserved A26 Reserved Reserved VCC A18 Power Other Reserved D25 Reserved Reserved VCC A24 Power Other Reserved W3 Reserved Reserved VCC A28 Power Other Reserved Y3 Reserved Reserved VCC A30 Power Other Reserved AC1 Reserved Reserved B6 Power Other Reserved AE15 Reserved Reserved VCC B20 Power Other Reserved AE16 Reserved Reserved VCC B26 Power Other Reserved AE28 Reserved Reserved VCC B29 Power Other Reserved AE29 Reserved Reserved VCC B31 Power Other RESET Y8 Common CIk Input VCC C2 Power Other 0 E21 Common CIk Input C4 Power Other 1 022 Common Input VCC C16 Power Other RS2 F21 Common Input VCC C22 Power Other RSP C6 Common CIk Input C28 Power Other SKTOCC Power Other Output VCC C30 Power Other SLP AE6 Async GTL Input 01 Power Other SLEW CTRL 0
24. Power Other VSSA 5 Power Other Input VSS AA23 Power Other VSSSENSE D26 Power Other Output VSS AA30 Power Other VTT A4 Power Other VSS AB1 Power Other VTT B4 Power Other VSS AB5 Power Other VTT C5 Power Other VSS AB11 Power Other VTT B12 Power Other VSS AB21 Power Other VTT C10 Power Other VSS AB27 Power Other VTT E12 Power Other VSS AB31 Power Other VTT F10 Power Other VSS AC2 Power Other VTT Y10 Power Other VSS AC7 Power Other VTT AA12 Power Other VSS AC13 Power Other VTT AC10 Power Other VSS AC19 Power Other VTT AD12 Power Other VSS AC25 Power Other VTTEN E1 Power Other Output NOTE In systems using the Intel Xeon processor with 800 MHz system bus the system designer must pull up these signals to the processor VT Datasheet 57 Intel Xeon Processor with 800 MHz System Bus 5 1 2 Pin Listing by Pin Number Table 22 Pin Listing by Pin Number Sheet 1 of 8 viel Pin Name ES Direction c Pin Name i Direction A1 VID5 Power Other Output B8 27 Source Sync 2 VCC Power Other B9 VSS Power Other A3 SKTOCC Power Other Output B10 21 Source Sync 4 VTT Power Other B11 22 Source Sync A5 VSS Power Other B12 VTT Power Other A6 2 Source Sync B13 A13 Source Sync I O A33 Sourc
25. 04402 131M 10 1839802 8211138 YOIYd FHL 1108118 03111008 BO 031 14910 032000434 019012010 38 LON S1N31N02 SLI ANV 398301180 039019510 SI 11 1Y11N301JN0 8011 804802 SNIYINOO 9NIMVAQ SIHI m Intel Xeon Processor with 800 MHz System Bus Figure 26 Datasheet 88 intel 8 2 2 8 2 2 1 8 2 3 8 3 8 3 1 Datasheet Intel Xeon Processor with 800 MHz System Bus Boxed Processor Heatsink Weight Thermal Solution Weight The 2U passive and 20 active heatsink solutions will not exceed a mass of 1050 grams Note that this is per processor so a dual processor system will have up to 2100 grams total mass in the heatsinks The 1U heatsink will not exceed a mass of 700 grams for a total of 1400 grams a dual processor system This large mass will require a minimum chassis stiffness to be met in order to withstand force during shock and vibration See Section 3 0 for details on the processor weight Boxed Processor Retention Mechanism and Heatsink Support CEK Baseboards and chassis designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor Refer to the Server System Infrastructure Specification SSI EEB 3 5 see http Wwww ssiforum org for details on the hole locations Figure 19 illustrates the new Common Enabling Kit CEK retention sol
26. Because this pin does not connect to the processor silicon any platform voltage and termination value is acceptable SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If is asserted during the deassertion of RESET the processor will tri state its outputs STPCLK STPCLK Stop Clock when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the front side bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input Datasheet 45 Intel Xeon Processor with 800 MHz System Bus Table 20 Signal Definitions Sheet 8 of 9 Description Notes TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI Test Data In transfers serial te
27. DBI3 DSTBP3 42 Datasheet intel Table 20 Intel Xeon Processor with 800 MHz System Bus Signal Definitions Sheet 5 of 9 Name Type Description Notes FERR PBE FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK t is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to Vol 3 of the A 32 Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note This signal does not have on die termination and must be terminated at the end agent FORCEPR The FORCEPR input can be used by the platform to force the Intel Xeon processor with 800 MHz system bus to activate the Thermal Control Circuit TCC
28. F6 Common Clk G28 VCC Power Other F7 VSS Power Other G29 VSS Power Other F8 BPM1 Common Clk I O G30 VCC Power Other F9 GTLREF Power Other Input G31 VSS Power Other F10 VTT Power Other H1 Power Other F11 BINIT Common Clk I O H2 VSS Power Other F12 1 Common Input H3 VCC Power Other F13 VSS Power Other H4 VSS Power Other F14 ADSTB1 Source Sync I O H5 VCC Power Other F15 A19 Source Sync H6 VSS Power Other F16 VCC Power Other H7 VCC Power Other F17 ADSTBO Source Sync H8 VSS Power Other F18 DBSY Common Clk H9 Power Other F19 VSS Power Other H23 Power Other F20 24 VSS Power Other F21 RS2 Common Clk Input H25 Power Other F22 VCC Power Other H26 VSS Power Other F23 GTLREF Power Other Input H27 Power Other F24 TRST TAP Input H28 VSS Power Other F25 VSS Power Other H29 Power Other F26 THERMTRIP Async GTL Output H30 VSS Power Other F27 A20M Async GTL Input H31 Power Other F28 VSS Power Other J1 VSS Power Other F29 VCC Power Other J2 VCC Power Other F30 VSS Power Other J3 VSS Power Other F31 VCC Power Other J4 VCC Power Other G1 VSS Power Other J5 VSS Power Other G2 VCC Power Other J6 VCC Power Other G3 VSS Power Other J7 VSS Power Other G4 VCC Power Other J8 VCC Power Other G5 VSS Power Other J9 VSS Power Other G6 VCC Power Other J23 VSS Power Other G7 BOOT SELECT Power Other Input J24 VCC P
29. Figure 19 shows exploded view of the boxed processor thermal solution for the Intel Xeon processor with 800 MHz system bus and the other CEK retention components 1U Passive CEK Heatsink 79 intel Figure 19 8 2 8 2 1 Datasheet Intel Xeon Processor with 800 MHz System Bus Passive Intel amp Xeon Processor with 800 MHz System Bus Thermal Solution 2U and larger 1 Heat sink screw dii springs 2 2 Heat sink Heat sink screws ga Heat sink standoffs 5 p p Thermal Interface Material processor ee Protective Tape pd ER ae CEK spring Chassis pan NOTES 1 The heatsink in this image is for reference only and may not represent any of the actual boxed processor heatsinks 2 The screws springs and standoffs will be captive to the heatsink This image shows all of the components in an exploded view 3 It is intended that the CEK spring will ship with the baseboard and be pre attached prior to shipping Mechanical Specifications This section documents the mechanical specifications of the boxed processor Boxed Processor Heatsink Dimensions CEK The boxed processor will be shipped with an unattached thermal solution Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the
30. MCERR AGTL Source Synchronous to assoc Synchronous I O strobe Signals Associated Strobe 4 0 16 3 3 ADSTBO A 35 17 9 ADSTB1 D 15 0 DBIO DSTBPO DSTBNO D 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 AGTL Strobe I O Synchronous to BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 AGTL Asynchronous Output Asynchronous FERR PBE IERR PROCHOT GTL Asynchronous Input Asynchronous A20M FORCEPR IGNNE LINTO INTR LINT1 NMI SLP STPCLK GTL Asynchronous Output Asynchronous THERMTRIP Front Side Bus Clock Clock BCLK1 BCLKO TAP Input Synchronous to TCK tck tdi tms trst TAP Output Synchronous to TCK TDO Power Other Power Other BOOT SELECT BSEL 1 0 COMP 1 0 GTLREF 3 0 ODTEN OPTIMIZED COMPAT PWRGOOD Reserved SKTOCC SLEW_CTRL SMB_PRT TEST_BUS TESTHI 6 0 THERMDA Vcc VccioPLL VCCSENSE VID 5 0 Vss Vssa VSSSENSE VIDPWRGD VTTEN NOTES 1 Refer to Section 4 0 for signal descriptions 2 The Intel Xeon processor with 800 MHz system bus only uses BRO and BR1 BR2 and BR3 must be terminated to For additional details regarding the BR 3 0 signals see Section 4 0 and Section 7 1 3 The value of these pins during the active to inactive edge of RESET defines the processor configuration options See Section 7 1 for details 4 These signals may be dr
31. Power Other Input VCC D8 Power Other SMB_PRT AE4 Power Other Output VCC D14 Power Other SMI C27 Async GTL Input VCC D18 Power Other STPCLK D4 Async GTL Input VCC D24 Power Other 52 Datasheet intel Intel Xeon Processor with 800 MHz System Bus Table 21 Pin Listing by Pin Name Sheet 4 of 8 Pin Name E Direction Pin Name d Direction 029 Power Other VCC K1 Power Other VCC D31 Power Other VCC K3 Power Other E2 Power Other VCC K5 Power Other Power Other VCC K7 Power Other E20 Power Other VCC K9 Power Other 26 Power Other VCC K23 Power Other E28 Power Other VCC K25 Power Other E30 Power Other VCC K27 Power Other F1 Power Other VCC K29 Power Other F4 Power Other VCC K31 Power Other F16 Power Other VCC L2 Power Other VCC F22 Power Other VCC L4 Power Other VCC F29 Power Other VCC L6 Power Other F31 Power Other VCC L8 Power Other G2 Power Other VCC L24 Power Other G4 Power Other VCC L26 Power Other G6 Power Other VCC L28 Power Other VCC G8 Power Other VCC L30 Power Other G24 Power Other VCC M1 Power Other G26 Power Other VCC M3 Power Other G28 Power Other VCC M5 Power Other VCC G30 Power Other VCC M7 Power Other H1 Power Other VCC M9 Powe
32. Source Sync I O D5 VSS Power Other E14 A24 Source Sync I O D6 INIT Async GTL Input E15 VSS Power Other D7 MCERR Common Clk I O E16 1 Power Other Input D8 VCC Power Other E17 VSS Power Other D9 AP1 Common Clk I O E18 DRDY Common Clk I O D10 BR3 Common Clk Input E19 TRDY Common Clk Input D11 VSS Power Other E20 Power Other D12 29 Source Sync E21 0 Common Input D13 25 Source Sync E22 HIT Common Clk I O D14 VCC Power Other E23 VSS Power Other D15 A18 Source Sync E24 TCK TAP Input D16 17 Source Sync 25 TDO TAP Output D17 9 Source Sync 26 Power Other D18 VCC Power Other E27 FERR PBE Async GTL Output D19 ADS Common Clk I O E28 Power Other D20 BRO Common Clk I O E29 VSS Power Other D21 VSS Power Other E30 Power Other D22 1 Common Input E31 VSS Power Other D23 BPRI Common Clik Input F1 VCC Power Other Datasheet 59 Intel Xeon Processor with 800 MHz System Bus Table 22 Pin Listing by Pin Number Sheet 3 of 8 E Pin Name S Direction Ra Pin Name M ne Direction F2 VSS Power Other G24 Power Other F3 VIDO Power Other Output G25 VSS Power Other F4 VCC Power Other G26 VCC Power Other F5 BPM3 Common Clk I O G27 VSS Power Other
33. 1 1 0 1 1125 0 0 1 1 1 0 1 5125 1 1 1 1 0 1 1 1250 1 0 1 1 0 1 1 5250 0 1 1 1 0 1 1 1375 0 0 1 1 0 1 1 5375 1 1 1 1 0 0 1 1500 1 0 1 1 0 0 1 5500 0 1 1 1 0 0 1 1625 0 0 1 1 0 0 1 5625 1 1 1 0 1 1 1 1750 1 0 1 0 1 1 1 5750 0 1 1 0 1 1 1 1875 0 0 1 0 1 1 1 5875 1 1 1 0 1 0 1 2000 1 0 1 0 1 0 1 6000 NOTES 1 When this VID pattern is observed the voltage regulator output should be disabled 2 Shading denotes the expected default VID range during normal operation for Intel Xeon processor with 800 MHz system bus 1 2875 V 1 4000 V Please note this is subject to change 3 Shaded areas do not represent the entire range of VIDs that may be driven by the processor Events causing dynamic VID transitions see Section 2 4 may result in a more broad range of VID values 2 5 Datasheet Reserved or Unused Pins All Reserved pins must remain unconnected Connection of these pins to Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 5 0 for a pin listing of the processor and the location of all Reserved pins For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level In a system level design on die termination has been included by the processor to allow end agents to be terminated within the processor silicon for most signals In this context end agent refers to the bus agent that resid
34. 12 V Yellow 3 Sense 2 pulses per revolution Green Figure 28 Cable Connector Pinout 4 pin active heatsink PIN 3 PIN4 PIN 2 32 Fan Cable Connector Pinout 4 pin active heatsink Pin Number Signal Color 1 Ground Black 2 Power 12 V Yellow 3 Sense 2 pulses per revolution Green 4 Control 21 KHz 28 KHz Blue Table 33 Fan Cable Connector Supplier and Part Number Vendor 3 Pin Connector Part Number 4 Pin Connector Part Number AMP Fan Connector 643815 3 N A Header 640456 3 Walden Fan Connector 22 01 3037 Fan Connector 47054 1000 Molex Header 22 23 2031 Header 47053 1000 Wieson N A Fan Connector 2510C888 001 Header 2366C888 007 Foxconn N A Fan Connector N A Header HF27040 M1 Datasheet 91 Intel Xeon Processor with 800 MHz System Bus ntel 8 4 8 4 1 8 4 1 1 8 4 1 2 8 4 1 3 92 Thermal Specifications This section describes the cooling requirements of the heatsink solution used by the boxed processor Boxed Processor Cooling Requirements As previously stated the boxed processor will be available in three product configurations Each configuration will require unique design considerations Meeting the processor s temperature specifications is also the function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specifications are found in Section 6 0 of this document
35. 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity SKTOCC SKTOCC Socket occupied will be pulled to ground by the processor to indicate that the processor is present There is no connection to the processor silicon for this signal SLEW_CTRL The front side bus slew rate control input SLEW_CTRL is used to establish distinct edge rates for middle and end agents SLP SLP Sleep when asserted in Stop Grant state causes processors to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Lock Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will only recognize the assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units SMB_PRT The SMBus present SMB_PRT pin is defined to inform the platform if the installed processor includes SMBus components such as the integrated thermal sensor and the processor information ROM PIROM This pin is tied to VSS by the processor if these features are not present Platforms using this pin should use a pull up resistor to the appropriate voltage level for the logic tied to this pin
36. 3 Vin Input High Voltage GTLREF Vit V 2 4 5 0 10 Vou Output High Voltage 0 90 V 2 5 lo Output Low Current N A 2 6 0 50 RTT Row lii Input Leakage Current N A 200 7 8 lio Output Leakage Current N A 200 7 8 Buffer On Resistance 7 11 Ww NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies The represented these specifications refers to instantaneous is defined as the voltage range at a receiving agent that will be interpreted as a logical low value is defined as the voltage range at a receiving agent that will be interpreted as a logical high value and Voy may experience excursions above V r Refer to Table 6 to determine which signals include additional on die termination resistance Leakage to Vgs with pin held at Leakage to with pin held at 300 mV PWRGOOD Input and TAP Signal Group DC Specifications Symbol Parameter Min Max Unit Vuys Input Hysteresis 200 350 mV 3 Vu Input Low to High 0 5 Vrr Vuvs min 0 5 Vrr Vuvs V 4 Threshold Voltage Vi Input High to Low 0 5 Vrr Vuvs max 0 5 Vrr _ V 4 Threshold Voltage Vou Output High Voltage N A Vit V 4 lot Output Low Current
37. 34 9 ONY 9NINOISN3WIQ O APGTN JO ONILYY 10 WOWININ 3AVH TVHS LY d Q3HSINIJ ALI TI BVNWVTI E y Eu den 71 039701 D 0 H 0341903 27040971 150 805 Y Y NOI 68 1123 XP 681 8 8172 8011 304802 TILNI 10 1835802 W3LLINM 901884 JHI LOOMLIA 13111006 0 034974510 0320003434 035201291019 LON LVW 513180 SLI ONY 324301 JN02 NI 035010510 SI 11 NOIIVMUOJNI 1711301 3907 NOILVYOJYOJ 131 SNIYJNOO ONIMVN SIHI Figure 25 87 Datasheet 4 Pin Baseboard Fan Header for active CEK heatsink 30 133HS 9NIMVHO 21 25 LON O0 1 37 58 u3QY3HNI de W3 WnN 3002 IMSINI 4 u3Q0v3H Nid v SOF ibu 532NV83101 6119 29096 V2 VINYS 4402 83 381 11A NI 34 29012942010 KE Map er UT RM 0418 3931102 NOISSIN 0022 9 1 431413345 35143810 53 TWN 1511 144 ASSY 934 ALO NO11d 182530 ON W3LI 100 200 00 ISNY 434 9NIONYH3101 ONY 9NINOISN3NIQ p AR O AV61 30 9 ALITIGVHNVT4 10 V 3AVH TIVHS 18 4 Q3HSINIG ALITIGYHAY E p 80100 72 ELVIE 29310953108 14 2701 IN ids 00 T p9 0 Xr 7920 xr 8 g 20 802 UORSI poe XE 62 807 011
38. AD24 Source Sync I O 061 Source Sync I O 022 AE23 Source Sync I O 062 Y9 Source Sync I O 023 AC23 Source Sync 063 6 Source Sync I O D24 18 Source Sync I O DBSY F18 Common Clk I O D25 20 Source Sync I O DEFER C23 Common Clk Input D26 AC21 Source Sync I O DBIO 27 Source Sync I O D27 AE22 Source Sync I O DBI1 AD22 Source Sync I O D28 AE20 Source Sync I O DBI2 AE12 Source Sync I O D29 AD21 Source Sync I O DBI3 AB9 Source Sync I O D30 AD19 Source Sync I O DPO AC18 Common Clk I O D31 AB17 Source Sync I O DP1 19 Common Clk D32 AB16 Source Sync I O DP2 AC15 Common Clk D33 AA16 Source Sync I O DP3 AE17 Common Clk I O D34 AC17 Source Sync I O DRDY E18 Common Clk I O D35 AE13 Source Sync I O DSTBNO Y21 Source Sync 036 AD18 Source Sync I O DSTBN1 Y18 Source Sync I O D37 AB15 Source Sync I O DSTBN2 Y15 Source Sync 038 AD13 Source Sync DSTBN3 Y12 Source Sync I O 039 AD14 Source Sync DSTBPO Y20 Source Sync I O D40 AD11 Source Sync I O DSTBP1 Y17 Source Sync I O D41 AC12 Source Sync I O DSTBP2 Y14 Source Sync I O D42 AE10 Source Sync I O DSTBP3 Y11 Source Sync 11 Source Sync FERR PBE E27 Async GTL Output D44 Source Sync FORCEPR A15 Async GTL Input D45 AD10 Source Sync
39. Intel EM64T Processor will not operate including 32 bit operation without an Intel EM64T enabled BIOS Performance will vary depending on your hardware and software configurations Intel EM64T enabled OS BIOS device drivers and applications may not be available Check with your vendor for more information Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See www intel com products processor number for details Other names and brands may be claimed as the property of others Copyright O 2004 Intel Corporation 2 Datasheet ntel Intel Xeon Processor with 800 MHz System Bus D Contents 1 0 2 0 3 0 4 0 5 0 Introductio M A w M 9 127 Teninology iir is See oie 10 1 2 m 12 1 3 Ea usui is n eene drag 12 Electrical Specifications nuu 13 24 JPowerand Ground Pins tentat etre hd ite te a ere ee era et 13 2 2 Decoupling Guideline Ssnin iiien na eene aaea nnns 13 2 2 1 Meg Decoupling eee teni tea 13 2 2 2 MT T oi deett nee pet b Ran deter 13 2 2
40. MB on die level 2 L2 cache with increased bandwidth The floating point and multi media units include 128 bit wide registers and a separate register for data movement Streaming SIMD2 SSE2 instructions provide highly efficient double precision floating point SIMD integer and memory management operations In addition SSE3 instructions have been added to further extend the capabilities of Intel processor technology Other processor enhancements include core frequency improvements and microarchitectural improvements The Intel Xeon processor with 800 MHz system bus supports Intel Extended Memory 64 Technology Intel EM64T as an enhancement to Intel s IA 32 architecture This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Further details on Intel amp Extended Memory 64 Technology and its programming model can be found in the 64 bit Extension Technology Software Developer s Guide at http developer intel com technology 64bitextensions Intel Xeon processor with 800 MHz system bus is intended for high performance workstation and server systems with up to two processors on one system bus The processor will be packaged in 604 pin Flip Chip Micro Pin Grid Array FC mPGA4 package and will use a surface mount Zero Insertion Force ZIF socket mPGA 604 Intel Xeon Processor with 800 MHz System Bus ntel Table 1 1 1
41. OUTLINE SHOWN FOR REFERENCE ONLY ES g 5 E 2s 7 DES gs K xo E 2S3 55 um 8 55 CIE E ee 2 2 25 C 22 Jg 15 25 2 zz 2 et 2 BE lt gt 5 22 e 50 2 zz E nE wor eau ga 158 S 5 5 8 s d 5 85 58 2 55 a a lt Datasheet 85 Intel Xeon Processor with 800 MHz System Bus n Figure 24 Volumetric Height Keep Ins p pm 5 22 H x 8 e e i CU r3 i gt KE 598 4 722 uo o ud pes oO E i lt gt a e gt 1 86 Datasheet Intel Xeon Processor with 800 MHz System Bus 4 Pin Fan Cable Connector for active CEK heatsink t 30 133HS 9 3105 LON 00 1 2 31 25 INO Nid SOF 6118 25096 2 VIT VINYS 4902 54313NI TUN NI 34 SNOISNINIG 1185 X09 9 d 1 18 3931102 NOISSIN 0077 3 431412345 35149310 SETIN 1511 lt 18 4 6 21 0114192530 ISNY
42. Power Other VSS J29 Power Other VSS D28 Power Other VSS J31 Power Other VSS D30 Power Other VSS K2 Power Other VSS E9 Power Other VSS K4 Power Other VSS E15 Power Other VSS K6 Power Other VSS E17 Power Other VSS K8 Power Other VSS E23 Power Other VSS K24 Power Other VSS E29 Power Other VSS K26 Power Other Datasheet 55 Intel Xeon Processor with 800 MHz System Bus Table 21 Pin Listing by Pin Name Sheet 7 of 8 Pin Name 2 M Direction Pin Name hi i ae Direction VSS K28 Power Other VSS R6 Power Other VSS K30 Power Other VSS R8 Power Other VSS L1 Power Other VSS R24 Power Other VSS L3 Power Other VSS R26 Power Other VSS L5 Power Other VSS R28 Power Other VSS L7 Power Other VSS R30 Power Other VSS L9 Power Other VSS T1 Power Other VSS L23 Power Other VSS T3 Power Other VSS L25 Power Other VSS T5 Power Other VSS L27 Power Other VSS T7 Power Other VSS L29 Power Other VSS T9 Power Other VSS L31 Power Other VSS T23 Power Other VSS M2 Power Other VSS T25 Power Other VSS M4 Power Other VSS T27 Power Other VSS M6 Power Other VSS T29 Power Other VSS M8 Power Other VSS T31 Power Other VSS M24 Power Other VSS U2 Power Other VSS M26 Power Other VSS U4 Power Other VSS M28 Power Other VSS U6 Power Other VSS M30 Power Other VSS U8 Power Other VSS N2 Power Oth
43. The Vccp input should left unconnected VCCSENSE VSSSENSE VCCSENSE and VSSSENSE provide an isolated low impedance connection to the processor core power and ground They can be used to sense or measure power near the silicon with little noise VID 5 0 VID 5 0 Voltage ID pins are used to support automatic selection of power supply voltages Vcc These are open drain signals that are driven by the processor and must be pulled up through a resistor Conversely the VR output must be disabled prior to the voltage supply for these pins becomes invalid The VID pins are needed to support processor voltage specification variations See Table 4 for definitions of these pins The VR must supply the voltage that is requested by these pins or disable itself 46 Datasheet ntel Intel Xeon Processor with 800 MHz System Bus D Table 20 Signal Definitions Sheet 9 of 9 Name Type Description Notes VIDPWRGD The processor requires this input to determine that the supply voltage for BSEL 1 0 and VID 5 0 is stable and within specification Vssa provides an isolated internal ground for internal PLL s Do not connect directly to ground This is to be connected to and through a discrete filter circuit The front side bus termination voltage input pins Refer to Table 9 for further details VTTEN The VTTEN can be used as an output ena
44. Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 6 4 GBytes second 6400 MBytes second Finally the system bus is also used to deliver interrupts Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the asserted state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 refers to hex A and D 3 0 also refers to a hex H High logic level L Low logic level Front side bus or System bus refers to the interface between the processor system core logic a k a the chipset components and other bus agents The system bus is a multiprocessing interface to processors memory and I O For this document front side bus or system bus are used as generic terms for the Intel Xeon processor with 800 MHz system bus Commonly used terms are explained here for clarification Intel Xeon Processor with 800 MHz System Bus Intel 32 bit microprocessor intended for dual processor servers and workstations The Intel Xeon processor with 800 system bus is based on Intel
45. an interrupt delivered over the front side bus RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the JA 32 Intel Architecture Software Developer s Manual Volume III System Programming Guide for more information The system can generate a STPCLK while the processor is in the HALT Power Down state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state While in HALT Power Down state the processor will process front side bus snoops and interrupts Stop Clock State Machine HALT or Instruction and HALT Bus Cycle Generated HALT State INIT BINT INTR SIME BCLK running RESET FSB Interrupts Snoops and interrupts allowed Stop Grant State BCLK running Service and interrupts allowed CS00268 Stop Grant State When the STPCLK pin is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Acknowledge special bus cycle Once the STPCLK has been asserted it may only be deasserted once the processor is in the state For the Intel Xeon processor with 800 MHz system bus both logical processors must be in the state before the deassertion of STPCLK Datasheet 7 2 4 7 2 5 Datasheet Intel Xeon Processor with 800 MHz Sys
46. boxed processor and assembled heatsink are shown in Figure 20 through Figure 24 Figure 25 through Figure 26 are the mechanical drawings for the 4 pin server board fan header and 4 pin connector used for the active CEK fan heatsink solution 81 Intel Xeon Processor with 800 MHz System Bus Figure 20 82 Top Side Board Keepout Zones Part 1 t a wo z Ne 55 cs 32 G R 4 8 E i 53 m a E S T d SII 2 z 8 pi l eo0cee m T Datasheet n Intel Xeon Processor with 800 MHz System Bus Figure 24 Side Board Keepout Zones Part 2
47. capacitors amp W N Package pin Die Side Capacitors Processor Package Assembly Sketch NOTE This drawing is to scale and is for reference only The mPGA604 socket is not shown Package Mechanical Drawings The package mechanical drawings are shown in Figure 7 and Figure 8 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include Package reference and tolerance dimensions total height length width etc IHS parallelism and tilt Pin dimensions Top side and back side component keepout dimensions Reference datums QN A N drawing dimensions are in mm in 31 Intel Xeon Processor with 800 MHz System Bus Processor Package Drawing Sheet 1 of 2 Figure 7 1 30 31 29 LON 00 3 IWS 3002 3999 3715 SIRE L 5 711130 ONIMVHC SLNE AB NOllO3fONd 319NV QMIHL 320 0 F ar 3 5 aui 5 200 10071 192071 0118 25090 Yo nva viis Pu
48. from previous generations are 1 Centralization of the Geyserville control mechanism into the processor 2 Reduced hardware overhead and continued execution of instructions during voltage transitions Voltage frequency selection is software controlled by writing to the processor Model Specific Registers MSRs If the target frequency is higher than the current frequency is incremented in steps 412 5 mV by placing new value on the VID signals The Phase Lock Loop PLL then locks to the new frequency Note that the top frequency for the processor can not be exceeded If the target frequency is lower than the current frequency the PLL locks to the new frequency The is then decremented in step 12 5 mV by changing the target VID through the VID signals Datasheet intel 8 0 Intel Xeon Processor with 800 MHz System Bus Boxed Processor Specifications 8 1 Figure 16 Datasheet Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels The Intel Xeon processor with 800 MHz system bus will be offered as an Intel boxed processor Intel will offer boxed the Intel Xeon processor with 800 MHz system bus with three product configurations available for each processor frequency 1U passive 20 passive and 20 Active Although the active heatsink mechanically fits into a 2U keepout additional design con
49. in the mPGA604 Socket Design Guidelines Processor Mass Specifications The typical mass of the Intel Xeon processor with 800 MHz system bus is 25 grams 0 88 oz This mass weight includes all components which make up the entire processor product Processor Materials The Intel Xeon processor with 800 MHz system bus is assembled from several components The basic material properties are described in Table 19 Processor Materials Component Material Integrated Heat Spreader IHS Nickel over copper Substrate Fiber reinforced resin Substrate Pins Gold over nickel 35 Intel Xeon Processor with 800 MHz System Bus n 3 8 Processor Markings Figure 9 shows the topside markings and Figure 10 shows the bottom side markings on the processor These diagrams are to aid in the identification of the Intel Xeon processor with 800 MHz system bus Figure 9 Processor Top Side Markings Example 2D Matrix IN Includes ATPO and Serial ipi Number front end mark Serial Number Ys Pin 1 Indicator NOTES 1 All characters will be in upper case 2 Drawing is not to scale Figure 10 Processor Bottom Side Markings Example Pin 1 Indicator Pin Field Speed Cache Bus Voltage 3600DP 1MB 800 1 325V SL6NY COSTARICA S Spec 0096109 0021 Country Assy FPO Serial 13 characters NOTES
50. micro architecture and the Hyper Threading Technology it is binary compatible with previous Intel Architecture 32 processors The Intel Xeon processor with 800 MHz system bus is scalable to two processors in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Windows XP Windows Server 2003 Linux and The Intel Xeon processor with 800 MHz system bus delivers compute power at unparalleled value and flexibility for powerful workstations internet infrastructure and departmental server applications The Intel NetBurst micro architecture and Hyper Threading Technology deliver outstanding performance and headroom for peak internet server workloads resulting in faster response times support for more users and improved scalability E E us di Document Number 302355 001 June 2004 Intel Xeon Processor with 800 MHz System Bus n INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILI
51. receiving agent that will be interpreted as a logical low value 4 is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 5 and Voy may experience excursions above V 4 6 Refer to Table 2 5 to determine which signals include additional on die termination resistance 7 Leakage to Vgg with pin held at Vyr 8 Leakage to with pin held at 300 mV VIDPWRGD DC Specifications Symbol Parameter Min Max Unit Input Low Voltage 0 0 0 30 V Vin Input High Voltage 0 90 Vit V Datasheet Intel Xeon Processor with 800 MHz System Bus Mechanical Specifications Figure 6 3 1 Datasheet The Intel Xeon processor with 800 MHz system bus is packaged in Flip Chip Micro Pin Grid Array FC mPGA4 package that interfaces to the baseboard via mPGA604 socket The package consists of a processor core mounted on a substrate pin carrier integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 6 shows a sketch of the processor package components and how they are assembled together Refer to the mPGA604 Socket Design Guidelines for complete details on the mPGA604 socket The package components shown in Figure 6 include the following 1 Integrated Heat Spreader IHS Processor die Substrate Pin side
52. s 90 nanometer process and will include core frequency improvements a large cache array microarchitectural improvements and additional instructions The Intel Xeon processor with 800 MHz system bus will use the mPGA604 socket For this document processor is used as the generic term for the Intel Xeon processor with 800 MHz system bus Central Agent The central agent is the host bridge to the processor and is typically known as the chipset Datasheet Datasheet Intel Xeon Processor with 800 MHz System Bus Demand Based Switching DBS with Enhanced Intel SpeedStep Technology Demand Based Switching DBS with Enhanced Intel SpeedStep Technology is the next generation implementation of Geyserville technology which extends power management capabilities of servers and workstations Enterprise Voltage Regulator Down EVRD DC DC converter integrated onto the system board that provide the correct voltage and current for the processor based on the logic state of the VID bits Flip Chip Micro Pin Grid Array 4 Package The processor package is a Flip Chip Micro Pin Grid Array FC mPGA4 consisting of a processor core mounted a pinned substrate with an integrated heat spreader IHS This package technology employs a 1 27 mm 0 05 in pitch for the processor pins Front Side Bus FSB The electrical interface that connects the processor to the chipset Also referred to as the p
53. should be used for processor chipset thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum 5 These specifications are based on silicon characterization however they may be updated as further data becomes available 6 Power specifications are defined at all VIDs found in Table 9 The Intel Xeon processor with 800 MHz system bus may be shipped under multiple VIDs listed for each frequency 7 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements FMB is a design target that is sequential in time Datasheet n Intel Xeon Processor with 800 MHz System Bus Figure 13 Intel Xeon Processor with 800 MHz System Bus Thermal Profiles and B Tease cn E LLL 1 Thermal Profile Tease wx gisathermal solution desi int 1 i Tea plos Thermal ProfleA units will not i 028 43 exceed Tcase adue 404 to TCC activation i 0 10 3D 40 5D 6 70 50 9 100 110 PoonmoL Base PoonTROL_BASE_A Power W NOTES 1 Thermal Profile A is representative of a volumetrically unconstrained platform Please refer to Table 24 for discrete points that constitute the t
54. system all the STPCLK signals are bussed together thus all processors are affected in unison The Hyper Threading Technology feature adds the conditions that all logical processors share the same STPCLK signal internally When the STPCLK signal is asserted the processor enters the state issuing a Special Bus Cycle SBC for each processor or logical processor The chipset needs to account for a variable number of processors asserting the SBC on the bus before allowing the processor to be transitioned into one of the lower processor power states Refer to the applicable chipset specification for more information Due to the inability of processors to recognize bus transactions during the Sleep state multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the other processors in Normal or Stop Grant state 75 Intel Xeon Processor with 800 MHz System Bus ntel 7 2 1 7 2 2 Figure 15 7 2 3 76 Normal State This is the normal operating state for the processor HALT Power Down State HALT is a low power state entered when all logical processors have executed the HALT or MWAIT instruction When one of the logical processors executes the HALT or MWAIT instruction that logical processor is halted however the other processor continues normal operation The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT LINT 1 0 NMI INTR or
55. the heatsink Thermal Interface Material pre applied on heatsink Installation Manual Intel Inside Logo The other items listed in Figure 19 that are required to compete this solution will be shipped with either the chassis or boards They are as follows CEK Spring supplied by baseboard vendors Heatsink standoffs supplied by chassis vendors 93 Intel Xeon Processor with 800 MHz System Bus 94 Datasheet Intel Xeon Processor with 800 MHz System Bus Debug Tools Specifications 9 1 Note 9 2 9 2 1 9 3 Datasheet Please refer to the 700 Debug Port Design Guide for information regarding debug tool specifications Section 1 2 provides collateral details Debug Port System Requirements The Intel Xeon processor with 800 MHz system bus debug port is the command and control interface for the In Target Probe ITP debugger The ITP enables run time control of the processors for system debug The debug port which is connected to the front side bus is a combination of the system JTAG and execution signals There are several mechanical electrical and functional constraints on the debug port that must be followed The mechanical constraint requires the debug port connector to be installed in the system with adequate physical clearance Electrical constraints exist due to the mixed high and low speed signals of the debug port for the processor While the signals operate at a maximum of 75
56. voltage regulation circuit cannot supply the voltage that is requested it must disable itself See the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines or Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 1 Design Guidelines for further details The Intel Xeon processor with 800 MHz system bus provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 9 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 10 and Figure 4 The VRM or VRD used must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 9 and Table 10 Please refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines or Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 1 Design Guidelines for further details Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable
57. will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRIP Driving of the THERMTRIP signals is enabled within 10 ms of the assertion of PWRGOOD and is disabled on de assertion of PWRGOOD Once activated THERMTRIP remains latched until PWRGOOD is de asserted While the de assertion of the PWRGOOD signal will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 ms of the assertion of PWRGOOD TMS TMS Test Mode Select is a JTAG specification support signal used by debug tools This signal does not have on die termination and must be terminated at the end agent TRDY TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all front side bus agents TRST TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset VCCA Voca provides isolated power for the analog portion of the internal processor core PLLs VccioPLL Provides isolated power for digital portion of the internal processor core PLLs VccPLL The on die PLL filter solution will not be implemented on this platform
58. with 800 MHz system bus the SLP pin may only be asserted when all logical processors in the Stop Grant state SLP assertions while the processors are not in the Stop Grant state are out of specification and may results in illegal operation Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior 77 Intel Xeon Processor with 800 MHz System Bus ntel 7 3 78 Note In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP or RESET are allowed on the front side bus while the processor is in Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through Stop Grant state If RESET is driven active while the processor is in the Sleep state the SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the reset sequence When the processor is in Sleep state it will not respond to interrupts or snoop transactions Demand Based Switching DBS with Enhanced Intel SpeedStep Technol
59. 0 56 59 98 70 58 59 60 60 62 60 64 61 Table 25 Intel Xeon Processor with 800 MHz System Bus Thermal Profile B Power W Tcase C Power W Tcase C Base p 18 20 64 66 O 22 24 68 68 26 70 64504 28 72 6 30 32 36 57 80 72 38 40 42 ee 74 46 60 90 76 48 50 52 78 56 64 100 79 58 12 80 O 60 104 ao 70 Datasheet intel 6 1 2 Figure 14 6 2 6 2 1 Datasheet Intel Xeon Processor with 800 MHz System Bus Thermal Metrology The maximum case temperatures Asp are specified in Table 24 Table 25 and measured at the geometric top center of the processor integrated heat spreader IHS Figure 14 illustrates the location where temperature measurements should be made For detailed guidelines on temperature measurement methodology refer to the appropriate thermal mechanical design guide Case Temperature Measurement Location 21 25 mm 0 837 in Measure from edge of processor 2125 mm 0 837 in Measure T cAsE atthis point 42 5 mm FC mPGA4 Package NOTE Figure is not to scale and is for reference only Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the Thermal Control Circuit TCC when the processor silicon reaches its maximum operating temperature The TCC
60. 0 DC specification Front Side Bus termination voltage 1 140 1 20 1 260 V 10 11 AC amp DC specification loc Icc for Intel Xeon processor with 800 MHz system bus with multiple VIDs 2 80 3 60 GHz 100 A 6 19 FMB 120 A 6 7 20 Front Side Bus 4 8 A 12 current Front Side Bus mid agent 1 5 A 18 current Icc for PLL power pins 120 mA 14 vccioPLL loc for PLL power pins 100 mA 14 GrLREF lec for GTLREF pins 200 15 Icc Stop Grant for Intel 7 16 19 processor with 800 MHz system bus 2 80 GHz 50 loc TCC Active loc A 17 loc Icc for Intel Xeon processor with 800 MHz system bus Thermal Design Current 2 80 3 60 GHz 85 A 18 19 FMB 105 A 7 18 20 NOTES 1 Unless otherwise noted all specifications in this table apply to all processors These specifications are based on silicon characterization however they may be updated as further data becomes available Listed frequencies are not necessarily committed production frequencies 2 Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different VID settings 3 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 4 for more information 4 The voltage specification requiremen
61. 0 MHz system bus should only be used in SMP systems which have two or fewer agents Thermal Design Power Processor chipset thermal solution should be designed to this target It is the highest expected sustainable power while running known power intensive real applications TDP is not the maximum power that the processor chipset can dissipate Voltage Regulator Module VRM DC DC converter built onto a module that interfaces with an appropriate card edge socket that supplies the correct voltage and current to the processor The processor core power supply Vss The processor ground The system bus termination voltage Intel Xeon Processor with 800 MHz System Bus 1 2 1 3 12 INTel References Material and concepts available in the following documents may be beneficial when reading this document Intel Document Document Number Intel Extended Memory 64 Technology Software Developer s Manual Volume 1 300834 Intel Extended Memory 64 Technology Software Developer s Manual Volume 2 300835 mPGA604 Socket Design Guidelines 254232 AP 485 Intel Processor Identification and CPUID Instruction 241618 32 Intel Architecture Optimization Reference Manual 248966 IA 32 Intel Architecture Software Developer s Manual Volume 1 Basic Architecture 253665 IA 32 Intel Architecture Software Developer s Manual Volume 2A Instruction Set 253666 Refer
62. 15 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset purposes the processor does not distinguish between a warm reset and a power on reset Power On Configuration Option Pins Configuration Option Pin Notes Output tri state 1 2 Execute BIST Built In Self Test INIT 1 2 In Order Queue de pipelining set IOQ depth to 1 ATi 1 2 Disable MCERR observation 9 1 2 Disable BINIT observation A104 1 2 Disable bus parking A158 1 2 Symmetric agent arbitration ID BR 3 0 1 2 3 Disable Hyper Threading Technology A31 1 2 NOTES 1 Asserting this signal during RESET will select the corresponding option 2 Address pins not identified in this table as configuration options should not be asserted during RESET 3 The Intel Xeon processor with 800 MHz system bus only uses the BRO and BR1 signals Platforms must not use BR2 and BR3 signals Clock Control and Low Power States The processor allows the use of HALT Stop Grant and Sleep states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 15 for a visual representation of the processor low power states The state requires chipset and BIOS support on multiprocessor systems In a multiprocessor
63. 3 Front Side Bus AGTL 13 2 3 Front Side Bus Clock BCLK 1 0 and Processor Clocking 14 2 3 1 Front Side Bus Frequency Select Signals 5 1 0 14 2 3 2 Phase Lock Loop PLL and Filter 15 2 4 Voltage Identification VID 15 2 5 Reserved or Unused PINS Ea 17 2 6 Front Side Bus Signal Groups 18 2 7 Asynchronous AGTL Asynchronous 5 20 2 8 Test Access Port TAP eene nennen nennen 21 2 9 Mixing PIOCESSOIS ipei ite ite be EH dl eva ie 21 2 10 Absolute Maximum and Minimum Ratings 21 2 11 Processor DC Specifications nine dt 22 2 11 1 Flexible Motherboard Guidelines 22 2 11 2 Overshoot Specification 27 2 11 3 Die Voltage Validation era ek teca Eo ee rax 28 Mechanical Specifications 31 3 1 Package Mechanical 31 3 2 Processor Component Keepout 7 34 3 3 Package Loading 0 4 4 34 3 4 Package Handling Guidelines
64. 4 FORCEPR Signal 72 6 2 5 THERMTRIP t Signal 73 6 2 6 and Fan Speed 73 6 2 7 Thermal Diode ne ng 73 Features oclo tec t teet am en termi td 75 7 1 Power On Configuration 75 7 2 Clock Control and Low Power 75 7 2 1 Normal State E eet a De E dede i Dev tec eae 76 7 2 2 HALT Power Down 81 76 7 2 3 Stop Grant State eaaet edt e e e eee 76 7 2 4 HALT Snoop State or Snoop 77 7 2 5 Sleep State une pe epe 77 7 8 Demand Based Switching DBS with Enhanced Intel SpeedStep Technology 78 Boxed Processor 79 8 1 Introduction REIS 79 8 2 Mechanical Specifications 81 8 2 1 Boxed Processor Heatsink Dimensions 81 8 2 2 Boxed Processor Heatsink Weight 89 8 2 3 Boxed Processor Retention Mechanism and Heatsink Support 89 8 3 Electrical 89 8 8 1 Fan Power Supply active 89 8 4 Thermal SpecifiCatioris ieri er eor E e e PR ERE RR SE EX a tere e ah 92 8 4 1 Boxed Processor Coo
65. 45 mA 5 lu Input Leakage Current N A 200 lio Output Leakage Current N A 200 RoN Buffer On Resistance 7 11 Ww NOTES Unless otherwise noted all specifications in this table apply to all processor frequencies All outputs are open drain represents the amount of hysteresis nominally centered about 0 5 Vr for all PWRGOOD inputs The represented in these specifications refers to instantaneous The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load 29 Intel Xeon Processor with 800 MHz System Bus n Table 15 Table 16 30 GTL Asynchronous and AGTL Asynchronous Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Vit Input Low Voltage 0 0 GTLREF 0 10 V 2 8 Input High Voltage GTLREF 0 10 V 2 4 5 Vou Output High Voltage 0 90 Vr V 2 5 lot Output Low Current N A 2 6 0 50 MIN Row lu Input Leakage Current N A 200 7 8 lio Output Leakage Current N A 200 7 8 Ron Buffer On Resistance 7 11 Ww NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The represented in these specifications refers to instantaneous 3 is defined as the voltage range at a
66. All processor front side bus agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss Datasheet 39 Intel Xeon Processor with 800 MHz System Bus Table 20 Signal Definitions Sheet 2 of 9 Description Notes BINIT yo BINIT Bus Initialization may be observed and driven by all processor front side bus agents and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future information If BINIT observation is enabled during power on configuration see Figure 7 1 and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their I O Queue and transaction tracking state machines upon observation of BINIT assertion Once the BINIT assertion has been observed the bus agents will re arbitrate for the front side bus and attempt completion of their bus queue and IOQ entries If BINIT observation is disabled during power on configuration central agent may handle an assertion of BINIT as appropriate to the error handling architecture of the System Since multiple agents may drive this signal at the same time
67. C depending on the pedestal chassis layout Also while the active heatsink solution is designed to mechanically fit into a 2U chassis it may require additional space at the top of the heatsink to allow sufficient airflow into the heatsink fan Therefore additional design criteria may need to be considered if this heatsink is used in a 2U rack mount chassis or in a chassis that has drive bay obstructions above the inlet to the fan heatsink Thermal Profile A should be used to help determine the thermal performance of the platform Once again it is recommended that the ambient air temperature outside of the chassis be kept at or below 35 C The air passing directly over the processor heatsink should not be preheated by other system components Meeting the processor s temperature specification is the responsibility of the system integrator Datasheet Datasheet Intel Xeon Processor with 800 MHz System Bus Boxed Processor Contents A direct chassis attach method must be used to avoid problems related to shock and vibration due to the weight of the heatsink required to cool the processor The board must not bend beyond specification in order to avoid damage The boxed processor contains the components necessary to solve both issues The boxed processor will include the following items Intel Xeon processor with 800 MHz system bus Unattached Active or Passive Heatsink 4 screws 4 springs and 4 heatsink standoffs all captive to
68. D 0 146 VID 0 153 VID 0 159 VID 0 165 VID 0 171 VID 0 178 VID 0 184 VID 0 190 intel NOTES 1 The Voc loadlines represent static and transient limits Please see Section 2 11 2 for Voc overshoot specifications 2 This table is intended to aid in reading discrete points on Figure 4 3 The loadlines specify voltage limits at the die measured at the VCCSENSE and VSSSENSE pins Voltage regulation feedback for voltage regulator circuits must be taken from processor Vcc Vss pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines and Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 1 Design Guidelines for socket loadline guidelines and VR implementation Datasheet Figure 4 Intel Xeon Processor with 800 MHz System Bus Static and Transient Tolerance VID 0 000 VID 0 040 Vcc V VID 0 200 VID 0 020 4 VID 0 060 4 VID 0 080 4 VID 0 100 4 VID 0 120 4 VID 0 140 4 VID 0 160 4 VID 0 180 4 0 1 A 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 Pd Maximum Vcc Minimum NOTES 1 The Voc loadlines represent static and transient limits Please see Section 2 11 2 for overshoot specif
69. D 63 48 DBSY Vo DBSY Data Bus Busy is asserted by the agent responsible for driving data on the 4 processor front side bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor front side bus agents DEFER DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in 4 order completion Assertion of DEFER is normally the responsibility of the addressed memory or I O agent This signal must connect the appropriate pins of all processor front side bus agents DP 3 0 yo DP 3 0 Data Parity provide parity protection for the D 63 0 signals They are driven 4 by the agent responsible for driving D 63 0 and must connect the appropriate pins of all processor front side bus agents DRDY VO DRDY Data Ready is asserted by the data driver on each data transfer indicating valid 4 data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor front side bus agents DSTBN 3 0 yo Data strobe used to latch in D 63 0 4 Signals Associated Strobes D 15 0 DBIO DSTBNO D 31 16 DBI1 DSTBN1 D 47 32 DBI2 DSTBN2 D 63 48 DBI3 DSTBN3 DSTBP 3 0 yo Data strobe used to latch in D 63 0 4 Signals Associated Strobes D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48
70. EVRD 10 1 Design Guidelines The voltage set by the VID signals is the maximum voltage allowed by the processor please see Section 2 11 2 for overshoot specifications VID signals are open drain outputs which must be pulled up to Please refer to 15 Intel Xeon Processor with 800 MHz System Bus ntel Table 12 for the DC specifications for these signals A minimum voltage is provided in Table 9 and changes with frequency This allows processors running at a higher frequency to have a relaxed minimum voltage specification The specifications have been set such that one voltage regulator can operate with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings This is reflected by the VID Range values provided in Table 9 Refer to the Intel Xeon processor with 800 MHz System Bus Specification Update for Specification Update for further details on specific valid core frequency and VID values of the processor The Intel Xeon processor with 800 MHz system bus uses six voltage identification signals VID 5 0 to support automatic selection of power supply voltages Table 4 specifies the voltage level corresponding to the state of VID 5 0 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty VID 5 0 x11111 or the
71. I NMI SMI SLP and STPCLK use Datasheet 2 8 2 9 2 10 Datasheet Intel Xeon Processor with 800 MHz System Bus input buffers Legacy output THERMTRIP uses output buffers of these Asynchronous GTL signals follow the same DC requirements signals however the outputs are not driven high during the logical 0 to 1 transition by the processor FERR PBE TERR and IGNNE have now been defined as AGTL asynchrnous signals as they include active p MOS device asynchronous and AGTL asynchronous signals do not have setup or hold time specifications in relation to BCLK 1 0 However all of the GTL asynchronous and AGTL asynchronous signals are required to be asserted deasserted for at least six BCLKs in order for the processor to recognize them See Table 15 for the DC specifications for the asynchronous GTL signal groups Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor s be first in the TAP chain and followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Similar considerations must be made for TMS and TRST Two copies of each signal may be required with each driving a different voltage lev
72. Intel Xeon Processor with 800 MHz System Bus Datasheet Product Features m Available at 2 80 3 3 20 3 40 3 60 GHz m Intel Extended Memory 64 Technology m 90 nm process technology m 1 Advanced Transfer Cache On die m Dual processing server workstation support full speed Level 2 L2 Cache with 8 way associativity and Error Correcting Code m Binary compatible with applications ECC running on previous members of Intel s IA 32 microprocessor line See system support of up to 64 GB of m Intel NetBurst micro architecture po AE m 144 Streaming SIMD Extensions 2 SSE2 m Hyper Threading Technology instructions m Hardware support for multithreaded m 13 Streaming SIMD Extensions 3 SSE3 applications instructions m Faster 800 MHz system bus m Enhanced floating point and multimedia m Rapid Execution Engine Arithmetic Logic unit for enhanced video audio encryption Units ALUS run at twice the processor and 3D performance core frequency m System Management mode m Hyper Pipelined Technology m Thermal Motor m Advanced Dynamic Execution m Machine Check Architecture MCA m Very deep out of order execution m Demand Based Switching DBS with m Enhanced branch prediction Enhanced Intel SpeedStep Technology m Includes 16 KB Level 1 data cache The Intel Xeon processor with 800 MHz system bus is designed for high performance dual processor workstation and server applications Based on the Intel NetBurst
73. MHz the execution signals operate at the common clock front side bus frequency 200 MHz The functional constraint requires the debug port to use the JTAG system via a handshake and multiplexing scheme In general the information in this chapter may be used as a basis for including all run control tools in Intel Xeon processor with 800 MHz system bus based system designs including tools from vendors other than Intel The debug port and JTAG signal chain must be designed into the processor board in order to use the ITP for debug purposes Target System Implementation System Implementation Specific connectivity and layout guidelines for the Debug Port are provided in the 7P700 Debug Port Design Guide Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Intel Xeon processor with 800 MHz system bus systems Tektronix and Agilent should be contacted to obtain specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Intel Xeon processor with 800 MHz system bus based multiprocessor systems the LAI is critical in providing the ability to probe and capture front side bus signals There are two sets of considerations to keep in mind when designing a Intel amp XeonTM processor with 800 MHz syst
74. MPAT 2 PROCHOT PWRGOOD REQ 4 0 RESET RS 2 0 RSP SKTOCC SLEW SLP SMI STPCLK TDI TEST BUS TESTHI 6 0 THERMDA THERMDC THERMTRIP TMS TRDY TRST VID 5 0 VIDPWRGD VTTEN Open Drain Signals 5 0 BRO BSEL 1 0 FERR PBE IERR THERMTRIP VID 5 0 NOTES 1 Signals that do not have nor are actively driven to their high voltage level 2 The termination for these signals is not The OPTIMIZED COMPAT and SELECT pins have 500 5000 pull up to Signal Reference Voltages GTLREF 0 5 Vir BINIT BNR BPM 5 0 BPRI BR 3 0 NMI LOCK MCERR ODTEN RESET STPCLK TRDY A20M A 35 3 ADS ADSTB 1 0 AP 1 0 0163 0 DBI 3 0 DBSY DEFER 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FORCEPR HIT HITM IGNNE INIT LINTO INTR LINT1 REQ 4 0 RS 2 0 RSP SLEW_CTRL SLP BOOT_SELECT OPTIMIZED COMPAT PWRGOOD TDI TMS TRST4 VIDPWRGD NOTES 1 These signals also have hysteresis added to the reference voltage See Table 14 for more information GTL Asynchronous and AGTL Asynchronous Signals The Intel Xeon processor with 800 MHz system bus does not use CMOS voltage levels on any signals that connect to the processor silicon As a result input signals such as A20Mff FORCEPR IGNNE INIT LINTO INTR LINT
75. NTR signal becomes INTR a maskable interrupt request signal and LINT1 NMI becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK yo LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor front side bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor front side bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor front side bus throughout the bus locked operation and ensure the atomicity of lock MCERR yo Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor front side bus agents assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled Asserted if configu
76. Other N8 VSS Power Other L5 VSS Power Other N9 VCC Power Other L6 VCC Power Other N23 VCC Power Other L7 VSS Power Other N24 VSS Power Other L8 VCC Power Other N25 VCC Power Other L9 VSS Power Other N26 VSS Power Other L23 VSS Power Other N27 VCC Power Other L24 VCC Power Other N28 VSS Power Other L25 VSS Power Other N29 VCC Power Other L26 VCC Power Other N30 VSS Power Other L27 VSS Power Other N31 VCC Power Other L28 VCC Power Other P1 VSS Power Other L29 VSS Power Other P2 VCC Power Other L30 VCC Power Other P3 VSS Power Other L31 VSS Power Other P4 VCC Power Other Datasheet 61 Intel Xeon Processor with 800 MHz System Bus Table 22 Pin Listing by Pin Number Sheet 5 of 8 E Pin Name Direction ia Pin Name M ne Direction P5 VSS Power Other T9 VSS Power Other P6 VCC Power Other T23 VSS Power Other P7 VSS Power Other T24 Power Other P8 VCC Power Other T25 VSS Power Other P9 VSS Power Other T26 VCC Power Other P23 VSS Power Other T27 VSS Power Other P24 VCC Power Other T28 VCC Power Other P25 VSS Power Other T29 VSS Power Other P26 VCC Power Other T30 Power Other P27 VSS Power Other T31 VSS Power Other P28 VCC Power Other U1 VCC Power Other P29 VSS Power Other U2 VSS Power Other P30 VCC Power Other U3 Power Other P31 VSS
77. Power Ground e 28 26 24 22 30 38 In 4 0 Intel Xeon Processor with 800 MHz System Bus Signal Definitions 4 1 Table 20 Signal Definitions Signal Definitions Sheet 1 of 9 Name Type Description Notes 35 3 A 35 3 Address define 236 physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the front side bus 35 3 are protected by parity signals AP 1 0 A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processors sample a subset of the A 35 3 pins to determine their power on configuration See Section 7 1 A20M If 2 Address 20 Mask is asserted the processor masks physical address bit 20 20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of 20 is only supported in real mode A20Mi is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding write bus transactio
78. Power Other U4 VSS Power Other R1 VCC Power Other U5 Power Other R2 VSS Power Other U6 VSS Power Other R3 VCC Power Other U7 VCC Power Other R4 VSS Power Other U8 VSS Power Other R5 VCC Power Other U9 Power Other R6 VSS Power Other U23 Power Other R7 VCC Power Other U24 VSS Power Other R8 VSS Power Other U25 VCC Power Other R9 VCC Power Other U26 VSS Power Other R23 VCC Power Other U27 VCC Power Other R24 VSS Power Other U28 VSS Power Other R25 VCC Power Other U29 VCC Power Other R26 VSS Power Other 030 VSS Power Other R27 VCC Power Other U31 VCC Power Other R28 VSS Power Other V1 VSS Power Other R29 VCC Power Other V2 Power Other R30 VSS Power Other V3 VSS Power Other R31 VCC Power Other V4 Power Other T1 VSS Power Other V5 VSS Power Other T2 VCC Power Other V6 VCC Power Other T3 VSS Power Other V7 VSS Power Other T4 VCC Power Other V8 Power Other T5 VSS Power Other V9 VSS Power Other T6 VCC Power Other V23 VSS Power Other T7 VSS Power Other V24 VCC Power Other T8 VCC Power Other V25 VSS Power Other 62 Datasheet intel Intel Xeon Processor with 800 MHz System Bus Table 22 Pin Listing by Pin Number Sheet 6 of 8 E Pin Name M Direction Pin Name oa Direction V26 VCC Power Other Y17 DSTBP1 Source Sync I O V27 VSS Power Othe
79. R9 Power Other VCC Y30 Power Other VCC R23 Power Other VCC AA1 Power Other VCC R25 Power Other VCC AA4 Power Other VCC R27 Power Other VCC Power Other R29 Power Other VCC AA20 Power Other VCC R31 Power Other VCC AA26 Power Other VCC T2 Power Other VCC AA31 Power Other VCC T4 Power Other VCC AB2 Power Other VCC T6 Power Other VCC AB8 Power Other VCC T8 Power Other VCC AB14 Power Other VCC T24 Power Other VCC AB18 Power Other VCC T26 Power Other VCC AB24 Power Other VCC T28 Power Other VCC AB30 Power Other VCC T30 Power Other VCC Power Other VCC U1 Power Other VCC 4 Power Other VCC U3 Power Other VCC AC16 Power Other VCC U5 Power Other VCC AC22 Power Other VCC U7 Power Other VCC AC31 Power Other VCC U9 Power Other VCC AD2 Power Other VCC U23 Power Other VCC AD6 Power Other VCC U25 Power Other VCC AD20 Power Other VCC U27 Power Other VCC AD26 Power Other VCC U29 Power Other VCC AD30 Power Other VCC U31 Power Other VCC AE3 Power Other VCC V2 Power Other VCC AE8 Power Other VCC V4 Power Other VCC AE14 Power Other VCC V6 Power Other VCC AE18 Power Other VCC V8 Power Other VCC AE24 Power Other VCC V24 Power Other VCCA AB4 Power Other Input VCC V26 Power Other VCCIOPLL AD4 Power Other Input 54 Datasheet ntel Intel Xeon Processor with 800 MHz System Bus D Table 21 Pin Listing by Pin Name Sheet 6 of 8
80. THI6 Power Other Input AE29 Reserved Reserved Reserved SLP Async GTL Input AE30 N C N C N C NOTE systems using the Intel Xeon processor with 800 MHz system bus the system designer must pull up these signals to the processor VT Datasheet 65 Intel Xeon Processor with 800 MHz System Bus 66 Datasheet intel 6 0 Intel Xeon Processor with 800 MHz System Bus Thermal Specifications 6 1 Note Datasheet Package Thermal Specifications The Intel Xeon processor with 800 MHz system bus requires a thermal solution to maintain temperatures within operating limits Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting For more information on designing a component level thermal solution refer to the Intel Xeon Proce
81. TY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Xeon processor with 800 MHz system bus may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Intel Pentium Intel Xeon SpeedStep and Intel NetBurst are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Intel Extended Memory 64 Technology Intel EM64T requires a computer system with a processor chipset BIOS OS device drivers and applications enabled for
82. The TCC will remain active until the system deasserts FORCEPR GTLREF GTLREF determines the signal reference level for GTL input pins GTLREF is used by the GTL receivers to determine if a signal is a logical 0 or a logical 1 HIT HITM HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any front side bus agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting and HITM together Since multiple agents may deliver snoop results at the same time HIT and HITM are wired OR signals which must connect the appropriate pins of all processor front side bus agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers HIT and HITM are activated on specific clock edges and sampled on specific clock edges IERR IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor front side bus This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not have on die termination and must be terminated at the end agent IGNNE IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric e
83. able 15 Table 9 through Table 15 list the DC specifications for the processor and are valid only while meeting specifications for case temperature as specified in Section 6 0 clock frequency and input voltages Care should be taken to read all notes associated with each parameter Flexible Motherboard Guidelines FMB The Flexible Motherboard FMB guidelines are estimates of the maximum values the Intel amp Xeon processor with 800 MHz system bus will have over certain time periods The values are only estimates and actual specifications for future processors may differ Processors may or may not have specifications equal to the FMB value in the foreseeable future System designers should meet the FMB values to ensure their systems will be compatible with future Intel Xeon processor with 800 MHz system bus Datasheet n Intel Xeon Processor with 800 MHz System Bus Table 9 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes VID range VID range for Intel Xeon 1 2875 1 4000 V 2 8 processor with 800 MHz system bus Voc Voc for Intel Xeon processor See Table 10 and VID max 1 25 V 3 4 5 6 7 with 800 MHz system bus FMB Figure 4 processor VID VID step size during a transition 212 5 mV 8 Transition Total allowable DC load line shift 450 mV 9 from VID steps VIT Front Side Bus termination voltage 1 176 1 20 1 224 V 1
84. arkings Example 36 11 Processor Pinout Coordinates Top nennen 37 12 Processor Pinout Coordinates Bottom View 38 13 Intel Xeon Processor with 800 MHz System Bus Thermal Profiles A and B 69 14 Case Temperature TCASE Measurement Location essen 71 15 Stop Clock State 76 16 1U Passive Hoeatsink occid ls 79 17 20 Passive eene nnne ntes nnn resin nns rennen nennen nns 80 18 Active Heatsink 3 and 4 Pin representation 2202 2 00 80 19 Passive Intel Xeon Processor with 800 MHz System Bus Thermal Solution 2U and larger nitet ee e de Leva ea ee CE 81 20 Side Board Keepout Zones Part 1 eene 82 21 Side Board Keepout Zones Part 2 nennen 83 22 Bottom Side Board Keepout 7 84 23 Board Mounting Hole Keepout 2 85 24 Volumetric Height 86 25 4 Pin Fan Cable Connector for active heatsink 87 26 4 Baseboard Fan Header for active heatsink
85. asheet Power and Ground Pins For clean on chip power distribution the processor has 181 power and 185 Vs ground inputs pins must be connected to the processor power plane while all Vss pins must be connected to the system ground plane The processor pins must be supplied with the voltage determined by the processor Voltage IDentification VID pins Eleven signals are denoted as which provide termination for the front side bus and power to the I O buffers The platform must implement a separate supply for these pins which meets the specifications outlined in Table 9 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the Intel Xeon processor with 800 MHz system bus is capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cau such as electrolytic or aluminum polymer capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 9 Failure to do so can result in timing
86. ates that the processor Thermal Control Circuit TCC has been activated if enabled See Section 6 2 3 for more details PWRGOOD PWRGOOD Power Good is an input The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 15 and be followed by a 1 10 ms RESET pulse The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation 44 Datasheet intel Table 20 Intel Xeon Processor with 800 MHz System Bus Signal Definitions Sheet 7 of 9 Name Type Description Notes 4 0 y o REQ 4 0 Request Command must connect the appropriate pins of all processor front side bus agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 1 0 Re
87. ature 40 85 3 4 NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no pins can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any tray or packaging Processor DC Specifications processor DC specifications in this section are defined at the processor core pads unless noted otherwise See Section 5 1 for the Intel amp Xeon M processor with 800 MHz system bus pin listings and Section 4 1 for signal definitions Voltage and current specifications are detailed in Table 9 For platform power delivery planning refer to Table 10 which provides static and transient tolerances This same information is presented graphically in Figure 4 BSEL 1 0 and VID 5 0 signals are specified in Table 12 The DC specifications for signals are listed in Table 13 The DC specifications for the PWRGOOD input and TAP signal group are listed in Table 14 and the Asynchronous GTL signal group is listed in T
88. ble for the VTT regulator in the event an incompatible processor is inserted into the platform There is no connection to the processor silicon for this signal and it must be pulled up through a resistor NOTES 1 The Intel Xeon processor with 800 MHz system bus only supports BRO and BR1 However platforms must terminate BR2 and BR3 to V 2 For this pin on Intel Xeon processor with 800 MHz system bus the maximum number of symmetric agents is one Maximum number of central agents is zero 3 For this pin on Intel Xeon processor with 800 MHz system bus the maximum number of symmetric agents is two Maximum number of central agents is zero 4 For this pin on Intel Xeon processor with 800 MHz system bus the maximum number of symmetric agents is two Maximum number of central agents is one Datasheet 47 Intel Xeon Processor with 800 MHz System Bus 48 Datasheet Intel Xeon Processor with 800 MHz System Bus Pin List 5 1 Datasheet Intel Xeon Processor with 800 MHz System Bus Pin Assignments This section provides sorted pin lists in Table 21 and Table 22 Table 21 is a listing of all processor pins ordered alphabetically by pin name Table 22 is a listing of all processor pins ordered by pin number 49 Intel Xeon Processor with 800 MHz System Bus
89. by the PLL clock generators on the Intel Xeon processor with 800 MHz system bus Since these PLLs are analog in nature they require quiet power supplies for minimum jitter Jitter is detrimental to the system it degrades external I O timings as well as internal core timings i e maximum frequency To prevent this degradation these supplies must be low pass filtered from The AC low pass requirements are as follows e 02 dB gain in pass band e 0 5 dB attenuation in pass band lt 1 Hz e gt 34 dB attenuation from 1 MHz to 66 MHz 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 1 Phase Lock Loop PLL Filter Requirements 0 2 dB 0 dB xdB 28 dB 34 dB DC 1Hz fpeak 1 MHz 66 MHz fcore 1 67 GHz lt lt gt 50 kHz 500 MHz High Passband Frequency 500141 NOTES 1 Diagram not to scale 2 No specifications for frequencies beyond core frequency if existent should be less than 0 05 MHz 4 foore represents the maximum core frequency supported by the platform Voltage Identification VID The Voltage Identification VID specification for the Intel Xeon processor with 800 MHz system bus is defined by the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines and Voltage Regulator Module VRM and Enterprise Voltage Regulator Down
90. ct which processor is present and then select the appropriate Tcontrol base value When Tdiode is above Tcontrol then must be at or below as defined by the thermal profile For Intel Xeon processor with 800 MHz system bus see Figure 13 Table 24 and Table 25 Otherwise the processor temperature can be maintained at Tcontrol Thermal Diode The processor incorporates an on die thermal diode A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management long term die temperature change purposes Table 26 and Table 27 provide the diode parameter and interface specifications This thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor Thermal Diode Parameters Symbol Symbol Min Typ Max Unit Notes lew Forward Bias Current 11 187 1 n Diode ideality factor 1 0083 1 011 1 0183 2 9 4 Series Resistance 3 242 3 33 3 594 Ww 2 3 5 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Characterized at 75 C 73 Intel Xeon Processor with 800 MHz System Bus n Table 27 74 3 Not 100 tested Specified by design characterization 4 The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode n equation Igw 15 e 1 Where
91. des PRDY Probe Ready functionality for the port PRDY isa processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the port PREQ is used by debug tools to request debug operation of the processors BPM 5 4 must be bussed to all bus agents These signals do not have on die termination and must be terminated at the end agent BPRI BPRI Bus Priority Request is used to arbitrate for ownership of the processor front side bus It must connect the appropriate pins of all processor front side bus agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI 40 Datasheet Intel Xeon Processor with 800 MHz System Bus intel Table 20 Signal Definitions Sheet 3 of 9 Name Type Description Notes BRO BR 3 0 Bus Request drive the BREQ 3 0 signals the system The BREQ 3 0 1 4 BR 1 3 4 signals are interconnected in a rotating manner to individual processor pins The tables below provide the rotating interconnect between the processor and bus signals for 2 way systems BR 1 0 Signals Rotating Interconnect 2 way sys Bus Signal Agent 0 Pins
92. e Sync I O B14 12 Source Sync A8 VCC Power Other B15 VSS Power Other A9 26 Source Sync B16 A114 Source Sync A10 20 Source Sync 17 VSS Power Other A11 VSS Power Other B18 Abit Source Sync A12 14 Source Sync I O B19 REQO Source Sync I O A13 A10 Source Sync I O B20 Power Other A14 VCC Power Other B21 REQ1 Source Sync I O A15 FORCEPR Async GTL Input B22 REQ4 Source Sync I O A16 TEST_BUS Power Other I O B23 VSS Power Other A17 LOCK Common Clk I O B24 LINTO INTR Async GTL Input A18 VCC Power Other B25 PROCHOT Power Other Output A19 A7 Source Sync I O B26 Power Other A20 4 Source Sync B27 VCCSENSE Power Other Output A21 VSS Power Other B28 VSS Power Other A22 Source Sync 29 Power Other A23 HITM Common Clk I O B30 VSS Power Other A24 VCC Power Other B31 VCC Power Other A25 TMS TAP Input C1 OPTIMIZED COMPAT Power Other Input A26 Reserved Reserved Reserved C2 VCC Power Other A27 VSS Power Other C3 VID3 Power Other Output A28 VCC Power Other C4 Power Other A29 VSS Power Other C5 VTT Power Other A30 VCC Power Other C6 RSP Common Input A31 VSS Power Other C7 VSS Power Other B1 VIDPWRGD Power Other Input C8 A35 Source Sync I O B2 VSS Power Other C9 A34 Source Sync I O B3 VID4 Power Other Output C10 VTT Power Other B4 VTT Power Other C11 A30 Source Sync I O B5 OTDEN Power Other Input C12 A23 S
93. e quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to strobes and DBI DSTBN DSTBP Data Group D 15 0 0 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DBI pins determine the polarity of the data signals Each group of 16 data signals corresponds to DBI signal When the signal is active the corresponding data group is inverted and therefore sampled active high Datasheet 41 Intel Xeon Processor with 800 MHz System Bus Table 20 Signal Definitions Sheet 4 of 9 Name Type Description Notes DBI 3 0 Vo DBI 3 0 are source synchronous and indicate the polarity of the D 63 0 signals The 4 DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electronically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DBIO D 15 0 DBI1 D 31 16 DBI2 D 47 32 DBI3
94. el Mixing Processors Intel only supports and validates dual processor configurations in which both Intel Xeon processor with 800 MHz system bus operate with the same front side bus frequency core frequency and have the same internal cache sizes Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel Note Processors within a system must operate at the same frequency per bits 15 8 of the IA 32 FLEX BRVID SEL MSR however this does not apply to frequency transitions initiated due to thermal events Demand Based Switching DBS with Enhanced Intel SpeedStep Technology transitions or assertion of the FORCEPR signal See Section 6 0 Not all operating systems support dual processors with mixed frequencies Intel does not support or validate operation of processors with different cache sizes Mixing processors of different steppings but the same model as per CPUID instruction is supported Please see the Intel Xeon Processor with 800 MHz System Bus Specification Update for the applicable mixed stepping table Details regarding the CPUID instruction are provided in the Intel Processor Identification and the CPUID Instruction application note Absolute Maximum and Minimum Ratings Table 8 specifies absolute maximum and minimum ratings Within functional operation limits functionality and long term reliability can be expected At conditions outside functiona
95. em bus based system that can make use of an LAI mechanical and electrical 95 Intel Xeon Processor with 800 MHz System Bus ntel 9 3 1 9 3 2 96 Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI pins plug into the socket while the processor pins plug into a socket on the LAI Cabling that is part of the LAT egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may include different requirements from the space normally occupied by the heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the front side bus therefore it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide Datasheet
96. ence A M 32 Intel Architecture Software Developer s Manual Volume 2B Instruction Set 253667 Reference N Z 32 Intel Architecture Software Developer s Manual Volume 3 System Programming 253668 Guide ITP700 Debug Port Design Guide 249679 Intel Xeon Processor with 800 MHz System Bus Specification Update 302402 Intel Xeon Processor with 800 MHz System Bus Core Boundary Scan Descriptive 302403 Language BSDL Model V1 0 and Cell Descriptor File V1 0 Intel Xeon Processor with 800 MHz System Bus Thermal Models zip file Intel Xeon Processor with 800 MHz System Bus Mechanical Models IGES zip file Intel Xeon Processor with 800 MHz System Bus Mechanical Models zip file Intel Xeon Processor with 800 MHz System Bus Thermal Mechanical Design Guide 302404 Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 302731 Design Guidelines Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 1 302732 Design Guidelines NOTE Contact your Intel representative for the latest revision of documents without document numbers State of Data The data contained within this document is subject to change It is the most accurate information available by the publication date of this document Datasheet intel 2 0 Intel Xeon Processor with 800 MHz System Bus Electrical Specifications 2 1 2 2 2 2 1 2 2 2 2 2 3 Dat
97. er VSS U24 Power Other VSS N4 Power Other VSS U26 Power Other VSS N6 Power Other VSS U28 Power Other VSS N8 Power Other VSS U30 Power Other VSS N24 Power Other VSS V1 Power Other VSS N26 Power Other VSS V3 Power Other VSS N28 Power Other VSS V5 Power Other VSS N30 Power Other VSS V7 Power Other VSS P1 Power Other VSS v9 Power Other VSS P3 Power Other VSS V23 Power Other VSS P5 Power Other VSS V25 Power Other VSS P7 Power Other VSS V27 Power Other VSS P9 Power Other VSS V29 Power Other VSS P23 Power Other VSS V31 Power Other VSS P25 Power Other VSS W2 Power Other VSS P27 Power Other VSS W4 Power Other VSS P29 Power Other VSS W24 Power Other VSS P31 Power Other VSS W26 Power Other VSS R2 Power Other VSS W28 Power Other VSS R4 Power Other VSS W30 Power Other 56 Datasheet ntel Intel Xeon Processor with 800 MHz System Bus D Table 21 Pin Listing by Pin Name Sheet 8 of 8 Pin Name E Direction Pin Name d Direction VSS Y1 Power Other VSS AD3 Power Other VSS Y5 Power Other VSS AD9 Power Other VSS Y7 Power Other VSS AD15 Power Other VSS Y13 Power Other VSS AD17 Power Other VSS Y19 Power Other VSS AD23 Power Other VSS Y25 Power Other VSS AD31 Power Other VSS Y31 Power Other VSS AE2 Power Other VSS AA2 Power Other VSS 11 Power Other VSS AA9 Power Other VSS AE21 Power Other VSS AA15 Power Other VSS AE27 Power Other VSS AA17
98. es on either end of the daisy chained front side bus interface while a middle agent is any bus agent in between the two end agents For end agents most unused inputs should be left as no connects as AGTL termination is provided on the processor silicon However see Table 6 for details on AGTL signals that do not include on die termination For middle agents the on die termination must be disabled so the platform must ensure that unused input signals which do not connect to end agents are connected to via a pull up resistor Unused active high inputs should be connected through a resistor to ground Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 2096 of the impedance of the baseboard trace for front side bus signals For unused input or I O signals use pull up resistors of the same value as the on die termination resistors 17 Intel Xeon Processor with 800 MHz System Bus ntel 2 6 Asynchronous GTL inputs and Asynchronous outputs do not include on die termination Inputs and utilized outputs must be terminated on the baseboard Unused outputs may be
99. f NA 288 0 45 kg 100 G N 1 3 5 6 7 NA 65 Ibf static 1 Ibm 100 G lbf Transient NA 445 N 1 3 8 100 lbf NOTES 1 These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 This specification applies for thermal retention solutions that allow baseboard deflection 5 This specification applies either for thermal retention solutions that prevent baseboard deflection or for the Intel enabled reference solution CEK 6 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement 7 Experimentally validated test condition used a heatsink mass of 1 Ibm 0 45 kg with 100 G acceleration measured at heatsink mass The dynamic portion of this specification in the product application can have flexibility in specific values but the ultimate product of mass times acceleration should not exceed this validated dynamic load 1 Ibm x 100 G 100 Ib Allowable strain in the dynamic compressive load specification is in addition to the strain allowed in static loading 8 Transient loading is defined a
100. fer to the AP 1 0 signal description for details on parity checking of these signals RESET Asserting the RESET signal resets all processors to known states and invalidates their internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least 1 ms after Vcc and BCLK have reached their proper specifications On observing active RESET all front side bus agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 7 1 This signal does not have on die termination and must be terminated at the end agent RS 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor front side bus agents RSP RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of all processor front side bus agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS
101. for details on system thermal solution design thermal profiles and environmental considerations The upper point of the thermal profile consists of the Thermal Design Power TDP defined in Table 23 and the associated Tc Asp value It should be noted that the upper point associated with Thermal Profile B x and y TDP represents a thermal solution design point In actuality the processor case temperature will never reach this value due to TCC activation see Figure 23 The lower point of the thermal profile consists of x BASE and y TcAsE BASE Pcontrol is defined as the processor power at which Tcasp calculated from the thermal profile corresponds to the lowest possible value of Tcontrol This point is associated with the Tcontrol value see Section 6 2 6 However because Tcontrol represents a diode temperature it is necessary to define the associated case temperature This is Tcasp max PCONTROL_BASE Please see Section 6 2 6 and the appropriate thermal mechanical design guide for proper usage of the Tcontrol specification The case temperature is defined at the geometric top center of the processor IHS Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 23 ins
102. hermal profile 2 Implementation of Thermal Profile A should result in virtually no TCC activation Furthermore usage of thermal solutions that do not meet processor Thermal Profile A will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Thermal Profile B is representative of a volumetrically constrained platform Please refer to Table 25 for discrete points that constitute the thermal profile 4 Implementation of Thermal Profile B will result in increased probability of TCC activation and may incur measurable performance loss Furthermore usage of thermal solutions that do not meet Thermal Profile B do not meet the processor s thermal specifications and may result in permanent damage to the processor 5 Refer to the Intel Xeon Processor with 800 MHz System Bus Thermal Mechanical Design Guidelines for system and environmental implementation details Datasheet 69 Intel Xeon Processor with 800 MHz System Bus ntel Table 24 Intel Xeon Processor with 800 MHz System Bus Thermal Profile A Power W Tease C Power W Tease PcoNrRoL A 25 50 e 61 26 50 68 62 28 51 30 51 32 52 34 53 36 53 38 54 2 eoo d 40 54 82 66 42 55 44 55 Hu 50 2 46 56 88 68 48 56 90 6 50 57 92 46 52 58 oa 69 54 58 96 7
103. ications 2 The Vcc min loadlines are plots of the discrete point found in Table 10 3 Refer to Table 9 for processor VID information 4 The loadlines specify voltage limits at the die measured at the VCCSENSE and VSSSENSE pins Voltage regulation feedback for voltage regulator circuits must be taken from processor Vcc and Vss pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines and Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 1 Design Guidelines for socket loadline guidelines and VR implementation 2 11 2 Table 11 Datasheet Vcc Overshoot Specification The Intel Xeon processor with 800 MHz system bus can tolerate short transient overshoot events where exceeds the VID voltage when transitioning from high to low current load condition This overshoot cannot exceed VID Vos max Vos is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCCSENSE and VSSSENSE pins Vcc Overshoot Specifications Symbol Parameter Min Max Units Figure Notes Vos MAX Magnitude of Voc 0 050 V 5 overshoot above VID Tos Time duration of Voc 25 us 5 overshoot above VID 27 Intel Xeon Processor with 800 MHz System Bus Figure 5 2 11 3 Table 12 28 Overshoot Example Waveform
104. ignal can be driven when the processor is Stop Grant state PBE will be asserted if there is any pending interrupt latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that it should return the processor to the Normal state HALT Snoop State or Snoop State The processor will respond to snoop or interrupt transactions on the front side bus while in Stop Grant state or in HALT Power Down state During a snoop or interrupt transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus or the interrupt has been latched After the snoop is serviced or the interrupt is latched the processor will return to the Stop Grant state or HALT Power Down state as appropriate Sleep State The Sleep state is a very low power state in which each processor maintains its context maintains the phase locked loop PLL and has stopped most of internal clocks The Sleep state can only be entered from Stop Grant state Once in the Stop Grant state the processor will enter the Sleep state upon the assertion of the SLP signal The SLP pin has a minimum assertion of one BCLK period The SLP pin should only be asserted when the processor is in the state For Intel Xeon processor
105. iven simultaneously by multiple agents wired OR Datasheet 19 Intel Xeon Processor with 800 MHz System Bus Table 6 Table 7 2 7 20 intel Table 6 outlines the signals which include on die termination and lists signals which include additional on die resistance O pen drain signals are also included Table 7 provides signal reference voltages Signal Description Table Signals with Signals with No 35 3 ADS ADSTB 1 0 1 0 BINIT BOOT SELECT BPRI D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FORCEPR HIT HITM LOCK MCERR OPTIMIZED COMPAT 2 REQ 4 0 RS 2 0 RSP SLEW_CTRL TEST_BUS TRDY A20M BCLK 1 0 BPM 5 0 BR 3 0 BSEL 1 0 COMP 1 0 FERR PBE GTLREF 3 0 IERR IGNNE INIT LINTO INTR LINT1 NMI ODTEN PROCHOT PWRGOOD RESET SKTOCC SLP STPCLK TDI TESTHI 6 0 THERMTRIP TMS TRST VID 5 0 VIDPWRGD VTTEN Signals with RL Signals with No R BINIT BNR HIT HITM MCERR A20M A 35 3 ADS ADSTB 1 0 amp AP 1 0 BCLK 1 0 BPM 5 0 BPRI BR 3 0 BSEL 1 0 SELECT 0 D 63 0 DBI 3 0 DBSY DEFER 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FERR PBE FORCEPR GTLREF 3 0 IERR IGNNE INIT LINTO INTR LINT1 NMI LOCK ODTEN OPTIMIZED CO
106. l Systems that implement fan speed control must be designed to take these conditions into account Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications Intel has developed two thermal profiles either of which can be implemented with the Intel Xeon processor with 800 MHz system bus Both ensure adherence to Intel reliability requirements Thermal Profile A see Figure 23 Table 24 is representative of a volumetrically unconstrained thermal solution i e industry enabled 2U heatsink In this scenario it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Thermal Profile B see Figure 23 Table 25 is indicative of a constrained thermal environment i e 1U Because of the reduced cooling capability represented by this thermal solution the probability of TCC activation and performance loss is increased Additionally usage of a thermal solution that does not meet Thermal Profile B 67 Intel Xeon Processor with 800 MHz System Bus n Table 23 68 will violate the thermal specifications and may result in permanent damage to the processor Intel has developed these thermal profiles to allow to choose the thermal solution and environmental parameters that best suit their platform implementation Refer to the appropriate thermal mechanical design guide
107. l operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits 21 Intel Xeon Processor with 800 MHz System Bus Table 8 2 11 2 11 1 22 intel At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes Voc Core voltage with respect to Vss 0 30 1 55 V Vit System bus termination voltage with 0 30 1 55 V respect to Vss TCASE Processor case temperature See Section See Section C 6 0 6 0 TsrORAGE Storage temper
108. ling Requirements eese 92 8 5 Boxed Processor 93 Debug Tools Specifications 95 9 1 Debug Port System Requirements 95 9 2 Target System nennen nennen enne 95 9 2 1 System 95 9 3 Logic Analyzer Interface 95 9 3 1 Mechanical 96 9 3 2 Electrical Considerations 96 Datasheet ntel Intel Xeon Processor with 800 MHz System Bus D Figures 1 Phase Lock Loop PLL Filter Requirements emm 15 2 1 Xeon Processor with 800 MHz System Bus Load Current vs Time 10 0 25 3 Intel Xeon Processor with 800 MHz System Bus Load Current vs Time VRM 10 1 25 4 VCC Static and Transient 27 5 Overshoot Example nennen 28 6 Processor Package Assembly 31 7 Processor Package Drawing Sheet 1 32 8 Processor Package Drawing Sheet 2 2 33 9 Processor Top Side Markings 36 10 Processor Bottom Side M
109. mo lt m gt lt lt lt lt lt oOOOOO0l eeoeooceocoecocioecooeo eoeeocleeeoeooceoeocicoee ecco 9 9 OeooOecsjeeeceoccecececceocoeoc ooeo 8 eooeo ooeooe oeooe ooeoo eooeoo 00000 Sor ooeooe oeooe onz oeooeo eoeoo x ot 000009 00000 92005 000000 0090 9 ooeooe o00e 00 eooeoo oeooe oeooeo eooeo ooeooe ooeoo 6 0 0 090000000000000000 00000 e 0000600600006000000060 0000090 monoulil gr x zzuamrkto 2 z azcmonu lt lt lt lt lt SSA 99A Intel Xeon Processor with 800 MHz System Bus Figure 12 Datasheet CLOCKS 10 12 Reserved No Connect GTLREF 14 e 16 DATA 20 18 Signal
110. n ADS ADS Address Strobe is asserted to indicate the validity of the transaction address the A 35 3 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must connect the appropriate pins on all Intel Xeon processor with 800 MHz system bus agents ADSTB 1 0 amp y o Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edge Strobes are associated with signals as shown below Signals Associated Strobes REQ 4 0 A 16 3 ADSTBO 35 17 ADSTB1 AP 1 0 yo AP 1 0 Address Parity are driven by the request initiator along with ADS A 35 3 and the transaction type the REQ 4 0 pins A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins of all Intel Xeon processor with 800 MHz system bus agents The following table defines the coverage model of these signals Request Signals Subphase 1 Subphase 2 35 24 1 23 3 1 BCLK 1 0 The differential bus clock pair BCLK 1 0 determines the front side bus frequency
111. nes for further details The processor is capable of drawing indefinitely Refer to Figure 2 and Figure for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested 19 This specification refers to platforms implementing a power delivery system that complies with VR 10 0 guidelines Please see the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 0 Design Guidelines for further details 20 This specification refers to platforms implementing a power delivery system that complies with VR 10 1 guidelines Please see the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 1 Design Guidelines for further details 24 Datasheet n Intel Xeon Processor with 800 MHz System Bus Figure 2 Intel Xeon Processor with 800 MHz System Bus Load Current vs Time VRM 10 0 10 0 Current 105 100 lt 95 5 o 8 o 85 80 0 01 0 1 1 10 100 1000 Time Duration s NOTES 1 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than TDC 2 Not 100 tested Specified by design characterization Figure 3 Intel Xeon Processor with 800 MHz System Bus Load Current vs Time VRM 10 1 10 1 Current 125 120 Sustained Current A
112. not be interpreted as an indication of processor case temperature This temperature delta accounts for processor package lifetime and manufacturing variations and attempts to ensure the Thermal Control Circuit is not activated below maximum when dissipating TDP power There is no defined or fixed correlation between the trip temperature the case temperature or the thermal diode temperature Thermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of Tease PROCHOT or Tdiode on random processor samples FORCEPR Signal Pin The FORCEPR force power reduction input be used by the platform to cause the Intel Xeon processor with 800 MHz system bus to activate the TCC If the Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal The TCC will remain active until the system deasserts FORCEPR FORCEPR is an asynchronous input Datasheet 6 2 5 6 2 6 6 2 7 Table 26 Datasheet Intel Xeon Processor with 800 MHz System Bus FORCEPR can be used to thermally protect other system components To use the VR as an example when the FORCEPR pin is asserted the TCC circuit in the processor will activate reducing the current consumption of the processor and the corresponding temperature of the VR If should be noted that assertion of FORCEPR does not automatically assert
113. ogy Intel Xeon processor with 800 MHz system bus adds support Demand Based Switching DBS with Enhanced Intel SpeedStep Technology This technology enables power management for the processor Not all Intel Xeon processors are capable of supporting Demand Based Switching DBS with Enhanced Intel SpeedStep Technology More details on which processor frequencies will support this feature will be provided in future releases of the Intel Xeon Processor with 800 MHz System Bus Specification Update when available Demand Based Switching DBS with Enhanced Intel SpeedStep Technology is a technology that creates processor performance states P states P states are power consumption and capability states within the Normal state as shown in Figure 15 Demand Based Switching DBS with Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system Note that the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The key features that differentiate Demand Based Switching DBS with Enhanced Intel SpeedStep Technology
114. ons 30 16 VIDPWRGD DC Specifications 30 17 Processor Loading 34 18 Package Handling Guidelines 35 19 Processor Materials 35 20 Signal Definitions cente 39 21 Pin Listing by Pin 2 2 25 2 creer iie peste sanas ped etica a 50 22 Pin Listing by Pin Number etie E 58 23 Intel Xeon Processor with 800 MHz System Bus Thermal Specifications 68 24 Intel Xeon Processor with 800 MHz System Bus Thermal Profile 70 25 Intel Xeon Processor with 800 MHz System Bus Thermal Profile 70 26 Thermal Diode Parameters 73 27 Thermal Diode 74 28 Power On Configuration Option PINS 75 29 PWM Fan Frequency Specifications 4 pin active 90 30 Fan Specifications 3 and 4 pin active 4440 00 90 31 Fan Cable Connector Pinout 3 pin active heatsink 91 32 Fan Cable Connector Pinout 4 pin active
115. ource Sync I O B6 VCC Power Other C13 VSS Power Other B7 A311 Source Sync C14 16 Source Sync 58 Datasheet intel Intel Xeon Processor with 800 MHz System Bus Table 22 Pin Listing by Pin Number Sheet 2 of 8 d Pin Name Direction ADD Direction C15 A15 Source Sync I O D24 VCC Power Other C16 VCC Power Other D25 Reserved Reserved Reserved C17 8 Source Sync 026 VSSSENSE Power Other Output C18 Source Sync 027 VSS Power Other C19 VSS Power Other D28 VSS Power Other C20 REQ3 Source Sync I O D29 Power Other C21 REQ2 Source Sync I O D30 VSS Power Other C22 VCC Power Other D31 Power Other C23 DEFER Common Clk Input E1 VTTEN Power Other Output C24 TDI TAP Input E2 VCC Power Other C25 VSS Power Other E3 VID1 Power Other Output C26 IGNNE Async GTL Input E4 BPM5 Common Clk I O C27 SMI Async GTL Input E5 IERR Async GTL Output C28 VCC Power Other E6 VCC Power Other C29 VSS Power Other E7 BPM2 Common Clk C30 VCC Power Other E8 BPM4 Clk C31 VSS Power Other E9 VSS Power Other D1 VCC Power Other E10 Common Clk D2 VSS Power Other E11 BR2 Common Input D3 VID2 Power Other Output E12 VTT Power Other D4 STPCLK Async GTL Input E13 A28
116. ource and must not be connected to This specification is measured at the pin 11 Baseboard bandwidth is limited to 20 MHz 12 This specification refers to a single processor with enabled Please note the end agent and middle agent may not require simultaneously This parameter is based on design characterization and not tested 13 This specification refers to a single processor with disabled Please note the end agent and middle agent may not require Irr max simultaneously Details will be provided in future revisions of this document 14 These specifications apply to the PLL power pins VCCA VCCIOPLL and VSSA See Section 2 3 2 for details These parameters are based on design characterization and are not tested 15 This specification represents a total current for all GTLREF pins 16 The current specified is also for HALT State 17 The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of the PROCHOT signal is the maximum for the processor 18 Thermal Design Current is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please see the applicable design guideli
117. ower Other 64 Datasheet intel Intel Xeon Processor with 800 MHz System Bus Table 22 Pin Listing by Pin Number Sheet 8 of 8 E Pin Name Direction Pin Name Direction AD13 038 Source Sync AE7 D58 Source Sync I O AD14 D39 Source Sync AE8 Power Other AD15 VSS Power Other AE9 D44 Source Sync I O AD16 COMPO Power Other Input AE10 D42 Source Sync I O AD17 VSS Power Other AE11 VSS Power Other AD18 D36 Source Sync I O AE12 DBI2 Source Sync I O AD19 D30 Source Sync I O AE13 D35 Source Sync I O AD20 VCC Power Other AE14 VCC Power Other AD21 D29 Source Sync AE15 Reserved Reserved Reserved AD22 DBI1 Source Sync AE16 Reserved Reserved Reserved AD23 VSS Power Other AE17 DP3 Common Clk I O AD24 D21 Source Sync I O AE18 VCC Power Other AD25 D18 Source Sync I O AE19 DP1 Common Clk I O AD26 VCC Power Other AE20 D28 Source Sync I O AD27 D4 Source Sync I O AE21 VSS Power Other AD28 N C N C N C AE22 D27 Source Sync I O AD29 N C N C N C AE23 022 Source Sync I O AD30 VCC Power Other AE24 VCC Power Other AD31 VSS Power Other AE25 D19 Source Sync I O AE2 VSS Power Other AE26 D16 Source Sync I O AE3 VCC Power Other AE27 VSS Power Other AE4 SMB_PRT Power Other Output AE28 Reserved Reserved Reserved AE5 TES
118. ower Other G8 VCC Power Other J25 VSS Power Other G9 VSS Power Other J26 Power Other G23 LINT 1 NMI Async GTL Input J27 VSS Power Other 60 Datasheet ntel Intel Xeon Processor with 800 MHz System Bus D Table 22 Pin Listing by Pin Number Sheet 4 of 8 E Pin Name Direction Direction J28 VCC Power Other M1 Power Other J29 VSS Power Other M2 VSS Power Other J30 VCC Power Other M3 VCC Power Other J31 VSS Power Other M4 VSS Power Other K1 VCC Power Other M5 VCC Power Other K2 VSS Power Other M6 VSS Power Other K3 VCC Power Other M7 VCC Power Other K4 VSS Power Other M8 VSS Power Other K5 VCC Power Other M9 VCC Power Other K6 VSS Power Other M23 VCC Power Other K7 VCC Power Other M24 VSS Power Other K8 VSS Power Other M25 Power Other K9 VCC Power Other M26 VSS Power Other K23 VCC Power Other M27 VCC Power Other K24 VSS Power Other M28 VSS Power Other K25 VCC Power Other M29 VCC Power Other K26 VSS Power Other M30 VSS Power Other K27 VCC Power Other M31 Power Other K28 VSS Power Other N1 Power Other K29 VCC Power Other N2 VSS Power Other K30 VSS Power Other N3 VCC Power Other K31 VCC Power Other N4 VSS Power Other L1 VSS Power Other N5 VCC Power Other L2 VCC Power Other N6 VSS Power Other L3 VSS Power Other N7 VCC Power Other L4 VCC Power
119. r Clocking BCLKT 1 0 directly controls the front side bus interface speed as well as the core frequency of the processor As in previous processor generations the Intel Xeon processor with 800 MHz system bus core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier will be set during manufacturing The default setting will be the maximum speed for the processor It will be possible to override this setting using software This will permit operation at a speed lower than the processor s tested frequency The BCLK 1 0 inputs directly control the operating speed of the front side bus interface The processor core frequency is configured during reset by using values stored internally during manufacturing The stored value sets the highest bus fraction at which the particular processor can operate If lower speeds are desired the appropriate ratio can be configured by setting bits 15 8 of the IA 32 FLEX BRVID SEL MSR Clock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK 1 0 input with exceptions for spread spectrum clocking The Intel Xeon processor with 800 MHz system bus uses differential clocks Details regarding BCLK 1 0 driver specifications are provided in CK409 Clock Synthesizer Driver Design Guidelines or CK409B Clock Synthesizer Driver Design Guidelines Table 2 contains core frequency to front side bus multiplier
120. r Other H3 Power Other VCC M23 Power Other 5 Power Other VCC M25 Power Other H7 Power Other VCC M27 Power Other H9 Power Other VCC M29 Power Other H23 Power Other VCC M31 Power Other 25 Power Other VCC N1 Power Other 27 Power Other VCC N3 Power Other 29 Power Other VCC N5 Power Other H31 Power Other VCC N7 Power Other 42 Power Other VCC N9 Power Other 94 Power Other VCC N23 Power Other VCC J6 Power Other VCC N25 Power Other VCC J8 Power Other VCC N27 Power Other 424 Power Other VCC N29 Power Other VCC J26 Power Other VCC N31 Power Other VCC J28 Power Other VCC P2 Power Other VCC J30 Power Other VCC P4 Power Other Datasheet 53 Intel Xeon Processor with 800 MHz System Bus Table 21 Pin Listing by Pin Name Sheet 5 of 8 Pin Name ih MS Direction Pin Name sak Direction VCC P6 Power Other VCC V28 Power Other P8 Power Other V30 Power Other 24 Power Other W1 Power Other P26 Power Other W25 Power Other 28 Power Other VCC W27 Power Other VCC P30 Power Other VCC W29 Power Other VCC R1 Power Other VCC w31 Power Other VCC R3 Power Other VCC Y2 Power Other VCC R5 Power Other VCC Y16 Power Other VCC R7 Power Other VCC Y22 Power Other VCC
121. r Y18 DSTBN1 Source Sync I O V28 VCC Power Other Y19 VSS Power Other V29 VSS Power Other Y20 DSTBPO Source Sync I O V30 VCC Power Other Y21 DSTBNO Source Sync V31 VSS Power Other Y22 Power Other W1 VCC Power Other Y23 D5 Source Sync I O W2 VSS Power Other Y24 D2 Source Sync I O W3 Reserved Reserved Reserved Y25 VSS Power Other W4 VSS Power Other Y26 00 Source Sync I O W5 BCLK1 Sys Bus Input Y27 THERMDA Power Other Output W6 TESTHIO Power Other Input Y28 THERMDC Power Other Output W7 TESTHI1 Power Other Input Y29 N C N C N C W8 TESTHI2 Power Other Input Power Other W9 GTLREF Power Other Input Y31 VSS Power Other W23 GTLREF Power Other Input AA1 Power Other W24 VSS Power Other AA2 VSS Power Other W25 VCC Power Other AA3 BSELO Power Other Output W26 55 Power Other 4 Power Other W27 VCC Power Other 5 VSSA Power Other Input W28 VSS Power Other AA6 Power Other W29 VCC Power Other TESTHI4 Power Other Input W30 VSS Power Other AA8 D61 Source Sync I O W31 VCC Power Other AA9 VSS Power Other Y1 VSS Power Other 10 D54 Source Sync Y2 VCC Power Other AA11 D53 Source Sync Reserved Reserved Reserved AA12 VIT Power Other Y4 BCLKO Sys Bus Input AA13 D48 Source Sync I O Y5 VSS Power Other AA14 D49 Source Sync I O Y6 TESTHI3 Power Other Input AA15 VSS Power Other Y7 VSS Power Other AA16 D33 So
122. red for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the A 32 Software Developer s Manual Volume 3 System Programming Guide Since multiple agents may drive this signal at the same time MCERR is a wired OR signal which must connect the appropriate pins of all processor front side bus agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers is activated on specific clock edges and sampled on specific clock edges ODTEN ODTEN On die termination enable should be connected to to enable on die termination for end bus agents For middle bus agents pull this signal down via a resistor to ground to disable on die termination Whenever ODTEN is high on die termination will be active regardless of other states of the bus OPTIMIZED This is an input pin to the processor to determine if the processor is in an optimized platform or a compatible platform This signal does includes a weak on die pull up to PROCHOT PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor die temperature has reached its factory configured trip point This indic
123. reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The Thermal Monitor feature must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 50 Clocks will not be off for more than 3 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With a thermal solution designed to meet Thermal Profile A it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor pe
124. rformance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable A thermal solution that is designed to Thermal Profile B may cause a noticeable performance loss due to increased TCC activation Thermal Solutions that exceed Thermal Profile B will exceed the maximum temperature 71 Intel Xeon Processor with 800 MHz System Bus ntel 6 2 2 6 2 3 6 2 4 72 specification and affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the appropriate thermal mechanical design guide for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems using the Intel Xeon processor with 800 MHz system bus must not rely on software usage of this mechanism to limit the processor temperature
125. rocessor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and the chipset over the FSB Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied Integrated Heat Spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface mPGA 604 Socket The Intel Xeon processor with 800 MHz system bus mates with the baseboard through this surface mount 604 pin zero insertion force ZIF socket See the 604 Socket Design Guidelines for details regarding this socket Processor Core The processor s execution engine Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor pins should not be connected to any supply voltages have any I Os biased or receive any clocks Symmetric Agent A symmetric agent is a processor which shares the same I O subsystem and memory array and runs the same operating system as another processor in a system Systems using symmetric agents are known as Symmetric Multiprocessor SMP systems Intel Xeon processor with 80
126. rror and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding write bus transaction INIT INIT Initialization when asserted resets integer registers inside all processors without affecting their internal caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor front side bus agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST Datasheet 43 Intel Xeon Processor with 800 MHz System Bus Table 20 Signal Definitions Sheet 6 of 9 Description Notes LINT 1 0 LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all front side bus agents When the APIC functionality is disabled the LINTO I
127. s a 2 second duration peak load superimposed on the static load requirement representative of loads experienced by the package during heatsink installation Datasheet Table 18 3 5 3 6 3 7 Table 19 Datasheet Intel Xeon Processor with 800 MHz System Bus Package Handling Guidelines Table 18 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N 1 4 5 80 Ibf Tensile 156N 2 4 5 35 Ibf Torque 8 N m 3 4 5 70 Ibf in NOTES 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface 3 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization and incidental applications one time only 5 Handling guidelines are for the package only and do not include the limits of the processor socket Package Insertion Specifications The Intel Xeon processor with 800 MHz system bus can be inserted and removed 15 times from an mPGA604 socket which meets the criteria outlined
128. s and their corresponding core frequencies Core Frequency to Front Side Bus Multiplier Configuration Core Frequency to Frequency with Notes Front Side Bus Multiplier 200 MHz Front Side Bus Clock 1 14 2 80 GHz 1 1 15 3 GHz 1 1 16 3 20 GHz 1 1 17 3 40 GHz 1 1 18 3 60 GHz 1 1 Individual processors operate only at or below the frequency marked on the package Front Side Bus Frequency Select Signals BSEL 1 0 Upon power up the front side bus frequency is set to the maximum supported by the individual processor BSEL 1 0 are open drain outputs which must be pulled up to and are used to select the front side bus frequency Please refer to Table 12 for DC specifications Table 3 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the processor s chipset and clock synthesizer front side bus agents must operate at the same core and front side bus frequencies Individual processors will only operate at their specified front side bus clock frequency BSEL 1 0 Frequency Table BSEL1 BSELO Bus Clock Frequency 0 0 Reserved 0 1 Reserved 1 0 200 MHz 1 1 Reserved Datasheet intel 2 3 2 Figure 1 2 4 Datasheet Intel Xeon Processor with 800 MHz System Bus Phase Lock Loop PLL and Filter and are power sources required
129. siderations may need to be addressed to provide sufficient airflow to the fan inlet The active heatsink is primarily designed to be used in a pedestal chassis where sufficient air inlet space is present and side directional airflow is not an issue The 1U and 20 passive heatsinks require the use of chassis ducting and are targeted for use in rack mount servers The retention solution used for these products is called the Common Enabling Kit or CEK The CEK base is compatible with all three heatsink solutions The active heatsink solution for the boxed Intel Xeon processor with 800 MHz system bus will be transitioning after initial product introduction from a 3 pin thermistor controlled solution to a 4 pin pulse width modulated PWM T diode controlled solution This transition is being done to help customers meet acoustic targets in pedestal platforms through the ability to directly control the active heatsink fan RPM To properly support this new active heatsink solution it may be necessary to modify existing baseboard designs with 4 pin CPU fan headers If a 4 pin active fan heatsink solution is plugged into the older 3 pin fan header the heatsink will revert back to a thermistor controlled mode Please see the Section 8 3 Electrical Requirements on page 89 for more details Figure 16 through Figure 18 are representations of the three heatsink solutions that will be offered as part of a boxed Intel Xeon processor with 800 MHz system bus
130. ssor with 800 MHz System Bus Thermal Mechanical Design Guidelines The boxed processor will ship with a component thermal solution Refer to Section 8 0 for details on the boxed processor Thermal Specifications To allow the optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature Asp specifications as defined by the applicable thermal profile see Table 23 Figure 23 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the appropriate processor thermal mechanical design guideline The Intel Xeon processor with 800 MHz system bus introduces a new methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and assure processor reliability Selection of the appropriate fan speed will be based on the temperature reported by the processor s Thermal Diode If the diode temperature is greater than or equal to Tcontrol see Section 6 2 6 then the processor case temperature must remain at or below the temperature as specified by the thermal profile see Figure 23 If the diode temperature is less than Tcontrol then the case temperature is permitted to exceed the thermal profile but the diode temperature must remain at or below Tcontro
131. st data into the processor TDI provides the serial input needed for JTAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TEST BUS yo Must be connected to all other processor TEST BUS signals in the system TESTHI 6 0 All TESTHI inputs should be individually connected to via a pull up resistor which matches the trace impedance TESTHI 3 0 and TESTHI 6 5 may all be tied together and pulled up with a single resistor if desired However usage of boundary scan test will not be functional if these pins are connected together TESTHI4 must always be pulled up independently from the other TESTHI pins For optimum noise margin all pull up resistor values used for TESTHI 6 0 should have a resistance value within 20 of the impedance of the baseboard transmission line traces For example if the trace impedance is 50 than a value between 40 Q 60 Q should be used THERMDA Other Thermal Diode Anode See Section 6 2 7 THERMDC Other Thermal Diode Cathode See Section 6 2 7 THERMTRIP Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur Measurement of the temperature is accomplished through an internal thermal sensor Upon assertion of THERMTRIP the processor
132. tead of the maximum processor power consumption The Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more details on this feature refer to Section 6 2 To ensure maximum flexibility for future requirements systems should be designed to the Flexible Motherboard FMB guidelines even if a processor with a lower thermal dissipation is currently planned Thermal Monitor feature must be enabled for the processor to remain within specification Intel Xeon Processor with 800 MHz System Bus Thermal Specifications Core Maximum Thermal Minimum Maximum Frequency Power Design Power TCASE TCASE Notes GHz W W C C 2 80 GHz FMB 111 103 5 See Figure 13 Table 24 1 2 3 4 5 6 7 or Table 25 NOTES 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static and combination wherein exceeds Vcc at specified Please refer to the static and transient tolerance specifications in Section 2 0 2 Listed frequencies are not necessarily committed production frequencies 3 Maximum Power is the maximum thermal power that can be dissipated by the processor through the integrated heat spreader IHS Maximum Power is measured at maximum 4 Thermal Design Power TDP
133. tem Bus Since the signal pins receive power from the front side bus these pins should not be driven allowing the level to return to Vrr for minimum power drawn by the termination resistors in this state In addition all other input pins on the front side bus should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal When re entering the Stop Grant state from the Sleep state STPCLK should only be deasserted or more bus clocks after the deassertion of SLP A transition to the Grant Snoop state will occur when the processor detects a snoop on the front side bus see Section 7 2 4 A transition to the Sleep state see Section 7 2 5 will occur with the assertion of the SLP signal While in the Stop Grant state SMI INIT BINIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus The PBE s
134. term AGTL Input refers to the input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving AGTL asynchronous outputs can become active anytime and include an active pMOS pull up transistor to assist during the first clock of a low to high voltage transition With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as rising edge of BCLKO Asynchronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 5 identifies which signals are common clock source synchronous and asynchronous Datasheet INTel Intel Xeon Processor with 800 MHz System Bus Table 5 Front Side Bus Signal Groups Signal Group Type Signals AGTL Common Clock Synchronous to BCLK 1 0 BPRI BR 3 1 DEFER RESET RS 2 0 Input RSP TRDY AGTL Common Clock Synchronous to BCLK 1 0 ADS AP 1 0 BINIT 4 BNR BPM 5 0 BRO4 DBSY DP 3 0 DRDY HITM LOCK
135. terminated on the baseboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the 7P700 Debug Port Design Guide See Section 1 2 TESTHI 6 0 pins should be individually connected to Vyr via a pull up resistor which matches the nominal trace impedance TESTHI 3 0 and TESTHI 6 5 may be tied together and pulled up to with a single resistor if desired However usage of boundary scan test will not be functional if these pins are connected together TESTHI4 must always be pulled up independently from the other TESTHI pins For optimum noise margin all pull up resistor values used for TESTHI 6 0 pins should have a resistance value within 20 of the impedance of the board transmission line traces For example if the nominal trace impedance is 50 then a value between 40 and 60 Q should be used N C no connect pins of the processor are not used by the processor There is no connection from the pin to the die These pins may perform functions in future processors intended for platforms using the Intel Xeon processor with 800 MHz system bus Front Side Bus Signal Groups The front side bus signals have been combined into groups by buffer type AGTL input signals have differential input buffers which use GTLREF as a reference level In this document the
136. th Enhanced Intel SpeedStep Technology These capabilities are targeted for dual processor DP servers and workstations in data center and office environments Thermal Monitor provides efficient and effective cooling in high temperature situations Demand Based Switching DBS with Enhanced Intel SpeedStep Technology allows tradeoffs to be made between performance and power consumption This may lower average power consumption in conjunction with OS support The Intel Xeon processor with 800 MHz system bus supports Hyper Threading Technology This feature allows a single physical processor to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architecture state with its own set of general purpose registers control registers to provide increased system responsiveness in multitasking environments and headroom for next generation multithreaded applications More information on Hyper Threading Technology can be found at http www intel com technology hyperthread Other features within the Intel NetBurst microarchitecture include Advanced Dynamic Execution Advanced Transfer Cache enhanced floating point and multi media unit Streaming SIMD Extensions 2 SSE2 and Streaming SIMD Extensions 3 SSE3 Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor The Advanced Transfer Cache is a 1
137. ting baseboard designs to support this new 4 pin active heatsink solution if PWM T diode control is desired It may also be necessary to verify that the larger 4 pin fan connector will not interfere with other components installed on the baseboard The fan power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The fan power header identification and location must be documented in the suppliers platform documentation or on the baseboard itself The baseboard fan power header should be positioned within 177 8 mm 7 in from the center of the processor socket PWM Fan Frequency Specifications 4 pin active CEK heatsink Description Min Frequency Nominal Frequency Max Frequency Unit PWM Control 21 000 25 000 28 000 Hz Frequency Range Fan Specifications 3 and 4 pin active CEK heatsink 2222 Typ Max Max Description Min Steady Steady Startup Unit 12 V 12 volt fan power supply 10 8 12 12 13 2 V IC Fan Current Draw N A 1 1 25 1 5 A SENSE SENSE frequency 2 2 2 2 Pulses per fan revolution Fan Cable Connector Pinout 3 pin active CEK heatsink PIN 3 PIN 2 PIN 1 WIRE Datasheet Intel Xeon Processor with 800 MHz System Bus Table 31 Fan Cable Connector Pinout 3 pin active CEK heatsink Pin Number Signal Color 1 Ground Black 2 Power
138. ts are measured across vias on the platform for the VCCSENSE and VSSSENSE pins close to the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe Refer to Table 10 and corresponding Figure 4 The processor should not be subjected to any static Vcc level that exceeds the max associated with any particular current Failure to adhere to this specification can shorten processor lifetime 6 Minimum Vcc and maximum lcc are specified at the maximum processor case temperature TcAsg shown in Table 23 lcc is specified at the relative Voc point on the load line The processor is capable of drawing lcc for up to 10 ms Refer to Figure 2 for further details on the average processor current draw over various time durations Datasheet 23 Intel Xeon Processor with 800 MHz System Bus ntel 7 FMB is the flexible motherboard guideline These guidelines are for estimation purposes only See Section 2 11 1 for further details on FMB guidelines 8 This specification represents the reduction due to each VID transition See Section 2 4 9 This specification refers to the potential total reduction of the load line due to VID transitions below the specified VID 10 must be provided via a separate voltage s
139. urce Sync I O Y8 RESET Common Clk Input AA17 VSS Power Other Y9 062 Source Sync AA18 D24 Source Sync I O Y10 VTT Power Other 19 D15 Source Sync Y11 DSTBP3 Source Sync I O AA20 VCC Power Other Y12 DSTBN3 Source Sync I O 21 D11 Source Sync I O Y13 VSS Power Other AA22 D10 Source Sync Y14 DSTBP2 Source Sync I O AA23 VSS Power Other Y15 DSTBN2 Source Sync I O 24 06 Source Sync Y16 VCC Power Other AA25 03 Source Sync I O Datasheet 63 Intel Xeon Processor with 800 MHz System Bus Table 22 Pin Listing by Pin Number Sheet 7 of 8 E Pin Name Direction E Pin Name E ne Direction AA26 VCC Power Other ACA Power Other AA27 D1 Source Sync I O AC5 D60 Source Sync I O AA28 N C N C N C AC6 D59 Source Sync I O AA29 N C N C N C AC7 55 Power Other AA30 VSS Power Other AC8 056 Source Sync 1 VCC Power Other AC9 D47 Source Sync I O AB1 VSS Power Other AC10 VTT Power Other AB2 VCC Power Other AC11 D43 Source Sync I O AB3 BSEL1 Power Other Output AC12 D41 Source Sync I O AB4 VCCA Power Other Input AC13 VSS Power Other AB5 VSS Power Other AC14 D50 Source Sync I O AB6 D63 Source Sync I O AC15 DP2 Common Clk AB7 PWRGOOD Async GTL
140. ution The CEK is designed to extend air cooling capability through the use of larger heatsinks with minimal airflow blockage and bypass CEK retention mechanisms can allow the use of much heavier heatsink masses compared to legacy limits by using a load path directly attached to the chassis pan The CEK spring on the secondary side of the baseboard provides the necessary compressive load for the thermal interface material The baseboard is intended to be isolated such that the dynamic loads from the heatsink are transferred to the chassis pan via the stiff screws and standoffs The retention scheme reduces the risk of package pullout and solder joint failures The baseboard mounting holes for the CEK solution are the same location as the legacy server processor hole locations as specified by the SSI EEB 3 5 However the CEK assembly requires larger diameter holes to compensate for the CEK spring embosses The holes now need to be 10 2 mm 0 402 in in diameter components of the heatsink solution will be captive to the heatsink and will only require a Phillips screwdriver to attach to the chassis pan For further details on the thermal solution refer to the Intel Xeon Processor with 800 System Bus Thermal Mechanical Design Guidelines see Section 1 2 Electrical Requirements Fan Power Supply active CEK Initially the boxed Intel Xeon processor with 800 MHz system bus will be introduced with a 3 pin acti
141. ve fan heatsink solution This heatsink solution requires a constant 12 V supplied to pin 2 and does not support variable voltage speed control or 3 pin pulse width modulation PWM control Fan RPM is automatically varied based on temperature measured by a thermistor located at the fan inlet 89 Intel Xeon Processor with 800 MHz System Bus Table 29 Table 30 Figure 27 90 intel A new 4 pin PWM T diode controlled active fan heatsink solution will replace the 3 pin thermistor controlled solution after initial boxed Intel Xeon processor with 800 MHz system bus introduction This new solution is being offered to help provide better control over pedestal chassis acoustics This is achieved though more accurate measurement of processor die temperature through the processor s temperature diode T diode Fan RPM is modulated through the use of an ASIC located on the baseboard that sends out a PWM control signal to the 4th pin of the connector labeled as Control This heatsink solution also requires a constant 12 V supplied to pin 2 and does not support variable voltage control or 3 pin PWM control See Table 30 for details on the 3 and 4 pin active heatsink solution connectors If the new 4 pin active fan heatsink solution is connected to an older 3 pin baseboard CPU fan header it will default back to a thermistor controlled mode allowing compatibility with existing designs It may be necessary to change exis
142. violations or reduced lifetime of the component Vcc Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and the baseboard designer must assure a low interconnect resistance from the voltage regulator or pins to the mPGA604 socket The power delivery solution must insure the voltage and current specifications are met defined in Table 9 Decoupling Decoupling must be provided on the baseboard Decoupling solutions must be sized to meet the expected load To insure optimal performance various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors Front Side Bus AGTL Decoupling The Intel Xeon processor with 800 MHz system bus integrates signal termination on the die as well as part of the required high frequency decoupling capacitance on the processor package However additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the front side bus Bulk decoupling must also be provided by the baseboard for proper AGTL bus operation Intel Xeon Processor with 800 MHz System Bus ntel 2 3 Table 2 2 3 1 Table 3 Front Side Bus Clock BCLK 1 0 and Processo

Intel Xeon 2.80 GHz

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