Transcend 64MB SDRAM 144Pin SO-DIMM PC133 Unbuffer Non-ECC Memory
Contents
1. OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter RAS to CAS delay J DIH O IOIO s VD fO _ D0 O I lo0loO E O e lt O R lt O J3 10 2 Ba 3 eje o 2 2 o Slo o lt O lt CD o D Q lt Row cycle time ast data in to new col address delay ast data in to row precharge ast data in to burst stop tBDL min CCD min eo eal sales o O o o a D N 0 P O Q o o o o D n 0 o D o lt pje Z C O O a O lt o O O C P O C pa o D pe o Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc J TS8MSS64V6C 144PIN PC133 Unbutfered SO DIMM 64MB With 8Mx16 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Min Max tOH ns Output data hold time 3 CLK high pulse width CLK to output in Hi Z Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall2. clock Dimensions Side Millimeters Inches 67 60 0 200 2 661 0 008 B 32 80 1 291 C 23 20 0 913 D 4 60 0 181 E 3 30 0 130 F 2 50 0 098 G 2 00 0 079 H 6 00 0 236 20 00 0 787 J 24 00 0 200 0 945 0 008 K 1 00 0 100 0 039 0 004 Transcend information Inc 144PIN PC133 Unbuffered SO DIMM 64MB With 8Mx16 CL3 TS8MSS64V6C Block Diagram Pin Identification Pin Name No Name Please refer Block Diagram Transcend information Inc Name Name ROAI A Symbol Function A0 11 BA0 1 DQ0 DQ63 GE AO A11 Address inputs RAS IRAS BAO BA1 Select Bank NE CAS 8Mx16 DQ0 DQ63 Data inputs outputs SDRAM ICS NE CLK Clock Input ICKE CKE Clock Enable Input Ke ICS Chip Select Input RAS Row address strobe A0 11 BA0 1 CAS Column address strobe A WE Write Enable RAS CAS 8Mx16 DQMO 7 DQM Vcc Power Supply Vss Ground SDA Serial Address Data l O SDA SDA SCL SCL SCL Serial Clock Emmi io NC No Connection 24C02 Pinouts Pin Pin Name 144PIN PC133 Unbuffered SO DIMM 1S8MSS64V6C 64MB With 8Mx16 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Value Voltage on any pin relative to Vss 1 0 4 6 Voltage on VDD supply relative to Vss 1 0 4 6 Power dissipation O a hort circuit current s o Operating Temperature Note Permanent device damage may occur if TONE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Expo
3. Bank on Module 64MB Command Address Setup Time CI 4 C 1 0 1 5 4 10 1 F 4 1 1 E 0 14 F 14 D 10 15 Command Address Hold Time Data Signal Setup Time Data Signal Hold Time 217 28 29 30 31 32 33 34 39 Transcend information Inc 8 144PIN PC133 Unbuffered SO DIMM 1S8MSS64V6C 64MB With 8Mx16 CL3 36 61 Supersetinformation 62 SPD Data Revision Code 02 63 ChecksumforBytes082 lt o o o oo o ooo o o 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend 7F 4F Manufacturing Location 54 54 5338 40 5353 73 90 Manufacturers Part Number TS8MSS64V6C 34 91 92 RevisionCode 3 O 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly SerialNumber ByManufacturer Variable 99 125 Manufacturer Specific Data o o oo o oo o o 126 ntel Specification Frequency O Jo o o o gt o o o 127 Intel Specification CASH Latency Clock Signal Support CL 2 3 Clock 0 128 Unused Storage Locations Open FF 20 20 20 20 20 20 64 Transcend information Inc 9
4. TS8MSS64V6C 144PIN PC133 Unbuffered SO DIMM 64MB With 8Mx16 CL3 Description The TS8MSS64V6C is a 8M bit x 64 Synchronous Dynamic RAM high density memory module The TS8MSS64V6C consists of 4 piece of CMOS 8Mx16bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 144 pin printed circuit board The TS8MSS64V6C is a Dual In Line Memory Module and is intended for mounting into 144 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation freguencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Placement Z E E E E E E E E E E E E E E E E E E E E E E z f a oF EH a 98 pe E PCB 09 1002 Features RoHS compliant Performance Range PC133 Burst Mode Operation Auto and Self Refresh Serial Presence Detect SPD with serial EEPROM LVTTL compatible inputs and outputs Single 3 3V 0 3V power supply MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Scramble Sequential amp Interleave All inputs are sampled at the positive going edge of the system
5. is High at row precharge BAo and BA is ignored and all banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 O Transcend information Inc 7 144PIN PC133 Unbuffered SO DIMM TS8MSS64V6C 64MB With 8Mx16 CL3 Serial Presence Detect Specification Serial Presence Detect Byte No Function Described Standard Specification Vendor Part of Column Addresses on this Assembly 9 OO Data Width Continuation J o 0 o Primary SDRAM Width o oe Error Checking SDRAM Width o o 0 O SDRAM Device Attributes General Prec All Auto Prec R W Burst 23 SDRAM Cycle Time 2 highest CL 24 SDRAM Access from Clock 2 highest CL 25 SDRAM Cycle Time 3 highestCL o oo 7 ooo o o 26 SDRAM Access from Clock 3 highest CL A ni OO SDRAM Access from Clock highest CL X16 283 T 10 11 12 14 15 16 17 18 19 20 21 22 0 0 0 4 0 7 5 0 8 0 0 0 0 A Minimum Row Active to Row Activate 0 Minimum RAS to CAS Delay Minimum RAS Pulse Width 2 Density of Each
6. penal si tRC gt tRC min One Bank Active loL lt 0mA Precharge Standby Current CRESVIL max ice 10ns ma in power down mode CKE 8 CLK lt VIL max tece N CKEZVIH min CS gt VIH min tcc 10ns Input signals are changed one time during 20ns Precharge Standby Current je in non power down mode CKE gt VIH min CLK lt VIL max tcc lt Icc2NS Input signals are stable Active Standby Current CKE lt SVIL max tcc 10ns in power down mode CKE 8 CLK lt VIL max tccse Icc2 CKEZVIH min CS gt VIH min tcc 10ns sa Input signals are changed one time during 20ns Active Standby Current in non power down mode One Bank Active S CKE gt VIH min CLK lt VIL max tcc lt Input signals are stable lOL 0 mA Operating Current Icca Page Burst Burst Mode teco 2CLKs Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap ICC3N Transcend information Inc 4 144PIN PC133 Unbuffered SO DIMM 1S8MSS64V6C 64MB With 8Mx16 CL3 AC OPERATING TEST CONDITIONS von 3 3V 0 3V TA 0 to 70 C 410 Input rise and fall time tr tf 1 1 ns Output timing measurement reference level V Output load condition See Fig 2 3 3V Vtt 1 4V 1200 Ohm 50 Ohm Output e VoH DC 2 4V lon 2mA Output Z0 50 Ohm VoL DC 0 4V lo 2mA 50pF 50pF TETAS 77177 1777 Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit 870 Ohm
7. sure to higher than recommended voltage for extended periods of time could affect device reliability torage temperature 55 150 oe DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Parameter Symbol Min Typ Note Supply voltage v 30 33 36 v Input high voltage vi 20 30 Vopws v 1 input low voltage w os o f os v 2 Output high voltage von 24 v low 2ma Output low voltage voa o v loez2mA Input leakage current ta o a 5 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV s Vin sVDDO Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri state output CAPACITANCE Voo 3 3V Ta 23 C f 1MHz VREF 1 4V 200mV Parameter Input capacitance A0 A11 BAO BA1 Input capacitance RAS CAS WE Input capacitance CKE Input capacitance CLK Input capacitance CS Input capacitance DOMO DOM7 Data input output capacitance DQ0 DQ63 Transcend information Inc 3 144PIN PC133 Unbuffered SO DIMM 1S8MSS64V6C 64MB With 8Mx16 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Symbol eee Operating Current Puls
8. time tr amp tf 1ns If tr 8 tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 6 144PIN PC133 Unbuffered SO DIMM 1S8MSS64V6C 64MB With 8Mx16 CL3 SIMPLIFIED TRUTH TABLE COMMAND Mode Register Set Auto Refresh Refresh Entry Read 8 Address Ao As Column Address Column Address Ao As Clock Suspend or Active Power Down Entry H L Precharge Power Down Mode L H H H Exit L H i X X A ee No Operation Command H X x V Valid X Don t Care H Logic High L Logic Low X Note 1 OP Code Operand Code Ao A11 BAo BA1 Program keys MRS 2 MRS can be issued only at all banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAo BA1 Bank select address If both BAo and BA1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA are High at read write row active and precharge bank D is selected If A10 AP
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