Transcend 128MB SDRAM PC100 Unbuffer Non-ECC Memory
Contents
1. Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 8 W Short circuit current los 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current Inputs liL 16 8 uA 3 Input leakage current I O pins IOL 3 1 5 uA 4 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional b2. 168PIN PC100 Unbuffered DIMM TS16MLS64V8D 128MB With 16Mx8 CL3 SIMPLIFIED TRUTH TABLE A11 COMMAND CKEn 1 CKEn CS_ RAS CAS WE DQM BAo 1 A1o AP Ao Ag Note Register Mode Register Set H X L L L L X OP CODE 1 2 Auto Refresh H 3 Entry H L L L L H X X 3 Refresh Self i L H H H 3 Refresh Ext L H FAT xi x x a 3 Bank Active amp Row Addr H X L L H H X V Row Address Read amp Auto Precharge Disable L Golufn 4 Column Address Auto Precharge Enable H x L H L H x M H TE 4 5 Write amp Auto Precharge Disable L Column 4 Column Address auto Precharge Enable 5 x L 3 L L X y H TEAS 4 5 Burst Stop H X L H H L x 6 Bank Selection V L Precharge Both Banks H X L L H L X xX H X H xX xX xX Clock Suspend or Entry H L L V V V X Active Power Down x Exit L H X xX xX xX X H xX xX xX Entry H L x L H H H Precharge Power Down Mode H X X X x Exit L H x L V V V DQM H X V X 7 H xX xX xX No Operation Command H x x x L H H H V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A11 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharg
3. Bank Active CKE2ViH min CLK lt ViL max tcc lt 200 ICC3NS input signals are stable lOL 0 mA Operating Current Icc4 Page Burst mA 1 Bust Mod 800 vests teco 2CLKs Refresh Current ICC5 tRc tRC min 1 520 mA 2 Self Refresh Current ICC6 CKE lt 0 2V 16 mA Note 1 Measured with outputs open 2 Refresh period is 64ms Transcend information Inc 6 168PIN PC100 Unbuffered DIMM TS16MLS64V8D 128MB With 16Mx8 CL3 AC OPERATING TEST CONDITIONS vop 3 3V 0 3V TA 0 to 70 C Parameter Vawe nit AC Input levels VIH VIL 2 4 0 4 Input timing measurement reference level Input rise and fall time tr tf 1 1 Output timing measurement reference level Output load condition 3 3V Vit 1 4V O 1200 Ohm 50 Ohm gt Von DC 2 4V lon 2mA Output Q z0 50 Ohm Vor DC 0 4V lo 2mA 50pF 50pF 870 Ohm 71117 Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Vale unit note Row active to row active delay tRRD min RAS to CAS dela Row precharge time tRP min Row active time a Row cycle time tRc min Last data in to new col address dela Last data in to row precharge tRDL min Last data in to burst stop tBDL min Col address to col address dela Number of valid CAS latency 3 output data CAS latency 2 Note 1 The minimum
4. number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 7 168PIN PC100 Unbuffered DIMM TS16MLS64V8D 128MB With 16Mx8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Unit Note Min Max CLK cycle time CAS latency 3 tcc 10 1000 ns 1 CAS latency 2 12 CLK to valid CAS latency 3 tSAC 6 ns 1 2 output delay CAS latency 2 Output data CAS latency 3 tOH 3 ns 2 hold time CAS latency 2 3 CLK high pulse width tCH 3 ns 3 CLK low pulse width tCL 3 ns 3 Input setup time tss 2 ns 3 Input hold time tSH 1 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output CAS latency 3 tSHZ 6 ns in Hi Z CAS latency 2 7 Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8
5. 168PIN PC100 Unbuffered DIMM TS16MLS64V8D 128MB With 16Mx8 CL3 Description Placement The TS16MLS64V8D is a 16M bit x 64 Synchronous Dynamic RAM high density for PC 100 The TS16MLS64V8D consists of 8pcs CMOS 16Mx8 bits p i A Synchronous DRAMS in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS16MLS64V8D is a Dual In Line Memory 2 Module and is intended for mounting into 168 pin edge connector sockets a Synchronous design allows precise cycle control with j the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies m programmable latencies allow the same device to be A useful for a variety of high bandwidth high performance i A memory system applications m m Features e Performance Range PC 100 0 B e Conformed to JEDEC Standard Spec D e Burst Mode Operation AA e Auto and Self Refresh i A E i e CKE Power Down Mode C e DQM Byte Masking Read Write a i WY e Serial Presence Detect SPD with serial EEPROM e L
6. Part pecification 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly A0 A11 0C 4 of Column Addresses on this Assembly A0 A9 OA 5 of Module Banks on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 10ns AO 10 SDRAM Access from Clock highest CL 6ns 60 11 DIMM configuration type non parity ECC None 00 15 625us Self 12 Refresh Rate Type Refresh 80 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 3 2 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 Prec All Auto Prec 22 SDRAM Device Attributes General R W Burst OE 23 SDRAM Cycle Time 2 highest CL 12ns Co 24 SDRAM Access from Clock 2 highest CL Tns 70 25 SDRAM Cycle Time 3 highest CL 0 00 26 SDRAM Access from Clock 3 highest CL 0 00 27 Minimum Row Precharge Time 20 14 28 Minimum Row Active to Row Activate 20 14 29 Minimum RAS to CAS Delay 20 14 30 Minimum RAS Pulse Width 50 32 31 Density of Each Bank on Module 128MB 20 32 Command Address Setup Time 2ns 20 33 Comman
7. Q11 57 16 DQ12 58 17 DQ13 59 18 Vcc 60 19 DQ14 61 20 DQ15 62 21 CBO 63 22 CB1 64 23 Vss 65 24 NC 66 25 NC 67 26 Vcc 68 27 WE 69 28 DQMO 70 29 DQM1 71 30 CSO 72 31 NC 73 32 Vss 74 33 AO 75 34 A2 76 35 A4 77 36 AG 78 37 A8 79 38 A10 AP 80 39 BA1 81 40 Vcc 82 41 Vcc 83 42 CLKO 84 Pin No 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Please refer Block Diagram Transcend information Inc 168PIN PC100 Unbuffered DIMM TS16MLS64V8D 128MB With 16Mx8 CL3 Block Diagram AO A11 A0 A11 A0 A11 BAO BA1 ip BAO BA1 BAO BA1 DQ0 DQ63 DQ0 DQ7 DQ0 DQ7 RAS ICAS IWE CSO a T CKEO CKE O a GS 5 ICS2 A0 A11 A0 A11 BAO BA1 BAO BA1 BAO BA1 DQ0 DQ7 Ei DQ0 DQ7 E DQ0 DQ7 CLKO CLK1 CLK2 CLK3 Serial EEPROM SCL SCL SDA SDA AO A1 A2 SAO SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 4 TS16MLS64V8D ABSOLUTE MAXIMUM RATINGS 168PIN PC100 Unbuffered DIMM 128MB With 16Mx8 CL3
8. VTTL compatible inputs and outputs E ial _ gt e Single 3 3V 0 3V power supply c H e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave PCB 09 7308 e Allinputs are sampled at the positive going edge of the system clock Transcend information Inc l 168PIN PC100 Unbuffered DIMM 128MB With 16Mx8 CL3 TS16MLS64V8D Dimensions Pin Identification Side Millimeters Inches Symbol RUNGGI A 133 35 0 40 5 250 0 016 A0 A11 BAO BA1 Address input B 65 67 2 585 DQ0 DQ63 Data Input Output C 23 49 0 925 CLKO CLK3 Clock Input D 8 89 0 350 E 3 00 0 118 CKEO Clock Enable Input F 29 21 0 20 1 15 0 008 CSO CS2 Chip Select Input G 19 78 0 779 IRAS Row Address Strobe H 15 78 0 622 CAS Column Address Strobe l 1 27 0 10 0 050 0 004 Refer Placement WE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vec 3 3 Voltage Power Supply Vss Ground NC No Connection Transcend information Inc TS16MLS64V8D 168PIN PC100 Unbuffered DIMM 128MB With 16Mx8 CL3 Pinouts Pin Pin Pin No Name No 01 Vss 43 02 DQO 44 03 DQ1 45 04 DQ2 46 05 DQ3 47 06 Vcc 48 07 DQ4 49 08 DQ5 50 09 DQ6 51 10 DQ7 52 11 DQ8 53 12 Vss 54 13 DQ9 55 14 DQ10 56 15 D
9. d Address Hold Time ins 10 34 Data Signal Setup Time 2ns 20 35 Data Signal Hold Time ins 10 36 61 Superset Information 00 62 SPD Data Revision Code Version 1 2 12 63 Checksum for Bytes 0 62 46 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 Transcend information Inc 10 168PIN PC100 Unbuffered DIMM TS16MLS64V8D 128MB With 16Mx8 CL3 54 53 31 36 4D 4C 73 90 Manufacturers Part Number TS16MLS64V8D 53 36 34 56 38 44 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 100MHz 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 3 F6 128 _ Unused Storage Locations Open FF Transcend information Inc 11
10. e command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA1 are ignored and both banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc 9 TS16MLS64V8D Serial Presence Detect Specification 168PIN PC100 Unbuffered DIMM 128MB With 16Mx8 CL3 Serial Presence Detect Byte No Function Described eau Vendor
11. uffers with Tri State outputs 4 Dout is disabled OV lt VOUT lt VDDQ CAPACITANCE TA 25 C f 1MHz Parameter Symbol Min Max Unit Input capacitance Ao A11 BAo BA1 CIN1 25 45 pF Input capacitance RAS CAS WE CIN2 25 45 pF Input capacitance CKE0 CIN3 25 45 pF Input capacitance CLKO CLK3 CIN4 10 13 pF Input capacitance CSO CS2 CIN5 15 25 pF Input capacitance DQM0 DQM 7 CIN6 8 12 pF Data input output capacitance DQ0 DQ63 COUT 9 12 pF Transcend information Inc 5 168PIN PC100 Unbuffered DIMM TS16MLS64V8D 128MB With 16Mx8 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition CAS Latency Value Unit Note Operating Current as Burst Length 1 A i m One Bank Active IRE ein loL OmA Precharge Standby Current lcc2P___ CKE lt ViL max tcc 15ns 16 A in power down mode Icc2PS_ CKE amp CLK lt ViL max tcc lt 16 Se Nii agra aie Goenged one ime aurtna 30n 160 Precharge Standby Current mA in non power down mode fot IccoNS eee CLK lt VIL max tcc 80 nput signals are stable Active Standby Current Icc3P CKE lt VIL max tcc 15ns 40 mA in power down mode Icc3PS_ CKE amp CLK lt ViL max tcc 40 CKE gt ViH min CS gt ViH min tcc 15ns 240 ICC3N input signals are changed one time during 30ns Active Standby Current mA in non power down mode One
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