Transcend 128MB SDRAM 144Pin SO-DIMM PC133 Unbuffer Non-ECC Memory
Contents
1. amp Interleave All inputs are sampled at the positive going edge of the system clock Dimensions Side Millimeters Inches 67 60 0 200 2 661 0 008 B 32 80 1 291 C 23 20 0 913 D 4 60 0 181 E 3 30 0 130 F 2 50 0 098 G 2 00 0 079 H 6 00 0 236 20 00 0 787 J 24 00 0 200 0 945 0 008 K 1 00 0 100 0 039 0 004 Transcend information Inc TS16MSS64V6G 144PIN PC133 Unbuffered SO DIMM 128MB With 16Mx16 CL3 Block Diagram Pin Identification Symbol Function AO A12 A0 A12 Address inputs BAO BA1 BAO BA1 Select Bank DQ0 DQ63 Data inputs outputs ICAS 16Mx16 CLK Clock Input WE SDRAM CKE Clock Enable Input ICS Chip Select Input RAS Row address strobe ICAS Column address strobe WE Write Enable IRAS DQM0 7 DQM ICAS 16Mx16 H CAS 16Mx16 Vcc Power Supply WE SDRAM Vss Ground SDA Serial Address Data I O SCL Serial Clock SDA sch DQM4 A DQM5 NC No Connection A2 24C02 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 01 Vss 49 DQ13 97 DQ22 02 Vss 50 DQ45 98 DQ54 03 DQO 51 DQ14 99 DQ23 04 DQ32 52 DQ46 100 DQ55 05 DQ1 53 DQ15 101 Vcc 06 DQ33 54 DQ47 102 Vcc 07 DQ2 55 Vss 103 AG 08 DQ34 56 Vss 104 AT 09 DQ3 57 CBO 105 A8 10 DQ35 58 CB4 106 BAO 11 Vcc 59 CB1 107 Vss 12 Vcc 60 CB5 108 Vss 13 DQ4 61 CLKO 109 AQ 14 DQ36 62 CKEO 110 BA1 15 DQ5 63 Vcc 1112. Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC DIMM 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X16 10 14 Error Checking SDRAM Width 0 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 amp 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec All Auto Prec R W OE Burst 23 SDRAM Cycle Time 2 highest CL 10ns AO 24 SDRAM Access from Clock ar highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 128MB 20 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 Transcend information Inc 8 144PIN PC133 Unbuffered SO DIMM TS16MSS64V6G 128MB With 16Mx16 CL3 36 61 Superset Information 00 62 SPD Data Revision Code VER1 2 12 63 Checksum for Bytes 0 62 B7 B9 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T
3. 54 54 53 31 36 4D 53 73 90 Manufacturers Part Number TS16MSS64V6G 53 36 34 56 36 47 2020 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 86 128 Unused Storage Locations Open FF Transcend information Inc 9
4. A10 16 DQ37 64 Vcc 112 A11 17 DQ6 65 RAS 113 Vcc 18 DQ38 66 ICAS 114 Vcc 19 DQ7 67 IWE 115 DQM2 20 DQ39 68 CKE1 116 DQM6 21 Vss 69 CSO 117 DQM3 22 Vss 70 A12 118 DQM 7 23 DQMO 71 CS1 119 Vss 24 DQM4 72 A13 120 Vss 25 DQM1 73 NC 121 DQ24 26 DQM5 74 CLK1 122 DQ56 27 Vcc 75 Vss 123 DQ25 28 Vcc 76 Vss 124 DQ57 29 AO TT CB2 125 DQ26 30 A3 78 CB6 126 DQ58 31 A1 79 CB3 127 DQ27 32 A4 80 CB7 128 DQ59 33 A2 81 Vcc 129 Vcc 34 A5 82 Vcc 130 Vcc 35 Vss 83 DQ16 131 DQ28 36 Vss 84 DQ48 132 DQ60 37 DQ8 85 DQ17 133 DQ29 38 DQ40 86 DQ49 134 DQ61 39 DQ9 87 DQ18 135 DQ30 40 DQ41 88 DQ50 136 DQ62 41 DQ10 89 DQ19 137 DQ31 42 DQ42 90 DQ51 138 DQ63 43 DQ11 91 Vss 139 Vss 44 DQ43 92 Vss 140 Vss 45 Vcc 93 DQ20 141 SDA 46 Vcc 94 DQ52 142 SCL 47 DQ12 95 DQ21 143 Vcc 48 DQ44 96 DQ53 144 Vcc Please refer Block Diagram Transcend information Inc TS16MSS64V6G 144PIN PC133 Unbuffered SO DIMM 128MB With 16Mx16 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply relative to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 4 W Short circuit current Los 50 mA Operating Temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition E
5. Row Addr H x X V Row Address Read amp Auto Precharge Disable L Column 4 H x L H L H x V Address Column Address Auto Precharge Enable H 4 5 Ao As Write amp Auto Precharge Disable L Column 4 H x L H L L x V Address Column Address Auto Precharge Enable H ROR 4 5 O A8 Burst Stop H X L H H L X X 6 Bank Selection V L Precharge H x L L H L x x Both Banks x H Clock Suspend or Entry H L H X X x x Active Power L V V V X Down Exit L H x x x x x H xX xX xX Ent ed H L x Precharge Power L H H H x Down Mode H xX xX xX Exit x L H X L V V V DQM H X V X 7 H xX xX xX d No Operation Comman H x x x L H H H Note 1 OP Code Operand Code Ao A12 BAo BA1 Program keys MRS 2 MRS can be issued only at all banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAo BA1 Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA is Low at read write row active and precharge bank C is selected V Valid X Don t Care H Logic High L Logic Low If both BAo and BA are High
6. S64V6G 128MB With 16Mx16 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Unit Note Min Max CLK cycle time tcc 7 5 1000 ns 1 CLK to valid output delay tSAC 5 4 ns 1 2 Output data hold time tOH 3 ns 2 CLK high pulse width tCH 2 5 ns 3 CLK low pulse width tCL 2 5 ns 3 Input setup time tss 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output in Hi Z tSHZ 5 4 ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 6 TS16MSS64V6G 144PIN PC133 Unbuffered SO DIMM 128MB With 16Mx16 CL3 SIMPLIFIED TRUTH TABLE A12 A11 COMMAND CKEn 1 CKEn CS RAS CAS WE DQM BAo 1 A10 AP rier Note Register Mode Register Set H x L L L L x OP CODE 1 2 Auto Refresh H 3 Ho neres H iz L H x x Entry L 3 Refresh Self L H H H 3 Refresh Exit L H X X H X 3 Bank Active amp
7. TS16MSS64V6G 144PIN PC133 Unbuffered SO DIMM 128MB With 16Mx16 CL3 Description The TS16MSS64V6G is a 16M bit x 64 Synchronous Dynamic RAM high density memory module The TS16MSS64V6G consists of 4 piece of CMOS 16Mx16bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 144 pin printed circuit board The TS16MSS64V6G is a Dual In Line Memory Module and is intended for mounting into 144 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Placement mm m a Ria RA NEE 5 5 5 5 i B a n B Cy i 3 gE E g elle amp amp i PE H B 5 By a 9H z i O adlan ogr PCB 09 1002 Features RoHS compliant products Performance Range PC133 Burst Mode Operation Auto and Self Refresh Serial Presence Detect SPD with serial EEPROM LVTTL compatible inputs and outputs Single 3 3V 0 3V power supply MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Scramble Sequential
8. at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA is ignored and all banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc TS16MSS64V6G Serial Presence Detect Specification 144PIN PC133 Unbuffered SO DIMM 128MB With 16Mx16 CL3 Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 13 oD 4 of Column Addresses on this Assembly 9 09 5 of Module Banks on this Assembly 1 banks 01 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5NnS 75 10 SDRAM
9. ended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Value Unit Note Operating Current Icc1 Burst Length 1 600 mA 1 One Bank Active tRC gt tRC min loL OmA Precharge Standby Current Icc2P CKE lt ViL max tcc 10ns 8 mA mpawendownmmade Icc2PS_ CKE amp CLK lt VIL max tcc 8 Precharge Standby Current ICc2N CKE2ViH min CS2VIH min tcc 10ns 64 mA in non power down mode Input signals are changed one time during 20ns Icc2NS_ CKE2ViH min CLK lt VIL max tcc lt 56 Input signals are stable Active Standby Current Icc3P CKE lt ViL max tcc 10ns 24 mA PPRNO Ede Icc3PS CKE amp CLK lt ViL max toc 24 Active Standby Current Icc3N CKE2 ViH min CS2 ViIH min tcc 10ns 140 mA in non power down mode Input signals are changed one time during 20ns One Bank Active Icc3NS_ CKE2ViH min CLK lt VIL max tcc lt 120 Input signals are stable Operating Current Icc4 loL omA mA 1 Burst Mode Page Burst 880 tccp 2CLKs mA 2 Refresh current Icc5 tRC lt tRC min 880 Self Refresh Current ICC6 CKE lt 0 2V 12 mA Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Transcend information Inc 4 144PIN PC133 Unbuffered SO DIMM TS16MSS64V6G 128MB With 16Mx16 CL3 AC OPERATING TEST CONDITIONS von 3 3V 0 3V TA 0 to 70 C Parameter Value Unit AC Input l
10. evels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 O 3 3V ow AV 1200 Ohm 50 Ohm Vox DC 2 4V lon 2mA Output _Z0 50 Ohm Vor DC 0 4V loL 2mA 50pPF Z 50pPF 870 Ohm T1117 Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time RASIMI 1 ns d tRAS max 100 us Row cycle time Operation tRC min 65 ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccD min 1 CLK 3 Number of valid output data 2 ea 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 5 144PIN PC133 Unbuffered SO DIMM TS16MS
11. xposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V IOH 2MA Output low voltage VOL 0 4 V IOL 2mA Input leakage current ILI 10 10 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt Vin sVDDaQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri state output CAPACITANCE voo 3 3V TA 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Input capacitance AO A12 BAO BA1 CIN1 15 25 pF Input capacitance RAS CAS WE CIN2 15 25 pF Input capacitance CKE CIN3 15 25 pF Input capacitance CLK CIN4 15 21 pF Input capacitance CS CIN5 15 25 pF Input capacitance DQM0 DQM 7 CIN6 10 12 pF Data input output capacitance DQ0 DQ63 COUT 10 12 pF Transcend information Inc 3 144PIN PC133 Unbuffered SO DIMM TS16MSS64V6G 128MB With 16Mx16 CL3 DC CHARACTERISTICS Recomm
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