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Intel Pentium B940

1. 2 8 27 C1DRA23 Channel 1 DRAM Rank 2 3 Attributes Register The operation of this register is detailed in the description for register CODRAO1 B D F Type 0 0 0 MCHBAR Address Offset 60A 60Bh Reset Value 0000h Access RW L z Reset PEP Bit Attr Value Description Channel 1 DRAM Rank 3 Attributes C1DRA3 15 8 RW L 00h See CODRA3 register description This register is locked by Memory pre allocated for ME lock Channel 1 DRAM Rank 2 Attributes C1DRA2 7 0 RW L 00h See CODRA2 register description This register is locked by Memory pre allocated for ME lock Datasheet Volume 2 87 Processor Configuration Registers intel 2 8 28 C1WRDATACTRL Channel 1 Write Data Control Register This register provides Channel 1 Write Data Control B D F Type 0 0 0 MCHBAR Address Offset 64D 64Fh Reset Value 004111h Access RW BIOS Optimal Reset Value 00h b Reset ET Bit Attr Value Description 23 16 RW 00h Reserved 15 RW Ob Reserved Reserved sd1_cr_wrblk_wriodlldur 14 0 RW 4110h There is a legacy signal connected to this register that attaches to logic but the output of that logic does not connect to any functionality 2 8 29 C1CYCTRKPCHG Channel 1 CYCTRK PCHG Register This register provides Channel 1 CYCTRK Precharge control B D F Type 0 0 0 MCHBAR Address Offset 650 651h Reset Value 0000h Access RW RO
2. B D F Type 0 0 0 VCOPREMAP Address Offset 3C 3Fh Reset Value 00000000h Access RO RW Reset er Bit Attr Value Description Extended I nterrupt Message Data EI MD 31 16 RO 0000h This field is valid only for implementations supporting 32 bit MSI data fields Hardware implementations supporting only 16 bit MSI data may treat this field as read only 0 15 0 RW 0000h Interrupt message data 1 D Data value in the fault event interrupt message 2 15 11 FEADDR_REG Fault Event Address Register This register specifies the interrupt message address B D F Type 0 0 0 VCOPREMAP Address Offset 40 43h Reset Value 00000000h Access RW RO i Reset PNP Bit Attr Value Description 31 2 RW 00000000 Message Address MA h When fault events are enabled the contents of this register specify the DWORD aligned address bits 31 2 for the MSI memory write transaction 1 0 RO Oh Reserved 2 15 12 FEUADDR_REG Fault Event Upper Address Register This register specifies the interrupt message address For platforms supporting only interrupt messages in the 32 bit address range this register is treated as read only 0 B D F Type 0 0 0 VCOPREMAP Address Offset 44 47h Reset Value 00000000h Access RO Reset PERES Bit Attr Value Description Message upper address MUA This register need to be implemented only if hardware supports 64 bit 31 0 RO 0
3. B D F Type 0 1 0 PCI Address Offset 1Ah Reset Value 00h Access RW Reset TE Bit Attr Value Description Subordinate Bus Number BUSN This register is programmed by configuration software with the number of 7 0 RW 00h the highest subordinate bus that lies behind the device 1 bridge When only a single PCI device resides on the PCI Express G segment this register will contain the same value as the SBUSN1 register Datasheet Volume 2 Processor Configuration Registers 2 10 12 2 10 13 Datasheet Volume 2 intel IOBASE1 I O Base Address Register This register controls the processor to PCI Express G I O access routing based on the following formula 10_BASE lt address lt IO_LIMIT Only the upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are treated as 0 Thus the bottom of the defined I O address range will be aligned to a 4 KB boundary B D F Type 0 1 0 PCI Address Offset 1Ch Reset Value FOh Access RW RO Reset inai Bit Attr Value Description 1 O Address Base I OBASE This field corresponds to A 15 12 of the I O addresses passed by bridge 1 to 7 4 RW Fh PCI Express G BIOS must not set this register to 00h otherwise OCF8h OCFCh accesses will be forwarded to the PCI Express hierarchy associated with this device 3 0 RO Oh Reserved IOLI MIT1 1I O Limit Address Register This register c
4. Datasheet Volume 2 351 Intel QuickPath Architecture System Address Decode Register Description intel 3 6 3 SAD HEN This register is for legacy Hole Enable Device o Function 1 Offset 48h Access as a Dword Bit Type bed Description 31 8 RV 0 Reserved HEN This bit enables a memory hole in DRAM space The DRAM that lies behind 7 RW 0 this space is not remapped 0 No Memory hole 1 Memory hole from 15 MB to 16 MB 6 0 RV 0 Reserved 352 Datasheet Volume 2 Intel QuickPath Architecture System Address Decode Register Description intel 3 6 4 SAD_SMRAM This register is for legacy 9Dh address space Note This register must be programmed consistently with any other registers controlling access to SMM space within the system such as on OH devices if present Device 0 Function 1 Offset 4Ch Access as a Dword Bit Type ts Description 31 15 RV 0 Reserved SMM Space Open D_ OPEN When D_OPEN 1 and D_LCK 0 the SMM space DRAM is made visible even 14 RW 0 when SMM decode is not active This is intended to help BIOS initialize SMM space Software should ensure that D_OPEN 1 and D_CLS 1 are not set at the same time SMM Space Closed D_ CLS When D_CLS 1 SMM space DRAM is not accessible to data references even if SMM decode is active Code references may still access SMM space 13 RW 0 DRAM This will allow SMM software to reference through SMM
5. B D F Type 0 0 0 DMIVCLREMAP Address Offset 9C 9Fh Reset Value 00000000h Access RO A Reset ra Bit Attr Value Description 31 1 RO 90909050 Reserved Invalidation Wait Descriptor Complete IWC Indicates completion of Invalidation Wait Descriptor with Interrupt Flag IF 0 RO Ob A a field Set Hardware implementations not supporting queued invalidations implement this field as reserved 244 Datasheet Volume 2 Processor Configuration Registers intel 2 16 23 IECTL_REG I nvalidation Event Control Register This register specifies the invalidation event interrupt control bits This register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type Address Offset Reset Value Access 0 0 0 DMI VCLREMAP A0 A3h 00000000h RO Bit Attr Reset Value Description 31 RO Ob Interrupt Mask IM 0 No masking of interrupt When a invalidation event condition is detected hardware issues an interrupt message using the I nvalidation Event Data amp Invalidation Event Address register values 1 When implemented this is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is Set 30 RO Ob Interrupt Pending IP Hardware sets the IP field whenever it detec
6. Processor allows cycle to go to DMI resulting in Master Abort DW I O Write to CONFIG_ADDRESS with bit 31 1 y VO Read Write to CONFIG_DATA Dev Enabled amp Bus gt SEC BUS Bus lt SUB BUS Yes Processor Generates DMI Type 1 Configuration Cycle Processor Generates Type 0 Access to PCI Express Device 0 amp Function 0 Processor Claims Device 1 amp Dev 1 Enabled amp Function 0 Processor Claims Device 2 amp Dev 2 Enabled amp Function 0 Processor Claims Processor Generates DMI Typed Configuration Cycles Internal Device Configuration Accesses The processor decodes the Bus Number Bits 23 16 and the Device Number fields of the CONFIG_ADDRESS register If the Bus Number field of CONFIG_ADDRESS is 0 the configuration cycle is targeting a PCI Bus 0 device If the targeted PCI Bus 0 device exists in the processor and is not disabled the configuration cycle is claimed by the appropriate device Datasheet Volume 2 41 2 4 5 2 4 5 1 42 Processor Configuration Registers Bridge Related Configuration Accesses Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs Bus Number 7 0 is Header Byte 8 7 0 e Device Number 4 0 is Header Byte 9 7 3 e Funct
7. Datasheet Volume 2 217 218 Processor Configuration Registers B D F Type Address Offset Reset Value Access 0 0 0 VCOPREMAP F08 FOBh 20004000h RW L RO Bit Attr Reset Value Description 14 10 RO 10000b PEGO VT Completion Tracking Queue Resource Available PEGOVTCTRA Number of entries available in PEGO VT Completion Tracking Queue 1 based The values programmed in the fields below must not be greater than the value advertised in this field Note If device 6 is also enabled the default is 01000b otherwise it is 10000b 9 5 RW L 00000b PEGO VCO Write VT Completion Tracking Queue Resource Threshold PEGOVCOWRCTQRT This field provides a 1 based minimum threshold value used to throttle PEGO VCO Write VT fetch When the number of free PEGO VT Completion Tracking Queue entries equals or falls below the value programmed in this field PEGO VCO Write VT fetch is throttled until the number of free PEGO Completion Tracking Queue entries rise above this threshold For example 00000 Throttle PEGO VCO Write VT Fetch when there is no entry left 00001 Throttle PEGO VCO Write VT Fetch when there is 1 or less entry left 00010 Throttle PEGO VCO Write VT Fetch when there is 2 or less entry left 00011 Throttle PEGO VCO Write VT Fetch when there is 3 or less entry left 00100 Throttle PEGO VCO Write VT Fetch when there is 4 or less entry left 4 0
8. c cceeeeeeeee tees ee teen ees 85 C1DRBO Channel 1 DRAM Rank Boundary Address 0 Register 5 86 C1DRB1 Channel 1 DRAM Rank Boundary Address 1 Register 86 C1DRB2 Channel 1 DRAM Rank Boundary Address 2 Register 5 86 C1DRB3 Channel 1 DRAM Rank Boundary Address 3 Register 5 87 C1DRA01 Channel 1 DRAM Rank 0 1 Attributes Register cee 87 C1DRA23 Channel 1 DRAM Rank 2 3 Attributes Register ceecee 87 C1WRDATACTRL Channel 1 Write Data Control Register eeeee 88 C1CYCTRKPCHG Channel 1 CYCTRK PCHG Register eneee 88 C1CYCTRKACT Channel 1 CYCTRK ACT Register asne 89 C1CYCTRKWR Channel 1 CYCTRK WR Re GisSter c cceeee eee ee ects ee ea ene 90 C1CYCTRKRD Channel 1 CYCTRK READ Register scce 90 C1CKECTRL Channel 1 CKE Control Register cccceeeee erect eee ea ea eae 91 C1PWLRCTRL Channel 1 Partial Write Line Read Control Register 92 C1ODTCTRL Channel 1 ODT Control Register cceceeee eset ects teen eee 92 C1DTC Channel 1 DRAM Throttling Control Register ceeeeeee eee es 93 Datasheet Volume 2 2 8 37 SSKPD Sticky Scratchpad Data Register cccccecee eee ee eee ee ee eee ee neta 94 2 8 38 TSC1 Thermal Sensor Control 1 Register cccceceeeeee eee ee este neta eee ee eas 94 2 8 39 TSS1 Thermal Sensor Status 1 ReGiSter cece ee
9. Datasheet Volume 2 305 intel Processor Configuration Registers 2 19 25 PM_CAPID6 Power Management Capabilities Register 306 B D F Type 0 6 0 PCI Address Offset 80 83h Reset Value C8039001h Access RO n Reset PERA Bit Attr Value Description PME Support PMES This field indicates the power states in which this device may indicate PME 31 27 RO 19h wake using PCI Express messaging DO D3hot amp D3cold This device is not required to do anything to support D3hot amp D3cold it simply must report that those states are supported Refer to the PCI Power Management 1 1 specification for encoding explanation and other power management details D2 Power State Support D2PSS 26 RO Ob Hardwired to 0 to indicate that the D2 power management state is NOT supported D1 Power State Support D1PSS 25 RO Ob Hardwired to 0 to indicate that the D1 power management state is NOT supported Auxiliary Current AUXC 24 22 RO 000b Hardwired to 0 to indicate that there are no 3 3Vaux auxiliary current requirements Device Specific Initialization DSI 21 RO Ob Hardwired to 0 to indicate that special initialization of this device is NOT required before generic class device driver is to use it Auxiliary Power Source APS 20 RO 9B Hardwired to 0 19 RO Ob PME Clock PMECLK Hardwired to 0 to indicate this device does NOT support PMEB generation PCI PM CAP Version PCI PMCV 18 16 RO 011b Ve
10. 161 2 12 2 DMIPVCCAP1 DMI Port VC Capability Register 1 cceeeeeeee eee eee 162 2 12 3 DMIPVCCAP2 DMI Port VC Capability Register 2 cceeeeee eee ee eee 162 2 12 4 DMIPVCCTL DMI Port VC Control Register 0 cccceeeee eee eee eee ee neta eats 163 2 12 5 DMIVCORCAP DMI VCO Resource Capability Register ceeeeeeeee 163 2 12 6 DMIVCORCTLO DMI VCO Resource Control Register ceeeeeeeeeeee ees 164 2 12 7 DMIVCORSTS DMI VCO Resource Status Register secere 165 2 12 8 DMIVC1RCAP DMI VC1 Resource Capability Register eeeeeeeee 165 2 12 9 DMIVC1RCTLI DMI VC1 Resource Control Register ceeeeeeeeeeee ees 166 2 12 10 DMIVC1RSTS DMI VC1 Resource Status RegiSter cee ee ee eeee eee eee 167 2 12 11 DMIVCPRCTL DMI VCp Resource Control Register ceeeeeeeeeeeee tees 168 2 12 12 DMIVCPRSTS DMI VCp Resource Status ReGiSter cceeeeee cere eee eee 169 2 12 13 DMIESD DMI Element Self Description Register cceeeeeeeeeeee ee eae 169 2 12 14 DMILE1D DMI Link Entry 1 Description Register ceeeeeeeeee ee eee ee 170 2 12 15 DMILE1A DMI Link Entry 1 Address Register 170 2 12 16 DMILE2D DMI Link Entry 2 Description Register ceeeeeeeeee eee eee 171 2 12 17 DMILE2A DMI Link Entry 2 Address Register l e 171 2 12 18 DMILCAP DMI Link Capabilities Register ccc erneer ere
11. cceccececene eet eateeeee eat eateeeeeeatentnnes 56 TOUUD Top of Upper Usable DRAM Register cceceeeenteeteeeeeeaeeaeeneees 58 GBSM Graphics Base of Pre allocated Memory Register eeee 58 BGSM Base of GTT Pre allocated Memory RegiSter c ceeeeee eee ee eee 59 TSEGMB TSEG Memory Base ReGjiSteP cceeeceeeee ee ee ee eee eee ee eet ee nena ened 59 TOLUD Top of Low Usable DRAM ReGiSter c cceeeeee teen eeeee eet eeeenanaed 60 PBFC Primary Buffer Flush Control Register cceceeeeeee eset teeter eaeas 61 SBFC Secondary Buffer Flush Control Register ccceeeeeeeeeeeeeee seen ees 61 ERRSTS Error Status Registe csornai anr arinin aN 62 ERRCMD Error Command Register ssssssssssrssrrrerirrrrrrrrnerrnrrrsrrrrrrrrne 63 SMICMD SMI Command Register s sssssissssssrrsrrssrrnnrrnerinsrrnrrrnerrnrrrre 64 SKPD Scratchpad Data Register ssssssrsrsererrrrerrrrrrsrrererserererrererserere 64 CAPIDO Capability Identifier Register cece cette eee eee teeta tata 65 MCSAMPML Memory Configuration System Address Map and Pre allocated Memory Lock Register ccceeeeee ee ee er 65 HBAR REGISteFSiscccsein tsetse tiivbiseds deagarseepiieel Wiiaeie ee Uaa aapa ra iari Eei 66 CSZMAP Channel Size Mapping ReGiSter cc cece eee ee ee eee eeeeee teen eens 68 CHDECMISC Channel Decode Miscellaneous Register
12. eceeeee ee eae 69 CODRBO Channel 0 DRAM Rank Boundary Address 0 Register 05 70 CODRB1 Channel 0 DRAM Rank Boundary Address 1 Register 71 CODRB2 Channel 0 DRAM Rank Boundary Address 2 Register 05 71 CODRB3 Channel 0 DRAM Rank Boundary Address 3 Register 65 72 CODRA01 Channel 0 DRAM Rank 0 1 Attribute Register eee 73 CODRA23 Channel 0 DRAM Rank 2 3 Attribute Register eeeeeee 74 COWRDATACTRL Channel 0 Write Data Control Register eeeeee 74 COCYCTRKPCHG Channel 0 CYCTRK PCHG Register ceee 75 COCYCTRKACT Channel 0 CYCTRK ACT Register eessen 76 COCYCTRKWR Channel 0 CYCTRK WR Register 0 cceeeeee eee eeeeeeea ene ees 77 COCYCTRKRD Channel 0 CYCTRK READ Register eneee 77 COCYCTRKREFR Channel 0 CYCTRK REFR ReGjSteP c eceeeee eee teen eae 78 COPWLRCTRL Channel 0 Partial Write Line Read Control Register 78 COREFRCTRL Channel 0 DRAM Refresh Control Register ceeeeeee 79 COJ EDEC Channel 0 J EDEC Control ReQiSter cccccccceeeeeeeneeteeeeeeeneenees 81 COODT Channel 0 ODT Matrix ReQiSter ccceeeee cece ee ee ee nena teen neta 82 COODTCTRL Channel 0 ODT Control Register ccceceeeee cece eee eeren 84 CODTC Channel 0 DRAM Throttling Control Register eeeeeee eee es 84 CORSTCTL Channel 0 Reset Controls Register
13. 14 8 RO 00h Reserved Port Arbitration Capability PAC 7 0 RO Olh Having only bit 0 set indicates that the only supported arbitration scheme for this VC is non configurable hardware fixed Datasheet Volume 2 163 intel Processor Configuration Registers 2 12 6 DMI VCORCTLO DMI VCO Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0 164 Access B D F Type Address Offset Reset Value 0 0 0 DMIBAR 14 17h 8000_OOFFh RW RO Bit Attr Reset Value Description 31 RO 1b Virtual Channel 0 Enable VCOE For VCO this is hardwired to 1 and read only as VCO can never be disabled 30 27 RO Oh Reserved 26 24 RO 000b Virtual Channel 0 ID VCOID Assigns a VC ID to the VC resource For VCO this is hardwired to 0 and read only 23 20 RO Oh Reserved 19 17 RW 000b Port Arbitration Select PAS This field configures the VC resource to provide a particular Port Arbitration service Valid value for this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource Because only bit 0 of that field is asserted This field will always be programmed to 1 16 8 RO 000h Reserved 7 1 RW 7Fh Traffic Class Virtual Channel 0 Map TCVCOM This field indicates the TCs Traffic Classes
14. cc rererere 278 2 18 20 IQT_REG Invalidation Queue Tail Register ccc eee eee teeta eae 278 2 18 21 IQA REG Invalidation Queue Address RegiSter ccececeeeeeeeeeee eee tees 279 2 18 22 ICS REG Invalidation Completion Status Register ceeeeeeeee eee ee 279 2 18 23 IECTL_REG Invalidation Completion Event Control Register 0 280 2 18 24 IEDATA_REG Invalidation Completion Event Data Register cees 281 2 18 25 EUADDR_REG Invalidation Completion Event Upper Address Register 281 2 18 26 IRTA_REG Interrupt Remapping Table Address Register l c 282 Datasheet Volume 2 2 18 27 IVA_REG Invalidate Address Register ccc iieeetee eee e eee nee rete eta ta een ea ees 283 2 18 28 IOTLB_REG IOTLB Invalidate Register cc ccecetee eset e ete ee ee ee een eeees 284 2 18 29 FRCD_REG Fault Recording Registers cececce eee ee eee eee eee teeta ea enes 286 2 18 30 VTPOLICY VT Policy R QiSter smiriti kirunmi nir aniei aA 287 2 19 PCI DeVice 6 Registers ois iirirn resipi pran inn i io EEO E KAA DERIN EEEE RABENA 288 2 19 1 VID6 Vendor Identification Register sssssssessressrrsrrrrrrerrrrrirrrrrerrrreo 289 2 19 2 DID6 Device Identification Register cceceeeee cece nets ee ee eee e nena en en eee 290 2 19 3 PCICMD6 PCI Command ReGjSteP cece cece reece eee e teense eee eee ne eae 290 2 19 4 PCISTS6 PCI Status ReGiSter cc
15. 47 RO Ob Reserved 46 44 RW 010b Initial Refresh Count INI TREFCNT Initial Refresh Count Value 43 38 RW 10h Direct Rcomp Quiet Window DIRQUIET This configuration setting indicates the amount of refresh_tick events to wait before the service of rcomp request in non default mode of independent rank refresh 37 32 RW 18h Indirect Rcomp Quiet Window INDI RQUI ET This configuration setting indicates the amount of refresh_tick events to wait before the service of rcomp request in non default mode of independent rank refresh 31 27 RW 06h Rcomp Wait RCOMPWAIT This configuration setting indicates the amount of refresh_tick events to wait before the service of rcomp request in non default mode of independent rank refresh 26 RW Ob ZQCAL Enable ZQCALEN This bit enables the DRAM controller to issue ZQCAL commands periodically 25 RW Ob Refresh Counter Enable REFCNTEN This bit is used to enable the refresh counter to count during times that DRAM is not in self refresh but refreshes are not enabled Such a condition may occur due to need to reprogram the DIMMs following a DRAM controller switch This bit has no effect when Refresh is enabled that is there is no mode where Refresh is enabled but the counter does not run so in conjunction with bit 23 REFEN the modes are REFEN REFCNTEN Description 0 0 Normal refresh disable 0 1 Refresh disabled but counter is accum
16. Clearing this bit has no effect The value returned on read of this field is undefined Enable Advanced Fault Logging EAFL This field is valid only for implementations supporting advanced fault logging Software writes to this field to request hardware to enable or disable advanced fault logging 0 Disable advanced fault logging In this case translation faults are reported through the Fault Recording registers 28 RO Ob 1 Enable use of memory resident fault log When enabled translation faults are recorded in the memory resident log The fault log pointer must be set in hardware through SFL field before enabling advanced fault logging Hardware reports the status of the advanced fault logging enable operation through the AFLS field in the Global Status register Value returned on read of this field is undefined Write Buffer Flush WBF This bit is valid only for implementations requiring write buffer flushing Software sets this field to request hardware to flush the root complex internal write buffers This is done to ensure any updates to the memory resident remapping structures are not held in any internal write posting buffers Refer to the VTd specification for details on write buffer flushing requirements Hardware reports the status of the write buffer flushing operation through the WBFS field in the Global Status register Clearing this bit has no effect Value returned on read of this field is u
17. Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Intel Intel Core Intel Scalable Memory Interconnect Intel SMI Intel Virtualization Technology for Directed 1 0 Intel Trusted Execution Technology Intel TXT Intel Management Engine Intel ME Intel Interconnect BIST Intel IBIST and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2011 Intel Corporation All Rights Reserved 2 Datasheet Volume 2 Contents 1 PNErOGDUCTION icc ide k cite ddan BTM a eed dour ana ans eee Mar See ote 13 2 Processor Configuration Registers ccc eaten need 15 2 1 Register Terminology krissa nanih cede EEEE NEREDE daddies enone is 15 2 2 System Address Mah c ccece ec ee ee ener inkin RAin Anini haii 17 2 2 1 Legacy Address Rane iiss de vietasevecian airna rnnr NOD EEN EREDA EA ERNER ES 19 2 2 1 1 DOS Range 0000_0000h 0009_FFFFh a ssseesseeeeereeer eee eee 19 2 2 1 2 Legacy Video Area 000A_0000h 000B_FFFFh aeee 19 2 2 1 3 PAM 000C_0000h 000F_FFFFh ssssssssssrsssrrsssssrrrrnrnsrnrrnrserrrrrnsns 20 2 2 2 Main Memory Address Range 1MB TOLUD ccccccceeeeeeeeeeaeee eae eneeneas 21 2 2 2 1 ISA Hole 15 MB 16 MB ss ssssssssssssssrrrssn
18. 0 Hardware does not support pass through translation type in context entries 1 Hardware supports pass through translation type in context entries Caching Hints CH 0 Hardware does not support OTLB caching hints ALH and EH fields in context entries are treated as reserved 1 Hardware supports IOLTB caching hints through the ALH and EH fields in context entries Extended Interrupt Mode EI M 0 Hardware supports only 8 bit APICIDs Legacy Interrupt Mode on Intel 64 and A 32 platforms and 16 bit APIC IDs on the processor platforms 1 Hardware supports Extended Interrupt Mode 32 bit APIC IDs on Intel 64 platforms This field is valid only when the IR field is reported as Set Interrupt Remapping IR 0 Hardware does not support interrupt remapping 1 Hardware supports interrupt remapping Implementations reporting this field as Set must also support Queued Invalidation QI 1b Device I OTLB Support DI 0 Hardware does not support device IOTLBs 1 Hardware supports Device OTLBs Implementations reporting this field as Set must also support Queued Invalidation QI 1b Queued I nvalidation QI 0 Hardware does not support queued invalidations 1 Hardware supports queued invalidations 260 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 2 0 GFXVTBAR Address Offset 10 17h Reset Value 0000000000001000h Access
19. 00h Reserved 9 4 RO 00h Olh X1 02h X2 04h X4 08h X8 10h X16 All other encodings are reserved Datasheet Volume 2 319 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset B2 B3h Reset Value 1000h Access RO RW1C i Reset ae Bit Attr Value Description Current Link Speed CLS This field indicates the negotiated Link speed of the given PCI Express Link Defined encodings are 3 0 RO Oh 0001b 2 5 GT s PCI Express Link 0010b 5 0 GT s PCI Express Link All other encodings are reserved The value in this field is undefined when the Link is not up 2 19 41 SLOTCAP Slot Capabilities Register Note Hot Plug is not supported on the platform B D F Type 0 6 0 PCI Address Offset B4 B7h Reset Value 00040000h Access RW O RO Reset E Bit Attr Value Description Physical Slot Number PSN 31 19 RW O 0000h This field indicates the physical slot number attached to this Port BIOS Requirement This field must be initialized by BIOS to a value that assigns a slot number that is globally unique within the chassis 18 RW O No Command Completed Support NCCS When set to 1 this bit indicates that this slot does not generate software 1b notification when an issued command is completed by the Hot Plug Controller This bit is only permitted to be set to 1b if the hotplug capable port is able to accept writes to all fields of the Slot Contr
20. 2 2 3 1 1 Case 1 Less than 4 GB of Physical Memory no remap Figure 2 5 Case 1 Less than 4 GB of Physical Memory no remap HOST SYSTEM VIEW 64 MB aligned TOUUD BASE 1 MB aligned TOLUD BASE 1 MB aligned 0 PCI MMIO PHYSICAL MEMORY DRAM CONTROLLER VIEW 4GB EP Stolen EP UMA 0 64 MB BASE Wasted Only if 4G minus PCI MMIO space is greater than 4G minus EP stolen base gt GFX Stolen BASE a GFX Stolen GFX GTT Stolen BASE GFX GTT STOLEN TSEG TSEG BASE SEG SE TSEG LOW DRAM OS VISIBLE lt 4GB 64 MB aligned 1 MB aligned 1 MB aligned 1 MB aligned 1 MB aligned 1 MB aligned Datasheet Volume 2 Populated Physical Memory 2 GB Address Space allocated to memory mapped I O 1 GB Remapped Physical Memory 0 GB TOM 020h 2 GB ME stolen size 00001b 1 MB TOUUD O7FFh 2 GB minus 1 MB 1 MB aligned TOLUD 01F00h 2 GB minus 64 MB 63 MB wasted because MMIO space required is greater than 4G to EP stolen base REMAPBASE 3FFh 64 GB 1 boundary default REMAPLIMIT 000h OGB boundary default 29 intel 2 2 3 1 2 Note Processor Configuration Registers Case 2 Greater than 4 GB of Physical Memory Internal graphics is not supported on the Intel Xeon processor L3406 Figure 2 6 Case 2 Greater than 4 GB of Physical Memory 30 64G RECLA
21. Datasheet Volume 2 Processor Configuration Registers intel 2 10 28 SS_CAPID Subsystem ID and Vendor ID Capabilities Register This capability is used to uniquely identify the subsystem where the PCI device resides Because this device is an integrated part of the system and not an add in device it is anticipated that this capability will never be used However it is necessary because Microsoft will test for its presence B D F Type 0 1 0 PCI Address Offset 88 8Bh Reset Value 0000800Dh Access RO Reset EEP Bit Attr Value Description 31 16 RO 0000h Reserved Pointer to Next Capability PNC 15 8 RO 80h This contains a pointer to the next item in the capabilities list which is the PCI Power Management capability Capability ID CID 7 0 RO ODh Value of ODh identifies this linked list item capability structure as being for SSID SSVID registers in a PCI to PCI Bridge 2 10 29 SS Subsystem ID and Subsystem Vendor ID Register System BIOS can be used as the mechanism for loading the SSID SVID values These values must be preserved through power management transitions and a hardware reset B D F Type 0 1 0 PCI Address Offset 8C 8Fh Reset Value 00008086h Access RW O Reset ee Bit Attr Value Description Subsystem ID SSID 1 16 RW O 0000h 4 This field identifies the particular subsystem and is assigned by the vendor Subsystem Vendor ID S
22. Reset Pare Bit Attr Value Description 15 12 RO Oh Reserved SMI on Processor Thermal Sensor Trip TSTSMI 1 ASMI DMI special cycle is generated by the processor when the thermal 11 RW 0b sensor trip requires an SMI A thermal sensor trip point cannot generate more than one special cycle 0 Reporting of this condition using SMI messaging is disabled 10 2 RO 000h Reserved 1 RW Ob Reserved 0 RW Ob Reserved 2 7 27 SKPD Scratchpad Data Register This register holds 32 writable bits with no functionality behind them It is for the convenience of BIOS and graphics drivers B D F Type 0 0 0 PCI Address Offset DC DFh Reset Value 0000_0000h Access RW Reset TRET Bit Attr Value Description 31 0 RW 0000000 Scratchpad Data SKPD 1 DWORD of data storage 64 Datasheet Volume 2 Processor Configuration Registers 7 2 7 28 CAPI DO Capability I dentifier Register This register is used to report various processor capabilities B D F Type 0 0 0 PCI Address Offset E0 EBh Reset Value SKU dependent Access RO 5 Reset kaii Bit Attr Value Description 96 35 RO Reserved DMFC DDR3 Maximum Frequency Capability This field controls which values may be written to the Memory Frequency Select field 6 4 of the Clocking Configuration registers MCHBAR Offset C00h Any attempt to write an unsupported value will be ignored 000 GMCH capable of All memory frequencie
23. Reset ae Bit Attr Value Description 31 16 RO 0000h Reserved Fault Record Index FRI This field is valid only when the PPF field is set 15 8 RO V S 00h The FRI field indicates the index from base of the fault recording register to which the first pending fault was recorded when the PPF field was set by hardware The value read from this field is undefined when the PPF field is clear 7 RO Ob Reserved Invalidation Time out Error ITE Hardware detected a Device I OTLB invalidation completion time out At this 6 RW1C Ob time a fault event may be generated based on the programming of the Fault S Event Control register Hardware implementations not supporting Device OTLBs implement this bit as reserved Invalidation Completion Error 1 CE Hardware received an unexpected or invalid Device OTLB invalidation RWIC completion This could be due to either an invalid ITag or invalid source id in an 5 S J Ob invalidation completion response At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting Device OTLBs implement this bit as reserved Invalidation Queue Error 1QE Hardware detected an error associated with the invalidation queue This could be due to either a hardware error while fetching a descriptor from the 4 RO Ob invalidation queue or hardware detecting an erroneous or invalid descriptor in the invalidation queue At this time a fault event
24. e Device 2 Intel QPI Device 2 Function 0 contains the Intel QuickPath Interconnect configuration registers for Intel QPI Link O and resides at DID of 2D10h Device 2 Function 1 contains the physical layer registers for Intel QPI Link O and resides at DID of 2D11h Each component in the processor is uniquely identified by a PCI bus address consisting of Bus Number Device Number and Function Number Device configuration is based on the PCI Type 0 configuration conventions All processor registers appear on the PCI bus assigned for the processor socket Bus number is derived by the maximum bus range setting and processor socket number Table 3 2 Functions Specifically Handled by the Processor Component Register Group DID Device Function Inte QuickPath Architecture Generic Non core 2C61h 0 Registers 0 Intel QuickPath Architecture System Address Decoder 2D01h l Processor Intel QPI Link 0 2D10h 0 Intel QPI Physical 0 2D11h 1 2 Intel Reserved 2D12h 2 Intel Reserved 2D13h 3 Datasheet Volume 2 337 Intel QuickPath Architecture System Address Decode Register Description intel 3 3 Detailed Configuration Space Maps Table 3 3 Device 0 Function 0 Generic Non core Registers DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR OCh 8Ch 10h 90h 14h 94h
25. Datasheet Volume 2 Processor Configuration Registers intel 2 19 36 DCTL Device Control Register This register provides control for PCI Express device specific capabilities The error reporting enable bits are in reference to errors detected by this device not error messages received across the link The reporting of error messages ERR_CORR ERR_NONFATAL ERR_FATAL received by Root Port is controlled exclusively by Root Port Command Register B D F Type 0 6 0 PCI Address Offset A8 A9h Reset Value 0000h Access RW RO Reset Peer Bit Attr Value Description 15 RO Oh Reserved 14 12 RO 000b Reserved for Max Read Request Size MRRS 11 RO Ob Reserved for Enable No Snoop 10 RO Ob Reserved 9 RO Ob Reserved 8 RO Ob Reserved Max Payload Size MPS 000 128B maximum supported payload for Transaction Layer Packets TLP As a receiver the Device must handle TLPs as large as the set value as transmitter the Device must not generate TLPs exceeding 7 5 RW 000b the set value All other encodings are reserved Hardware will actually ignore this field It is writeable only to support compliance testing 4 RO Ob Reserved for Enable Relaxed Ordering Unsupported Request Reporting Enable URRE When set this bit allows signaling ERR_NONFATAL ERR_FATAL or ERR_CORR to the Root Control register when detecting an unmasked 3 RW Ob Unsupported Request UR An ERR_CORR is signale
26. Datasheet Volume 2 Processor Configuration Registers 2 10 48 LSTS2 Link Status 2 Register B D F Type 0 1 0 PCI Address Offset D2 D3h Reset Value 0000h Access RO g Reset eee Bit Attr Value Description 15 1 RO 0000h Reserved Current De emphasis Level CURDELVL 1 3 5 dB 0 RO Ob 0 640B When the link is operating at 2 5 GT s speed this bit is Ob 2 10 49 PEGLC PCI Express Legacy Control Register This register controls functionality that is needed by Legacy non PCI Express aware OS s during run time B D F Type 0 1 0 PCI Address Offset EC EFh Reset Value 0000_0000h Access RO RW 5 Reset EER Bit Attr Value Description 31 3 RO Aa a Reserved PME GPE Enable PMEGPE 0 Do not generate GPE PME message when PME is received 2 RW Ob 1 Generate a GPE PME message when PME is received Assert_ PMEGPE and Deassert_PMEGPE messages on DMI This enables the MCH to support PMEs on the PEG port under legacy OSs Hot Plug GPE Enable HPGPE 0 Do not generate GPE Hot Plug message when Hot Plug event is 1 RW Ob received 1 Generate a GPE Hot Plug message when Hot Plug Event is received Assert_HPGPE and Deassert_HPGPE messages on DMI This enables the MCH to support Hot Plug on the PEG port under legacy OSs General Message GPE Enable GENGPE 0 Do not forward received GPE assert de assert messages 1 Forward received GPE assert de asser
27. Domain page selective invalidation request The target address mask and invalidation hint must be specified in the Invalidate Address register and the domain id must be provided in the DID field 100 111 Reserved Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalidation request by clearing the IVT field At this time the granularity at which actual invalidation was performed is reported through the IAIG field 212 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 108 10Fh Reset Value 0000000000000000h Access RW RO Reset er Bit Attr Value Description 1OTLB Actual I nvalidation Granularity 1 Al G Hardware reports the granularity at which an invalidation request was processed through this field at the time of reporting invalidation completion by clearing the IVT field The following are the encodings for the IAIG field 000 Reserved This indicates hardware detected an incorrect invalidation request and ignored the request Examples of incorrect invalidation requests include detecting an unsupported address mask value in Invalidate Address register for page selective invalidation requests 001 Global Invalidation performed This could be in response to a global 59 57 RO Oh domain selective domain page selective or
28. Figure 2 7 Case 3 4 GB or less of Physical Memory Internal graphics is not supported on the Intel Xeon processor L3406 4 GB or Less of Physical Memory PHYSICAL MEMORY Raabe DRAM CONTROLLER VIEW 64 GB MMO TOUUD BASE Pease Pe 64 MB aligned N RECLAIM BASE 64 MB aligned TOLUD BASE 64 MB aligned 0 TOM N EP UMA 1 64 MB Stolen BASE 0MB bs 63 MB Wasted PCI MMIO i GFX Stolen GFX Stolen BASE GFX GTT Stolen GFX GTT Stolen BASE TSEG TSEG BASE TSEG Os LOW DRAM VISIBLE lt 4GB 0 gt 64 MB aligned 1 MB aligned 64 MB aligned 64 MB aligned for reclaim 1 MB aligned 1 MB aligned 1 MB aligned In this case the amount of memory remapped is the range between TOLUD and TOM minus the ME stolen memory This physical memory will be mapped to the logical address range defined between the REMAPBASE and the REMAPLIMIT registers Example 3 GB Physical Memory with 2 GB allocated to Memory Mapped I O Datasheet Volume 2 Populated Physical Memory 3 GB Address Space allocated to memory mapped I O 2 GB Remapped Physical Memory 1 GB TOM 030h 3 GB ME stolen size 00000b 0 MB TOUUD 1400h 5GB 1 MB aligned TOLUD 02000h 2 GB 64 MB aligned because remap is enabled and the remap register has 64 MB granularity REMAPBASE 040h 4 GB REMAPLIMIT O4Fh 5 GB 1 boundary 31 m t 1 Processor Configur
29. Indicates hardware accesses to remapping structures are coherent Hardware access to advanced fault log and invalidation queue are always coherent Datasheet Volume 2 Processor Configuration Registers intel 2 16 4 GCMD_REG Global Command Register This register controls DMA remapping hardware If multiple control fields in this register need to be modified software must serialize the modifications through multiple writes to this register B D F Type 0 0 0 DMI VCLREMAP Address Offset 18 1Bh Reset Value 00000000h Access W RO Reset EUPA Bit Attr Value Description Translation Enable TE Software writes to this field to request hardware to enable disable DMA remapping hardware 0 Disable DMA remapping 1 Enable DMA remapping Hardware reports the status of the translation enable operation through the TES field in the Global Status register 31 Ww Ob There may be active DMA requests in the platform when software updates this field Hardware must enable or disable remapping logic only at deterministic transaction boundaries so that any in flight transaction is either subject to remapping or not at all Hardware implementations supporting DMA draining must drain any in flight DMA read write requests queued within the root complex before completing the translation enable command and reflecting the status of the command through the TES field in the GSTS_ REG Value re
30. Oh Primary Fault Overflow PFO Hardware sets this field to indicate overflow of fault recording registers Software writing 1 clears this field 198 Datasheet Volume 2 Processor Configuration Registers intel 2 15 9 FECTL_REG Fault Event Control Register This register specifies the fault event interrupt message control bits The VTd specification describes hardware handling of fault events B D F Type 0 0 0 VCOPREMAP Address Offset 38 3Bh Reset Value 80000000h Access RW RO Reset re Bit Attr Value Description Interrupt Mask IM 0 No masking of interrupt When a interrupt condition is detected hardware issues an interrupt message using the Fault Event Data amp 31 RW 1b Fault Event Address register values 1 This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is set Interrupt Pending IP Hardware sets the IP field whenever it detects an interrupt condition An interrupt condition is defined as e When primary fault logging is active an interrupt condition occurs when hardware records a fault through one of the Fault Recording registers and sets the PPF field in Fault Status register If the PPF field was already set at the time of recording a fault it is not treated as a new interrupt condition e When advanced fault logging is active an inter
31. On IOTLB invalidations hardware does not support draining of 55 RO 1b translated DMA read requests queued within the root complex 1 On IOTLB invalidations hardware supports draining of translated DMA read requests queued within the root complex Indicates supported architecture version DMA Write Draining DWD 0 On IOTLB invalidations hardware does not support draining of 54 RO 1b translated DMA writes queued within the root complex 1 IOTLB invalidations hardware supports draining of translated DMA writes queued within the root complex Maximum Address Mask Value MAMV 53 48 RO 00h The value in this field indicates the maximum supported value for the Address Mask AM field in the Invalidation Address IVA_REG register Number of Fault Recording Registers NFR Number of fault recording registers is computed as N 1 where N is the value reported in this field 47 40 RO 00h Implementations must support at least one fault recording register NFR 0 for each DMA remapping hardware unit in the platform The maximum number of fault recording registers per DMA remapping hardware unit is 256 Page Selective I nvalidation Support PSI 0 Hardware supports only domain and global invalidates for OTLB 39 RO Ob 1 Hardware supports page selective domain and global invalidates for IOTLB and hardware must support a minimum MAMV value of 9 38 RO Ob Reserved Super Page support SPS This field indicates the super page sizes supp
32. The MCP supports PEG port upper prefetchable base limit registers This allows the PEG unit to claim IO accesses above 36 bit complying with the PCI Express Base Specificaiton 2 1 Addressing of greater than 4 GB is allowed on either the DMI Interface or PCI Express interface The MCP supports a maximum of 16 GB of DRAM No DRAM memory will be accessible above 16 GB DRAM capacity is limited by the number of address pins available When running in internal graphics mode Tilex Tiley linear reads writes to GMADR range are supported Write accesses to GMADR linear regions are supported from both DMI and PEG GMADR write accesses to tileX and tileY regions defined using fence registers are not supported from DMI or the PEG port GMADR read accesses are not supported from either DMI or PEG In the following sections it is assumed that all of the compatibility memory ranges reside on the DMI Interface The exception to this rule is VGA ranges which may be mapped to PCI Express or DMI or to the internal graphics device IGD In the absence of more specific references cycle descriptions referencing PCI should be interpreted as the DMI Interface PCI while cycle descriptions referencing PCI Express or IGD are related to the PCI Express bus or the internal graphics device respectively The processor does not remap APIC or any other memory spaces above TOLUD Top of Low Usable DRAM The TOLUD register is set to the appropriate value by BIOS The rem
33. This configuration setting indicates the mode in which the controller is operating 000 Post Reset state 001 NOP Command Enable 010 All Banks Pre charge Enable 011 Mode Register Set Enable 100 Extended Mode Register Set Enable 101 Reserved 110 CBR Refresh Enable 111 Normal mode of operation Ob Reserved Datasheet Volume 2 81 82 Processor Configuration Registers COODT Channel O ODT Matrix Register This is an ODT related configuration register It is BIOS responsibility to program these bits to turn on off the DRAM ODT signals according to how the system is populated that is 2r 2r 2r 1r 1r 2r 1r 1r 2r nc nc 2r 1r nc nc 1r This software approach has the benefit of simplifying the hardware helping PV and increasing greater flexibility in ODT choices especially when multiple ODT are required to be turned on B D F Type 0 0 0 MCHBAR Address Offset 298 29Bh Reset Value 0000 _0000h Access RW RO Reset Pe Bit Attr Value Description 31 20 RO 000h Reserved DODTAOS3 sd0O_cr_dodtao_r3 19 RW Ob Force DRAM ODT Always ON for rank3 1 ON 0 OFF except during self refresh commands DODTAOZ2 sd0O_cr_dodtao_r2 18 RW Ob Farce DRAM ODT Always ON for rank2 1 ON 0 OFF except during self refresh commands DODTAO1 sd0O_cr_dodtao_r1 17 RW Ob Force DRAM ODT Always ON for rank1 1 ON 0 OFF except during
34. 00000000h RO Bit Attr Reset Value Description 31 RO Ob Translation Enable Status TES This field indicates the status of DMA remapping hardware 0 DMA remapping hardware is not enabled 1 DMA remapping hardware is enabled 30 RO Ob Root Table Pointer Status RTPS This field indicates the status of the root table pointer in hardware This field is cleared by hardware when software sets the SRTP field in the Global Command register This field is set by hardware when hardware completes the set root table pointer operation using the value provided in the Root Entry Table Address register 29 RO Ob Fault Log Status FLS This field e Is cleared by hardware when software Sets the SFL field in the Global Command register e Is Set by hardware when hardware completes the set fault log pointer operation using the value provided in the Advanced Fault Log register 28 RO Ob Advanced Fault Logging Status AFLS This field is valid only for implementations supporting advanced fault logging It indicates the advanced fault logging status 0 Advanced Fault Logging is not enabled 1 Advanced Fault Logging is enabled Datasheet Volume 2 Processor Configuration Registers B D F Type Address Offset Reset Value Access 0 2 0 GFXVTBAR 1C 1Fh 00000000h RO Bit Attr Reset Value Description 27 RO Ob Write Buffer Flush Status
35. 00000000h Access RO Reset gs Bit Attr Value Description Extended I nterrupt Message Data EI MD This field is valid only for implementations supporting 32 bit interrupt data 31 16 RO 0000h fields Hardware implementations supporting only 16 bit interrupt data treat this field as reserved Interrupt Message Data IMD 15 0 RO 0000h Data value in the interrupt request Software requirements for programming this register are described in the VTd specification 2 16 25 EADDR_REG Invalidation Event Address Register This register specifies the Invalidation Event Interrupt message address This register is treated as reserved by implementations reporting Queued I nvalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 DMIVCLREMAP Address Offset A8 ABh Reset Value 00000000h Access RO Reset ii Bit Attr Value Description Message Address MA 00000000 When fault events are enabled the contents of this register specify the 31 2 RO h DWORD aligned address bits 31 2 for the interrupt request Software requirements for programming this register are described in the VTd specification Section 5 7 1 0 RO 00b Reserved 246 Datasheet Volume 2 Processor Configuration Registers intel 2 16 26 IEUADDR_REG Invalidation Event Upper Address Register This register specifies the Invalidation Event interrupt message upper addres
36. Address Offset 8h Reset Value 08h Access RO Bit Attr Reset Description Value Revision Identification Number RID This is an 8 bit value that indicates the revision identification number for the 7 0 RO 12h processor Device 0 Refer to the Intel Core i5 600 and i3 500 Desktop Processor Series and Intel Pentium Desktop Processor 6000 Series Specification Update for the value of the Revision ID Register 2 7 6 CC Class Code Register This register identifies the basic function of the device a more specific sub class and a register specific programming interface B D F Type 0 0 0 PCI Address Offset 9 Bh Reset Value 060000h Access RO Reset Saati Bit Attr Value Description Base Class Code BCC 23 16 RO 06h This is an 8 bit value that indicates the base class code for the processor This code has the value 06h indicating a Bridge device Sub Class Code SUBCC 15 8 RO 00h This is an 8 bit value that indicates the category of Bridge into which the processor falls The code is 00h indicating a Host Bridge Programming I nterface PI This is an 8 bit value that indicates the programming interface of this device This value does not specify a particular register set layout and provides no practical use for this device 7 0 RO 00h 2 7 7 MLT Master Latency Timer Register Device 0 in the processor is not a PCI master Therefore this register is no
37. Bit Attr Value Description Context Actual I nvalidation Granularity CAI G Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion by clearing the ICC field The following are the encodings for the CAIG field 00 Reserved 60 59 RO 00b 01 Global Invalidation performed This could be in response to a global domain selective or device selective invalidation request 10 Domain selective invalidation performed using the domain id specified by software in the DID field This could be in response to a domain selective or device selective invalidation request 11 Device selective invalidation performed using the source id and domain id specified by software in the SID and FM fields This can only be in response to a device selective invalidation request 58 34 RO 0000000h Reserved Function Mask FM Software may use the Function Mask to perform device selective invalidations on behalf of devices supporting PCI Express Phantom Functions This field specifies which bits of the function number portion least significant three bits of the SID field to mask when performing device selective invalidations The following encodings are defined for this field 33 32 w 00b 00 No bits in the SID field masked 01 Mask most significant bit of function number in the SID field 10 Mask two most significant bit of function nu
38. Device 1 Internal Graphics Device Device 2 Secondary Host to PCI Express Bridge Device 6 Device 6 is not supported on all SKUs Configuration Mechanisms The GMCH is the originator of configuration cycles Internal to the GMCH transactions received through both configuration mechanisms are translated to the same format Standard PCI Configuration Mechanism The following is the mechanism for translating GMCH I O bus cycles to configuration cycles The PCI specification defines a slot based configuration space that allows each device to contain up to eight functions with each function containing up to 256 8 bit configuration registers The PCI specification defines two bus cycles to access the PCI configuration space Configuration Read and Configuration Write Memory and I O spaces are supported directly by the GMCH Configuration space is supported by a mapping mechanism implemented within the GMCH The configuration access mechanism makes use of the CONFIG_ADDRESS Register at I O address OCF8h though OCFBh and CONFIG_DATA Register at O address OCFCh though OCFFh To reference a configuration register a DW I O write cycle is used to place a value into CONFIG_ADDRESS that specifies the PCI bus the device on that bus the function within the device and a specific configuration register of the device function being accessed CONFIG_ADDRESS 31 must be 1 to enable a configuration cycle CONFIG_DATA then becomes a window
39. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state Reads of this field must reflect the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined 9 8 RO 00b 00 Reserved 01 On 10 Blink 11 Off If the Power Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b 322 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset B8 B9h Reset Value 0000h Access RO RW i Reset Higi Bit Attr Value Description Reserved for Attention Indicator Control AIC If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state Reads of this field must reflect the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined If the indicator is electrically controlled by chassis the indicator is controlled 7 6 RO 00b directly by the downstream port through implementation specific mechanisms 00 Reserved 01 On 10 Blink 11 Off If the Attention Indicator Present bi
40. Indicates the remapping hardware unit blocks and treats as fault zero 22 RO Ob length DMA read requests to write only pages 1 Indicates the remapping hardware unit supports zero length DMA read requests to write only pages Maximum Guest Address Width MGAW This field indicates the maximum DMA virtual addressability supported by remapping hardware The Maximum Guest Address Width MGAW is computed as N 1 where N is the value reported in this field For example a hardware implementation supporting 48 bit MGAW reports a value of 47 101111b in this field 21 16 RO 23h If the value in this field is X untranslated and translated DMA requests to addresses above 2 x 1 1 are always blocked by hardware Translation requests to address above 2 X 1 1 from allowed devices return a null Translation Completion Data Entry with R W 0 Guest addressability for a given DMA request is limited to the minimum of the value reported through this field and the adjusted guest address width of the corresponding page table structure Adjusted guest address widths supported by hardware are reported through the SAGAW field 15 13 RO 000b Reserved Supported adjusted guest address width SAGAW This 5 bit field indicates the supported adjusted guest address widths which in turn represents the levels of page table walks for the 4KB base page size supported by the hardware implementation A value of 1 in any of these bits indic
41. It returns a 1b to indicate the DL_Active state Ob otherwise This bit must be implemented if the corresponding Data Link Layer Active Capability bit is implemented Otherwise this bit must be hardwired to Ob 12 RO 1b Slot Clock Configuration SCC 0 The device uses an independent clock irrespective of the presence of a reference on the connector 1 The device uses the same physical reference clock that the platform provides on the connector 11 RO Ob Link Training LTRN This bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun Hardware clears this bit when the LTSSM exits the Configuration Recovery state once Link training is complete 10 RO Ob Undefined Undefined The value read from this bit is undefined In previous versions of this specification this bit was used to indicate a Link Training Error System software must ignore the value read from this bit System software is permitted to write any value to this bit 146 Datasheet Volume 2 Processor Configuration Registers Access B D F Type Address Offset Reset Value 0 1 0 PCI B2 B3h 1000h RW1C RO Bit Attr Reset Value Description 9 4 RO 00h Negotiated Link Width NLW This field indicates negotiated link width This field is valid only when the link i
42. Memory Map to PCI Express Device Configuration Space FFFFFFFh FFFFFh 7FFFh kpr Bus 255 Device 31 Function 7 PCI Express Extended Configuration Space PCI Compatible Configuration Device 1 Function 1 Space FFFFFh PCI Compatible Device 0 Function 0 Configuration 1FFFFFh Space Header 0 Located by PCI Express Base Address Datasheet Volume 2 39 m t l Processor Configuration Registers 2 4 3 40 Just the same as with PCI devices each device is selected based on decoded address information that is provided as a part of the address portion of Configuration Request packets A PCI Express device will decode all address information fields bus device function and extended address numbers to provide access to the correct register To access this space step 1 is done only once by BIOS First determine the maximum bus number using the following algorithm 1 Write to I O address OCF8h with value 80FF_1050h 2 Read from I O address OCFCh If the value is FFFF_FFFFh master abort then go to step 3 otherwise max bus number is FFh 3 Write to I O address OCF8h with value 807F_1050h 4 Read from I O address OCFCh If the value is FFFF_FFFFh master abort then maximum bus number is 3Fh otherwise maximum bus number is 7Fh Write to the PCIEXBAR register at the maximum bus number device 2 function 0 offset 50h Write 1 to bit O of the register to enable the enhanced configuration
43. Prefetchable Memory Address Limit PMLI MIT 15 4 RW 000h This field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express G 64 bit Address Support 3 0 RO th This field indicates that the upper 32 bits of the prefetchable memory region limit address are contained in the Prefetchable Memory Base Limit Address register at 2Ch PMBASEU1 Prefetchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implementation This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 1 0 PCI Address Offset 28 2Bh Reset Value 0000_0000h Access RW Reset gee Bit Attr Value Description 0000 000 Prefetchable Memory Base Address
44. Processor Configuration Registers B D F Type Address Offset Reset Value 0 0 0 MCHBAR 2B4 2B7h 0000_0000h Access RO RW L K RW L i Reset Kizi Bit Attr Value Description Time Constant TC 000 2 28 Clocks 001 2 29 Clocks noe RWL 009b 010 2 30 Clocks 011 2 31 Clocks Others Reserved Weighted Average Bandwidth Limit WAB a Average weighted bandwidth allowed per clock during bandwidth based 15 8 RW L 00h J throttling The processor does not allow any transactions to proceed on the System Memory bus if the output of the filter equals or exceeds this value Weighted Average Thermal Limit WAT Average weighted bandwidth allowed per clock during for thermal sensor 7 0 RW L 00h enabled throttling The processor does not allow any transactions to proceed on the System Memory bus if the output of the filter equals or exceeds this value 2 8 21 CORSTCTL Channel 0O Reset Controls Register This register contains all the reset controls for the DDR 10 buffers B D F Type 0 0 0 MCHBAR Address Offset 5D8h Reset Value OEh Access RW P RO i Reset Pare Bit Attr Value Description 7 1 RO 00h Reserved DRAM IO Buffers Activate I OBUFACT This bit controls BOTH channels This bit is cleared to 0 during reset and remains inactive even after reset de asserts until it is set to 1 by BIOS If at 0 RW S Ob any time this bit is cleared both channels 1O
45. Programming Interface PI When MCHBAR offset 44 bit 31 is 0 this value is 00h indicating a Display 7 0 RO 00h Controller When MCHBAR offset 44 bit 31 is 1 this value is 00h indicating a NOP Datasheet Volume 2 177 Processor Configuration Registers intel 2 13 7 CLS Cache Line Size Register The IGD does not support this register as a PCI slave B D F Type 0 2 0 PCI Address Offset Ch Reset Value 00h Access RO Reset P Bit Attr Value Description Cache Line Size CLS 7 0 RO 00h This field is hardwired to Os The IGD as a PCI compliant master does not use i the Memory Write and Invalidate command and in general does not perform operations based on cache line size 2 13 8 MLT2 Master Latency Timer Register The IGD does not support the programmability of the master latency timer because it does not perform bursts B D F Type 0 2 0 PCI Address Offset Dh Reset Value 00h Access RO P Reset EA Bit Attr Value Description 7 0 RO 00h Master Latency Timer Count Value MLTCV Hardwired to Os 2 13 9 HDR2 Header Type Register This register contains the Header Type of the IGD B D F Type 0 2 0 PCI Address Offset Eh Reset Value 00h Access RO A Reset rar Bit Attr Value Description Multi Function Status MFUNC 7 RO Ob Indicates if the device is a Multi Function Device The value is hardwired to 0 to indi
46. RW AA ABh DSTS Device Status 0000h RO RW1C AC AFh LCAP Link Capabilities 02214D02h RO RW O BO B1h LCTL Link Control 0000h RO BRW B2 B3h LSTS Link Status 1000h RWIC RO B4 B7h SLOTCAP Slot Capabilities 00040000h RW O RO B8 B9h SLOTCTL Slot Control 0000h RO RW BA BBh SLOTSTS Slot Status 0000h RO RW1C BC BDh RCTL Root Control 0000h RW RO BE BFh RSVD Reserved Oh RO CO C3h RSTS Root Status 0000_0000h RO RW1C DO Dih LCTL2 Link Control 2 0002h RO RWS D2 D3h LSTS2 Link Status 2 0000h RO EC EFh PEGLC PCI Express G Legacy Control 0000_0000h RO RW Datasheet Volume 2 Processor Configuration Registers intel 2 10 1 VI D1 Vendor Identification Register This register combined with the Device Identification register uniquely identify any PCI device B D F Type 0 1 0 PCI Address Offset 0 1h Reset Value 8086h Access RO Reset icak Bit Attr Value Description Vendor Identification VI D1 15 0 RO 8086h PCI standard identification for Intel 2 10 2 DI D1 Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device B D F Type 0 1 0 PCI Address Offset 2 3h Reset Value 0041h Access RO Reset ceca Bit Attr Value Description Device Identification Number DID1 UB 15 4 RO 004h Identifier assigned to the processor device 1 virtual PCI to PCI bridge PCI Express Graphics port Device
47. Reserved Datasheet Volume 2 69 m t 1 Processor Configuration Registers 70 CODRBO Channel 0 DRAM Rank Boundary Address 0 Register The DRAM Rank Boundary Registers define the upper boundary address of each DRAM rank with a granularity of 64 MB Each rank has its own single word DRB register These registers are used to determine which chip select will be active for a given address Channel and rank map cho rankO 200h cho rank1 202h cho rank2 204h cho rank3 206h ch1 rankO 600h ch1 rank1 602h ch1 rank2 604h ch1 rank3 606h Programming guide If Channel 0 is empty all of the CODRBs are programmed with 00h CODRBO Total memory in chO rankO in 64 MB increments CODRB1 Total memory in chO rankO chO rank1 in 64 MB increments and so on If Channel 1 is empty all of the C1DRBs are programmed with OOh C1DRBO Total memory in ch1 rankO in 64 MB increments C1DRB1 Total memory in ch1 rankO ch1 rank1 in 64 MB increments and so on B D F Type 0 0 0 MCHBAR Address Offset 200 201h Reset Value 0000h Access RW L RO Reset Pare Bit Attr Value Description 15 10 RO 00h Reserved Channel 0 DRAM Rank Boundary Address 0 CODRBAO This register defines the DRAM rank boundary for rankO of Channel 0 64 MB granularity RO 9 0 RW L 000h RO Total rankO memory size 64 MB R1 Total rankl memory size 64 MB R2 Total rank2 memory size 64 MB R3 Total rank3 memory si
48. Root Control Register This register allows control of PCI Express Root Complex specific parameters The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error reported in this device s Device Status register or when an error message is received across the link Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register B D F Type 0 6 0 PCI Address Offset BC BDh Reset Value 0000h Access RO RW Reset F Bit Attr Value Description 15 5 RO 000h Reserved Reserved for CRS Software Visibility Enable CSVE This bit when set enables the Root Port to return Configuration Request Retry Status CRS Completion Status to software Root Ports that do not implement this capability must hardwire this bit to Ob PME Interrupt Enable PMEIE 0 No interrupts are generated as a result of receiving PME messages 3 RW Ob 1 Enables interrupt generation upon receipt of a PME message as reflected in the PME Status bit of the Root Status Register A PME interrupt is also generated if the PME Status bit of the Root Status Register is set when this bit is set from a cleared state System Error on Fatal Error Enable SEFEE This bit controls the Root Complex s response to fatal errors 2 RW Ob 0 No SERR generated on receipt of fatal error 1 Indicates that a SERR should be generated if a fatal
49. System software reads this field to determine the number of messages being requested by this device 000 1 All of the following are reserved in this implementation 001 2 3 1 RO 000b 010 4 011 8 100 16 101 32 110 Reserved 111 Reserved MSI Enable MSIEN Controls the ability of this device to generate MSIs 0 RW Ob 0 MSI will not be generated 1 MSI will be generated when we receive PME or HotPlug messages INTA will not be generated and INTA Status PCISTS1 3 will not be set Datasheet Volume 2 Processor Configuration Registers 2 19 31 MA Message Address Register B D F Type 0 6 0 PCI Address Offset 94 97h Reset Value 00000000h Access RW RO 5 Reset Pe Bit Attr Value Description Message Address MA 31 2 RW 00000000 This field is used by system software to assign an MSI address to the device h The device handles an MSI by writing the padded contents of the MD register to this address Force DWord Align FDWA 1 0 RO 00b Hardwired to 0 so that addresses assigned by system software are always aligned on a dword address boundary 2 19 32 MD Message Data Register B D F Type 0 6 0 PCI Address Offset 98 99h Reset Value 0000h Access RW r Reset er Bit Attr Value Description Message Data MD Base message data pattern assigned by system software and used to handle 15 0 RW 0000h an MSI from the device l l l l When the device mus
50. VCOPREMAP Address Offset 90 97h Reset Value 0000000000000000h Access RW RO Reset aa Bit Attr Value Description Invalidation Queue Base Address IQA 00000000 This field points to the base of 4 KB aligned invalidation request queue 63 12 RW 00000h Hardware ignores and not implement bits 63 HAW where HAW is the host address width Reads of this field return the value that was last programmed to it 11 3 RO 000h Reserved Queue Size QS 2 0 RW Oh This field specifies the size of the invalidation request queue A value of X in this field indicates an invalidation request queue of X 1 4 KB pages The number of entries in the invalidation queue is 2 X 8 Datasheet Volume 2 207 intel Processor Configuration Registers 2 15 22 ICS REG Invalidation Completion Status Register This register reports the completion status of invalidation wait descriptor with Interrupt Flag IF Set This register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 9C 9Fh Reset Value 00000000h Access RO RW1C S Reset mate Bit Attr Value Description 31 1 RO 90000099 Reserved Invalidation Wait Descriptor Complete IWC 0 RW1C Ob This bit indicates completion of Invalidation Wait Descriptor with Interrupt S Flag IF field Set Hardware implementations not supporting
51. When this bit is set it freezes the FSM when initialization aborts 11 RW 0 DISABLE_ISI_CHECK Defeature mode to disable ISI checking during Polling _LaneDeskew state 10 8 RW 0 INIT_ MODE i Hee REN Initialization mode that determines altered initialization modes LINK_SPEED Identifies slow speed or at speed operation for the Intel QPI port RW 0 1 Force direct operational speed initialization 0 Slow speed initialization 6 RV 0 Reserved 5 RW 1 PHYI NI TBEGI N Instructs the port to start initialization 4 RW 0 SINGLE_ STEP Enables single step mode 3 RW 0 LAT_FIX_CTL If set instructs the remote agent to fix the latency BYPASS_ CALIBRATION Indicates the physical layer to bypass 2 RW 0 P 75 calibration 1 RW 0 RESET_MODIFIER Modifies soft reset to default reset when set 0 RWIS 0 PHY_ RESET Physical Layer Reset 358 Datasheet Volume 2 Intel QuickPath Architecture System Address Decode Register Description 3 8 3 QPI_O PH_PIS QPI_1_PH_PIS This is an Intel QPI Physical Layer Initialization Status Register Device 2 Function 1 Offset 80h Access as a Dword Reset err Bit Type Value Description 31 30 RV Reserved 29 RO GLOBAL_ERROR Set upon any error detected on the link during Loopback Pattern 28 RO E TEST_ BUSY Saa E Test busy bit indicating that a test is in progress STATE_ HOLD 27 RW1C 0 State machine hold bit for singl
52. cece eee eect eeee ee 110 2 9 2 EPPVCCTL EP Port VC Control RegisSter eeeceeeeee eee eee ee nena teen nena 110 2 9 3 EPVCORCTL EP VC 0 Resource Control Register rreren 111 2 9 4 EPVCORCAP EP VC 0 Resource Capability Register ceceeeeeeee eee es 112 2 9 5 EPVC1RCTL EP VC 1 Resource Control Register cceeeeeeeeeee eee ees 113 2 9 6 EPVC1IRSTS EP VC 1 Resource Status Register ceecee 114 2 10 PCI Device 1 Registers j iciater tereiehmentaxiancaxdiee EE E EE Ti 115 2 10 1 VID1 Vendor Identification Register sssssssssrserrsrrserrnnrrnrnnnernernner 117 2 10 2 DID1 Device Identification Register cceceeeeee eee e eee ee teen eee a eae 117 2 10 3 PCICMD1 PCI Command ReGiSteP cceceeeee eee eee ete e ee eae eee eee eee ne tae 117 2 10 4 PCISTS1 PCI Status ReGiSter ccc eee eee ee teen ee eee en teeta tnes 119 2 10 5 RID1 Revision Identification ReQiSter cece cence eee e eee neta eee ee eae 120 2 10 6 CC1 Class Code ReGiSter cece eee eee ee ee eee nena ea ees 120 2 10 7 CL1 Cache Line Size Register c cece eee ee eect ee eee e eee teeta nena eaeas 121 2 10 8 HDR1 Header Type ReGISter ccc nee teen e eae ee nea 121 2 10 9 PBUSN1 Primary Bus Number Register ccceeeee ee eeeeeeeee ee ee eee ne eas 121 2 10 10 SBUSN1 Secondary Bus Number Register cceceeeeeee ee eee eeeeeaeaees 122 2
53. configuration transactions for power management control This device also cannot generate interrupts or respond to MMR cycles in the D3 state The device must return to the DO state in order to be fully functional When the Power State is other than DO the bridge will Master Abort that is not claim any downstream cycles with exception of type 0 config cycles Consequently these unclaimed cycles will go down DMI and come back up as Unsupported Requests which the MCH logs as Master Aborts in Device 0 PCISTS 13 There is no additional hardware functionality required to support these Power States Datasheet Volume 2 307 intel 2 19 27 2 19 28 308 Processor Configuration Registers SS _CAPID Subsystem ID and Vendor ID Capabilities Register This capability is used to uniquely identify the subsystem where the PCI device resides Because this device is an integrated part of the system and not an add in device it is anticipated that this capability will never be used However it is necessary because Microsoft will test for its presence B D F Type 0 6 0 PCI Address Offset 88 8Bh Reset Value 0000800Dh Access RO Reset Poe Bit Attr Value Description 31 16 RO 0000h Reserved Pointer to Next Capability PNC 15 8 RO 80h This field contains a pointer to the next item in the capabilities list which is the PCI Power Management capability Capability ID CID 7 0 RO ODh Value of ODh identif
54. disabled TOLUD can be 1 MB aligned TSEG_BASE The TSEG_BASE register reflects the total amount of low addressable DRAM below TOLUD BIOS will calculate and program this register so the processor has knowledge of where TOLUD Gfx stolen Gfx GTT stolen TSEG is located I O blocks use this minus DPR for upstream DRAM decode Datasheet Volume 2 27 2 28 intel Processor Configuration Registers 2 3 1 Programming Model The memory boundaries of interest are Bottom of Logical Address Remap Window defined by the REMAPBASE register which is calculated and loaded by BIOS Top of Logical Address Remap Window defined by the REMAPLIMIT register which is calculated and loaded by BIOS Bottom of Physical Remap Memory defined by the existing TOLUD register Top of Physical Remap Memory which is implicitly defined by either 4 GB or TOM minus Manageability Engine stolen size Mapping steps 1 2 o Oe J S w 9 Determine TOM Determine TOM minus ME stolen size Determine MMIO allocation Determine TOLUD Determine GFX stolen base Determine GFX GTT stolen base Determine TSEG base Determine remap base limit Determine TOUUD The following diagrams show the three possible general cases of remapping Case 1 Less than 4 GB of Physical Memory no remap Case 2 Greater than 4 GB of Physical Memory Case 3 4 GB or Less of Physical Memory Datasheet Volume 2 Processor Configuration Registers
55. in DRAM clocks between the READ and PRE commands to the same rank bank Precharge To Precharge Delay COsd_cr_pchg_pchg 1 0 RW 00b This configuration register indicates the minimum allowed spacing in DRAM clocks between two PRE commands to the same rank Datasheet Volume 2 75 intel 2 8 11 Processor Configuration Registers COCYCTRKACT Channel 0 CYCTRK ACT Register B D F Type Reset Value Access Address Offset 0 0 0 MCHBAR 252 255h 0000_0000h RW RO Bit Attr Reset Value Description 31 30 RO 00b Reserved 29 RW Ob FAW Windowcnt Bug Fix Disable FAWWBFD This bit disables the CYCTRK FAW windowcnt bug fix 1 Disable CYCTRK FAW windowcnt bug fix 0 Enable CYCTRK FAW windowcnt bug fix COsd_cr_cyctrk_faw_windowcnt_fix_disable 28 RW Ob FAW Phase Bug Fix Disable FAWPBFD This bit disables the CYCTRK FAW phase indicator bug fix 1 Disable CYCTRK FAW phase indicator bug fix 0 Enable CYCTRK FAW phase indicator bug fix COsd_cr_cyctrk_faw_phase_fix_disable 27 22 RW 00h Activate Window Count COsd_cr_act_windowcnt This field indicates the window duration in DRAM clocks during which the controller counts the number of activate commands which are launched to a particular rank If the number of activate commands launched within this window is greater than 4 then a check is implemented to block launch of further activate
56. mechanism Allocate either 256 128 or 64 busses to PCI Express by writing 000 111 or 110 respectively to bits 3 1 Pick a naturally aligned base address for mapping the configuration space onto memory space using 1 MB per bus number and write that base address into Bits 39 20 Calculate the host address of the register you wish to set using PCI Express base bus number 1 MB device number 32 KB function number 4 KB 1 B offset within the function host address Use a memory write or memory read cycle to the calculated host address to write or read that register Routing Configuration Accesses The processor supports two PCI related interfaces DMI and PCI Express The processor is responsible for routing PCI and PCI Express configuration cycles to the appropriate device that is an integrated part of the processor or to one of these two interfaces Configuration cycles to the PCH internal devices and Primary PCI including downstream devices are routed to the PCH using DMI Configuration cycles to both the PCI Express Graphics PCI compatibility configuration space and the PCI Express Graphics extended configuration space are routed to the PCI Express Graphics port device or associated link Datasheet Volume 2 Processor Configuration Registers Figure 2 10 Processor Configuration Cycle Flow Chart 2 4 4 Processor Generates Type 1 Access to PCI Express Device 0
57. that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 7 is set in this field TC7 is mapped to this VC resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link RO 1b Traffic Class 0 Virtual Channel 0 Map TCOVCOM Traffic Class 0 is always routed to VCO Datasheet Volume 2 Processor Configuration Registers intel 2 12 7 DMI VCORSTS DMI VCO Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 0 0 DMI BAR Address Offset 1A 1Bh Reset Value 0002h Access RO Reset ee Bit Attr Value Description Reserved Reserved and Zero for future R WC S implementations Software 15 2 RO 0000h must use 0 for writes to these bits Virtual Channel 0 Negotiation Pending VCONP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control initialization It is 1 RO 1b set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link succ
58. 0 0 0 VCOPREMAP 100 107h 0000000000000000h W RO Bit Attr Reset Value Description 63 12 Ww 00000000 00000h Address Addr Software provides the DMA address that needs to be page selectively invalidated To request a page selective invalidation request to hardware software must first write the appropriate fields in this register and then issue appropriate page selective invalidate command through the l OTLB_REG Hardware ignores bits 63 N where N is the maximum guest address width MGAW supported Value returned on read of this field is undefined 00h Reserved Oh Invalidation Hint 1H The field provides hint to hardware to preserve or flush the non leaf page directory entries that may be cached in hardware 0 Software may have modified both leaf and non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware must flush both the cached leaf and non leaf page table Value returned on a read of this field is undefined Entries corresponding to mappings specified by ADDR and AM fields 1 Software has not modified any non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware may preserve the cached non leaf page table entries corresponding to mappings specified by ADDR and AM fields 5 0 WwW 00h Address Mask
59. 0 GFXVTBAR Address Offset 100 107h Reset Value 0000000000000000h Access RO Reset ar Bit Attr Value Description 63 36 RO 0000000h Reserved Address ADDR Software provides the DMA address that needs to be page selectively invalidated To make a page selective invalidation request to hardware software must first write the appropriate fields in this register and then issue 35 12 RO 000000h appropriate page selective invalidate command through the OTLB_REG Hardware ignores bits 63 N where N is the maximum guest address width MGAW supported Value returned on read of this field is undefined 11 7 RO 00h Reserved Invalidation Hint IH The field provides hints to hardware about preserving or flushing the non leaf page directory entries that may be cached in hardware 0 Software may have modified both leaf and non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware must flush both the 6 RO 0b cached leaf and non leaf page table entries corresponding to the mappings specified by ADDR and AM fields 1 Software has not modified any non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware may preserve the cached non leaf page table entries corresponding to the mappings specified by the ADDR and AM fields A value returned on a read of thi
60. 0 to indicate that the D2 power management state is NOT supported 25 RO Ob D1 Power State Support D1PSS Hardwired to 0 to indicate that the D1 power management state is NOT supported 24 22 RO 000b Auxiliary Current AUXC Hardwired to 0 to indicate that there are no 3 3Vaux auxiliary current requirements 21 RO Ob Device Specific Initialization DSI Hardwired to 0 to indicate that special initialization of this device is NOT required before generic class device driver is to use it 20 RO Ob Auxiliary Power Source APS Hardwired to 0 19 RO Ob PME Clock PMECLK Hardwired to 0 to indicate this device does NOT support PMEB generation 18 16 RO 011b PCI PM CAP Version PCI PMCV Version A value of 011b indicates that this function complies with revision 1 2 of the PCI Power Management Interface Specification RO 90h Pointer to Next Capability PNC This contains a pointer to the next item in the capabilities list If MSICH CAPL 0 7Fh is 0 the next item in the capabilities list is the Message Signaled Interrupts MSI capability at 90h If MSICH CAPL O 7Fh is 1 then the next item in the capabilities list is the PCI Express capability at AOh 7 0 RO Olh Capability ID CID Value of 01h identifies this linked list item capability structure as being for PCI Power Management registers Datasheet Volu
61. 00000h Reserved 103 96 RO V S 00h Fault Reason FR This field contains the reason for the fault The VT specification 1 2 Appendix enumerates the various translation fault reason encodings This field is relevant only when the F field is set 95 80 RO 0000h Reserved 79 64 RO V S 0000h Source Identifier SID This field contains the Requester id of the faulted DMA request This field is relevant only when the F field is set 63 12 RO V S 00000000 00000h Page Address PADDR This field contains the address page granular in the faulted DMA request Hardware may treat bits 63 N as reserved 0 where N is the maximum guest address width MGAW supported This field is relevant only when the F field is set RO 000h Reserved 214 Datasheet Volume 2 Processor Configuration Registers intel 2 15 31 VTCMPLRESR VT Completion Resource Dedication This register provides a programmable interface to dedicate the DMI Completion Tracking Queue resources to DMI VCO Read DMI VCO Write DMI VC1 and DMI VCp VT fetch and PEG Completion Tracking Queue resources to PEG VCO read and PEG VCO write VT fetch B D F Type Address Offset Reset Value Access 0 0 0 VCOPREMAP F00 FO3h 00060000h RW L RO Bit Attr Reset Value Description 31 20 RW L 000h Reserved 19 16 RO 6h DMI VT Completion Tracking Queue
62. 0000_0000h Access RW RO z Reset PRP Bit Attr Value Description Protected Low Memory Limit PLML 31 21 RW 000h This register specifies the last host physical address of the DMA protected low memory region in system memory 20 0 RO 000000h Reserved Datasheet Volume 2 275 m t 1 Processor Configuration Registers 2 18 17 276 PHMBASE_REG Protected High Memory Base Register This register is used to set up the base address of DMA protected high memory region This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled When the LT CMD LOCK PMRC command is invoked this register is locked treated as RO When the LT CMD UNLOCK PMRC command is invoked this register is unlocked treated as RW This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as 0 in the Capability register The alignment of the protected high memory region base depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of this register are decoded by hardware as all Os Software may setup the protected high memory region either above or below 4 GB B D F Type 0 2 0 GFXVT
63. 0000h Access RO Reset Pare Bit Attr Value Description 15 2 RO 0000h Reserved and zero VC1 Negotiation Pending VC1NP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling 1 RO Ob For this non default Virtual Channel software may use this bit when enabling or disabling the VC Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Ob Reserved for Port Arbitration Table Status PATS Datasheet Volume 2 Processor Configuration Registers 2 10 Table 2 7 PCI Device 1 Registers PCI Express Device 1 Register Address Map Address Register Reset Datasheet Volume 2 Offset Symbol Register Name Value Access 0 1h VID1 Vendor Identification 8086h RO 2 3h DID1 Device Identification 0041h RO 4 5h PCICMD1 PCI Command 0000h RO RW 6 7h PCISTS1 PCI Status 0010h RO RW1C 8h RID1 Revision dentification 12h RO 9 Bh CCl Class Code 060400h RO Ch CL1 Cache Line Size 00h RW Eh HDR1 Header Type Olh RO 18h PBUSN1 Primary Bus Number 00h RO 19h SBUSN1 Secondary Bus Number 00h RW 1Ah SUBUSN1 Subordinate Bus Number 00h RW 1Ch OBASE1 I O Base Address FOh RW RO 1Dh IOLIMIT1 I O Limit Address 00h RW RO 1E 1Fh S
64. 10 11 SUBUSN1 Subordinate Bus Number Register c cceceeeeeeeeeeeeeea teens 122 2 10 12 IOBASE1 I O Base Address RegiSter cc cece eee ee eee e nets eee ee ee nena enens 123 2 10 13 IOLIMIT1 I O Limit Address Register ccceceeeeeee eee eee ee ee eee eeeeeaene es 123 2 10 14 SSTS1 Secondary Status Register c cece eee eee eae ee eens 124 2 10 15 MBASE1 Memory Base Address Register cccceeeeeeeee tees eee eeeeeaeaeas 125 2 10 16 MLIMIT1 Memory Limit Address Register ccceceeeeee ee ee eee eeeeea ea ene 126 2 10 17 PMBASE1 Prefetchable Memory Base Address Register 0 ee es 127 2 10 18 PMLIMIT1 Prefetchable Memory Limit Address Register 128 2 10 19 PMBASEU1 Prefetchable Memory Base Address Upper Register 128 2 10 20 PMLIMITU1 Prefetchable Memory Limit Address Upper Register 129 2 10 21 CAPPTR1 Capabilities Pointer Register ccceceeeee ee ee ee eee eee e ee ee eee 129 2 10 22 INTRLINE1 Interrupt Line Register cccceceeeeee cette eee ee teeta ee ea ens 130 2 10 23 INTRPIN1 Interrupt Pin Register ccc cece rece eee eee etna eee ea ees 130 2 10 24 BCTRL1 Bridge Control Register ccc cece ce cece eee eee te ee eee nena ea en ees 131 2 10 25 MSAC Multi Size Aperture Control Register cccecceeee eect ee eee ea en eee 132 2 10 26 PM_CAPID1 Power
65. 18 4 RO 0000h command that will be fetched next by hardware Hardware resets this field to 0 whenever the queued invalidation is disabled QIES field Clear in the Global Status register 3 0 RO Oh Reserved 2 18 20 1QT_REG Invalidation Queue Tail Register This register indicates the invalidation tail head The register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 2 0 GFXVTBAR Address Offset 88 8Fh Reset Value 0000000000000000h Access RO A Reset oe Bit Attr Value Description 00000000 Reserved 63 19 RO 0000h Queue Tail QT 18 4 RO 0000h Specifies the offset 128 bit aligned to the invalidation queue for the command that will be written next by software 3 0 RO Oh Reserved 278 Datasheet Volume 2 Processor Configuration Registers intel 2 18 21 1I1QA_REG Invalidation Queue Address Register This register is used to configure the base address and size of the invalidation queue The register is treated as reserved by implementations reporting Queued I nvalidation QI as not supported in the Extended Capability register When supported writing to this register causes the Invalidation Queue Head and Invalidation Queue Tail registers to be reset to Oh B D F Type 0 2 0 GFXVTBAR Address Offset 90 97h Reset Value 0000000000000000h Access
66. 18h 98h 1Ch 9Ch 20h AOh 24h A4h 28h A8h SID SVID 2Ch ACh 30h BOh 34h B4h 38h B8h 3Ch BCh 40h CURRENT_UCLK_RATIO COh 44h C4h 48h C8h 4Ch CCh 50h DOh 54h D4h 58h D8h 5Ch DCh MAX_RTIDS 60h EOh 64h E4h 68h E8h 6Ch ECh 70h FOh 74h F4h 78h F8h 7Ch FCh 338 Datasheet Volume 2 Intel QuickPath Architecture System Address Decode Register Description Table 3 4 Device 0 Function 1 System Address Decoder Registers DID VID 00h SAD_DRAM_RULE_0O 80h PCISTS PCICMD 04h SAD_DRAM_RULE_1 84h CCR RID 08h SAD_DRAM_RULE_2 88h HDR OCh SAD_DRAM_RULE_3 8Ch 10h SAD_DRAM_RULE_4 90h 14h SAD_DRAM_RULE_5 94h 18h SAD_DRAM_RULE_6 98h 1Ch SAD_DRAM_RULE_7 9Ch 20h AOh 24h A4h 28h A8h SID SVID 2Ch ACh 30h BOh 34h B4h 38h B8h 3Ch BCh SAD_PAM0123 40h COh SAD_PAM456 44h C4h 48h C8h SAD_SMRAM 4Ch CCh 50h DOh SAD_PCIEXBAR 54h D4h 58h D8h 5Ch DCh 60h EOh 64h E4h 68h E8h 6Ch ECh 70h FOh 74h F4h 78h F8h 7Ch FCh Datasheet Volume 2 339 Intel QuickPath Architecture System Address Decode Register Description intel Table 3 5 Device 2 Function 0 Intel QPI Link 0 Registers DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR OCh 8Ch
67. 2 0 GFXVTBAR Address Offset 44 47h Reset Value 0000_0000h Access RO Bit Attr ORe Description Message Upper Address MUA Hardware implementations supporting Extended Interrupt Mode are required to implement this register 31 0 RO 00995900 Software requirements for programming this register are described in the VTd specification Hardware implementations not supporting Extended Interrupt Mode may treat this field as reserved Datasheet Volume 2 271 intel 2 18 13 272 Processor Configuration Registers AFLOG_REG Advanced Fault Log Register This register specifies the base address of memory resident fault log region This register is treated as read only 0 for implementations not supporting advanced translation fault logging AFL field reported as 0 in the Capability register B D F Type 0 2 0 GFXVTBAR Address Offset 58 5Fh Reset Value 0000000000000000h Access RO Reset ET Bit Attr Value Description Fault Log Address FLA This field specifies the base of 4KB aligned fault log region in system memory Hardware ignores and not implement bits 63 HAW where HAW is 00000000 the host address width 63 12 RO 00000h a F Software specifies the base address and size of the fault log region through this register and programs it in hardware through the SFL field in the Global Command register When implemented reads of this field return the value t
68. 2 19 37 DSTS Device Status ReQiSter cece eee teeter eens 314 2 19 38 LCAP Link Capabilities Register cece cece e eee eee eee eee rerne 315 2 19 39 LCTL Link Control Register 0 ccc ce eeee cent eee ee eee eee teeta nena tae 317 2 19 40 LSTS Link Status ReGiSter cece teeta eee ee nena 319 2 19 41 SLOTCAP Slot Capabilities Register cc cece ee eee ee ners eee e tena eae ee nae 320 2 19 42 SLOTCTL Slot Control Register ccc eee eee ee eee eee nena 322 2 19 43 SLOTSTS Slot Status Register cece eee ee eee ee eee eee e eee eee ene ea eae 324 2 19 44 RCTL Root Control Register c ccc eect ener ee eaten e eaten es 326 2 19 45 RSTS ROOt StatuS sicccciiioicicaanestacdeseeedesddeneneeetalae teiemee TRETA 327 2 19 46 PEGLC PCI Express G Legacy Control Register ccceceeeee sete teeta eee 327 2 20 Device 6 Extended Configuration Registers cece eee eee eee ee eaten eee eee ee neta 328 2 20 1 PVCCAP1 Port VC Capability Register 1 0 0 0 cece eee eect eee ea eaee 328 2 20 2 PVCCAP2 Port VC Capability Register 2 ccececcee cece eee eee teen teeta eaee 329 2 20 3 PVCCTL Port VC Control Register ccee eee e eect ene e ee eaten eee ea eens 329 2 20 4 VCORCAP VCO Resource Capability Register cecce 330 Datasheet Volume 2 9 10 ntel 2 20 5 VCORCTL VCO Resource Control RegiSter ssssssssrrsrersrrrrrir
69. 2 Address Register This register provides the second part of a Link Entry which declares an internal link to another Root Complex Element B D F Type 0 0 0 DMIBAR Address Offset 68 6Fh Reset Value 0000_0000_0000_0000h Access RO RWO gt Reset PEPP Bit Attr Value Description 63 36 RO 0000000h Reserved Reserved for Link Address high order bits Link Address LA 35 12 RW O 000000h This field provides the memory mapped base address of the RCRB that is the target element Egress Port for this link entry 11 0 RO 000h Reserved Datasheet Volume 2 171 intel 2 12 18 172 Processor Configuration Registers DMILCAP DMI Link Capabilities Register This field indicates DMI specific capabilities B D F Type Reset Value Access Address Offset 0 0 0 DMIBAR 84 87h 00012C41h RO RW O Bit Attr Reset Value Description 31 18 RO 0000h Reserved 17 15 RW O 010b L1 Exit Latency L1SELAT This field indicates the length of time this Port requires to complete the transition from L1 to LO The value 010b indicates the range of 2 us to less than 4 us 000 Less than 1ps 001 1 us to less than 2 us 010 2 us to less than 4 us 011 4 us to less than 8 us 100 8 us to less than 16 us 101 16 us to less than 32 us 110 32 us 64 us 111 More than 64 us Both bytes of this register that contain a portion of this field m
70. 7 0 00 means cfg0 DRA 7 0 01 means cfgl DRA 7 0 09 means cfg9 and so on Table 2 6 DRAM Rank Attribute Register Programming DRA Config Tech Depth Width Row Col Bank Rank rage Capacity Size 00h through 83h Reserved 84h 512Mb 64M 8 13 10 3 512 MB 8K 85h 512Mb 32M 16 12 10 3 256 MB 8K 86h 1Gb 128M 8 14 10 3 1 GB 8K 87h 1Gb 64M 16 13 10 3 512MB 8K 88h 2Gb 256M 8 15 10 3 2 GB 8K 89h 2Gb 128M 16 14 10 3 1 GB 8K 8Ah Reserved 8Bh 4Gb 256M 16 15 10 3 2 GB 8K 8Ch through FFh Reserved B D F Type 0 0 0 MCHBAR Address Offset 208 209h Reset Value 0000h Access RW L Reset fae Bit Attr Value Description Channel 0 DRAM Rank 1 Attributes CODRA1 This register defines DRAM page size number of banks for rank 1 for given 15 8 RW L 00h channel See Table 2 6 for programming This register is locked by Memory pre allocated for MR lock Channel 0 DRAM Rank O Attributes CODRAO This register defines DRAM page size number of banks for rank 0 for given 7 0 RW L 00h channel See Table 2 6 for programming This register is locked by Memory pre allocated for MRE lock Datasheet Volume 2 73 Processor Configuration Registers intel 2 8 8 CODRA23 Channel 0 DRAM Rank 2 3 Attribute Register See CODRAO1 register description for programming details B D F Type 0 0 0 MCHBAR Address Offset 20A 20Bh Reset Value 0000h Access RW L i Reset E Bit Attr V
71. AM The value in this field specifies the number of low order bits of the ADDR field that must be masked for the invalidation operation The Mask field enables software to request invalidation of contiguous mappings for size aligned regions For example Mask Value ADDR bits masked Pages invalidated Mask Value Addr bits masked Pg inval Nil 1 12 2 13 12 4 14 12 8 15 12 16 16 12 32 17 12 64 18 12 128 8 19 12 256 Hardware implementations report the maximum supported mask value through the Capability register Value returned on read of this field is undefined NOUBWNF OO Datasheet Volume 2 211 intel Processor Configuration Registers 2 15 29 OTLB_REG IOTLB Invalidate Register Register to control page table entry caching The act of writing the upper byte of the OTLB_REG with IVT field set causes the hardware to perform the IOTLB invalidation There is an OTLB_REG for each IOTLB I nvalidation unit supported by hardware Access B D F Type Address Offset Reset Value 0 0 0 VCOPREMAP 108 10Fh 0000000000000000h RW RO Bit Attr Reset Value Description 63 RW Ob Invalidate OTLB IVT Software requests IOTLB invalidation by setting this field Software must also set the requested invalidation granularity by programming the IIRG field Hardware clears the IVT field to indicate the invalidation request is complete Hardware also indicates the granularity a
72. Adjusted guest address widths supported by hardware are reported through the SAGAW field 15 13 RO 000b Reserved Supported Adjusted Guest Address Widths SAGAW This 5 bit field indicates the supported adjusted guest address widths which in turn represents the levels of page table walks supported by the hardware implementation A value of 1 in any of these bits indicates the corresponding adjusted guest address width is supported The adjusted guest address widths corresponding to various bit positions within this field are 12 8 RO 00010b_ 0 30 bit AGAW 2 level page table 1 39 bit AGAW 3 level page table 2 48 bit AGAW 4 level page table 3 57 bit AGAW 5 level page table 4 64 bit AGAW 6 level page table Software must ensure that the adjusted guest address width used to setup the page tables is one of the supported guest address widths reported in this field Caching Mode CM 0 Hardware does not cache not present and erroneous entries in the context cache and IOTLB Invalidations are not required for modifications to individual not present or invalid entries However any modifications that result in decreasing the effective permissions or partial permission increases require invalidations for them to be effective Hardware may cache not present and erroneous mappings in the context cache or l OTLB Any software updates to the DMA remapping structures including updates to not present or erroneous
73. Advanced Fault Logging Status AFLS This field is valid only for implementations supporting advanced fault logging 28 RO Ob This field indicates advanced fault logging status 0 Advanced Fault Logging is not enabled 1 Advanced Fault Logging is enabled Write Buffer Flush Status WBFS This bit is valid only for implementations requiring write buffer flushing 27 RO Ob This field indicates the status of the write buffer flush operation This field is set by hardware when software sets the WBF field in the Global Command register This field is cleared by hardware when hardware completes the write buffer flushing operation Queued I nvalidation Enable Status QIES 26 RO Ob This field indicates queued invalidation enable status 0 queued invalidation is not enabled 1 queued invalidation is enabled Interrupt Remapping Enable Status IRES 25 RO Ob This field indicates the status of I nterrupt remapping hardware 0 Interrupt remapping hardware is not enabled 1 Interrupt remapping hardware is enabled Interrupt Remapping Table Pointer Status I RTPS This field indicates the status of the interrupt remapping table pointer in hardware 24 RO Ob This field is cleared by hardware when software sets the SIRTP field in the Global Command register This field is Set by hardware when hardware completes the set interrupt remap table pointer operation using the value provided in the Interrupt Remapping Table Address register Compatibility
74. CODTC Channel O DRAM Throttling Control Register Programmable Event weights are input into the averaging filter Each Event weight is an normalized 8 bit value that the BIOS must program The BIOS must account for burst length and 1N 2N rule considerations It is also possible for BIOS to take into account loading variations of memory caused as a function of memory types and population of ranks B D F Type 0 0 0 MCHBAR Address Offset 2B4 2B7h Reset Value 0000_0000h Access RO RW L K RW L P Reset Pane Bit Attr Value Description 31 24 RO 00h Reserved DRAM Throttle Lock DTLOCK 23 RW L K Ob This bit secures the DRAM throttling control registers DT EW and DTC Once a 1 is written to this bit all of these configuration register bits become read only 22 22 RO Oh Reserved DRAM Bandwidth Based Throttling Enable DBBTE 0 Bandwidth Threshold WAB is not used for throttling 21 RW L Ob 1 Bandwidth Threshold WAB is used for throttling If both Bandwidth based and thermal sensor based throttling modes are on and the thermal sensor trips weighted average WAT is used for throttling DRAM Thermal Sensor Trip Enable DTSTE 20 RW L Ob 0 GMCH throttling is not initiated when the GMCH thermal sensor trips 1 GMCH throttling is initiated when the GMCH thermal sensor trips and the Filter output is equal to or exceeds thermal threshold WAT 19 RO Ob Reserved 84 Datasheet Volume 2
75. CYCTRK READ Register This register is for Channel 1 CYCTRK READ control B D F Type 0 0 0 MCHBAR Address Offset 658 65Ah Reset Value 000000h Access RW RO Reset Be Bit Attr Value Description 23 21 RO Oh Reserved Min ACT To READ Delayed C1sd_cr_act_rd 20 17 RW Oh This field indicates the minimum allowed spacing in DRAM clocks between the ACT and READ commands to the same rank bank This field corresponds to tRCD_rd in the DDR specification Same Rank Write To READ Delayed C1sd_cr_wrsr_rd This field indicates the minimum allowed spacing in DRAM clocks between 16 12 RW 00000b the WRITE and READ commands to the same rank This field corresponds to tWTR in the DDR specification Different Ranks Write To READ Delayed C1sd_cr_wrdr_rd This field indicates the minimum allowed spacing in DRAM clocks between 11 8 RW 0000b the WRITE and READ commands to different ranks This field corresponds to tWR_RD in the DDR specification Same Rank Read To Read Delayed C1sd_cr_rdsr_rd 7 4 RW 0000b This field indicates the minimum allowed spacing in DRAM clocks between two READ commands to the same rank Different Ranks Read To Read Delayed C1sd_cr_rddr_rd 3 0 RW 0000b This field indicates the minimum allowed spacing in DRAM clocks between two READ commands to different ranks This field corresponds to tRD_RD 90 Datasheet Volume 2 Processor Configuration Registers 2 8 33
76. Control Register 14 RW1C Ob Received System Error RSE This bit is set when the Secondary Side for a Type 1 configuration space header device receives an ERR_FATAL or ERR_NONFATAL 13 RW1C Ob Received Master Abort RMA This bit is set when the Secondary Side for Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Unsupported Request Completion Status 12 RW1C Ob Received Target Abort RTA This bit is set when the Secondary Side for Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Completer Abort Completion Status 11 RO Ob Signaled Target Abort STA Not Applicable or Implemented Hardwired to 0 The processor does not generate Target Aborts the processor will never complete a request using the Completer Abort Completion status 10 9 RO 00b DEVSELB Timing DEVT Not Applicable or Implemented Hardwired to 0 8 RW1C Ob Master Data Parity Error SMDPE When set indicates that the MCH received across the link upstream a Read Data Completion Poisoned TLP EP 1 This bit can only be set when the Parity Error Enable bit in the Bridge Control register is set Ob Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 Ob Reserved Ob 66 60 MHz capability CAP66 Not Applicable or Implem
77. D F Type Address Offset Reset Value Access 0 6 0 PCI 1E 1Fh 0000h RW1C RO Bit Attr Reset Value Description 15 RW1C Ob Detected Parity Error DPE This bit is set by the Secondary Side for a Type 1 Configuration Space header device whenever it receives a Poisoned TLP regardless of the state of the Parity Error Response Enable bit in the Bridge Control Register 14 RW1C Ob Received System Error RSE This bit is set when the Secondary Side for a Type 1 configuration space header device receives an ERR_FATAL or ERR_NONFATAL 13 RW1C Ob Received Master Abort RMA This bit is set when the Secondary Side for Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Unsupported Request Completion Status 12 RW1C Ob Received Target Abort RTA This bit is set when the Secondary Side for Type 1 Configuration Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Completer Abort Completion Status 11 RO Ob Signaled Target Abort STA Not Applicable or Implemented Hardwired to 0 The GMCH does not generate Target Aborts the GMCH will never complete a request using the Completer Abort Completion status 10 9 RO 00b DEVSELB Timing DEVT Not Applicable or Implemented Hardwired to 0 8 RW1C Ob Master Data Parity Error SMDPE
78. DFh SKPD Scratchpad Data 0000_0000h RW E0 EBh CAPIDO Capability Identifier ier gent RO pa esea ie a Sear a T Datasheet Volume 2 45 Processor Configuration Registers intel 2 7 1 VI D Vendor Identification Register This register combined with the Device Identification register uniquely identifies any PCI device B D F Type 0 0 0 PCI Address Offset 0 1h Reset Value 8086h Access RO Reset soem Bit Attr Value Description Vendor Identification Number VID B RO 8086h PCI standard identification for Intel 2 7 2 DI D Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device B D F Type 0 0 0 PCI Address Offset 2 3h Reset Value 0040h Access RO n Reset jai Bit Attr Value Description Device Identification Number DID 15 0 RO 00401 Identifier assigned to the processor core primary PCI device 46 Datasheet Volume 2 Processor Configuration Registers intel 2 7 3 PCI CMD PCI Command Register Since processor Device 0 does not physically reside on PCI_A many of the bits are not implemented B D F Type 0 0 0 PCI Address Offset 4 5h Reset Value 0006h Access RO RW Reset jarai Bit Attr Value Description 15 10 RO 00h Reserved Fast Back to Back Enable FB2B This bit controls whether or not the
79. Indicator is electrically controlled by the chassis for this slot RO Ob Reserved for Attention I ndicator Present AI P When set to 1b this bit indicates that an Attention Indicator is electrically controlled by the chassis RO Ob Reserved for MRL Sensor Present MSP When set to 1b this bit indicates that an MRL Sensor is implemented on the chassis for this slot RO Ob Reserved for Power Controller Present PCP When set to 1b this bit indicates that a software programmable Power Controller is implemented for this slot adapter depending on form factor RO Ob Reserved for Attention Button Present ABP When set to 1b this bit indicates that an Attention Button for this slot is electrically controlled by the chassis Datasheet Volume 2 Processor Configuration Registers 2 10 43 SLOTCTL Slot Control Register Note Hot Plug is not supported on the platform B D F Type 0 1 0 PCI Address Offset B8 B9h Reset Value 0000h Access RO RW 5 Reset eae Bit Attr Value Description 15 13 RO 000b Reserved Reserved for Data Link Layer State Changed Enable DLLSCE If the Data Link Layer Link Active capability is implemented when set to 1b this field enables software notification when Data Link Layer Link Active field 12 RO Ob is changed If the Data Link Layer Link Active capability is not implemented this bit is permitted to be read only
80. Key Hash Lower Half Register These registers hold the hash of the processor s public key It is 256 bits 32 Bytes B D F Type 0 0 0 TXT Specific Address Offset 400 40Fh Reset Value 73A13C69E7DCF24C384C652BA19DA250h Access RO Reset PR Bit Attr Value Description Public Key Hash Lower half TXT PUBLI C KEYHASH This is a 256 bit 32 byte field that contains the hash of the processor s 73A13C69 public key For the processor the value of the processor s public key differs E7DCF24 between Production mode and Debug mode 127 0 RO Penne Debug Mode Public Key lower half 50h 73A13C69E7DCF24C384C652BA19DA250h Production Mode Public Key lower half C8012D55129B7568DF3979FC2B8BDE54h 2 21 4 TXT PUBLIC KEY UPPER TXT Processor Public Key Hash Upper Half Register B D F Type 0 0 0 TXT Specific Address Offset 410 41Fh Reset Value D884C70067DFC104BFDF8368D7254DBBh Access RO Bit Attr tied Description Public Key Hash Upper half TXT PUBLIC KEYHASH This is a 256 bit 32 byte field that contains the hash of the processor s D884C70 public key For this processor the value of the processor s public key differs 067DFC1 between Production mode and Debug mode 127 0 RO A Debug Mode Public Key upper half DBBh D884C70067DFC104BFDF8368D7254DBBh Production Mode Public Key upper half 1337927100B39E8EC9166899A0E12BE0h 334 SS Datasheet Volume 2 Intel
81. MBASEU 31 0 RW Oh This field corresponds to A 63 32 of the lower limit of the prefetchable memory range that will be passed to PCI Express G Datasheet Volume 2 Processor Configuration Registers t 2 10 20 PMLI MI TU1 Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC that is prefetchable from the processor perspective B D F Type 0 1 0 PCI Address Offset 2C
82. Mode PCTQRSM 11 PEG1 and PEGO will each be assigned half of the resources in the Completion Tracking Queue 10 PEG1 will be assigned all of the resources in the Completion Tracking Queue 01 PEGO will be assigned all of the resources in the Completion Tracking Queue 00 See below for more description for this encoding If both Device 1 and Device 6 are enabled PEG1 and PEGO will each be assigned half of the resources in the Completion Tracking Queue If Device 6 is enabled and Device 1 is disabled PEG1 will be assigned all of the resources in the Completion Tracking Queue If Device 1 is enabled and Device 6 is disabled PEGO will be assigned all of the resources in the Completion Tracking Queue If both Device 1 and Device 6 are disabled PEG1 and PEGO will each be assigned half of the resources in the Completion Tracking Queue 31 30 RW L 00b PEG1 VT Completion Tracking Queue Resource Available PEG1VTCTRA Number of entries available in PEG1 VT Completion Tracking Queue 1 based 29 25 RO 10000b The values programmed in the fields below must not be greater than the value advertised in this field Note If device 1 is disabled the default is 10000b otherwise it is 01000b This is a status bit PEG1 VCO Write VT Completion Tracking Queue Resource Threshold PEG1VCOWRCTQRT This field provides a 1 based minimum threshold value used to throttle PEG1 VCO Write VT fetch When the number of free PEG1 VT Comple
83. Ob Received Master Abort Status RMAS Not Applicable or Implemented Hardwired to 0 The concept of a master abort does not exist on primary side of this device 12 RO Ob Received Target Abort Status RTAS Not Applicable or Implemented Hardwired to 0 The concept of a target abort does not exist on primary side of this device 11 RO Ob Signaled Target Abort Status STAS Not Applicable or Implemented Hardwired to 0 The concept of a target abort does not exist on primary side of this device 10 9 RO 00b DEVSELB Timing DEVT This device is not the subtractively decoded device on bus 0 This bit field is therefore hardwired to 00 to indicate that the device uses the fastest possible decode RO Ob Master Data Parity Error PMDPE Because the primary side of the PEG s virtual P2P bridge is integrated with the MCH functionality there is no scenario where this bit will get set Because hardware will never set this bit it is impossible for software to have an opportunity to clear this bit or otherwise test that it is implemented The PCI specification defines it as a R WC but for our implementation an RO definition behaves the same way and will meet all Microsoft testing requirements This bit can only be set when the Parity Error Enable bit in the PCI Command register is set RO Ob Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 RO Ob Res
84. PCI Express G 3 0 RO Oh Reserved Datasheet Volume 2 Processor Configuration Registers 7 t 2 19 16 Note Note MLI MI T6 Memory Limit Address Register This register controls the processor to PCI Express G non prefetchable memory access routing based on the following formula MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Memory range covered by MBASE and MLIMIT registers are used to map non prefetchable PCI Express G address ranges typically where control status memory mapped I O data structures of the graphics controller will reside and PMBASE and PMLIMIT are used to map prefetchable address ranges typically graphics local memory This segregation allows application of USWC space attribute to be performed in a true plug and play manner to the prefetchable address range for improved processor PCI Express memory access performance Configuration software is responsible for programming all address range registers prefetchable non prefetchable with the values
85. QuickPath Architecture System Address Decode Register Description 3 3 1 Table 3 1 intel Intel QuickPath Architecture System Address Decode Register Description The processor supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism in the PCI specification as defined in the PCI Local Bus Specification Revision 2 3 as well as the PCI Express enhanced configuration mechanism as specified in the PCI Express Base Specification Revision 1 1 All the registers are organized by bus device function etc as defined in the PCI Express Base Specification Revision 1 1 All processor registers appear on the PCI bus assigned for the processor socket Bus number is derived by the maximum bus range setting and processor socket number All multi byte numeric fields use little endian ordering that is lower addresses contain the least significant parts of the field As processor features vary by SKU not all of the register descriptions in this chapter apply to all processors This document highlights registers that do not apply to all processor SKUs Refer to the particular processor specification update for a list of features supported Register Terminology Registers and register bits are assigned one or more of the following attributes These attributes define the behavior of register and the bit s that are contained within All bits are set to Reset Values by a hard reset Sticky bits re
86. RO Ob Translation Enable Status TES This field indicates the status of DMA remapping hardware 0 DMA remapping hardware is not enabled 1 DMA remapping hardware is enabled 30 RO Ob Root Table Pointer Status RTPS This field indicates the status of the root table pointer in hardware This field is cleared by hardware when software sets the SRTP field in the Global Command register This field is set by hardware when hardware completes the set root table pointer operation using the value provided in the Root Entry Table Address register 29 RO Ob Fault Log Status FLS This field is valid only for implementations supporting advanced fault logging This field indicates the status of the fault log pointer in hardware This field is cleared by hardware when software sets the SFL field in the Global Command register This field is set by hardware when hardware completes the set fault log pointer operation using the value provided in the Advanced Fault Log register 28 RO Ob Advanced Fault Logging Status AFLS This field is valid only for implementations supporting advanced fault logging This field indicates advanced fault logging status 0 Advanced Fault Logging is not enabled 1 Advanced Fault Logging is enabled 27 RO Ob Write Buffer Flush Status WBFS This bit is valid only for implementations requiring write buffer flushing This field indicates the status of the write buf
87. RO Reset ae Bit Attr Value Description Invalidation Queue Address IQA This field points to the base of 4 KB aligned invalidation request queue 63 12 RO 00 00b Hardware ignores and not implement bits 63 HAW where HAW is the host address width Reads of this field return the value that was last programmed to it 11 3 RO 000h Reserved Queue Size QS 2 0 RO 000b This field specifies the size of the invalidation request queue A value of X in i this field indicates an invalidation request queue of X 1 4 KB pages The number of entries in the invalidation queue is 2 X 8 2 18 22 ICS_REG Invalidation Completion Status Register This register reports completion status of invalidation wait descriptor with Interrupt Flag IF Set The register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 2 0 GFXVTBAR Address Offset 9C 9Fh Reset Value 00000000h Access RO Reset eae Bit Attr Value Description 31 1 RO 00 00b Reserved Invalidation Wait Descriptor Complete IWC This bit indicates completion of Invalidation Wait Descriptor with Interrupt 0 RO Ob Flag IF field Set Hardware implementations not supporting queued invalidations implement this field as reserved Datasheet Volume 2 279 intel 2 18 23 280 Processor Configuration Registers IECTL_REG I nvalidation Comp
88. RO i Reset er Bit Attr Value Description Pointer to Next Capability PNC 15 8 RO AOh This field contains a pointer to the next item in the capabilities list which is the PCI Express capability Capability ID CID 7 0 RO 05h Value of 05h identifies this linked list item capability structure as being for MSI registers Datasheet Volume 2 309 intel 2 19 30 310 Processor Configuration Registers MC Message Control Register System software can modify bits in this register but the device is prohibited from doing SO If the device writes the same message multiple times only one of those messages is ensured to be serviced If all of them must be serviced the device must not generate the same message again until the driver services the earlier one B D F Type 0 6 0 PCI Address Offset 92 93h Reset Value 0000h Access RO RW Bit Attr ba Description 15 8 RO 00h Reserved 64 bit Address Capable 64AC 7 RO Ob Hardwired to 0 to indicate that the function does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64 bit memory address Multiple Message Enable MME System software programs this field to indicate the actual number of 6 4 RW 000b messages allocated to this device This number will be equal to or less than the number actually requested The encoding is the same as for the MMC field below Multiple Message Capable MMC
89. RW S Ob 0 PMEB generation not possible from any D State 1 PMEB generation enabled from any D State The setting of this bit has no effect on hardware See PM_CAP 15 11 7 4 RO 0000b Reserved No Soft Reset NSR 1 When set to 1 this bit indicates that the device is transitioning from D3hot to DO because the power state commands do not perform a internal reset Config context is preserved Upon transition no additional operating system intervention is required to preserve configuration a context beyond writing the power state bits i 7 0 When clear the devices do not perform an internal reset upon transitioning from D3hot to DO using software control of the power state bits Regardless of this bit the devices that transition from a D3hot to DO by a system or bus segment reset will return to the device state DO uniintialized with only PME context preserved if PME is supported and enabled 2 RO Ob Reserved Power State PS This field indicates the current power state of this device and can be used to set the device into a new power state If software attempts to write an unsupported state to this field write operation must complete normally on the bus but the data is discarded and no state change occurs 00 DO 01 D1 Not supported in this device 10 D2 Not supported in this device 11 D3 1 0 RW 00b Support of D3cold does not require any special action While in the D3hot state this device can only act as the target of PCI
90. ReGISter cccececeeee eee ee eet teeta ee eanees 196 2 15 8 FSTS REG Fault Status Register cece eee etter tenet neste ta seen ne ee teenies 198 2 15 9 FECTL_REG Fault Event Control Register cccceeeeeeee sees ete ee ea eeeeeneees 199 2 15 10 FEDATA_REG Fault Event Data ReQiSter cece ceee ee ee ete ee teen ea eaee es 200 2 15 11 FEADDR_REG Fault Event Address Register 200 2 15 12 FEUADDR_REG Fault Event Upper Address Register cceceeeee eee 200 2 15 13 AFLOG_REG Advanced Fault Log Register cccceceeee cece eee ee eee en en ees 201 2 15 14 PMEM_REG Protected Memory Enable Register c ccceeeeeeeeeeea teens 202 2 15 15 PLMBASE REG Protected Low Memory Base Register eccere 203 2 15 16 PLMLIMIT_REG Protected Low Memory Limit Register eeeeee 204 2 15 17 PHMBASE_REG Protected High Memory Base Register neccen 205 2 15 18 PHMLIMIT_REG Protected High Memory Limit Register sece 206 2 15 19 IQH REG Invalidation Queue Head Register cceceeee ee eee tees ee ee en ees 206 2 15 20 IQT_REG Invalidation Queue Tail Register cceceeee cece e teeta teens 207 2 15 21 IQA REG Invalidation Queue Address Register ccceeeeeee eee eeeee ee ees 207 2 15 22 ICS REG Invalidation Completion Status Register ccceeeeeeeeeee ees 208 2 15 23 IECTL_REG Invalidation Event Control Register cccceeeeeeee eee ee ee
91. Register CAPPTR contains the offset pointing to the start address with configuration space of this device where the capability register resides This bit must be set for a PCI Express device or if the VSEC capability If no capability structures are implemented this bit is hard wired to 0 Interrupt Status If this device generates an interrupt then this read only bit reflects the state of the interrupt in the device function Only when the Interrupt 3 RO 0 Disable bit in the command register is a 0 and this Interrupt Status bit is a 1 will the device s function s INTx signal be asserted Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit If this device does not generate interrupts then this bit is not implemented RO and reads returns 0 2 0 RO 0 Reserved 348 Datasheet Volume 2 Intel QuickPath Architecture System Address Decode Register Description 7 3 5 3 5 1 3 6 3 6 1 Generic Non core Registers MAX_RTIDS Maximum number of RTIDs other homes have How many requests can this caching agent send to the other home agents This number is one more than the highest numbered RTID to use Note that these values reset to 2 and need to be increased by BIOS to whatever the home agents can support Device 0 Function 0 Offset 60h Access as a Dword Reset ar Bit Type Value Description 31 22 RV 000h Reserved LOCAL_MC elite 2 Maxi
92. Reset Values on cold reset RW S Read Write Sticky bit s These bits can be read and written by software Bits are not returned to their Reset Values by warm reset but will return to Reset Values with a cold complete reset for PCI Express related bits a cold reset is Power Good Reset as defined in the PCI Express spec RW O Read Write Once bit s Reads prior to the first write return the Reset Value The first write after warm reset stores any value written Any subsequent write to this bit field is ignored All subsequent reads return the first value written The value returns to default on warm reset If there are multiple RW O or RW O S fields within a DWORD they should be written all at once atomically to avoid capturing an incorrect value RW O S Read Write Once Sticky bit s Reads prior to the first write return the Reset Value The first write after cold reset stores any value written Any subsequent write to this bit field is ignored All subsequent reads return the first value written The value returns to default on cold reset If there are multiple RW O or RW O S fields within a DWORD they should be written all at once atomically to avoid capturing an incorrect value Write only These bits may be written by software but will always return zeros when read They are used for write side effects Any data written to these registers cannot be retrieved WIC Write 1 to Clear only These
93. Sensor Control Registers 3000h to 3FFFh Unlocked registers for future expansion B D F Type 0 0 0 PCI Address Offset 48 4Fh Reset Value 0000_0000_0000_0000h Access RW L RO i Reset ET Bit Attr Value Description 63 36 RO 0000000h Reserved MCH Memory Mapped Base Address MCHBAR This field corresponds to bits 35 4 of the base address processor memory mapped configuration space BIOS will program this register resulting in a 35 14 RW L 000000h base address for a 16 KB block of contiguous memory address space This register ensures that a naturally aligned 16 KB space is allocated within the first 64 GB of addressable memory space System Software uses this base address to program the processor memory mapped register set All the bits in this register are locked in Intel TXT mode 13 1 RO 0000h Reserved MCHBAR Enable MCHBAREN 0 Disable MCHBAR is disabled and does not claim any memory 0 RW L Ob 1 Enable MCHBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel TXT Datasheet Volume 2 Processor Configuration Registers 2 7 13 GGC Graphics Control Register All the bits in this register are Intel TXT lockable B D F Type 0 0 0 PCI Address Offset 52 53h Reset Value 0030h Access RW L RO Reset Aer Bit Attr Value Description 15 12 RO Oh Reserved GTT Graphics Memory Size GGMS This field i
94. The fault log pointer is specified through Advanced Fault Log register 29 w Ob Hardware reports the status of the fault log set operation through the FLS field in the Global Status register The fault log pointer must be set before enabling advanced fault logging through EAFL field Once advanced fault logging is enabled the fault log pointer may be updated through this field while DMA remapping is active Clearing this bit has no effect Value returned on read of this field is undefined Datasheet Volume 2 227 Processor Configuration Registers B D F Type 0 0 0 DMIVC1REMAP Address Offset 18 1Bh Reset Value 00000000h Access W RO Reset Bee Bit Attr Value Description Enable Advanced Fault Logging EAFL This field is valid only for implementations supporting advanced fault logging Software writes to this field to request hardware to enable or disable advanced fault logging 0 Disable advanced fault logging In this case translation faults are reported through the Fault Recording registers 28 WwW Ob 1 Enable use of memory resident fault log When enabled translation faults are recorded in the memory resident log The fault log pointer must be set in hardware through SFL field before enabling advanced fault logging Hardware reports the status of the advanced fault logging enable operation through the AFLS field in the Global Status register Value returned on read of this field is
95. VC Control Register B D F Type 0 1 0 MMR Address Offset 10C 10Dh Reset Value 0000h Access RO RW s Reset zagi Bit Attr Value Description 15 4 RO 000h Reserved VC Arbitration Select VCAS 3 1 RW 000b This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field Since there is no other VC supported than the default this field is reserved Reserved for Load VC Arbitration Table 0 RO Ob This bit is used for software to update the VC Arbitration Table when VC arbitration uses the VC Arbitration Table As a VC Arbitration Table is never used by this component this field will never be used Datasheet Volume 2 157 intel Processor Configuration Registers 2 11 4 VCORCAP VCO Resource Capability Register B D F Type 0 1 0 MMR Address Offset 110 113h Reset Value 0000 _0001h Access RO gt Reset ee Bit Attr Value Description 31 24 RO 00h Reserved for Port Arbitration Table Offset 23 RO Ob Reserved 22 16 RO 00h Reserved for Maximum Time Slots Reject Snoop Transactions RSNPT 0 Transactions with or without the No Snoop bit set within the TLP header 15 RO Ob are allowed on this VC 1 When Set any transaction for which the No Snoop attribute is applicable but is not Set within the TLP Header will be rejected as an Unsupported Request 14 8 RO 00h Reserved 2 11 5 VCORCTL VCO Re
96. WBFS This field is valid only for implementations requiring write buffer flushing This field indicates the status of the write buffer flush command It is Set by hardware when software sets the WBF field in the Global Command register Cleared by hardware when hardware completes the write buffer flushing operation 26 RO Ob Queued I nvalidation Enable Status QIES This field indicates queued invalidation enable status 0 Queued invalidation is not enabled 1 Queued invalidation is enabled 25 RO Ob Interrupt Remapping Enable Status I RES This field indicates the status of Interrupt remapping hardware 0 Interrupt remapping hardware is not enabled 1 Interrupt remapping hardware is enabled 24 RO Ob Interrupt Remapping Table Pointer Status I RTPS This field indicates the status of the interrupt remapping table pointer in hardware This field is cleared by hardware when software sets the SIRTP field in the Global Command register This field is set by hardware when hardware completes the set interrupt remap table pointer operation using the value provided in the Interrupt Remapping Table Address register 23 RO Ob Compatibility Format I nterrupt Status CI FS This field indicates the status of Compatibility format interrupts on Intel 64 implementations supporting interrupt remapping The value reported in this field is applicable only when interrupt remapping is enabled
97. When set indicates that the MCH received across the link upstream a Read Data Completion Poisoned TLP EP 1 This bit can only be set when the Parity Error Enable bit in the Bridge Control register is set Ob Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 Ob Reserved Ob 66 60 MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 4 0 RO 00h Reserved Datasheet Volume 2 297 intel MBASE6 Memory Base Address Register This register controls the processor to PCI Express G non prefetchable memory access routing based on the following formula 2 19 15 298 Processor Configuration Registers MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 6 0 PCI Address Offset 20 21h Reset Value FFFOh Access RW RO Reset Pre Bit Attr Value Description Memory Address Base MBASE 15 4 RW FFFh This field corresponds to A 31 20 of the lower limit of the memory range that will be passed to
98. a PCI compliant master Memory Access Enable MAE 1 RW Ob This bit controls the IGD response to memory space accesses 0 Disable 1 Enable I O Access Enable 1 OAE 0 RW Ob This bit controls the IGD response to I O space accesses 0 Disable 1 Enable Datasheet Volume 2 175 intel Processor Configuration Registers 2 13 4 PCISTS2 PCI Status Register PCISTS is a 16 bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort PCISTS also indicates the DEVSEL timing that has been set by the IGD B D F Type 0 2 0 PCI Address Offset 6 7h Reset Value 0090h Access RO j Reset ETE Bit Attr Value Description 15 RO Ob Detected Parity Error DPE Since the IGD does not detect parity this bit is always hardwired to 0 14 RO Ob Signaled System Error SSE The IGD never asserts SERR therefore this bit is hardwired to 0 13 RO Ob Received Master Abort Status RMAS The IGD never gets a Master Abort therefore this bit is hardwired to 0 12 RO Ob Received Target Abort Status RTAS The IGD never gets a Target Abort therefore this bit is hardwired to 0 11 RO Ob Signaled Target Abort Status STAS Hardwired to 0 The IGD does not use target abort semantics DEVSEL Timing DEVT 10 9 RO aap Not applicable These bits are hardwired to 00 Master Data Parity Error Detected DP
99. are locked in Intel TXT mode 11 1 RO 000h Reserved PXPEPBAR Enable PXPEPBAREN 0 Disable PXPEPBAR is disabled and does not claim any memory 0 RW L Ob 1 Enable PXPEPBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel TXT il Datasheet Volume 2 51 2 7 12 52 intel Processor Configuration Registers MCHBAR MCH Memory Mapped Register Range Base Register This is the base address for the processor memory mapped configuration space There is no physical memory within this 16 KB window that can be addressed The 16 KB reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset the processor MMIO memory mapped configuation space is disabled and must be enabled by writing a 1 to MCHBAREN Device 0 offset48h bit 0 All the bits in this register are locked in Intel TXT mode The register space contains memory control initialization timing and buffer strength registers clocking registers and power and thermal management registers The 16 KB space reserved by the MCHBAR register is not accessible during Intel TXT mode of operation or if the ME security lock is asserted MESMLCK ME_SM_lock at PCI device 0 function 0 offset F4h except for the following offset ranges 02B8h to 02BFh Channel 0 Throttle Counter Status Registers O6B8h to O6BFh Channel 1 Throttle Counter Status Registers OCDOh to OCFFh Thermal
100. bit 3 or bit 2 is 1 00 Swap Enabled for Bank Selects and Rank Selects 01 XOR Enabled for Bank Selects and Rank Selects 10 Swap Enabled for Bank Selects only 11 XOR Enabled for Bank Select only This register is locked by Memory pre allocated for MWlock Reserved Channel 1 Enhanced Mode CH1_ENHMODE This bit indicates that enhanced addressing mode of operation is enabled for channel 1 Enhanced addressing mode of operation should be enabled only when both the channels are equally populated with same size and same type of DRAM memory An added restriction is that the number of ranks channel has to be 1 2 or 4 Note If any of the channels is in enhanced mode the other channel should also be in enhanced mode 0 Standard addressing 1 Enhanced addressing This register is locked by Memory Pre allocated for Graphics lock Channel 0 Enhanced Mode CHO_ENHMODE This bit indicates that enhanced addressing mode of operation is enabled for Channel 0 Enhanced addressing mode of operation should be enabled only when both the channels are equally populated with same size and same type of DRAM memory An added restriction is that the number of ranks channel has to be 1 2 or 4 0 Standard addressing 1 Enhanced addressing Note If any of the two channels is in enhanced mode the other channel should also be in enhanced mode This register is locked by Memory pre allocated for MElock 1 0 RO 00b
101. bits may be cleared by software by writing a 1 Writing a 0 has no effect The state of the bits cannot be read directly The states of such bits are tracked outside the processor and all read transactions to the address of such bits are routed to the other agent Write transactions to these bits go to both agents MBZ Must Be Zero when writing this bit Datasheet Volume 2 Processor Configuration Registers 7 t 2 2 Note System Address Map The processor s Multi Chip Package MCP conceptually consists of the processor and the north bridge chipset GMCH combined together in a single package Hence this section will have references to the processor as well as GMCH or MCH address mapping The MCP supports 64 GB 36 bit of addressable memory space and 64 KB 3 of addressable I O space With the new QPI interface the processor performs decoding that historically occurred within the GMCH Specifically the GMCH address decoding for processor initiated PAM 15 MB 16 MB ISA hole SMM CSEG TSEG PClexBAR and DRAM accesses will occur within the processor and the GMCH has no direct knowledge In addition the ME device 3 will move to the PCH so ME associated register ranges have been removed from the graphics controller This section focuses on how the memory space is partitioned and what the separate memory regions are used for I O address space has simpler mapping and is explained near the end of this section
102. by warm reset but is reset with a cold complete reset for PCI Express related bits a cold reset is Power Good Reset as defined in the PCI Express Base Specification AF Atomic Flag bit s The first time the bit is read with an enabled byte it returns the value 0 but a side effect of the read is that the value changes to 1 Any subsequent reads with enabled bytes return a 1 until a 1 is written to the bit When the bit is read but the byte is not enabled the state of the bit does not change and the value returned is irrelevant but will match the state of the bit When a 0 is written to the bit there is no effect When a 1 is written to the bit its value becomes 0 until the next byte enabled read When the bit is written but the byte is not enabled there is no effect Conceptually this is Read to Set Write 1 to Clear RW Read Write bit s These bits can be read and written by software Hardware may only change the state of this bit by reset RW1C Read Write 1 to Clear bit s These bits can be read Internal events may set this bit A software write of 1 clears sets to 0 the corresponding bit s and a write of 0 has no effect RW1C L S Read Write 1 to Clear Lockable Sticky bit s These bits can be read Internal events may set this bit A software write of 1 clears sets to 0 the corresponding bit s and a write of 0 has no effect Bits are not cleared by warm reset but is r
103. by the MDAP configuration bit When MDAP is set the processor will decode legacy monochrome 10 ranges and forward them to the DMI Interface The IO ranges decoded for the monochrome adapter are 3B4h 3B5h 3B8h 3B9h 3Bah and 3BFh Datasheet Volume 2 Processor Configuration Registers 7 t 2 3 2 3 1 Note Note Note that the processor Device 1 I O address range registers defined above are used for all I O space allocation for any devices requiring such a window on PCI Express The PCICMD1 register can disable the routing of I O cycles to PCI Express Configuration Process and Registers Platform Configuration Structure The DMI physically connects the processor and the Intel PCH so from a configuration standpoint the DMI is logically PCI Bus 0 As a result all devices internal to the processor and the Intel PCH appear to be on PCI Bus 0 The PCH internal LAN controller does not appear on Bus 0 it appears on the external PCI bus whose number is configurable The system s primary PCI expansion bus is physically attached to the PCH and from a configuration perspective appears to be a hierarchical PCI bus behind a PCI to PCl bridge and therefore has a programmable PCI Bus number The PCI Express Graphics Attach appears to system software to be a real PCI bus behind a PCI to PCI bridge that is a device resident on PCI Bus 0 A physical PCI bus O does not exist DMI and the internal devices in the processor and P
104. cece ee etree ee eee ee eee eee na ea eas 230 Datasheet Volume 2 7 D 2 17 2 18 2 16 6 RTADDR_REG Root Entry Table Address Register l enn 231 2 16 7 CCMD_REG Context Command Reg SteEr ssssrsrrrrrrrrrrrrrerrerrrrrrirerieree 232 2 16 8 FSTS REG Fault Status Register s sssssressrsurrnrrnsrnsrnnnnnnnrnrrnnrnenennrens 234 2 16 9 FECTL_REG Fault Event Control Register ssssssrsrrrrrrrrrrsrrrrrrerrreersenua 235 2 16 10 FEDATA_REG Fault Event Data Register ssssssssrrsrrsrrrrrirrrrrrrrrrrrrrerr 236 2 16 11 FEADDR_REG Fault Event Address ReQiSter ccccceeeeeeeee tees tate enna ees 236 2 16 12 FEUADDR_REG Fault Event Upper Address Register eeeeee eee es 237 2 16 13 AFLOG_REG Advanced Fault Log Register cceceeeeeee ee ee eee e eaten ened 237 2 16 14 PMEN_REG Protected Memory Enable Register nencen 238 2 16 15 PLMBASE REG Protected Low Memory Base ReQiSteP cseeeeee eres 239 2 16 16 PLMLIMIT_REG Protected Low Memory Limit Register iaer 240 2 16 17 PHMBASE_REG Protected High Memory Base Register acceca 241 2 16 18 PHMLIMIT_REG Protected High Memory Limit Register eee 242 2 16 19 IQH REG Invalidation Queue Head ReGiSter cc ceceee reee 243 2 16 20 IQT_REG Invalidation Queue Tail Register c icici ee eee eee ee eee ee ea ed 243 2 16 21 IQA REG Invalidation Queue Address RegiSter cceceeeeeeeee
105. condition using SERR messaging is disabled SERR on Hot Thermal Sensor Event HOTSERR 4 RW Ob 1 Do not mask the generation of a SERR DMI cycle on a Hot thermal sensor trip 0 Disable Reporting of this condition using SERR messaging is disabled SERR on Aux 3 Thermal Sensor Event AUX3SERR 3 RW Ob 1 Do not mask the generation of a SERR DMI cycle on a Aux3 thermal sensor trip 0 Disable Reporting of this condition using SERR messaging is disabled SERR on Aux 2 Thermal Sensor Event AUX2SERR 2 Ob 1 Do not mask the generation of a SERR DMI cycle on a Aux2 thermal RW sensor trip 0 Disable Reporting of this condition using SERR messaging is disabled SERR on Aux 1 Thermal Sensor Event AUX1SERR 1 Do not mask the generation of a SERR DMI cycle on a Aux1 thermal 1 RW Ob sensor trip 0 Disable Reporting of this condition using SERR messaging is disabled SERR on Aux 0 Thermal Sensor Event AUXOSERR 0 RW Ob 1 Do not mask the generation of a SERR DMI cycle on a Aux0 thermal sensor trip 0 Disable Reporting of this condition using SERR messaging is disabled Datasheet Volume 2 103 Processor Configuration Registers intel 2 8 50 TSMICMD Thermal SMI Command Register This register selects specific errors to generate a SMI DMI cycle as enabled by the SMI Error Command Register SMI on Thermal Sensor Trip B D F Type 0 0 0 MCHBAR Address Offset 10E5h Reset Value 00h Access R
106. correspond to TC values For example 7 1 RW 7Fh when bit 7 is set in this field TC7 is mapped to this VC resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link 0 RO lb TCO VCO Map TCOVCOM Traffic Class 0 is always routed to VCO 2 11 6 VCORSTS VCO Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 1 0 MMR Address Offset 11A 11Bh Reset Value 0002h Access RO Reset aoi Bit Attr Value Description 15 2 RO 0000h Reserved and Zero VCO Negotiation Pending VCONP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control initialization It is 1 RO 1b set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Ob Reserved for Port Arbitration Table Status Datasheet Volume 2
107. device page selective invalidation request 010 Domain selective invalidation performed using the domain id specified by software in the DID field This could be in response to a domain selective domain page selective or device page selective invalidation request 011 Domain page selective invalidation performed using the address mask and hint specified by software in the Invalidate Address register and domain id specified in DID field This can be in response to a domain page selective or device page selective invalidation request 100 111 Reserved 56 50 RO 00h Reserved Drain Reads DR This field is ignored by hardware if the DRD field is reported as clear in the Capability register When the DRD field is reported as set in the Capability register the following encodings are supported for this field 0 Hardware may complete the IOTLB invalidation without draining any 49 RW 000000h translated DMA reads that are queued in the root complex and yet to be processed 1 Hardware must drain all relevant translated DMA reads that are queued in the root complex before indicating OTLB invalidation completion to software A DMA read request to system memory is defined as drained when root complex has finished fetching all of its read response data from memory Drain Writes DW This field is ignored by hardware if the DWD field is reported as clear in the Capability register When DWD field is reported as set
108. draining DMA Write Draining DWD 0 On IOTLB invalidations hardware does not support draining of DMA 54 RO 1b writes 1 On IOTLB invalidations hardware supports draining of DMA writes Refer to VTd specification Section 6 3 for description of DMA draining Maximum Address Mask Value MAMV 53 48 RO 09h The value in this field indicates the maximum supported value for the f Address Mask AM field in the Invalidation Address IVA_REG register This field is valid only when the PSI field is reported as Set Number of Fault Recording Registers NFR This field indicates a value of N 1 where N is the number of fault recording registers supported by hardware 47 40 RO 00h Implementations must support at least one fault recording register NFR 0 for each DMA remapping hardware unit in the platform The maximum number of fault recording registers per DMA remapping hardware unit is 256 Page Selective I nvalidation Support PSI 0 Hardware supports only domain and global invalidates for OTLB 39 RO 1b f i i 1 Hardware supports page selective domain and global invalidates for IOTLB and hardware must support a minimum MAMV value of 9 38 RO Ob Reserved Super Page Support SPS This field indicates the super page sizes supported by hardware A value of 1 in any of these bits indicates the corresponding super page size is supported The super page sizes corresponding to various bit positions within this field are 0 21 bit offset to p
109. due to other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field e Software servicing the WC field in the Invalidation Completion Status register 00 00b Reserved Datasheet Volume 2 Processor Configuration Registers 2 18 24 2 18 25 intel IEDATA_REG I nvalidation Completion Event Data Register This register specifies the Invalidation Event interrupt message data The register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 2 0 GFXVTBAR Address Offset A4 A7h Reset Value 0000_0000h Access RO Reset are Bit Attr Value Description Extended I nterrupt Message Data EI MD This field is valid only for implementations supporting 32 bit interrupt data 31 16 RO 0000h fields Hardware implementations supporting only 16 bit interrupt data treat this field as reserved Interrupt Message Data IMD 15 0 RO 0000h Data value in the interrupt request Software requirements for programming this register are described in the VTd specification EVADDR_REG I nvalidation
110. eee eee eae 244 2 16 22 ICS REG Invalidation Completion Status Register cceeeeeee eee ee 244 2 16 23 ECTL_REG Invalidation Event Control Register cccceeeeeeee eee ee teens 245 2 16 24 IEDATA_REG Invalidation Event Data Register cece eeee nent teens 246 2 16 25 IEADDR_REG Invalidation Event Address Register cccceeeeeeee ee eee es 246 2 16 26 IEUADDR_REG Invalidation Event Upper Address Register 05 247 2 16 27 IRTA_REG Interrupt Remapping Table Address Register i c 247 2 16 28 IVA_REG Invalidate Address ReGiSter ccceceeeee neste teen ee eee anata e nee ees 248 2 16 29 IOTLB_REG IOTLB Invalidate Register cece eee tee eee e eee ee enna 249 2 16 30 FRCD_REG Fault Recording ReGiSters ccceeceee eee ee eee ee eee eee eee ed 251 2 16 31 VTPOLICY DMA Remap Engine Policy Control cccceceeeeee eee eee eee ee 252 Graphics Control ReQiSters cceceee eect een eee eee ee A AiE AEA 253 2 17 1 MGGC Graphics Control Register eceeeee cece eee eee eee neta eee ne natn 253 247 2 GFXPLEI GFX PLL BlOS ereronde aaen i eeii 254 GFXVTBAR REQISTEF S isunen inini anin EAEEREN ENA ERRE E E inn RAA RnR iN 255 2 18 1 VER_REG Version Register sssssssrsrrsrrrsrtrnrrnrrntrnrrnenrinrrnrrrerrerrenrent 256 2 18 2 CAP_REG Capability Register esssssrsssssrrrerirsrrrrrrrnrrnrnrnrintrrreresrinr 257 2 18 3 ECAP_REG Ex
111. eees 208 2 15 24 EDATA_REG Invalidation Event Data RegiSter cccceseeeeee eee eaee es 209 2 15 25 IEADDR_REG Invalidation Event Address ReQiSter ccceceeeeeeeeee teens 209 2 15 26 EUADDR_REG Invalidation Event Upper Address Register 5005 210 2 15 27 IRTA_REG Interrupt Remapping Table Address Register 210 2 15 28 IVA_REG Invalidate Address Register ssssrsresrrsrrrrrrrrrrrrrrrrrrrrrrrrree 211 2 15 29 IOTLB_ REG IOTLB Invalidate Register cceccececeeeeeee seen ee eeeea een ea ee es 212 2 15 30 FRCD_REG Fault Recording Registers cceceee cece nent ee eee eee e neta eee ne as 214 2 15 31 VTCMPLRESR VT Completion Resource Dedication eceeeeeee eee ee 215 2 15 32 WVTFTCHARBCTL VCO VCp VTd Fetch Arbiter Control cceceeeeeeeee eee 216 2 15 33 PEGVTCMPLRESR PEG VT Completion Resource Dedication 4 217 2 15 34 VTPOLICY DMA Remap Engine Policy Control 219 2 16 DMI VCI REMAP ReGiSters c cece cece eee een eee ene nee rete eee enana eae 221 2 16 1 VER_REG Version ReGiSter c cece ce teeter erent terete rritni rrr nnrir rrene 222 2 16 2 CAP_REG Capability Register c cece cece cence eee eee teeta ee rrien ns 223 2 16 3 ECAP_REG Extended Capability Register 225 2 16 4 GCMD_REG Global Command ReGister cccceeeeeesee ee eect eee eee teen eaee es 227 2 16 5 GSTS REG Global Status Register
112. enables generation of an interrupt on enabled hot 5 RO Ob plug events Ea l l l The Reset Value of this field is Ob If the Hot Plug Capable field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob Reserved for Command Completed Interrupt Enable CCI If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register when set to 4 RO Ob 1b this bit enables software notification when a hot plug command is completed by the Hot Plug Controller Reset Value of this field is Ob If Command Completed notification is not supported this bit must be hardwired to Ob Presence Detect Changed Enable PDCE 3 RW Ob When set to 1b this bit enables software notification on a presence detect changed event Reserved for MRL Sensor Changed Enable MSCE When set to 1b this bit enables software notification on a MRL sensor 2 RO Ob changed event Reset Value of this field is Ob If the MRL Sensor Present field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob Reserved for Power Fault Detected Enable PFDE 1 RO Ob When set to 1b this bit enables software notification on a power fault event Reset Value of this field is Ob If Power Fault detection is not supported this bit is permitted to be read only with a value of Ob Reserved for Attention Button Pressed Enable ABPE 0 RO Ob W
113. error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself System Error on Non Fatal Uncorrectable Error Enable SENFUEE This bit controls the Root Complex s response to non fatal errors 1 RW Ob 0 No SERR generated on receipt of non fatal error 1 Indicates that a SERR should be generated if a non fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself System Error on Correctable Error Enable SECEE This bit controls the Root Complex s response to correctable errors 0 RW Ob 0 No SERR generated on receipt of correctable error 1 Indicates that a SERR should be generated if a correctable error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself Datasheet Volume 2 Processor Configuration Registers intel 2 19 45 RSTS Root Status This register provides information about PCI Express Root Complex specific parameters B D F Type 0 6 0 PCI Address Offset C0 C3h Reset Value 00000000h Access RO RW1C Reset joai Bit Attr Value Description Reserved MBZ 31 18 RO moon For future R WC S implementations software must use 0 for writes to bits PME Pending PMEP This bit indicates that another PME is pending when the PME Status bit is set 17 RO Ob When the PME Status bit is cleared by
114. for Memory Base Address eae RW O0000090N Must be set to 0 since addressing above 64 GB is not supported Memory Base Address MBA 0000h Set by the OS these bits correspond to address signals 35 22 4 MB 35 22 RW combined for MMIO and Global GTT table aperture 512 KB for MMIO and 2 MB for GTT Reserved ai RO pogoen Hardwired to Os to indicate at least 4 MB address range 3 RO Ob Prefetchable Memory PREFMEM Hardwired to 0 to prevent prefetching Memory Type MEMTYP 00 To indicate 32 bit base address 2 1 RO 10b 01 Reserved 10 To indicate 64 bit base address 11 Reserved Memory 10 Space MI OS Hardwired to 0 to indicate memory space Datasheet Volume 2 179 intel 2 13 11 180 Processor Configuration Registers GMADR Graphics Memory Range Address Register The IGD graphics memory base address is specified in this register Software must not change the value in MSAC 1 0 offset 62h after writing to the GMADR register B D F Type 0 2 0 PCI Address Offset 18 1Fh Reset Value 0000_0000_0000_000Ch Access RO RW L RW i Reset ji Bit Attr Value Description Memory Base Address MBA2 63 36 RW 0000000h Memory Base Address MBA Set by the OS these bits correspond to address signals 63 36 Memory Base Address MBA 35 29 RW 0000000b Memory Base Address MBA Set by the OS these bits correspond to address signals 35 29 512MB Add
115. hardware unit in the platform The maximum number of fault recording registers per DMA remapping hardware unit is 256 Bit 40 in the capability register is the least significant bit of the NFR field 47 40 Page Selective I nvalidation Support PSI 0 DMAr engine does not support page selective invalidations 39 RO 1b 1 DMAr engine does support page selective IOTLB invalidations The MAMV field indicates the maximum number of contiguous translations that may be invalidated in a single request 38 RO Ob Reserved Super Page Support SPS This field indicates the super page sizes supported by hardware A value of 1 in any of these bits indicates the corresponding super page size is supported The super page sizes corresponding to various bit positions within this field 37 34 RO 0000b_ are 0 21 bit offset to page frame 1 30 bit offset to page frame 2 39 bit offset to page frame 3 48 bit offset to page frame Fault recording Register offset FRO This field specifies the location to the first fault recording register relative to 33 24 RO 020h the register base address of this DMA remapping hardware unit If the register base address is X and the value reported in this field is Y the address for the first fault recording register is calculated as X 16 Y Datasheet Volume 2 187 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 8 Fh Reset Value 00C90080206
116. in DRAM clocks between the PRE ALL and REF commands to the same rank Same Rank Refresh to Refresh Delay COsd_cr_rfsh_rfsh 8 0 RW 000h This field indicates the minimum allowed spacing in DRAM clocks between two REF commands to the same rank 2 8 15 COPWLRCTRL Channel 0 Partial Write Line Read Control Register This register configures the DRAM controller partial write policies B D F Type 0 0 0 MCHBAR Address Offset 265 266h Reset Value 0000h Access RW RO i Reset Bees Bit Attr Value Description 15 14 RO 00b Reserved Read And Merging write Window COsd_cr_rdmodwr_ window This configuration setting defines the time period in mclks between the 13 8 RW 00h read and the merging write commands on the DRAM bus This window duration is a function of the tRD and write data latency through the chipset 7 5 RO 000b Reserved Partial Write Trip Threshold PWTRIP 4 0 RW 00h This configuration setting indicates the threshold for number of partial writes which are blocked from arbitration before indicating a trip 78 Datasheet Volume 2 Processor Configuration Registers intel 2 8 16 COREFRCTRL Channel 0 DRAM Refresh Control Register This register provides settings to configure the DRAM refresh controller B D F Type Address Offset Reset Value Access 0 0 0 MCHBAR 269 26Eh 241830000C30h RW RO Bit Attr Reset Value Description
117. intel Intel Core i5 600 i3 500 Desktop Processor Series and Intel Pentium Desktop Processor 6000 Series Datasheet Volume 2 January 2011 Document Number 322910 003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining critical control or safety systems or in nuclear facility applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Core i7 800 and i5 700 desktop processor series and Intel Pentium desktop processor 6000 series may contain design defects or errors known a
118. invalidated Mask Value Addr bits masked Pg inval 0 Nil 1 1 12 2 5 0 Ww 00h 2 13 12 4 3 14 12 8 4 15 12 16 5 16 12 32 6 17 12 64 7 18 12 128 8 19 12 256 Hardware implementations report the maximum supported mask value through the Capability register Value returned on read of this field is undefined 248 Datasheet Volume 2 Processor Configuration Registers intel 2 16 29 OTLB_REG I OTLB I nvalidate Register This register is used to invalidate OTLB The act of writing the upper byte of the IOTLB_REG with IVT field set causes the hardware to perform the IOTLB invalidation B D F Type 0 0 0 DMI VC1REMAP Address Offset 108 10Fh Reset Value 0000000000000000h Access RO RW RW SC Reset on ges Bit Attr Value Description Invalidate OTLB I VT Software requests OTLB invalidation by setting this field Software must also set the requested invalidation granularity by programming the IIRG field Hardware clears the IVT field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the IAIG field Software must not submit another invalidation request through this register while the IVT field is set nor update 63 RW SC Ob the associated I nvalidate Address register Software must not submit IOTLB invalidation requests when there is a context cache invalidation request pending at this DMA remapping hard
119. is undefined 28 Ww Ob Enable Advanced Fault Logging EAFL This field is valid only for implementations supporting advanced fault logging If advanced fault logging is not supported writes to this field are ignored Software writes to this field to request hardware to enable or disable advanced fault logging 0 Disable advanced fault logging In this case translation faults are reported through the Fault Recording registers 1 Enable use of memory resident fault log When enabled translation faults are recorded in the memory resident log The fault log pointer must be set in hardware through SFL field before enabling advanced fault logging Hardware reports the status of the advanced fault logging enable operation through the AFLS field in the Global Status register Value returned on read of this field is undefined 27 wo Ob Write Buffer Flush WBF This bit is valid only for implementations requiring write buffer flushing If write buffer flushing is not required writes to this field are ignored Software sets this field to request hardware to flush the root complex internal write buffers This is done to ensure any updates to the memory resident DMA remapping structures are not held in any internal write posting buffers Refer to the VTd specification for details on write buffer flushing requirements Hardware reports the status of the write buffer flushing operation through the WBFS fie
120. less than 2 us 110 2 us 4 us 111 More than 4 us The actual value of this field depends on the common Clock Configuration bit LCTL 6 and the Common and Non Common clock LOs Exit Latency values in PEGLOSLAT Offset 22Ch 11 10 RW O 11b Active State Link PM Support ASLPMS This field indicates support for ASPM LOs and L1 9 4 RW O 08h Max Link Width MLW This field indicates the maximum number of lanes supported for this link 3 0 RW O 0010b Max Link Speed MLS This field indicates the supported Link speed s of the associated Port Defined encodings are 0001b 2 5GT s Link speed supported 0010b 5 0GT s and 2 5GT s Link speeds supported All other encodings are reserved Datasheet Volume 2 Processor Configuration Registers 2 19 39 LCTL Link Control Register This register allows control of PCI Express link B D F Type 0 6 0 PCI Address Offset BO B1h Reset Value 0000h Access RW RO RW SC Reset rar Bit Attr Value Description 15 12 RO 0000b Reserved Link Autonomous Bandwidth Interrupt Enable LABI E When Set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set 11 RW Ob This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Devices that do not implement the Link Bandw
121. link enters LO and resumes communication This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns 6 3 RO Oh Reserved Ob Reserved 1 0 RW 00b Active State Power Management Support ASPMS This field controls the level of active state power management supported on the given link 00 Disabled 01 LOs Entry Supported 10 L1 Entry Enabled 11 LOs and L1 Entry Supported 2 12 20 DMILSTS DMI Link Status Register B D F Type 0 0 0 DMI BAR Address Offset 8A 8Bh Reset Value 0001h Access RO Reset nara Bit Attr Value Description 15 10 RO 00h Reserved Negotiated Width NWI D This field indicates negotiated link width This field is valid only when the link is in the LO LOs or L1 states after link width negotiation is successfully completed 9 4 RO 00h 00h Reserved Olh X1 02h X2 04h X4 All other encodings are reserved Negotiated Speed NSPD This field indicates negotiated link speed 3 0 RO 1h 1h 2 5 Gb s All other encodings are reserved Datasheet Volume 2 173 intel Processor Configuration Registers 2 13 PCI Device 2 Function 0 Registers Table 2 10 PCI Device 2 Function 0 Register Address Map oo prae Register Name Reset Value Access 0 1h VI D2 Vendor Identification 8086h RO
122. master can do fast back to back write 9 RO Ob 4 A ae Since device 0 is strictly a target this bit is not implemented and is hardwired to 0 Writes to this bit position have no effect SERR Enable SERRE This bit is a global enable bit for Device 0 SERR messaging The processor does not have an SERR signal The processor communicates the SERR condition by sending an SERR message over DMI to the PCH 1 The processor is enabled to generate SERR messages over DMI for specific Device 0 error conditions that are individually enabled in the ERRCMD and DMIUEMSK registers The error status is reported in the 8 RW Ob ERRSTS PCISTS and DMIUEST registers 0 The SERR message is not generated by the processor for Device 0 This bit only controls SERR messaging for Device 0 Device 1 has its own SERRE bits to control error reporting for error conditions occurring in that device The control bits are used in a logical OR manner to enable the SERR DMI message mechanism 0 Device 0 SERR disabled 1 Device 0 SERR enabled Address Data Stepping Enable ADSTEP 7 RO Ob Address data stepping is not implemented in the processor and this bit is hardwired to 0 Writes to this bit position have no effect Parity Error Enable PERRE This bit controls whether or not the Master Data Parity Error bit in the PCI 6 RW Ob Status register can bet set 0 Master Data Parity Error bit in PCI Status register can NOT be set 1 Master Data Parity Error bit in PC
123. memory It is the responsibility of BIOS to properly initialize these regions Graphics Stolen Spaces GTT Stolen Space GSM GSM is allocated to store the GFX translation table entries depending on VT d support it may be divided into 2 sections Global GTT Stolen Space GGSM GGSM always exists regardless of VT d as long as internal GFX is enabled This space is allocated to store accesses as page table entries are getting updated through virtual GTTMMADR range Hardware is responsible to map PTEs into this physical space Direct accesses to GGSM is not allowed only hardware translations and fetches can be directed to GGSM Datasheet Volume 2 23 Processor Configuration Registers 2 2 2 6 3 Shadow GTT Stolen Space SGSM Shadow GSM will be only used once internal GFX and VT d translations are enabled The purpose of shadow GSM is to provide a physical space to hardware where VT d translation for PTE updates can be made on the fly and re written back into physical memory 2 2 2 7 Intel Management Engine Intel ME UMA ME the iAMT Manageability Engine can be allocated UMA memory ME memory is stolen from the top of the host address map The ME stolen memory base is calculated by subtracting the amount of memory stolen by the Manageability Engine from TOM Only ME can access this space it is not accessible by or coherent with any processor side accesses 2 2 2 8 PCI Memory Address Range TOLUD 4 GB This
124. not allow any transactions to proceed on the system memory bus if the output of the filter equals or exceeds this value 7 0 RW L 00h Weighted Average Thermal Limit WAT Average weighted bandwidth allowed per clock during for thermal sensor enabled throttling The processor does not allow any transactions to proceed on the system memory bus if the output of the filter equals or exceeds this value Datasheet Volume 2 93 intel Processor Configuration Registers 2 8 37 SSKPD Sticky Scratchpad Data Register This register holds 64 writable bits with no functionality behind them It is for the convenience of BIOS and graphics drivers B D F Type 0 0 0 MCHBAR Address Offset C20 C27h Reset Value 0000_0000_0000_0000h Access RW P Reset Eee Bit Attr Value Description 63 0 RW S 00 00b Scratchpad Data SKPD 4 Words of data storage 2 8 38 TSC1 Thermal Sensor Control 1 Register This register controls the operation of the internal thermal sensor located in the graphics region of the die B D F Type 0 0 0 MCHBAR Address Offset 1001 1002h Reset Value 0000h Access RW L RO RW AF A Reset ee Bit Attr Value Description 15 14 RO 00b Reserved Digital Hysteresis Amount DHA This bit enables the analog hysteresis control to the thermal sensor When enabled about 1 degree of hysteresis is applied This bit shoul
125. of Flow Control initialization It is set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Ob Reserved Datasheet Volume 2 167 Processor Configuration Registers intel 2 12 11 DMIVCPRCTL DMI VCp Resource Control Register This register controls the resources associated with the DMI Private Channel B D F Type 0 0 0 DMIBAR Address Offset 2C 2Fh Reset Value 0000_0000h Access RW RO Reset P Bit Attr Value Description Virtual Channel Enable VCE 0 Virtual Channel is disabled 1 Virtual Channel is enabled See exceptions below Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete When VC Negotiation Pending bit is cleared a 1 read from this VC Enable bit indicates that the VC is enabled Flow Control Initialization is completed for the PCI Express port A 0 read from this bit indicates that the Virtual Channel is currently disabled 31 RW Ob BIOS Requirement 1 To enable a Virtual Channel the VC Enable bits for that Virtual Channel must be set in both Components on a Link 2 To disable a Virtual Channel the VC Enable bits for that Virtu
126. predetermined default states Some register values at reset are determined by external strapping options The Reset Value default state represents the minimum functionality feature set required to successfully bring up upon a the system Hence it does not represent the optimal system configuration It is the Reset responsibility of the system initialization software usually BIOS to properly determine the DRAM configurations operating parameters and optional system features that are applicable and to program the processor registers accordingly ST The bit is sticky or unchanged by a hard reset These bits can only be cleared by a PWRGOOD appended to the end of a bit name reset MBZ Must Be Zero when writing this bit Datasheet Volume 2 Intel QuickPath Architecture System Address Decode Register Description t I 3 2 Platform Configuration Structure The processor contains PCI devices within a single physical component The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket Bus number is derived by the maximum bus range setting and processor socket number e Device 0 Generic processor non core Device 0 Function 0 contains the generic non core configuration registers for the processor and resides at DID Device ID of 2C62h Device 0 Function 1 contains the System Address Decode registers and resides at DID of 2D01h
127. processor documentation e ISA Expansion Area 000C_0000h O000D_FFFFh e Extended System BIOS Area OOOE_0000h OOOE_FFFFh e System BIOS Area 000F_0000h OOOF_FFFFh The processor contains the PAM registers and the GMCH has no knowledge of the register programming The processor decodes the request and routes to the appropriate destination DRAM or DMI by sending the request on HOM or NCS NCB Snooped accesses from PCI Express or DMI to this region are snooped on QPI Non snooped accesses from PCI Express or DMI to this region are always sent to DRAM Graphics translated requests to this region are not allowed If such a mapping error occurs the request will be routed to 000C_0000h Writes will have the byte enables de asserted Datasheet Volume 2 Processor Configuration Registers t 2 2 2 Main Memory Address Range 1MB TOLUD This address range extends from 1 MB to the top of Low Usable physical memory that is permitted to be accessible by the GMCH as programmed in the TOLUD register The processor will route all addresses within this range as HOM accesses which will be forwarded by the GMCH to the DRAM unless it falls into the optional TSEG optional ISA Hole or optional IGD stolen VGA memory Figure 2 3 Main Memory Address Range 2 2 2 1 FFFF_FFFFh 4 GB Max FLASH APIC Intel TXT Contains Dev 0 1 2 6 BARS PCI Memory Range and PCH PCI ranges TOLUD IG
128. registers have no effect on the processor Registers that are marked as Intel Reserved must not be modified by system software Writes to Intel Reserved registers may cause system failure Reads from Intel Reserved registers may return a non zero value Upon a Full Reset the processor sets its entire set of internal configuration registers to predetermined default states Some register values at reset are determined by external strapping options The default state represents the minimum functionality feature set required to successfully bringing up the system Hence it does not represent the optimal system configuration It is the responsibility of the system initialization software usually BIOS to properly determine the DRAM configurations operating parameters and optional system features that are applicable and to program the processor registers accordingly I O Mapped Registers The processor contains two registers that reside in the processor I O address space the Configuration Address CONFIG_ADDRESS Register and the Configuration Data CONFIG_DATA Register The Configuration Address Register enables disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window Datasheet Volume 2 Processor Configuration Registers 2 7 Table 2 4 PCI Express Device 0 Registers intel Table 2 4 shows the PCI Express Device 0 register address map Detailed register
129. reported as set in the Capability register the following encodings are supported for this field 49 RW Ob 0 Hardware may complete the OTLB invalidation without draining any translated DMA reads that are queued in the root complex and yet to be processed 1 Hardware must drain all relevant translated DMA reads that are queued in the root complex before indicating OTLB invalidation completion to software Refer to the VTd specification for description of DMA draining Drain Writes DW This field is ignored by hardware if the DWD field is reported as clear in the Capability register When DWD field is reported as set in the Capability register the following encodings are supported for this field 48 RW Ob 0 Hardware may complete the OTLB invalidation without draining any translated DMA writes that are queued in the root complex for processing 1 Hardware must drain all relevant translated DMA writes that are queued in the root complex before indicating OTLB invalidation completion to software Refer to the VTd specification for description of DMA draining Domain ID DID Indicates the ID of the domain whose IOTLB entries need to be selectively invalidated This field must be programmed by software for domain selective and domain page selective invalidation requests eee RW goo0h The Capability register reports the domain id width supported by hardware Software must ensure that the value written to this field is w
130. request and bits 47 12 are cleared This field is relevant only when the F field is set RO 000h Reserved Datasheet Volume 2 251 intel Processor Configuration Registers 2 16 31 VTPOLICY DMA Remap Engine Policy Control This registers contains all the policy bits related to the DMA remap engine 252 Access B D F Type Address Offset Reset Value 0 0 0 DMIVCLREMAP FFC FFFh 00000000h RO RW L K RW L Bit Attr Reset Value Description 31 RW L K Ob DMA Remap Engine Policy Lock Down DMAR_LCKDN This bit protects all the DMA remap engine specific policy configuration registers Once this bit is set by software all the DMA remap engine registers within the range OxFOO to OxFFC will be read only This bit can only be clear through platform reset 30 5 RO 0000000h Reserved Ob TLB Lookup Policy TLB I nvalidation LKUPPTLBI NV DMI Intel High Definition Audio Remap Engine TLB Lookup Policy On TLB Invalidation 1 Mask all TLB Lookup to DMI Intel High Definition Audio remap engine during TLB Invalidation Window 0 Continue to perform TLB lookup to DMI Intel High Definition Audio remap engine during TLB Invalidation Window TLB Invalidation Window refers to the period from when the TLB Invalidation is initiated until all the outstanding DMA read and write cycles at the point of TLB Invalidation are initiated are Globally Or
131. setup before enabling the DMA remapping hardware units To optimally support platform configurations supporting varying amounts of main memory the protected memory region is defined as two non overlapping regions Protected Low memory Region This is defined as the protected memory region below 4 GB to hold the MVMM code private data and the initial DMA remapping structures that control DMA to host physical addresses below 4 GB DMA remapping hardware implementations on platforms supporting Intel TXT are required to support protected low memory region 5 e Protected High memory Region This is defined as a variable sized protected memory region above 4 GB enough to hold the initial DMA remapping structures for managing DMA accesses to addresses above 4 GB DMA remapping hardware implementations on platforms supporting Intel TXT are required to support protected high memory region 6 if the platform supports main memory above 4 GB Datasheet Volume 2 Processor Configuration Registers 7 t 2 2 2 4 2 2 2 5 2 2 2 6 2 2 2 6 1 2 2 2 6 2 Once the protected low high memory region registers are configured bus master protection to these regions is enabled through the Protected Memory Enable register For platforms with multiple DMA remapping hardware units each of the DMA remapping hardware units must be configured with the same protected memory regions and enabled DRAM Protected Range DPR This protection range onl
132. software the PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately The PME pending bit is cleared by hardware if no more PMEs are pending PME Status PMES 16 RW1C Ob This bit indicates that PME was asserted by the requestor D indicated in the PME Requestor ID field Subsequent PMEs are kept pending until the status register is cleared by writing a 1 to this field i PME Requestor ID PMERI D 15 0 RO 0090h This bit indicates the PCI requestor ID of the last PME requestor 2 19 46 PEGLC PCI Express G Legacy Control Register This register controls functionality that is needed by Legacy non PCI Express aware OSs during run time B D F Type 0 6 0 PCI Address Offset EC EFh Reset Value 0000_0000h Access RO RW i Reset heen Bit Attr Value Description 31 3 RO 00 00b Reserved PME GPE Enable PMEGPE 0 Do not generate GPE PME message when PME is received 2 RW Ob 1 Generate a GPE PME message when PME is received Assert_ PMEGPE and Deassert_PMEGPE messages on DMI This enables the MCH to support PMEs on the PEG port under legacy OSs Hot Plug GPE Enable HPGPE 0 Do not generate GPE Hot Plug message when Hot Plug event is 1 RW Ob received 1 Generate a GPE Hot Plug message when Hot Plug Event is received Assert_HPGPE and Deassert_HPGPE messages on DMI This enables the MCH to support Hot Plug on the PEG port
133. supported therefore will have no address translation concerns PCI Express and DMI Interface reads to GMADR will be remapped to address 000C_0000h The read will complete with UR unsupported request completion status GTT fetches are always decoded at fetch time to ensure that they are not in SMM actually anything above base of TSEG or 640 KB 1 MB Thus they will be invalid and go to address 000C_0000h but that is not specific to PCI Express or DMI it applies to the processor or internal graphics engines 1 O Address Space The processor generates either DMI Interface or PCI Express bus cycles for all processor O accesses that it does not claim The processor no longer contains the two internal registers in the processor I O space Configuration Address Register CONFIG_ADDRESS and the Configuration Data Register CONFIG_DATA The processor now handles accesses to these registers which ultimate generate a QPI configuration access The processor allows 64K 3 bytes to be addressed within the I O space The processor propagates the processor I O address without any translation on to the destination bus and therefore provides addressability for 64K 3 byte locations Note that the upper 3 Datasheet Volume 2 35 m t l Processor Configuration Registers 2 2 9 1 36 locations can be accessed only during I O address wrap around when address bit 16 is asserted Address bit 16 is asserted on the processor bus whenever an I
134. supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC that is prefetchable from the processor perspective B D F Type 0 6 0 PCI Address Offset 26 27h Reset Value 0001h Access RO RW x Reset a gic Bit Attr Value Description Prefetchable Memory Address Limit PMLI MIT 15 4 RW 000h This field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express G 64 bit Address Support Reserved 3 0 RO th Indicates that the upper 32 bits of the prefetchable memory region limit address are contained in the Prefetchable Memory Base Limit Address register at 2Ch Datasheet Volume 2 301 m t 1 Processor Configuration Registers 2 19 19 302 PMBASEU6 Prefetchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implementation This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of
135. target abort does not exist on primary side of this device Signaled Target Abort Status STAS 11 RO Ob Not Applicable or Implemented Hardwired to 0 The concept of a target abort does not exist on primary side of this device DEVSELB Timing DEVT 10 9 RO 00b This device is not the subtractively decoded device on bus 0 This bit field is i therefore hardwired to 00 to indicate that the device uses the fastest possible decode Master Data Parity Error PMDPE Because the primary side of the PEG s virtual P2P bridge is integrated with the MCH functionality there is no scenario where this bit will get set Because hardware will never set this bit it is impossible for software to have an 8 RO Ob opportunity to clear this bit or otherwise test that it is implemented The PCI specification defines it as a R WC but for our implementation an RO definition behaves the same way and will meet all Microsoft testing requirements This bit can only be set when the Parity Error Enable bit in the PCI Command register is set Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 6 RO Ob Reserved 66 60MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 Capabilities List CAPL Indicates that a capabilities list is present Hardwired to 1 INTA Status INTAS Indicates that an interrupt message is pending internally to the device Only PME and Hot Plug sources feed into this s
136. the Fault F field in all the Fault Recording registers with faults causing the PPF field in the Fault Status register to be evaluated as Clear Software clearing other status fields in the Fault Status register by writing back the value read from the respective fields 00 00h Reserved Datasheet Volume 2 235 Processor Configuration Registers intel 2 16 10 FEDATA_REG Fault Event Data Register This register specifies the interrupt message data B D F Type 0 0 0 DMIVC1REMAP Address Offset 3C 3Fh Reset Value 00000000h Access RO RW Reset E Bit Attr Value Description Extended Interrupt Message Data EI MD This field is valid only for implementations supporting 32 bit MSI data fields Hardware implementations supporting only 16 bit MSI data may treat this field as read only 0 31 16 RO 0000h Interrupt message Data ID 15 0 RW 0000h Data value in the interrupt request Software requirements for programming this register are described in the VTd specification 2 16 11 FEADDR_REG Fault Event Address Register This Register specifies the interrupt message address B D F Type 0 0 0 DMIVC1REMAP Address Offset 40 43h Reset Value 00000000h Access RW RO Reset ones Bit Attr Value Description Message Address MA 00000000 When fault events are enabled the contents of this register specify the 31 2 RW h DWORD aligned addr
137. the dref_high flag is set 17 16 RW 00b 00 3 01 4 10 5 11 6 DRAM Refresh Low Watermark REFLOWWM When the refresh count exceeds this level a refresh request is launched to the scheduler and the dref_low flag is set 15 14 RW 00b 00 1 01 2 10 3 11 4 Refresh Counter Time Out Value REFTIMEOUT Program this field with a value that will provide 7 8 us at mb4clk frequency At various mb4clk frequencies this results in the following values 266 MHz gt 820 hex 13 0 oe oc30h 333 MHz gt A28 hex 400 MHz gt C30 hex 533 MHz gt 1040 hex 666 MHz gt 1450 hex Datasheet Volume 2 Processor Configuration Registers 2 8 17 COJ EDEC Channel 0 J EDEC Control Register This is the Channel 0 J EDEC Control Register B D F Type Address Offset Reset Value Access 0 0 0 MCHBAR 271h 00h RW RO Bit Attr Reset Value Description Ob Functional Loopback Mode Enable FLME This configuration setting indicates that the chip is placed in FME Functional Loopback Mode Enable mode Ob Write Levelization Mode WRLVLMDE This configuration bit indicates that memory controller is in write levelization mode 5 4 RW 00b EMRS Mode sd0_cr_emrs_ mode This configuration field indicates the type of the EMRS command being issued as a part of the J EDEC initialization 00 no EMRS command 01 EMRS 10 EMRS2 11 EMRS3 3 1 RW 000b Mode Select sdO_cr_sms
138. the interrupt message data B D F Type 0 2 0 GFXVTBAR Address Offset 3C 3Fh Reset Value 00000000h Access RO RW f Reset er Bit Attr Value Description Extended Interrupt Message Data EID This field is valid only for implementations supporting 32 bit interrupt data 31 16 RO 0000h fields Hardware implementations supporting only 16 bit interrupt data treat this field as reserved Interrupt message data ID 15 0 RW 0000h Data value in the interrupt request Software requirements for programming this register are described in the VTd specification 2 18 11 FEADDR_REG Fault Event Address Register This register specifies the interrupt message address 2 18 12 B D F Type 0 2 0 GFXVTBAR Address Offset 40 43h Reset Value 0000_ 0000h Access RW RO Reset icia Bit Attr Value Description Message Address MA 0000 000 When fault events are enabled the contents of this register specify the 31 2 RW Oh DWORD aligned address bits 31 2 for the interrupt request Software requirements for programming this register are described in the VTd specification 1 0 RO 00b Reserved FEUADDR_REG Fault Event Upper Address Register This register specifies the interrupt message upper address This register is treated as reserved by implementations reporting Extended Interrupt Mode EIM as not supported in the Extended Capability register B D F Type 0
139. the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Memory range covered by MBASE and MLIMIT registers are used to map non prefetchable PCI Express G address ranges typically where control status memory mapped I O data structures of the graphics controller will reside and PMBASE and PMLIMIT are used to map prefetchable address ranges typically graphics local memory This segregation allows application of USWC space attribute to be performed in a true plug and play manner to the prefetchable address range for improved processor PCI Express memory access performance Configuration software is responsible for programming all address range registers prefetchable non prefetchable with the values that provide exclusive address ranges that is prevent overlap with each other and or with the ranges covered with the main memory There is no provision in the processor hardware to enforce prevention of overlap and operations of the system in the case of overlap are not ensured B D F Type 0 1 0 PCI Address Offset 22 23h Reset Value 0000h Access RW RO A Re
140. threshold for number of partial writes which are blocked from arbitration before indicating a trip C1LODTCTRL Channel 1 ODT Control Register This register provides ODT controls B D F Type 0 0 0 MCHBAR Address Offset 69C 69Fh Reset Value 0000_0000h Access RO RW Reset PORE Bit Attr Value Description 31 12 RO 00000h Reserved DRAM ODT for Read Commands sd1_cr_odt_duration_rd 11 8 RW Oh This field specifies the duration in DRAM bus clocks to assert DRAM ODT for Read Commands The Async value should be used when the Dynamic Powerdown bit is set Otherwise use the Sync value DRAM ODT for Write Commands sd1_cr_odt_duration_wr 7 4 RW Oh This field specifies the duration in DRAM bus clocks to assert DRAM ODT for Write Commands The Async value should be used when the Dynamic Powerdown bit is set Otherwise use the Sync value MCH ODT for Read Commands sd1_cr_mchodt_ duration 3 0 RW Oh This field specifies the duration in DRAM bus clocks to assert MCH ODT for Read Commands Datasheet Volume 2 Processor Configuration Registers intel 2 8 36 C1DTC Channel 1 DRAM Throttling Control Register Programmable Event weights are input into the averaging filter Each Event weight is an normalized 8 bit value that the BIOS must program The BIOS must account for burst length and 1N 2N rule considerations It is also possible for BIOS to take into account loading variations of me
141. time a fault event is generated based on the programming of the Fault Event Control register Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as reserved 268 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 2 0 GFXVTBAR Address Offset 34 37h Reset Value 00000000h Access RO RW1C S RO V S 5 Reset ae Bit Attr Value Description Primary Pending Fault PPF This field indicates if there are one or more pending faults logged in the fault recording registers Hardware computes this field as the logical OR of Fault F fields across all the fault recording registers of this remapping hardware 1 RO V S Ob unit l l l l 0 No pending faults in any of the fault recording registers 1 One or more fault recording registers has pending faults The FRI field is updated by hardware whenever the PPF field is Set by hardware Also depending on the programming of Fault Event Control register a fault event is generated when hardware sets this field Primary Fault Overflow PFO 0 RW1C Ob Hardware sets this field to indicate overflow of the fault recording registers S Software writing 1 clears this field When this field is Set hardware does not record any new faults until software clears this field Datasheet Volume 2 269 Processor Configuration Registers intel 2 18 9 FECTL_REG Fault
142. to 0 RO Ob Memory Write and I nvalidate Enable MWIE Not Applicable or Implemented Hardwired to 0 RO Ob Special Cycle Enable SCE Not Applicable or Implemented Hardwired to 0 RW Ob Bus Master Enable BME This bit controls the ability of the PEG port to forward Memory and 10 Read Write Requests in the upstream direction 0 This device is prevented from making memory or IO requests to its primary bus Note that according to PCI Specification as MSI interrupt messages are in band memory writes disabling the bus master enable bit prevents this device from generating MSI interrupt messages or passing them from its secondary bus to its primary bus Upstream memory writes reads O writes reads peer writes reads and MSIs will all be treated as illegal cycles Writes are forwarded to memory address C0000h with byte enables de asserted Reads will be forwarded to memory address C0000h and will return Unsupported Request status or Master abort in its completion packet 1 This device is allowed to issue requests to its primary bus Completions for previously issued memory read requests on the primary bus will be issued when the data is available This bit does not affect forwarding of Completions from the primary interface to the secondary interface RW Ob Memory Access Enable MAE 0 All of device 1 s memory space is disabled 1 Enable the Memory and Pre fetchable memory address ranges defin
143. to this VC resource When more 7 1 RW 7Fh than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link TCO VCO Map TCOVCOM Traffic Class 0 is always routed to VCO Datasheet Volume 2 111 intel 2 9 4 Processor Configuration Registers EPVCORCAP EP VC O Resource Capability Register B D F Type 0 0 0 PXPEPBAR 112 Address Offset 10 13h Reset Value 0000 _0001h Access RO A Reset oe Bit Attr Value Description 31 24 RO 00h Reserved for Port Arbitration Table Offset No VCO port arbitration necessary 23 RO Ob Reserved Reserved for Maximum Time Slots 22 1 RO 00h o No VCO port arbitration necessary Reject Snoop Transactions RSNPT 0 Transactions with or without the No Snoop bit set within the TLP header 15 RO Ob are allowed on this VC 1 When Set any transaction for which the No Snoop attribute is applicable but is not Set within the TLP Header will be rejected as an Unsupported Request 14 8 RO 00h Reserved Port Arbitration Capability PAC 7 0 RO Olh This field indicates types of Port Arbitration supported by this VCO resource The Reset Value of 01h indicates that the only port arbitration capability for VCO is non configurable hard
144. under legacy OSs General Message GPE Enable GENGPE 0 Do not forward received GPE assert de assert messages 1 Forward received GPE assert de assert messages These general GPE 0 RW Ob message can be received using the PEG port from an external Intel device that is PxH and will be subsequently forwarded to the PCH using Assert_GPE and Deassert_GPE messages on DMI For example PxH might send this message if a PCI Express device is hot plugged into a PxH downstream port Datasheet Volume 2 327 intel Processor Configuration Registers 2 20 Device 6 Extended Configuration Registers Note Device 6 is not supported on all SKUs Table 2 15 Device 6 Extended Configuration Register Address Map goonies pare Register Name Reset Value Access 104 107h PVCCAP1 Port VC Capability Register 1 00000000h RO 108 10Bh PVCCAP2 Port VC Capability Register 2 00000000h RO 10C 10Dh PVCCTL Port VC Control 0000h RO RW 110 113h VCORCAP VCO Resource Capability 00000001h RO 114 117h VCORCTL VCO Resource Control 800000FFh RO RW 11A 11Bh VCORSTS VCO Resource Status 0002h RO 140 143h RCLDECH Root Complex Link Declaration Enhanced 00010005h RO 2 20 1 PVCCAP1 Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 6 0 MMR Address Offset 104 107h Reset Val
145. with a value less than the protected low memory base register disables the protected low memory region B D F Type 0 0 0 VCOPREMAP Address Offset 6C 6Fh Reset Value 00000000h Access RW RO P Reset PERE Bit Attr Value Description Protected Low Memory Limit PLML 31 21 RW 000h This register specifies the last host physical address of the DMA protected low memory region in system memory 20 0 RO 000000h Reserved Datasheet Volume 2 Processor Configuration Registers intel 2 15 17 PHMBASE_ REG Protected High Memory Base Register This register is used to setup the base address of DMA protected high memory region This register must be setup before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled When LT CMD LOCK PMRC command is invoked this register is locked treated RO When LT CMD UNLOCK PMRC command is invoked this register is unlocked treated RW This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as 0 in the Capability register The alignment of the protected high memory region base depends on the number of reserved bits N of this register Software may determine the value of N by writing all 1s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of the limit
146. 0 1 0 PCI Address Offset A8 A9h Reset Value 0000h Access RO RW Reset goes Bit Attr Value Description 15 RO Oh Reserved 14 12 RO 000b Reserved for Max Read Request Size MRRS 11 RO Ob Reserved for Enable No Snoop 10 RO Ob Reserved Reserved for Auxiliary AUX PM Enable 9 RO Ob Reserved Reserved for Phantom Functions Enable 8 RO Ob Reserved Reserved for Extended Tag Field Enable Max Payload Size MPS 000 128B max supported payload for Transaction Layer Packets TLP As a receiver the Device must handle TLPs as large as the set value as transmitter the Device must not generate TLPs exceeding the set 7 5 RW 000b value All other encodings are reserved Hardware will actually ignore this field It is writeable only to support compliance testing 4 RO Ob Reserved for Enable Relaxed Ordering Unsupported Request Reporting Enable URRE When set this bit allows signaling ERR_NONFATAL ERR_FATAL or ERR_CORR to the Root Control register when detecting an unmasked 3 RW Ob Unsupported Request UR An ERR_CORR is signaled when an unmasked Advisory Non Fatal UR is received An ERR_FATAL or ERR_NONFATAL is sent to the Root Control register when an uncorrectable non Advisory UR is received with the severity bit set in the Uncorrectable Error Severity register Fatal Error Reporting Enable FERE 2 RW Ob When set this bit enables signaling of ERR_FATAL to the Root Control register due to internally detected e
147. 0 TR1 Thermometer Read 1 Register This register generally provides the uncalibrated counter value from the thermometer circuit when the Thermometer mode is enabled See the temperature tables for the temperature calculations B D F Type 0 0 0 MCHBAR Address Offset 1006h Reset Value FFh Access RO Reset ar Bit Attr Value Description Thermometer Reading TR This field provides the current counter value The current counter value corresponds to thermal sensor temperature if TSS Thermometer mode 7 0 RO FFh Output Valid 1 This register has a straight binary encoding that will range from OOh to FFh Note When thermometer mode is disabled using TERATE register TR will read FFh Datasheet Volume 2 95 intel Processor Configuration Registers 2 8 41 TOF1 Thermometer Offset 1 Register This register is used for programming the thermometer offset B D F Type 0 0 0 MCHBAR Address Offset 1007h Reset Value 00h Access RW Reset EE Bit Attr Value Description Thermometer Offset TOF This value is used to adjust the current thermometer reading so that the TR value is not relative to a specific trip or calibration point and is positive going x for positive increases in temperature The initial Reset Value is 00h and 7 0 RW 00h A software must determine the correct temperature adjustment that corresponds to a zero reading by reading the fuses and referrin
148. 0 of the base address of TSEG DRAM memory BIOS determines the base of TSEG memory by subtracting the TSEG size 31 20 RW L 000h PCI Device 0 offset 9Eh bits 2 1 from graphics GTT memory pre allocated for graphics base PCI Device 0 offset A8h bits 31 20 This register is locked and becomes read only when CMD LOCK MEMCONFIG is received or when ME_SM_LOCK is set to 1 19 0 RO 00000h Reserved Datasheet Volume 2 59 60 intel Processor Configuration Registers TOLUD Top of Low Usable DRAM Register This 16 bit register defines the Top of Low Usable DRAM TSEG GTT Graphics memory and Memory pre allocated for graphics are within the usable DRAM space defined Programming Example C1DRB3 is set to 5 GB BIOS knows the OS requires 1 GB of PCI space BIOS also knows the range from 0_FECO_0000h to 0_FFFF_FFFFh is not usable by the system This 20 MB range at the very top of addressable memory space is lost to APIC and Intel TXT According to the above information TOLUD is originally calculated to 4 GB 1_0000_0000h The system memory requirements are 4 GB 1 GB PCI space 20 MB lost memory Due to the minimum granularity of the REMAPBASE and REMAPLIMIT registers this becomes 3 GB 64 MB 0_BCO0_0000h Since 0_BCOO_0000h PCI and other system requirements is less than 1_0000_0000h TOLUD should be programmed to BCOh These bits are Intel TXT lockable B D F Type 0 0 0 PCI
149. 00 This field selects any one of the DWORD registers within the MMIO register i h space of Device 2 if the target is MMIO Registers This field selects a GTT offset if the target is the GTT 1 0 RO Oh Reserved Data MMIO Data Register A 32 bit 1O write to this port is re directed to the MMIO register GTT location pointed to by the MMIO index register A 32 bit IO read to this port is re directed to the MMIO register address pointed to by the MMIO index register regardless of the target selection in MMIO_INDEX 1 0 8 or 16 bit 1O writes are completed by the processor and may have un intended side effects hence must not be used to access the data port 8 or 16 bit IO reads are completed normally Note that if the target field in MMIO Index selects GTT reads to MMIO data return is undefined B D F Type 0 2 0 PCI 10 Address Offset 4 7h Reset Value 0000_0000h Access RW Reset AE Bit Attr Value Description 31 0 RW 00000000 MMIO Data Window DATA h Datasheet Volume 2 Processor Configuration Registers ntel 2 15 DMI and PEG VCO VCp Remap Registers Table 2 11 MMI and PEG VCO VCp Remap Register Address Map Sheet 1 of 2 Address Register p Offset Symbol Register Name Reset Value Access 0 3h VER_REG Version 0000_0010h RO 8 Fh CAP_REG Capability 00C90080206302 RO 10 17h ECA
150. 0000000 message address If implemented the contents of this register specify the g h upper 32 bits of a 64 bit MSI write transaction If hardware does not support 64 bit messages the register is treated as read only 0 200 Datasheet Volume 2 Processor Configuration Registers intel 2 15 13 AFLOG_REG Advanced Fault Log Register This register specifies the base address of memory resident fault log region This register is treated as read only 0 for implementations not supporting advanced translation fault logging AFL field reported as 0 in the Capability register This register is sticky and can be cleared only through a powergood reset or using software clearing the RW1C fields by writing a 1 B D F Type 0 0 0 VCOPREMAP Address Offset 58 5Fh Reset Value 0000000000000000h Access RO Reset PeT Bit Attr Value Description Fault Log Address FLA This field specifies the base of size aligned fault log region in system memory Hardware may ignore and not implement bits 63 HAW where HAW 00000000 is the host address width 63 12 RO oo000h ifi i i Software specifies the base address and size of the fault log region through this register and programs it in hardware through the SFL field in the Global Command register When implemented reads of this field returns value that was last programmed to it Fault Log Size FLS This field specifies the size of t
151. 00000b PEGO VCO Read VT Completion Tracking Queue Resource Threshold PEGOVCORDCTQRTCT This field provides a 1 based minimum threshold value used to throttle PEGO VCO Read VT fetch When the number of free PEGO VT Completion Tracking Queue entries equals or falls below the value programmed in this field PEGO VCO Read VT fetch is throttled until the number of free PEGO Completion Tracking Queue entries rise above this threshold For example 00000 Throttle PEGO VCO Read VT Fetch when there is no entry left 00001 Throttle PEGO VCO Read VT Fetch when there is 1 or less entry left 00010 Throttle PEGO VCO Read VT Fetch when there is 2 or less entry left 00011 Throttle PEGO VCO Read VT Fetch when there is 3 or less entry left 00100 Throttle PEGO VCO Read VT Fetch when there is 4 or less entry left Datasheet Volume 2 Processor Configuration Registers intel 2 15 34 VTPOLICY DMA Remap Engine Policy Control This registers contains all the policy bits related to the DMA remap engine B D F Type 0 0 0 VCOPREMAP Address Offset FFC FFFh Reset Value 00000000h Access RW L 5 Reset iaai Bit Attr Value Description DMA Remap Engine Policy Lock Down DMAR_LCKDN This register bit protects all the DMA remap engine specific policy 31 RW L Ob configuration registers Once this bit is set by software all the DMA remap engine registers within the range FOOh to FFCh will be read only This bit can only b
152. 00000h RO V S RO FFC FFFh VTPOLI CY DMA Remap Engine Policy Control 00000000h ROSRW IK Datasheet Volume 2 221 intel 2 16 1 222 Processor Configuration Registers VER_REG Version Register This register reports the architecture version supported Backward compatibility for the architecture is maintained with new revision numbers allowing software to load DMA remapping drivers written for prior architecture versions B D F Type 0 0 0 DMIVC1REMAP Address Offset 0 3h Reset Value 00000010h Access RO Reset ae Bit Attr Value Description 31 8 RO 000000h Reserved Major Version number MAX tes RO th Indicates supported architecture version Minor Version number MIN 3 0 RO Oh P Indicates supported architecture minor version Datasheet Volume 2 Processor Configuration Registers 2 16 2 CAP_REG Capability Register This register reports general DMA remapping hardware capabilities B D F Type 0 0 0 DMI VCLREMAP Address Offset 8 Fh Reset Value 00C9008020E30272h Access RO Reset Paes Bit Attr Value Description 63 56 RO 00h Reserved DMA Read Draining DRD 0 On IOTLB invalidations hardware does not support draining of DMA read 55 RO lb requests 1 On IOTLB invalidations hardware supports draining of DMA read requests Refer to VTd specification Section 6 3 for description of DMA
153. 000h RW B8 BFh IRTA_REG Interrupt Remapping Table Address 009090090 0000 RW RO 100 107h IVA REG Invalidate Address 0000_0000_0000 W RO 0000h 108 10Fh IOTLB REG IOTLB Invalidate 0000_0000 0000 RW RO 0000h Datasheet Volume 2 185 intel Processor Configuration Registers Table 2 11 MMI and PEG VCO VCp Remap Register Address Map Sheet 2 of 2 Address Register Offset Symbol Register Name Reset Value Access Fault Recording 0000 0000 _ 0000 200 20Fh FRCD_REG 0000 0000 000 paWICS 0_0000_0000h F00 F03h VTCMPLRESR VT Completion Resource Dedication 0006_0000h RW L RO FO4 FO7h VTFTCHARBCTL VCO VCp VTd Fetch Arbiter Control 0000_FFFFh RW L FO8 FOBh PEGVICM PEG VT Completion Resource Dedication 2000_4000h RW L RO FFC FFFh VTPOLICY DMA Remap Engine Policy Control 0000_0000h RW L 2 15 1 VER_REG Version Register This register reports the architecture version supported Backward compatibility for the architecture is maintained with new revision numbers allowing software to load DMA remapping drivers written for prior architecture versions B D F Type 0 0 0 VCOPREMAP Address Offset 0 3h Reset Value 0000_0010h Access RO Reset PP Bit Attr Value Description 31 8 RO 000000h Reserved 7 4 RO 1h Major Version number MAX Indicates supported architecture version 3 0 RO Oh Minor Version number MIN Indicates supported architecture
154. 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 23 22 RV 0 Reserved PAM2_HI ENABLE 0CCOOOh OCFFFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OCCOOOh to OCFFFFh 21 20 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 19 18 RV 0 Reserved PAM2_LOENABLE 0C8000h OCBFFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0C8000h to OCBFFFh 17 16 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 15 14 RV 0 Reserved PAM1_HIENABLE 0C4000h 0C7FFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from 0C4000h to OC7FFFh 13 12 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All
155. 01Fh 0000h RO RW1C Bit Attr Reset Value Description 3 RW1C Ob Aux 3 Thermal Sensor Interrupt Event A3TSI E 1 Aux 3 Thermal Sensor trip event occurred based on a lower to higher temperature transition through the trip point 0 No trip for this event Software must write a 1 to clear this status bit 2 RW1C Ob Aux 2 Thermal Sensor Interrupt Event A2TSIE 1 Aux 2 Thermal Sensor trip event occurred based on a lower to higher temperature transition thru the trip point 0 No trip for this event Software must write a 1 to clear this status bit 1 RW1C Ob Aux 1 Thermal Sensor Interrupt Event A1TSIE 1 Aux1 Thermal Sensor trip event occurred based on a lower to higher temperature transition thru the trip point 0 No trip for this event Software must write a 1 to clear this status bit 0 RW1C Ob Aux 0 Thermal Sensor Interrupt Event AOTSI E 1 Aux 0 Thermal Sensor trip event occurred based on a lower to higher temperature transition through the trip point 0 No trip for this event Software must write a 1 to clear this status bit The following scenario is possible An interrupt is initiated on a rising temperature trip the appropriate DMI cycles are generated and eventually the software services the interrupt and sees a rising temperature trip as the cause in the status bits for the interrupts Assume that the software then goes and clears the local interrup
156. 1 Primary Bus Number Register This register identifies that this virtual Host PCl Express bridge is connected to PCI bus 0 B D F Type 0 1 0 PCI Address Offset 18h Reset Value 00h Access RO gt R t PEP Bit Attr ae Description Primary Bus Number BUSN Configuration software typically programs this field with the number of the 7 0 RO 00h bus on the primary side of the bridge Since device 1 is an internal device and its primary bus is always 0 these bits are read only and are hardwired to 0 Datasheet Volume 2 121 intel 2 10 10 2 10 11 122 Processor Configuration Registers SBUSN1 Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the virtual bridge that is to PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G B D F Type 0 1 0 PCI Address Offset 19h Reset Value 00h Access RW Reset gates Bit Attr Value Description Secondary Bus Number BUSN 7 0 RW 00h This field is programmed by configuration software with the bus number assigned to PCI Express G SUBUSN1 Subordinate Bus Number Register This register identifies the subordinate bus if any that resides at the level below PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G
157. 10 7 0 RV Reserved Datasheet Volume 2 353 Intel QuickPath Architecture System Address Decode Register Description intel 3 6 5 SAD_PCIEXBAR This is the Global register for PCIEXBAR address space Device 0 Function 1 Offset 50h Access as a QWord Bit Type Fae Description 63 40 RV 0 Reserved ADDRESS 39 20 RW 0 This field contains the Base address of PCIEXBAR It must be naturally aligned to size low order bits are ignored 19 4 RV 0 Reserved SIZE Size of the PCIEXBAR address space Maximum bus number 000 256 MB 001 Reserved 010 Reserved 2il RW 0 011 Reserved 100 Reserved 101 Reserved 110 64 MB 111 128 MB ENABLE 0 RW 0 Enable for PCIEXBAR address space Editing size should not be done without also enabling range 354 Datasheet Volume 2 Intel QuickPath Architecture System Address Decode Register Description 7 3 6 6 SAD _DRAM_RULE_0 SAD_DRAM_RULE_1 SAD_DRAM_RULE_2 SAD_DRAM_RULE_3 SAD_DRAM_RULE_4 SAD_DRAM_RULE_5 SAD_DRAM_RULE_6 SAD_DRAM_RULE_7 This register provides the SAD DRAM rules Address Map for package determination Device 0 Function 1 Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch Access as a Dword Reset PEA Bit Type Value Description 31 20 RV 0 Reserved LIMIT DRAM rule top limit address Must be strictly greater than previous rule 19 6 RW even if this rule is di
158. 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h AOh 24h A4h 28h A8h SID SVID 2Ch ACh 30h BOh 34h B4h 38h B8h 3Ch BCh 40h COh 44h C4h QPI_QPILCL_LO 48h C8h 4Ch CCh 50h DOh 54h D4h 58h D8h 5Ch DCh 60h EOh 64h E4h 68h E8h 6Ch ECh 70h FOh 74h F4h 78h F8h 7Ch FCh 340 Datasheet Volume 2 Intel QuickPath Architecture System Address Decode Register Description Table 3 6 Device 2 Function 1 Intel QPI Physical 0 Registers DID VID 00h QPI_0O_PH_PIS 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h HDR OCh 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h AOh 24h A4h 28h A8h SID SVID 2Ch ACh 30h BOh 34h B4h 38h B8h 3Ch BCh 40h COh 44h C4h 48h C8h 4Ch CCh 50h DOh 54h D4h 58h D8h 5Ch DCh 60h EOh 64h E4h QPI_O_PH_CPR 68h E8h QPI_O_PH_CTR 6Ch ECh 70h FOh 74h F4h 78h F8h 7Ch FCh Datasheet Volume 2 341 m t I Intel QuickPath Architecture System Address Decode Register Description 3 4 3 4 1 3 4 2 342 PCI Standard Registers These registers appear in every function for every device VI D Vendor Identification Register The VID Register contains the vendor identification number This 16 bit register combined with the Device Identification Register uniquely identifies the manufacturer of the function with
159. 159 Processor Configuration Registers intel 2 11 7 PEG_TC PCI Express Completion Timeout Register This register reports PCI Express configuration control of PCI Express Completion Timeout related parameters that are not required by the PCI Express specificaiton B D F Type 0 1 0 MMR Address Offset 204h Reset Value 0000_OCOOh Access RW Reset see Bit Attr Value Description 31 12 RW 0000_0h Reserved PCI Express Completion Timeout PEG_TC This field determines the number of milliseconds the Transaction Layer will wait to receive an expected completion To avoid hang conditions the Transaction Layer will generate a dummy completion to the requestor if it 11 12 RW 11b does not receive the completion within this time period 00 Disable 01 Reserved 10 Reserved 11 48 ms for normal operation default 2 0 0000 0 Reserved 9 0 RW 000b7 160 Datasheet Volume 2 Processor Configuration Registers 2 12 Table 2 9 2 12 1 DMI BAR Registers DMI Register Address Map Pv a Register Symbol Register Name Reset Value Access 0 3h DMIVCECH ae Channel Enhanced 00010002h RW O RO 4 7h DMI PVCCAP1 DMI Port VC Capability Register 1 0000_0000h RO RW O 8 Bh DMI PVCCAP2 DMI Port VC Capability Register 2 0000_0000h RO C Dh DMIPVCCTL DMI Port VC Control 0000h RO RW E Fh RSVD Reserved Oh RO 10 13h DMIVCORCA
160. 16 WwW 0000h entry needs to be selectively invalidated This field along with the FM field must be programmed by software for device selective invalidation requests Value returned on read of this field is undefined Domain ID DID This field indicates the ID of the domain whose context entries needs to be selectively invalidated This field must be programmed by software for both domain selective and device selective invalidation requests The Capability 15 0 RW 0000h ag register reports the domain id width supported by hardware Software must ensure that the value written to this field is within this limit Hardware may ignore and not implement bits 15 N where N is the supported domain id width reported in the capability register Datasheet Volume 2 197 intel Processor Configuration Registers 2 15 8 FSTS_ REG Fault Status Register This register indicates the primary fault logging status The VTd specification describes hardware behavior for primary fault logging Access B D F Type Address Offset Reset Value 0 0 0 VCOPREMAP 34 37h 00000000h RO RO V S RW1C S Bit Attr Reset Value Description 31 16 RO 0000h Reserved 15 8 RO V S 00h Fault Record Index FRI This field is valid only when the PPF field is set The FRI field indicates the index from base of the fault recording register to which the first pending fault was recorded when t
161. 2 3h DID2 Device Identification 0042h RO 4 5h PCICMD2 PCI Command 0000h RO RW 6 7h PCISTS2 PCI Status 0090h RO 8h RID2 Revision Identification 12h RO 9 Bh cc Class Code 030000h RO Ch CLS Cache Line Size 00h RO Dh MLT2 Master Latency Timer 00h RO Eh HDR2 Header Type 00h RO 10 17h GTTMMADR Fee Table Memory Mapped 000 0004h RW RO 18 1Fh GMADR Graphics Memory Range Address 000 000Ch RARU L 20 23h 1OBAR 1 O Base Address 0000_0001h RO RW 2C 2Dh SVID2 Subsystem Vendor Identification 0000h RW O 2E 2Fh SID2 Subsystem Identification 0000h RW O 30 33h ROMADR Video BIOS ROM Base Address 0000_0000h RO 34h CAPPOINT Capabilities Pointer 90h RO 3Dh INTRPIN Interrupt Pin Olh RO 3Eh MINGNT Minimum Grant 00h RO 3Fh MAXLAT Maximum Latency 00h RO 2 13 1 VI D2 Vendor Identification Register This register combined with the Device Identification register uniquely identifies any PCI device B D F Type 0 2 0 PCI Address Offset 0 1h Reset Value 8086h Access RO Bit Attr site Description Vendor Identification Number VID 13 0 RO evel PCI standard identification for Intel 174 Datasheet Volume 2 Processor Configuration Registers intel 2 13 2 DI D2 Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device B D F Type 0 2 0 PCI Address Offset 2 3h Reset Value 0042h Access RO 3 Reset re Bit Attr Val
162. 2Fh Reset Value 0000_0000h Access RW Reset Fas Bit Attr Value Description 0000 000 Prefetchable Memory Address Limit MLI MI TU 31 0 RW Oh This field corresponds to A 63 32 of the upper limit of the prefetchable Memory range that will be passed to PCI Express G 2 10 21 CAPPTR1 Capabilities Pointer Register The capabilities pointer provides the address offset to the location of the first entry in this device s linked list of capabilities B D F Type 0 1 0 PCI Address Offset 34h Reset Value 88h Access RO Reset er Bit Attr Value Description First Capability CAPPTR1 7 0 RO 88h The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability Datasheet Volume 2 129 intel 2 10 22 2 10 23 130 Processor Configuration Registers INTRLINE1 I nterrupt Line Register This register contains interrupt line routing information The device itself does not use this value rather it is used by device drivers and operating systems to determine priority and vector information B D F Type 0 1 0 PCI Address Offset 3Ch Reset Value 00h Access RW Reset aat Bit Attr Value Description Interrupt Connection INTCON This field is used to communicate interrupt line routing information 7 0 RW 00h BIOS Requirement POST software writes the routing information into this register as it initializes and configures the system The value in
163. 30272h Access RO Reset oe Bit Attr Value Description Isochrony Isoch 0 Indicates this DMA remapping hardware unit has no critical isochronous requesters in its scope 23 RO Ob 1 Indicates this DMA remapping hardware unit has one or more critical isochronous requesters in its scope To ensure isochronous performance software must ensure invalidation operations do not impact active DMA streams This implies that when DMA is active software perform page selective invalidations instead of coarser invalidations Zero Length Read ZLR 0 Indicates the remapping hardware unit blocks and treats as fault zero 22 RO 1b length DMA read requests to write only pages 1 Indicates the remapping hardware unit supports zero length DMA read requests to write only pages Maximum Guest Address Width MGAW This field indicates the maximum DMA virtual addressability supported by remapping hardware The Maximum Guest Address Width MGAW is computed as N 1 where N is the value reported in this field For example a hardware implementation supporting 48 bit MGAW reports a 21 16 RO 100011b value of 47 101111b in this field If the value in this field is X DMA requests to addresses above 2 x 1 1 are always blocked by hardware Guest addressability for a given DMA request is limited to the minimum of the value reported through this field and the adjusted guest address width of the corresponding page table structure
164. 4 2B7h CODTC Channel 0 DRAM Throttling Control 0000_0000h ee 600 601h C1DRBO Channel 1 DRAM Rank Boundary Address 0 0000h RW L RO 602 603h C1DRB1 Channel 1 DRAM Rank Boundary Address 1 0000h RO RW L 604 605h C1DRB2 Channel 1 DRAM Rank Boundary Address 2 0000h RW L RO 606 607h C1DRB3 Channel 1 DRAM Rank Boundary Address 3 0000h RW L RO 608 609h C1DRA01 Channel 1 DRAM Rank 0 1 Attributes 0000h RW L 60A 60Bh C1DRA23 Channel 1 DRAM Rank 2 3 Attributes 0000h RW L 64D 64Fh C1IWRDATACTRL Channel 1 Write Data Control 004111h RW 650 651h C1CYCTRKPCHG Channel 1 CYCTRK PCHG 0000h RW RO 652 655h C1CYCTRKACT Channel 1 CYCTRK ACT 0000_0000h RW RO 656 657h C1LCYCTRKWR Channel 1 CYCTRK WR 0000h RW 658 65Ah C1CYCTRKRD Channel 1 CYCTRK READ 000000h RW RO 660 663h C1CKECTRL Channel 1 CKE Control 0000_0800h RW RW L RO 69C 69Fh C1ODTCTRL Channel 1 ODT Control 0000_0000h RO RW 6A4 6ATh C1GTC Channel 1 Processor Throttling Control 0000_0000h RWA 6B4 6B7h C1DTC Channel 1 DRAM Throttling Control 0000_0000h i EK C20 C27h SSKPD Sticky Scratchpad Data 00000000F RW P 66 Datasheet Volume 2 Processor Configuration Registers Table 2 5 MCHBAR Register Address Map Sheet 2 of 2 intel Address z E Reset Offset Register Symbol Register Name Value Access 1001 1002h TSC1 Thermal Sensor Control 1 0000h RW L RO RW AF 1004 1005h TSS1 Thermal Sensor Status 1 0000
165. A resources are defined as the following Memory OBO000h OB7FFFh 1 0 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not used in decode Any I O reference that includes the I O locations listed above or their 1 RW Ob aliases will remain on the backbone even if the reference also includes I O locations not listed above The following table shows the behavior for all combinations of MDA and VGA VGAEN MDAP Description 0 0 All References to MDA and VGA space are not claimed by Device 6 0 1 Illegal combination 1 0 All VGA and MDA references are routed to PCI Express Graphics Attach device 6 1 1 All VGA references are routed to PCI Express Graphics Attach device 6 MDA references are not claimed by device 6 VGA and MDA memory cycles can only be routed across PEG1 when MAE PCICMD6 1 is set VGA and MDA I O cycles can only be routed across PEG1 if OAE PCICMD6 0 is set 0 No MDA 1 MDA Present Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 PCI Address Offset 97h Reset Value 00h Access RW BIOS Optimal Reset Value 00h x Reset doai Bit Attr Value Description PEGO MDA Present MDAPO This bit works with the VGA Enable bits in the BCTRL register of Device 1 to control the routing of processor initiated transactions targeting MDA compatible O and memory address ranges This bit should not be set if device 1 s VGA E
166. Address Offset BO B1h Reset Value 0010h Access RW L RO Reset eer Bit Attr Value Description Top of Low Usable DRAM TOLUD This register contains bits 31 20 of an address one byte above the maximum DRAM memory below 4 GB that is usable by the operating system Address bits 31 20 programmed to 01h implies a minimum memory size of 1 MB Configuration software must set this value to the smaller of the following 2 choices maximum amount memory in the system minus memory pre allocated for ME plus one byte or the minimum address allocated for PCI memory 15 4 RW L 0Oo1h Address bits 19 0 are assumed to be 0_0000h for the purposes of address comparison The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register The Top of Low Usable DRAM is the lowest address above both memory pr allocated for graphics and TSEG BIOS determines the base of memory pre allocated for graphics by subtracting the memory pre allocated for Graphics Size from TOLUD and further decrements by TSEG size to determine the base of TSEG All the bits in this register are locked in Intel TXT mode This register must be 64 MB aligned when reclaim is enabled 3 0 RO Oh Reserved Datasheet Volume 2 Processor Configuration Registers 2 7 22 PBFC Primary Buffer Flush Control Register B D F Type 0 0 0 PCI Address Offset c0 C3h Reset Va
167. B aligned interrupt remapping table 63 12 RO 00 00b Hardware ignores and not implement bits 63 HAW where HAW is the host address width Reads of this field returns value that was last programmed to it Extended Interrupt Mode Enable EI ME 0 Legacy interrupt mode is active Hardware interprets only low 8 bits of Destination ID field in the IRTEs The high 24 bits of the Destination 1D field is treated as reserved On the processor platforms hardware 11 RO Ob interprets the low 16 bits of the Destination ID field in the IRTEs and treats the high 16 bits as reserved 1 Intel 64 platform is operating in Extended Interrupt Mode Hardware interprets all 32 bits of the Destination ID field in the IRTEs Hardware reporting Extended Interrupt Mode EIM as Clear in the Capability register treats this field as reserved 10 4 RO 00h Reserved Size S This field specifies the size of the interrupt remapping table The number of 3 0 RO Oh Napa entries in the interrupt remapping table is 2 X 1 where X is the value programmed in this field Datasheet Volume 2 Processor Configuration Registers intel 2 18 27 IVA_REG Invalidate Address Register This register provides the DMA address whose corresponding OTLB entry needs to be invalidated through the corresponding OTLB I nvalidate register The register is a write only register A value returned on a read of this register is undefined B D F Type 0 2
168. BAR Address Offset 70 77h Reset Value 0000000000000000h Access RO RW Reset are Bit Attr Value Description 63 36 RO 0000000h Reserved Protected High Memory Base PHMB This register specifies the base of protected high memory region in system 35 21 RW 0000h memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width 20 0 RO 000000h Reserved Datasheet Volume 2 Processor Configuration Registers t 2 18 18 PHMLIMIT_REG Protected High Memory Limit Register This register is used to set up the limit address of DMA protected high memory region The register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled When the LT CMD LOCK PMRC command is invoked this register is locked treated as RO When the LT CMD UNLOCK PMRC command is invoked this register is unlocked treated as RW This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as 0 in the Capability register The alignment of the protected high memory region limit depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1 s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of the limit register are d
169. C1CKECTRL Channel 1 CKE Control Register This register provides Channel 1 CKE Control B D F Type 0 0 0 MCHBAR Address Offset 660 663h Reset Value 0000_0800h Access RW RW L RO 5 Reset ar Bit Attr Value Description 31 28 RO Oh Reserved start the self refresh exit sequence sd1_cr_srcstart 27 RW Ob se de toa een i This bit indicates the request to start the self refresh exit sequence CKE pulse width requirement in high phase sd1_cr_cke_pw_hl_ safe 26 24 RW 000b ape ee This field indicates CKE pulse width requirement in high phase The field corresponds to tCKE high in the DDR specification Rank 3 Population sd1_cr_rankpop3 1 Rank 3 populated 23 er 0b 0 Rank 3 not populated This register is locked by ME pre allocated Memory lock Rank 2 Population sd1_cr_rankpop2 1 Rank 2 populated 22 RIVAL 0b 0 Rank 2 not populated This register is locked by ME pre allocated Memory lock Rank 1 Population sd1_cr_rankpop1 1 Rank 1 populated 21 a Ob 0 Rank 1 not populated This register is locked by ME pre allocated Memory lock Rank 0 Population sd1_cr_rankpop0 1 Rank 0 populated 20 AWEL 0b 0 Rank 0 not populated This register is locked by ME pre allocated Memory lock CKE pulse width requirement in low phase sd1_cr_cke_pw_Ih_safe 19 17 RW 000b This field indicates CKE pulse width requirement in low phase The field corresponds to tCKE low in the DDR S
170. CH logically constitute PCI Bus 0 to configuration software The processor contains the following PCI devices within a single physical component The configuration registers for these devices are mapped as devices residing on PCI Bus 0 Device 0 Host Bridge DRAM Controller Logically this appears as a PCI device residing on PCI Bus 0 Device 0 contains the standard PCI header registers PCI Express base address register DRAM control including thermal throttling control configuration for the DMI and other processor specific registers e Device 1 Host PCl Express Bridge Logically this appears as a virtual PCI to PCI bridge residing on PCI Bus 0 and is compliant with PCI Express Base Specification Device 1 contains the standard PCI to PCI bridge registers and the standard PCI Express PCl configuration registers including the PCI Express memory address mapping e Device 2 Internal Graphics Device Logically this appears as an APCI device residing on PCI Bus 0 Physically Device 2 contains the configurations registers for 3D 2D and display functions e Device 6 Secondary Host to PCI Express Bridge Not supported on all SKUs Datasheet Volume 2 37 m t 1 Processor Configuration Registers Table 2 3 2 4 2 4 1 38 Device Number Assignment for I nternal Processor Devices Processor Function Device Number Host Bridge DRAM Controller Device 0 Host to PCl Express Bridge virtual P2P
171. CI Address Offset 2E 2Fh Reset Value 0000h Access RW O A Reset PRA Bit Attr Value Description Subsystem Identification SUBI D i _ This value is used to identify a particular subsystem This field should be 15 0 RW O 0000h programmed by BIOS during boot up Once written this register becomes Read Only This register can only be cleared by a Reset 2 13 15 ROMADR Video BIOS ROM Base Address Register The IGD does not use a separate BIOS ROM therefore this register is hardwired to Os 2 13 16 182 B D F Type 0 2 0 PCI Address Offset 30 33h Reset Value 0000 _0000h Access RO Reset ET Bit Attr Value Description 31 18 RO 0000h ROM Base Address RBA Hardwired to Os Address Mask ADMSK fe RO an Hardwired to Os to indicate 256 KB address range Reserved ain RO ni Hardwired to Os ROM BIOS Enable RBE a RO ob 0 ROM not accessible INTRPIN I nterrupt Pin Register B D F Type 0 2 0 PCI Address Offset 3Dh Reset Value Olh Access RO Reset Se Bit Attr Value Description Interrupt Pin INTPIN 7 0 RO Olh As a single function device the IGD specifies INTA as its interrupt pin 01h INTA Datasheet Volume 2 Processor Configuration Registers 2 13 17 MINGNT Minimum Grant Register B D F Type 0 2 0 PCI Address Offset 3Eh Reset Value 00h Access RO Reset k Bit Attr Value Description Minimum Gr
172. CRB that is the target element egress port of the PCH for this link entry 11 0 RO 000h Reserved 170 Datasheet Volume 2 Processor Configuration Registers intel 2 12 16 DMILE2D DMI Link Entry 2 Description Register This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element B D F Type 0 0 0 DMI BAR Address Offset 60 63h Reset Value 0000_0000h Access RO RWO Reset ici Bit Attr Value Description Target Port Number TPN This field specifies the port number associated with the element targeted by 31 24 RO 00h this link entry Egress Port The target port number is with respect to the component that contains this element as specified by the target component ID Target Component ID TCID This field identifies the physical or logical component that is targeted by this 23 16 RW O oon link entry aa l ee BIOS Requirement Must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS 15 2 RO 0000h Reserved Link Type LTYP 1 RO Ob This field indicates that the link points to memory mapped space for RCRB The link address specifies the 64 bit base address of the target RCRB Link Valid LV 0 RW O Ob 0 Link Entry is not valid and will be ignored 1 Link Entry specifies a valid link 2 12 17 DMILE2A DMI Link Entry
173. Completion Event Upper Address Register This register specifies the Invalidation Event interrupt message upper address The register is treated as reserved by implementations reporting both Queued I nvalidation QI and Extended Interrupt Mode EIM as not supported in the Extended Capability register B D F Type 0 2 0 GFXVTBAR Address Offset AC AFh Reset Value 0000_0000h Access RO Reset oer Bit Attr Value Description Message Upper Address MUA Hardware implementations supporting Queued Invalidations and Extended Interrupt Mode are required to implement this register Software requirements for programming this register are described in the VTd specification Hardware implementations not supporting Queued Invalidations and Extended Interrupt Mode may treat this field as reserved 0000_000 31 0 RO Oh Datasheet Volume 2 281 intel 2 18 26 282 Processor Configuration Registers IRTA_REG Interrupt Remapping Table Address Register This register provides the base address of Interrupt remapping table The register is treated as reserved by implementations reporting Interrupt Remapping IR as not supported in the Extended Capability register B D F Type 0 2 0 GFXVTBAR Address Offset B8 BFh Reset Value 0000000000000000h Access RO Reset RE Bit Attr Value Description Interrupt Remapping Table Address IRTA This field points to the base of 4 K
174. D 8 RO Ob Since Parity Error Response is hardwired to disabled and the IGD does not do any parity detection this bit is hardwired to 0 Fast Back to Back FB2B 7 RO 1b Hardwired to 1 The IGD accepts fast back to back when the transactions are not to the same agent 6 RO Ob User Defined Format UDF Hardwired to 0 66 MHz PCI Capable 66C 3 RO 0b Not applicable Hardwired to 0 Capability List CLI ST This bit is set to 1 to indicate that the register at 34h provides an offset into 4 RO 1b 3 ae the function s PCI Configuration Space containing a pointer to the location of the first item in the list Interrupt Status INTSTS 3 RO Ob This bit reflects the state of the interrupt in the device Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1 will the devices INTx signal be asserted 2 0 RO 000b Reserved 176 Datasheet Volume 2 Processor Configuration Registers intel 2 13 5 RI D2 Revision Identification Register This register contains the revision number for Device 2 Functions 0 and 1 This register contains the revision number of the processor The Revision ID RID is a traditional 8 bit Read Only RO register located at offset 08h in the standard PCI header of every PCI PCI Express compatible device and function B D F Type 0 2 0 PCI Address Offset 8h Reset Value 08h Access RO gt Reset EEA Bit Attr Valu
175. D IGGTT TSEG TSEG_BASE DPR Main Memory 0100_0000h 16 MB ISA Hole optional 00FO_0000h 15 MB Main Memory 0010_0000h 1 MB DOS Compatibility Memory Oh 0 MB ISA Hole 15 MB 16 MB This register moved to the processor As such the processor performs the necessary decode and routes the request appropriately Specifically if no hole is created the processor will route the request to DRAM HOM channel If a hole is created the processor will route the request on NCS NCB since the request does not target DRAM Graphics translated requests to the range will always route to DRAM Datasheet Volume 2 21 m t l Processor Configuration Registers 2 2 2 2 2 2 2 3 22 TSEG The TSEG register was moved from the GMCH to the processor The GMCH will have no direct knowledge of the TSEG size For processor initiated transactions the processor will perform necessary decode and route appropriately on HOM to DRAM or NCS NCB TSEG is below IGD stolen memory which is at the Top of Low Usable physical memory TOLUD When SMM is enabled the maximum amount of memory available to the system is equal to the amount of physical DRAM minus the value in the TSEG register BIOS will calculate and program a register so the GMCH has knowledge of where TOLUD Gfx stolen Gfx GTT stolen TSEG is located This is indicated by the TSEG_BASE register SMM mode processor accesses to enabled TSEG access the physical
176. DMIVC1REMAP 108 10Fh 0000000000000000h Access RO RW RW SC Reset Bee Bit Attr Value Description 1OTLB Actual I nvalidation Granularity 1 Al G Hardware reports the granularity at which an invalidation request was processed through this field at the time of reporting invalidation completion by clearing the IVT field The following are the encodings for the IAIG field 000 Reserved This indicates hardware detected an incorrect invalidation request and ignored the request Examples of incorrect invalidation requests include detecting an unsupported address mask value in Invalidate Address register for page selective invalidation requests 59 57 RO 000b 001 Global Invalidation performed This could be in response to a global domain selective or page selective invalidation request 010 Domain selective invalidation performed using the domain id specified by software in the DID field This could be in response to a domain selective or page selective invalidation request 011 Domain page selective invalidation performed using the address mask and hint specified by software in the Invalidate Address register and domain id specified in DID field This can be in response to a domain page selective invalidation request 100 111 Reserved 56 50 RO 00h Reserved Drain Reads DR This field is ignored by hardware if the DRD field is reported as clear in the Capability register When DRD field is
177. DR3 specification 20 17 RW Oh Same Rank Write To Read Delayed COsd_cr_wrsr_rd This field indicates the minimum allowed spacing in DRAM clocks between the WRITE and READ commands to the same rank This value corresponds to the tWTR parameter in the DDR3 specification 16 12 RW 00h Different Ranks Write To Read Delayed COsd_cr_wrdr_rd This field indicates the minimum allowed spacing in DRAM clocks between the WRITE and READ commands to different ranks This value corresponds to the tWR_RD parameter in the DDR3 specification Same Rank Read To Read Delayed COsd_cr_rdsr_rd 7 4 RW Oh This field indicates the minimum allowed spacing in DRAM clocks between two READ commands to the same rank Different Ranks Read To Read Delayed COsd_cr_rddr_rd This field indicates the minimum allowed spacing in DRAM clocks between two READ commands to different ranks This value corresponds to the tRD_RD parameter 3 0 RW Oh Datasheet Volume 2 77 Processor Configuration Registers intel 2 8 14 COCYCTRKREFR Channel O CYCTRK REFR Register This register provides Channel 0 CYCTRK Refresh control B D F Type 0 0 0 MCHBAR Address Offset 25B 25Ch Reset Value 0000h Access RO RW Reset P Bit Attr Value Description 15 13 RO 000b Reserved Same Rank Precharge All to Refresh Delay COsd_cr_pchgall_rfsh 12 9 RW Oh This field indicates the minimum allowed spacing
178. DRAM at the same address The processor will route these accesses on the QPI HOM channel When the extended SMRAM space is enabled processor accesses to the TSEG range without SMM attribute or without WB attribute are handled by the processor as invalid accesses Refer to the processor documentation for how the processor handles these accesses Non processor originated accesses are not allowed to SMM space PCI Express DMI and Internal Graphics originated cycle to enabled SMM space are handled as invalid cycle type with reads and writes to location 0 and byte enables turned off for writes Protected Memory Range PMR programmable For robust and secure launch of the MVMM the MVMM code and private data needs to be loaded to a memory region protected from bus master accesses Support for protected memory region is required for DMA remapping hardware implementations on platforms supporting Intel Trusted Execution Technology Intel TXT and is optional for non Intel TxT platforms Since the protected memory region needs to be enabled before the MVMM is launched hardware must support enabling of the protected memory region independently from enabling the DMA remapping hardware As part of the secure launch process the SINIT AC module verifies the protected memory regions are properly configured and enabled Once launched the MVMM can setup the initial DMA remapping structures in protected memory to ensure they are protected while being
179. EG1TLBDIS 1 PEG1VCO TLBs are disabled and each GPA request will result in a miss and a root walk will be requested from VTd Dispatcher e default PEG1VCO TLBs are enabled and normal hit miss lowed 10 RW L Ob 0 Normal mod flows are fol DMI VCOTLBDisable DMI VCO TLB Disable 1 DMIVCOP TLBs are disabled and each GPA request will result in a miss and a root walk will be requested from VTd Dispatcher e default DMIVCOP TLBs are enabled and normal hit miss lowed Ob 1 PEGVCO TLB 0 Normal mod flows are fol PEG TLB Disable PEGTLBDIS s are disabled and each GPA request will result in a miss and a root walk will be requested from VTd Dispatcher e default PEGVCO TLBs are enabled and normal hit miss owed Ob PEG Context Ca This is a TLBR po che TLBR PEGCTXTTLBR icy bit for PEGVCO Context Cache Ob This is a TLBR po PEG L1 TLBR PEGL1TLBR icy bit for PEGVCO L1 Cache Ob This is a TLBR po PEG L3 TLBR PEGL3TLBR icy bit for PEGVCO L3 Cache Ob This is a TLBR po DMI Context Cache TLBR DMI CTXTTLBR icy bit for DMIVCOp Context Cache Ob This is a TLBR po DMI L1 TLBR DMIL1TLBR icy bit for DMIVCOp L1 Cache Ob This is a TLBR po DMI L3 TLBR DMIL3TLBR icy bit for DMIVCOp L3 Cache Ob by BIOS only 1 48 bit AGAW 0 39 bit AGAW Maximum Guest Physical Address Mode GPAMODE Maximum Guest Physical Address Mode Thi
180. ERR Message Enable SERRE6 This bit controls Device 6 SERR messaging The root port communicates the SERR condition by sending an SERR message to the PCH This bit when set enables reporting of non fatal and fatal errors detected by the device to the Root Complex Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control Register In addition for Type 1 configuration space header devices this bit when set enables transmission by the primary interface of ERR_NONFATAL and ERR_FATAL error messages forwarded from the secondary interface This bit does not affect the transmission of forwarded ERR_COR messages 0 The SERR message is generated by the root port only under conditions enabled individually through the Device Control Register 1 The root port is enabled to generate SERR messages which will be sent to the PCH for specific root port error conditions generated detected or received on the secondary side of the virtual PCI to PCI bridge The status of SERRs generated is reported in the PCISTS6 register 290 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset 4 5h Reset Value 0000h Access RO RW i Reset ae Bit Attr Value Description Reserved 7 RO Ob Not Applicable or Implemented Hardwired to 0 Parity Error Response Enable PERRE Controls whethe
181. EVSEL Timing DEVT These bits are hard wired to 00 Writes to these bit positions have no 10 9 RO 0 effect This device does not physically connect to any PCI bus These bits are set to 00 fast decode so that optimum DEVSEL timing for physical PCI busses are not limited by this device Master Data Parity Error Detected DPD 8 RO 0 PERR signaling and messaging are not implemented by this bridge therefore this bit is hard wired to 0 Writes to this bit position have no effect Fast Back to Back FB2B This bit is hard wired to 1 Writes to this bit position have no effect This 7 RO 1 device is not physically connected to a PCI bus This bit is set to 1 indicating back to back capabilities so that the optimum setting for this PCI bus is not limited by this device 6 RO 0 Reserved 5 RO 0 66 MHz Capable Does not apply to PCI Express Must be hard wired to 0 Datasheet Volume 2 347 Intel QuickPath Architecture System Address Decode Register Description intel Device 0 Function 0 1 Offset 06h Device 2 Function 0 1 Offset 06h Bit Type agi Description Capability List CLIST This bit is hard wired to 1 to indicate to the configuration software that this device function implements a list of new capabilities A list of new capabilities is accessed using registers CAPPTR at the configuration 4 RO 0 address offset 34h from the start of the PCI configuration space header of this function
182. Error Detected NFED When set this bit indicates that non fatal error s were detected Errors are logged in this register regardless of whether error reporting is enabled or not 7 RWIG 0b in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the uncorrectable error mask register Correctable Error Detected CED When set this bit indicates that correctable error s were detected Errors 0 RW1C Ob are logged in this register regardless of whether error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the correctable error mask register 314 Datasheet Volume 2 Processor Configuration Registers 2 19 38 LCAP Link Capabilities Register This register indicates PCI Express device specific capabilities B D F Type 0 6 0 PCI Address Offset AC AFh Reset Value 03214C82h Access RO RW O Reset aai Bit Attr Value Description Port Number PN 31 24 RO 03h This field indicates the PCI Express port number for the given PCI Express link Matches the value in Element Self Description 31 24 23 22 RO 00b Reserved Link Bandwidth Notification Capability LBNC A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms This capability is required fo
183. Event Control Register This register specifies the fault event interrupt message control bits The VTd specification describes hardware handling of fault events B D F Type 0 2 0 GFXVTBAR Address Offset 38 3Bh Reset Value 80000000h Access RO RW Reset Eee Bit Attr Value Description Interrupt Mask IM 0 No masking of interrupts When an interrupt condition is detected hardware issues an interrupt message using the Fault Event Data amp 31 RW 1b Fault Event Address register values 1 This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is set Interrupt Pending IP Hardware sets the IP field whenever it detects an interrupt condition which is defined as e When primary fault logging is active an interrupt condition occurs when hardware records a fault through one of the Fault Recording registers and sets the PPF field in the Fault Status register e When advanced fault logging is active an interrupt condition occurs when hardware records a fault in the first fault record at index 0 of the current fault log and sets the APF field in the Fault Status register e Hardware detected error associated with the Invalidation Queue setting the IQE field in the Fault Status register e Hardware detected invalid Device OTLB invalidation completion setting the ICE field in the Fault Status
184. Extended Interrupt Mode Enable EIMI 0 xAPIC mode is active Hardware interprets only low 8 bits of Destination ID field in the IRTEs The high 24 bits of the Destination ID field are treated as reserved On the processor platforms hardware 11 RO Ob interprets low 16 bits of Destination ID field in the IRTEs and treats the high 16 bits as reserved 1 x2APIC mode is active Hardware interprets all 32 bits of the Destination ID field in the IRTEs Hardware reporting Extended Interrupt Mode EIM as Clear in the Capability register treats this field as reserved 10 4 RO 00h Reserved Size S 3 0 RO Oh This field specifies the size of the interrupt remapping table The number of entries in the interrupt remapping table is 2 X 1 where X is the value programmed in this field Datasheet Volume 2 247 intel Processor Configuration Registers 2 16 28 1IVA_REG Invalidate Address Register This register provides the DMA address whose corresponding OTLB entry needs to be invalidated through the corresponding I OTLB Invalidate register The register is a write only register Value returned on reads of this register is undefined B D F Type 0 0 0 DMIVCLREMAP Address Offset 100 107h Reset Value 0000000000000000h Access W RO Reset Bate Bit Attr Value Description Address ADDR Software provides the DMA address that needs to be page selectively invalidated To request a page selective inva
185. Fetch when there is no entry left 0001 Throttle DMI VCp VT Fetch when there is 1 or less entry left 0010 Throttle DMI VCp VT Fetch when there is 2 or less entry left 0011 Throttle DMI VCp VT Fetch when there is 3 or less entry left 0100 Throttle DMI VCp VT Fetch when there is 4 or less entry left 0101 1111 Reserved 7 4 RW L Oh DMI VCO Write VT Completion Tracking Queue Resource Threshold DMI VCOWRCTQRT This field provides a 1 based minimum threshold value used to throttle DMI VCO Write VT fetch When the number of free DMI VT Completion Tracking Queue entries equals or falls below the value programmed in this field DMI VCO Write VT fetch is throttled until the number of free DMI Completion Tracking Queue entries rise above this threshold For example 0000 Throttle DMI VCO Write VT Fetch when there is no entry left 0001 Throttle DMI VCO Write VT Fetch when there is 1 or less entry left 0010 Throttle DMI VCO Write VT Fetch when there is 2 or less entry left 0011 Throttle DMI VCO Write VT Fetch when there is 3 or less entry left 0100 Throttle DMI VCO Write VT Fetch when there is 4 or less entry left 0101 1111 Reserved Datasheet Volume 2 215 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset F00 FO3h Reset Value 00060000h Access RW L RO i Reset RA Bit Attr Value Description DMI VCO Read VT Completion Tracking Qu
186. Format Interrupt Status CFIS This field indicates the status of Compatibility format interrupts on Intel 64 implementations supporting interrupt remapping The value reported in this 23 RO Ob field is applicable only when interrupt remapping is enabled and extended interrupt mode x2APIC mode is disabled 0 Compatibility format interrupts are blocked 1 Compatibility format interrupts are processed as pass through bypassing interrupt remapping 22 0 RO 000000h Reserved Datasheet Volume 2 Processor Configuration Registers intel 2 16 6 RTADDR_REG Root Entry Table Address Register This register provides the base address of the root entry table B D F Type 0 0 0 DMI VC1REMAP Address Offset 20 27h Reset Value 0000000000000000h Access RW RO Reset iaai Bit Attr Value Description Root Table Address RTA This register points to base of page aligned 4 KB sized root entry table in system memory Hardware may ignore and not implement bits 63 HAW 63 12 RW 00000000 where HAW is the host address width 00000h Software specifies the base address of the root entry table through this register and programs it in hardware through the SRTP field in the Global Command register Reads of this register returns value that was last programmed to it 11 0 RO 000h Reserved Datasheet Volume 2 231 intel Processor Configuration Registers 2 16 7 CCMD_REG Context Comman
187. HBAR Address Offset 256 257h Reset Value 0000h Access RW ci Reset Se Bit Attr Value Description Activate To Write Delay COsd_cr_act_wr Oh This field indicates the minimum allowed spacing in DRAM clocks between the ACT and WRITE commands to the same rank bank This value corresponds to the tRCD_wr parameter in the DDR3 specification 15 12 RW Same Rank Write To Write Delay COsd_cr_wrsr_wr 11 8 RW Oh This field indicates the minimum allowed spacing in DRAM clocks between two WRITE commands to the same rank Different Rank Write to Write Delay COsd_cr_wrdr_wr This field indicates the minimum allowed spacing in DRAM clocks between a a On two WRITE commands to different ranks This value corresponds to the tWR_WR parameter in the DDR3 specification Read To Write Delay COsd_cr_rd_wr 3 0 RW Oh This field indicates the minimum allowed spacing in DRAM clocks between the READ and WRITE commands This value corresponds to the tRD_WR parameter 2 8 13 COCYCTRKRD Channel 0 CYCTRK READ Register B D F Type 0 0 0 MCHBAR Address Offset 258 25Ah Reset Value 000000h Access RO RW Reset er Bit Attr Value Description 23 21 RO 000b Reserved Minimum Activate To Read Delay COsd_cr_act_rd This field indicates the minimum allowed spacing in DRAM clocks between the ACT and READ commands to the same rank bank This value corresponds to tRCD_rd parameter in the D
188. I Status register CAN be set VGA Palette Snoop Enable VGASNOOP 5 RO Ob The processor does not implement this bit and it is hardwired to a 0 Writes to this bit position have no effect Memory Write and I nvalidate Enable MWIE 4 RO Ob The processor will never issue memory write and invalidate commands This bit is therefore hardwired to 0 Writes to this bit position will have no effect 3 3 RO Oh Reserved Bus Master Enable BME 2 RO 1b The processor is always enabled as a master on the backbone This bit is hardwired to a 1 Writes to this bit position have no effect Memory Access Enable MAE The processor always allows access to main memory except when such 1 RO 1b access would violate security principles Such exceptions are outside the scope of PCI control This bit is not implemented and is hardwired to 1 Writes to this bit position have no effect I O Access Enable I OAE 0 RO Ob This bit is not implemented in the processor and is hardwired to a 0 Writes to this bit position have no effect Datasheet Volume 2 47 48 Processor Configuration Registers PCI STS PCI Status Register This status register reports the occurrence of error events on Device 0 s PCI interface Since the processor Device 0 does not physically reside on PCI_A many of the bits are not implemented B D F Type 0 0 0 PCI Address Offset 6 7h Reset Value 0090h Access RW1C RO Reset ae Bit Attr Value Description 15 RW
189. IC Ob Detected Parity Error DPE This bit is set when this device receives a Poisoned TLP Signaled System Error SSE This bit is set to 1 when the processor Device 0 generates an SERR message 14 RW1C Ob over DMI for any enabled Device 0 error condition Device 0 error conditions are enabled in the PCICMD ERRCMD and DMIUEMSK registers Device 0 error flags are read reset from the PCISTS ERRSTS or DMIUEST registers Software clears this bit by writing a 1 to it Received Master Abort Status RMAS This bit is set when the processor generates a DMI request that receives an 13 RW1C Ob A A me Unsupported Request completion packet Software clears this bit by writing a 1 to it Received Target Abort Status RTAS This bit is set when the processor generates a DMI request that receives a 12 RW1C Ob t baa aa Completer Abort completion packet Software clears this bit by writing a 1 to it Signaled Target Abort Status STAS 11 RO Ob The processor will not generate a Target Abort DMI completion packet or Special Cycle This bit is not implemented in the processor and is hardwired to a 0 Writes to this bit position have no effect DEVSEL Timing DEVT These bits are hardwired to 00 Writes to these bit positions have no affect 10 9 RO 00b Device 0 does not physically connect to PCI_A These bits are set to 00 fast decode so that optimum DEVSEL timing for PCI_A is not limited by the processor Master Data P
190. IDO 38 1 or using a register DEVEN 3 0 0 RO Ob Reserved 2 17 2 GFXPLL1 GFX PLL BIOS This is the GFX PLL BIOS register See latest BIOS specification for more details B D F Type Address Offset Reset Value Access 0 0 0 MCHBAR 2C32 2C33h 0434h RO RW Bit Attr Reset Value Description 15 11 RO 00b Reserved 10 8 RW 100b Core Sampler Clock Pre Div CSPRE The CS pre divider encoding is 000 2 001 2 010 2 011 3 100 4 oe 5 10 6 11 6 Hoi ud we wo eu 7 6 RO 00b Reserved 5 4 RW 10b Core Render Sampler Clock Post Div GFXPOST Select CR CS clocks output sell sel0 CRpostdiv 0 0 div1 0 1 div2 1 0 div4 1 1 div8 RO Ob Reserved 2 0 RW 101b Core Render Clock Pre Div CRPRE The CR pre divider encoding is 000 001 2 2 2 3 4 5 6 6 toi wd wd de ue 254 Datasheet Volume 2 Processor Configuration Registers 2 18 GFXVTBAR Registers Table 2 13 GFXVTBAR Register Address Map genie pater Register Name Reset Value Access 0 3h VER_REG Version Register 00000010h RO 8 Fh CAP_REG Capability Register 00C00000202 RO 30272h ECAP_REG Extended Capability Register 00000000000 RO 10 17h 01000h 18 1Bh GCMD_REG Global Command Register 00000000h W RO RW 1C 1Fh GSTS_
191. IM LIMIT TOUUD BASE RECLAIM BASE x 64MB aligned RECLAIM BASE 64MB aligned TOLUD BASE 64MB aligned 0 HOST SYSTEM VIEW HMMIO MEMORY RECLAIM REGION PHYSICAL MEMORY DRAM CONTROLLER VIEW TOM EP UMA 1 64MB EP Stolen BASE OMB 63MB Wasted DRAM ABOVE 4GB PCI MMIO Os VISIBLE gt 4GB Os INVISIBLE RECLAIM GFX Stolen BASE GFX STOLEN 0 256 MB GFX GTT Stolen BAgE GFX GTT 0 64 MB TSEG TSEG BASE Lal TSEG 0 8 MB LOW DRAM OS VISIBLE lt 4GB 64MB aligned 1MB aligned 64MB aligned 64MB aligned for reclaim 1MB aligned 1MB aligned 1MB aligned In this case the amount of memory remapped is the range between TOLUD and 4 GB This physical memory will be mapped to the logical address range defined between the REMAPBASE and the REMAPLIMIT registers Example 5 GB Physical Memory with 1 GB allocated to Memory Mapped I O e Populated Physical Memory 5 GB e Address Space allocated to memory mapped I O 1 GB e Remapped Physical Memory 1 GB e TOM 050h 5 GB e ME stolen size 00000b 0 MB e TOUUD 1800h 6 GB 1 MB aligned e TOLUD 06000h 3 GB 64 MB aligned because remap is enabled and the remap register has 64 MB granularity e REMAPBASE 050h 5 GB e REMAPLIMIT O5Fh 6 GB 1 boundary Datasheet Volume 2 Processor Configuration Registers 2 2 3 1 3 Note
192. Identification Number DI D1 HW 3 2 RO 00b Identifier assigned to the processor device 1 virtual PCI to PCI bridge PCI Express Graphics port Device Identification Number DI D1 LB 1 0 RO 01b Identifier assigned to the processor device 1 virtual PCI to PCI bridge PCI Express Graphics port 2 10 3 PCI CMD1 PCI Command Register B D F Type 0 1 0 PCI Address Offset 4 5h Reset Value 0000h Access RO RW n Reset PPP Bit Attr Value Description 15 11 RO 00h Reserved INTA Assertion Disable INTAAD 0 This device is permitted to generate INTA interrupt messages 1 This device is prevented from generating interrupt messages Any INTA 10 RW Ob emulation interrupts already asserted must be de asserted when this bit is set Only affects interrupts generated by the device PCI INTA from a PME or Hot Plug event controlled by this command register It does not affect upstream MSIs upstream PCI INTA INTD assert and de assert messages Fast Back to Back Enable FB2B Not Applicable or Implemented Hardwired to 0 Datasheet Volume 2 117 118 Processor Configuration Registers B D F Type Address Offset Reset Value Access 0 1 0 PCI 4 5h 0000h RO RW Bit Attr Reset Value Description RW Ob SERR Message Enable SERRE1 This bit controls Device 1 SERR messaging The processor communicates the SERR condition by
193. Limit Register This register is used to set up the limit address of DMA protected low memory region below 4 GB The register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled When the LT CMD LOCK PMRC command is invoked this register is locked treated as RO When the LT CMD UNLOCK PMRC command is invoked this register is unlocked treated as RW Refer to the VTd specification for security considerations This register is always treated as RO for implementations not supporting protected low memory region PLMR field reported as 0 in the Capability register The alignment of the protected low memory region limit depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding most significant zero bit position with O in the value read back from the register Bits N 0 of the limit register are decoded by hardware as all 1s The Protected low memory base and limit registers function as follows Programming the protected low memory base and limit registers the same value in bits 31 N 1 specifies a protected low memory region of size 2 N 1 bytes Programming the protected low memory limit register with a value less than the protected low memory base register disables the protected low memory region B D F Type 0 2 0 GFXVTBAR Address Offset 6C 6Fh Reset Value
194. M Register This 16 bit register defines the Top of Upper Usable DRAM Configuration software must set this value to TOM minus all EP pre allocated memory if reclaim is disabled If reclaim is enabled this value must be set to reclaim limit 1byte 64 MB aligned since reclaim limit is 64 MB aligned Address bits 19 0 are assumed to be 000_0000h for the purposes of address comparison The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than or equal to 4 GB These bits are Intel TXT lockable B D F Type 0 0 0 PCI Address Offset A2 A3h Reset Value 0000h Access RW L Reset rr Bit Attr Value Description TOUUD TOUUD This register contains bits 35 20 of an address one byte above the maximum DRAM memory above 4 GB that is usable by the operating system Configuration software must set this value to TOM minus all EP pre allocated memory if reclaim is disabled If reclaim is enabled this value must be set to 15 0 RW L 0000h reclaim limit 64 MB aligned since reclaim limit 1byte is 64 MB aligned Address bits 19 0 are assumed to be 000_0000h for the purposes of address comparison The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than 4 GB All the bits in this register are locked in Intel TXT mode GBSM Gr
195. Management Capabilities Register ceeeee 133 2 10 27 PM_CS1 Power Management Control Status Register eeeeeeee 134 2 10 28 SS CAPID Subsystem ID and Vendor ID Capabilities Register 135 2 10 29 SS Subsystem ID and Subsystem Vendor ID Register 135 2 10 30 MSI_CAPID Message Signaled Interrupts Capability ID Register 136 Datasheet Volume 2 5 D 2 10 31 MC Message Control RegiSter ccc eee teeta eed 137 2 10 32 MA Message Address ReGISter c ce cece eect ete tenet a teenie 138 2 10 33 MD Message Data ReGiSter cece erent neta teen ed 138 2 10 34 PEG _CAPL PCI Express G Capability List Register ceceeeeeeee eee 138 2 10 35 PEG CAP PCI Express G Capabilities Register cccceceeeee cece eee eee 139 2 10 36 DCAP Device Capabilities Register cc cece eect eect eee eee ea ened 139 2 10 37 DCTL Device Control Register cece cee erent ee ee eee ene ea ened 140 2 10 38 DSTS Device Status Register cece eee teeta eae 141 2 10 39 LCAP Link Capabilities Register cece eee e nena e eee ne ead 142 2 10 40 CTL Link Control Register iene eater 144 2 10 41 LSTS Link Status Register cccceceeeee cece eee ee ee eee ence teeta enna 146 2 10 42 SLOTCAP Slot Capabilities Register c cece eee erence teeta ened 148 2 10 43 SLOTCTL Slot Control Re
196. No throttling at the outlet of the PEGO VCO Read Hit Queue PEGO VCO Write Queue Throttling PEGVCOWRHTQT 18 RW L Ob 1 Throttle the outlet PEGO VCO Write Hit Queue to fill up the queue 0 No throttling at the outlet of the PEGO VCO Write Hit Queue DMI VCp Hit Queue Throttling DMI VCPHTQT 17 RW L Ob 1 Throttle the outlet DMI VCp Hit Queue to fill up the queue 0 No throttling at the outlet of the DMI VCp Hit Queue DMI VCO Read Hit Queue Throttling DMI VCORDHTQT 16 RW L Ob 1 Throttle the outlet DMI VCO Read Hit Queue to fill up the queue 0 No throttling at the outlet of the DMI VCO Read Hit Queue DMI VCO Write Queue Throttling DMI VCOWRHTQT 15 RW L Ob 1 Throttle the outlet DMI VCO Write Hit Queue to fill up the queue 0 No throttling at the outlet of the DMI VCO Write Hit Queue PEG1 Context Cache TLBR PEG1LCTXTTLBR 14 RW L Ob This is a TLBR policy bit for PEG1VCO Context Cache PEG1 L1 TLBR PEG1L1TLBR 13 RW L Ob This is a TLBR policy bit for PEG1VCO L1 Cache Datasheet Volume 2 219 Processor Configuration Registers B D F Type Reset Value Access Address Offset 0 0 0 VCOPREMAP FFC FFFh 00000000h RW L Bit Attr Reset Value Description 12 RW L Ob PEG1 L3 TLBR This is a TLBR po PEG1L3TLBR licy bit for PEG1VCO L3 Cache 11 RW L Ob 0 Normal mod flows are fol PEG1 TLB Disable P
197. O 4 5h PCICMD6 PCI Command 0000h RO RW 6 7h PCISTS6 PCI Status 0010h RO RW1C 8h RID6 Revision Identification 08h RO 9 Bh CC6 Class Code 060400h RO Ch CL6 Cache Line Size 00h RW Eh HDR6 Header Type Olh RO 18h PBUSN6 Primary Bus Number 00h RO 19h SBUSN6 Secondary Bus Number 00h RW 1Ah SUBUSN6 Subordinate Bus Number 00h RW 1Ch OBASE6 I O Base Address FOh RW RO 1Dh IOLIMIT6 I O Limit Address 00h RO RW 1E 1Fh SSTS6 Secondary Status 0000h RW1C RO 20 21h MBASE6 Memory Base Address FFFOh RW RO 22 23h MLIMIT6 Memory Limit Address 0000h RO RW 24 25h PMBASE6 Prefetchable Memory Base Address FFF1h RW RO 26 27h PMLIMIT6 Prefetchable Memory Limit Address 0001h RO RW 28 2Bh PMBASEU6 Prefetchable Memory Base Address Upper 00000000h RW 2C 2Fh PMLIMITU6 Prefetchable Memory Limit Address Upper 00000000h RW 34h CAPPTR6 Capabilities Pointer 88h RO 3Ch INTRLINE6 Interrupt Line 00h RW 3Dh INTRPIN6 Interrupt Pin Olh RO 3E 3Fh BCTRL6 Bridge Control 0000h RO RW 40 7Eh RSVD Reserved Oh RO 7Fh CAPL Capabilities List Control 02h RW RO 80 83h PM_CAPID6 Power Management Capabilities C8039001h RO 84 87h PM_CS6 Power Management Control Status 00000008h RO RW 88 8Bh SS_CAPIDWs Subsystem ID and Vendor ID Capabilities 0000800Dh RO 8C 8Fh SS Subsystem ID and Subsystem Vendor ID 00008086h RW O 90 91h MSI_CAPID Message Signaled Interrupts Capability 1D A005h RO 92 93h MC Message Control 0000h RO RW 94 97h MA Message Address 00000000h RW RO 98 99h MD Message Da
198. O RW Reset pes Bit Attr Value Description 7 6 RO 00b Reserved SMI on Catastrophic Thermal Sensor Trip CATSMI 1 Does not mask the generation of an SMI DMI cycle on a catastrophic 5 RW 0b thermal sensor trip 0 Disable reporting of this condition using SMI messaging SMI on Hot Thermal Sensor Trip HOTSMI 1 Does not mask the generation of an SMI DMI cycle on a Hot thermal 4 RW Ob sensor trip 0 Disable reporting of this condition using SMI messaging SMI on AUX3 Thermal Sensor Trip AUX3SMI 1 Does not mask the generation of an SMI DMI cycle on an Aux3 thermal 3 RW Ob sensor trip 0 Disable reporting of this condition using SMI messaging SMI on AUX2 Thermal Sensor Trip AUX2SMI 2 0b 1 Does not mask the generation of an SMI DMI cycle on an Aux2 thermal RW sensor trip 0 Disable reporting of this condition using SMI messaging SMI on AUX1 Thermal Sensor Trip AUX1SMI 1 Does not mask the generation of an SMI DMI cycle on an Aux1 thermal 1 RW Ob sensor trip 0 Disable reporting of this condition using SMI messaging SMI on AUXO Thermal Sensor Trip AUXOSMI 1 Does not mask the generation of an SMI DMI cycle on an AuxO thermal 0 RW Ob sensor trip 0 Disable reporting of this condition using SMI messaging 104 Datasheet Volume 2 Processor Configuration Registers intel 2 8 51 TSCI CMD Thermal SCI Command Register This register selects specific errors to generate a SCI DMI cycle as enabl
199. O access is made to 4 bytes from address OFFFDh OFFFEh or OFFFFh Address bit 16 is also asserted when an I O access is made to 2 bytes from address OFFFFh A set of I O accesses are consumed by the internal graphics device if it is enabled The mechanisms for internal graphics 1O decode and the associated control is explained later The I O accesses are forwarded normally to the DMI Interface bus unless they fall within the PCI Express I O address range as defined by the mechanisms explained below I O writes are NOT posted Memory writes to PCH or PCI Express are posted The PCI Express devices have a register that can disable the routing of I O cycles to the PCI Express device The processor responds to I O cycles initiated on PCI Express or DMI with an UR status Upstream 1 0 cycles and configuration cycles should never occur If one does occur the request will route as a read to Memory address 000C_0000h so a completion is naturally generated whether the original request was a read or write The transaction will complete with an UR completion status QPI I O reads that lie within 8 byte boundaries but cross 4 byte boundaries are issued from the processor as 1 transaction The processor will break this into 2 separate transactions I O writes that lie within 8 byte boundaries but cross 4 byte boundaries will be split into 2 transactions by the processor PCI Express I O Address Mapping The processor can be programmed to direct non me
200. Ob If Power Fault detection is not supported this bit is permitted to be read only with a value of Ob Reserved for Attention Button Pressed Enable ABPE 0 RO Ob When set to 1 this bit enables software notification on an attention button pressed event Datasheet Volume 2 323 intel 2 19 43 Note 324 Processor Configuration Registers SLOTSTS Slot Status Register Hot Plug is not supported on the platform B D F Type 0 6 0 PCI Address Offset BA BBh Reset Value 0000h Access RO RW1C i Reset gees Bit Attr Value Description Reserved MBZ 15 9 RO 0000000b For future R WC S implementations software must use 0 for writes to bits Reserved for Data Link Layer State Changed DLLSC This bit is set when the value reported in the Data Link Layer Link Active field 8 RO Ob of the Link Status register is changed In response to a Data Link Layer State Changed event software must read the Data Link Layer Link Active field of the Link Status register to determine if the link is active before initiating configuration cycles to the hot plugged device Reserved for Electromechanical I nterlock Status EIS If an Electromechanical Interlock is implemented this bit indicates the 7 RO 0b current status of the Electromechanical Interlock 0 Electromechanical Interlock Disengaged 1 Electromechanical Interlock Engaged Presence Detect State PDS This bit indicates the presence of an adapte
201. P DMI VCO Resource Capability 0000_0001h RO 14 17h DMIVCORCTLO DMI VCO Resource Control 8000_00FFh RW RO 18 19h RSVD Reserved Oh RO 1A 1Bh DMIVCORSTS DMI VCO Resource Status 0002h RO 1C 1Fh DMIVC1RCAP DMI VC1 Resource Capability 00008001h RO 20 23h DMIVCIRCTL1 DMI VC1 Resource Control 0100_0000h RO RW 24 25h RSVD Reserved Oh RO 26 27h DMIVC1RSTS DMI VC1 Resource Status 0002h RO 84 87h DMILCAP DMI Link Capabilities 00012C41h RO RW O 88 89h DMILCTL DMI Link Control 0000h RO RW 8A 8Bh DMILSTS DMI Link Status 0001h RO DMI VCECH DMI Virtual Channel Enhanced Capability Register This register indicates DMI Virtual Channel capabilities B D F Type 0 0 0 DMIBAR Address Offset 0 3h Reset Value 00010002h Access RW O RO z Reset per Bit Attr Value Description Pointer to Next Capability PNC 31 20 RW O 000h This field contains the offset to the next PCI Express capability structure in the linked list of capabilities Link Declaration Capability PCI Express Virtual Channel Capability Version PCI EVCCV 19 16 RO ih Hardwired to 1 to indicate compliances with the 1 1 version of the PCI Express specification Note This version does not change for 2 0 compliance Extended Capability I D ECI D 15 0 RO 0002h Value of 0002h identifies this linked list item capability structure as being for PCI Express Virtual Channel registers Datasheet Volume 2 161 Processor Configuration Regi
202. P REG Extended Capability 0000_0000_0000 RO 1000h 18 1Bh GCMD_REG Global Command 0000_0000h w WO RO 1C 1Fh GSTS_REG Global Status 0000_0000h RO Root Entry Table Address 00000 0000 000 20 27h RTADDR_REG 00000 0000h RW RO 28 2Fh CCMD_REG Context Command 000009000099 W RW RO Fault Status RO RO V S 34 37h FSTS_REG 0000_0000h RWIC S 38 3Bh FECTL_REG Fault Event Control 8000_0000h RW RO 3C 3Fh FEDATA_REG Fault Event Data 0000_0000h RO RW 40 43h FEADDR_REG Fault Event Address 0000_0000h RW RO 44 47h FEUADDR_REG Fault Event Upper Address 0000_0000h RO 58 5Fh AFLOG REG Advanced Fault Log 0000_0000 0000 RO 0000h 64 67h PMEM_REG Protected Memory Enable 0000_0000h RW RO 68 6Bh PLMBASE_REG Protected Low Memory Base 0000_0000h RW RO 6C 6Fh PLMLIMIT_REG Protected Low Memory Limit 0000_0000h RW RO 70 77h PHMBASE_REG Protected High Memory Base 00000090 0990 RW RO 78 7Fh PHMLIMIT_REG Protected High Memory Limit 0000 0000 0000 RW RO 80 87h IQH_ REG Invalidation Queue Head 0000_0000_ 0000 RO 0000h 88 8Fh 1QT_ REG Invalidation Queue Tail 0000_0000_0000 RO 0000h 90 97h IQA_REG Invalidation Queue Address 0000 0090 0000 RW RO 9C 9Fh ICS_REG Invalidation Completion Status 0000_0000h RO RWIE A0 A3h IECTL_REG Invalidation Event Control 0000_0000h RW RO A4 A7h IEDATA_REG Invalidation Event Data 0000_0000h RW A8 ABh IEADDR_REG Invalidation Event Address 0000_0000h RW RO AC AFh IEUADDR_REG Invalidation Event Upper Address 0000_0
203. QA_REG Invalidation Queue Address Register This register is used to configure the base address and size of the invalidation queue The register is treated as reserved by implementations reporting Queued I nvalidation QI as not supported in the Extended Capability register When supported writing to this register causes the Invalidation Queue Head and Invalidation Queue Tail registers to be reset to Oh B D F Type 0 0 0 DMIVCLREMAP Address Offset 90 97h Reset Value 0000000000000000h Access RO Reset er Bit Attr Value Description Invalidation Queue Base Address IQA 00000000 This field points to the base of 4 KB aligned invalidation request queue 63 12 RO 00000h__ Hardware ignores and does not implement bits 63 HAW where HAW is the host address width Reads of this field return the value that was last programmed to it 11 3 RO 000h Reserved Queue Size QS 2 0 RO 000b This field specifies the size of the invalidation request queue A value of X in f this field indicates an invalidation request queue of 2 X 4KB pages The number of entries in the invalidation queue is 2 X 8 2 16 22 ICS_REG I nvalidation Completion Status Register This register reports completion status of invalidation wait descriptor with Interrupt Flag IF Set The register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register
204. R 0 Protected high memory region not supported 1 Protected high memory region is supported 1b Protected Low Memory Region PLMR 0 Protected low memory region not supported 1 Protected low memory region is supported 1b Required Write Buffer Flushing RWBF 0 No write buffer flushing needed to ensure changes to memory resident structures are visible to hardware 1 Software must explicitly flush the write buffers to ensure updates made to memory resident DMA remapping structures are visible to hardware Refer to the VTd specification for more details on write buffer flushing requirements Ob Advanced Fault Logging AFL 0 Advanced fault logging not supported Only primary fault logging is supported 1 Advanced fault logging is supported 2 0 RO 010b Number of domains supported ND 000b Hardware supports 4 bit domain ids with support for up to 16 domains 001b Hardware supports 6 bit domain ids with support for up to 64 domains 010b Hardware supports 8 bit domain ids with support for up to 256 domains 011b Hardware supports 10 bit domain ids with support for up to 1024 domains 100b Hardware supports 12 bit domain ids with support for up to 4K domains 100b Hardware supports 14 bit domain ids with support for up to 16K domains 110b Hardware supports 16 bit domain ids with support for up to 64K domains 111b Reserved 2 16 3 ECAP_REG Exte
205. REG Global Status Register 00000000h RO RTADDR_REG Root Entry Table Address Register 00000000000 RO RW 20 27h 00000h CCMD_REG Context Command Register 08000000000 RW RO 28 2Fh T 00000h 34 37h FSTS_REG Fault Status Register 00000000h RO RW1C S RO V S 38 3Bh FECTL_REG Fault Event Control Register 80000000h RO RW 3C 3Fh FEDATA_REG Fault Event Data Register 00000000h RO RW 40 43h FEADDR_REG Fault Event Address Register 00000000h RW RO 44 47h FEUADDR_REG Fault Event Upper Address Register 00000000h RO AFLOG_REG Advanced Fault Log Register 00000000000 RO 58 5Fh 00000h 64 67h PMEN_REG Protected Memory Enable Register 00000000h RW RO 68 6Bh PLMBASE_REG Protected Low Memory Base Register 00000000h RO RW 6C 6Fh PLMLIMIT_REG Protected Low Memory Limit Register 00000000h RW RO PHMBASE_REG Protected High Memory Base Register 00000000000 RO RW 70 77h 00000h PHMLIMIT_REG Protected High Memory Limit Register 00000000000 RO RW 78 7Fh 00000h 80 87h QH_REG Invalidation Queue Head 00000000000 RO 00000h 88 8Fh IQT_REG Invalidation Queue Tail 00000000000 RO 00000h 90 97h 1QA_REG Invalidation Queue Address 00000000000 RO 00000h 9C 9Fh ICS_REG Invalidation Completion Status 00000000h RO A0 A3h IECTL_REG Invalidation Completion Event Control 80000000h RO A4 A7h IEDATA_REG Invalidation Completion Event Data 00000000h RO AC AFh IEUADDR_REG Invalidation Completion Event Upper Address 00000000h RO IRTA_REG Interrupt Remapping Ta
206. RO i Reset ere Bit Attr Value Description Coherency C This field indicates if hardware access to the root context page table and interrupt remap structures are coherent Snooped or not 0 RO Ob 0 Indicates hardware accesses to remapping structures are noncoherent 1 Indicates hardware accesses to remapping structures are coherent Hardware access to advanced fault log and invalidation queue are always coherent 2 18 4 GCMD_REG Global Command Register This register to controls remapping hardware If multiple control fields in this register need to be modified software must serialize the modifications through multiple writes to this register B D F Type 0 2 0 GFXVTBAR Address Offset 18 1Bh Reset Value 00000000h Access W RO RW Reset eosk Bit Attr Value Description Translation Enable TE Software writes to this field to request hardware to enable disable DMA remapping hardware 0 Disable DMA remapping hardware 1 Enable DMA remapping hardware Hardware reports the status of the translation enable operation through the TES field in the Global Status register Before enabling or re enabling DMA remapping hardware through this field software must e Setup the DMA remapping structures in memory e Flush the write buffers through WBF field if write buffer flushing is reported as required e Set the root entry table pointer in hardware through SRTP field 31 RW Ob e Perform
207. Reserved 7 0 RO 00h Reserved for VC Arbitration Capability VCAC 2 20 3 PVCCTL Port VC Control Register B D F Type 0 6 0 MMR Address Offset 10C 10Dh Reset Value 0000h Access RO RW Reset PP Bit Attr Value Description 15 4 RO 000h Reserved VC Arbitration Select VCAS This field will be programmed by software to the only possible value as 3 1 Ruw 909b indicated in the VC Arbitration Capability field Since there is no other VC supported than the default this field is reserved Reserved for Load VC Arbitration Table 0 RO Ob Used for software to update the VC Arbitration Table when VC arbitration uses the VC Arbitration Table As a VC Arbitration Table is never used by this component this field will never be used Datasheet Volume 2 329 intel 2 20 4 330 Processor Configuration Registers VCORCAP VCO Resource Capability Register B D F Type Reset Value Access Address Offset 0 6 0 MMR 110 113h 0000_0001h RO Bit Attr Reset Value Description 31 24 RO 00h Reserved for Port Arbitration Table Offset 23 RO Ob Reserved 22 16 RO 00h Reserved for Maximum Time Slots 15 RO Ob Reject Snoop Transactions RSNPT 0 Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC 1 Any transaction for which the No Snoop attribute is applicable but is n
208. Reset aii Bit Attr Value Description Invalidate Context Cache ICC Software requests invalidation of context cache by setting this field Software must also set the requested invalidation granularity by programming the CIRG field Software must read back and check the ICC field is Clear to confirm the invalidation is complete Software must not update this register when this field is Set Hardware clears the ICC field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the CAIG field Software must submit a context cache invalidation request through this field 63 RW Ob aka only when there are no invalidation requests pending at this remapping hardware unit Refer to the VTd specification for software programming requirements Since information from the context cache may be used by hardware to tag IOTLB entries software must perform domain selective or global invalidation of OTLB after the context cache invalidation has completed Hardware implementations reporting a write buffer flushing requirement RWBF 1 in the Capability register must implicitly perform a write buffer flush before invalidating the context cache Refer to the VTd specification for write buffer flushing requirements 266 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 2 0 GFXVTBAR Address Offset 28 2Fh Rese
209. Resource Available DMI VTCTRA Number of entries available in DMI VT Completion Tracking Queue 1 based The values programmed in the fields below must not be greater than the value advertised in this field 15 12 RW L Oh DMI VC1 VT Completion Tracking Queue Resource Threshold DMI VC1CTQRT This field provides a 1 based minimum threshold value used to throttle DMI VC1 VT fetch When the number of free DMI VT Completion Tracking Queue entries equals or falls below the value programmed in this field DMI VC1 VT fetch is throttled until the number of free DMI Completion Tracking Queue entries rise above this threshold For example 0000 Throttle DMI VC1 VT Fetch when there is no entry left 0001 Throttle DMI VC1 VT Fetch when there is 1 or less entry left 0010 Throttle DMI VC1 VT Fetch when there is 2 or less entry left 0011 Throttle DMI VC1 VT Fetch when there is 3 or less entry left 0100 Throttle DMI VC1 VT Fetch when there is 4 or less entry left 0101 1111 Reserved Oh DMI VCp VT Completion Tracking Queue Resource Threshold DMI VCPCTQRT This field provides a 1 based minimum threshold value used to throttle DMI VCp VT fetch When the number of free DMI VT Completion Tracking Queue entries equals or falls below the value programmed in this field DMI VCp VT fetch is throttled until the number of free DMI Completion Tracking Queue entries rise above this threshold For example 0000 Throttle DMI VCp VT
210. SE 0 256 MB Memory DMI 1MB aligned GFX GTT j t t j t p GFX GTT Stolen BASE 0 2 MB 145 aligned Independently Programmable TSEG TSEG Non Overlapping Windows TSEG BASE 0 8 MB 1MB aligned Main os Memory VISIBLE Address lt 4GB Range 1MB Legacy Address Range o 0 18 Datasheet Volume 2 Processor Configuration Registers 2 2 1 Legacy Address Range This area is divided into the following address regions e 0 640 KB DOS Area e 640 768 KB Legacy Video Buffer Area e 768 896 KB in 16 KB sections total of 8 sections Expansion Area e 896 960 KB in 16 KB sections total of 4 sections Extended System BIOS Area e 960 KB 1 MB Memory System BIOS Area Figure 2 2 DOS Legacy Address Range ntel 000F_FFFFh 000F_0000h 000E_FFFFh 000E_0000h 000D_FFFFh 000C_0000h 000B_FFFFh 000A_0000h 0009_FFFFh 0000_0000h System BIOS Upper 64 KB Extended System BIOS Lower 64 KB 16 KB x 4 Expansion Area 128 KB 16 KB x 8 Legacy Video Area SMM Memory 128 KB DOS Area 960 KB 896 KB 768 KB 640 KB 2 2 1 1 DOS Range 0000_0000h 0009_ FFFFh The DOS area is 640 KB 0000_0000h 0009_FFFFh in size and is always mapped to the main memory controlled by the processor 2 2 1 2 Legacy Video Area 000A_0000h 000B_FFFFh The legacy 128 KB VGA memory range frame buffer 000A_0000h 000B_FFFFh can be mapped to IGD Dev
211. STS1 Secondary Status 0000h RWI1C RO 20 21h MBASE1 Memory Base Address FFFOh RW RO 22 23h MLIMIT1 Memory Limit Address 0000h RW RO 24 25h PMBASE1 Prefetchable Memory Base Address FFF1h RW RO 26 27h PMLIMIT1 Prefetchable Memory Limit Address 0001h RW RO 28 2Bh PMBASEU1 Prefetchable Memory Base Address Upper 0000_0000h RW 2C 2Fh PMLIMITU1 Prefetchable Memory Limit Address Upper 0000_0000h RW 34h CAPPTR1 Capabilities Pointer 88h RO 3Ch INTRLINE1 Interrupt Line 00h RW 3Dh INTRPIN1 Interrupt Pin Olh RO 3E 3Fh BCTRL1 Bridge Control 0000h RO RW 40 7Eh RSVD Reserved Oh RO 7Fh CAPL Capabilities List Control 02h RO RW 80 83h PM_CAPID1 Power Management Capabilities C8039001h RO 84 87h PM_CS1 Power Management Control Status 0000_0008h RO RWS 88 8Bh SS_CAPID Subsystem ID and Vendor ID Capabilities 0000800Dh RO 8C 8Fh SS Subsystem ID and Subsystem Vendor ID 00008086h RW O 90 91h MSI_CAPID Message Signaled Interrupts Capability ID A005h RO 92 93h MC Message Control 0000h RO RW 94 97h MA Message Address 0000_0000h RW RO 98 99h MD Message Data 0000h RW AO Alh PEG_CAPL PCI Express G Capability List 0010h RO A2 A3h PEG_CAP PCI Express G Capabilities 0142h RO RW O A4 A7h DCAP Device Capabilities 00008000h RO 115 intel Table 2 7 116 PCI Express Device 1 Register Address Map Processor Configuration Registers oe pie Register Name FE Access A8 A9h DCTL Device Control 0000h RO
212. SVI D 15 0 RW O 8086h This field identifies the manufacturer of the subsystem and is the same as the vendor ID which is assigned by the PCI Special Interest Group Datasheet Volume 2 135 intel MSI _ CAPI D Message Signaled I nterrupts Capability I D 2 10 30 136 Register Processor Configuration Registers When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item a message to a predefined memory address The reporting of the existence of this capability can be disabled by setting MSI CH CAPL O 7Fh In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express capability B D F Type 0 1 0 PCI Address Offset 90 91h Reset Value A005h Access RO r Reset PNE Bit Attr Value Description Pointer to Next Capability PNC 15 8 RO AOh This contains a pointer to the next item in the capabilities list which is the PCI Express capability Capability ID CID 7 0 RO 05h Value of 05h identifies this linked list item capability structure as being for MSI registers Datasheet Volume 2 Processor Configuration Registers intel 2 10 31 MC Message Control Register System software can modify bits in this register but the device is prohibited from doing so If the device writes the same message multiple times only one of those messages i
213. Status LABWS This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width without the port transitioning through DL_Down status for reasons other than to attempt to correct unreliable link operation This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change This bit must be set when the upstream component receives eight consecutive TS1 or TS2 ordered sets with the Autonomous Change bit set 14 RW1C Ob Link Bandwidth Management Status LBWMS This bit is set to 1b by hardware to indicate that either of the following has occurred without the port transitioning through DL_Down status A link retraining initiated by a write of 1b to the Retrain Link bit has completed Note This bit is Set following any write of 1b to the Retrain Link bit including when the Link is in the process of retraining for some other reason e Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation either through an LTSSM time out or a higher level process This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was not indicated as an autonomous change 13 RO Ob Data Link Layer Link Active Optional DLLLA This bit indicates the status of the Data Link Control and Management State Machine
214. TA_REG Fault Event Data Register 00000000h RO RW 40 43h FEADDR_REG Fault Event Address Register 00000000h RW RO 44 47h FEUADDR_REG Fault Event Upper Address Register 00000000h RO 58 5Fh AFLOG_REG Advanced Fault Log Register 0000000000000000h RO 64 67h PMEN_REG Protected Memory Enable Register 00000000h RW RO 68 6Bh PLMBASE_REG Protected Low Memory Base Register 00000000h RW RO 6C 6Fh PLMLIMIT_REG Protected Low Memory Limit Register 00000000h RW RO 70 77h PHMBASE_REG cai High Memory Base 0000000000000000h RW RO egister 78 7Fh PHMLIMIT_REG Protected High Memory Limit 0000000000000000h RW RO Register 80 87h IQH_REG Invalidation Queue Head Register 0000000000000000h RO 88 8Fh IQT_REG Invalidation Queue Tail Register 0000000000000000h RO 90 97h IQA_REG Invalidation Queue Address Register 0000000000000000h RO 9C 9Fh ICS_REG Inva idation Completion Status 00000000h RO Register A0 A3h IECTL_REG Invalidation Event Control Register 00000000h RO A4 A7h IEDATA_REG Invalidation Event Data Register 00000000h RO A8 ABh IEADDR_REG Invalidation Event Address Register 00000000h RO IEUADDR_REG Invalidation Event Upper Address AC AFh Register 00000000h RO B8 BFh IRTA_REG Interrupt Remapping Table Address 0000000000000000h RO Register 100 107h IVA_REG Invalidate Address Register 0000000000000000h W RO 108 10Fh OTLB_REG OTLB Invalidate Register 0000000000000000h RO RW RW 200 20Fh FRCD_REG Fault Recording Registers 00000000000000000 RWIC S 0000000000
215. The PCI Express Link associated with this port is connected to an 8 RW O 1b integrated component or is disabled 1 The PCI Express Link associated with this port is connected to a slot BIOS Requirement This field must be initialized appropriately if a slot connection is not implemented 7 4 RO Ah Device Port Type DPT Hardwired to 4h to indicate root port of PCI Express Root Complex PCI Express Capability Version PCI ECV 3 0 RO 2h Hardwired to 2h to indicate compliance to the PCI Express Capabilities Register Expansion ECN 2 19 35 DCAP Device Capabilities Register This register indicates PCI Express device capabilities B D F Type 0 6 0 PCI Address Offset A4 A7h Reset Value 00008000h Access RO Reset MEF Bit Attr Value Description Reserved 31 16 RO 0000h Not Applicable or Implemented Hardwired to 0 Role Based Error Reporting RBER 15 RO 1b This bit indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1 1 spec Reserved 14 6 RO ooon Not Applicable or Implemented Hardwired to 0 5 RO Ob Extended Tag Field Supported ETFS Hardwired to indicate support for 5 bit Tags as a Requestor 4 3 RO 00b Phantom Functions Supported PFS Not Applicable or Implemented Hardwired to 0 Max Payload Size MPS 2 0 RO 000b Hardwired to indicate 128B max supported payload for Transaction Layer Packets TLP 312
216. Upper Register 303 2 19 21 CAPPTR6 Capabilities Pointer Register ccccccceeee eee ee eee e eerste eee ea eaed 303 2 19 22 INTRLINE6 Interrupt Line Register cece eee eee nent terete eee ea en es 304 2 19 23 INTRPIN6 Interrupt Pin Register cece cece eee eee e tetra eee eee ea ene 304 2 19 24 BCTRL6 Bridge Control RegiSter ccc ee ce eect e eee eee eee eee ea eae 304 2 19 25 PM_CAPID6 Power Management Capabilities Register eeeeeee 306 2 19 26 PM _CS6 Power Management Control Status Register 307 2 19 27 SS CAPID Subsystem ID and Vendor ID Capabilities Register 308 2 19 28 SS Subsystem ID and Subsystem Vendor ID Register 308 2 19 29 MSI_CAPID Message Signaled Interrupts Capability ID Register 309 2 19 30 MC Message Control Register cece ee cece eee te ene te eee ee ene ea en ees 310 2 19 31 MA Message Address Register cccceccee reece eee tenet ene e ae te teeta ene ea ents 311 2 19 32 MD Message Data Register ccc ceceee teeter nent eee e nent ea nrnna nnna 311 2 19 33 PEG_CAPL PCI Express G Capability List Register neccen 311 2 19 34 PEG _CAP PCI Express G Capabilities Register cer 312 2 19 35 DCAP Device Capabilities Register ccc cecceeeee eee e ee ee eee eee ena eae ee ae 312 2 19 36 DCTL Device Control Register ccc eee eee eee tenet een en anata ees 313
217. Volume 2 Processor Configuration Registers 2 12 4 DMI PVCCTL DMI Port VC Control Register B D F Type 0 0 0 DMIBAR Address Offset C Dh Reset Value 0000h Access RO RW g Reset P Bit Attr Value Description 15 4 RO 000h Reserved VC Arbitration Select VCAS This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field The value 000b when written to this field will indicate the VC arbitration 3 1 RW 000b scheme is hardware fixed in the root complex This field cannot be modified when more than one VC in the LPVC group is enabled 000 Hardware fixed arbitration scheme such as Round Robin Others Reserved See the PCI express specification for more details 0 RO Ob Reserved for Load VC Arbitration Table 2 12 5 DMI VCORCAP DMI VCO Resource Capability Register B D F Type 0 0 0 DMIBAR Address Offset 10 13h Reset Value 0000_0001h Access RO 5 Reset ar Bit Attr Value Description 31 24 RO 00h Reserved for Port Arbitration Table Offset 23 RO Ob Reserved 22 16 RO 00h Reserved for Maximum Time Slots Reject Snoop Transactions REJ SNPT 0 Transactions with or without the No Snoop bit set within the TLP header 15 RO Ob are allowed on this VC 1 Any transaction for which the No Snoop attribute is applicable but is not set within the TLP Header will be rejected as an Unsupported Request
218. a register MMI O_Index MMIO_INDEX is a 32 bit register An 1O write to this port loads the offset of the MMIO register or offset into the GTT that needs to be accessed An IO Read returns the current value of this register See OBAR rules for detailed information MMI O_ Data MMIO_DATA is a 32 bit register An 1O write to this port is re directed to the MMIO register pointed to by the MMIO index register An 1O read to this port is re directed to the MMIO register pointed to by the MMIO index register See OBAR rules for detailed information The result of accesses through OBAR can be e Accesses directed to the GTT table that is route to DRAM e Accesses to internal graphics registers with the processor that is route to internal configuration bus e Accesses to internal graphics display registers now located within the PCH that is route to DMI GTT table space writes GTTADR are supported through this mapping mechanism This mechanism to access internal graphics MMIO registers must not be used to access VGA IO registers which are mapped through the MMIO space VGA registers must be accessed directly through the dedicated VGA I O ports Datasheet Volume 2 Processor Configuration Registers 7 t 2 2 7 Table 2 2 2 2 8 2 2 9 System Management Mode SMM The processor handles all SMM mode transaction routing The processor has no direct knowledge of SMM mode The processor will never allow I O device
219. able Entry Size 9 8 RO 00b Reserved Reserved for Reference Clock 7 RO Ob Reserved Low Priority Extended VC Count LPEVCC This field indicates the number of extended Virtual Channels in addition to 6 4 RO 000b the default VC belonging to the low priority VC LPVC group that has the lowest priority with respect to other VC resources in a strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration 3 RO Ob Reserved Extended VC Count EVCC 2 0 RO 000b This field indicates the number of extended Virtual Channels in addition to the default VC supported by the device 156 Datasheet Volume 2 Processor Configuration Registers intel 2 11 2 PVCCAP2 Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 1 0 MMR Address Offset 108 10Bh Reset Value 0000_0000h Access RO Reset igi Bit Attr Value Description VC Arbitration Table Offset VCATO This field indicates the location of the VC Arbitration Table This field contains 31 24 RO 00h the zero based offset of the table in DQWORDS 16 bytes from the base address of the Virtual Channel Capability Structure A value of 0 indicates that the table is not present due to fixed VC priority 23 8 RO 0000h Reserved 7 0 RO 00h Reserved for VC Arbitration Capability VCAC 2 11 3 PVCCTL Port
220. address range from the top of low usable DRAM TOLUD to 4 GB is normally mapped to the DMI Interface Device 0 exceptions are 1 Addresses decoded to the egress port registers PXPEPBAR 2 Addresses decoded to the memory mapped range for internal processor registers GMCHBAR 3 Addresses decoded to the registers associated with the processor PCH Serial Interconnect DMI register memory range DMIBAR For each PCI Express port there are two exceptions to this rule 1 Addresses decoded to the PCI Express Memory Window defined by the MBASE1 MLIMIT1 registers are mapped to PCI Express 2 Addresses decoded to the PCI Express prefetchable Memory Window defined by the PMBASE1 PMLIMIT1 registers are mapped to PCI Express In integrated graphics configurations there are exceptions to this rule 1 Addresses decode to the internal graphics translation window GMADR 2 Addresses decode to the Internal graphics translation table or IGD registers GTTMMADR Ina VT enable configuration there are exceptions to this rule 1 Addresses decoded to the memory mapped window to DMI VC1 VT remap engine registers DMIVC1BAR 2 Addresses decoded to the memory mapped window to Graphics VT remap engine registers GFXVTBAR 3 Addresses decoded to the memory mapped window to PEG DMI ME VCO VT remap engine registers VTDPVCOBAR 4 TCm accesses to ME stolen memory from PCH do not go through VT remap engines Some of the MMIO Bars may be m
221. ae 343 3 4 4 CCR Class Code Register 0 ccececc cece eee eee eee enter eee e eee ETEA 344 3 4 5 HDR Header Type Register eccecc cece eect eee ee eee teeta e te teeta eee ea en ees 345 3 4 6 SID SVID Subsystem I dentity Subsystem Vendor Identification Register 345 3 4 7 PCICMD Commaand R GiIStel 0ccceee cece eee eee ee eee neta teeta e eens 346 3 4 8 PCISTS PCl Status Register wctiisccecncades ioe eerid seeded odes tert eeridanedde deeds 347 3 5 Generic Non core Registers ccc ete e tenet entered 349 3 5 1 MAX RTIDS tid tiswit iia tiataca reine ded E EE EEA A aren EEEN 349 3 6 SAD System Address Decoder ReGiSterS c cece eeee treet eee ee ee et eet eee n tate tana ees 349 3 6 1 SAD PAMOU2 3 iranse sicnscneats A AE AT EA 349 3 6 2 SAD PAM45 Oricine rana a a A A aa a 351 3 6 3 SAD HEN iicstutuinsactetactenenic tana A E E OEE 352 3 6 4 SAD SMBAM b saccseievsaets i uaua a VEEE A A EEE 353 3 6 5 SAD PCEIEXBAR iccirco sonnin onneni o AAT ATENEA E a 354 3 6 6 SAD_DRAM_RULE_0 SAD_DRAM_RULE_1 SAD_DRAM_RULE_2 SAD_DRAM_RULE_3 SAD_DRAM_RULE_4 SAD_DRAM_RULE_5 SAD_DRAM_RULE_6 SAD_DRAM_RULE_7 cccccceccsessssseeesseeeeeeeceeeeeees 355 3 7 Intel QPI Link Registers sacks cs 28 iadaisvancaadngardesnendebenddaactncneiaaencaniadiadaataahoorands 356 3 7 1 QPI _QPILCL_LO QPI_QPILCL_L ssssssssssusiniiiiiniississrrenterttrukirirrrrrrrrrrssee 356 3 8 Intel QPI Physical Layer Reg SterS icsisc cccsans nccc
222. age frame 37 34 RO Oh 1 30 bit offset to page frame 2 39 bit offset to page frame 3 48 bit offset to page frame Hardware implementations supporting a specific super page size must support all smaller superpage sizes That is the only valid values for this field are 0001b 0011b 0111b 1111b Fault recording Register Offset FRO This field specifies the location to the first fault recording register relative to 33 24 RO 020h the register base address of this DMA remapping hardware unit If the register base address is X and the value reported in this field is Y the address for the first fault recording register is calculated as X 16 Y Datasheet Volume 2 223 Processor Configuration Registers B D F Type 0 0 0 DMIVC1REMAP Address Offset 8 Fh Reset Value 00C9008020E30272h Access RO Reset es Bit Attr Value Description Isochrony I soch 0 Indicates this DMA remapping hardware unit has no critical isochronous requesters in its scope 1 Indicates this DMA remapping hardware unit has one or more critical 23 RO 1b isochronous requesters in its scope To ensure isochronous performance software must ensure invalidation operations do not impact active DMA streams from such requesters This implies that when DMA is active software perform page selective invalidations instead of coarser invalidations Zero Length Read ZLR 0 Indicates the remapping hardware unit blocks and treats a
223. agement configuration software must only permit reference clock removal if all functions of the multifunction device indicate a 1b in this bit 17 15 010b L1 Exit Latency L1LELAT This field indicates the length of time this Port requires to complete the transition from L1 to LO The value 010 b indicates the range of 2 us to less than 4 us BIOS Requirement If this field is required to be any value other than the default BIOS must initialize it accordingly Both bytes of this register that contain a portion of this field must be written simultaneously in order to prevent an intermediate and undesired value from ever existing 142 Datasheet Volume 2 Processor Configuration Registers B D F Type Address Offset Reset Value Access 0 1 0 PCI AC AFh 02214D02h RO RW O Bit Attr Reset Value Description 14 12 RO 100b LOs Exit Latency LOSELAT This field indicates the length of time this Port requires to complete the transition from LOs to LO 000 Less than 64 ns 001 64ns to less than 128ns 010 128ns to less than 256 ns 011 256ns to less than 512ns 100 512ns to less than lus 101 1 us to less than 2 us 110 2us 4us 111 More than 4 us The actual value of this field depends on the common Clock Configuration bit LCTL 6 and the Common and Non Common clock LOs Exit Latency values in PEGLOSLAT Offset 22Ch 11 10 RW O 11b Active State Li
224. al Channel must be cleared in both Components on a Link 3 Software must ensure that no traffic is using a Virtual Channel at the time it is disabled 4 Software must fully disable a Virtual Channel in both Components on a Link before re enabling the Virtual Channel 30 27 RO Oh Reserved Virtual Channel ID VCI D 26 24 RW 010b Assigns a VC ID to the VC resource This field can not be modified when the VC is already enabled 23 8 RO 0000h Reserved Traffic Class Virtual Channel Map TCVCM This field indicates the TCs that are mapped to the VC resource This field is valid for all Functions Bit locations within this field correspond to TC values For example when bit 7 is Set in this field TC7 is mapped to this VC resource When more than 1 bit in this field is set it indicates that multiple TCs are mapped to the VC RW 00h resource To remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link BIOS Requirement Program this field including bit 0 with the value 01000100b which maps TC2 and TC6 to VCp 0 RO Ob Traffic Class 0 Virtual Channel Map TCOVCM Traffic Class 0 is always routed to VCO 168 Datasheet Volume 2 Processor Configuration Registers intel 2 12 12 DMIVCPRSTS DMI VCp Resource Status Register This register reports the Virtual Channel specific st
225. alue Description Channel 0 DRAM Rank 3 Attributes CODRA3 This register defines DRAM page size number of banks for rank 3 for given 15 8 RW L 00h channel This register is locked by Memory pre allocated for ME lock Channel 0 DRAM Rank 2 Attributes CODRA2 7 0 RW L 00h This register defines DRAM page size number of banks for rank2 for given channel This register is locked by Memory Pre allocated for graphics lock 2 8 9 COWRDATACTRL Channel 0 Write Data Control Register Channel 0 WR Data Control Registers B D F Type 0 0 0 MCHBAR Address Offset 24D 24Fh Reset Value 004111h Access RW BIOS Optimal Reset Value 00h n Reset jii Bit Attr Value Description 23 16 RW 00h Reserved 15 RW Ob Reserved 14 0 RW 4110h Reserved 74 Datasheet Volume 2 Processor Configuration Registers intel 2 8 10 COCYCTRKPCHG Channel O CYCTRK PCHG Register B D F Type 0 0 0 MCHBAR Address Offset 250 251h Reset Value 0000h Access RO RW g Reset ai Bit Attr Value Description 15 11 RO 00h Reserved Write To Precharge Delay COsd_cr_wr_pchg 00h This field indicates the minimum allowed spacing in DRAM clocks between the WRITE and PRE commands to the same rank bank This value corresponds to the tWR parameter in the DDR3 Specification 10 6 RW Read To Precharge Delay COsd_cr_rd_pchg 5 2 RW Oh This field indicates the minimum allowed spacing
226. an L1 21 RW 0 power state slave and should respond to L1 transitions with an ACK or NACK If the link power state of L1 is enabled then there is one master and one slave per link The master may only issue single L1 requests while the slave can only issue single L1_Ack or L1_NAck responses for the corresponding request L1_ ENABLE This bit enables L1 mode at the transmitter This bit should be ANDed 20 RW 0 with the receive L1 capability bit received during parameter exchange to determine if a transmitter is allowed to enter into L1 This is NOT a bit that determines the capability of a device 19 RV 0 Reserved LOS_ ENABLE This bit enables LOs mode at the transmitter This bit should be ANDed 18 RW 0 with the receive LOs capability bit received during parameter exchange to determine if a transmitter is allowed to enter into LOs This is NOT a bit that determines the capability of a device 17 0 RW 0 Intel Reserved 356 Datasheet Volume 2 Intel QuickPath Architecture System Address Decode Register Description 3 8 Intel QPI Physical Layer Registers 3 8 1 QPI_O_PH_CPR QPI_1 _PH_CPR This is the Intel QPI Physical Layer Capability Register Device 2 Function 1 Offset 68h Access as a Dword Reset ran Bit Type Value Description 31 30 RV Reserved 29 RO LFSR_POLYNOMIAL Agent s ITU polynomial capability for loopback NUMBER_OF_TX_LANES Number of Tx lanes with which an implementation can o
227. and Legacy interrupt mode is active 0 Compatibility format interrupts are blocked 1 Compatibility format interrupts are processed as pass through bypassing interrupt remapping RO 000000h Reserved Datasheet Volume 2 265 Processor Configuration Registers intel 2 18 6 RTADDR_REG Root Entry Table Address Register This register provides the base address of root entry table B D F Type 0 2 0 GFXVTBAR Address Offset 20 27h Reset Value 0000000000000000h Access RO RW Reset inii Bit Attr Value Description 63 36 RO 0000000h Reserved Root table address RTA This register points to base of page aligned 4 KB sized root entry table in system memory Hardware may ignore and not implement bits 63 HAW where HAW is the host address width Software specifies the base address of the root entry table through this register and programs it in hardware through the SRTP field in the Global Command register Reads of this register return the value that was last programmed to it 35 12 RW 000000h 11 0 RO 000h Reserved 2 18 7 CCMD_REG Context Command Register This register manages context cache The act of writing the uppermost byte of the CCMD_REG with the ICC field set causes the hardware to perform the context cache invalidation B D F Type 0 2 0 GFXVTBAR Address Offset 28 2Fh Reset Value 0800000000000000h Access RW RO
228. and hidden 1 Bus 0 Device 1 Function 0 is enabled and visible Host Bridge DOEN 0 RO 1b Bus 0 Device 0 Function 0 may not be disabled and is therefore hardwired tol Datasheet Volume 2 Processor Configuration Registers intel 2 7 15 DMI BAR Root Complex Register Range Base Address Register This is the base address for the Root Complex configuration space This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the processor There is no physical memory within this 4 KB window that can be addressed The 4 KB reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset the Root Complex configuration space is disabled and must be enabled by writing a 1 to DMIBAREN Device 0 offset 68h bit 0 All the bits in this register are locked in Intel TXT mode B D F Type 0 0 0 PC1OO00_O Address Offset 68 6Fh Reset Value 0000_0000_0000_0000h Access RW L RO Reset ee Bit Attr Value Description 63 36 RO 0000000h Reserved DMI BAR_rsv DMI Base Address DMI BAR This field corresponds to bits 35 12 of the base address DMI configuration space BIOS will program this register resulting in a base address for a 4 KB 35 12 RW L 000000h block of contiguous memory address space This register ensures that a naturally aligned 4 KB space is allocated within the first 64 GB of addressable memory spac
229. ant Value MGV 7 0 RO Oh 9 The IGD does not burst as a PCI compliant master 2 13 18 MAXLAT Maximum Latency Register B D F Type 0 2 0 PCI Address Offset 3Fh Reset Value 00h Access RO s Reset isit Bit Attr Value Description Maximum Latency Value MLV 7 0 RO 00h The IGD has no specific requirements for how often it needs to access the PCI bus 2 14 Device 2 I O Registers Address Register s Offset Symbol Register Name Reset Value Access 0 3h Index MMIO Address Register 0000_0000h RW 4 7h Data MMIO Data Register 0000_0000h RW Datasheet Volume 2 183 m t Processor Configuration Registers 2 14 1 2 14 2 184 I ndex MMI O Address Register A 32 bit I O write to this port loads the offset of the MMIO register or offset into the GTT that needs to be accessed An I O Read returns the current value of this register An 8 16 bit I O write to this register is completed by the processor but does not update this register This mechanism to access internal graphics MMIO registers must not be used to access VGA IO registers which are mapped through the MMIO space VGA registers must be accessed directly through the dedicated VGA 1 0 ports B D F Type 0 2 0 PCI 10 Address Offset 0 3h Reset Value 0000_0000h Access RW A Reset jabi Bit Attr Value Description Register GTT Offset REGGTTO 31 2 RW 000000
230. ant zero bit position below host address width HAW in the value read back from the register Bits N 0 of the limit register is decoded by hardware as all 1s The protected high memory base and limit registers functions as follows Programming the protected low memory base and limit registers with the same value in bits HAW N 1 specifies a protected low memory region of size 2 N 1 bytes Programming the protected high memory limit register with a value less than the protected high memory base register disables the protected high memory region B D F Type 0 0 0 VCOPREMAP Address Offset 78 7Fh Reset Value 0000000000000000h Access RW RO P Reset Peer Bit Attr Value Description 63 21 RW 00000000 Protected High Memory Limit PHML 000h This register specifies the last host physical address of the DMA protected high memory region in system memory Hardware may not use bits 63 HAW where HAW is the host address width 20 0 RO 000000h Reserved 1QH_REG I nvalidation Queue Head Register This register indicates the invalidation queue head This register is treated as reserved by implementations reporting Queued I nvalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 80 87h Reset Value 0000000000000000h Access RO i Reset EE Bit Attr Value Description 63 19 RO 00000000 Reserved 0000h 18 4 RO 0000h Q
231. apability register The alignment of the protected high memory region limit depends on the number of reserved bits N of this register Software may determine the value of N by writing all 1s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of the limit register is decoded by hardware as all 1s The protected high memory base amp limit registers functions as follows e Programming the protected low memory base and limit registers with the same value in bits HAW N 1 specifies a protected low memory region of size 2 N 1 bytes Programming the protected high memory limit register with a value less than the protected high memory base register disables the protected high memory region Software must not modify this register when protected memory regions are enabled PRS field Set in PMEN_REG B D F Type 0 0 0 DMIVC1REMAP Address Offset 78 7Fh Reset Value 0000000000000000h Access RW RO Reset uae Bit Attr Value Description 63 21 RW 00000000 Protected High Memory Limit PHML 000h This register specifies the last host physical address of the DMA protected high memory region in system memory Hardware may not use bits 63 HAW where HAW is the host address width 20 0 RO 000000h Reserved Datasheet Volume 2 Processor Configuration Registers intel 2 16 19 IQH_REG Invalidat
232. apability register This register is relevant only for primary fault logging These registers are sticky and can be cleared only through powergood reset or using software clearing the RW1C fields by writing a 1 Access B D F Type Address Offset Reset Value 0 0 0 VCOPREMAP 200 20Fh 00000000000000000000000000000000h RW1C S RO V S RO Bit Attr Reset Value Description 127 RW1C S Ob Fault F Hardware sets this field to indicate a fault is logged in this Fault Recording register The F field is set by hardware after the details of the fault is recorded in the PADDR SID FR and T fields When this field is set hardware may collapse additional faults from the same requestor SID Software writes the value read from this field to clear it Refer to the VTd specification for hardware details of primary fault logging 126 RO V S Ob Type T Type of the faulted DMA request 0 DMA write 1 DMA read request This field is relevant only when the F field is set 125 124 RO V S 00b Address Type AT This field captures the AT field from the faulted DMA request Hardware implementations not supporting Device OTLBs DI field Clear in Extended Capability register treat this field as reserved When supported this field is valid only when the F field is Set and when the fault reason FR indicates one of the DMA remapping fault conditions 123 104 RO
233. apbase remaplimit registers remap logical accesses bound for addresses above 4 GB onto physical addresses that fall within DRAM Datasheet Volume 2 17 Processor Configuration Registers intel Figure 2 1 represents system memory address map in a simplified form Figure 2 1 System Address Range PHYSICAL MEMORY HOST SYSTEM VIEW DRAM CONTROLLER VIEW 64G Sees etn ee E ee E Tr i ry PCI Memory ous PEN Device o Address vice Bars Berri Bars PXPEPBAR Range PMUBASE1 CGmaom eMuBaseW MCHBAR subtractively PMULIMIT1 s PMULIMIT1 PCIEXBAR decoded to DMIBAR DMI t 14 eee van N TOM 64MB aligned Independently Programmable TOUUD BASE RECLAIM LIMIT Memon gt EP UMA Non Overlapping Windows RECLAIM BASE x Reci A 1 64MB 64MB aligned oa EP Stolen BASE 1MB aligned Address OMB 63MB RECLAIM BASE Range Wasted _ 64mB aligned 64MB aligned Mero os y VISIBLE Address gt 4 GB Range E a a eee os PCI INVISIBLE Device 0 Memory RECLAIM Device 6 Device 1 GGC Device 0 Mehean Bars Kes Bars Graphics Bars TOLUD BASE Address 64MB aligned for reclaim EROTA MBASE1 crivinabr MBASEW Stolen PXPEPBAR ig Range GFX s MLIMIT1 MLIMIT1 Me MCHBAR En aia vat a ae Aas abate ETA PMLIMIT1 PMLIMIT1 Stolen DMIBAR decoded to GFX Stolen BA
234. aphics Base of Pre allocated Memory Register This register contains the base address of DRAM memory pre allocated for graphics data BIOS determines the base of memory pre allocated for graphics by subtracting the graphics data pre allocated memory size PCI Device 0 offset 52h bits 7 4 from TOLUD PCI Device 0 offset BOh bits 15 4 This register is locked and becomes read only when CMD LOCK MEMCONMFIG is received or when ME_SM_LOCK is set to 1 B D F Type 0 0 0 PCI Address Offset A4 A7h Reset Value 0000_0000h Access RW L RO Reset Pe Bit Attr Value Description Graphics Base of Pre allocated Memory GBSM This register contains bits 31 20 of the base address of DRAM memory pre allocated for graphics BIOS determines the base of memory pre allocated 31 20 RW L 000h for graphics by subtracting the pre allocated memory size PCI Device 0 offset 52h bits 6 4 from TOLUD PCI Device 0 offset BOh bits 15 4 This register is locked and becomes Read Only when CMD LOCK MEMCONFIG is received or when ME_SM_LOCK is set to 1 19 0 RO 00000h Reserved Datasheet Volume 2 Processor Configuration Registers 2 7 19 2 7 20 intel BGSM Base of GTT Pre allocated Memory Register This register contains the base address of DRAM memory pre allocated for the GTT BIOS determines the base of pre allocated GTT memory by subtracting the GTT graphics memory pre allocated size PCI Device 0 offse
235. apped to this range or to the range above TOUUD 24 Datasheet Volume 2 Processor Configuration Registers Figure 2 4 intel There are sub ranges within the PCI Memory address range defined as APIC Configuration Space MSI Interrupt Space and High BIOS Address Range The exceptions listed above for internal graphics and the PCI Express ports MUST NOT overlap with these ranges PCI Memory Address Range FFFF_FFFFh High BIOS FFEO_0000h DMI Interface subtractive decode FEFO_0000h MSI Interrupts FEEO_0000h DMI Interface FEDO 0000h subtractive decode Local CPU APIC FEC8_0000h VO APIC FECO_0000h DMI Interface subtractive decode FO00_0000h PCI Express Configuration Space E000_0000h DMI Interface subtractive decode 4GB 4GB 2MB 4GB 17MB 4 GB 18 MB 4 GB 19 MB 4 GB 20 MB 4 GB 256 MB Possible address range size not ensured 4 GB 512 MB BARs Internal Graphics ranges PCI Express Port CHAPADR could be here TOLUD Datasheet Volume 2 25 2 2 2 9 2 2 2 9 1 2 2 2 10 26 Processor Configuration Registers APIC Configuration Space FECO_0000h FECF_FFFFh This range is reserved for APIC configuration space The I O APIC s usually reside in the PCH portion of the chipset but may also exist as stand alone components like PXH The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers t
236. appropriate bytes within the DWord to be accessed Locked transactions to the PCI Express memory mapped configuration address space are not supported All changes made using either access mechanism are equivalent The PCI Express Enhanced Configuration Mechanism utilizes a flat memory mapped address space to access device configuration registers This address space is reported by the system firmware to the operating system There is a register PCIEXBAR that defines the base address for the block of addresses below 4 GB for the configuration space associated with busses devices and functions that are potentially a part of the PCI Express root complex hierarchy In the PCIEXBAR register there are controls to limit the size of this reserved memory mapped space 256 MB is the amount of address space required to reserve space for every bus device and function that could possibly exist Options for 128 MB and 64 MB exist in order to free up those addresses for other uses In these cases the number of busses and all of their associated devices and functions are limited to 128 or 64 busses respectively The PCI Express Configuration Transaction Header includes an additional 4 bits ExtendedRegisterAddress 3 0 between the Function Number and Register Address fields to provide indexing into the 4 KB of configuration space allocated to each potential device For PCI Compatible Configuration Requests the Extended Register Address field must be all zeros
237. appropriately The PME pending bit is cleared by hardware if no more PMEs are pending PME Status PMES 16 RW1C Ob Indicates that PME was asserted by the requestor ID indicated in the PME Requestor ID field Subsequent PMEs are kept pending until the status register is cleared by writing a 1 to this field PME Requestor ID PMERI D i RO pooo Indicates the PCI requestor ID of the last PME requestor 2 10 47 LCTL2 Link Control 2 Register B D F Type 0 1 0 PCI Address Offset DO D1h Reset Value 0002h Access RO RW S r Reset a Bit Attr Value Description 15 13 RO 000 Reserved Compliance De emphasis ComplianceDeemphasis This bit sets the de emphasis level in Polling Compliance state if the entry occurred due to the Enter Compliance bit being 1b 1 3 5 dB 0 6dB 2 s Ob When the link is operating at 2 5 GT s the setting of this bit has no effect 1 RW Components that support only 2 5 GT s speed are permitted to hardwire this bit to Ob For a multi function device associated with an upstream port the bit in Function 0 is of type RWS and only Function 0 controls the component s link behavior In all other functions of that device this bit is of type RsvdP The default value of this bit is Ob This bit is intended for debug compliance testing purposes System firmware and software are allowed to modify this bit only during debug or compliance testing 11 0 RO 002h Reserved 154
238. ard wired to 0 Writes to this bit position have no effect VGAPSE VGA palette snoop Enable 5 RO 0 This host bridge does not implement this bit This bit is hard wired to a 0 Writes to this bit position have no effect MWIEN Memory Write and I nvalidate Enable 4 RO 0 This host bridge will never issue memory write and invalidate commands This bit is therefore hard wired to 0 Writers to this bit position will have no effect SCE Special Cycle Enable 3 RO 0 This host bridge does not implement this bit This bit is hard wired to a 0 Writers to this bit position will have no effect BME Bus Master Enable 2 RO 1 This host bridge is always enabled as a master This bit is hard wired to a 1 Writes to this bit position have no effect MSE Memory Space Enable 1 RO 1 This host bridge always allows access to main memory This bit is not implemented and is hard wired to 1 Writes to this bit position have no effect 1OAE Access Enable 0 RO 0 This bit is not implemented in this host bridge and is hard wired to 0 Writes to this bit position have no effect 346 Datasheet Volume 2 Intel QuickPath Architecture System Address Decode Register Description intel 3 4 8 PCI STS PCI Status Register The PCI Status register is a 16 bit status register that reports the occurrence of various error events on this device s PCI interface Device 0 Function 0 1 Offset 06h Devic
239. arget port number is with 31 24 RW O 00h respect to the component that contains this element as specified by the target component ID This can be programmed by BIOS but the Reset Value will likely be correct because the DMI RCRB in the PCH will likely be associated with the default egress port for the PCH meaning it will be assigned port number 0 Target Component ID TCID This field identifies the physical component that is targeted by this link entry 23 16 RW O 00h BIOS Requirement Must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS 15 2 RO 0000h Reserved Link Type LTYP 1 RO Ob This field indicates that the link points to memory mapped space for RCRB The link address specifies the 64 bit base address of the target RCRB Link Valid LV 0 RW O Ob 0 Link Entry is not valid and will be ignored 1 Link Entry specifies a valid link 2 12 15 DMILE1LA DMI Link Entry 1 Address Register This field provides the second part of a Link Entry which declares an internal link to another Root Complex Element B D F Type 0 0 0 DMIBAR Address Offset 58 5Fh Reset Value 0000_0000_0000_0000h Access RO RWO A Reset P Bit Attr Value Description 63 36 RO 0000000h Reserved Reserved for Link Address high order bits Link Address LA 35 12 RW O 000000h This field provides the memory mapped base address of the R
240. arity Error Detected DPD 8 RW1C Ob This bit is set when DMI received a Poisoned completion from PCH This bit can only be set when the Parity Error Enable bit in the PCI Command register is set Fast Back to Back FB2B This bit is hardwired to 1 Writes to these bit positions have no effect Device 7 RO 1b 0 does not physically connect to PCI_A This bit is set to 1 indicating fast back to back capability so that the optimum setting for PCI_A is not limited by the processor 6 RO Ob Reserved 66 MHz Capable 66MC Does not apply to PCI Express Must be hardwired to 0 Capability List CLI ST This bit is hardwired to 1 to indicate to the configuration software that this device function implements a list of new capabilities A list of new capabilities 4 RO 1b is accessed using register CAPPTR at configuration address offset 34h Register CAPPTR contains an offset pointing to the start address within configuration space of this device where the Capability Identification register resides 3 RO Ob Reserved 2 0 RO 000b Reserved Datasheet Volume 2 Processor Configuration Registers intel 2 7 5 RI D Revision Identification This register contains the revision number of the processor The Revision ID RID is a traditional 8 bit Read Only RO register located at offset 08h in the standard PCI header of every PCI PCI Express compatible device and function B D F Type 0 0 0 PCI
241. ary B D F Type 0 6 0 PCI Address Offset 24 25h Reset Value FFF1h Access RW RO z Reset PEF Bit Attr Value Description Prefetchable Memory Base Address MBASE 15 4 RW FFFh This field corresponds to A 31 20 of the lower limit of the memory range that will be passed to PCI Express G 64 bit Address Support Reserved 3 0 RO 1h This field indicates that the upper 32 bits of the prefetchable memory region base address are contained in the Prefetchable Memory base Upper Address register at 28h Datasheet Volume 2 Processor Configuration Registers t 2 19 18 PMLIMIT6 Prefetchable Memory Limit Address Register This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note that prefetchable memory range is
242. at the inband presence detect state has changed This bit is set when the value reported in Presence Detect State is changed Datasheet Volume 2 151 Processor Configuration Registers B D F Type 0 1 0 PCI Address Offset BA BBh Reset Value 0000h Access RO RW1C r Reset RE Bit Attr Value Description Reserved for MRL Sensor Changed MSC 2 RO Ob If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected If an MRL sensor is not implemented this bit must not be set Reserved for Power Fault Detected PFD If a Power Controller that supports power fault detection is implemented this bit is set when the Power Controller detects a power fault at this slot Note 1 RO Ob that depending on hardware capability it is possible that a power fault can be detected at any time independent of the Power Controller Control setting or the occupancy of the slot If power fault detection is not supported this bit must not be set Reserved for Attention Button Pressed ABP 0 RO Ob If an Attention Button is implemented this bit is set when the attention button is pressed If an Attention Button is not supported this bit must not be set 152 Datasheet Volume 2 Processor Configuration Registers intel 2 10 45 RCTL Root Control Register Allows control of PCI Express Root Complex specific parameters The system error control bits in this r
243. ates the corresponding adjusted guest address width is supported The adjusted guest address widths corresponding to various bit positions within this field are 12 8 RO 02h Oh 30 bit AGAW 2 level page table 1h 39 bit AGAW 3 level page table 2h 48 bit AGAW 4 level page table 3h 57 bit AGAW 5 level page table 4h 64 bit AGAW 6 level page table Software must ensure that the adjusted guest address width used to set up the page tables is one of the supported guest address widths reported in this field Caching Mode CM 0 Not present and erroneous entries are not cached in any of the remapping caches Invalidations are not required for modifications to individual not present or invalid entries However any modifications that result in decreasing the effective permissions or partial permission increases require invalidations for them to be effective 1 Not present and erroneous mappings may be cached in the remapping caches Any software updates to the remapping structures including updates to notpresent or erroneous entries require explicit invalidation Hardware implementations of this architecture must support a value of 0 in this field Refer to the VTd specification for more details on Caching Mode 258 Datasheet Volume 2 Processor Configuration Registers B D F Type Address Offset Reset Value Access 0 2 0 GFXVTBAR 8 Fh 00C0000020230272h RO Reset Bit A
244. ation Registers 2 2 3 1 4 Case 4 Greater than 4 GB of Physical Memory Remap Note Internal graphics is not supported on the Intel Xeon processor L3406 Figure 2 8 Greater than 4 GB Remap Enabled PHYSICAL MEMORY HOST SYSTEM VIEW DRAM CONTROLLER VIEW 64 GB TOM c 64 MB aligned pam Ffa EP UMA 1 64 MB HMMIO RECLAIM LIMIT RECLAIM BASE x MEMORY i 64 MB aligned RECLAIM Se EP Stolen BASE 0 MB 1 MB aligned REGION oon RECLAIM BASE 64 MB aligned 64 MB aligned N DRAM OS ABOVE VISIBLE 4GB gt 4 GB os x INVISIBLE TOLUD BASE RECLAIM 64 MB aligned 64 MB aligned for reclaim i PCI MMIO ET STOLEN 0 64 MB 1 MB aligned GFX GTT GFX GTT Stolen BASE 0 64 MB al TSEG TSEG TSEG BASE 0 8 MB al GFX Stolen BASE 1 MB aligned 1 MB aligned os VISIBLE lt 4GB LOW DRAM In this case the amount of memory remapped is the range between TOLUD and 4 GB This physical memory will be mapped to the logical address range defined between the REMAPBASE and the REMAPLIMIT registers Example 5 GB Physical Memory with 1 GB allocated to Memory Mapped I O e Populated Physical Memory 5 GB e Address Space allocated to memory mapped I O 1 GB e Remapped Physical Memory 1 GB e TOM 050h 5 GB e ME stolen size 00000b 0 MB e TOUUD 17FFh 6 GB 1 MB 1 MB aligned e TOLUD 06000h 3 GB 64 MB aligned becaus
245. ation request by clearing the IVT field At that time the granularity at which actual invalidation was performed is reported through the IAIG field 59 57 RO 001b 1OTLB Actual I nvalidation Granularity 1 Al G Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion by clearing the IVT field The following are the encodings for this field 000 Reserved This indicates hardware detected an incorrect invalidation request and ignored the request Examples of incorrect invalidation requests include detecting an unsupported address mask value in Invalidate Address register for page selective invalidation requests 001 Global Invalidation performed This could be in response to a global domain selective or page selective invalidation request 010 Domain selective invalidation performed using the domain id specified by software in the DID field This could be in response to a domain selective or page selective invalidation request 011 Domain page selective invalidation performed using the address mask and hint specified by software in the Invalidate Address register and domain id specified in DID field This can be in response to a page selective invalidation request 100 111 Reserved 284 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 2 0 GFXVTBAR Address Of
246. ations implement this bit as reserved RW1C S Ob Advanced Pending Fault APF When this field is Clear hardware sets this field when the first fault record at index 0 is written to a fault log At this time a fault event is generated based on the programming of the Fault Event Control register Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as reserved RW1C S Ob Advanced Fault Overflow AFO Hardware sets this field to indicate advanced fault log overflow condition At this time a fault event is generated based on the programming of the Fault Event Control register Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as reserved RO V S Oh Primary Pending Fault PPF This field indicates if there are one or more pending faults logged in the fault recording registers Hardware computes this field as the logical OR of Fault F fields across all the fault recording registers of this DMA remapping hardware unit 0 No pending faults in any of the fault recording registers 1 One or more fault recording registers has pending faults The FRI field is updated by hardware whenever the PPF field is set by hardware Also depending on the programming of the Fault Event Control register a fault event is generated when hardware sets this field RW1C S
247. atus B D F Type 0 0 0 DMI BAR Address Offset 32 33h Reset Value 0002h Access RO Reset ee Bit Attr Value Description Reserved Reserved and Zero for future R WC S implementations Software 15 2 RO 0000h must use 0 for writes to these bits Virtual Channel private Negotiation Pending VCPNP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling Software may use this bit when enabling or disabling the VC This bit 1 RO 1b indicates the status of the process of Flow Control initialization It is set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Ob Reserved 2 12 13 DMIESD DMI Element Self Description Register This register provides information about the root complex element containing this Link Declaration Capability B D F Type 0 0 0 DMIBAR Address Offset 44 47h Reset Value 01000202h Access RO RWO Reset PERA Bit Attr Value Description Port Number PORTNUM This field specifies the port number associated with this element with respect 31 24 RO Olh to the component that contains this elemen
248. b Reserved 12 RWI1C S Ob Processor Software Generated Event for SMI GSGESMI This bit indicates the source of the SMI was a Device 2 Software Event Processor Thermal Sensor Event for SMI SCI SERR GTSE This bit indicates that a processor Thermal Sensor trip has occurred and an SMI SCI or SERR has been generated The status bit is set only if a message is sent based on thermal event enables in Error command SMI command 11 RW1C S Ob and SCI command registers A trip point can generate one of SMI SCI or SERR interrupts two or more per event is illegal Multiple trip points can generate the same interrupt if software chooses this mode subsequent trips may be lost If this bit is already set then an interrupt message will not be sent on a new thermal sensor event 10 RO Ob Reserved LOCK to non DRAM Memory Flag LCKF 9 RW1C S Ob When this bit is set to 1 the processor has detected a lock operation to memory space that did not map into DRAM 8 2 RO Ob Reserved 1 RWI1C S Ob Reserved 0 RW1C S Ob Reserved Datasheet Volume 2 Processor Configuration Registers intel 2 7 25 ERRCMD Error Command Register This register controls the processor responses to various system errors Since the processor does not have an SERR signal SERR messages are passed from the processor to the PCH over DMI When a bit in this register is set a SERR message will be generated on DMI whenever the corresponding flag is set in the ERRSTS registe
249. bility PNC This value terminates the capabilities list The Virtual Channel capability and 15 8 RO 00h any other PCI Express specific capabilities that are reported using this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration Space Capability ID CID 7 0 RO 10h Identifies this linked list item capability structure as being for PCI Express registers Datasheet Volume 2 Processor Configuration Registers 2 10 35 PEG _CAP PCI Express G Capabilities Register This register indicates PCI Express device capabilities B D F Type 0 1 0 PCI Address Offset A2 A3h Reset Value 0142h Access RO RW O p Reset rgi Bit Attr Value Description 15 RO Ob Reserved 14 RO Ob Reserved Reserved for TCS Routing Supported Interrupt Message Number I MN 13 9 RO 00h Not Applicable or Implemented Hardwired to 0 Slot I mplemented SI 0 The PCI Express Link associated with this port is connected to an 8 RW O 1b integrated component or is disabled 1 The PCI Express Link associated with this port is connected to a slot BIOS Requirement This field must be initialized appropriately if a slot connection is not implemented 7A RO 4h Device Port Type DPT Hardwired to 4h to indicate root port of PCI Express Root Complex PCI Express Capability Version PCI ECV 3 0 RO 2h Hardwired to 2h to indicate compliance to the PCI Express Capabilities Re
250. bit descriptions follow Table 2 4 PCI Express Device 0 Register Address Map Poea pai Register Name Reset Value Access 0 1h VID Vendor Identification 8086h RO 2 3h DID Device Identification 0040h RO 4 5h PCICMD PCI Command 0006h RO RW 6 7h PCISTS PCI Status 0090h RWIC RO 8h RID Revision Identification 12h RO 9 Bh CC Class Code 060000h RO Dh MLT Master Latency Timer 00h RO Eh HDR Header Type 00h RO 2C 2Dh SVID Subsystem Vendor Identification 0000h RW O 2E 2Fh SID Subsystem Identification 0000h RW O 40 47h PXPEPBAR PCI Express Egress Port Base Address 0000 0000R RW L RO 48 4Fh MCHBAR MCH Memory Mapped Register Range Base 0000 0000 RW L RO 52 53h GGC Graphics Control Register 0030h RW L RO 54 57h DEVEN Device Enable 0000210Bh RW L RO 68 6Fh DMIBAR Root Complex Register Range Base Address 0000 0000 RW L RO 97h LAC Legacy Access Control 00h RW A2 A3h TOUUD Top of Upper Usable DRAM 0000h RW L A4 A7h GBSM Graphics Base of Pre Allocated Memory 0000_0000h RW L RO A8 ABh BGSM Base of GTT Pre allocated memory 0000_0000h RW L RO AC AFh TSEGMB TSEG Memory Base 0000_0000h RO RW L BO B1h TOLUD Top of Low Usable DRAM 0010h RW L RO CO C3h PBFC Primary Buffer Flush Control 0000_0000h RO W C4 C7h SBFC Secondary Buffer Flush Control 0000_0000h RO W C8 C9h ERRSTS Error Status 0000h RO RW1C S CA CBh ERRCMD Error Command 0000h RO RW DC
251. bit is an indication to the operating system to allow for such removal without impacting continued software operation Reserved for Power Indicator Present PIP 4 RO Ob When set to 1 this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot Reserved for Attention Indicator Present AIP 3 RO Ob When set to 1 this bit indicates that an Attention Indicator is electrically controlled by the chassis Reserved for MRL Sensor Present MSP 2 RO Ob When set to 1 this bit indicates that an MRL Sensor is implemented on the chassis for this slot Reserved for Power Controller Present PCP 1 RO Ob When set to 1 this bit indicates that a software programmable Power Controller is implemented for this slot adapter depending on form factor Reserved for Attention Button Present ABP 0 RO Ob When set to 1 this bit indicates that an Attention Button for this slot is electrically controlled by the chassis Datasheet Volume 2 321 intel Processor Configuration Registers 2 19 42 SLOTCTL Slot Control Register Note Hot Plug is not supported on the platforms B D F Type 0 6 0 PCI Address Offset B8 B9h Reset Value 0000h Access RO RW i Reset Bee Bit Attr Value Description 15 13 RO 000b Reserved Reserved for Data Link Layer State Changed Enable DLLSCE If the Data Link Layer Link Active capability is implemented when set to 1b this field enables software notif
252. ble Address 00000000000 RO B8 BFh 00000h IVA_REG Invalidate Address Register 00000000000 RO 100 107h 00000h 108 10Fh IOTLB_REG IOTLB Invalidate Register 02000000000 RW RO 00000h FRCD_REG Fault Recording Registers 00000000000 RO V S 200 20Fh 00000000000 RO RW1C 0000000000h S FFC FFFh VTPOLICY VT Policy 40000000h ss roii Datasheet Volume 2 255 intel 2 18 1 256 Processor Configuration Registers VER_REG Version Register This register reports the architecture version supported Backward compatibility for the architecture is maintained with new revision numbers allowing software to load DMA remapping drivers written for prior architecture versions B D F Type 0 2 0 GFXVTBAR Address Offset 0 3h Reset Value 00000010h Access RO Reset ae Bit Attr Value Description 31 8 RO 000000h Reserved 7A RO th Major Version number MAX l Indicates supported architecture version 3 0 RO Oh Minor Version number MI N l l Indicates supported architecture minor version Datasheet Volume 2 Processor Configuration Registers 2 18 2 CAP_REG Capability Register This register reports general DMA remapping hardware capabilities B D F Type 0 2 0 GFXVTBAR Address Offset 8 Fh Reset Value 00C0000020230272h Access RO Reset par Bit Attr Value Description 63 56 RO 00h Reserved DMA Read Draining DRD 0
253. buffers will be put into their reset state 0 All DDR IO buffers are put into reset state 1 All DDR IO buffers are out of reset and in normal operation mode Datasheet Volume 2 85 intel Processor Configuration Registers 2 8 22 C1DRBO Channel 1 DRAM Rank Boundary Address 0 Register The operation of this register is detailed in the description for register CODRBO B D F Type 0 0 0 MCHBAR Address Offset 600 601h Reset Value 0000h Access RW L RO A Reset gona Bit Attr Value Description 15 10 RO 000000b Reserved Channel 1 DRAM Rank Boundary Address 0 C1DRBAO 9 0 RW L 000h See CODRBO register description This register is locked by Memory pre allocated for ME lock 2 8 23 C1DRB1 Channel 1 DRAM Rank Boundary Address 1 Register The operation of this register is detailed in the description for register CODRBO B D F Type 0 0 0 MCHBAR Address Offset 602 603h Reset Value 0000h Access RO RW L 7 Reset putes Bit Attr Value Description 15 10 RO 000000b Reserved Channel 1 DRAM Rank Boundary Address 1 C1DRBA1 9 0 RW L 000h See CODRB1 register description This register is locked by Memory pre allocated for ME lock 2 8 24 C1DRB2 Channel 1 DRAM Rank Boundary Address 2 Register The operation of this register is detailed in the description for register CODRBO B D F Type 0 0 0 MCHBAR Address Of
254. by the downstream component that was not indicated as an autonomous change Data Link Layer Link Active Optional DLLLA This bit indicates the status of the Data Link Control and Management State 13 RO Ob Machine It returns a 1b to indicate the DL_Active state Ob otherwise This bit must be implemented if the corresponding Data Link Layer Active Capability bit is implemented Otherwise this bit must be hardwired to Ob Slot Clock Configuration SCC 0 The device uses an independent clock irrespective of the presence of a 12 RO 1b reference on the connector 1 The device uses the same physical reference clock that the platform provides on the connector Link Training LTRN This bit indicates that the Physical Layer LTSSM is in the Configuration or 11 RO Ob Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun Hardware clears this bit when the LTSSM exits the Configuration Recovery state once Link training is complete Undefined Reserved The value read from this bit is undefined In previous versions of this 10 RO Ob specification this bit was used to indicate a Link Training Error System software must ignore the value read from this bit System software is permitted to write any value to this bit Negotiated Link Width NLW This field indicates negotiated link width This field is valid only when the link is in the LO LOs or L1 states after link width negotiation is successfully completed
255. capable of 16UI granularity in retraining duration PHY_ VERSION This is the Intel QPI Phy version 0 Current Intel QPI version 0 Others Reserved 3 0 RO Datasheet Volume 2 357 Intel QuickPath Architecture System Address Decode Register Description intel 3 8 2 QPI_O PH_CTR QPI_1 PH_CTR This is the Intel QPI Physical Layer Control Register Device 2 Function 1 Offset 6Ch Access as a Dword Reset ii Bit Type Value Description 31 28 RV 0 Reserved LA_LOAD_ DISABLE 27 RW 0 This bit disables the loading of the effective values of the Intel QPI CSRs when set 26 24 RV 0 Reserved ENABLE_PRBS 23 RW 0 This bit enables LFSR pattern during bitlock training 1 Use pattern in bitlock retraining 0 Use clock pattern for bitlock retraining ENABLE_ SCRAMBLE 22 RW 0 This bit enables data scrambling through LFSR 1 Data scrambled descrambled with LFSR 0 Data not scrambled descrambled 21 16 RV 0 Reserved DETERMI NI SM_ MODE Sets determinism mode of operation 00 Non deterministic initialization 15 14 RW 2 01 Slave mode initialization 10 Master mode of initialization valid only if a component can generate its PhyLOSynch DISABLE_AUTO_COMP Disables automatic entry into compliance 13 RW 1 0 Path from detect clkterm to compliance is allowed 1 Path from detect clkterm to compliance is disabled 12 RW 0 INIT_FREEZE l ae
256. cate that this Internal Graphics Device is a single function device Header Code H 6 0 RO 00h This is a 7 bit value that indicates the Header Code for the IGD This code has the value 00h indicating a type 0 configuration space format 178 Datasheet Volume 2 Processor Configuration Registers 2 13 10 intel GTTMMADR Graphics Translation Table Memory Mapped Range Address Register This register requests allocation for the combined Graphics Translation Table Modification Range and Memory Mapped Range The range requires 4 MB combined for MMIO and Global GTT aperture with 512K of that used by MMIO and 2MB used by GTT GTTADR will begin at GTTMMADR 2 MB while the MMIO base address will be the same as GTTMMADR For the Global GTT this range is defined as a memory BAR in graphics device config space Itis an alias into which software is required to write Page Table Entry values PTEs Software may read PTE values from the global Graphics Translation Table GTT PTEs cannot be written directly into the global GTT memory area The device snoops writes to this region in order to invalidate any cached translations within the various TLBs implemented on chip The allocation is for 4 MB and the base address is defined by bits 35 22 B D F Type 0 2 0 PCI Address Offset 10 17h Reset Value 0000_0000_0000_0004h Access RW RO Reset ar Bit Attr Value Description Reserved Reserved
257. cated in the VC Arbitration Capability field The value 000b when written 3 1 RW 000b to this field will indicate the VC arbitration scheme is hardware fixed in the root complex This field cannot be modified when more than one VC in the LPVC group is enabled 0 RO Ob Reserved for Load VC Arbitration Table 110 Datasheet Volume 2 Processor Configuration Registers intel 2 9 3 EPVCORCTL EP VC O Resource Control Register This register controls the resources associated with Egress Port Virtual Channel 0 B D F Type 0 0 0 PXPEPBAR Address Offset 14 17h Reset Value 8000_OOFFh Access RO RW Reset PEPP Bit Attr Value Description VCO Enable VCOE 31 RO Tb For VCO this is hardwired to 1 and read only as VCO can never be disabled 30 27 RO Oh Reserved VCO ID VCOID 26 24 RO 000b Assigns a VC ID to the VC resource For VCO this is hardwired to 0 and read only 23 20 RO Oh Reserved Port Arbitration Select PAS 19 17 RW 000b This field configures the VC resource to provide a particular Port Arbitration service The value of Oh corresponds to the bit position of the only asserted bit in the Port Arbitration Capability field 16 8 RO 000h Reserved TC VCO Map TCVCOM This field indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 7 is set in this field TC7 is mapped
258. cceeeee eee eect eens tenet rn ere 292 2 19 5 RID6 Revision Identification ReGiSter c cece eee e eee eee teeta eae 293 2 19 6 CC6 Class Code ReGiSter cece cece eee eee eee eee eee ee eaten ee ee teeta 293 2 19 7 CL6O Cache Line Size Register 1 0 eee eee ee eee ata ene eae 294 2 19 8 HDR6 Header Type ReGiSter cece cee ee eect eee eee teeta ee ea eae eee ee te nena 294 2 19 9 PBUSN6 Primary Bus Number Register ccceeeeee eee ee eee ee ee ee teen eas 294 2 19 10 SBUSN6 Secondary Bus Number Register c cceeee eee eeeeeeeeee eee ee ees 295 2 19 11 SUBUSN6 Subordinate Bus Number ReGiSter cccceee cece eee ee eaten 295 2 19 12 OBASE6 I O Base Address ReGiSter ccececeee eect eee e ee ee eee eeee teen tees 296 2 19 13 IOLIMIT6 I O Limit Address Register cece cece eee eee e tence eee eee r 296 2 19 14 SSTS6 Secondary Status ReGISter cee eee eee eaters 297 2 19 15 MBASE6 Memory Base Address Register ccccceeee ee ee eee eens teeta ees 298 2 19 16 MLIMIT6 Memory Limit Address Register ccsceeee eect ee eeee teen eens 299 2 19 17 PMBASE6 Prefetchable Memory Base Address Register 0ceeee eee 300 2 19 18 PMLIMIT6 Prefetchable Memory Limit Address Register 301 2 19 19 PMBASEU6 Prefetchable Memory Base Address Upper Register 302 2 19 20 PMLIMITU6 Prefetchable Memory Limit Address
259. cess RW O 5 Reset ar Bit Attr Value Description Subsystem ID SUBID 15 0 RW O 0000h This field should be programmed during BIOS initialization After it has been written once it becomes read only 2 7 11 PXPEPBAR PCI Express Egress Port Base Address Register This is the base address for the PCI Express Egress Port MMIO Configuration space There is no physical memory within this 4 KB window that can be addressed The 4 KB reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset the EGRESS port MMIO configuration space is disabled and must be enabled by writing a 1 to PXPEPBAREN Device 0 offset 40h bit 0 All the bits in this register are locked in Intel TXT mode B D F Type 0 0 0 PCI Address Offset 40 47h Reset Value 0000_0000_0000_0000h Access RW L RO Reset oe Bit Attr Value Description 63 36 RO 0000000h Reserved PCI Express Egress Port MMIO Base Address PXPEPBAR This field corresponds to bits 35 12 of the base address PCI Express Egress Port MMIO configuration space BIOS will program this register resulting in a _ base address for a 4 KB block of contiguous memory address space This 33u12 ae 9090091 register ensures that a naturally aligned 4 KB space is allocated within the first 64 GB of addressable memory space System Software uses this base address to program the processor MMIO register set All the bits in this register
260. chanism defined for the slot s corresponding form factor Note that the in band presence detect mechanism requires that power be applied to an adapter for its presence to be detected Consequently form factors that require a power controller for hot plug must 6 RO Ob implement a physical pin presence detect mechanism Defined encodings are Ob Slot Empty 1b Card Present in slot This register must be implemented on all Downstream Ports that implement slots For Downstream Ports not connected to slots where the Slot Implemented bit of the PCI Express Capabilities Register is Ob this bit must return 1b Reserved for MRL Sensor State MSS 5 RO Ob This register reports the status of the MRL sensor if it is implemented Ob MRL Closed 1b MRL Open Reserved for Command Completed CC If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register this bit is set when a hot plug command has completed and the Hot Plug Controller is ready to accept a subsequent command The Command Completed status bit 4 RO Ob is set as an indication to host software that the Hot Plug Controller has processed the previous command and is ready to receive the next command it provides no assurance that the action corresponding to the command is complete If Command Completed notification is not supported this bit must be hardwired to Ob Presence Detect Changed PDC 3 RW1C Ob A pulse indication th
261. covery state This mode provides external devices such as logic analyzers monitoring the Link time to achieve bit and symbol lock before the link enters LO and resumes communication This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns RW Ob Common Clock Configuration CCC 0 Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock 1 Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock The state of this bit affects the LOs Exit Latency reported in LCAP 14 12 and the N_FTS value advertised during link training See PEGLOSLAT at offset 22Ch Datasheet Volume 2 Processor Configuration Registers B D F Type 0 1 0 PCI Address Offset BO Bih Reset Value 0000h Access RO RW RW SC P Reset rere Bit Attr Value Description Retrain Link RL 0 Normal operation 1 Full Link retraining is initiated by directing the Physical Layer LTSSM from LO LOs or L1 states to the Recovery state This bit always returns 0 when read This bit is cleared automatically no need to write a 0 5 RW SC Ob Link Disable LD 0 Normal operation 1 Link is disabled Forces the LTSSM to transition to the Disabled state 4 RW Ob using Recovery from LO LOs or L1 states Link retrainin
262. ct Datasheet Volume 2 99 intel 2 8 47 100 Processor Configuration Registers TI S1 Thermal Interrupt Status 1 Register This register is used to report which specific error condition resulted in the D2FO or D2F1 ERRSTS Thermal Sensor event for SMI SCI SERR or memory mapped IIR Thermal Event Software can examine the current state of the thermal zones by examining the TSS Software can distinguish internal or external Trip Event by examining TSS B D F Type 0 0 0 MCHBAR Address Offset 101E 101Fh Reset Value 0000h Access RO RW1C z Reset PREE Bit Attr Value Description 15 14 RO 00b Reserved Was Catastrophic Thermal Sensor Interrupt Event WCTSI E 1 Indicates that a Catastrophic Thermal Sensor trip based on a higher to 13 RW1C Ob lower temperature transition thru the trip point 0 Notrip for this event Software must write a 1 to clear this status bit Was Hot Thermal Sensor I nterrupt Event WHTSIE 1 A Hot Thermal Sensor trip occurred based on a higher to lower 12 RW1C Ob temperature transition through the trip point 0 Notrip for this event Software must write a 1 to clear this status bit Was Aux 3 Thermal Sensor Interrupt Event WA3TSIE 1 Aux 3 Thermal Sensor trip occurred based on a higher to lower 11 RW1C Ob temperature transition through the trip point 0 No trip for this event Software must write a 1 to clear this status bit Was Aux 2 Thermal Sens
263. d Register This register manages context cache The act of writing the uppermost byte of the CCMD_REG with ICC field set causes the hardware to perform the context cache invalidation Access B D F Type Address Offset Reset Value 0 0 0 DMIVC1LREMAP 28 2Fh 0000000000000000h RW SC RW RO W Bit Attr Reset Value Description 63 RW SC Ob Invalidate Context Cache ICC Software requests invalidation of context cache by setting this field Software must also set the requested invalidation granularity by programming the CIRG field Software must read back and check the ICC field to be clear to confirm the invalidation is complete Software must not update this register when this field is set Hardware clears the ICC field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the CAIG field Software must not submit another invalidation request through this register while the ICC field is set Software must submit a context cache invalidation request through this field only when there are no invalidation requests pending at this DMA remapping hardware unit Refer to the VTd specification for software programming requirements Since information from the context cache may be used by hardware to tag OTLB entries software must perform domain selective or global invalidation of OTLB after the context cac
264. d as a DWord All multi byte numeric fields use little endian ordering that is lower addresses contain the least significant parts of the field Registers that reside in bytes 256 through 4095 of each device may only be accessed using memory mapped transactions in DWord 32 bit quantities Some of the processor registers described in this section contain reserved bits These bits are labeled Reserved Software must deal correctly with fields that are reserved On reads software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value On writes software must ensure that the values of reserved bit positions are preserved That is the values of reserved bit Datasheet Volume 2 43 m t 1 Processor Configuration Registers 2 6 44 positions must first be read merged with the new values for other bit positions and then written back Note the software does not need to perform read merge and write operation for the Configuration Address Register In addition to reserved bits within a register the processor contains address locations in the configuration space of the Host Bridge entity that are marked either Reserved or Intel Reserved The processor responds to accesses to Reserved address locations by completing the host cycle When a Reserved register location is read a zero value is returned Reserved registers can be 8 16 or 32 bits in size Writes to Reserved
265. d by DRAM 11 10 RV 0 Reserved PAM5_LOENABLE 0E0000h O0E3FFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from OE0000h to OE3FFFh 9 8 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 7 6 RV 0 Reserved PAM4_HI ENABLE O0DCOOOh ODFFFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from ODCOOOh to ODFFFFh 5 4 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 3 2 RV 0 Reserved PAM4_LOENABLE 0D8000h ODBFFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from O0D8000h to ODBFFFh 1 0 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM
266. d normally be off in thermometer mode since the thermometer mode of the thermal sensor defeats the usefulness of analog hysteresis T219 RW on 0 Hysteresis disabled 1 Analog hysteresis enabled This setting falls within the same byte as the In Use bit in bit 8 Therefore if this setting is read software must write a 1 to bit 8 if it does not intend to maintain ownership of the Thermal Sensor resource 9 9 RO Oh Reserved In Use IU Software semaphore bit After a full MCH RESET a read to this bit returns a 0 After the first read subsequent reads will return a 1 A write of a 1 to this bit will reset the next read value to 0 Writing a 0 to this bit has no effect Software can poll this bit until it reads a 0 and will then own the usage of the 8 AF Ob thermal sensor This bit has no other effect on the hardware and is only used as a semaphore among various independent software threads that may need to use the thermal sensor Software that reads this register but does not intend to claim exclusive access of the thermal sensor must write a one to this bit if it reads a 0 in order to allow other software threads to claim it See also THERM bit 15 which is an independent additional semaphore bit 7 1 RO 00h Reserved Thermal Sensor Enable TSE This bit enables the thermal sensor logic in the core The thermal sensor 0 RW L Ob circuit EBB is enabled on PWROK Lockable using TSTTPA1 bit 30 0 Disabled 1 Enabled 94 Datasheet Vo
267. d when an unmasked Advisory Non Fatal UR is received An ERR_FATAL or ERR_NONFATAL is sent to the Root Control register when an uncorrectable non Advisory UR is received with the severity bit set in the Uncorrectable Error Severity register Fatal Error Reporting Enable FERE 2 RW Ob When set this bit enables signaling of ERR_FATAL to the Root Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Non Fatal Error Reporting Enable NERE 1 RW Ob When set this bit enables signaling of ERR_NONFATAL to the Root Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Correctable Error Reporting Enable CERE When set this bit enables signaling of ERR_CORR to the Root Control register 0 RW Ob due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Datasheet Volume 2 313 Processor Configuration Registers intel 2 19 37 DSTS Device Status Register This register reflects status corresponding to controls in the Device Control register The error reporting bits are in reference to errors detected by this device not errors messages received across the link B D F Type 0 6 0 PCI Address O
268. d_cr_cyctrk_faw_phase_fix_disable ACT Window Count C1sd_cr_act_windowcnt This field indicates the window duration in DRAM clocks during which the 27 22 RW o00000b controller counts the number of activate commands which are launched to a particular rank If the number of activate commands launched within this window is greater than 4 then a check is implemented to block launch of further activates to this rank for the rest of the duration of this window Max ACT Check C1sd_cr_maxact_dischk 21 RW Ob This bit enables the check which ensures that there are no more than four activates to a particular rank in a given window ACT to ACT Delayed C1sd_cr_act_act This field indicates the minimum allowed spacing in DRAM clocks between two ACT commands to the same rank This field corresponds to tRRD in the DDR specification 20 17 RW 0000b PRE to ACT Delayed C1sd_cr_pre_act This field indicates the minimum allowed spacing in DRAM clocks between 0000b the PRE and ACT commands to the same rank bank 12 9R WOOOObPRE ALL to ACT Delayed C1sd_cr_preall_act This field indicates the minimum allowed spacing in DRAM clocks between the PRE ALL and ACT commands to the same rank This field corresponds to tRP in the DDR specification 16 13 RW ALLPRE to ACT Delay C1sd_cr_preall_ act 12 9 RW Oh From the launch of a prechargeall command wait for these many numbers of mclks before launching a activate command Corr
269. dered RW L Ob DMI VC1 Hit Queue Throttling DMIVCLHTQT 1 Throttle the outlet DMI VC1 Hit Queue to fill up the queue 0 No throttling at the outlet of the DMI VC1 Hit Queue RW L Ob DMIVC1 TLB Disable DMIVC1TLBDIS 1 DMIVC1 TLBs are disabled and each GPA request will result in a miss and a root walk will be requested from VTd Dispatcher 0 normal mode DMIVC1 TLBs are enabled and normal hit miss flows are followed RW L Ob Global I OTLB Invalidation Promotion GLBI OTLBI NV This bit controls the OTLB Invalidation behavior of the DMA remap engine 1 any type of IOTLB I nvalidation valid or invalid will be promoted to Global IOTLB Invalidation 0 normal operation Ob Global Context I nvalidation Promotion GLBCTXTI NV This bit controls the Context Invalidation behavior of the DMA remap engine 1 any type of Context Invalidation valid or invalid will be promoted to Global Context Invalidation 0 normal operation Datasheet Volume 2 Processor Configuration Registers 2 17 Graphics Control Registers 2 17 1 MGGC Graphics Control Register All the Bits in this register are Intel TXT lockable B D F Type Address Offset Reset Value Access 0 2 0 PCI 52 53h 0030h RO Bit Attr Reset Value Description 15 12 RO Oh Reserved Oh GTT Graphics Memory Size GGMS This field is used to select the amount of mai
270. dicates to which input of the system interrupt controller this device s interrupt pin is connected I NTRPI N1 I nterrupt Pin Register This register specifies which interrupt pin this device uses B D F Type 0 1 0 PCI Address Offset 3Dh Reset Value Olh Access RO A Reset goa Bit Attr Value Description Interrupt Pin INTPIN 7 0 RO Olh As a single function device the PCI Express device specifies INTA as its interrupt pin OLH INTA Datasheet Volume 2 Processor Configuration Registers intel 2 10 24 BCTRL1 Bridge Control Register This register provides extensions to the PCICMD1 register that are specific to PCI PCI bridges The BCTRL provides additional control for the secondary interface that is PCI Express G as well as some bits that affect the overall behavior of the virtual Host PCI Express bridge embedded within the processor such as VGA compatible address ranges mapping B D F Type 0 1 0 PCI Address Offset 3E 3Fh Reset Value 0000h Access RO RW Reset Sie Bit Attr Value Description 15 12 RO Oh Reserved 11 RO Ob Discard Timer SERR Enable DTSERRE Not Applicable or Implemented Hardwired to 0 10 RO Ob Discard Timer Status DTSTS l Not Applicable or Implemented Hardwired to 0 9 RO Ob Secondary Discard Timer SDT Not Applicable or Implemented Hardwired to 0 8 RO Ob Primary Discard Timer PDT Not Applicable or Implemen
271. dth reported in the Capability register 31 0 RO 0000 000 Reserved Datasheet Volume 2 285 intel 2 18 29 286 Processor Configuration Registers FRCD_REG Fault Recording Registers Registers to record fault information when primary fault logging is active Hardware reports the number and location of fault recording registers through the Capability register This register is relevant only for primary fault logging These registers are sticky and can be cleared only through power good reset or by software clearing the RW1C fields by writing a 1 B D F Type 0 2 0 GFXVTBAR Address Offset 200 20Fh Reset Value 00000000000000000000000000000000h Access RO V S RO RW1C S Reset ee Bit Attr Value Description Fault F Hardware sets this field to indicate a fault is logged in this Fault Recording register The F field is Set by hardware after the details of the fault is recorded in other fields 127 RWIC S 0b When this field is Set hardware may collapse additional faults from the same source id SID Software writes the value read from this field to Clear it Refer to the VTd specification for hardware details of primary fault logging Type T Type of the faulted request V 0 Write request 126 ro 2 1 Read request This field is relevant only when the F field is Set and when the fault reason FR indicates one of the DMA remapping fault conditions Address Typ
272. e When Set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches RW Ob Hardware Autonomous Width Disable HAWD Hardware Autonomous Width Disable When Set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width Devices that do not implement the ability autonomously to change Link width are permitted to hardwire this bit to Ob RO Ob Enable Clock Power Management ECPM Applicable only for form factors that support a Clock Request CLKREQ mechanism this enable functions as follows 0 Clock power management is disabled and device must hold CLKREQ signal low 1 When this bit is set to 1 the device is permitted to use CLKREQ signal to power manage link clock according to protocol defined in appropriate form factor specification The Reset Value of this field is 0b Components that do not support Clock Power Management as indicated by a Ob value in the Clock Power Management bit of the Link Capabilities Register must hardwire this bit to Ob RW Ob Extended Synch ES 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state and when in the Re
273. e 2 Function 0 1 Offset 06h Bit Type eae Description Detect Parity Error DPE 15 RO 0 The host bridge does not implement this bit and is hard wired to a 0 Writes to this bit position have no effect Signaled System Error SSE This bit is set to 1 when this device generates an SERR message over the 14 RO 0 bus for any enabled error condition If the host bridge does not signal errors using this bit this bit is hard wired to a O and is read only Writes to this bit position have no effect Received Master Abort Status RMAS This bit is set when this device generates request that receives an Unsupported Request completion packet Software clears the bit by 13 RO 0 writing 1 to it If this device does not receive Unsupported Request completion packets the bit is hard wired to 0 and is read only Writes to this bit position have no effect Received Target Abort Status RTAS This bit is set when this device generates a request that receives a Completer Abort completion packet Software clears this bit by writing a 1 12 RO 0 to it If this device does not receive Completer Abort completion packets this bit is hard wired to O and read only Writes to this bit position have no effect Signaled Target Abort Status STAS 11 RO 0 This device will not generate a Target Abort completion or Special Cycle This bit is not implemented in this device and is hard wired to a 0 Writes to this bit position have no effect D
274. e AT This field captures the AT field from the faulted DMA request Hardware implementations not supporting Device IOTLBs DI field Clear in 12a RO oop Extended Capability register treat this field as reserved When supported this field is valid only when the F field is Set and when the fault reason FR indicates one of the DMA remapping fault conditions 123 104 RO 00000h Reserved Fault Reason FR 103 96 RO V S 00h Reason for the fault The VT specification 1 2 Appendix enumerates the various translation fault reason encodings This field is relevant only when the F field is set 95 80 RO 0000h Reserved Source Identifier SID 79 64 RO V S 0000h Requester id associated with the fault condition This field is relevant only when the F field is Set Page Address PADDR When the Fault Reason FR field indicates one of the DMA remapping fault conditions bits 63 12 of this field contains the page address in the faulted DMA request Hardware treat bits 63 N as reserved 0 where N is the 63 12 RO V S 00090099 maximum guest address width MGAW supported When the Fault Reason FR field indicates one of the interrupt remapping fault conditions bits 63 48 of this field indicate the interrupt_index computed for the faulted interrupt request and bits 47 12 are cleared This field is relevant only when the F field is Set 11 0 RO 000h Reserved Datasheet Volume 2 Processor Configuration Registers 2 18 30 VTPOLICY VT Policy Regist
275. e System software uses this base address to program the DMI register set All the bits in this register are locked in Intel TXT mode 11 1 RO 000h Reserved DMI BAR Enable DMI BAREN 0 Disable DMIBAR is disabled and does not claim any memory 0 RW L Ob 1 Enable DMIBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel TXT Datasheet Volume 2 55 56 Processor Configuration Registers LAC Legacy Access Control Register This 8 bit register controls steering of MDA cycles There can only be at most one MDA device in the system BIOS must not program bits 1 0 to 11b B D F Type 0 0 0 PCI Address Offset 97h Reset Value 00h Access RW BIOS Optimal Reset Value 00h A Reset Hani Bit Attr Value Description 7 2 RO Oh Reserved PEG1 MDA Present MDAP1 This bit works with the VGA Enable bits in the BCTRL register of Device 6 to control the routing of processor initiated transactions targeting MDA compatible I O and memory address ranges This bit should not be set if device 6 s VGA Enable bit is not set If device 6 s VGA enable bit is not set then accesses to 1O address range x3BCh x3BFh remain on the backbone If the VGA enable bit is set and MDA is not present then accesses to 10O address range x3BCh x3BFh are forwarded to PCI Express through device 6 if the address is within the corresponding OBASE and IOLIMIT otherwise they remain on the backbone MD
276. e Description Revision Identification Number RID This is an 8 bit value that indicates the revision identification number for the 7 0 RO 08h processor Device 0 Refer to the Intel Core i5 600 and i3 500 Desktop Processor Series and Intel Pentium Desktop Processor 6000 Series Specification Update for the value of the Revision ID Register 2 13 6 CC Class Code Register This register contains the device programming interface information related to the Sub Class Code and Base Class Code definition for the IGD This register also contains the Base Class Code and the function sub class in relation to the Base Class Code B D F Type 0 2 0 PCI Address Offset 9 Bh Reset Value 030000h Access RO s Reset BAPA Bit Attr Value Description Base Class Code BCC This is an 8 bit value that indicates the base class code for the processor This code has the value 03h indicating a Display Controller 23 16 RO 03h When MCHBAR offset 44 bit 31 is 0 this code has the value 03h indicating a Display Controller When MCHBAR offset 44 bit 31 is 1 this code has the value 04h indicating a Multimedia Device Sub Class Code SUBCC When MCHBAR offset 44 bit 31 is 0 this value will be determined based on Device 0 GGC register GMS and IVD fields 15 8 RO 00h 00h VGA compatible 80h Non VGA GMS 0000 or IVD 1 When MCHBAR offset 44 bit 31 is 1 this value is 80h indicating other multimedia device
277. e clear through platform reset DMA Remap Engine Policy Control DMAR_ CTL It_gv_vt_scr_reserved_fault_en 30 RW L Ob 0 Default Hardware support s reserved field programming faults in root context and page translation structure that is fault code of Ah Bh Ch 1 Hardware ignores reserved field programming faults in the root context and page translation structure 29 23 RW L 00h Reserved Lookup Policy TLB I nvalidation LKUPPOLTLBI NVL VCO VCp Remap Engine TLB Lookup Policy On TLB Invalidation 1 Mask all TLB Lookup to VCO VCp remap engine during TLB Invalidation Window 22 RW L Ob 0 Continue to perform TLB lookup to VCO VCp remap engine during TLB Invalidation Window TLB Invalidation Window refers to the period from when the TLB I nvalidation is initiated until all the outstanding DMA read and write cycles at the point of TLB Invalidation are initiated are Globally Ordered PEG1 VCO Read Hit Queue Throttling PEG1VCORDHTQT 21 RW L Ob 1 Throttle the outlet PEGO VC1 Read Hit Queue to fill up the queue 0 No throttling at the outlet of the PEG1 VCO Read Hit Queue PEG1 VCO Write Queue Throttling PEG1VCOWRHTQT 20 RW L Ob 1 Throttle the outlet PEG1 VCO Write Hit Queue to fill up the queue 0 No throttling at the outlet of the PEG1 VCO Write Hit Queue PEGO VCO Read Hit Queue Throttling PEGVCORDHTQT 19 RW L Ob 1 Throttle the outlet PEGO VCO Read Hit Queue to fill up the queue 0
278. e ee eee eee een eae 95 2 8 40 TR1 Thermometer Read 1 Register cece cece eee eee ee eee nena teeta neta 95 2 8 41 TOF1 Thermometer Offset 1 Register cccececece tent ee eee ee tena eee ee eens 96 2 8 42 RTR1 Relative Thermometer Read 1 Register acnee 96 2 8 43 TSTTPA1 Thermal Sensor Temperature Trip Point Al Register 97 2 8 44 TSTTPB1 Thermal Sensor Temperature Trip Point B1 Register 98 2 8 45 TS10BITMCTRL Thermal Sensor 10 bit Mode Control Register 98 2 8 46 HWTHROTCTRL1 Hardware Throttle Control 1 Register ceeeeeeee 99 2 8 47 TIS1 Thermal Interrupt Status 1 Register cece eee ee eee nett eaten 100 2 8 48 TERATE Thermometer Mode Enable and Rate Register ceeee ee 102 2 8 49 TERRCMD Thermal Error Command Register ceecee 103 2 8 50 TSMICMD Thermal SMI Command Register neeese 104 2 8 51 TSCICMD Thermal SCI Command Register c cceceeeeeeeee tees teen nena 105 2 8 52 TINTRCMD Thermal INTR Command Register 0 ceceeeeee ee eee eee ee eae 106 2 8 53 EXTTSCS External Thermal Sensor Control and Status Register 107 2 8 54 DDRMPLL1I DDR PLL BIOS Register ccececee cette eee ee eee eee teenies 109 2 9 JEPBAR REGIStGrSis 2ciccstesectchoantece an atidhe re ayganeakadelaca dimes E ER E E AE E 110 2 9 1 EPPVCCAP1 EP Port VC Capability Register 1
279. e monitor VMM and for some uses certain platform software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Active Management Technology requires the computer system to have an Intel R AMT enabled chipset network hardware and software as well as connection with a power source and a corporate network connection Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality It may also require modifications of implementation of new business processes With regard to notebooks Intel AMT may not be available or certain capabilities may be limited over a host OS based VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see www intel com technology platform technology intel amt Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order
280. e processor access to this range will be sent on the HOM QPI channel PCI Express and DMI originated cycles to enabled SMM space are not allowed and are considered to be to the Video Buffer Area if IGD is not enabled as the VGA device DMI initiated writes cycles are attempted as peer writes cycles to a VGA enabled PCle port Monochrome Adapter MDA Range O000B_0000h O000B_7FFFh Legacy support requires the ability to have a second graphics controller monochrome in the system Accesses in the standard VGA range are forwarded to IGD PCI Express or the DMI Interface depending on configuration bits Since the monochrome adapter may be mapped to any of these devices the processor must decode cycles in the MDA range 000B_0000h 000B_7FFFh and forward either to IGD PCI Express or the DMI Interface This capability is controlled by a VGA steering bits and the legacy configuration bit MDAP bit In addition to the memory range BOOOOh to B7FFFh the processor decodes I O cycles at 3B4h 3B5h 3B8h 3B9h 3BAh and 3BFh and forwards them to the either IGD PCI Express and or the DMI Interface PAM 000C_0000h 000F_FFFFh The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory Area Each section has Read enable and Write enable attributes The processor documentation will now contain the registers and decode rules restrictions The PAM registers have moved to the processor For the PAM register details refer to
281. e processor registers described in this section contain reserved bits These bits are labeled Reserved Software must deal correctly with fields that are reserved On reads software must use appropriate masks to extract the defined bits and not rely on reserved bits Reserved being any particular value On writes software must ensure that the values of reserved bit Bits positions are preserved That is the values of reserved bit positions must first be read merged with the new values for other bit positions and then written back Note that software does not need to perform a read merge write operation for the Configuration Address CONFIG_ADDRESS register In addition to reserved bits within a register the processor contains address locations in the configuration space that are marked either Reserved or Intel Reserved The processor responds to accesses to Reserved address locations by completing the host cycle When a Reserved Reserved register location is read a zero value is returned Reserved registers can be 8 16 Registers or 32 bits in size Writes to Reserved registers have no effect on the processor Registers that are marked as Intel Reserved must not be modified by system software Writes to Intel Reserved registers may cause system failure Reads to Intel Reserved registers may return a non zero value Upon a reset the processor sets all of its internal configuration registers to
282. e remap is enabled and the remap register has 64 MB granularity e REMAPBASE 050h 5GB e REMAPLIMIT O5Fh 6 GB 1 boundary 32 Datasheet Volume 2 Processor Configuration Registers t 2 2 4 2 2 5 PCI Express Configuration Address Space PCIEXBAR has moved to the processor The processor now detects memory accesses targeting PCIEXBAR and the processor converts that access to QPI configuration accesses BIOS must assign this address range such that it will not conflict with any other address ranges PCI Express Graphics Attach PEG The processor can be programmed to direct memory accesses to a PCI Express interface When addresses are within either of two ranges specified using registers in each PEG s configuration space The first range is controlled using the Memory Base Register MBASE and Memory Limit Register MLIMIT registers The second range is controlled using the Pre fetchable Memory Base PMBASE and Pre fetchable Memory Limit PMLIMIT registers Conceptually address decoding for each range follows the same basic concept The top 12 bits of the respective Memory Base and Memory Limit registers correspond to address bits A 31 20 of a memory address For the purpose of address decoding the processor assumes that address bits A 19 0 of the memory base are zero and that address bits A 19 0 of the memory limit address are F_FFFFh This forces each memory address range to be aligned to a 1MB bounda
283. e step and init freeze modes INIT_SPEED Current initialization speed 26 RO 1 Operational Speed Initialization 0 Slow Speed Initialization 25 RO PORT_RMT_ACK Port Remote ACK status 24 RO PORT_TX_RDY Port Tx Ready status 23 21 RV Reserved 20 16 RO RX_STATE Current state of the local Rx 15 13 RV Reserved 12 8 RO TX_STATE Current state of the local Tx 7 2 RV Reserved CALI BRATI ON_ DONE 1 RWIC 0 This bit indicates that calibration has been completed for the Intel QPI link LI NKUP_I DENTI FIER Link up identifier for the Intel QPI link 0 RW1C 0 Set to 0 during Default Reset Set to 1 when initialization completes and link enters LO Datasheet Volume 2 359 Intel QuickPath Architecture System Address Decode Register Description intel 360 Datasheet Volume 2
284. ecoded by hardware as all 1s The protected high memory base amp limit registers function as follows e in bits HAW N 1 specifies a protected low memory region of size 2 N 1 bytes Programming the protected high memory limit register with a value less than the protected high memory base register disables the protected high memory region B D F Type 0 2 0 GFXVTBAR Address Offset 78 7Fh Reset Value 0000000000000000h Access RO RW Reset ee Bit Attr Value Description 63 36 RO 0000000h Reserved Protected High Memory Limit PHML This field specifies the last host physical address of the DMA protected high 35 21 RW 0000h memory region in system memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width 20 0 RO 000000h Reserved Datasheet Volume 2 277 intel Processor Configuration Registers 2 18 19 I1QH_REG Invalidation Queue Head Register This register indicates the invalidation queue head The register is treated as reserved by implementations reporting Queued I nvalidation QI as not supported in the Extended Capability register B D F Type 0 2 0 GFXVTBAR Address Offset 80 87h Reset Value 0000000000000000h Access RO Reset re Bit Attr Value Description 00000000 Reserved 63 19 RO 0000h Queue Head QH Specifies the offset 128 bit aligned to the invalidation queue for the
285. ed in the MBASE1 MLIMIT1 PMBASE1 and PMLIMIT1 registers RW Ob O Access Enable I OAE All of device 1 s I O space is disabled Enable the I O address range defined in the OBASE1 and IOLI MIT1 registers l 0 1 Datasheet Volume 2 Processor Configuration Registers intel 2 10 4 PCI STS1 PCI Status Register This register reports the occurrence of error conditions associated with primary side of the virtual Host PCl Express bridge embedded within the processor B D F Type 0 1 0 PCI Address Offset 6 7h Reset Value 0010h Access RO RW1C Reset Sosa Bit Attr Value Description Detected Parity Error DPE Not Applicable or Implemented Hardwired to 0 Parity generating poisoned 15 RO Ob 4 TLPs is not supported on the primary side of this device we don t do error forwarding Signaled System Error SSE This bit is set when this Device sends an SERR due to detecting an 14 RW1C Ob ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the Command register is 1 Both received if enabled by BCTRL1 1 and internally detected error messages do not affect this field Received Master Abort Status RMAS 13 RO Ob Not Applicable or Implemented Hardwired to 0 The concept of a master abort does not exist on primary side of this device Received Target Abort Status RTAS 12 RO Ob Not Applicable or Implemented Hardwired to 0 The concept of a
286. ed by the SCI Error Command Register SCI on Thermal Sensor Trip The SCI and SERR must not be enabled at the same time for the thermal sensor event B D F Type 0 0 0 MCHBAR Address Offset 10E6h Reset Value 00h Access RW RO Reset BAPA Bit Attr Value Description 7 6 RO 00b Reserved SCI on Catastrophic Thermal Sensor Trip CATSCI 1 Does not mask the generation of an SCI DMI cycle on a catastrophic 5 RW Ob thermal sensor trip 0 Disable reporting of this condition using SCI messaging SCI on Hot Thermal Sensor Trip HOTSCI 4 RW Ob 1 Does not mask the generation of an SCI DMI cycle on a Hot thermal sensor trip Disable reporting of this condition using SCI messaging SCI on AUX 3 Thermal Sensor Trip AUX3SCI 3 RW Ob Does not mask the generation of an SCI DMI cycle on an Aux3 thermal sensor trip Disable reporting of this condition using SCI messaging SCI on AUX 2 Thermal Sensor Trip AUX2SCI 2 Ob Does not mask the generation of an SCI DMI cycle on an Aux2 thermal RW sensor trip Disable reporting of this condition using SCI messaging SCI on AUX 1 Thermal Sensor Trip AUX1SCI Does not mask the generation of an SCI DMI cycle on an Aux1 thermal 1 RW 0b sensor trip Disable reporting of this condition using SCI messaging SCI on AUX 0 Thermal Sensor Trip AUXOSCI 0 RW Ob Does not mask the generation of an SCI DMI cycle on an AuxO thermal sensor trip 0 Disable repor
287. ee eee e ee eeea ea eneae 35 2 2 9 I O Address Spate suiicits cide teed orinn a a A ieee ARAR 35 2 2 9 1 PCI Express I O Address Mapping ssessssirsssssrrrerrrsrinrrnsrrnrrrssrs 36 2 3 Configuration Process and ReEGIStePS ccc cetera teeter 37 2 3 1 Platform Configuration Structure ccc cece eect cere ee teen e neta teen e tata 37 2 4 Configuration MechaniSMS ccceceee eee ee eee eee teeter 38 2 4 1 Standard PCI Configuration Mechanism cceeeeeee eens tees eee ee ee eenaenen ees 38 2 4 2 PCI Express Enhanced Configuration Mechanism ccceeeeeeeeeee ee enna 39 2 4 3 Routing Configuration ACCESSES ccc eee ene e aetna 40 2 4 4 Internal Device Configuration ACCESSES ececeee cece nent nett teeta ee ee eee ne nae 41 2 4 5 Bridge Related Configuration ACCESSES eceeeee ee ee eee eee eee eae ee ne eaeas 42 2 4 5 1 PCI Express Configuration ACCESSES cccecceeeseeeeeeeneeneet eee eneenees 42 2 4 5 2 DMI Configuration ACCESSES ccee eect eee eee eee ee nena t nents 43 2 5 Processor Register Introduction cect eee ener nae 43 2 6 I O Mapped Registers sc isctcidicistdigaeedeied ieee disease rn eer REENE ise baduaensers 44 2 7 PCI Express Device 0 ReQiSteMSs ccc cece een rene te tee enen ea ene ees 45 2 7 1 VID Vendor Identification Register cc eens eect cents ee eee ee ee ee eae n ees 46 2 7 2 DID Device Identification R
288. een completed 1 Indicates that the device has transaction s pending including completions for any outstanding non posted requests for all used Traffic Classes RO Ob Reserved RW1C Ob Unsupported Request Detected URD When set this bit indicates that the Device received an Unsupported Request Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register Additionally the Non Fatal Error Detected bit or the Fatal Error Detected bit is set according to the setting of the Unsupported Request Error Severity bit In production systems setting the Fatal Error Detected bit is not an option as support for AER will not be reported RW1C Ob Fatal Error Detected FED When set this bit indicates that fatal error s were detected Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the uncorrectable error mask register RW1C Ob Non Fatal Error Detected NFED When set this bit indicates that non fatal error s were detected Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the uncorrectable err
289. eestndudatans egesesdareacaieasndcmianesieneewads 357 3 8 1 QPI _O_PH_CPR OPI PH CPR ciniartOnidvadsnseantenSotorennstintignetauimercinacste 357 3 8 2 QPI_O_PH_CTR OPI 3 PH CUR ccd csiceacaccaaicecnsatcenees onsbeniurcaiaiaeeddccaeanss 358 3 8 3 OPI OPH PUS OPI LPH PIS cxvisccnsnectsnanaswectaxsendvorsantacenininstnestundganslte 359 Datasheet Volume 2 Figures 2 1 System Address Rane saikvasdicieeciecietileciveeie iena i EAEE RENA oa anA els 18 2 2 DOS Legacy Address Range cccceeeeee cette eee A Ea E 19 2 3 Main Memory Address Range ssssssrsssrssrrererstrartrstru nt rre ttnn eruten urna nnnNE NER SEn EENEN ees 21 2 4 PCI Memory Address Range ssssssssssssrrsssrsrrtnsrrarttntrnntin ernn ntrnt ru nsrnannnn tenet ene 25 2 5 Case 1 Less than 4 GB of Physical Memory no remap sssssssssssrssrssrrrsrrrsrirrrersrs 29 2 6 Case 2 Greater than 4 GB of Physical MemMOry ccceeeeee eee ee nett eee teeta tana en enes 30 2 7 4 GB or Less of Physical Memory cce cece ene teeta e eee 31 2 8 Greater than 4 GB Remap Enabled ccc eee eee tenet ed 32 2 9 Memory Map to PCI Express Device Configuration Space ccceceeeeceee eee ee eee eeneaeenes 39 2 10 Processor Configuration Cycle Flow Chart cece centre ee teeters 41 Tables 2 1 Register Terminology circi eee eee eee nena nanan 15 222 SMMURCGQIONS onina n E are cte eterna A ONA E TERENA 35 2 3 Device Number Assignment fo
290. efore enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled When the LT CMD LOCK PMRC command is invoked this register is locked treated as RO When the LT CMD UNLOCK PMRC command is invoked this register is unlocked treated as RW Refer to the VTd specification for security considerations This register is always treated as RO for implementations not supporting protected low memory region PLMR field reported as 0 in the Capability register The alignment of the protected low memory region base depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding the most significant bit position with O in the value read back from the register Bits N 0 of this register are decoded by hardware as all Os Software must setup the protected low memory region below 4 GB The VTd specification describes the Protected Low Memory Limit register and hardware decoding of these registers B D F Type 0 2 0 GFXVTBAR Address Offset 68 6Bh Reset Value 00000000h Access RO RW Reset Peer Bit Attr Value Description Protected Low Memory Base PLMB 31 21 RW 000h This register specifies the base of protected low memory region in system memory 20 0 RO 000000h Reserved Datasheet Volume 2 Processor Configuration Registers t 2 18 16 PLMLI MIT_REG Protected Low Memory
291. egister ccececccee eect e tees eee e tenant ented 46 2 7 3 PCICMD PCI Command Register c cceceee cere eet nee eee ee nents 47 2 7 4 PCISTS PCI Status Register cc ccecce cece eee eee tees ee ee eaten EEE 48 2 7 5 RID Revision Identification 0 cece eee ee eee eee teen enee 49 2 7 6 CC Class Code ReGiSter cranco A eee a ene 49 2 7 7 MLT Master Latency Timer ReQiSter c cece eee etcetera eee ne ee ee eee ne ae 49 2 7 8 HDR Header Type ReGiSter cccceceee cece cece eee ee eee e eee eae a eens ee eee ne eaeas 50 2 7 9 SVID Subsystem Vendor Identification Register ccceeeeeeeeeee eee eae 50 2 7 10 SlD Subsystem Identification Register ccccc cece eee eee eee teeta eaten 51 2 7 11 PXPEPBAR PCI Express Egress Port Base Address Register 6 ee 51 Datasheet Volume 2 3 B NNNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNNNN NNNNNNNNNNKBPBBBRBHBHPB ODNDUBWNKFOWUDAYNRHDUABAWHN WWWWWWWNNNNNNNNNNEPRPEPEPEPEPEPEPHEPHOODYOUAWNE DNDUBWNFOUWOANAUVUBWNFOUWOAOANDUBWNFO MCHBAR MCH Memory Mapped Register Range Base Register 5 52 GGC Graphics Control Register c cece eee eee eee ee ee teeta eee e nannies 53 DEVEN Device Enable ReGiSter c ce eece eee e renee etree ee eee ee nena ea ene 54 DMIBAR Root Complex Register Range Base Address Register 5 55 LAC Legacy Access Control R QISter
292. egister OTLB_REG followed by a 64 bit Invalidation Address Register IVA_REG Implementations must support at least one OTLB invalidation unit NIVU 0 for each DMA remapping hardware unit in the platform The maximum number of IOTLB invalidation register units per DMA remapping hardware unit is 256 23 20 RO 0000b Maximum Handle Mask Value MHMV The value in this field indicates the maximum supported value for the Handle Mask HM field in the interrupt entry cache invalidation descriptor iec_inv_dsc This field is valid only when the IR field is reported as Set 19 18 RO 00b Reserved RO 010h Invalidation Unit Offset IVO This field specifies the location to the first OTLB invalidation unit relative to the register base address of this DMA remapping hardware unit If the register base address is X and the value reported in this field is Y the address for the first OTLB invalidation unit is calculated as X 16 Y If N is the value reported in NIU field the address for the last OTLB invalidation unit is calculated as X 16 Y 16 N RO Ob Snoop Control SC 0 Hardware does not support 1 setting of the SNP field in the page table entries 1 Hardware supports the 1 setting of the SNP field in the page table entries RO Ob Pass Through PT 0 Hardware does not support pass through translation type in context entries 1 Hardware supports pass through translatio
293. egister describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 0 0 PXPEPBAR Address Offset 4 7h Reset Value 0000 _0001h Access RO RWO A Reset PER Bit Attr Value Description 31 12 RO 00000h Reserved 11 10 RO 00b Port Arbitration Table Entry Size PATES l l l l This field indicates that the size of the Port Arbitration table entry is 1 bit Reference Clock RC 9 8 RO 00b This field indicates the reference clock for Virtual Channels that support time based WRR Port Arbitration 00 100 ns 7 RO Ob Reserved Low Priority Extended VC Count LPEVCC This field indicates the number of extended Virtual Channels in addition to 6 4 RO 000b the default VC belonging to the low priority VC LPVC group that has the lowest priority with respect to other VC resources in a strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration 3 RO Ob Reserved Extended VC Count EVCC 2 0 RW O 001b This field indicates the number of extended Virtual Channels in addition to the default VC supported by the device 2 9 2 EPPVCCTL EP Port VC Control Register B D F Type 0 0 0 PXPEPBAR Address Offset C Dh Reset Value 0000h Access RO RW A Reset eae Bit Attr Value Description 15 4 RO 000h Reserved VC Arbitration Select VCAS This field will be programmed by software to the only possible value as indi
294. egister determine if corresponding SERRs are generated when our device detects an error reported in this device s Device Status register or when an error message is received across the link Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register B D F Type 0 1 0 PCI Address Offset BC BDh Reset Value 0000h Access RW RO Reset eee Bit Attr Value Description 15 5 RO 000h Reserved Reserved for CRS Software Visibility Enable CSVE 4 RO Ob This bit when set enables the Root Port to return Configuration Request Retry Status CRS Completion Status to software Root Ports that do not implement this capability must hardwire this bit to Ob PME Interrupt Enable PMEIE 0 No interrupts are generated as a result of receiving PME messages 3 RW Ob 1 Enables interrupt generation upon receipt of a PME message as reflected in the PME Status bit of the Root Status Register A PME interrupt is also generated if the PME Status bit of the Root Status Register is set when this bit is set from a cleared state System Error on Fatal Error Enable SEFEE This bit controls the Root Complex s response to fatal errors 2 RW Ob 0 No SERR generated on receipt of fatal error 1 Indicates that an SERR should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself Syst
295. em Error on Non Fatal Uncorrectable Error Enable SENFUEE This bit controls the Root Complex s response to non fatal errors 1 RW Ob 0 No SERR generated on receipt of non fatal error 1 Indicates that an SERR should be generated if a non fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself System Error on Correctable Error Enable SECEE This bit controls the Root Complex s response to correctable errors 0 RW Ob 0 No SERR generated on receipt of correctable error 1 Indicates that an SERR should be generated if a correctable error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself Datasheet Volume 2 153 intel Processor Configuration Registers 2 10 46 RSTS Root Status Register This register provides information about PCI Express Root Complex specific parameters B D F Type 0 1 0 PCI Address Offset C0 C3h Reset Value 0000_0000h Access RO RW1C Reset pose Bit Attr Value Description 31 18 RO 0000h Reserved and Zero Reserved for future R WC S implementations software must use 0 for writes to bits PME Pending PMEP Indicates that another PME is pending when the PME Status bit is set When 17 RO Ob the PME Status bit is cleared by software the PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID
296. em Vendor Identification Register ccceeeeeeee eee eee 181 2 13 14 S ID2 Subsystem Identification Register aiseee 182 2 13 15 ROMADR Video BIOS ROM Base Address Register eceeeeeeeeeee tees 182 2 13 16 INTRPIN Interrupt Pin Register cece eee nent eee eee 182 2 13 17 MINGNT Minimum Grant Register cceceeeee cece cette ee eee teen eee e eee tae 183 2 13 18 MAXLAT Maximum Latency Register cceceee cece tence ee eee eee neta eee rrn 183 2 14 Device 2 1 0 ReGIStOrS ia cis cir seceecieavnenkadees OT EEE TTEA E ETE A 183 2 14 1 Index MMIO Address Register ccececee eee cece eect eee eet e en eee eee eene eae 184 2 14 2 Data MMIO Data Register cc cece cece eee ee te eee e neta teeta nern nne 184 2 15 DMI and PEG VCO VCp Remap R GISterS cece cece eee eee ee ee eee eee e nena 185 2 15 1 VER_REG Version ReGiSter i ccecccce ee te eee ee rene een ee ee enna nent eta teee tn ea ens 186 2 15 2 CAP_REG Capability Register cece ccee cece eee eee e eee ee eee eee eaten 187 2 15 3 ECAP_REG Extended Capability Register rererere 190 2 15 4 GCMD_REG Global Command ReGister cccceeeee eect e eee ee eee ee ea eane es 191 2 15 5 GSTS REG Global Status ReGiSter ccc eee eee ee eee ee eet esata ea eas 194 2 15 6 RTADDR_REG Root Entry Table Address RegiSter cceeeeeeeeeeeee ees 195 2 15 7 CCMD_REG Context Command
297. enn 172 2 12 19 DMILCTL DMI Link Control Register cccece cece teen eee eee eater ened 173 2 12 20 DMILSTS DMI Link Status Register c cece eee eee eee ee eee ea ed 173 PCI Device 2 Function 0 Registers cece neater need 174 2 13 1 VID2 Vendor Identification RegiSter ccc eee eee tenet ee eee tad 174 2 13 2 DID2 Device Identification Register cece eect eects ee eee ee tena rrn 175 2 13 3 PCICMD2 PCI Command Register cceee cece eee ee eee ee ee eee nena ea enees 175 2 13 4 PCISTS2 PCI Status Register cece cece eee iren DEn ES EE n aa 176 2 13 5 RID2 Revision Identification Register ccececee eee ee eee e ee ee ee eee nena enn 177 2 13 6 CC Class Code Registel susirinko na n EEEE 177 2 13 7 CLS Cache Line Size RegisSter cece eee eee eee teeta eaed 178 Datasheet Volume 2 2 13 8 MLT2 Master Latency Timer ReQiSter cceceeeceeee sees eee eeeee teen ene ees 178 2 13 9 HDR2 Header Type ReGiSter cece ee eee ee eee eee ee eee eee ee teeta sete teeta 178 2 13 10 GTTMMADR Graphics Translation Table Memory Mapped Range Address REGISSEN aana ca trate aE aaa tute pian ENEA NA EA AENEA 179 2 13 11 GMADR Graphics Memory Range Address Register 0 ececeeeeeeeee eee 180 2 13 12 OBAR I O Base Address Register cecceeee eee ee ee ee eee ee teat nena eae ne tenes 181 2 13 13 SVID2 Subsyst
298. ented Hardwired to 0 4 0 RO 00h Reserved Datasheet Volume 2 Processor Configuration Registers t 2 10 15 MBASE1 Memory Base Address Register This register controls the processor to PCI Express G non prefetchable memory access routing based on the following formula MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 1 0 PCI Address Offset 20 21h Reset Value FFFOh Access RW RO Reset ae Bit Attr Value Description Memory Address Base MBASE 15 4 RW FFFh This field corresponds to A 31 20 of the lower limit of the memory range that will be passed to PCI Express G 3 0 RO Oh Reserved Datasheet Volume 2 125 m t 1 Processor Configuration Registers 2 10 16 Note Note 126 MLI MIT1 Memory Limit Address Register This register controls the processor to PCI Express G non prefetchable memory access routing based on the following formula MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of
299. entries require explicit invalidation Refer to the VTd specification for more details on caching mode Hardware implementations are recommended to support operation corresponding to CM 0 188 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 8 Fh Reset Value 00C9008020630272h Access RO Reset fae Bit Attr Value Description Protected High Memory Region PHMR 0 Indicates protected high memory region not supported 6 RO 1b 1 Indicates protected high memory region is supported DMA remapping hardware implementations on Intel TXT platforms supporting main memory above 4 GB are required to support protected high memory region Protected Low Memory Region PLMR 0 Indicates protected low memory region not supported 5 RO 1b 1 Indicates protected low memory region is supported DMA remapping hardware implementations on Intel TXT platforms are required to support protected low memory region Required Write Buffer Flushing RWBF 0 Indicates no write buffer flushing needed to ensure changes to memory resident structures are visible to hardware 4 RO 1b 1 Indicates software must explicitly flush the write buffers through the Global Command register to ensure updates made to memory resident DMA remapping structures are visible to hardware Refer to the VTd specification for more details on write buffer flushing re
300. er B D F Type 0 2 0 GFXVTBAR Address Offset FFC FFFh Reset Value 4000_0000h Access RW L RW O RO Reset PEE Bit Attr Value Description DMA Remap Engine Policy Lock Down DMAR_LCKDN This register bit protects all the DMA remap engine specific policy 31 RW O Ob configuration registers Once this bit is set by software all the DMA remap engine registers within the range FOOh to FFCh will be read only This bit can only be clear through platform reset 30 RO 1b Cl VT Level 2 Cache allocation mode CI L2TLBMODE 1 Uniform replacement algorithm 29 RW L Ob Cl VT Level 2 Cache Disable CIL2TLBDIS This bit will disable caching of Level 2 HPA completions within Cl if set Cl VT Level 1 Cache Disable CIL1ITLBDIS This bit will disable caching of Level 1 HPA completions within Cl if set 28 RW L Ob 0 Level 1 IOTLB is enabled and will be used to cache level 1 page table translations 1 Level 1 IOTLB is disabled and will not be used to cache level 1 page table translation CI Remap Engine Policy Control CI R_CTL cic_scr_reserved_fault_en 27 RW L Ob 0 Default Hardware support s reserved field programming faults in root context and page translation structure that is fault code of Ah Bh Ch 1 Hardware ignores reserved field programming faults in the root context and page translation structure 26 5 RO Oh Reserved Level 1 Allocation Mode Selection LLALOCMODE 4 RW L Ob 0 E
301. er identifies the header layout of the configuration space No physical register exists at this location B D F Type 0 6 0 PCI Address Offset Eh Reset Value Olh Access RO z Reset iii Bit Attr Value Description Header Type Register HDR 7 0 RO Olh This field returns 01 to indicate that this is a single function device with bridge header layout 2 19 9 PBUSN6 Primary Bus Number Register This register identifies that this virtual Host PCl Express bridge is connected to PCI bus 0 B D F Type 0 6 0 PCI Address Offset 18h Reset Value 00h Access RO P Reset teas Bit Attr Value Description Primary Bus Number BUSN Configuration software typically programs this field with the number of the 7 0 RO 00h bus on the primary side of the bridge Since device 6 is an internal device and its primary bus is always 0 these bits are read only and are hardwired to 0 294 Datasheet Volume 2 Processor Configuration Registers intel 2 19 10 SBUSN6 Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the virtual bridge that is to PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G B D F Type 0 6 0 PCI Address Offset 19h Reset Value 00h Access RW Reset Beaks Bit Attr Value Description Secondary B
302. eration through the IRES field in the Global Status register There may be active interrupt requests in the platform when software updates this field Hardware must enable or disable interrupt remapping logic only at deterministic transaction boundaries so that any in flight interrupts are either subject to remapping or not at all Hardware implementations must drain any in flight interrupts requests queued in the Root Complex before completing the interrupt remapping enable command and reflecting the status of the command through the IRES field in the Global Status register The value returned on a read of this field is undefined 25 RO Ob 228 Datasheet Volume 2 Processor Configuration Registers Access B D F Type Address Offset Reset Value 0 0 0 DMIVC1REMAP 18 1Bh 00000000h W RO Bit Attr Reset Value Description 24 RO Ob Set Interrupt Remap Table Pointer SIRTP This field is valid only for implementations supporting interrupt remapping Software sets this field to set update the interrupt remapping table pointer used by hardware The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address register Hardware reports the status of the interrupt remapping table pointer set operation through the IRTPS field in the Global Status register The interrupt remap table pointer set operation must be performed before enabling or re enab
303. eration through the PRS field in this register Hardware implementations supporting DMA draining must drain any in flight translated DMA requests queued within the Root Complex before indicating the protected memory region as enabled through the PRS field 30 1 RO 00 00b Reserved Protected Region Status PRS This field indicates the status of protected memory region 0 RO Ob 0 Protected memory region s not enabled 1 Protected memory region s enabled 238 Datasheet Volume 2 Processor Configuration Registers t 2 16 15 PLMBASE_REG Protected Low Memory Base Register This register is used to set up the base address of DMA protected low memory region below 4 GB This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is treated as RO for implementations not supporting protected low memory region PLMR field reported as Clear in the Capability register The alignment of the protected low memory region base depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding the most significant bit position with O in the value read back from the register Bits N 0 of this register are decoded by hardware as all Os Software must setup the protected low memory region below 4 GB The VTd specification describes the Protected Low Memory Limit re
304. ermine priority and vector information B D F Type 0 6 0 PCI Address Offset 3Ch Reset Value 00h Access RW Reset dug Bit Attr Value Description Interrupt Connection INTCON This field is used to communicate interrupt line routing information 7 0 RW 00h BIOS Requirement POST software writes the routing information into this register as it initializes and configures the system The value indicates to which input of the system interrupt controller this device s interrupt pin is connected 2 19 23 INTRPIN6 Interrupt Pin Register This register specifies which interrupt pin this device uses B D F Type 0 6 0 PCI Address Offset 3Dh Reset Value Olh Access RO A Reset Bose Bit Attr Value Description Interrupt Pin INTPIN 7 0 RO Olh As a single function device the PCI Express device specifies INTA as its interrupt pin 01h INTA 2 19 24 BCTRL6 Bridge Control Register This register provides extensions to the PCICMD6 register that are specific to PCI PCI bridges The BCTRL provides additional control for the secondary interface that is PCI Express G as well as some bits that affect the overall behavior of the virtual Host PCI Express bridge embedded within GMCH such as VGA compatible address ranges mapping B D F Type 0 6 0 PCI Address Offset 3E 3Fh Reset Value 0000h Access RO RW Reset cere Bit Attr Value Descri
305. errrrrrsrrrrrn 331 2 20 6 VCORSTS VCO Resource Status RegiSter ssssssssirerrerrrsrrrrrrrrrrreeirr 332 2 21 Intel Trusted Execution Technology Intel TXT Specific Registers sece 332 2 21 1 TXT DID TXT Device ID Register sssssssssissressrrrriesrrntrrrnrnrrrrrrirerrnre 333 2 21 2 TXT DPR DMA Protected Range Register uecnesrrererr errereen 333 2 21 3 TXT PUBLIC KEY LOWER TXT Processor Public Key Hash Lower Half ReGIStCr ei siccceinicacisaedes bieetiedind ii eeesaneataiwabeeleaeeeietens 334 2 21 4 TXT PUBLIC KEY UPPER TXT Processor Public Key Hash Upper Half Register 1 226 caciscceenstcitevedteaeaneernessmev nents accent TATO 334 Intel QuickPath Architecture System Address Decode Register Description 335 3 1 Register Terminology visa sob dacsageteshelavi reuna Mehr EO EEDA OE PETEAR EEE 335 3 2 Platform Configuration StruUcCtUre s s ssssssrssrrtrissttn trint titar nutr rnnt nnti natnn urnatu tnni nna 337 3 3 Detailed Configuration Space MapS s sssssssersrrsrerserrrsrrerrtrerneransrnnrirsernnrerernnrern 338 3 4 PCI Standard Registersis cc ctesdstieeerudsaaatanncaeiiediets bavaapaemet eden 342 3 4 1 VID Vendor Identification Register ccceeceeeee eee eee ee nets nets teeta tannins 342 3 4 2 DID Device Identification Register cccccceceeeee ee ee eee e eee eee eee teen ene 342 3 4 3 RID Revision Identification ReQiSter cece eect eee tenes tees teenie ea ene
306. errupt Mode are required to implement this register h Software requirements for programming this register are described in the VTd specification Hardware implementations not supporting Queued Invalidations and Extended Interrupt Mode may treat this field as reserved 2 15 27 IRTA_REG Interrupt Remapping Table Address Register Register providing the base address of Interrupt remapping table This register is treated as reserved by implementations reporting Interrupt Remapping IR as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset B8 BFh Reset Value 0000000000000000h Access RW RO Reset E Bit Attr Value Description Interrupt Remapping Table Address IRTA 63 12 RW 00000000 This field points to the base interrupt remapping table 00000h Hardware ignores and not 63 HAW where HAW is the width Reads of this field returns last programmed to it 210 Datasheet Volume 2 Processor Configuration Registers intel 2 15 28 IVA_REG Invalidate Address Register This register provides the DMA address whose corresponding OTLB entry needs to be invalidated through the corresponding OTLB Invalidate register This register is a write only register Value returned on reads of this register is undefined There is an IVA_REG for each IOTLB Invalidation unit supported by hardware B D F Type Address Offset Reset Value Access
307. erved RO Ob 66 60MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 RO 1b Capabilities List CAPL Indicates that a capabilities list is present Hardwired to 1 RO Ob I NTA Status INTAS This bit indicates that an interrupt message is pending internally to the device Only PME and Hot Plug sources feed into this status bit not PCI INTA INTD assert and de assert messages The INTA Assertion Disable bit PCICMD6 10 has no effect on this bit Note that I NTA emulation interrupts received across the link are not reflected in this bit 2 0 RO 000b Reserved 292 Datasheet Volume 2 Processor Configuration Registers 2 19 5 2 19 6 intel RI D6 Revision Identification Register This register contains the revision number of the processor The Revision ID RID is a traditional 8 bit Read Only RO register located at offset 08h in the standard PCI header of every PCI PCI Express compatible device and function This register contains the revision number of Device 6 These bits are read only and writes to this register have no effect B D F Type 0 6 0 PCI Address Offset 8h Reset Value 08h Access RO Reset er Bit Attr Value Description Revision Identification Number RI D6 This is an 8 bit value that indicates the revision identification number for the 7 0 RO 08h Device 6 Refer to the Intel Core i5 600 and i3 500 D
308. escription 1 O Address Base I OBASE This field corresponds to A 15 12 of the I O addresses passed by bridge 1 to 7 4 RW Fh PCI Express G BIOS must not set this register to 00h otherwise OCF8h OCFCh accesses will be forwarded to the PCI Express hierarchy associated with this device 3 0 RO Oh Reserved I OLIMIT6 I O Limit Address Register This register controls the processor to PCI Express G I O access routing based on the following formula 10_BASE lt address lt IO_LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are assumed to be FFFh Thus the top of the defined I O address range will be at the top of a 4 KB aligned address block B D F Type 0 6 0 PCI Address Offset 1Dh Reset Value 00h Access RO RW Reset Pare Bit Attr Value Description I O Address Limit I OLI MIT This field corresponds to A 15 12 of the I O address limit of device 6 7 4 RW h 9 Devices between this upper limit and IOBASE6 will be passed to the PCI Express hierarchy associated with this device 3 0 RO Oh Reserved Datasheet Volume 2 Processor Configuration Registers intel 2 19 14 SSTS6 Secondary Status Register SSTS6 is a 16 bit status register that reports the occurrence of error conditions associated with secondary side that is PCI Express G side of the virtual PCI PCI bridge embedded within GMCH B
309. eset with a cold complete reset for PCI Express related bits a cold reset is Power Good Reset as defined in the PCI Express Base spec Additionally there is a Key bit which is marked RW K or RW L K that when set prohibits this bit field from being writable bit field becomes Read Only Volatile RW1C S Read Write 1 to Clear Sticky bit s These bits can be read Internal events may set this bit A software write of 1 clears sets to 0 the corresponding bit s and a write of 0 has no effect Bits are not cleared by warm reset but is reset with a cold complete reset for PCI Express related bits a cold reset is Power Good Reset as defined in the PCI Express Base spec RW K Read Write Key bit s These bits can be read and written by software Additionally this bit when set prohibits some other target bit field from being writable bit fields become Read Only RW L Read Write Lockable bit s These bits can be read and written by software Additionally there is a Key bit which is marked RW K or RW L K that when set prohibits this bit field from being writable bit field becomes Read Only RW L K Read Write Lockable Key bit s These bits can be read and written by software This bit when set prohibits some other bit field s from being writable bit fields become Read Only Additionally there is a Key bit which is marked RW K or RW L K that when set prohibits this bit field from being
310. esktop Processor Series and Intel Pentium Desktop Processor 6000 Series Specification Update for the value of the Revision ID Register CC6 Class Code Register This register identifies the basic function of the device a more specific sub class and a register specific programming interface B D F Type 0 6 0 PCI Address Offset 9 Bh Reset Value 060400h Access RO s Reset PEP Bit Attr Value Description Base Class Code BCC 23 16 RO 06h Indicates the base class code for this device This code has the value 06h indicating a Bridge device Sub Class Code SUBCC 15 8 RO 04h Indicates the sub class code for this device The code is 04h indicating a PCI to PCI Bridge Programming Interface PI Indicates the programming interface of this device This value does not 7 0 RO 00h specify a particular register set layout and provides no practical use for this device Datasheet Volume 2 293 Processor Configuration Registers intel 2 19 7 CL6 Cache Line Size Register B D F Type 0 6 0 PCI Address Offset Ch Reset Value 00h Access RW a Reset Paa Bit Attr Value Description Cache Line Size Scratch pad 7 0 RW 00h Implemented by PCI Express devices as a read write field for legacy compatibility purposes but has no impact on any PCI Express device functionality 2 19 8 HDR6 Header Type Register This regist
311. esponds to tPALL_RP REF to ACT Delayed C1sd_cr_rfsh_act 8 0 RW 00000000 This field indicates the minimum allowed spacing in DRAM clocks between i Ob REF and ACT commands to the same rank This field corresponds to tRFC in the DDR specification Datasheet Volume 2 89 intel Processor Configuration Registers 2 8 31 C1CYCTRKWR Channel 1 CYCTRK WR Register This register provides Channel 1 CYCTRK WR control B D F Type 0 0 0 MCHBAR Address Offset 656 657h Reset Value 0000h Access RW Reset er Bit Attr Value Description ACT To Write Delay C1sd_cr_act_wr 15 12 RW Oh This field indicates the minimum allowed spacing in DRAM clocks between the ACT and WRITE commands to the same rank bank This field corresponds to tRCD_wr in the DDR specification Same Rank Write To Write Delayed C1sd_cr_wrsr_wr 11 8 RW Oh This field indicates the minimum allowed spacing in DRAM clocks between two WRITE commands to the same rank Different Rank Write to Write Delay C1lsd_cr_wrdr_wr 7 4 RW Oh This field indicates the minimum allowed spacing in DRAM clocks between i two WRITE commands to different ranks This field corresponds to tWR_WR in the DDR specification READ To WRTE Delay C1sd_cr_rd_wr 3 0 RW Oh This field indicates the minimum allowed spacing in DRAM clocks between the READ and WRITE commands This field corresponds to tRD_WR 2 8 32 C1CYCTRKRD Channel 1
312. ess bits 31 2 for the interrupt request Software requirements for programming this register are described in the VTd specification 1 0 RO 00b Reserved 236 Datasheet Volume 2 Processor Configuration Registers intel 2 16 12 FEUADDR_REG Fault Event Upper Address Register This register specifies the interrupt message upper address The register is treated as reserved by implementations reporting Extended Interrupt Mode EIM as not supported in the Extended Capability register B D F Type 0 0 0 DMI VCLREMAP Address Offset 44 47h Reset Value 00000000h Access RO Reset caer Bit Attr Value Description Message Upper Address MUA Hardware implementations supporting Extended Interrupt Mode are required 00000000 to implement this register l l l l l 31 0 RO h Software requirements for programming this register are described in the VTd specification Hardware implementations not supporting Extended Interrupt Mode may treat this field as reserved 2 16 13 AFLOG_REG Advanced Fault Log Register This register specifies the base address of the memory resident fault log region The register is treated as reserved for implementations not supporting advanced translation fault logging AFL field reported as 0 in the Capability register B D F Type Address Offset Reset Value Access 0 0 0 DMI VCLREMAP 58 5Fh 0000000000000000h RO Bit Attr Reset Val
313. ess Offset 9 Bh Reset Value 060400h Access RO P Reset Pare Bit Attr Value Description Base Class Code BCC 23 16 RO 06h Indicates the base class code for this device This code has the value 06h indicating a Bridge device Sub Class Code SUBCC 15 8 RO 04h Indicates the sub class code for this device The code is 04h indicating a PCI to PCI Bridge Programming I nterface PI Indicates the programming interface of this device This value does not specify a particular register set layout and provides no practical use for this device 7 0 RO 00h 120 Datasheet Volume 2 Processor Configuration Registers 2 10 7 CL1 Cache Line Size Register B D F Type 0 1 0 PCI Address Offset Ch Reset Value 00h Access RW Bit Attr Sia Description Cache Line Size Scratch pad 7 0 RW 00h Implemented by PCI Express devices as a read write field for legacy i compatibility purposes but has no impact on any PCI Express device functionality 2 10 8 HDR1 Header Type Register This register identifies the header layout of the configuration space No physical register exists at this location B D F Type 0 1 0 PCI Address Offset Eh Reset Value Olh Access RO s R t or Bit Attr aE Description Header Type Register HDR 7 0 RO Olh Returns 01 to indicate that this is a single function device with bridge header layout 2 10 9 PBUSN
314. essfully exits the FC_INIT2 state BIOS Requirement Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Ob Reserved 2 12 8 DMI VC1RCAP DMI VC1 Resource Capability Register B D F Type 0 0 0 DMI BAR Address Offset 1C 1Fh Reset Value 00008001h Access RO Reset disk Bit Attr Value Description 31 24 RO 00h Reserved for Port Arbitration Table Offset 23 RO Ob Reserved 22 16 RO 00h Reserved for Maximum Time Slots Reject Snoop Transactions REJ SNPT 0 Transactions with or without the No Snoop bit set within the TLP header 15 RO 1b are allowed on this VC 1 When Set any transaction for which the No Snoop attribute is applicable but is not Set within the TLP Header will be rejected as an Unsupported Request 14 8 RO 00h Reserved Port Arbitration Capability PAC 7 0 RO Olh Having only bit 0 set indicates that the only supported arbitration scheme for this VC is non configurable hardware fixed Datasheet Volume 2 165 intel Processor Configuration Registers 2 12 9 DMIVC1RCTL1 DMI VC1 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 1 B D F Type 0 0 0 DMI BAR Address Offset 20 23h Reset Value 0100_0000h Access RO RW i Reset e
315. et isi Bit Type Value Description 31 22 RV 0 Reserved PAM6_HIENABLE OECOOOh OEFFFFh Attribute HIENABLE This field controls the steering of read and write cycles that address the BIOS area from OECOOOh to OEFFFFh 21 20 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 19 18 RV 0 Reserved PAM6_LOENABLE 0E8000h OEBFFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from OE8000h to OEBFFFh 17 16 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 15 14 RV 0 Reserved PAM5_HI ENABLE 0E4000h 0E7FFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OE4000h to OE7FFFh 13 12 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are service
316. etailed within the descriptions of the affected registers Datasheet Volume 2 65 Processor Configuration Registers intel 2 8 MCHBAR Registers Table 2 5 MCHBAR Register Address Map Sheet 1 of 2 ge og Register Symbol Register Name ita Access 111h CHDECMISC Channel Decode Misc 00h RW L RO 200 201h CODRBO Channel 0 DRAM Rank Boundary Address 0 0000h RW L RO 202 203h CODRB1 Channel 0 DRAM Rank Boundary Address 1 0000h RW L RO 204 205h CODRB2 Channel 0 DRAM Rank Boundary Address 2 0000h RO RW L 206 207h CODRB3 Channel 0 DRAM Rank Boundary Address 3 0000h RO RW L 208 209h CODRAO1 Channel 0 DRAM Rank 0 1 Attribute 0000h RW L 20A 20Bh CODRA23 Channel 0 DRAM Rank 2 3 Attribute 0000h RW L 24D 24Fh COWRDATACTRL Channel 0 Write Data Control 004111h RW 250 251h COCYCTRKPCHG Channel 0 CYCTRK PCHG 0000h RO RW 252 255h COCYCTRKACT Channel 0 CYCTRK ACT 0000_0000h RW RO 256 257h COCYCTRKWR Channel 0 CYCTRK WR 0000h RW 258 25Ah COCYCTRKRD Channel 0 CYCTRK READ 000000h RO RW 25B 25Ch COCYCTRKREFR_ Channel 0 CYCTRK REFR 0000h RO RW 265 266h COPWLRCTRL Channel 0 PWLRCTL 0000h RO RW 269 26Eh COREFRCTRL Channel 0 DRAM Refresh Control 21830000C RW RO 271h COJ EDEC Channel 0 J EDEC CTRL 00h RW RO 298 29Bh COODT Channel 0 ODT Matrix 0000_0000h RW RO 29C 29Fh COODTCTRL Channel 0 ODT Control 0000_0000h RW RO 2B
317. eue Resource Threshold DMI VCORDCTQRT This field provides a 1 based minimum threshold value used to throttle DMI VCO Read VT fetch When the number of free DMI VT Completion Tracking Queue entries equals or falls below the value programmed in this field DMI VCO Read VT fetch is throttled until the number of free DMI Completion 3 0 RW L Oh Tracking Queue entries rise above this threshold For example 0000 Throttle DMI VCO Read VT Fetch when there is no entry left 0001 Throttle DMI VCO Read VT Fetch when there is 1 or less entry left 0010 Throttle DMI VCO Read VT Fetch when there is 2 or less entry left 0011 Throttle DMI VCO Read VT Fetch when there is 3 or less entry left 0100 Throttle DMI VCO Read VT Fetch when there is 4 or less entry left 0101 1111 Reserved 2 15 32 VTFTCHARBCTL VCO VCp VTd Fetch Arbiter Control This register controls the relative grant count given to each of the DMI VCO DMI VC1 and PEG VCO VT fetch requests B D F Type 0 0 0 VCOPREMAP Address Offset F04 FO7h Reset Value 0000_FFFFh Access RW L P Reset ee Bit Attr Value Description 31 16 RW L 0000h Reserved PEG1 VCO VT Fetch Grant Count PEG1VCOGNTCNT 15 12 RW L Fh The arbiter will continue to grant PEG1 VCO VT fetch as long as the grant count value in this field is greater than zero PEG VCO VT Fetch Grant Count PEGVCOGNTCNT 11 8 RW L Fh The arbiter will continue to grant PEG VCO VT fetch as
318. fer flush operation This field is set by hardware when software sets the WBF field in the Global Command register This field is cleared by hardware when hardware completes the write buffer flushing operation 26 RO Ob Queued I nvalidation Enable Status QIES This field indicates queued invalidation enable status 0 queued invalidation is not enabled 1 queued invalidation is enabled 25 RO Ob Interrupt Remapping Enable Status I RES This field indicates the status of Interrupt remapping hardware 0 Interrupt remapping hardware is not enabled 1 Interrupt remapping hardware is enabled 24 RO Ob Interrupt Remapping Table Pointer Status I RTPS This field indicates the status of the interrupt remapping table pointer in hardware This field is cleared by hardware when software sets the SIRTP field in the Global Command register This field is Set by hardware when hardware completes the set interrupt remap table pointer operation using the value provided in the Interrupt Remapping Table Address register 194 Datasheet Volume 2 Processor Configuration Registers 7 B D F Type 0 0 0 VCOPREMAP Address Offset 1C 1Fh Reset Value 00000000h Access RO i Reset rane Bit Attr Value Description Compatibility Format Interrupt Status CFI S This field indicates the status of Compatibility format interrupts on Intel 64 implementations supporting interrupt remappin
319. ffset AA ABh Reset Value 0000h Access RO RW1C Reset ae Bit Attr Value Description 15 6 RO 000h Reserved and Zero For future R WC S implementations software must use 0 for writes to bits Transactions Pending TP 0 All pending transactions including completions for any outstanding non 5 RO Ob posted requests on any used virtual channel have been completed 1 Indicates that the device has transaction s pending including completions for any outstanding non posted requests for all used Traffic Classes 4 RO Ob Reserved Unsupported Request Detected URD When set this bit indicates that the Device received an Unsupported Request Errors are logged in this register regardless of whether error 3 RW1C Ob reporting is enabled or not in the Device Control Register Additionally the Non Fatal Error Detected bit or the Fatal Error Detected bit is set according to the setting of the Unsupported Request Error Severity bit In production systems setting the Fatal Error Detected bit is not an option as support for AER will not be reported Fatal Error Detected FED When set this bit indicates that fatal error s were detected Errors are 2 RW1C Ob logged in this register regardless of whether error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the uncorrectable error mask register Non Fatal
320. fication is not supported this bit must be hardwired to Ob Presence Detect Changed PDC 3 RW1C Ob A pulse indication that the inband presence detect state has changed This bit is set when the value reported in Presence Detect State is changed Datasheet Volume 2 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset BA BBh Reset Value 0000h Access RO RW1C 5 Reset PREA Bit Attr Value Description Reserved for MRL Sensor Changed MSC 2 RO Ob If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected If an MRL sensor is not implemented this bit must not be set Reserved for Power Fault Detected PFD If a Power Controller that supports power fault detection is implemented this bit is set when the Power Controller detects a power fault at this slot Note 1 RO Ob that depending on hardware capability it is possible that a power fault can be detected at any time independent of the Power Controller Control setting or the occupancy of the slot If power fault detection is not supported this bit must not be set Reserved for Attention Button Pressed ABP If an Attention Button is implemented this bit is set when the attention 0 RO Ob A it button is pressed If an Attention Button is not supported this bit must not be set Datasheet Volume 2 325 intel 2 19 44 326 Processor Configuration Registers RCTL
321. fset 108 10Fh Reset Value 0200000000000000h Access RW RO Reset Haza Bit Attr Value Description 56 50 RO 00h Reserved Drain Reads DR This field is ignored by hardware if the DRD field is reported as clear in the Capability register When DRD field is reported as set in the Capability register the following 49 RW Ob encodings are supported for this field 0 Hardware may complete the IOTLB invalidation without draining DMA read requests 1 Hardware must drain DMA read requests Refer VTd specification for description of DMA draining Drain Writes DW This field is ignored by hardware if the DWD field is reported as clear in the Capability register When DWD field is reported as set in the Capability register the following 48 RW Ob encodings are supported for this field 0 Hardware may complete the IOTLB invalidation without draining DMA write requests 1 Hardware must drain relevant translated DMA write requests Refer VTd specification for description of DMA draining Domain ID DID Indicates the ID of the domain whose IOTLB entries need to be selectively invalidated This field must be programmed by software for domain selective 47 32 RW 0000h and page selective invalidation requests i The Capability register reports the domain id width supported by hardware Software must ensure that the value written to this field is within this limit Hardware ignores and not implement bits 47 32 N where N is the supported domain id wi
322. fset 604 605h Reset Value 0000h Access RW L RO Reset EE Bit Attr Value Description 15 10 RO 000000b Reserved Channel 1 DRAM Rank Boundary Address 2 C1DRBA2 9 0 RW L 000h See CODRB2 register description This register is locked by Memory pre allocated for ME lock 86 Datasheet Volume 2 Processor Configuration Registers intel 2 8 25 C1DRB3 Channel 1 DRAM Rank Boundary Address 3 Register The operation of this register is detailed in the description for register CODRBO B D F Type 0 0 0 MCHBAR Address Offset 606 607h Reset Value 0000h Access RW L RO s Reset PREA Bit Attr Value Description 15 10 RO 000000b Reserved Channel 1 DRAM Rank Boundary Address 3 C1DRBA3 9 0 RW L 000h See CODRB3 register description This register is locked by Memory pre allocated for ME lock 2 8 26 C1DRA0O1 Channel 1 DRAM Rank 0 1 Attributes Register The operation of this register is detailed in the description for register CODRAO1 B D F Type 0 0 0 MCHBAR Address Offset 608 609h Reset Value 0000h Access RW L s Reset ar Bit Attr Value Description Channel 1 DRAM Rank 1 Attributes C1DRA1 15 8 RW L 00h See CODRAI register description This register is locked by Memory pre allocated for ME lock Channel 1 DRAM Rank 0 Attributes C1DRAO 7 0 RW L 00h See CODRAO register description This register is locked by Memory pre allocated for ME lock
323. g The interrupt message could be held pending due to interrupt mask IM field being set or due to other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field e Software servicing the WC field in the Invalidation Completion Status register RO 90900099 Reserved 208 Datasheet Volume 2 Processor Configuration Registers intel 2 15 24 IEDATA_REG Invalidation Event Data Register Register specifying the Invalidation Event interrupt message data This register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset A4 A7h Reset Value 00000000h Access RW Reset pois Bit Attr Value Description Extended Interrupt Message Data EI MD This field is valid only for implementations supporting 32 bit interrupt data 31 16 RW 0000h fields Hardware implementations supporting only 16 bit interrupt data treat this field as reserved Interrupt Message Data I MD 15 0 RW 0000h Data value in the interrupt request Software requirements for programming this register are descr
324. g The value reported in this field is applicable only when interrupt remapping is enabled and Legacy 23 RO Ob A 3 interrupt mode is active 0 Compatibility format interrupts are blocked 1 Compatibility format interrupts are processed as pass through bypassing interrupt remapping 22 0 RO 000000h Reserved 2 15 6 RTADDR_REG Root Entry Table Address Register This register provides the base address of root entry table B D F Type 0 0 0 VCOPREMAP Address Offset 20 27h Reset Value 0000000000000000h Access RW RO Reset rane Bit Attr Value Description Root table address RTA This register points to base of page aligned 4 KB sized root entry table in system memory Hardware may ignore and not implement bits 63 HAW 00000000 where HAW is the host address width 63 12 RW 00000h ies Software specifies the base address of the root entry table through this register and programs it in hardware through the SRTP field in the Global Command register Reads of this register returns value that was last programmed to it 11 0 RO 000h Reserved Datasheet Volume 2 195 intel Processor Configuration Registers 2 15 7 CCMD_REG Context Command Register Register to manage context cache The act of writing the uppermost byte of the CCMD_REG with ICC field set causes the hardware to perform the context cache invalidation Access B D F Type Add
325. g happens automatically on 0 to 1 transition just like when coming out of reset Writes to this bit are immediately reflected in the value read from the bit regardless of actual Link state Read Completion Boundary RCB Hardwired to 0 to indicate 64 byte 2 RO Ob Reserved FEDLB Active State PM ASPM This field controls the level of active state power management supported on the given link 00 Disabled 01 LOs Entry Supported 10 L1 Entry Enabled 11 LOs and L1 Entry Supported 1 0 RW 00b Note LOs Entry Enabled indicates the Transmitter entering LOs is supported The Receiver must be capable of entering LOs even when the field is disabled 00b ASPM L1 must be enabled by software in the Upstream component on a Link prior to enabling ASPM L1 in the Downstream component on that Link When disabling ASPM L1 software must disable ASPM L1 in the Downstream component on a Link prior to disabling ASPM L1 in the Upstream component on that Link ASPM L1 must only be enabled on the Downstream component if both components on a Link support ASPM L1 Datasheet Volume 2 145 intel Processor Configuration Registers 2 10 41 LSTS Link Status Register This register indicates PCI Express link status B D F Type Address Offset Reset Value Access 0 1 0 PCI B2 B3h 1000h RWI1C RO Bit Attr Reset Value Description 15 RW1C Ob Link Autonomous Bandwidth
326. g invalidation completion by clearing the ICC field The following are the encodings for the CAIG field 00 Reserved 60 59 RO Oh 01 Global Invalidation performed This could be in response to a global domain selective or device selective invalidation request 10 Domain selective invalidation performed using the domain id specified by software in the DID field This could be in response to a domain selective or device selective invalidation request 11 Device selective invalidation performed using the source id and domain id specified by software in the SID and FM fields This can only be in response to a device selective invalidation request 58 34 RO 00 00b Reserved Function Mask FM This field specifies which bits of the function number portion least significant three bits of the SID field to mask when performing device selective invalidations The following encodings are defined for this field 00 No bits in the SID field masked 33 32 WwW Oh 01 Mask most significant bit of function number in the SID field 10 Mask two most significant bit of function number in the SID field 11 Mask all three bits of function number in the SID field The device s specified through the FM and SID fields must correspond to the domain id specified in the DID field Value returned on read of this field is undefined Source ID SID This field indicates the source id of the device whose corresponding context 31
327. g software control of the power state bits Regardless of this bit the devices that transition from a D3hot to DO by a system or bus segment reset will return to the device state DO uniintialized with only PME context preserved if PME is supported and enabled Ob Reserved 134 1 0 RW 00b Power State PS This field indicates the current power state of this device and can be used to set the device into a new power state If software attempts to write an unsupported state to this field write operation must complete normally on the bus but the data is discarded and no state change occurs 00 DO 01 D1 Not supported in this device 10 D2 Not supported in this device 11 D3 Support of D3cold does not require any special action While in the D3hot state this device can only act as the target of PCI configuration transactions for power management control This device also cannot generate interrupts or respond to MMR cycles in the D3 state The device must return to the DO state in order to be fully functional When the Power State is other than DO the bridge will Master Abort that is not claim any downstream cycles with exception of type 0 config cycles Consequently these unclaimed cycles will go down DMI and come back up as Unsupported Requests which the MCH logs as Master Aborts in Device 0 PCISTS 13 There is no additional hardware functionality required to support these Power States
328. g to the temperature tables and then programming the computed offset into this register 2 8 42 RTR1 Relative Thermometer Read 1 Register This register contains the relative temperature B D F Type 0 0 0 MCHBAR Address Offset 1008h Reset Value 00h Access RO Bit Attr tied Description Relative Thermometer Reading RTR1 In Thermometer mode this register reports the relative temperature of the thermal sensor This field provides a two s complement value of the thermal 7 0 RO 00h sensor relative to TOF TR and HTPS can both vary between 0 and 255 RTR1 TR TOF See also TSS Thermometer mode Output Valid In the Analog mode the RTR field reports HTPS value 96 Datasheet Volume 2 Processor Configuration Registers intel 2 8 43 TSTTPA1 Thermal Sensor Temperature Trip Point Al Register This register sets the target values for some of the trip points in thermometer mode See also TST Direct DAC Connect Test Enable This register also reports the relative thermal sensor temperature See also TSTTPB B D F Type Address Offset Reset Value Access 0 0 0 MCHBAR 1010 1013h 0000_0000h RW L RO Bit Attr Reset Value Description 31 RW L Ob Lock Bit for Aux0 Aux1 Aux2 and Aux3 Trip points AUXLOCK This bit when written to a 1 locks the Aux x Trip point settings This lock is reversible The reversing procedure is the following seq
329. gister ccceeeeeeee cette ee eee e seen ee eana ead 149 2 10 44 SLOTSTS Slot Status ReGiSter ccc neater eae 151 2 10 45 RCTL Root Control Register cece ceceeeee eee enter ee eee eee nena teeta 153 2 10 46 RSTS Root Status Register cece eee nent eee earned 154 2 10 47 LCTL2 Link Control 2 Register ccc ete ee tenet eee teenie 154 2 10 48 LSTS2 Link Status 2 ReQISter eee teeta eee 155 2 10 49 PEGLC PCI Express Legacy Control Register ccceeeeeeee eee eee eee 155 Device 1 Extended Configuration ReQiSters ccccecee eect eee ee eee eee ee eater aed 156 2 11 1 PVCCAP1 Port VC Capability Register 1 00 0 cece cece ee eee ee eee eee ena eae 156 2 11 2 PVCCAP2 Port VC Capability Register 2 cceciceeeee eect tees este teeta ee eneee 157 2 11 3 PVCCTL Port VC Control ReQiSter cceceee cece cent eee e eee eee ee nanan 157 2 11 4 VCORCAP VCO Resource Capability Register ccecceeeee eee eee eee eee ed 158 2 11 5 VCORCTL VCO Resource Control RegiSter c cece cece ects ee ee ee eee eee ee ea ed 158 2 11 6 VCORSTS VCO Resource Status ReGiSter c cece eect eee etter 159 2 11 7 PEG_TC PCI Express Completion Timeout RegiSter ccceeeeee teeta 160 DMIIBAR REGISSEN S trigan aa e EEN E na tends te edin iv EA EENEN RES 161 2 12 1 DMIVCECH DMI Virtual Channel Enhanced Capability Register
330. gister Expansion ECN 2 10 36 DCAP Device Capabilities Register This register indicates PCI Express device capabilities B D F Type 0 1 0 PCI Address Offset A4 A7h Reset Value 00008000h Access RO z Reset Pe Bit Attr Value Description 31 16 RO 0000h Reserved Not Applicable or Implemented Hardwired to 0 Role Based Error Reporting RBER 15 RO 1b This bit indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1 1 specification 14 6 RO 000h Reserved Not Applicable or Implemented Hardwired to 0 5 RO Ob Extended Tag Field Supported ETFS Hardwired to indicate support for 5 bit Tags as a Requestor 4 3 RO 00b Phantom Functions Supported PFS Not Applicable or Implemented Hardwired to 0 Max Payload Size MPS 2 0 RO 000b Hardwired to indicate 128B max supported payload for Transaction Layer Packets TLP Datasheet Volume 2 139 Processor Configuration Registers intel 2 10 37 DCTL Device Control Register This register provides control for PCI Express device specific capabilities The error reporting enable bits are in reference to errors detected by this device not error messages received across the link The reporting of error messages ERR_CORR ERR_NONFATAL ERR_FATAL received by Root Port is controlled exclusively by Root Port Command Register B D F Type
331. gister and hardware decoding of these registers Software must not modify this register when protected memory regions are enabled PRS field Set in PMEN_REG B D F Type 0 0 0 DMI VC1REMAP Address Offset 68 6Bh Reset Value 00000000h Access RW RO Reset P Bit Attr Value Description Protected Low Memory Base PLMB 31 21 RW 000h This register specifies the base of protected low memory region in system memory 20 0 RO 000000h Reserved Datasheet Volume 2 239 m t i Processor Configuration Registers 2 16 16 240 PLMLI MIT_REG Protected Low Memory Limit Register This register is used to setup the limit address of DMA protected low memory region below 4 GB This register must be setup before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected low memory region PLMR field reported as 0 in the Capability register The alignment of the protected low memory region limit depends on the number of reserved bits N of this register Software may determine the value of N by writing all 1s to this register and finding most significant zero bit position with 0 in the value read back from the register Bits N 0 of the limit register is decoded by hardware as all 1s The Protected low memory base amp limit registers functions as follows Progra
332. global invalidation of the context cache and global invalidation of OTLB e If advanced fault logging supported setup fault log pointer through SFL field and enable advanced fault logging through EAFL field Refer to the VTd specification for detailed software requirements There may be active DMA requests in the platform when software updates this field Hardware must enable or disable remapping logic only at deterministic transaction boundaries so that any in flight transaction is either subject to remapping or not at all Hardware implementations supporting DMA draining must drain any in flight translated DMA read write requests queued within the root complex before completing the translation enable command and reflecting the status of the command through the TES field in the GSTS_REG Value returned on read of this field is undefined Datasheet Volume 2 261 Processor Configuration Registers B D F Type 0 2 0 GFXVTBAR Address Offset 18 1Bh Reset Value 00000000h Access W RO RW Reset Be Bit Attr Value Description Set Root Table Pointer SRTP Software sets this field to set update the root entry table pointer used by hardware The root entry table pointer is specified through the Root entry Table Address register Hardware reports the status of the root table pointer set operation through the RTPS field in the Global Status register The root table pointer set operation must be perfo
333. h Notification capability must hardwire this bit to Ob 20 RO Ob Data Link Layer Link Active Reporting Capable DLLLARC For a Downstream Port this bit must be set to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine For a hot plug capable Downstream Port as indicated by the Hot Plug Capable field of the Slot Capabilities register this bit must be set to 1b For Upstream Ports and components that do not support this optional capability this bit must be hardwired to Ob 19 RO Ob Surprise Down Error Reporting Capable SDERC For a Downstream Port this bit must be set to 1b if the component supports the optional capability of detecting and reporting a Surprise Down error condition For Upstream Ports and components that do not support this optional capability this bit must be hardwired to Ob 18 RO Ob Clock Power Management CPM A value of 1b in this bit indicates that the component tolerates the removal of any reference clock s when the link is in the L1 and L2 3 Ready link states A value of 0b indicates the component does not have this capability and that reference clock s must not be removed in these link states This capability is applicable only in form factors that support clock request CLKREQ capability For a multi function device each function indicates its capability independently Power Man
334. h PCI Express Virtual Channel 0 B D F Type 0 6 0 MMR Address Offset 114 117h Reset Value 800000FFh Access RO RW f Reset rogi Bit Attr Value Description 31 RO 1b VCO Enable VCOE For VCO this is hardwired to 1 and read only as VCO can never be disabled 30 27 RO Oh Reserved VCO ID VCOID 26 24 RO 000b Assigns a VC ID to the VC resource For VCO this is hardwired to 0 and read only 23 20 RO Oh Reserved Port Arbitration Select PAS This field configures the VC resource to provide a particular Port Arbitration service This field is valid for RCRBs Root Ports that support peer to peer 19 17 RW 000b traffic and Switch Ports but not for PCI Express Endpoint devices or Root Ports that do not support peer to peer traffic The permissible value of this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource 16 RO Ob Reserved Reserved for Load Port Arbitration Table 15 8 RO 00h Reserved TC VCO Map TCVCOM Indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 7 is 7 1 RW 7Fh set in this field TC7 is mapped to this VC resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no ne
335. h RO 1006h TR1 Thermometer Read 1 FFh RO 1007h TOF1 Thermometer Offset 1 00h RW 1008h RTR1 Relative Thermometer Read 1 00h RO 1010 1013h TSTTPA1 Thermal Sensor Temperature Trip Point A1 0000_0000h RW L RO 1014 1017h TSTTPB1 Thermal Sensor Temperature Trip Point B1 0000_0000h RW L 1018 1019h TS1OBITMCTRL Thermal Sensor 10 bit Mode Control 0000h RW L 101Ch HWTHROTCTRL1 Hardware Throttle Control 1 00h RWE RO 101E 101Fh TIS1 Thermal Interrupt Status 1 0000h RO RW1C 1070h TERATE Thermometer Mode Enable and Rate 00h RO RW 10E4h TERRCMD Thermal Error Command 00h RO RW 10E5h TSMICMD Thermal SMI Command 00h RO RW 10E6h TSCICMD Thermal SCI Command 00h RW RO 10E7h TINTRCMD Thermal INTR Command 00h RO RW 10EC 10EDh EXTTSCS External Thermal Sensor Control and Status 0000h RO RWO 1300 13FFh RSVD Reserved Oh RO 2C20 2C22h DDRMPLL1 DDR PLL BIOS 000000h RO RW Datasheet Volume 2 67 Processor Configuration Registers intel 2 8 1 CSZMAP Channel Size Mapping Register This register indicates the total memory that is mapped to Interleaved and Asymmetric operation respectively 1 MB granularity used for Channel address decode B D F Type 0 0 0 MCHBAR Address Offset 100 107h Reset Value 0000_0000_0000_0000h Access RW Reset see Bit Attr Value Description 63 48 RO Oh Reserved 2 Channel Size 2CHSZ This register indicates the total memory that is mapped to 2 channel 47 32 RW L 0000h operation 1 MB granular
336. hat may be populated in the system Since it is difficult to relocate an interrupt controller using plug and play software fixed address decode regions have been allocated for them Processor accesses to the default OAPIC region FECO_0000h to FEC7_FFFFh are always forwarded to DMI The processor optionally supports additional O APICs behind the PCI Express Graphics port When enabled using the PCI Express Configuration register Device 1 Offset 200h and Device 6 Offset 200h the PCI Express port s will positively decode a subset of the APIC configuration space Specifically e Device 6 can be enabled to claim FEC8_0000h thru FECB_FFFFh e Device 1 can be enabled to claim FECC_0000h thru FECF_FFFFh Memory requests to this range would then be forwarded to the PCI Express port This mode is intended for the entry Workstation SKU of the processor and would be disabled in typical Desktop systems When disabled any access within entire APIC Configuration space FECO_0000h to FECF_FFFFh is forwarded to DMI MSI Interrupt Memory Space FEEO_ 0000 FEEF_FFFF Any PCI Express or DMI device may issue a Memory Write to OFEEx_xxxxh This Memory Write cycle does not go to DRAM The processor will forward this Memory Write along with the data to the processor as a QPI Interrupt Message Transaction This interrupt message will be delivered to the processor as an IntPhysical or IntLogical message High BIOS Area For security reasons
337. hat was last programmed to it Fault Log Size FLS This field specifies the size of the fault log region pointed to by the FLA field 11 9 RO 000b The size of the fault log region is 2 X 4KB where X is the value programmed in this register When implemented reads of this field return the value that was last programmed to it 8 0 RO 000h Reserved Datasheet Volume 2 Processor Configuration Registers intel 2 18 14 PMEN_REG Protected Memory Enable Register This register enables the DMA protected memory regions set up through the PLMBASE PLMLIMT PHMBASE PHMLIMIT registers This register is always treated as RO 0 for implementations not supporting protected memory regions PLMR and PHMR fields reported as 0 in the Capability register Protected memory regions may be used by software to securely initialize remapping structures in memory B D F Type 0 2 0 GFXVTBAR Address Offset 64 67h Reset Value 00000000h Access RW RO Reset Saad Bit Attr Value Description Enable Protected Memory Region EPM This field controls DMA accesses to the protected low memory and protected high memory regions 0 DMA accesses to protected memory regions are handled as follows If DMA remapping is not enabled DMA requests including those to protected regions are not blocked If DMA remapping is enabled DMA requests are translated per the programming of the DMA remapping structu
338. he Global Status register Refer to the VTd specification for details on Compatibility Format interrupt requests The value returned on a read of this field is undefined This field is not implemented RO 000000h Reserved Datasheet Volume 2 229 intel 2 16 5 230 Processor Configuration Registers GSTS_ REG Global Status Register This register reports general DMA remapping hardware status B D F Type 0 0 0 DMIVCLREMAP Address Offset 1C 1Fh Reset Value 00000000h Access RO Reset Poe Bit Attr Value Description Translation Enable Status TES 31 RO Ob This field indicates the status of DMA remapping hardware 0 DMA remapping hardware is not enabled 1 DMA remapping hardware is enabled Root Table Pointer Status RTPS This field indicates the status of the root table pointer in hardware 30 RO Ob This field is cleared by hardware when software sets the SRTP field in the Global Command register This field is set by hardware when hardware completes the set root table pointer operation using the value provided in the Root Entry Table Address register Fault Log Status FLS This field is cleared by hardware when software sets the SFL field in the 29 RO Ob Global Command register This field is set by hardware when hardware completes the set fault log pointer operation using the value provided in the Advanced Fault Log register
339. he IAIG field Software must not submit another invalidation request through this register while the IVT field is Set nor update the associated I nvalidate Address register Software must not submit OTLB invalidation requests when there is a context cache invalidation request pending at this remapping hardware unit Refer to the VTd specification for software programming requirements Hardware implementations reporting a write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flushing before invalidating the OTLB Refer to the VTd specification for write buffer flushing requirements 62 60 RW 000b IOTLB I nvalidation Request Granularity 11 RG When requesting hardware to invalidate the OTLB by setting the IVT field software writes the requested invalidation granularity through this field The following are the encodings for the field 000 Reserved 001 Global invalidation request 010 Domain selective invalidation request The target domain id must be specified in the DID field 011 Page selective invalidation request The target address mask and invalidation hint must be specified in the Invalidate Address register and the domain id must be provided in the DID field 100 111 Reserved Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalid
340. he PPF field was set by hardware Valid values for this field are from O to N where N is the value reported through NFR field in the Capability register The value read from this field is undefined when the PPF field is clear RO 0b Reserved RWIC S Ob Invalidation Time out Error ITE Hardware detected a Device OTLB invalidation completion time out At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting Device OTLBs implement this bit as reserved RW1C S Ob Invalidation Completion Error ICE Hardware received an unexpected or invalid Device OTLB invalidation completion This could be due to either an invalid ITag or invalid source id in an invalidation completion response At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting Device OTLBs implement this bit as reserved RW1C S Ob Invalidation Queue Error 1QE Hardware detected an error associated with the invalidation queue This could be due to either a hardware error while fetching a descriptor from the invalidation queue or hardware detecting an erroneous or invalid descriptor in the invalidation queue At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting queued invalid
341. he VC resource 16 8 RO 000h Reserved Traffic Class Virtual Channel Map TCVCM Indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 7 is set in this field TC7 is mapped to this VC 7 1 RW 00h resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link BIOS Requirement Program this field including bit 0 with the value 00100010b 22h which maps TC1 and TC5 to VC1 0 RO Ob Traffic Class 0 Virtual Channel 1 Map TCOVC1M Traffic Class 0 is always routed to VCO 166 Datasheet Volume 2 Processor Configuration Registers intel 2 12 10 DMIVC1RSTS DMI VC1 Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 0 0 DMI BAR Address Offset 26 27h Reset Value 0002h Access RO P Reset aoai Bit Attr Value Description 15 2 RO 0000h Reserved Virtual Channel 1 Negotiation Pending VC1NP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling Software may use this bit when enabling or disabling the VC This bit 1 RO 1b indicates the status of the process
342. he fault log region pointed by the FLA field 11 9 RO Oh The size of the fault log region is 2X 4KB where X is the value programmed in this register When implemented reads of this field returns value that was last programmed to it 8 2 RO 00h Reserved Advanced Pending Fault APF When this field is clear hardware sets this field When the first fault record at 1 RO Oh index 0 is written to a fault log At this time a fault event is generated based on the programming of the Fault Event Control register Software writing 1 to this field clears it Advanced Fault Overflow AFO 0 RO Oh Hardware sets this field to indicate advanced fault log overflow condition Software writing 1 to this field clears it Datasheet Volume 2 201 intel 2 15 14 202 Processor Configuration Registers PMEM_REG Protected Memory Enable Register This register enables the DMA protected memory regions setup through the PLMBASE PLMLIMT PHMBASE PHMLIMIT registers When LT CMD LOCK PMRC command is invoked this register is locked treated RO When LT CMD UNLOCK PMRC command is invoked this register is unlocked treated RW This register is always treated as RO 0 for implementations not supporting protected memory regions PLMR and PHMR fields reported as 0 in the Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 64 67h Reset Value 00000000h Access RW RO j Reset E Bit Attr Value Descr
343. he invalidation has completed Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flush before invalidating the context cache Refer to the VTd specification for write buffer flushing requirements 62 61 RW 00b Context I nvalidation Request Granularity CI RG Software provides the requested invalidation granularity through this field when setting the ICC field Following are the encodings for the CIRG field 00 Reserved 01 Global I nvalidation request 10 Domain selective invalidation request The target domain id must be specified in the DID field 11 Device selective invalidation request The target source id s must be specified through the SID and FM fields and the domain id that was programmed in the context entry for these device s must be provided in the DID field Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalidation request by clearing the ICC field At this time hardware also indicates the granularity at which the actual invalidation was performed through the CAIG field 232 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 DMI VC1REMAP Address Offset 28 2Fh Reset Value 0000000000000000h Access RW SC RW RO W i Reset rar
344. he processor Device 0 and 2 Refer to the Intel Core i5 600 and i3 i 500 Desktop Processor Series and Intel Pentium Desktop Processor 6000 Series Specification Update for the value of the Revision ID Register Datasheet Volume 2 343 intel 3 4 4 344 Intel QuickPath Architecture System Address Decode Register Description CCR Class Code Register This register contains the Class Code for the device Writes to this register have no effect Device o Function 0 1 Offset 09h Device 2 Function 0 1 Offset 09h Bit Type ti Description Base Class 23 16 RO 06h This field indicates the general device category For the processor this field is hard wired to 06h indicating it is a Bridge Device Sub Class 15 8 RO 0 This field qualifies the Base Class providing a more detailed specification g of the device function For all devices the default is 00h indicating Host Bridge Register Level Programming I nterface This field identifies a specific programming interface if any that device 7 0 RO 0 independent software can use to interact with the device There are no such interfaces defined for Host Bridge types and this field is hard wired to 00h Datasheet Volume 2 Intel QuickPath Architecture System Address Decode Register Description 7 3 4 5 3 4 6 HDR Header Type Register This register identifies the header layout of the configurati
345. heet Volume 2 137 Processor Configuration Registers intel 2 10 32 MA Message Address Register 2 10 33 MD Message Data Register B D F Type 0 1 0 PCI Address Offset 98 99h Reset Value 0000h Access RW Reset Eae Bit Attr Value Description Message Data MD Base message data pattern assigned by system software and used to handle 15 0 RW 0000h an MSI from the device l l l l When the device must generate an interrupt request it writes a 32 bit value to the memory address specified in the MA register The upper 16 bits are always set to 0 The lower 16 bits are supplied by this register B D F Type 0 1 0 PCI Address Offset 94 97h Reset Value 0000_0000h Access RW RO Reset PEET Bit Attr Value Description Message Address MA 31 2 RW 0000 _000 This field is used by system software to assign an MSI address to the device oR The device handles an MSI by writing the padded contents of the MD register to this address Force DWord Align FDWA 1 0 RO 00b Hardwired to 0 so that addresses assigned by system software are always aligned on a dword address boundary 2 10 34 PEG_CAPL PCI Express G Capability List Register This register enumerates the PCI Express capability structure 138 B D F Type 0 1 0 PCI Address Offset A0 Alh Reset Value 0010h Access RO Reset Pa Bit Attr Value Description Pointer to Next Capa
346. hen set to 1b this bit enables software notification on an attention button pressed event Datasheet Volume 2 Processor Configuration Registers 2 10 44 SLOTSTS Slot Status Register Note Hot Plug is not supported on the platform B D F Type 0 1 0 PCI Address Offset BA BBh Reset Value 0000h Access RO RW1C 5 Reset PEA Bit Attr Value Description i Reserved and Zero Reserved for future R WC S implementations software 15 9 RO 0000000b must use 0 for writes to bits Reserved for Data Link Layer State Changed DLLSC This bit is set when the value reported in the Data Link Layer Link Active field 8 RO Ob of the Link Status register is changed In response to a Data Link Layer State Changed event software must read the Data Link Layer Link Active field of the Link Status register to determine if the link is active before initiating configuration cycles to the hot plugged device Reserved for Electromechanical I nterlock Status EIS If an Electromechanical Interlock is implemented this bit indicates the 7 RO Ob current status of the Electromechanical Interlock Defined encodings are 0 Electromechanical Interlock Disengaged 1 Electromechanical Interlock Engaged Presence Detect State PDS This bit indicates the presence of an adapter in the slot reflected by the logical OR of the Physical Layer in band presence detect mechanism and if present any out of band presence detect me
347. her downstream PCI bus or PCI Express link Configuration accesses that are forwarded to the PCH but remain unclaimed by any device or bridge will result in a master abort Processor Register I ntroduction The processor contains two sets of software accessible registers accessed using the Host processor I O address space Control registers and internal configuration registers e Control registers are I O mapped into the processor I O space which control access to PCI and PCI Express configuration space see section entitled O Mapped Registers e Internal configuration registers residing within the processor are partitioned into three logical device register sets logical since they reside within a single physical device The first register set is dedicated to Host Bridge functionality that is DRAM configuration other chip set operating parameters and optional features The second register block is dedicated to Host PCI Express Bridge functions controls PCI Express interface configurations and operating parameters The third register block is for the internal graphics functions The processor internal registers 1 O Mapped Configuration and PCI Express Extended Configuration registers are accessible by the Host processor The registers that reside within the lower 256 bytes of each device can be accessed as Byte Word 16 bit or DWord 32 bit quantities with the exception of CONFIG_ADDRESS which can only be accesse
348. i Reset paci Bit Attr Value Description 15 11 RO 00000b Reserved Write To PRE Delayed C1sd_cr_wr_pchg 10 6 RW 00000b This field indicates the minimum allowed spacing in DRAM clocks between the WRITE and PRE commands to the same rank bank This field corresponds to tWR in the DDR Specification READ To PRE Delayed C1sd_cr_rd_pchg 5 2 RW 0000b_ This field indicates the minimum allowed spacing in DRAM clocks between the READ and PRE commands to the same rank bank PRE To PRE Delayed C1sd_cr_pchg_pchg 1 0 RW 00b This field indicates the minimum allowed spacing in DRAM clocks between two PRE commands to the same rank 88 Datasheet Volume 2 Processor Configuration Registers intel 2 8 30 C1CYCTRKACT Channel 1 CYCTRK ACT Register This register provides Channel 1 CYCTRK ACT control B D F Type 0 0 0 MCHBAR Address Offset 652 655h Reset Value 0000_0000h Access RW RO Reset oer Bit Attr Value Description 31 30 RO Oh Reserved FAW Windowcnt Bug Fix Disable FAWWBFD This bit disables the CYCTRK FAW windowcnt bug fix 29 RW Ob 1 Disable CYCTRK FAW windowcnt bug fix 0 Enable CYCTRK FAW windowcnt bug fix C1sd_cr_cyctrk_faw_windowcnt_fix_disable FAW Phase Bug Fix Disable FAWPBFD This bit disables the CYCTRK FAW phase indicator bug fix 28 RW Ob 1 Disable CYCTRK FAW phase indicator bug fix 0 Enable CYCTRK FAW phase indicator bug fix C1s
349. ibed in the VTd specification 2 15 25 I EADDR_REG I nvalidation Event Address Register This register specifies the Invalidation Event Interrupt message address This register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset A8 ABh Reset Value 00000000h Access RW RO Reset Peer Bit Attr Value Description Message address MA 00000000 When fault events are enabled the contents of this register specify the 31 2 RW h DWORD aligned address bits 31 2 for the interrupt request Software requirements for programming this register are described in the VTd specification 1 0 RO 00b Reserved Datasheet Volume 2 209 intel Processor Configuration Registers 2 15 26 I EUADDR_REG Invalidation Event Upper Address Register This register specifies the Invalidation Event interrupt message upper address This register is treated as reserved by implementations reporting both Queued I nvalidation QI and Extended Interrupt Mode EIM as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset AC AFh Reset Value 00000000h Access RW Reset ea Bit Attr Value Description Message Upper Address MUA Hardware implementations supporting Queued I nvalidations and Extended 31 0 RW 00000000 Int
350. ication compliance The processor locates MMIO space above 4 GB using these registers Datasheet Volume 2 33 m t 1 Processor Configuration Registers 2 2 6 1 Note 34 Graphics Memory Address Ranges The processor can be programmed to direct memory accesses to IGD when addresses are within any of five ranges specified using registers in the processor Device 2 configuration space 1 The Graphics Memory Aperture Base Register GMADR is used to access graphics memory allocated using the graphics translation table 2 The Graphics Translation Table Base Register GTTADR is used to access the translation table and graphics control registers 3 This is part of GTTMMADR register These ranges can reside above the Top of Low DRAM and below High BIOS and APIC address ranges They MUST reside above the top of memory TOLUD and below 4 GB so they do not steal any physical DRAM memory space Alternatively these ranges can reside above 4 GB similar to other BARs which are larger than 32 bits in size GMADR is a Prefetchable range in order to apply USWC attribute from the processor point of view to that range The USWC attribute is used by the processor for write combining 1 OBAR Mapped Access to Device 2 MMIO Space Device 2 integrated graphics device contains an OBAR register If Device 2 is enabled then IGD registers or the GTT table can be accessed using this OBAR The IOBAR is composed of an index register and a dat
351. ication when Data Link Layer Link Active field 12 RO Ob is changed If the Data Link Layer Link Active capability is not implemented this bit is permitted to be read only with a value of Ob Reserved for Electromechanical I nterlock Control EIC 11 RO 0b If an Electromechanical Interlock is implemented a write of 1b to this field causes the state of the interlock to toggle A write of Ob to this field has no effect A read to this register always returns a 0 Reserved for Power Controller Control PCC If a Power Controller is implemented this field when written sets the power state of the slot per the defined encodings Reads of this field must reflect the value from the latest write even if the corresponding hotplug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined Depending on the form factor the power is turned on off either to the slot or within the adapter Note that in some cases the power controller may 10 RO Ob autonomously remove slot power or not respond to a power up request based on a detected fault condition independent of the Power Controller Control setting The defined encodings are Ob Power On 1b Power Off If the Power Controller Implemented field in the Slot Capabilities register is set to Ob then writes to this field have no effect and the read value of this field is undefined Reserved Power Indicator Control PIC
352. ice 2 to PCI Express Device 1 and or to the DMI Interface The appropriate mapping depends on which devices are enabled and the programming of the VGA steering bits Based on the VGA steering bits priority for VGA mapping is constant The processor always decodes internally mapped devices first Internal to the processor decode priority is 1 IGD 2 PCI Express 3 DMI Interface subtractive Datasheet Volume 2 19 m t l Processor Configuration Registers 2 2 1 3 20 Non SMM mode processor accesses to this range are considered to be to the Video Buffer Area as described above The processor will route these accesses on the non coherent NCS or NCB channels The processor always positively decodes internally mapped devices namely the IGD and PCI Express Subsequent decoding of regions mapped to PCI Express or the DMI Interface depends on the Legacy VGA configuration bits VGA Enable and MDAP This region is also the default for SMM space Compatible SMRAM Address Range 000A_0000h OOOB_FFFFh Unlike FSB platforms the Intel Core i5 600 i3 500 Desktop processor series and Intel Pentium desktop processor 6000 series see no SMM indication with processor accesses When compatible SMM space is enabled SMM mode processor accesses to this range route to physical system DRAM at 000A_0000h 000B_FFFFh The processor performs the decode and routes the access to physical system DRAM In other words an SMM mod
353. idth Notification capability must hardwire this bit to Ob Link Bandwidth Management Interrupt Enable LBMIE When Set this bit enables the generation of an interrupt to indicate that the 10 RW Ob Link Bandwidth Management Status bit has been Set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Hardware Autonomous Width Disable HAWD When Set this bit disables hardware from changing the Link width for 9 RW Ob reasons other than attempting to correct unreliable Link operation by reducing Link width Devices that do not implement the ability autonomously to change Link width are permitted to hardwire this bit to Ob Enable Clock Power Management ECPM Applicable only for form factors that support a Clock Request CLKREQ mechanism this enable functions as follows 0 Clock power management is disabled and device must hold CLKREQ signal low 8 RO Ob 1 When this bit is set to 1 the device is permitted to use CLKREQ signal to power manage link clock according to protocol defined in appropriate form factor specification Components that do not support Clock Power Management as indicated by a Ob value in the Clock Power Management bit of the Link Capabilities Register must hardwire this bit to Ob Extended Synch ES 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state a
354. ies this linked list item capability structure as being for SSID SSVID registers in a PCI to PCI Bridge SS Subsystem ID and Subsystem Vendor ID Register System BIOS can be used as the mechanism for loading the SSID SVID values These values must be preserved through power management transitions and a hardware reset B D F Type 0 6 0 PCI Address Offset 8C 8Fh Reset Value 00008086h Access RW O A Reset ae Bit Attr Value Description Subsystem ID SSID 31 16 RW O 0000h This field identifies the particular subsystem and is assigned by the vendor Subsystem Vendor ID SSVID 15 0 RW O 8086h This field identifies the manufacturer of the subsystem and is the same as the vendor ID which is assigned by the PCI Special Interest Group Datasheet Volume 2 Processor Configuration Registers intel 2 19 29 MSI_CAPID Message Signaled Interrupts Capability I D Register When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item a message to a predefined memory address The reporting of the existence of this capability can be disabled by setting MSICH CAPL O 7Fh In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express capability B D F Type 0 6 0 PCI Address Offset 90 91h Reset Value A005h Access
355. if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined 9 8 RO 00b 00 Reserved 01 On 10 Blink 11 Off If the Power Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b Datasheet Volume 2 149 150 Processor Configuration Registers B D F Type 0 1 0 PCI Address Offset B8 B9h Reset Value 0000h Access RO RW i Reset Bee Bit Attr Value Description Reserved for Attention I ndicator Control AIC If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state Reads of this field must reflect the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined If the indicator is electrically controlled by chassis the indicator is controlled directly by the downstream port through implementation specific 7 6 RO 00b mechanisms 00 Reserved 01 On 10 Blink 11 Off If the Attention Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b Reserved for Hot plug I nterrupt Enable HPIE When set to 1b this bit
356. in the Capability register the following encodings are supported for this field 0 Hardware may complete the OTLB invalidation without draining any 48 RW 00h translated DMA writes that are queued in the root complex for processing 1 Hardware must drain all relevant translated DMA writes that are queued in the root complex before indicating OTLB invalidation completion to software A DMA write request to system memory is defined as drained when the effects of the write is visible to the processor accesses to all addresses targeted by the DMA write Domain ID DID This field indicates the ID of the domain whose I OTLB entries needs to be selectively invalidated This field must be programmed by software for domain selective domainpage selective and device page selective 47 32 RW 0000h invalidation requests The Capability register reports the domain id width supported by hardware Software must ensure that the value written to this field is within this limit Hardware may ignore and not implement bits 47 32 N where N is the supported domain id width reported in the capability register 31 0 RO 00000000h Reserved Datasheet Volume 2 213 intel Processor Configuration Registers 2 15 30 FRCD_REG Fault Recording Registers This registers records DMA remapping fault information when primary fault logging is active Hardware reports the number and location of fault recording registers through the C
357. in the processor Writes to this register have no effect Device 0 Function 0 1 Offset 00h Device 2 Function 0 1 Offset 00h Reset EE Bit Type Value Description 15 0 RO 3086h Vendor Identification Number The value assigned to Intel DI D Device Identification Register This 16 bit register combined with the Vendor Identification register uniquely identifies the Function within the processor Writes to this register have no effect See Section 3 2 for the DID of each processor function Device 0 Function 0 1 Offset 02h Device 2 Function 0 1 Offset 02h Reset eee Bit Type Value Description A See Device I dentification Number 15 0 RO Section 3 2 fi A ici This field identifies each function of the processor Datasheet Volume 2 Intel QuickPath Architecture System Address Decode Register Description intel 3 4 3 RI D Revision Identification Register This register contains the revision number of the processor The Revision ID RID is a traditional 8 bit Read Only RO register located at offset 08h in the standard PCI header of every PCI PCI Express compatible device and function Device 0 Function 0 1 Offset 08h Device 2 Function 0 1 Offset 08h Reset ar Bit Type Value Description Revision dentification Number This is an 8 bit value that indicates the revision identification number for 7 0 RO Oh t
358. indicates that the upper 32 bits of the prefetchable memory region base address are contained in the Prefetchable Memory base Upper Address register at 28h Datasheet Volume 2 127 m t 1 Processor Configuration Registers 2 10 18 2 10 19 128 PMLI MIT1 Prefetchable Memory Limit Address Register This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC that is prefetchable from the processor perspective B D F Type 0 1 0 PCI Address Offset 26 27h Reset Value 0001h Access RW RO Reset F Bit Attr Value Description
359. into the four bytes of configuration space specified by the contents of CONFIG_ADDRESS Any read or write to CONFIG_DATA will result in the GMCH translating the CONFIG_ADDRESS into the appropriate configuration cycle The GMCH is responsible for translating and routing the GMCH s I O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH configuration registers DMI or PCI Express Datasheet Volume 2 Processor Configuration Registers t 2 4 2 Figure 2 9 PCI Express Enhanced Configuration Mechanism PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the latest PCI Local Bus Specification PCI Express configuration space is divided into a PCI 3 0 compatible region which consists of the first 256B of a logical device s configuration space and a PCI Express extended region which consists of the remaining configuration space The PCI compatible region can be accessed using either the Standard PCI Configuration Mechanism or using the PCI Express Enhanced Configuration Mechanism described in this section The extended configuration registers may only be accessed using the PCI Express Enhanced Configuration Mechanism To maintain compatibility with PCI configuration addressing mechanisms system software must access the extended configuration space using 32 bit operations 32 bit aligned only These 32 bit operations include byte enables allowing only
360. ion Number 2 0 is Header Byte 9 2 0 And special fields for this type of TLP e Extended Register Number 3 0 is Header Byte 10 3 0 e Register Number 5 0 is Header Byte 11 7 2 See the PCI Express Base Specification and the PCI Local Bus Specification Revision 3 0 for more information on both the PCI 3 0 compatible and PCI Express Enhanced Configuration Mechanism and transaction rules PCI Express Configuration Accesses When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express Enhanced Configuration access matches the Device 1 Secondary Bus Number a PCI Express Type 0 Configuration TLP is generated on the PCI Express link targeting the device directly on the opposite side of the link This should be Device 0 on the bus number assigned to the PCI Express link likely Bus 1 The device on other side of link must be Device 0 The processor will Master Abort any Type 0 Configuration access to a non zero device number If there is to be more than one device on that side of the link there must be a bridge implemented in the downstream device When the bus number of a type 1 Standard PCI Configuration cycle or PCI Express Enhanced Configuration access is within the claimed range between the upper bound of the bridge device s Subordinate Bus Number register and the lower bound of the bridge device s Secondary Bus Number register but does not match the Device 1 Secondary Bus Number a PCI Express Type 1 Configura
361. ion Queue Head Register This register indicates the invalidation queue head This register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 DMI VC1REMAP Address Offset 80 87h Reset Value 0000000000000000h Access RO Reset PAPP Bit Attr Value Description 63 19 RO 00000000 Reserved 0000h Queue Head QH Specifies the offset 128 bit aligned to the invalidation queue for the 18 4 RO 0000h command that will be fetched next by hardware Hardware resets this field to 0 whenever the queued invalidation is disabled QIES field Clear in the Global Status register 3 0 RO Oh Reserved 2 16 20 IQT_REG Invalidation Queue Tail Register This register indicates the invalidation tail head This register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 DMI VC1REMAP Address Offset 88 8Fh Reset Value 0000000000000000h Access RO s Reset P Bit Attr Value Description p 00000000 Reserved 63 19 RO 0000h Queue Tail QT 18 4 RO 0000h Specifies the offset 128 bit aligned to the invalidation queue for the command that will be written next by software 3 0 RO Oh Reserved Datasheet Volume 2 243 intel Processor Configuration Registers 2 16 21 1
362. iption Enable Protected Memory EPM This field controls DMA accesses to the protected low memory and protected high memory regions 0 DMA accesses to protected memory regions are handled as follows If DMA remapping hardware is not enabled DMA requests including those to protected regions are not blocked If DMA remapping hardware is enabled DMA requests are translated per the programming of the DMA remapping structures Software may program the DMA remapping structures to allow or block DMA to the protected memory regions 1 DMA accesses to protected memory regions are handled as follows 31 RW Oh If DMA remapping hardware is not enabled DMA to protected memory regions are blocked These DMA requests are not recorded or reported as DMA remapping faults If DMA remapping hardware is enabled hardware may or may not block DMA to the protected memory region s Software must not depend on hardware protection of the protected memory regions and must ensure the DMA remapping structures are properly programmed to not allow DMA to the protected memory regions Hardware reports the status of the protected memory enable disable operation through the PRS field in this register Hardware implementations supporting DMA draining must drain any in flight translated DMA requests queued within the root complex before indicating the protected memory region as enabled through the PRS field 30 1 RO pes ae Reserved Protected Region S
363. is NOT necessarily the highest main memory address holes may exist in main memory address map due to addresses allocated for memory mapped I O above TOM The Manageability Engine s ME stolen size register reflects the total amount of physical memory stolen by the Manageability Engine The ME stolen memory is located at the top of physical memory The ME stolen memory base is calculated by subtracting the amount of memory stolen by the Manageability Engine from TOM Top of Upper Usable DRAM TOUUD The Top of Upper Usable Dram TOUUD register reflects the total amount of addressable DRAM If remap is disabled TOUUD will reflect TOM minus Manageability Engine s stolen size If remap is enabled then it will reflect the remap limit When there is more than 4 GB of DRAM and reclaim is enabled the reclaim base will be the same as TOM minus ME stolen memory size to the nearest 64 MB alignment shown in case 2 below Top of Low Usable DRAM TOLUD TOLUD register is restricted to 4 GB memory A 31 20 but the processor can support up to 16 GB limited by DRAM pins For physical memory greater than 4 GB the TOUUD register helps identify the address range in between the 4 GB boundary and the top of physical memory This identifies memory that can be directly accessed including remap address calculation which is useful for memory access indication and early path indication When remap is enabled TOLUD must be 64 MB aligned but when remap is
364. it can reset it correctly during S3 resume B D F Type 0 2 0 PCI Address Offset 62h Reset Value 02h Access RO RW RW K n Reset aai Bit Attr Value Description 7 4 RW Oh Reserved These RW bits are Scratch Bits Only They have no physical effect on hardware 3 RO Ob Reserved Untrusted Aperture Size LHSAS 11 bits 28 27 of GMADR register are made Read only and forced to zero allowing only 512 MB of GMADR z 01 bit 28 of GMADR is made R W and bit 27 of GMADR is forced to zero ee REE 01b allowing 256 MB of GMADR 00 bits 28 27 of GMADR register are made RW allowing 128 MB of GMADR 10 Ivalid programming 0 RO Oh Reserved 132 Datasheet Volume 2 Processor Configuration Registers intel 2 10 26 PM_CAPID1 Power Management Capabilities Register Access B D F Type Address Offset Reset Value 0 1 0 PCI 80 83h C8039001h RO Bit Attr Reset Value Description 31 27 RO 19h PME Support PMES This field indicates the power states in which this device may indicate PME wake using PCI Express messaging DO D3hot and D3cold This device is not required to do anything to support D3hot and D3cold it simply must report that those states are supported Refer to the PCI Power Management 1 1 specification for encoding explanation and other power management details 26 RO Ob D2 Power State Support D2PSS Hardwired to
365. ithin this limit Hardware may ignore and not implement bits 47 32 N where N is the supported domain id width reported in the capability register 31 0 RO 00975099 Reserved Datasheet Volume 2 Processor Configuration Registers intel 2 16 30 FRCD_REG Fault Recording Registers These Registers record fault information when primary fault logging is active Hardware reports the number and location of fault recording registers through the Capability register This register is relevant only for primary fault logging These registers are sticky and can be cleared only through powergood reset or using software clearing the RWC fields by writing a 1 Access B D F Type Address Offset Reset Value 0 0 0 DMIVCLREMAP 200 20Fh 00000000000000000000000000000000h RW1C S RO V S RO Bit Attr Reset Value Description RW1C S Ob Fault F Hardware sets this field to indicate a fault is logged in this Fault Recording register The F field is Set by hardware after the details of the fault is recorded in other fields When this field is Set hardware may collapse additional faults from the same source id SID Software writes the value read from this field to Clear it Refer to the VTd specification for hardware details of primary fault logging 126 RO V S Ob Type T Type of the faulted request 0 Write request 1 Read request This field is relevant only whe
366. ity This register is locked by ME pre allocated Memory lock and may also be forced to 0000h by the Performance Dual Channel Disable fuse 1 Channel Size 1CHSZ This register indicates the total memory that is mapped to 1 channel operation 1 MB granularity This register is locked by ME pre allocated Memory lock Channel 0 Single Channel Size COSCSI ZE 15 0 RW L 0000h This register indicates the quantity of memory physically in channel 0 that is mapped to 1 channel operation 1 MB granularity 31 16 RW L 0000h 68 Datasheet Volume 2 Processor Configuration Registers intel 2 8 2 CHDECMI SC Channel Decode Miscellaneous Register This register provides enhanced addressing configuration bits B D F Type Address Offset Reset Value Access BIOS Optimal Reset Value 0 0 0 MCHBAR 111h 00h RW L RO Oh Reset Bit Attr Value Description Enhanced Address for DIMM Select ENHDIMMSEL This bit may only be set when enhanced mode of addressing for ranks is enabled bit 6 is 0 and at least one of bit 3 or bit 2 are 1 and all four ranks are populated with equal amount of memory 0 Use Standard methods for DIMM Select 1 Use Enhanced Address as DIMM Select This register is locked by Memory pre allocated for ME lock 6 5 RW L 00b Enhanced Mode Select ENHMODESEL Enhanced Mode select applies only when enhanced addressing is enabled at least one of
367. ld in the Global Status register Clearing this bit has no effect Value returned on read of this field is undefined Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 18 1Bh Reset Value 00000000h Access W WO RO P Reset aoai Bit Attr Value Description Queued I nvalidation Enable QIE This field is valid only for implementations supporting queued invalidations Software writes to this field to enable or disable queued invalidations 0 Disable queued invalidations 1 Enable use of queued invalidations Hardware reports the status of queued invalidation enable operation through QIES field in the Global Status register Refer to the VTd specification for software requirements for enabling disabling queued invalidations The value returned on a read of this field is undefined 26 Ww Ob Interrupt Remapping Enable IRE This field is valid only for implementations supporting interrupt remapping 0 Disable interrupt remapping hardware 1 Enable interrupt remapping hardware Hardware reports the status of the interrupt remapping enable operation through the IRES field in the Global Status register 25 WwW Ob There may be active interrupt requests in the platform when software updates this field Hardware must enable or disable interrupt remapping logic only at deterministic transaction boundaries so that any in flight interrupts are either s
368. le advanced fault logging through EAFL field Refer to the VTd specification for detailed software requirements There may be active DMA requests in the platform when software updates this field Hardware must enable or disable remapping logic only at deterministic transaction boundaries so that any in flight transaction is either subject to remapping or not at all Hardware implementations supporting DMA draining must drain any in flight translated DMA read write requests queued within the root complex before completing the translation enable command and reflecting the status of the command through the TES field in the GSTS_REG Value returned on read of this field is undefined Datasheet Volume 2 191 192 Processor Configuration Registers B D F Type Address Offset Reset Value Access 0 0 0 VCOPREMAP 18 1Bh 00000000h W WO RO Bit Attr Reset Value Description 30 wo Ob Set Root Table Pointer SRTP Software sets this field to set update the root entry table pointer used by hardware The root entry table pointer is specified through the Root entry Table Address register Hardware reports the status of the root table pointer set operation through the RTPS field in the Global Status register The root table pointer set operation must be performed before enabling or re enabling after disabling DMA remapping hardware After a root table pointer set operation software must globally in
369. letion Event Control Register This register specifies the invalidation event interrupt control bits The register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type Reset Value Access Address Offset 0 2 0 GFXVTBAR A0 A3h 80000000h RO Bit Attr Reset Value Description 31 RO 1b Interrupt Mask IM 0 No masking of interrupt When a invalidation event condition is detected hardware issues an interrupt message using the Invalidation Event Data amp Invalidation Event Address register values 1 This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is Set 30 RO Ob Interrupt Pending IP Hardware sets the IP field whenever it detects an interrupt condition Interrupt condition is defined as e An Invalidation Wait Descriptor with Interrupt Flag IF field Set completed setting the IWC field in the Invalidation Completion Status register e Ifthe IWC field in the Invalidation Completion Status register was already Set at the time of setting this field it is not treated as a new interrupt condition The IP field is kept Set by hardware while the interrupt message is held pending The interrupt message could be held pending due to interrupt mask IM field being Set or
370. lidation request to hardware 00000000 software must first write the appropriate fields in this register and then issue 63 12 w 00000h appropriate page selective invalidate command through the IOTLB_REG Hardware ignores bits 63 N where N is the maximum guest address width MGAW supported Value returned on read of this field is undefined 11 7 RO 00h Reserved Invalidation Hint IH The field provides hint to hardware to preserve or flush the non leaf page directory entries that may be cached in hardware 0 Software may have modified both leaf and non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware must flush both the 6 w Ob cached leaf and non leaf page table entries corresponding to mappings specified by ADDR and AM fields 1 Software has not modified any non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware may preserve the cached non leaf page table entries corresponding to mappings specified by ADDR and AM fields Value returned on read of this field is undefined Address Mask AM The value in this field specifies the number of low order bits of the ADDR field that must be masked for the invalidation operation Mask field enables software to request invalidation of contiguous mappings for size aligned regions For example Mask Value ADDR bits masked Pages
371. ling after disabling interrupt remapping hardware through the IRE field After an interrupt remap table pointer set operation software must globally invalidate the interrupt entry cache This is required to ensure hardware uses only the interrupt remapping entries referenced by the new interrupt remap table pointer and not any stale cached entries While interrupt remapping is active software may update the interrupt remapping table pointer through this field However to ensure valid in flight interrupt requests are deterministically remapped software must ensure that the structures referenced by the new interrupt remap table pointer are programmed to provide the same remapping results as the structures referenced by the previous interrupt remap table pointer Clearing this bit has no effect The value returned on a read of this field is undefined 23 RO Ob Compatibility Format Interrupt CFI This field is valid only for Intel 64 implementations supporting interrupt remapping Software writes to this field to enable or disable Compatibility Format interrupts on Intel 64 platforms The value in this field is effective only when interrupt remapping is enabled and Extended Interrupt Mode x2APIC mode is disabled 0 Block Compatibility format interrupts 1 Process Compatibility format interrupts as pass through bypass interrupt remapping Hardware reports the status of updating this field through the CFIS field in t
372. ll 1s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of this register are decoded by hardware as all Os Software may setup the protected high memory region either above or below 4GB The VTd specification describes the Protected High Memory Limit register and hardware decoding of these registers Software must not modify this register when protected memory regions are enabled PRS field Set in PMEN_REG B D F Type 0 0 0 DMI VC1REMAP Address Offset 70 77h Reset Value 0000000000000000h Access RW RO Reset isai Bit Attr Value Description Protected High Memory Base PHMB 00000000 This register specifies the base of protected high memory region in system 63 21 RW 000h memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width 20 0 RO 000000h Reserved Datasheet Volume 2 241 m t 1 Processor Configuration Registers 2 16 18 PHMLIMIT_REG Protected High Memory Limit Register 242 This register is used to setup the limit address of DMA protected high memory region This register must be setup before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as 0 in the C
373. long as the grant count value in this field is greater than zero DMI VCp VT Fetch Grant Count DMI VCPGNTCNT The arbiter will continue to grant DMI VCp VT fetch as long as the grant count 7 4 RW L Fh value in this field is greater than zero and there is no higher priority VT fetch request Arbitration will switch to PEG VCO VT fetch request if the grant count corresponding to PEG VCO VT fetch is greater than zero and the VT fetch request corresponding to PEG VCO stream is available DMI VCO VT Fetch Grant Count DMI VCOGNTCNT The arbiter will continue to grant DMI VCO VT fetch as long as the grant count 3 0 RW L Fh value in this field is greater than zero and there is no higher priority VT fetch requests Arbitration will switch to DMI VCp or PEG VCO VT fetch requests if the grant count corresponding to those VT fetch is greater than zero and the VT fetch requests corresponding to those streams are available 216 Datasheet Volume 2 Processor Configuration Registers intel 2 15 33 PEGVTCMPLRESR PEG VT Completion Resource Dedication This register provides a programmable interface to dedicate the PEGO and PEG1 Completion Tracking Queue resources to PEGO VCO read PEGO VCO write PEG1 VCO read and PEG1 VCO write VT fetch B D F Type 0 0 0 VCOPREMAP Address Offset F08 FOBh Reset Value 20004000h Access RW L RO Reset iak Bit Attr Value Description PEG Completion Tracking Queue Resource Sharing
374. ls Routing Control EXTTSSRC 0 RW L Ob 0 Route all external sensor signals to affect internal thermal sensor registers as appropriate 1 No affect of external sensor signals to internal thermal sensor registers Datasheet Volume 2 Processor Configuration Registers 2 8 54 DDRMPLL1 DDR PLL BIOS Register This register is for DDR PLL register programming B D F Type Address Offset Reset Value Access 0 0 0 MCHBAR 2C20 2C22h 00000Ch RO RW RW S Bit Attr Reset Value Description 23 12 RO 00b Reserved 11 RW S Ob Alternative VCO Select VCOSEL 0 Use VCO A 1 Use VCO B VCO A is recommended Default value 10 RW S Ob Post Divide For DDR 800 Mode DI VSEL Post Divider value 1 versus 2 0 Divide by 1 1 Divide by 2 Only DRR 800 uses the additional divide by 2 due to the increased VCO speed used by DRR 800 mode 9 8 RW S Ob Reserved Ob Reserved 6 1 RW 000110b Feedback Divider Ratio 6 1 FBRATIO Encoding for bits 7 0 Data edge rate in MHz OCh 800 MHz 10h 1066 MHz 14h 1333 MHz Ob Feedback Divider Ratio 0 FBRATIONLSB FB ratios are always even so the LSB is not needed A write to this bit will be dropped will have no effect Datasheet Volume 2 109 Processor Configuration Registers intel 2 9 EPBAR Registers 2 9 1 EPPVCCAP1 EP Port VC Capability Register 1 This r
375. lue 0000_0000h Access RO W g Reset eee Bit Attr Value Description 31 1 RO Oh Reserved Primary CWB Flush Control PCWBFLSH 0 Ww Ob A processor write to this bit flushes the PCWB of all writes The data associated with the write to this register is discarded 2 7 23 SBFC Secondary Buffer Flush Control Register B D F Type 0 0 0 PCI Address Offset C4 C7h Reset Value 0000_0000h Access RO W Reset icik Bit Attr Value Description 31 1 RO Oh Reserved Secondary CWB Flush Control SCWBFLSH 0 Ww Ob A processor write to this bit flushes the SCWB of all writes The data associated with the write to this register is discarded Datasheet Volume 2 61 62 Processor Configuration Registers ERRSTS Error Status Register This register is used to report various error conditions using the SERR DMI messaging mechanism An SERR DMI message is generated on a zero to one transition of any of these flags if enabled by the ERRCMD and PCICMD registers These bits are set regardless of whether or not the SERR is enabled and generated After the error processing is complete the error logging mechanism can be unlocked by clearing the appropriate status bit by software writing a 1 to it B D F Type 0 0 0 PCI Address Offset C8 C9h Reset Value 0000h Access RO RW1C S BIOS Optimal Reset Value Oh Reset ae Bit Attr Value Description 15 13 RO 000
376. lue is a bit mask for compatibility with prior steppings i Device I D TXT DI D ALLO RO AGON A000h This processor i Vendor ID TXT VI D 15 0 RO even This register field contains the PCI standard identification for Intel 8086h 2 21 2 TXT DPR DMA Protected Range Register This is the DMA protected range register B D F Type 0 0 O TXT Specific Address Offset 330 337h Reset Value 0000000000000000h Access RO RW L RW L K f Reset ae Bit Attr Value Description 63 32 RO 99009900 Reserved Top of DMA Protected Range TopOfDPR 31 20 RO 000h Top address 1 of DPR On the processor this is the base of TSEG Bits 19 0 of the BASE reported here are 0_0000h 19 12 RO 00h Reserved DMA Protected Memory Size DPR SI ZE 11 4 RW L 00h This is the size of memory in MB that will be protected from DMA accesses A value of 00h in this field means no additional memory is protected The maximum amount of memory that will be protected is 255 MB 3 1 RO 000b Reserved Lock LOCK Bits 19 0 are locked down in this register when this bit is set 0 RW L K Ob This bit is a write once bit If BIOS writes a 0 to the bit then it can not be written to a 1 on subsequent writes BIOS must write the entire register with the correct values and set this bit with that write Datasheet Volume 2 333 intel Processor Configuration Registers 2 21 3 TXT PUBLIC KEY LOWER TXT Processor Public
377. lume 2 Processor Configuration Registers intel 2 8 39 TSS1 Thermal Sensor Status 1 Register This read only register provides trip point and other status of the thermal sensor B D F Type 0 0 0 MCHBAR Address Offset 1004 1005h Reset Value 0000h Access RO 5 Reset PREP Bit Attr Value Description 15 11 RO 00h Reserved Thermometer Mode Output Valid TMOV 1 The Thermometer mode is able to converge to a temperature and the TR register is reporting a reasonable estimate of the thermal sensor 10 RO Ob temperature 0 The Thermometer mode is off or the temperature is out of range or the TR register is being looked at before a temperature conversion has had time to complete 9 9 RO Oh Reserved 8 RO Ob Reserved 7 6 RO 00b Reserved 5 RO Ob Catastrophic Trip Indicator CTI 1 Internal thermal sensor temperature is above the catastrophic setting 4 RO Ob Hot Trip I ndictor HTI 1 Internal thermal sensor temperature is above the Hot setting 3 RO Ob Aux3 Trip Indicator A3TI 1 Internal thermal sensor temperature is above the Aux3 setting 2 RO Ob Aux2 Trip Indicator A2TI 1 Internal thermal sensor temperature is above the Aux2 setting 1 RO Ob Aux1 Trip Indicator A1TI 1 Internal thermal sensor temperature is above the Aux1 setting 0 RO Ob Aux0O Trip Indicator AOTI 1 Internal thermal sensor temperature is above the AuxO setting 2 8 4
378. may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting queued invalidations implement this bit as reserved Advanced Pending Fault APF When this field is Clear hardware sets this field when the first fault record at 3 RW1C Ob index 0 is written to a fault log At this time a fault event is generated based S on the programming of the Fault Event Control register Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as reserved Advanced Fault Overflow AFO Hardware sets this field to indicate advanced fault log overflow condition At RW1C this time a fault event is generated based on the programming of the Fault 2 Ob S Event Control register Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as reserved Primary Pending Fault PPF This field indicates if there are one or more pending faults logged in the fault recording registers Hardware computes this field as the logical OR of Fault F fields across all the fault recording registers of this DMA remapping HW unit 1 RO V S Ob 0 No pending faults in any of the fault recording registers 1 One or more fault recording registers has pending faults The FRI field is updated by hardware whenever the PPF field is set by hardware Also depending on the programming of Fault Event Co
379. mber in the SID field 11 Mask all three bits of function number in the SID field The context entries corresponding to all the source ids specified through the FM and SID fields must have the domain id specified in the DID field Value returned on read of this field is undefined Source ID SID Indicates the source id of the device whose corresponding context entry 31 16 WwW 0000h needs to be selectively invalidated This field along with the FM field must be programmed by software for device selective invalidation requests Value returned on read of this field is undefined Domain ID DID Indicates the ID of the domain whose context entries needs to be selectively invalidated This field must be programmed by software for both domain selective and device selective invalidation requests The Capability register reports the domain id width supported by hardware Software must ensure that the value written to this field is within this limit Hardware may ignore and not implement bits 15 N where N is the supported domain id width reported in the capability register 15 0 RW 0000h Datasheet Volume 2 233 intel 2 16 8 234 Processor Configuration Registers FSTS_REG Fault Status Register This register indicates the various error status B D F Type 0 0 0 DMIVCLREMAP Address Offset 34 37h Reset Value 00000000h Access RW1C S RO V S RO
380. me 2 133 intel Processor Configuration Registers 2 10 27 PM_CS1 Power Management Control Status Register B D F Type Address Offset Reset Value Access 0 1 0 PCI 84 87h 0000_0008h RO RW S RW Bit Attr Reset Value Description 31 16 RO 0000h Reserved Not Applicable or Implemented Hardwired to 0 15 RO Ob PME Status PMESTS Indicates that this device does not support PMEB generation from D3cold 14 13 RO 00b Data Scale DSCALE Indicates that this device does not support the power management data register Oh Data Select DSEL Indicates that this device does not support the power management data register Ob PME Enable PMEE Indicates that this device does not generate PMEB assertion from any D state 0 PMEB generation not possible from any D State 1 PMEB generation enabled from any D State The setting of this bit has no effect on hardware See PM_CAP 15 11 7 4 RO 0000b Reserved 1b No Soft Reset NSR When set to 1 this bit indicates that the device is transitioning from D3hot to DO because the power state commands do not perform a internal reset Config context is preserved Upon transition no additional operating system intervention is required to preserve configuration context beyond writing the power state bits When clear the devices do not perform an internal reset upon transitioning from D3hot to DO usin
381. measured environment has been established and before the TXT CMD CLOSE PRIVATE command has been issued The private space registers are mapped to the address range starting at FED20000h The public space registers are mapped to the address range starting at FED30000h and are available before during and after a measured environment launch The offsets in the table are from the start of either the public or private spaces all registers are available within both spaces though with different permissions Table 2 16 Intel TXT Register Address Map Address Register 5 Offset Symbol Register Name Reset Value Access 110 117h TXT DID TXT Device ID Register 00000003A0008086h RO TXT DMA Protected Range RW L 330 337h TXT DPR 0000000000000000h RW L K RO TXT PUBLI TXT Processor Public Key Hash Lower Half 73A13C69E7DCF24C3 Seen E KEN LON 84C652BA19DA250h TXT PUBLI TXT Processor Public Key Hash Upper Half D884C70067DFC104B Pa ete FDF8368D7254DBBh RO 332 Datasheet Volume 2 Processor Configuration Registers 2 21 1 TXT DI D TXT Device I D Register This register contains the TXT ID for the processor B D F Type 0 0 0 TXT Specific Address Offset 110 117h Reset Value 00000003A0008086h Access RO Reset dogi Bit Attr Value Description 63 48 RO 0000h Reserved Revision ID TXT RID 47 32 RO 0003h For the initial stepping of the component the value is 0001h The va
382. minor version 186 Datasheet Volume 2 Processor Configuration Registers 2 15 2 CAP_REG Capability Register This register reports general DMA remapping hardware capabilities B D F Type 0 0 0 VCOPREMAP Address Offset 8 Fh Reset Value 00C9008020630272h Access RO Reset par Bit Attr Value Description 63 56 RO 00h Reserved DMA Read Draining DRD 0 On IOTLB invalidations hardware does not support draining of 55 RO 1b translated DMA read requests queued within the root complex 1 On IOTLB invalidations hardware supports draining of translated DMA read requests queued within the root complex Indicates supported architecture version DMA Write Draining DWD 0 On IOTLB invalidations hardware does not support draining of 54 RO 1b translated DMA writes queued within the root complex 1 On IOTLB invalidations hardware supports draining of translated DMA writes queued within the root complex Maximum Address Mask Value MAMV 53 48 RO 001001b The value in this field indicates the maximum supported value for the Address Mask AM field in the Invalidation Address IVA_REG register Number of Fault Recording Registers NFR This field indicates a value of N 1 where N is the number of fault recording registers supported by hardware 47 40 RO 00000000 Implementations must support at least one fault recording register NFR 0 b for each DMA remapping
383. mming the protected low memory base and limit registers with the same value in bits 31 N 1 specifies a protected low memory region of size 2 N 1 bytes Programming the protected low memory limit register with a value less than the protected low memory base register disables the protected low memory region Software must not modify this register when protected memory regions are enabled PRS field Set in PMEN_REG B D F Type 0 0 0 DMIVC1REMAP Address Offset 6C 6Fh Reset Value 00000000h Access RW RO F Reset Eee Bit Attr Value Description Protected Low Memory Limit PLML 31 21 RW 000h This register specifies the last host physical address of the DMA protected low memory region in system memory 20 0 RO 000000h Reserved Datasheet Volume 2 Processor Configuration Registers t 2 16 17 PHMBASE_ REG Protected High Memory Base Register This register is used to set up the base address of DMA protected high memory region This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as Clear in the Capability register The alignment of the protected high memory region base depends on the number of reserved bits N 0 of this register Software may determine N by writing a
384. mory I O accesses to the PCI Express bus interface when processor initiated O cycle addresses are within the PCI Express I O address range This range is controlled using the I O Base Address IOBASE and I O Limit Address 1OLIMIT registers in processor Device 1 or Device 6 if a 24 PEG port is enabled configuration space Address decoding for this range is based on the following concept The top 4 bits of the respective I O Base and I O Limit registers correspond to address bits A 15 12 of an I O address For the purpose of address decoding the processor assumes that lower 12 address bits A 11 0 of the I O base are zero and that address bits A 11 0 of the I O limit address are FFFh This forces the I O address range alignment to 4 KB boundary and produces a size granularity of 4 KB The processor positively decodes O accesses to PCI Express I O address space as defined by the following equation O_Base_Address lt processor I O Cycle Address lt I O_Limit_Address The effective size of the range is programmed by the plug and play configuration software and it depends on the size of I O space claimed by the PCI Express device The processor also forwards accesses to the Legacy VGA I O ranges according to the settings in the Device 1 configuration registers BCTRL VGA Enable and PCICMD1 1OAE1 unless a second adapter monochrome is present on the DMI Interface PCl or ISA The presence of a second graphics adapter is determined
385. mory caused as a function of memory types and population of ranks Access B D F Type Address Offset Reset Value 0 0 0 MCHBAR 6B4 6B7h 0000_0000h RO RW L K RW L Bit Attr Reset Value Description 31 24 RO 00h Reserved 23 RW L K Ob DRAM Throttle Lock DTLOCK This bit secures the DRAM throttling control registers DT EW and DTC Once a 1 is written to this bit all of these configuration register bits become read only 22 RO Ob Reserved 21 RW L Ob DRAM Bandwidth Based Throttling Enable DBBTE 0 Bandwidth Threshold WAB is not used for throttling 1 Bandwidth Threshold WAB is used for throttling If both Bandwidth based and thermal sensor based throttling modes are on and the thermal sensor trips weighted average WAT is used for throttling 20 RW L Ob DRAM Thermal Sensor Trip Enable DTSTE 0 GMCH throttling is not initiated when the processor thermal sensor trips 1 GMCH throttling is initiated when the processor thermal sensor trips and the Filter output is equal to or exceeds thermal threshold WAT 19 RO Ob Reserved 18 16 RW L 000b Time Constant TC 000 2 28 Clocks 001 2 29 Clocks 010 2 30 Clocks 011 2 31 Clocks Others Reserved 00h Weighted Average Bandwidth Limit WAB Average weighted bandwidth allowed per clock during for bandwidth based throttling The processor does
386. ms Note that access to this 1O BAR is independent of VGA functionality within Device 2 Also note that this mechanism is available only through function 0 of Device 2 and is not duplicated in function 1 If accesses to this 1O bar are allowed the processor claims all 8 16 or 32 bit 1O cycles from the processor that falls within the 8B claimed B D F Type 0 2 0 PCI Address Offset 20 23h Reset Value 0000_0001h Access RO RW gt Reset ar Bit Attr Value Description 31 16 RO 0000h Reserved I O Base Address I OBASE 15 3 R ppp This field is set by the OS The bits correspond to address signals 15 3 Memory Type MEMTYPE aid nO 009 Hardwired to Os to indicate 32 bit address 0 RO lb Memory 10 Space MIOS Hardwired to 1 to indicate I O space 2 13 13 SVID2 Subsystem Vendor Identification Register B D F Type 0 2 0 PCI Address Offset 2C 2Dh Reset Value 0000h Access RW O gt Reset ons 3 Bit Attr Value Description Subsystem Vendor ID SUBVID This value is used to identify the vendor of the subsystem This register should be programmed by BIOS during boot up Once written this register becomes Read Only This register can only be cleared by a Reset 15 0 RW O 0000h Datasheet Volume 2 181 intel Processor Configuration Registers 2 13 14 SID2 Subsystem Identification Register B D F Type 0 2 0 P
387. mum number of RTI Ds for the local home agent 15 14 RV 00b Reserved SIBLING 13 8 RW 2h Maximum number of RTI Ds for the sibling home agent 7 6 RV 00b Reserved CHI PSET 5 0 RW an Maximum number of RTIDs for the IOH home agent SAD System Address Decoder Registers SAD_PAM0123 This register is for legacy Device 0 Function 0 90h 93h address space Device 0 Function 1 Offset 40h Access as a Dword z Reset er Bit Type Value Description 31 30 RV 0 Reserved PAM3_HI ENABLE 0D4000h 0D7FFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D4000h to OD7FFFh 29 28 RW o 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM ll 27 26 RV 0 Reserved Datasheet Volume 2 349 intel 350 Intel QuickPath Architecture System Address Decode Register Description Device 0 Function 1 Offset 40h Access as a Dword Reset Bit Type Value Description PAM3_LOENABLE 0D0000h 0D3FFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D0000h to OD3FFFh 25 24 RW 0 00 DRAM Disabled All accesses are directed to ESI
388. must ensure that the structures referenced by the new interrupt remap table pointer are programmed to provide the same remapping results as the structures referenced by the previous interrupt remap table pointer Clearing this bit has no effect The value returned on a read of this field is undefined Compatibility Format I nterrupt CFI This field is valid only for Intel 64 implementations supporting interrupt remapping Software writes to this field to enable or disable Compatibility Format interrupts on Intel 64 platforms The value in this field is effective only when interrupt remapping is enabled and Legacy Interrupt Mode is active 0 Block Compatibility format interrupts 1 Process Compatibility format interrupts as pass through bypass interrupt 23 w Ob remapping Hardware reports the status of updating this field through the CFIS field in the Global Status register Refer to the VTd specification for details on Compatibility Format interrupt requests The value returned on a read of this field is undefined This field is not implemented 22 0 RO 000000h Reserved Datasheet Volume 2 193 intel Processor Configuration Registers 2 15 5 GSTS_REG Global Status Register This register reports general DMA remapping hardware status Access B D F Type Address Offset Reset Value 0 0 0 VCOPREMAP 1C 1Fh 00000000h RO Bit Attr Reset Value Description 31
389. must fully disable a Virtual Channel in both Components on a Link before re enabling the Virtual Channel 30 27 RO Oh Reserved VC1 ID VC1ID 26 24 RW 001b Assigns a VC ID to the VC resource Assigned value must be non zero This field can not be modified when the VC is already enabled 23 20 RO Oh Reserved Port Arbitration Select PAS F This field configures the VC resource to provide a particular Port Arbitration 19 17 RW 000b a service The Reset Value of Oh corresponds to bit position of the only asserted bit in the Port Arbitration Capability field 16 RO Ob Reserved 15 8 RO 00h Reserved TC VC1 Map TCVC1M This field indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example 7 1 RW 00h when bit 7 is set in this field TC7 is mapped to this VC resource i When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link TCO VC1 Map TCO VC1M Traffic Class 0 is always routed to VCO Datasheet Volume 2 113 intel 2 9 6 114 Processor Configuration Registers EPVC1RSTS EP VC 1 Resource Status Register B D F Type 0 0 0 PXPEPBAR Address Offset 26 27h Reset Value
390. n memory that is pre allocated to support the Internal Graphics Translation Table The BIOS ensures that memory is pre allocated only when Internal graphics is enabled GSM is assumed to be a contiguous physical DRAM space with DSM and BIOS needs to allocate a contiguous memory chunk Hardware will drive the base of GSM from DSM only using the GSM size programmed in the register Oh No memory pre allocated GTT cycles Memory and 10 are not claimed 1h No VT mode 1 MB of memory pre allocated for GTT 3h No VT mode 2 MB of memory pre allocated for GTT 9h VT mode 2 MB of memory pre allocated for 1 MB of Global GTT and 1 MB for Shadow GTT Ah VT mode 3 MB of memory pre allocated for 1 5 MB of Global GTT and 1 5 MB for Shadow GTT Bh VT mode 4 MB of memory pre allocated for 2 MB of Global GTT and 2 MB for Shadow GTT All unspecified encodings of this register field are reserved hardware functionality is not ensured if used 7 4 RO 0011b Graphics Mode Select GMS This field is used to select the amount of main memory that is pre allocated to support the Internal Graphics device in VGA non linear and Native linear modes The BIOS ensures that memory is pre allocated only when Internal graphics is enabled Oh No memory pre allocated Device 2 IGD does not claim VGA cycles Memory and I0 and the Sub Class Code field within Device 2 function 0 Class Code register is 80h 1h DVMT UMA mode 1 MB
391. n the F field is set and when the fault reason FR indicates one of the DMA remapping fault conditions 125 124 RO V S 00b Address Type AT This field captures the AT field from the faulted DMA request Hardware implementations not supporting Device IOTLBs DI field Clear in Extended Capability register treat this field as reserved When supported this field is valid only when the F field is set and when the fault reason FR indicates one of the DMA remapping fault conditions 123 104 RO 00000h Reserved 103 96 RO V S 00h Fault Reason FR Reason for the fault VTd specification 1 2 Appendix enumerates the various translation fault reason encodings This field is relevant only when the F field is set 95 80 RO 0000h Reserved 79 64 RO V S 0000h Source Identifier SID Requester id associated with the fault condition This field is relevant only when the F field is set 63 12 RO V S Fault Info FI When the Fault Reason FR field indicates one of the DMA remapping fault conditions bits 63 12 of this field contains the page address in the faulted DMA request Hardware treat bits 63 N as reserved 0 where N is the 00000000 maximum guest address width MGAW supported 00000h When the Fault Reason FR field indicates one of the interrupt remapping fault conditions bits 63 48 of this field indicate the interrupt_index computed for the faulted interrupt
392. n type in context entries RO Ob Caching Hints CH 0 Hardware does not support IOTLB caching hints ALH and EH fields in context entries are treated as reserved 1 Hardware supports IOLTB caching hints through the ALH and EH fields in context entries RO Ob Extended Interrupt Mode EI M 0 Hardware supports only 8 bit APICIDs Legacy Interrupt Mode on Intel 64 and IA 32 architecture and 16 bit APIC IDs 1 Hardware supports Extended Interrupt Mode 32 bit APIC IDs on Intel 64 platforms This field is valid only when the IR field is reported as Set RO Ob Interrupt Remapping Support IR 0 Hardware does not support interrupt remapping 1 Hardware supports interrupt remapping Implementations reporting this field as Set must also support Queued Invalidation QI 1b 190 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 10 17h Reset Value 0000000000001000h Access RO P Reset Hoza Bit Attr Value Description Device I OTLB Support DI 2 RO Ob 0 Hardware does not support device OTLBs 1 Hardware supports Device OTLBs Implementations reporting this field as Set must also support Queued Invalidation QI 1b Queued I nvalidation Support QI 1 RO Ob 0 Hardware does not support queued invalidations 1 Hardware supports queued invalidations Coherency C 0 Indicates that hardwa
393. nable bit is not set If device 1 s VGA enable bit is not set then accesses to I O address range x3BCh x3BFh remain on the backbone If the VGA enable bit is set and MDA is not present accesses to I O address range x3BCh x3BFh are forwarded to PCI Express through device 1 if the address is within the corresponding OBASE and IOLIMIT otherwise they remain on the backbone MDA resources are defined as the following Memory 0B0000h OB7FFFh 1 0 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not used in decode Any I O reference that includes the I O locations listed above or their 0 RW Ob aliases will remain on the backbone even if the reference also includes I O locations not listed above The following table shows the behavior for all combinations of MDA and VGA VGAEN MDAP Description 0 0 All References to MDA and VGA space are not claimed by Device 1 0 1 Illegal combination 1 0 All VGA and MDA references are routed to PCI Express Graphics Attach device 1 1 1 All VGA references are routed to PCI Express Graphics Attach device 1 MDA references are not claimed by device 1 VGA and MDA memory cycles can only be routed across PEGO when MAE PCICMD1 1 is set VGA and MDA I O cycles can only be routed across PEGO if IOAE PCICMD1 0 is set 0 No MDA 1 MDA Present Datasheet Volume 2 57 2 7 18 58 intel Processor Configuration Registers TOUUD Top of Upper Usable DRA
394. nables Round Robin re allocation mode 1 Enables LRU re allocation mode Level 1 Cache LRU mode Selection LLLRUMODE 0 Enables the LRU scheme to use a first avail starting from entry 0 to find 3 RW L Ob one of the oldest entries when more than 1 are available 1 Enables the LRU scheme to use a first avail starting from a round robin selected entry Context Cache Disable CCDIS 2 RW L Ob 0 Context Cache is enabled and will be used to cache context translations 1 Context Cache is disabled and will not be used to cache context translation Level 1 I OTLB Disable L1TLBDI S 0 Level 1 IOTLB is enabled and will be used to cache level 1 page table 1 RW L Ob translations 1 Level 1 IOTLB is disabled and will not be used to cache level 1 page table translation Level 3 I OTLB Disable L3TLBDIS 0 Level 3 IOTLB is enabled and will be used to cache level 3 page table 0 RW L Ob translations 1 Level 3 IOTLB is disabled and will not be used to cache level 3 page table translation Datasheet Volume 2 287 intel 2 19 Note Processor Configuration Registers PCI Device 6 Registers Device 6 is not supported on all SKUs Table 2 14 PCI Device 6 Register Address Map Sheet 1 of 2 prey aoe Register Name ae Access 0 1h VID6 Vendor Identification 8086h RO 2 3h DID6 Device Identification 0043h R
395. nction 0 1 Offset 04h Bit Type Joek Description 15 11 RV 0 Reserved by PCI SIG INTxDisable Interrupt Disable This bit controls the ability of the PCI Express port to generate INTx messages If this device does not generate interrupts then this bit is not implemented and is RO 10 RO 0 If this device generates interrupts then this bit is RW and this bit disables the device function from asserting INTx A value of 0 enables the assertion of its INTx signal A value of 1 disables the assertion of its INTx signal 0 Legacy Interrupt mode is disabled 1 Legacy Interrupt mode is enabled FB2B Fast Back to Back Enable This bit controls whether or not the master can do fast back to back 9 RO 0 A n EEN writes Since this device is strictly a target this bit is not implemented This bit is hard wired to 0 Writes to this bit position have no effect SERRE SERR Message Enable This bit is a global enable bit for this devices SERR messaging This host 8 RO 0 bridge will not implement SERR messaging This bit is hard wired to 0 Writes to this bit position have no effect If SERR is used for error generation then this bit must be RW and enable disable SERR signaling IDSELWCC IDSEL Stepping Wait Cycle Control 7 RO 0 Per the PCI 2 3 specification this bit is hard wired to 0 Writes to this bit position have no effect PERRE Parity Error Response Enable 6 RO 0 Parity error is not implemented in this host bridge This bit is h
396. nd when in the Recovery state 7 RW Ob This mode provides external devices such as logic analyzers monitoring the Link time to achieve bit and symbol lock before the link enters LO and resumes communication This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns Common Clock Configuration CCC 0 Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock 6 RW Ob 1 Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock The state of this bit affects the LOs Exit Latency reported in LCAP 14 12 and the N_FTS value advertised during link training See PEGLOSLAT at offset 22Ch Datasheet Volume 2 317 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset BO B1h Reset Value 0000h Access RW RO RW SC Reset Bee Bit Attr Value Description Retrain Link RL 0 Normal operation 1 Full Link retraining is initiated by directing the Physical Layer LTSSM from LO LOs or L1 states to the Recovery state This bit always returns 0 when read This bit is cleared automatically no 5 RW SC Ob need to write a 0 It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register If the LTSSM is not already in Recovery or Configuration
397. nded Capability Register This register reports DMA remapping hardware extended capabilities B D F Type 0 0 0 DMI VCLREMAP Address Offset 10 17h Reset Value 0000000000001000h Access RO Reset EAn Bit Attr Value Description 63 24 RO 00000000 Reserved 00h Maximum Handle Mask Value MHMV The value in this field indicates the maximum supported value for the Handle 23 20 RO Oh Mask HM field in the interrupt entry cache invalidation descriptor iec_inv_dsc This field is valid only when the IR field is reported as set to 1 19 18 RO 00b Reserved Datasheet Volume 2 225 226 Processor Configuration Registers B D F Type 0 0 0 DMIVC1REMAP Address Offset 10 17h Reset Value 0000000000001000h Access RO Reset ss Bit Attr Value Description Invalidation Unit Offset IVO This field specifies the location to the first OTLB registers relative to the 17 8 RO 010h register base address of this DMA remapping hardware unit If the register base address is X and the value reported in this field is Y the address for the first IOTLB register is calculated as X 16 Y Snoop Control SC 7 RO Ob 0 Hardware does not support setting the SNP field to 1 in the page table entries 1 Hardware supports setting the SNP field to 1 in the page table entries Pass Through PT 6 RO Ob 0 Hardware does not support pass through translation ty
398. ndefined 27 Ww Ob 262 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 2 0 GFXVTBAR Address Offset 18 1Bh Reset Value 00000000h Access W RO RW Reset Cane Bit Attr Value Description Queued I nvalidation Enable QIE This field is valid only for implementations supporting queued invalidations Software writes to this field to enable or disable queued invalidations 0 Disable queued invalidations 26 RO Ob 1 Enable use of queued invalidations Hardware reports the status of queued invalidation enable operation through QIES field in the Global Status register Refer to the VTd specification for software requirements for enabling disabling queued invalidations The value returned on a read of this field is undefined Interrupt Remapping Enable I RE This field is valid only for implementations supporting interrupt remapping 0 Disable interrupt remapping hardware 1 Enable interrupt remapping hardware Hardware reports the status of the interrupt remapping enable operation through the IRES field in the Global Status register There may be active interrupt requests in the platform when software 25 RO Ob updates this field Hardware must enable or disable interrupt remapping logic only at deterministic transaction boundaries so that any in flight interrupts are either subject to remapping or not at all Hardware implementations must drain any in flight i
399. ng the programmed trip points and Thermometer mode rate Note When disabling the Thermometer mode while the thermometer is running the Thermometer mode controller will finish the current cycle Note During boot all other thermometer mode registers except lock bits 3 0 RW Oh should be programmed appropriately before enabling the Thermometer Mode Thermometer rate select that is fast clock select 0000 Thermometer mode disabled that is analog sensor mode 0001 enabled 2 usec 0010 enabled 4 usec 0011 enabled 6 usec 0100 enabled 8 usec 0101 enabled 10 usec 0110 enabled 12 usec 0111 enabled 14 usec all other permutations reserved 1111 enabled 8 clock mode for testing digital logic 102 Datasheet Volume 2 Processor Configuration Registers intel 2 8 49 TERRCMD Thermal Error Command Register This register select which errors are generate a SERR DMI interface special cycle as enabled by ERRCMD SERR Thermal Sensor event The SERR and SCI must not be enabled at the same time for the thermal sensor event B D F Type 0 0 0 MCHBAR Address Offset 10E4h Reset Value 00h Access RO RW Reset Be Bit Attr Value Description 7 6 RO 00b Reserved SERR on Catastrophic Thermal Sensor Event CATSERR 1 Does not mask the generation of a SERR DMI cycle on a catastrophic 5 RW 0b thermal sensor trip 0 Disable Reporting of this
400. nk PM Support ASLPMS Graphics Processing Engine supports ASPM LOs and L1 9 4 RW O 10h Max Link Width MLW This field indicates the maximum number of lanes supported for this link 3 0 RW O 2h Max Link Speed MLS Supported Link Speed This field indicates the supported Link speed s of the associated Port Defined encodings are 0001b 2 5GT s Link speed supported 0010b 5 0GT s and 2 5GT s Link speeds supported All other encodings are reserved Datasheet Volume 2 143 intel Processor Configuration Registers 2 10 40 CTL Link Control Register This register allows control of PCI Express link 144 B D F Type Address Offset Reset Value Access 0 1 0 PCI BO Blh 0000h RO RW RW SC Bit Attr Reset Value Description 15 12 RO 0000b Reserved 11 RW Ob Link Autonomous Bandwidth I nterrupt Enable LABI E Link Autonomous Bandwidth Interrupt Enable When Set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Devices that do not implement the Link Bandwidth Notification capability must hardwire this bit to Ob 10 RW Ob Link Bandwidth Management Interrupt Enable LBMIE Link Bandwidth Management Interrupt Enabl
401. nsures that memory is pre allocated only when Internal graphics is enabled Oh No memory pre allocated Device 2 IGD does not claim VGA cycles Memory and 10 and the Sub Class Code field within Device 2 Function 0 Class Code register is 80h 1h 4h Reserved 5h Dh DVMT UMA mode memory pre allocated for frame buffer in quantities as shown in the Encoding table Eh Fh Reserved This register is locked and becomes read only when CMD LOCK MEMCONFIG 7 4 RW L 3h is received or when ME_SM_LOCK is set to 1 Hardware does not clear or set any of these bits automatically based on IGD being disabled enabled BIOS Requirement BIOS must not set this field to Oh if IVD bit 1 of this register is 0 Oh No memory pre allocated 5h 32 MB 6h 48 MB 7h 64 MB 8h 128 MB 9h 256 MB Ah 96 MB Bh 160 MB Ch 224 MB Dh 352 MB Datasheet Volume 2 53 Processor Configuration Registers 2 7 14 54 B D F Type 0 0 0 PCI Address Offset 52 53h Reset Value 0030h Access RW L RO Reset Bee Bit Attr Value Description 3 2 RO 00b Reserved IGD VGA Disable IVD 0 Enable Device 2 IGD claims VGA memory and IO cycles the Sub Class Code within Device 2 Class Code register is 00 1 Disable Device 2 IGD does not claim VGA cycles Memory and 10 and the Sub Class Code field within Device 2 function 0 Class Code 1 RW L Ob register is 80 Ea BIOS Requirement BIOS must not se
402. nterrupts requests queued in the Root Complex before completing the interrupt remapping enable command and reflecting the status of the command through the IRES field in the Global Status register The value returned on a read of this field is undefined Set Interrupt Remap Table Pointer SIRTP This field is valid only for implementations supporting interrupt remapping Software sets this field to set update the interrupt remapping table pointer used by hardware The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address register Hardware reports the status of the interrupt remapping table pointer set operation through the IRTPS field in the Global Status register The interrupt remap table pointer set operation must be performed before enabling or re enabling after disabling interrupt remapping hardware through the IRE field 24 RO Ob After an interrupt remap table pointer set operation software must globally invalidate the interrupt entry cache This is required to ensure hardware uses only the interrupt remapping entries referenced by the new interrupt remap table pointer and not any stale cached entries While interrupt remapping is active software may update the interrupt remapping table pointer through this field However to ensure valid in flight interrupt requests are deterministically remapped software must ensure that the structures referenced by the new interrupt remap table pointe
403. ntrol register a fault event is generated when hardware sets this field Primary Fault Overflow PFO 0 RW1C Ob Hardware sets this field to indicate overflow of fault recording registers S Software writing 1 clears this field When this field is set hardware does not record any new faults until software clears this field Datasheet Volume 2 Processor Configuration Registers intel 2 16 9 FECTL_REG Fault Event Control Register This register specifies the fault event interrupt message control bits The VTd specification describes hardware handling of fault events B D F Type Address Offset Reset Value Access 0 0 0 DMI VCLREMAP 38 3Bh 80000000h RW RO Bit Attr Reset Value Description 31 RW 1b Interrupt Mask IM 0 No masking of interrupt When a interrupt condition is detected hardware issues an interrupt message using the Fault Event Data amp Fault Event Address register values 1 This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is set 30 RO Ob Interrupt Pending IP Hardware sets the IP field whenever it detects an interrupt condition which is defined as e When primary fault logging is active an interrupt condition occurs when hardware records a fault through one of the Fault Recording registers and sets the PPF field in the Faul
404. of memory pre allocated for frame buffer 2h DVMT UMA mode 4 MB of memory pre allocated for frame buffer 3h DVMT UMA mode 8 MB of memory pre allocated for frame buffer 4h DVMT UMA mode 16 MB of memory pre allocated for frame buffer 5h DVMT UMA mode 32 MB of memory pre allocated for frame buffer 6h DVMT UMA mode 48 MB of memory pre allocated for frame buffer 7h DVMT UMA mode 64 MB of memory pre allocated for frame buffer 8h DVMT UMA mode 128 MB of memory pre allocated for frame buffer 9h DVMT UMA mode 256 MB of memory pre allocated for frame buffer BIOS Requirement BIOS must not set this field to 000 if IVD bit 1 of this register is 0 3 2 RO 00b Reserved Datasheet Volume 2 253 Processor Configuration Registers B D F Type 0 2 0 PCI Address Offset 52 53h Reset Value 0030h Access RO Reset be Bit Attr Value Description IGD VGA Disable IVD 0 Enable Device 2 IGD claims VGA memory and IO cycles the Sub Class Code within Device 2 Class Code register is 00 1 Disable Device 2 IGD does not claim VGA cycles Memory and 10 1 RO Ob and the Sub Class Code field within Device 2 function 0 Class Code register is 80 BIOS Requirement BIOS must not set this bit to 0 if the GMS field bits 6 4 of this register pre allocates no memory This bit MUST be set to 1 if Device 2 is disabled either using a fuse or fuse override CAP
405. ol register without delay between successive writes 17 RO Ob Reserved for Electromechanical I nterlock Present EIP When set to 1b this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot 16 15 RW O 00b Slot Power Limit Scale SPLS Specifies the scale used for the Slot Power Limit Value 00 1 0x 01 0 1x 10 0 01x 11 0 001x If this field is written the link sends a Set_Slot_Power_Limit message 14 7 RW O 00h Slot Power Limit Value SPLV In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by slot Power limit in Watts is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field If this field is written the link sends a Set_Slot_Power_Limit message RO Ob Reserved for Hot plug Capable HPC When set to 1b this bit indicates that this slot is capable of supporting hot lug operations RO Ob Reserved for Hot plug Surprise HPS When set to 1b this bit indicates that an adapter present in this slot might be removed from the system without any prior notification This is a form factor specific capability This bit is an indication to the operating system to allow for such removal without impacting continued software operation RO Ob Reserved for Power I ndicator Present PIP When set to 1b this bit indicates that a Power
406. ol register without delay between successive writes 17 RO Reserved for Electromechanical Interlock Present EIP Ob When set to 1 this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot 16 15 RW O Slot Power Limit Scale SPLS This field specifies the scale used for the Slot Power Limit Value 00 1 0x 00b 01 0 1x 10 0 01x 11 0 001x If this field is written the link sends a Set_Slot_Power_Limit message 14 7 RW O Slot Power Limit Value SPLV In combination with the Slot Power Limit Scale value specifies the upper 00h limit on power supplied by slot Power limit in Watts is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field If this field is written the link sends a Set_Slot_Power_Limit message Reserved for Hot plug Capable HPC Ob When set to 1 this bit indicates that this slot is capable of supporting hot lug operations 320 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset B4 B7h Reset Value 00040000h Access RW O RO 5 Reset Hozi Bit Attr Value Description Reserved for Hot plug Surprise HPS When set to 1 this bit indicates that an adapter present in this slot might be 5 RO Ob removed from the system without any prior notification This is a form factor specific capability This
407. on performed using the domain id specified by software in the DID field This could be in response to a domain selective or device selective invalidation request 11 Device selective invalidation performed using the source id and domain id specified by software in the SID and FM fields This can only be in response to a device selective invalidation request 58 34 RO 0000000h Reserved Function Mask FM This field specifies which bits of the function number portion least significant three bits of the SID field to mask when performing device selective invalidations The following encodings are defined for this field 00 No bits in the SID field masked 01 Mask most significant bit of function number in the SID field 10 Mask two most significant bit of function number in the SID field 11 Mask all three bits of function number in the SID field The device s specified through the FM and SID fields must correspond to the domain ID specified in the DID field Value returned on read of this field is undefined 33 32 RO 00b Source ID SID This field indicates the source id of the device whose corresponding context 31 16 RO 0000h entry needs to be selectively invalidated This field along with the FM field must be programmed by software for device selective invalidation requests Value returned on read of this field is undefined Domain ID DID This field indicates the ID of the domain whose context en
408. on space Device 0 Function 0 1 Offset OEh Device 2 Function 0 1 Offset OEh Bit Type st ed Description Multi function Device 7 RO 1 This bit selects whether this is a multi function device that may have alternative configuration layouts This bit is hard wired to 1 for devices in the processor Configuration Layout This field identifies the format of the configuration header layout for a 6 0 RO 0 PCI to PCI bridge from bytes 10h through 3Fh For all devices the default is 00h indicating a conventional type 00h PCI header SI D SVID Subsystem I dentity Subsystem Vendor Identification Register This register identifies the manufacturer of the system This 32 bit register uniquely identifies any PCI device Device 0 Function 0 1 Offset 2Ch 2Eh Device 2 Function 0 1 Offset 2Ch 2Eh Access as a DWord ss Reset Soe Bit Type Value Description Subsystem Identification Number pee RWO SoBgh The Reset Value specifies Intel 15 0 RWO 8086h Vendor Identification Number The Reset Value specifies Intel Datasheet Volume 2 345 intel Intel QuickPath Architecture System Address Decode Register Description 3 4 7 PCI CMD Command Register This register defines the PCI 3 0 compatible command register values applicable to PCI Express space Device 0 Function 0 1 Offset 04h Device 2 Fu
409. ontrols the processor to PCI Express G I O access routing based on the following formula 10_BASE lt address lt IO_LIMIT Only the upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are assumed to be FFFh Thus the top of the defined I O address range will be at the top of a 4 KB aligned address block B D F Type 0 1 0 PCI Address Offset 1Dh Reset Value 00h Access RW RO gt Reset PAPP Bit Attr Value Description 1 O Address Limit I OLI MIT 7 4 RW Oh This field corresponds to A 15 12 of the I O address limit of device 1 Devices between this upper limit and OBASE1 will be passed to the PCI Express hierarchy associated with this device 3 0 RO Oh Reserved 123 intel 2 10 14 124 Processor Configuration Registers SSTS1 Secondary Status Register SSTS1 is a 16 bit status register that reports the occurrence of error conditions associated with secondary side that is PCI Express G side of the virtual PCI PCI bridge embedded within processor B D F Type Address Offset Reset Value Access 0 1 0 PCI 1E 1Fh 0000h RWIC RO Bit Attr Reset Value Description 15 RW1C Ob Detected Parity Error DPE This bit is set by the Secondary Side for a Type 1 Configuration Space header device whenever it receives a Poisoned TLP regardless of the state of the Parity Error Response Enable bit in the Bridge
410. or Interrupt Event WA2TSIE 1 Aux 2 Thermal Sensor trip occurred based on a higher to lower 10 RW1C Ob temperature transition through the trip point 0 No trip for this event Software must write a 1 to clear this status bit Was Aux 1 Thermal Sensor I nterrupt Event WA1TSI E 1 Aux 1 Thermal Sensor trip occurred based on a higher to lower 9 RW1C Ob temperature transition through the trip point 0 No trip for this event Software must write a 1 to clear this status bit Was Aux 0 Thermal Sensor Interrupt Event WAOTSIE 1 Aux 0 Thermal Sensor trip occurred based on a higher to lower 8 RW1C Ob temperature transition through the trip point 0 No trip for this event Software must write a 1 to clear this status bit 7 6 RO 00b Reserved Catastrophic Thermal Sensor Interrupt Event CTSI E 1 A Catastrophic Thermal Sensor trip event occurred based on a lower to 5 RW1C Ob higher temperature transition through the trip point 0 Notrip for this event Software must write a 1 to clear this status bit Hot Thermal Sensor Interrupt Event HTSIE 1 A Hot Thermal Sensor trip event occurred based on a lower to higher 4 RW1C Ob temperature transition through the trip point 0 No trip for this event Software must write a 1 to clear this status bit Datasheet Volume 2 Processor Configuration Registers B D F Type Address Offset Reset Value Access 0 0 0 MCHBAR 101E 1
411. or mask register RW1C Ob Correctable Error Detected CED When set this bit indicates that correctable error s were detected Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the correctable error mask register Datasheet Volume 2 141 intel Processor Configuration Registers 2 10 39 LCAP Link Capabilities Register This register indicates PCI Express device specific capabilities Access B D F Type Address Offset Reset Value 0 1 0 PCI AC AFh 02214D02h RO RW O Bit Attr Reset Value Description 31 24 RO 02h Port Number PN This bit indicates the PCI Express port number for the given PCI Express link Matches the value in Element Self Description 31 24 23 22 RO 00b Reserved 21 RO 1b Reserved Link Bandwidth Notification Capability A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms This capability is required for all Root Ports and Switch downstream ports supporting Links wider than x1 and or multiple Link speeds This field is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Devices that do not implement the Link Bandwidt
412. ort ASPM L1 Datasheet Volume 2 Processor Configuration Registers 2 19 40 LSTS Link Status Register This register indicates PCI Express link status B D F Type 0 6 0 PCI Address Offset B2 B3h Reset Value 1000h Access RO RW1C f Reset aa Bit Attr Value Description Link Autonomous Bandwidth Status LABWS This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width without the port transitioning through DL_Down 15 RW1C Ob status for reasons other than to attempt to correct unreliable link operation This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change Link Bandwidth Management Status LBWMS This bit is set to 1b by hardware to indicate that either of the following has occurred without the port transitioning through DL_Down status A link retraining initiated by a write of 1b to the Retrain Link bit has completed Note This bit is Set following any write of 1b to the Retrain Link bit 14 RW1C Ob including when the Link is in the process of retraining for some other reason Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation either through an LTSSM time out or a higher level process This bit must be set if the Physical Layer reports a speed or width change was initiated
413. ort for up to 1024 domains 100b 12 bit domain IDs with support for up to 4K domains 100b 14 bit domain IDs with support for up to 16K domains 110b 16 bit domain IDs with support for up to 64K domains 111b Reserved Datasheet Volume 2 259 intel Processor Configuration Registers 2 18 3 ECAP_REG Extended Capability Register This register reports DMA remapping hardware extended capabilities B D F Type Address Offset Reset Value Access 0 2 0 GFXVTBAR 10 17h 0000000000001000h RO Reset Bit Attr Value Description 63 24 RO Oh Reserved 23 20 RO Oh Maximum Handle Mask Value MHMV The value in this field indicates the maximum supported value for the Handle Mask HM field in the interrupt entry cache invalidation descriptor iec_inv_dsc This field is valid only when the IR field is reported as Set 19 18 RO 00b Reserved 17 8 RO 010h Invalidation Unit Offset IVO This field specifies the offset to the IOTLB invalidation register relative to the register base address of this remapping hardware unit If the register base address is X and the value reported in this field is Y the address for the I OTLB invalidation register is calculated as X 16 Y Snoop Control SC 0 Hardware does not support setting the SNP field to 1 in the page table entries 1 Hardware supports setting the SNP field to 1 in the page table entries Pass Through PT
414. orted by hardware A value of 1 in any of these bits indicates the corresponding super page size is Supported 37 34 RO Oh Ls super page sizes corresponding to various bit positions within this field Oh 21 bit offset to page frame 2 MB 1h 30 bit offset to page frame 1 GB 2h 39 bit offset to page frame 512 GB 3h 48 bit offset to page frame 1 TB Fault recording Register offset FRO This field specifies the location to the first fault recording register relative to 33 24 RO 020h the register base address of this DMA remapping hardware unit If the register base address is X and the value reported in this field is Y the address for the first fault recording register is calculated as X 16 Y Datasheet Volume 2 257 Processor Configuration Registers B D F Type 0 2 0 GFXVTBAR Address Offset 8 Fh Reset Value 00C0000020230272h Access RO Reset oe Bit Attr Value Description Isochrony I SOCH 0 Indicates this DMA remapping hardware unit has no critical isochronous requesters in its scope 1 Indicates this DMA remapping hardware unit has one or more critical 23 RO Ob isochronous requesters in its scope To ensure isochronous performance software must ensure invalidation operations do not impact active DMA streams from such requesters This implies that when DMA is active software perform page selective invalidations instead of coarser invalidations Zero Length Read ZLR 0
415. ot set within the TLP Header will be rejected as an Unsupported Request 14 8 RO 0000000b Reserved The Port Arbitration Capability is not valid for root ports 7 0 RO Olh Port Arbitration Capability PAC This field indicates types of Port Arbitration supported by the VC resource This field is valid for all Switch Ports Root Ports that support peer to peer traffic and RCRBs but not for PCI Express Endpoint devices or Root Ports that do not support peer to peer traffic Each bit location within this field corresponds to a Port Arbitration Capability defined below When more than one bit in this field is Set it indicates that the VC resource can be configured to provide different arbitration services Software selects among these capabilities by writing to the Port Arbitration Select field see below Defined bit positions are Bit 0 Non configurable hardware fixed arbitration scheme such as Round Robin RR Bit 1 Weighted Round Robin WRR arbitration with 32 phases Bit 2 WRR arbitration with 64 phases Bit 3 WRR arbitration with 128 phases Bit 4 Time based WRR with 128 phases Bit 5 WRR arbitration with 256 phases Bits 6 7 Reserved MCH default indicates Non configurable hardware fixed arbitration scheme Datasheet Volume 2 Processor Configuration Registers intel 2 20 5 VCORCTL VCO Resource Control Register This register controls the resources associated wit
416. ough the ICC field Refer to the VTd specification for write buffer flushing requirements 62 61 RW Oh Context I nvalidation Request Granularity CI RG Software provides the requested invalidation granularity through this field when setting the ICC field Following are the encodings for the CIRG field 00 Reserved 01 Global I nvalidation request 10 Domain selective invalidation request The target domain id must be specified in the DID field 11 Device selective invalidation request The target source id s must be specified through the SID and FM fields and the domain id that was programmed in the context entry for these device s must be provided in the DID field Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalidation request by clearing the ICC field At this time hardware also indicates the granularity at which the actual invalidation was performed through the CAIG field 196 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 28 2Fh Reset Value 0000000000000000h Access W RW RO Reset esa Bit Attr Value Description Context Actual I nvalidation Granularity CAI G Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reportin
417. pe in context entries 1 Hardware supports pass through translation type in context entries Caching Hints CH 0 Hardware does not support IOTLB caching hints ALH and EH fields in 5 RO Ob context entries are treated as reserved 1 Hardware supports OLTB caching hints through the ALH and EH fields in context entries Extended Interrupt Mode EI M 0 On Intel 64 platforms hardware supports only 8 bit API C IDs xAPIC Mode 4 RO Ob 1 On Intel 64 platforms hardware supports 32 bit API C IDs x2APIC mode The processor supports 16 bit APICIDs and always report this field as 0 This field is valid only when the IR field is reported as Set Interrupt Remapping Support IR 0 Hardware does not support interrupt remapping 3 RO Ob 1 Hardware supports interrupt remapping Implementations reporting this field as Set must also support Queued Invalidation QI 1b Device I OTLB Support DI 0 Hardware does not support device OTLBs 2 RO Ob 1 Hardware supports Device OTLBs Implementations reporting this field as Set must also support Queued Invalidation QI 1b Queued I nvalidation Support QI 1 RO Ob 0 Hardware does not support queued invalidations 1 Hardware supports queued invalidations Coherency C This field indicates if hardware access to the root context page table and interrupt remap structures are coherent Snooped or not 0 RO Ob 0 Indicates hardware accesses to remapping structures are noncoherent 1
418. pecification 16 14 RO 000b Reserved Minimum Powerdown Exit to Non Read command spacing sd1_cr_txp This field indicates the minimum number of clocks to wait following assertion 13 10 RW 0010b of CKE before issuing a non read command 1010 1111 Reserved 0010 1001 2 9 clocks 0000 0001 Reserved 00000000 Self refresh exit count sd1_cr_slfrfsh_exit_cnt 9 1 RW Ob This field indicates the Self refresh exit count Program to 255 This field corresponds to tXSNR tXSRD in the DDR specification 0 RW Ob This bit indicates only 1 DIMM populated sd1_cr_singledimmpop This configuration register indicates that only 1 DIMM is populated Datasheet Volume 2 91 2 8 35 92 Processor Configuration Registers C1PWLRCTRL Channel 1 Partial Write Line Read Control Register This register is to configure the DRAM controller s partial write policies B D F Type 0 0 0 MCHBAR Address Offset 665 666h Reset Value 0000h Access RW RO A Reset goa Bit Attr Value Description 15 14 RO 00b Reserved Read And Merging write Window C1sd_cr_rdmodwr_window i This configuration setting defines the time period in mclks between the 13 8 RW 00000 3 9999900 read and the merging write commands on the DRAM bus This window duration is a function of the tRD and write data latency through the chipset 7 5 RO 000b Reserved Partial Write Trip Threshold PWTRIP 4 0 RW 00000b This configuration setting indicates the
419. perate for full width 28 24 RO z Bit 28 If set 20 lanes The bit indicating the maximum lanes will determine the number of control status bits implemented in Tx Rx Data lane Control Status Registers PRBS_ CAPABILITY 23 RO If set implementation is capable of using specified pattern in bitlock retraining SCRAMBLE_ CAPABILITY 22 RO 7 If set implementation is capable of data scrambling descrambling with LFSR RAS_ CAPABILITY 21 20 RO 7 Any of these bits set indicates Alternate Clock RAS capability available and that corresponding control bits in QPI_ _PH_CTR are implemented 19 18 RV Reserved DETERMI NISM_SUPPORT Determinism supported mode of operations i S Bit 17 If set Master mode of operation supported Component 17 16 RO te i Specification or equivalent document should contain the information about PhyLOSynch Bit 16 If set Slave mode of operation supported 15 11 RV 0 Reserved LINK_WIDTH_CAPABILITY 10 8 RO 7 Bit 8 If set Full Width capable DEBUG_ CAPABILITY Bit7 If set an implementation is not capable of extracting slave electrical parameter from TS Loopback and apply during the test 7 5 RO 0 Bit 6 If set an implementation is not capable of running in Compliance slave mode as well as transitioning to Loopback Pattern from Compliance state Bit 5 If set an implementation is not capable of doing Loopcount Stal RETRAI N_ GRANULARITY 4 RO 0 If set implementation is
420. pre allocated for ME lock Datasheet Volume 2 71 intel 2 8 6 Processor Configuration Registers CODRB3 Channel 0 DRAM Rank Boundary Address 3 Register See CODRBO register description for details B D F Type 0 0 0 MCHBAR 72 Address Offset 206 207h Reset Value 0000h Access RO RW L s Reset Pe Bit Attr Value Description 15 10 RO 00h Reserved Channel 0 DRAM Rank Boundary Address 3 CODRBA3 This register defines the DRAM rank boundary for rank3 of Channel 0 64 MB granularity R3 R2 R1 RO 9 0 RW L 000h RO Total rankO memory size 64 MB R1 Total rank1 memory size 64 MB R2 Total rank2 memory size 64 MB R3 Total rank3 memory size 64 MB This register is locked by Memory pre allocated for MR lock Datasheet Volume 2 Processor Configuration Registers intel 2 8 7 CODRAO1 Channel 0 DRAM Rank 0 1 Attribute Register The DRAM Rank Attribute Registers define the page sizes number of banks to be used when accessing different ranks These registers should be left with their Reset Value all zeros for any rank that is unpopulated as determined by the corresponding CxDRB registers Each byte of information in the CxDRA registers describes the page size of a pair of ranks Channel and rank map ChO RankO 1 208h 209h ChO Rank2 3 20Ah 20Bh Ch1 RankO 1 608h 609h Ch1 Rank2 3 60Ah 60Bh DRA
421. ption 15 12 RO Oh Reserved 11 RO 0b Discard Timer SERR Enable DTSERRE Not Applicable or Implemented Hardwired to 0 10 RO Ob Discard Timer Status DTSTS l Not Applicable or Implemented Hardwired to 0 304 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset 3E 3Fh Reset Value 0000h Access RO RW P Reset ere Bit Attr Value Description 9 RO Ob Secondary Discard Timer SDT Not Applicable or Implemented Hardwired to 0 8 RO Ob Primary Discard Timer PDT Not Applicable or Implemented Hardwired to 0 7 RO Ob Fast Back to Back Enable FB2BEN Not Applicable or Implemented Hardwired to 0 Secondary Bus Reset SRESET 6 RW Ob Setting this bit triggers a hot reset on the corresponding PCI Express Port This will force the LTSSM to transition to the Hot Reset state using Recovery from LO LOs or L1 states Master Abort Mode MAMODE Does not apply to PCI Express Hardwired to 0 VGA 16 bit Decode VGA16D Enables the PCI to PCI bridge to provide 16 bit decoding of VGA I O address precluding the decoding of alias addresses every 1 KB This bit only has 4 RW Ob meaning if bit 3 VGA Enable of this register is also set to 1 enabling VGA 1 O decoding and forwarding by the bridge 0 Execute 10 bit address decodes on VGA I O accesses 1 Execute 16 bit address decodes on VGA I O accesses VGA Enable VGAEN 3 RW Ob This bit control
422. quely identifies any PCI device B D F Type 0 6 0 PCI Address Offset 2 3h Reset Value 0043h Access RO Reset noig Bit Attr Value Description Device Identification Number Upper Bits DI D6UB 15 4 RO 004h Identifier assigned to device 6 virtual PCI to PCI bridge PCI Express Graphics port Device Identification Number Hardware controlled DI D6HW 3 2 RO 00b Identifier assigned to the device 6 virtual PCI to PCI bridge PCI Express Graphics port Device Identification Number Lower Bits DI D6LB 1 0 RO 11b Identifier assigned to the device 6 virtual PCI to PCI bridge PCI Express Graphics port 2 19 3 PCI CMD6 PCI Command Register B D F Type Address Offset Reset Value Access 0 6 0 PCI 4 5h 0000h RO RW Bit Attr Reset Value Description 15 11 RO 00h Reserved 10 RW Ob INTA Assertion Disable I NTAAD 0 This device is permitted to generate INTA interrupt messages 1 This device is prevented from generating interrupt messages Any INTA emulation interrupts already asserted must be de asserted when this bit is set Only affects interrupts generated by the device PCI INTA from a PME or Hot Plug event controlled by this command register It does not affect upstream MSIs upstream PCI INTA INTD assert and de assert messages Ob Fast Back to Back Enable FB2B Not Applicable or Implemented Hardwired to 0 Ob S
423. queued invalidations implement this field as reserved 2 15 23 IECTL_REG Invalidation Event Control Register This register specifies the invalidation event interrupt control bits This register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register Access B D F Type Address Offset Reset Value 0 0 0 VCOPREMAP A0 A3h 00000000h RW RO Bit Attr Reset Value Description 31 RW Ob Interrupt Mask IM 0 No masking of interrupt When a invalidation event condition is detected hardware issues an interrupt message using the Invalidation Event Data amp Invalidation Event Address register values 1 This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is Set 30 RO Ob Interrupt Pending IP Hardware sets the IP field whenever it detects an interrupt condition Interrupt condition is defined as e An Invalidation Wait Descriptor with Interrupt Flag IF field Set completed setting the IWC field in the Invalidation Completion Status register e Ifthe IWC field in the Invalidation Completion Status register was already set at the time of setting this field it is not treated as a new interrupt condition The IP field is kept set by hardware while the interrupt message is held pendin
424. quirements Advanced Fault Logging AFL 3 RO Ob 0 Indicates advanced fault logging not supported Only primary fault logging is supported 1 Indicates advanced fault logging is supported Number of domains supported ND 000b Hardware supports 4 bit domain ids with support for up to 16 domains 001b Hardware supports 6 bit domain ids with support for up to 64 domains 010b Hardware supports 8 bit domain ids with support for up to 256 domains 2 0 RO 010b 011b oe supports 10 bit domain ids with support for up to 1024 omains 100b Hardware supports 12 bit domain ids with support for up to 4K domains 101b Hardware supports 14 bit domain ids with support for up to 16K domains 110b Hardware supports 16 bit domain ids with support for up to 64K domains 111b Reserved Datasheet Volume 2 189 intel Processor Configuration Registers 2 15 3 ECAP_REG Extended Capability Register This register reports DMA remapping hardware extended capabilities Access B D F Type Address Offset Reset Value 0 0 0 VCOPREMAP 10 17h 0000000000001000h RO Bit Attr Reset Value Description 63 32 RO 90000009 Reserved 31 24 RO 00h Number of I OTLB I nvalidation Units NIU This field indicates a value of N 1 where N is the number of I OTLB invalidation units supported by hardware Each IOTLB invalidation unit consists of two registers A 64 bit OTLB Invalidation R
425. r Bit Attr Value Description Virtual Channel Enable VCE 0 Virtual Channel is disabled 1 Virtual Channel is enabled See exceptions below Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete When VC Negotiation Pending bit is cleared a 1 read from this VC Enable bit indicates that the VC is enabled Flow Control Initialization is completed for the PCI Express port A 0 read from this bit indicates that the Virtual Channel is currently disabled 31 RW Ob BIOS Requirement 1 To enable a Virtual Channel the VC Enable bits for that Virtual Channel must be set in both Components on a Link 2 To disable a Virtual Channel the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link 3 Software must ensure that no traffic is using a Virtual Channel at the time it is disabled 4 Software must fully disable a Virtual Channel in both Components on a Link before re enabling the Virtual Channel 30 27 RO Oh Reserved Virtual Channel ID VCI D 26 24 RW 001b Assigns a VC ID to the VC resource Assigned value must be non zero This field can not be modified when the VC is already enabled 23 20 RO Oh Reserved Port Arbitration Select PAS This field configures the VC resource to provide a particular Port Arbitration 19 17 RW 000b Pees A service Valid value for this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of t
426. r The actual generation of the SERR message is globally enabled for Device 0 using the PCI Command register B D F Type 0 0 0 PCI Address Offset CA CBh Reset Value 0000h Access RO RW Reset eee Bit Attr Value Description 15 12 RO Oh Reserved SERR on Processor Thermal Sensor Event TSESERR 1 The processor generates a DMI SERR special cycle when bit 11 of the 11 RW Ob ERRSTS is set The SERR must not be enabled at the same time as the SMI for the same thermal sensor event 0 Reporting of this condition using SERR messaging is disabled 10 RO Ob Reserved SERR on LOCK to non DRAM Memory LCKERR 9 RW Ob 1 The processor will generate a DMI SERR special cycle whenever a processor lock cycle is detected that does not hit DRAM 0 Reporting of this condition using SERR messaging is disabled 8 RW Ob Reserved 7 2 RO Oh Reserved 1 RW Ob Reserved 0 RW Ob Reserved Datasheet Volume 2 63 Processor Configuration Registers 2 7 26 SMI CMD SMI Command Register This register enables various errors to generate an SMI DMI special cycle When an error flag is set in the ERRSTS register it can generate an SERR SMI or SCI DMI special cycle when enabled in the ERRCMD SMICMD or SCICMD registers respectively Note that one and only one message type can be enabled B D F Type 0 0 0 PCI Address Offset CC CDh Reset Value 0000h Access RO RW
427. r Internal Processor DeVICES ccceceeseeee eee eatenteeenees 38 2 4 PCI Express Device 0 Register Address Map cc cceeeeee eee e eee ee eee e eee eee eee ee natn ea enes 45 2 5 MCHBAR Register Address Map sssssssrssssrssrrtrrrstrt trnu t rnt nn rnnr E NEEAE EEEE e ene nant taee 66 2 6 DRAM Rank Attribute Register Programming ccceeee cece eee eee e ee eee teen eaee 73 2 7 PCI Express Device 1 Register Address Map ccccec eee eee eee ee ee eee e ee tee eene natn ed 115 2 8 Device 1 Extended Configuration Register Address Map ccsceeeee teens tena ea ea ee 156 2 9 DMI Register Address Map ccceceeee eee eee nena eee rete teeta eee n ees 161 2 10 PCI Device 2 Function 0 Register Address Map ccccccseceeseeeer eet eeeeeeeeenteaenneneed 174 2 11 MMI and PEG VCO VCp Remap Register Address Map ccceeeeeeeeeeeee eee eeeeeaeaee 185 2 12 DMI VC1 Remap Register Address Map cccececeee eee eee eee eee teeta 221 2 13 GFXVTBAR Register Address Map sssssssrssrsssrrsrrttrrnttin neta ened 255 2 14 PCI Device 6 Register Address Map ssssssssressrrarsrsernrrersrrnrirrerunsrrnrunnernererserans 288 2 15 Device 6 Extended Configuration Register Address Map c cceeeeeeeeeee tetas nena eaee 328 2 16 Intel TXT Register Address Map ccccccsessesececseceeececeseceeesusesssenaneneneceesenesesenens 332 3 1 Register Terminology vases nade Ait aie aes aac
428. r all Root Ports and Switch downstream ports supporting Links wider than x1 and or multiple Link 21 RO 1b speeds This field is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Devices that do not implement the Link Bandwidth Notification capability must hardwire this bit to Ob Data Link Layer Link Active Reporting Capable DLLLARC For a Downstream Port this bit must be set to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine For a hot plug capable Downstream 20 RO 0b Port as indicated by the Hot Plug Capable field of the Slot Capabilities register this bit must be set to 1b For Upstream Ports and components that do not support this optional capability this bit must be hardwired to Ob Surprise Down Error Reporting Capable SDERC For a Downstream Port this bit must be set to 1b if the component supports 19 RO Ob the optional capability of detecting and reporting a Surprise Down error condition For Upstream Ports and components that do not support this optional capability this bit must be hardwired to Ob Clock Power Management CPM A value of 1b in this bit indicates that the component tolerates the removal of any reference clock s when the link is in the L1 and L2 3 Ready link states A value of 0b indicates the component does not have this capability and
429. r are programmed to provide the same remapping results as the structures referenced by the previous interrupt remap table pointer Clearing this bit has no effect The value returned on a read of this field is undefined Datasheet Volume 2 263 2 18 5 264 Processor Configuration Registers B D F Type 0 2 0 GFXVTBAR Address Offset 18 1Bh Reset Value 00000000h Access W RO RW Reset A Bit Attr Value Description Compatibility Format I nterrupt CFI This field is valid only for Intel 64 implementations supporting interrupt remapping Software writes to this field to enable or disable Compatibility Format interrupts on Intel 64 platforms The value in this field is effective only when interrupt remapping is enabled and Legacy Interrupt Mode is active 0 Block Compatibility format interrupts 23 RO 0b 1 Process Compatibility format interrupts as pass through bypass interrupt remapping Hardware reports the status of updating this field through the CFIS field in the Global Status register Refer to the VTd specification for details on Compatibility Format interrupt requests The value returned on a read of this field is undefined This field is not implemented 22 0 RO 000000h Reserved GSTS_REG Global Status Register This register reports general remapping hardware status B D F Type Address Offset Reset Value Access 0 2 0 GFXVTBAR 1C 1Fh
430. r in the slot reflected by the logical OR of the Physical Layer in band presence detect mechanism and if present any out of band presence detect mechanism defined for the slot s corresponding form factor Note that the in band presence detect mechanism requires that power be applied to an adapter for its presence to be detected Consequently form factors that require a power controller for hot plug must 6 RO Ob implement a physical pin presence detect mechanism 0 Slot Empty 1 Card Present in slot This register must be implemented on all Downstream Ports that implement slots For Downstream Ports not connected to slots where the Slot Implemented bit of the PCI Express Capabilities Register is Ob this bit must return 1b Reserved for MRL Sensor State MSS 5 RO Ob This register reports the status of the MRL sensor if it is implemented 0 MRL Closed 1 MRL Open Reserved for Command Completed CC If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register this bit is set when a hot plug command has completed and the Hot Plug Controller is ready to accept a subsequent command The Command Completed status bit 4 RO Ob is set as an indication to host software that the Hot Plug Controller has processed the previous command and is ready to receive the next command it provides no assurance that the action corresponding to the command is complete If Command Completed noti
431. r or not the Master Data Parity Error bit in the PCI Status 6 RW Ob register can bet set 0 Master Data Parity Error bit in PCI Status register can NOT be set 1 Master Data Parity Error bit in PCI Status register CAN be set 5 RO Ob VGA Palette Snoop VGAPS Not Applicable or Implemented Hardwired to 0 4 RO Ob Memory Write and I nvalidate Enable MWI E Not Applicable or Implemented Hardwired to 0 3 RO Ob Special Cycle Enable SCE Not Applicable or Implemented Hardwired to 0 Bus Master Enable BME This bit controls the ability of the PEG port to forward Memory and 10 Read Write Requests in the upstream direction 0 This device is prevented from making memory or 10 requests to its primary bus Note that according to PCI Specification as MSI interrupt messages are in band memory writes disabling the bus master enable bit prevents this device from generating MSI interrupt messages or passing them from its secondary bus to its primary bus Upstream 2 RW 0b memory writes reads 1O writes reads peer writes reads and MSIs will all be treated as illegal cycles Writes are forwarded to memory address C0000h with byte enables de asserted Reads will be forwarded to memory address C0000h and will return Unsupported Request status or Master abort in its completion packet 1 This device is allowed to issue requests to its primary bus Completions for previously issued memory read requests on the primary bus will be issued when the da
432. re accesses to the root context and page table 0 RO Ob structures are non coherent non snoop 1 Indicates that hardware accesses to the root context and page table structures are coherent snoop Hardware writes to the advanced fault log is required to be coherent 2 15 4 GCMD_REG Global Command Register This register controls DMA remapping hardware If multiple control fields in this register need to be modified software must serialize through multiple writes to this register B D F Type 0 0 0 VCOPREMAP Address Offset 18 1Bh Reset Value 00000000h Access W WO RO Reset S A Bit Attr Value Description Translation Enable TE Software writes to this field to request hardware to enable disable DMA remapping hardware 0 Disable DMA remapping hardware 1 Enable DMA remapping hardware Hardware reports the status of the translation enable operation through the TES field in the Global Status register Before enabling or re enabling DMA remapping hardware through this field software must e Setup the DMA remapping structures in memory e Flush the write buffers through WBF field if write buffer flushing is reported as required e Set the root entry table pointer in hardware through SRTP field 31 WwW Ob e Perform global invalidation of the context cache and global invalidation of OTLB e If advanced fault logging supported setup fault log pointer through SFL field and enab
433. reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 11 10 RV 0 Reserved PAM1_LOENABLE 0C0000h 0C3FFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from OC0000h to OC3FFFh 9 8 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 7 6 RV 0 Reserved PAMO_HIENABLE OFOOOOh OFFFFFh Attribute HIENABLE This field controls the steering of read and write cycles that address the BIOS area from OFOOOOh to OFFFFFh 5 4 RW 0 00 DRAM Disabled All accesses are directed to ESI 01 Read Only All reads are sent to DRAM All writes are forwarded to ESI 10 Write Only All writes are send to DRAM Reads are serviced by ESI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 3 0 RV 0 Reserved Datasheet Volume 2 Intel QuickPath Architecture System Address Decode Register Description 3 6 2 SAD_PAM456 This register is for legacy Device 0 Function 0 94h 97h address space Device 0 Function 1 Offset 44h Access as a Dword 5 Res
434. register e Hardware detected Device OTLB invalidation completion time out setting the ITE field in the Fault Status register If any of the status fields in the Fault Status register was already Set at the 30 RO Ob time of setting any of these fields it is not treated as a new interrupt condition The IP field is kept Set by hardware while the interrupt message is held pending The interrupt message could be held pending due to the interrupt mask IM field being Set or other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either a change in the transient hardware condition that caused the interrupt message to be held pending or due to software clearing the IM field e Software servicing all the pending interrupt status fields in the Fault Status register as follows When primary fault logging is active software clearing the Fault F field in all the Fault Recording registers with faults causing the PPF field in the Fault Status register to be evaluated as Clear Software clearing other status fields in the Fault Status register by writing back the value read from the respective fields 29 0 RO 00 00b Reserved 270 Datasheet Volume 2 Processor Configuration Registers 2 18 10 FEDATA_REG Fault Event Data Register This register specifies
435. register This bit may only be set to a zero by a hardware reset Once locked writing a 0 to bit has no effect EXTTSO and EXTTS1 input signal pins are dedicated for external thermal sensor use An asserted External Thermal Sensor Trip signal can also cause a SCI SMI SERR or INTR interrupt in the same manner as the Internal 15 RW O Ob Sensor can A 0 on the pins can be used to trigger throttling If both internal sensor throttling and external sensor throttling are enabled either can initiate throttling The ASO and AS1 bits of this register allow control of what action is triggered by external sensor trips The processor Throttling select bit controls the type of throttling action that will happen and the ASO AS1 bits control what trip actions will result 0 External Sensor input is disabled 1 External Sensor input is enabled 14 RO Ob Reserved Select between EXTTS PIN O and 1 EXTTPINSEL 13 RW L Ob 0 Use EXTTS Pin 0 for Thermal throttling based of EXTTPMTRIP EXTTFMX and SD2X 1 Use EXTTS Pin 1 for the above EXTTS Based Power Monitor Trip EXTTPMTRI P When this is set on extts bit 0 can be programmed to look like a power monitor trip 1 will be OR ed with the Global monitor Gfx monitor so that when programmed for gfx throttle when EXTTS is asserted at the sample 12 RW L Ob point it will look like a monitor trip and force RP down by the programmed amount 2 EXTTS is only sampled on the sampling window for graphics thro
436. register is decoded by hardware as all Os B D F Type 0 0 0 VCOPREMAP Address Offset 70 77h Reset Value 0000000000000000h Access RW RO Reset gia Bit Attr Value Description Protected High Memory Base PHMB 00000000 This register specifies the base of size aligned protected memory region in 63 21 RW oooh system memory Hardware may not utilize bits 63 HAW where HAW is the host address width The protected high memory region has a minimum size of 2 MB and must be size aligned 20 0 RO 000000h Reserved Datasheet Volume 2 205 m t 1 Processor Configuration Registers 2 15 18 2 15 19 206 PHMLI MI T_REG Protected High Memory Limit Register Register to setup the limit address of DMA protected high memory region This register must be setup before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled When LT CMD LOCK PMRC command is invoked this register is locked treated RO When LT CMD UNLOCK PMRC command is invoked this register is unlocked treated RW This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as 0 in the Capability register The alignment of the protected high memory region limit depends on the number of reserved bits N of this register Software may determine the value of N by writing all 1 s to this register and finding most signific
437. res Software may program the DMA remapping structures to allow or block DMA to the protected memory regions 1 DMA accesses to protected memory regions are handled as follows 31 RW Ob If DMA remapping is not enabled DMA requests to protected memory regions are blocked These DMA requests are not recorded or reported as DMA remapping faults If DMA remapping is enabled hardware may or may not block DMA to the protected memory region s Software must not depend on hardware protection of the protected memory regions and must ensure the DMA remapping structures are properly programmed to not allow DMA to the protected memory regions Hardware reports the status of the protected memory enable disable operation through the PRS field in this register Hardware implementations supporting DMA draining must drain any in flight translated DMA requests queued within the Root Complex before indicating the protected memory region as enabled through the PRS field 30 1 RO 00 00b Reserved Protected Region Status PRS 0 RO Ob This field indicates the status of protected memory region s 0 Protected memory region s disabled 1 Protected memory region s enabled Datasheet Volume 2 273 m t 1 Processor Configuration Registers 2 18 15 274 PLMBASE_REG Protected Low Memory Base Register This register is used to set up the base address of DMA protected low memory region below 4 GB This register must be set up b
438. ress G 1 GMCH will not forward to PCI Express G any I O transactions addressing the last 768 bytes in each 1 KB block even if the addresses are within the range defined by the OBASE and IOLIMIT registers Datasheet Volume 2 131 Processor Configuration Registers B D F Type 0 1 0 PCI Address Offset 3E 3Fh Reset Value 0000h Access RO RW Reset EA Bit Attr Value Description SERR Enable SERREN 0 No forwarding of error messages from secondary side to primary side 1 RW Ob that could result in an SERR 1 ERR_COR ERR_NONFATAL and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register Parity Error Response Enable PEREN Controls whether or not the Master Data Parity Error bit in the Secondary Status register is set when the MCH receives across the link upstream a 0 RW Ob Read Data Completion Poisoned TLP 0 Master Data Parity Error bit in Secondary Status register can NOT be set 1 Master Data Parity Error bit in Secondary Status register CAN be set 2 10 25 MSAC Multi Size Aperture Control Register This register determines the size of the graphics memory aperture in function 0 and in the trusted space Only the system BIOS will write this register based on pre boot address allocation efforts but the graphics may read this register to determine the correct aperture size System BIOS needs to save this value on boot so that
439. ress Mask 512ADMSK This bit is either part of the Memory Base Address R W or part of the Address Mask RO depending on the value of MSAC 2 1 See MSAC Dev2 Function 0 offset 62h for details 28 RW L Ob 256 MB Address Mask 256ADMSK 27 RW L 0b This bit is either part of the Memory Base Address R W or part of the Address Mask RO depending on the value of MSAC 2 1 See MSAC Device 2 Function 0 offset 62h for details Address Mask ADM 26 4 RO opo90gh Hardwired to Os to indicate at least 128MB address range Prefetchable Memory PREFMEM 3 RO 1b Hardwired to 1 to enable prefetching Memory Type MEMTYP 2 1 RO 10b 00 32 bit address 10 64 bit address Memory 10 Space MI OS Hardwired to 0 to indicate memory space Datasheet Volume 2 Processor Configuration Registers 2 13 12 intel I OBAR I O Base Address Register This register provides the Base offset of the I O registers within Device 2 Bits 15 3 are programmable allowing the I O Base to be located anywhere in 16bit I O Address Space Bits 2 1 are fixed and return zero bit 0 is hardwired to a one indicating that 8 bytes of I O space are decoded Access to the 8Bs of 1O space is allowed in PM state DO when IO Enable PCICMD bit 0 set Access is disallowed in PM states D1 D3 or if 1O Enable is clear or if Device 2 is turned off or if Internal graphics is disabled thru the fuse or fuse override mechanis
440. ress Offset Reset Value 0 0 0 VCOPREMAP 28 2Fh 0000000000000000h W RW RO Bit Attr Reset Value Description 63 RW Ob Invalidate Context Cache ICC Software requests invalidation of context cache by setting this field Software must also set the requested invalidation granularity by programming the CIRG field Software must read back and check the ICC field to be clear to confirm the invalidation is complete Software must not update this register when this field is set Hardware clears the ICC field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the CAIG field Software must not submit another invalidation request through this register while the ICC field is set Software must submit a context cache invalidation request through this field only when there are no invalidation requests pending at this DMA remapping hardware unit Refer to the VTd specification for software programming requirements Since information from the context cache may be used by hardware to tag IOTLB entries software must perform domain selective or global invalidation of OTLB after the context cache invalidation has completed Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flushing before reporting invalidation complete to software thr
441. rmed before enabling or re enabling after disabling DMA remapping through the TE field After a root table pointer set operation software must globally invalidate 30 Ww Ob the context cache and then globally invalidate the OTLB This is required to ensure hardware uses only the remapping structures referenced by the new root table pointer and not any stale cached entries While DMA remapping is active software may update the root table pointer through this field However to ensure valid in flight DMA requests are deterministically remapped software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root table pointer Clearing this bit has no effect The value returned on a read of this field is undefined Set Fault Log SFL This field is valid only for implementations supporting advanced fault logging Software sets this field to request hardware to set update the fault log pointer used by hardware The fault log pointer is specified through Advanced Fault Log register 29 RO Ob Hardware reports the status of the fault log set operation through the FLS field in the Global Status register The fault log pointer must be set before enabling advanced fault logging through EAFL field Once advanced fault logging is enabled the fault log pointer may be updated through this field while DMA remapping is active
442. rottling Control register 1 processor throttling based on the settings in the Device 0 MCHBAR processor Throttling Control Register and the Device 2 Graphics Render Throttle Control Register Catastrophic and Hot Hardware controlled Thermal Throttle Duty Cycle otherwise TTS has no meaning Software must keep this bit at 0 EXTTS1 Action Select AS1 Lockable by EXTTSCS External Sensor Enable If External Thermal Sensor 5 RW L Ob Enable 1 then l l l 0 The external sensor trip functions same as a Thermometer mode hot trip 1 The external sensor trip functions same as a Thermometer mode aux0 trip EXTTSO Action Select ASO Lockable by EXTTSCS External Sensor Enable If External Thermal Sensor 4 RW L Ob Enable 1 then l l 0 The external sensor trip functions same as a Thermometer mode catastrophic trip 1 The external sensor trip functions same as a Thermometer mode hot trip EXTTSO Trip Indicator SOTI 1 An externally monitored temperature is exceeding the programmed 3 RO 0b setting of its external thermal sensor 0 This externally monitored temperature is not exceeding the programmed setting of its external thermal sensor EXTTS1 Trip Indicator S1TI 1 An externally monitored temperature is exceeding the programmed 2 RO Ob setting of its external thermal sensor 0 This externally monitored temperature is not exceeding the programmed setting of its external thermal sensor 1 RO Ob Reserved External Thermal Sensor Signa
443. rrors or error messages received across the link Other bits also control the full scope of related error reporting Non Fatal Error Reporting Enable NERE 1 RW Ob When set this bit enables signaling of ERR_NONFATAL to the Root Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Correctable Error Reporting Enable CERE When set this bit enables signaling of ERR_CORR to the Root Control register 0 RW Ob due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting 140 Datasheet Volume 2 Processor Configuration Registers intel 2 10 38 DSTS Device Status Register This register reflects status corresponding to controls in the Device Control register The error reporting bits are in reference to errors detected by this device not errors messages received across the link Access B D F Type Address Offset Reset Value 0 1 0 PCI AA ABh 0000h RO RW1C Bit Attr Reset Value Description RO 000h Reserved and Zero Reserved for future R WC S implementations software must use 0 for writes to bits RO Ob Transactions Pending TP 0 All pending transactions including completions for any outstanding non posted requests on any used virtual channel have b
444. rrrrrrrrrrrrrrrrsssrrrrrrrrrrnne 21 22 22 TSEG amenar a EE E E A 22 2 2 2 3 Protected Memory Range PMR programmable 0cceeeeeeeee 22 2 2 2 4 DRAM Protected Range DPR ccccssecceseet eee eeeee eet eeteeeen eat enennene es 23 2 2 2 5 Pre allocated Memory ceceeee eee ee reece teen e eee eae e ee ee tee tana tains 23 2 2 2 6 Graphics Stolen SPACOS i veevrs iss inani a a e EE TA E 23 2 2 2 7 Intel Management Engine Intel ME UMA ccccceeeeseceeceeeeeeeees 24 2 2 2 8 PCI Memory Address Range TOLUD 4 GB cceceeeeceeneee eee en een ees 24 2 2 2 9 APIC Configuration Space FECO_OO00Oh FECF_FFFFh 04 26 2 2 2 10 High BIOS Area ci cvehottities nisi i Eae EENES eles Leet feveedals 26 2 2 3 Main Memory Address Space 4 GB to TOUUD ccccseceeeeneeaeeneeeeneenees 27 2 2 3 1 Programming Model ii ciccics a ciseessieaeiadeceeeedienscnene cevbeuaeecsraneens 28 2 2 4 PCI Express Configuration Address Space ccceceee eee ee eee e eee eaten nea 33 2 2 5 PCI Express Graphics Attach PEG ccccecscese eee eee eset eeteeeaeeateateeeanentaas 33 2 2 6 Graphics Memory Address Ranges ceee cece rene eee eee eee teeter ed 34 2 2 6 1 IOBAR Mapped Access to Device 2 MMIO Space cceceeeeeeeee ee eee 34 2 2 7 System Management Mode SMM cccccccecceeeee eee eee eee eeeeeeeteneeeeeneenentnnes 35 2 2 8 SMM and VGA Access through GTT TLB cccecee eect nent e
445. rsion A value of 011b indicates that this function complies with revision 1 2 of the PCI Power Management Interface Specification Pointer to Next Capability PNC This field contains a pointer to the next item in the capabilities list If MSI CH 15 8 RO 90h CAPL 0 7Fh is 0 then the next item in the capabilities list is the Message Signaled Interrupts MSI capability at 90h If MSICH CAPL 0 7Fh is 1 then the next item in the capabilities list is the PCI Express capability at AOh Capability ID CID 7 0 RO Olh Value of 01h identifies this linked list item capability structure as being for PCI Power Management registers Datasheet Volume 2 Processor Configuration Registers intel 2 19 26 PM_CS6 Power Management Control Status Register B D F Type 0 6 0 PCI Address Offset 84 87h Reset Value 00000008h Access RO RW RW S Reset pre Bit Attr Value Description Reserved 31 16 RO 0000h Not Applicable or Implemented Hardwired to 0 15 RO Ob PME Status PMESTS Indicates that this device does not support PMEB generation from D3cold Data Scale DSCALE 14 13 RO 00b Indicates that this device does not support the power management data register Data Select DSEL 12 9 RO Oh Indicates that this device does not support the power management data register PME Enable PMEE Indicates that this device does not generate PMEB assertion from any D state 8
446. rupt condition occurs when hardware records a fault in the first fault record at index 0 of the current fault log and sets the APF field in the Advanced Fault Log register If the APF field was already set at the time of detecting recording a fault it is not treated as a new interrupt condition The IP field is kept set by hardware while the interrupt message is held 30 RO Ob pending The interrupt message could be held pending due to interrupt mask IM field being set or due to other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field e Software servicing the interrupting condition through one of the following ways When primary fault logging is active software clearing the Fault F field in all the Fault Recording registers with faults causing the PPF field in Fault Status register to be evaluated as clear When advanced fault logging is active software clearing the APF field in Advanced Fault Log register 29 0 RO 00 00b Reserved Datasheet Volume 2 199 intel Processor Configuration Registers 2 15 10 FEDATA_REG Fault Event Data Register This register specifies the interrupt message data
447. ry and to have a size granularity of 1 MB The processor positively decodes memory accesses to PCI Express memory address space as defined by the following equations Memory_Base_Address lt Address lt Memory_Limit_Address Prefetchable_Memory_Base_Address lt Address lt Prefetchable_Memory_Limit_Address The window size is programmed by the plug and play configuration software The window size depends on the size of memory claimed by the PCI Express device Normally these ranges will reside above the Top of Low Usable DRAM and below High BIOS and APIC address ranges They MUST reside above the top of low memory TOLUD if they reside below 4 GB and MUST reside above top of upper memory TOUUD if they reside above 4 GB or they will steal physical DRAM memory space It is essential to support a separate Pre fetchable range in order to apply USWC attribute from the processor point of view to that range The USWC attribute is used by the processor for write combining Note that the processor memory range registers described above are used to allocate memory address space for any PCI Express devices sitting on PCI Express that require such a window The PCICMD1 register can override the routing of memory accesses to PCI Express In other words the memory access enable bit must be set to enable the memory base limit and pre fetchable base limit windows The upper PMUBASE PMULIMIT registers have been implemented for PCI Express Specif
448. s 001 Reserved 34 32 RO 010 Reserved 011 Reserved 100 Reserved 101 GMCH capable of up to DDR3 1333 MHz 110 GMCH capable of up to DDR3 1067 MHz 111 Reserved 31 0 RO Reserved 2 7 29 MCSAMPML Memory Configuration System Address Map and Pre allocated Memory Lock Register B D F Type 0 0 0 PCI Address Offset F4h Reset Value 00h Access RW O RW L RW L K Reset er Bit Attr Value Description 7 5 RW O 000b Reserved 4 RW L 0 Reserved Lock Mode LOCKMODE LOCKMODE and ME_SM_LOCK bit 0 must always be programmed to the 3 RW L K 0 same value See bit 0 for description details 0 Registers are not locked 1 Registers are locked 2 RW L 0 Reserved RO 0 Reserved ME Stolen Memory Lock ME_SM_LOCK When ME_SM_LOCK is set to 1 all registers related to MCH configuration become read only BIOS will initialize configuation bits related to MCH configuration and then use ME_SM_lock to lock down the MCH configuration in the future so that no application software or BIOS itself can violate the integrity of DRAM including ME stolen memory space 0 RW L K 0 If BIOS writes this bit to 1 bit 3 LOCKMODE bit must also be written to 1 to ensure proper register lockdown If BIOS writes this bit to 0 bit 3 LOCKMODE bit must also be written to 0 This bit and the LOCKMODE bit 3 should never be programmed differently PCI device 0 and MCHBAR registers affected by this bit are d
449. s This register is treated as reserved by implementations reporting both Queued I nvalidation QI and Extended Interrupt Mode EIM as not supported in the Extended Capability register B D F Type 0 0 0 DMI VCLREMAP Address Offset AC AFh Reset Value 0000_0000h Access RO Reset ERS Bit Attr Value Description Message Upper Address MUA Hardware implementations supporting Queued Invalidations and Extended 31 0 RO 0000_000 Interrupt Mode are required to implement this register Oh Software requirements for programming this register are described in the VTd specification Hardware implementations not supporting Queued Invalidations and Extended Interrupt Mode may treat this field as reserved 2 16 27 IRTA_REG Interrupt Remapping Table Address Register This register provides the base address of Interrupt remapping table The register is treated as reserved by implementations reporting Interrupt Remapping IR as not supported in the Extended Capability register B D F Type 0 0 0 DMI VCLREMAP Address Offset B8 BFh Reset Value 0000000000000000h Access RO Reset re Bit Attr Value Description Interrupt Remapping Table Address I RTA 63 12 RO 00000000 This field points to the base of the 4 KB aligned interrupt remapping table 00000h Hardware ignores and not 63 HAW where HAW is the width Reads of this field returns last value programmed to it
450. s ensured to be serviced If all of them must be serviced the device must not generate the same message again until the driver services the earlier one B D F Type 0 1 0 PCI Address Offset 92 93h Reset Value 0000h Access RO RW Bit Attr Pi Description 15 8 RO 00h Reserved 64 bit Address Capable 64AC Hardwired to 0 to indicate that the function does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64 bit RO Ob memory address This may need to change in future implementations when addressable system memory exceeds the 32b 4 GB limit Multiple Message Enable MME System software programs this field to indicate the actual number of 6 4 RW 000b messages allocated to this device This number will be equal to or less than the number actually requested The encoding is the same as for the MMC field below Multiple Message Capable MMC System software reads this field to determine the number of messages being requested by this device 000 1 All of the following are reserved in this implementation 001 2 3 1 RO 000b 010 4 011 8 100 16 101 32 110 Reserved 111 Reserved MSI Enable MSIEN This bit controls the ability of this device to generate MSIs 0 RW Ob 0 MSI will not be generated 1 MSI will be generated when we receive PME or HotPlug messages INTA will not be generated and INTA Status PCISTS1 3 will not be set Datas
451. s access to CSEG TSEG HSEG ranges DMI Interface and PCI Express masters are not allowed to access the SMM space SMM Regions SMM Space Enabled Transaction Address Space DRAM Space DRAM Compatible C 000A_0000h to 000B_FFFFh 000A_0000h to 000B_FFFFh TSEG T TOLUD STOLEN TSEG to TOLUD STOLEN TSEG to TOLUD STOLEN TOLUD STOLEN SMM and VGA Access through GTT TLB Accesses through GTT TLB address translation SMM DRAM space are not allowed Writes will be routed to Memory address 000C_0000h with byte enables de asserted and reads will be routed to Memory address 000C_0000h If a GTT TLB translated address hits SMM DRAM space an error is recorded in the PGTBL_ER register PCI Express and DMI Interface originated accesses are never allowed to access SMM space directly or through the GTT TLB address translation If a GTT TLB translated address hits enabled SMM DRAM space an error is recorded in the PGTBL_ER register PCI Express and DMI Interface write accesses through GMADR range will not be snooped Only PCI Express and DMI assesses to GMADR linear range defined using fence registers are supported PCI Express and DMI Interface tileY and tileX writes to GMADR are not supported If when translated the resulting physical address is to enabled SMM DRAM space the request will be remapped to address 000C_0000h with de asserted byte enables PCI Express and DMI Interface read accesses to the GMADR range are not
452. s bit is static and will be modified mode mode Ob Global OTLB Invalidation Promotion GLBI OTLBI NV This bit controls the IOTLB Invalidation behavior of the DMA remap engine When this bit is set any type of OTLB Invalidation valid or invalid will be promoted to Global OTLB Invalidation Ob Global Context When this bit is s Invalidation Promotion GLBCTXTI NV This bit controls the Context Invalidation behavior of the DMA remap engine et any type of Context Invalidation valid or invalid will be promoted to Global Context I nvalidation 220 Datasheet Volume 2 Processor Configuration Registers 2 16 DMI VC1 REMAP Registers Table 2 12 DMI VC1 Remap Register Address Map Address Register s Offset Symbol Register Name Reset Value Access 0 3h VER_REG Version Register 00000010h RO 8 Fh CAP_REG Capability Register 00C9008020E30272h RO 10 17h ECAP_REG Extended Capability Register 0000000000001000h RO 18 1Bh GCMD_REG Global Command Register 00000000h W RO 1C 1Fh GSTS_REG Global Status Register 00000000h RO 20 27h RTADDR_REG Root Entry Table Address Register 0000000000000000h RW RO 28 2Fh CCMD_REG Context Command Register 0000000000000000h RME SC RW FSTS_REG Fault Status Register RWIC S 34 37h 00000000h RO V S RO 38 3Bh FECTL_REG Fault Event Control Register 80000000h RW RO 3C 3Fh FEDA
453. s errata which may cause the product to deviate from published specifications Current characterized errata are available on request 4lntel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor_number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor_number for details No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific software for some uses For more information see http www intel com technology security Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machin
454. s fault zero 22 RO 1b length DMA read requests to write only pages 1 Indicates the remapping hardware unit supports zero length DMA read requests to write only pages Maximum Guest Address Width MGAW This field indicates the maximum DMA virtual addressability supported by remapping hardware The Maximum Guest Address Width MGAW is computed as N 1 where N is the value reported in this field For example a hardware implementation supporting 48 bit MGAW reports a value of 47 101111b 2Fh in this field 21 16 RO 23h If the value in this field is X DMA requests to addresses above 2 x 1 1 are always blocked by hardware Guest addressability for a given DMA request is limited to the minimum of the value reported through this field and the adjusted guest address width of the corresponding page table structure Adjusted guest address widths supported by hardware are reported through the SAGAW field Implementations are recommended to support MGAW at least equal to the physical addressability host address width of the platform 15 13 RO 000b Reserved Supported Adjusted Guest Address Widths SAGAW This 5 bit field indicates the supported adjusted guest address widths which in turn represents the levels of page table walks for the 4 KB page size supported by the hardware implementation A value of 1 in any of these bits indicates the corresponding adjusted guest address width is supported The adjusted guest addre
455. s field is undefined Address Mask AM The value in this field specifies the number of low order bits of the ADDR field that must be masked for the invalidation operation Mask field enables software to request invalidation of contiguous mappings for size aligned regions For example Mask Value ADDR bits masked Pages invalidated 0 None 1 1 12 2 2 13 12 4 5 0 RO 00h 3 14 12 8 4 15 12 16 5 16 12 32 6 17 12 64 7 18 12 128 8 19 12 256 Hardware implementations report the maximum supported mask value through the Capability register Value returned on read of this field is undefined Datasheet Volume 2 283 intel Processor Configuration Registers 2 18 28 OTLB_REG IOTLB I nvalidate Register This register is used to invalidate OTLB The act of writing the upper byte of the l OTLB_ REG with the IVT field Set causes the hardware to perform the OTLB invalidation B D F Type Reset Value Access Address Offset 0 2 0 GFXVTBAR 108 10Fh 0200000000000000h RW RO Bit Attr Reset Value Description 63 RW Ob Invalidate I OTLB IVT Software requests OTLB invalidation by setting this field Software must also set the requested invalidation granularity by programming the IIRG field Hardware clears the IVT field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through t
456. s in the LO LOs or L1 states after link width negotiation is successfully completed 00h Reserved Olh X1 02h X2 04h X4 08h X8 10h X16 All other encodings are reserved 3 0 RO Oh Current Link Speed CLS This field indicates the negotiated Link speed of the given PCI Express Link Defined encodings are 0001b 2 5 GT s PCI Express Link 0010b 5 GT s PCI Express Link All other encodings are reserved The value in this field is undefined when the Link is not up Datasheet Volume 2 147 intel Processor Configuration Registers 2 10 42 SLOTCAP Slot Capabilities Register Note 148 Hot Plug is not supported on the platform B D F Type Address Offset Reset Value Access 0 1 0 PCI B4 B7h 00040000h RW O RO Bit Attr Reset Value Description 31 19 RW O 0000h Physical Slot Number PSN Indicates the physical slot number attached to this Port BIOS Requirement This field must be initialized by BIOS to a value that assigns a slot number that is globally unique within the chassis 18 RW O 1b No Command Completed Support NCCS When set to 1b this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot Plug Controller This bit is only permitted to be set to 1b if the hotplug capable port is able to accept writes to all fields of the Slot Contr
457. s the routing of processor initiated transactions targeting VGA compatible I O and memory address ranges See the VGAEN MDAP table in device 0 offset 97h 0 ISA Enable I SAEN Needed to exclude legacy resource decode to route ISA resources to legacy decode path Modifies the response by the GMCH to an I O access issued by the processor that target ISA I O addresses This applies only to 1 0 addresses that are enabled by the OBASE and IOLI MIT registers 0 All addresses defined by the IOBASE and IOLI MIT for processor I O transactions will be mapped to PCI Express G 1 GMCH will not forward to PCI Express G any I O transactions addressing the last 768 bytes in each 1 KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers SERR Enable SERREN 0 No forwarding of error messages from secondary side to primary side 1 RW Ob that could result in an SERR 1 ERR_COR ERR_NONFATAL and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register Parity Error Response Enable PEREN This bit controls whether or not the Master Data Parity Error bit in the Secondary Status register is set when the MCH receives across the link 0 RW Ob upstream a Read Data Completion Poisoned TLP 0 Master Data Parity Error bit in Secondary Status register can NOT be set 1 Master Data Parity Error bit in Secondary Status register CAN be set
458. s to this rank for the rest of the duration of this window 21 RW Ob Max Activate Check COsd_cr_maxact_dischk This bit enables the check which ensures that there are no more than four activates to a particular rank in a given window 20 17 RW Oh Activate to Activate Delay COsd_cr_act_act This field indicates the minimum allowed spacing in DRAM clocks between two ACT commands to the same rank This value corresponds to the tRRD parameter in the DDR3 specification 16 13 RW Oh Precharge to Activate Delay COsd_cr_pre_act This configuration register indicates the minimum allowed spacing in DRAM clocks between the PRE and ACT commands to the same rank bank This value corresponds to the tRP parameter in the DDR3 specification Oh Precharge All to Activate Delay COsd_cr_preall_ act From the launch of a precharge all command wait for this many memory bus clocks before launching an activate command This value corresponds to the tPALL_RP parameter 8 0 RW 76 000h Refresh to Activate Delay COsd_cr_rfsh_act This configuration register indicates the minimum allowed spacing in DRAM clocks between REF and ACT commands to the same rank This value corresponds to the tRFC parameter in the DDR3 specification Datasheet Volume 2 Processor Configuration Registers intel 2 8 12 COCYCTRKWR Channel O CYCTRK WR Register B D F Type 0 0 0 MC
459. s used to select the amount of main memory that is pre allocated to support the Internal Graphics Translation Table The BIOS ensures that memory is pre allocated only when internal graphics is enabled Memory pre allocated for internal graphics is assumed to be a contiguous physical DRAM space with memory pre allocated for data and BIOS needs to allocate a contiguous memory chunk Hardware will drive the base of memory pre allocated for internal graphics from memory pre allocated for data only using the memory pre allocated for graphics size programmed in the register Oh No memory pre allocated GTT cycles memory and I O are not claimed 11 8 RW L Oh 1h No VT mode 1 MB of memory pre allocated for GTT 3h No VT mode 2 MB of memory pre allocated for GTT 9h VT mode 2 MB of memory pre allocated for 1 MB of Global GTT and 1 MB for Shadow GTT Ah VT mode 3 MB of memory pre allocated for 1 5 MB of Global GTT and 1 5 MB for Shadow GTT Bh VT mode 4 MB of memory pre allocated for 2 MB of Global GTT and 2 MB for Shadow GTT All unspecified encodings of this register field are reserved hardware functionality is not ensured if used This register is locked and becomes read only when CMD LOCK MEMCONFIG is received or when ME_SM_LOCK is set to 1 Graphics Mode Select GMS This field is used to select the amount of Main Memory that is pre allocated to support the Internal Graphics device in VGA non linear and Native linear modes The BIOS e
460. sabled unless this rule and all following rules are disabled Lower limit is the previous rule or 0 if it is first rule This field is compared against MA 39 26 in the memory address map 5 3 RV 0 Reserved MODE DRAM rule interleave mode If a DRAM_RULE hits a 3 bit number is used to index into the corresponding interleave_list to determine which package the DRAM belongs to This mode selects how that number is computed 2 1 RW gt 00 Address bits 8 7 6 01 Address bits 8 7 6 XORed with 18 17 16 10 Address bit 6 MOD3 Address 39 6 Note 6 is the high order bit 11 Reserved ENABLE Enable for DRAM rule If Enabled Range between this rule and previous 0 RW 0 rule is Directed to HOME channel unless overridden by other dedicated address range registers If disabled all accesses in this range are directed in MMIO to the IOH Datasheet Volume 2 355 m Intel QuickPath Architecture System Address Decode Register Description intel 3 7 Intel QPI Link Registers 3 7 1 QPI_QPILCL_LO QPI_QPILCL_L1 This register provides Intel QPI Link Control Device 2 Function 0 Offset 48h Access as a Dword Reset Bee Bit Type Value Description 31 22 RV 0 Reserved L1_MASTER This bit indicates that this end of the link is the L1 master This link transmitter bit is an L1 power state master and can initiate an L1 power state transition If this bit is not set then the link transmitter is
461. self refresh commands DODTAOO sdO_cr_dodtao_r0 16 RW Ob Farce DRAM ODT Always ON for rankO 1 ON 0 OFF except during self refresh commands DODTRD1R3 sd0_cr_rdrank1_r3odt 15 RW Ob Assert rank3 ODT during Reads from RANK1 1 ON 0 OFF DODTRD1R2 sdO_cr_rdrank1_r2odt 14 RW Ob Assert rank2 ODT during Reads from RANK1 1 ON 0 OFF DODTRD1R1 sdO_cr_rdrank1_rlodt 13 RW Ob Assert rank1 ODT during Reads from RANK1 1 ON 0 OFF DODTRD1RO sdO_cr_rdrank1_rOodt 12 RW Ob Assert rankO ODT during Reads from RANK1 1 ON 0 OFF DODTRDOR3 sd0O_cr_rdrankO_r3odt 11 RW Ob Assert rank3 ODT during Reads from RANKO 1 ON 0 OFF DODTRDOR2 sdO_cr_rdrankO_r2odt 10 RW Ob Assert rank2 ODT during Reads from RANKO 1 ON 0 OFF Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 MCHBAR Address Offset 298 29Bh Reset Value 0000_0000h Access RW RO Reset rare Bit Attr Value Description DODTRDOR1 sd0_cr_rdrankO_rlodt 9 RW Ob Assert rank1 ODT during Reads from RANKO 1 ON 0 OFF DODTRDORO sd0O_cr_rdrank0O_rOodt 8 RW Ob Assert rankO ODT during Reads from RANKO 1 ON 0 OFF DODTWRI1R3 sd0_cr_wrrank1_r3odt 7 RW Ob Assert rank3 ODT during Writes to RANK1 1 ON 0 OFF DODTWRI1R2 sd0_cr_wrrank1_r2odt 6 RW Ob Assert rank2 ODT during Writes to RANK1 1 ON 0 OFF DODTWRIR1 sdO_cr_wrrank1_rlodt 5 RW Ob Assert rank1 ODT during Wri
462. sending an SERR message to the PCH This bit when set enables reporting of non fatal and fatal errors detected by the device to the Root Complex Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control Register In addition for Type 1 configuration space header devices this bit when set enables transmission by the primary interface of ERR_NONFATAL and ERR_FATAL error messages forwarded from the secondary interface This bit does not affect the transmission of forwarded ERR_COR messages 0 The SERR message is generated by the processor for Device 1 only under conditions enabled individually through the Device Control Register 1 The processor is enabled to generate SERR messages which will be sent to the PCH for specific Device 1 error conditions generated detected on the primary side of the virtual PCI to PCI bridge not those received by the secondary side The status of SERRs generated is reported in the PCISTS1 register RO Ob Reserved Not Applicable or Implemented Hardwired to 0 RW Ob Parity Error Response Enable PERRE Controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set 0 Master Data Parity Error bit in PCI Status register can NOT be set 1 Master Data Parity Error bit in PCI Status register CAN be set RO Ob VGA Palette Snoop VGAPS Not Applicable or Implemented Hardwired
463. set T Bit Attr Value Description Memory Address Limit MLI MI T 15 4 RW 000h This field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express G 3 0 RO Oh Reserved Datasheet Volume 2 Processor Configuration Registers t 2 10 17 PMBASE1 Prefetchable Memory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 1 0 PCI Address Offset 24 25h Reset Value FFF1h Access RW RO Reset FP Bit Attr Value Description Prefetchable Memory Base Address MBASE 15 4 RW FFFh This field corresponds to A 31 20 of the lower limit of the memory range that will be passed to PCI Express G 64 bit Address Support 64 bit Address Support 3 0 RO 1h This field
464. sical component The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket This document describes these configuration space registers or device specific control and status registers CSRs only This document does NOT include Model Specific Registers MSRs Throughout this document the Intel Core i5 600 i3 500 Desktop processor series and Intel Pentium desktop processor 6000 seriesmay be referred to as processor Througout this document the Intel 5 series Chipset Platform Controller Hub is also referred to as PCH The term DT refers to desktop platforms Datasheet Volume 2 13 14 Introduction Datasheet Volume 2 Processor Configuration Registers 2 Processor Configuration Registers 2 1 Register Terminology Table 2 1 shows the register related terminology that is used in this chapter Table 2 1 Register Terminology Sheet 1 of 2 Item Description RO Read Only bit s Writes to these bits have no effect These are static values only RO V Read Only Volatile bit s Writes to these bits have no effect These are status bits only The value to be read may change based on internal events RO V S Read Only Volatile Sticky bit s Writes to these bits have no effect These are status bits only The value to be read may change based on internal events Bits are not returned to their Reset Values
465. source Control Register This register controls the resources associated with PCI Express Virtual Channel 0 B D F Type 0 1 0 MMR Address Offset 114 117h Reset Value 8000_OOFFh Access RO RW Reset poe Bit Attr Value Description 31 RO ib VCO Enable VCOE For VCO this is hardwired to 1 and read only as VCO can never be disabled 30 27 RO Oh Reserved VCO ID VCOI D 26 24 RO 000b This field assigns a VC ID to the VC resource For VCO this is hardwired to 0 and read only 23 20 RO Oh Reserved Port Arbitration Select PAS This field configures the VC resource to provide a particular Port Arbitration service This field is valid for RCRBs Root Ports that support peer to peer 19 17 RW 000b traffic and Switch Ports but not for PCI Express Endpoint devices or Root Ports that do not support peer to peer traffic The permissible value of this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource 16 RO Ob Reserved Reserved for Load Port Arbitration Table 158 Datasheet Volume 2 Processor Configuration Registers B D F Type 0 1 0 MMR Address Offset 114 117h Reset Value 8000_OOFFh Access RO RW Reset PEE Bit Attr Value Description 15 8 RO 00h Reserved TC VCO Map TCVCOM This field indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field
466. space to update the display even when SMM is mapped over the VGA range Software should ensure that D_OPEN 1 and D_CLS 1 are not set at the same time SMM Space Locked D_LCK When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK D_OPEN C_BASE_SEG G_SMRAME PCIEXBAR DRAM_RULEs and INTERLEAVE_LISTs become read only D_LCK can be set to 1 using a normal configuration space write but can only be cleared by a Reset The 12 RW1S 0 combination of D_LCK and D_OPEN provide convenience with security The BIOS can use the D_OPEN function to initialize SMM space and then use D_LCK to lock down SMM space in the future so that no application software or BIOS itself can violate the integrity of SMM space even if the program has knowledge of the D_OPEN function Note that TAD does not implement this lock Global SMRAM Enable G_SMRAME If set to a 1 then Compatible SMRAM functions are enabled providing 11 RW 0 128 KB of DRAM accessible at the A0000h address while in SMM ADSB with SMM decode To enable Extended SMRAM function this bit has to be set to 1 Once D_LCK is set this bit becomes read only Compatible SMM Space Base Segment C_BASE_ SEG This field indicates the location of SMM space SMM DRAM is not remapped 10 8 RO It is simply made visible if the conditions are right to access SMM space otherwise the access is forwarded to HI Only SMM space between A0000h and BFFFFh is supported so this field is hard wired to 0
467. ss widths corresponding to various bit positions within this field are 12 8 RO 02h 0 30 bit AGAW 2 level page table 1 39 bit AGAW 3 level page table 2 48 bit AGAW 4 level page table 3 57 bit AGAW 5 level page table 4 64 bit AGAW 6 level page table Software must ensure that the adjusted guest address width used to setup the page tables is one of the supported guest address widths reported in this field Caching Mode CM 0 Hardware does not cache not present and erroneous entries in any of the remapping caches Invalidations are not required for modifications to individual not present or invalid entries However any modifications that result in decreasing the effective permissions or partial permission increases require invalidations for them to be effective 7 RO Ob 1 Hardware may cache not present and erroneous mappings in the remapping caches Any software updates to the DMA remapping structures including updates to not present or erroneous entries require explicit invalidation Refer to the VTd specification for more details on caching mode Hardware implementations are required to support operation corresponding to CM 0 224 Datasheet Volume 2 Processor Configuration Registers B D F Type Address Offset Reset Value Access 0 0 0 DMI VC1LREMAP 8 Fh 00C9008020E30272h RO Bit Attr Reset Value Description 1b Protected High Memory Region PHM
468. stem memory The protected low memory region has a minimum size of 2 MB and must be size aligned 20 0 RO 000000h Reserved Datasheet Volume 2 203 intel PLMLI MIT_REG Protected Low Memory Limit Register Register to setup the limit address of DMA protected low memory region This register must be setup before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled When LT CMD LOCK PMRC command is invoked this register is locked treated RO When LT CMD UNLOCK PMRC command is invoked this register is unlocked treated RW This register is always treated as RO for implementations not supporting protected low memory region PLMR field reported as 0 in the Capability register The alignment of the protected low memory region limit depends on the number of reserved bits N of this register Software may determine the value of N by writing all 1s to this register and finding most significant zero bit position with 0 in the value read back from the register Bits N 0 of the limit register is decoded by hardware as all 1s The Protected low memory base amp limit registers functions as follows Programming the protected low memory base and limit registers with the same value in bits 31 N 1 specifies a protected low memory region of size 2 N 1 2 15 16 204 bytes Processor Configuration Registers Programming the protected low memory limit register
469. sters intel 2 12 2 DMI PVCCAP1 DMI Port VC Capability Register 1 Describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 0 0 DMIBAR Address Offset 4 7h Reset Value 0000_0000h Access RO RW O n Reset jni Bit Attr Value Description 31 7 RO 0000000h Reserved Low Priority Extended VC Count LPEVCC This field indicates the number of extended Virtual Channels in addition to the default VC belonging to the low priority VC LPVC group that has the oA RO 000b lowest priority with respect to other VC resources in a strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration 3 RO Ob Reserved Extended VC Count EVCC This field indicates the number of extended Virtual Channels in addition to 2 0 RW O 000b the default VC supported by the device For DMI only the default Virtual Channel VCO is advertised in the Extended VC Capability structure 2 12 3 DMI PVCCAP2 DMI Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 0 0 DMIBAR Address Offset 8 Bh Reset Value 0000_0000h Access RO A Reset EF Bit Attr Value Description 31 24 RO 00h Reserved for VC Arbitration Table Offset 23 8 RO 0000h Reserved 7 0 RO 00h Reserved for VC Arbitration Capability VCAC 162 Datasheet
470. t Hardware will clear this bit RWL Read Write Lock A register bit with this attribute can be read or written by software Hardware or a configuration bit can lock the bit and prevent it from being updated Datasheet Volume 2 335 intel Table 3 1 336 Intel QuickPath Architecture System Address Decode Register Description Register Terminology Sheet 2 of 2 Term Description Read Write Once A register bit with this attribute can be written to only once after power up After the first write the bit becomes read only This attribute is applied on a bit by bit basis For RWO example if the RWO attribute is applied to a 2 bit field and only one bit is written then the written bit cannot be rewritten unless reset The unwritten bit of the field may still be written once This is special case of RWL RRW Read Restricted Write This bit can be read and written by software However only supported values is written Writes of non supported values will have no effect L Lock A register bit with this attribute becomes Read Only after a lock bit is set Reserved Bit This bit is reserved for future expansion and must not be written The PCI Local RSVD Bus Specification Revision 2 2 requires that reserved bits must be preserved Any software that modifies a register that contains a reserved bit is responsible for reading the register modifying the desired bits and writing back the result Some of th
471. t This port number value is utilized by the egress port of the component to provide arbitration to this Root Complex Element Component ID CID This field identifies the physical component that contains this Root Complex Element 23 16 RW O 00h 2h a BIOS Requirement Must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS Number of Link Entries NLE This field indicates the number of link entries following the Element Self 15 8 RO 02h Description This field reports 2 one for the processor egress port to main memory and one to egress port belonging to PCH on other side of internal link 7 4 RO Oh Reserved Element Type ETYP 3 0 RO 2h This field indicates the type of the Root Complex Element Value of 2h represents an Internal Root Complex Link DMI Datasheet Volume 2 169 intel Processor Configuration Registers 2 12 14 DMILE1LD DMI Link Entry 1 Description Register This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element B D F Type 0 0 0 DMIBAR Address Offset 50 53h Reset Value 0000_0000h Access RWO RO Reset PEAS Bit Attr Value Description Target Port Number TPN This field specifies the port number associated with the element targeted by this link entry egress port of the PCH The t
472. t implemented B D F Type 0 0 0 PCI Address Offset Dh Reset Value 00h Access RO s Reset er Bit Attr Value Description 7 0 RO 00h Reserved Datasheet Volume 2 49 Processor Configuration Registers intel 2 7 8 HDR Header Type Register This register identifies the header layout of the configuration space No physical register exists at this location B D F Type 0 0 0 PCI Address Offset Eh Reset Value 00h Access RO Reset Eee Bit Attr Value Description PCI Header HDR This field always returns 0 to indicate that the processor is a single function device with standard header layout Reads and writes to this location have no effect 7 0 RO 00h 2 7 9 SVID Subsystem Vendor Identification Register This value is used to identify the vendor of the subsystem B D F Type 0 0 0 PCI Address Offset 2C 2Dh Reset Value 0000h Access RW O H Reset i Bit Attr Value Description Subsystem Vendor ID SUBVI D 15 0 RW O 0000h This field should be programmed during boot up to indicate the vendor of the system board After it has been written once it becomes read only 50 Datasheet Volume 2 Processor Configuration Registers 2 7 10 SI D Subsystem Identification Register This value is used to identify a particular subsystem B D F Type 0 0 0 PCI Address Offset 2E 2Fh Reset Value 0000h Ac
473. t 52h bits 11 8 from the Base of memory pre allocated for graphics PCI Device 0 offset A4h bits 31 20 This register is locked and becomes Read Only when CMD LOCK MEMCONFIG is received or when ME_SM_LOCK is set to 1 B D F Type 0 0 0 PCI Address Offset A8 ABh Reset Value 0000_0000h Access RW L RO Reset Peer Bit Attr Value Description Memory Pre allocated for graphics MPG This register contains bits 31 20 of the base address of pre allocated DRAM memory BIOS determines the base of memory pre allocated for graphics by subtracting the graphics pre allocated memory size PCI Device 0 offset 31 20 RWE 000h 52h bits 9 8 from the graphics pre allocated memory base PCI Device 0 offset A4h bits 31 20 This register is locked and becomes Read Only when CMD LOCK MEMCONFIG is received or when ME_SM_LOCK is set to 1 19 0 RO 00000h Reserved TSEGMB TSEG Memory Base Register This register contains the base address of TSEG DRAM memory BIOS determines the base of TSEG memory which must be at or below memory pre allocated for graphics PCI Device 0 offset A8h bits 31 20 This register is locked and becomes Read Only when CMD LOCK MEMCONFIG is received or when ME_SM_LOCK is set to 1 B D F Type 0 0 0 PCI Address Offset AC AFh Reset Value 0000_0000h Access RO RW L n Reset PaF Bit Attr Value Description TESG Memory base TSEGMB This register contains bits 31 2
474. t Status register e When advanced fault logging is active an interrupt condition occurs when hardware records a fault in the first fault record at index 0 of the current fault log and sets the APF field in the Fault Status register e Hardware detected error associated with the Invalidation Queue setting the IQE field in the Fault Status register e Hardware detected invalid Device OTLB invalidation completion setting the ICE field in the Fault Status register e Hardware detected Device OTLB invalidation completion time out setting the ITE field in the Fault Status register If any of the status fields in the Fault Status register was already Set at the time of setting any of these fields it is not treated as a new interrupt condition The IP field is kept Set by hardware while the interrupt message is held pending The interrupt message could be held pending due to the interrupt mask IM field being Set or other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either a change in the transient hardware condition that caused the interrupt message to be held pending or due to software clearing the IM field e Software servicing all the pending interrupt status fields in the Fault Status register as follows When primary fault logging is active software clearing
475. t Value 0800000000000000h Access RW RO Reset re Bit Attr Value Description Context I nvalidation Request Granularity CI RG Software provides the requested invalidation granularity through this field when setting the ICC field 00 Reserved 01 Global Invalidation request 10 Domain selective invalidation request The target domain id must be specified in the DID field Device selective invalidation request The target source id s must be specified through the SID and FM fields and the domain id that was programmed in the context entry for these device s must be provided in the DID field Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalidation request by clearing the ICC field At this time hardware also indicates the granularity at which the actual invalidation was performed through the CAIG field 62 61 RW 00b 11 Context Actual I nvalidation Granularity CAI G Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion by clearing the ICC field The following are the encodings for this field 00 Reserved 60 59 RO 01b 01 Global Invalidation performed This could be in response to a global domain selective or device selective invalidation request 10 Domain selective invalidati
476. t generate an interrupt request it writes a 32 bit value to the memory address specified in the MA register The upper 16 bits are always set to 0 The lower 16 bits are supplied by this register 2 19 33 PEG_CAPL PCI Express G Capability List Register This register enumerates the PCI Express capability structure B D F Type 0 6 0 PCI Address Offset A0 Alh Reset Value 0010h Access RO Reset er Bit Attr Value Description Pointer to Next Capability PNC This value terminates the capabilities list The Virtual Channel capability and 15 8 RO 00h any other PCI Express specific capabilities that are reported using this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration Space Capability ID CID 7 0 RO 10h Identifies this linked list item capability structure as being for PCI Express registers Datasheet Volume 2 311 intel Processor Configuration Registers 2 19 34 PEG _CAP PCI Express G Capabilities Register This register indicates PCI Express device capabilities B D F Type 0 6 0 PCI Address Offset A2 A3h Reset Value 0142h Access RO RW O Reset RA Bit Attr Value Description 15 RO Ob Reserved 14 RO Ob Reserved Reserved for TCS Routing Supported Interrupt Message Number I MN 13 9 RO 00h Not Applicable or Implemented Hardwired to 0 Slot Implemented SI 0
477. t in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b Reserved for Hot plug I nterrupt Enable HPI E When set to 1 this bit enables generation of an interrupt on enabled hot plug 5 RO Ob events a l l l Reset Value of this field is Ob If the Hot Plug Capable field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob Reserved for Command Completed Interrupt Enable CCI If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register when set to 0 Ob 1b this bit enables software notification when a hot plug command is 4 R completed by the Hot Plug Controller Reset Value of this field is Ob If Command Completed notification is not supported this bit must be hardwired to Ob Presence Detect Changed Enable PDCE 3 RW Ob When set to 1 this bit enables software notification on a presence detect changed event Reserved for MRL Sensor Changed Enable MSCE When set to 1 this bit enables software notification on a MRL sensor changed 2 RO Ob event Reset Value of this field is Ob If the MRL Sensor Present field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob Reserved for Power Fault Detected Enable PFDE 1 RO Ob When set to 1 this bit enables software notification on a power fault event Reset Value of this field is
478. t messages These general GPE 0 RW Ob message can be received using the PEG port from an external Intel device that is PxH and will be subsequently forwarded to the PCH using Assert_GPE and Deassert_GPE messages on DMI For example PxH might send this message if a PCI Express device is hot plugged into a PxH downstream port Datasheet Volume 2 155 Processor Configuration Registers intel 2 11 Device 1 Extended Configuration Registers Table 2 8 Device 1 Extended Configuration Register Address Map oe pears Register Name Reset Value Access 100 103h VCECH Virtual Channel Enhanced Capability Header 00010002h RW O RO 104 107h PVCCAP1 Port VC Capability Register 1 0000_0000h RO 108 10Bh PVCCAP2 Port VC Capability Register 2 0000_0000h RO 10C 10Dh PVCCTL Port VC Control 0000h RO RW 110 113h VCORCAP VCO Resource Capability 0000 _0001h RO 114 117h VCORCTL VCO Resource Control 8000_00FFh RO RW 11A 11Bh VCORSTS VCO Resource Status 0002h RO 204 207h PEG_TC PCI Express Completion Timeout 0000_0000h RW 2 11 1 PVCCAP1 Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 1 0 MMR Address Offset 104 1107h Reset Value 0000_0000h Access RO Reset desea Bit Attr Value Description 31 12 RO 00000h Reserved 11 10 RO 00b Reserved Reserved for Port Arbitration T
479. t status bit in the TIS register for that trip event It is possible at this point that a falling temperature trip event occurs before the software has had the time to clear the global interrupts status bit But since software has already looked at the status register before this event happened software may not clear the local status flag for this event Therefore after the global interrupt is cleared by software software must look at the instantaneous status in the TSS register Datasheet Volume 2 101 Processor Configuration Registers intel 2 8 48 TERATE Thermometer Mode Enable and Rate Register This common register helps select between the analog and the thermometer mode and also helps select the DAC settling timer B D F Type 0 0 0 MCHBAR Address Offset 1070h Reset Value 00h Access RO RW Reset Eee Bit Attr Value Description 7 4 RO Oh Reserved Thermometer Mode Enable and Rate TE If analog thermal sensor mode is not enabled by setting these bits to 0000b these bits enable the thermometer mode functions and set the Thermometer controller rate When the Thermometer mode is disabled and TSC1 TSC enabled the analog sensor mode should be fully functional In the analog sensor mode the Catastrophic trip is functional The other trip points are not functional in this mode When Thermometer mode is enabled all the trip points Catastrophic Hot Aux 0 Aux 1 Aux 2 will all operate usi
480. t this bit to 0 if the GMS field bits 6 4 of this register pre allocates no memory This bit MUST be set to 1 if Device 2 is disabled either using a fuse or fuse override CAPIDO 46 1 or using a register DEVEN 3 0 This register is locked and becomes Read Only when CMD LOCK MEMCONFIG is received or when ME_SM_LOCK is set to 1 0 RO Ob Reserved DEVEN Device Enable Register This register allows for enabling disabling of PCI devices and functions that are within the processor The table below describes the behavior of all combinations of transactions to devices controlled by this register All the bits in this register are Intel TXT Lockable B D F Type 0 0 0 PCI Address Offset 54 57h Reset Value 0000_210Bh Access RW L RO BIOS Optimal Reset Value 000000h z Reset PE Bit Attr Value Description 31 4 RO Oh Reserved PCI Express Port D6EN 1 RW L 1b 0 Bus 0 Device 1 Function 0 is disabled and hidden 1 Bus 0 Device 1 Function 0 is enabled and visible 12 4 RO 00h Reserved Internal Graphics Engine Function 0 D2FOEN 0 Bus 0 Device 2 Function 0 is disabled and hidden 3 RW L 1b 1 Bus 0 Device 2 Function 0 is enabled and visible If this processor does not have internal graphics capability then Device 2 Function 0 is disabled and hidden independent of the state of this bit 2 RO Oh Reserved PCI Express Port D1EN 1 RW L 1b 0 Bus 0 Device 1 Function 0 is disabled
481. t which the invalidation operation was performed through the IAIG field Software must not submit another invalidation request through this register while the IVT field is set nor update the associated Invalidate Address register Software must not submit OTLB invalidation requests through any of the OTLB invalidation units when there is a context cache invalidation request pending at this DMA remapping hardware unit When more than one IOTLB invalidation units are supported by a DMA remapping hardware unit software may submit IOTLB invalidation request through any of the currently free units while there are pending requests on other units Refer to the VTd specification for software programming requirements Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flushing before reporting invalidation complete to software through the IVT field Refer to the VTd specification for write buffer flushing requirements 62 60 RW Oh 1OTLB I nvalidation Request Granularity 11 RG When requesting hardware to invalidate the OTLB by setting the IVT field software writes the requested invalidation granularity through this IIRG field Following are the encodings for the IIRG field 000 Reserved 001 Global invalidation request 010 Domain selective invalidation request The target domain id must be specified in the DID field 011
482. ta 0000h RW AO Alh PEG_CAPL PCI Express G Capability List 0010h RO A2 A3h PEG_CAP PCI Express G Capabilities 0142h RO RW O 288 Datasheet Volume 2 Processor Configuration Registers intel Table 2 14 PCI Device 6 Register Address Map Sheet 2 of 2 pies a Register Name asi Access A4 A7h DCAP Device Capabilities 00008000h RO A8 A9h DCTL Device Control 0000h RW RO AA ABh DSTS Device Status 0000h RO RW1C AC AFh LCAP Link Capabilities 03214C82h RO RW O BO B1h LCTL Link Control 0000h RW RO B2 B3h LSTS Link Status 1000h RO RW1C B4 B7h SLOTCAP Slot Capabilities 00040000h RW O RO B8 B9h SLOTCTL Slot Control 0000h RO RW BA BBh SLOTSTS Slot Status 0000h RO RW1C BC BDh RCTL Root Control 0000h RO RW C0 C3h RSTS Root Status 00000000h RO RWIC EC EFh PEGLC PCI Express G Legacy Control 00000000h RO RW 2 19 1 VI D6 Vendor Identification Register This register combined with the Device Identification register uniquely identify any PCI device B D F Type 0 6 0 PCI Address Offset 0 1h Reset Value 8086h Access RO Reset PAPP Bit Attr Value Description i Vendor Identification VI D6 15 0 RO Bogen PCI standard identification for Intel Datasheet Volume 2 289 intel Processor Configuration Registers 2 19 2 DI D6 Device Identification Register This register combined with the Vendor Identification register uni
483. ta is available This bit does not affect forwarding of Completions from the primary interface to the secondary interface Memory Access Enable MAE 1 RW 0b 0 All of device 6 s memory space is disabled 1 Enable the Memory and Pre fetchable memory address ranges defined in the MBASE6 MLIMIT6 PMBASE6 and PMLIMIT6 registers 1O Access Enable I OAE 0 RW Ob 0 All of device 6 s I O space is disabled 1 Enable the I O address range defined in the OBASE6 and OLIMIT6 registers Datasheet Volume 2 291 intel Processor Configuration Registers 2 19 4 PCISTS6 PCI Status Register This register reports the occurrence of error conditions associated with primary side of the virtual Host PCl Express bridge embedded within the GMCH B D F Type Address Offset Reset Value Access 0 6 0 PCI 6 7h 0010h RO RW1C Bit Attr Reset Value Description 15 RO Ob Detected Parity Error DPE Not Applicable or Implemented Hardwired to 0 Parity generating poisoned TLPs is not supported on the primary side of this device we don t do error forwarding 14 RW1C Ob Signaled System Error SSE This bit is set when this Device sends an SERR due to detecting an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the Command register is 1 Both received if enabled by BCTRL6 1 and internally detected error messages do not affect this field 13 RO
484. tae dase tee 335 3 2 Functions Specifically Handled by the Proc SSOF cccceceseee eee eeeee eee eeeeeeneeneeenaeea 337 3 3 Device 0 Function 0 Generic Non core Registers cece cece eee ee eee eee eaten 338 3 4 Device 0 Function 1 System Address Decoder ReGiSters ccceeeee eect eee ees 339 3 5 Device 2 Function 0 Intel QPI Link 0 REJIStel Sienen e anaE E a 340 3 6 Device 2 Function 1 Intel QPI Physical O REGiSters ccccssceeceeeeseseeeeeeeeaenans 341 Datasheet Volume 2 11 intel Revision History 12 Revision ee Revision Number Description Date _ ne January 001 Initial release 2010 e Added the MCSAMPML Memory Configuration System Address Map and Pre allocated Memory Lock Register See Section 2 7 28 002 e Added the PEG_TC PCI Express Completion Timeout Register See November Section 2 11 7 2010 e Updated the system address map section and main memory address space for better clarification Added the series designation Intel Pentium desktop processor 6000 003 series J ae Added the Intel Pentium processor G6960 Datasheet Volume 2 Introduction 1 Note Note Note intel Introduction This is Volume 2 of the Datasheet for the Intel Core i5 600 i3 500 Desktop processor series and Intel Pentium desktop processor 6000 series The processor contains one or more PCI devices within a single phy
485. tain their states between hard resets Register Terminology Sheet 1 of 2 Term Description RO Read Only If a register bit is read only the hardware sets its state The bit may be read by software Writes to this bit have no effect wo Write Only The register bit is not implemented as a bit The write causes some hardware event to take place RW Read Write A register bit with this attribute can be read and written by software RC Read Clear The bit or bits can be read by software but the act of reading causes the value to be cleared RCW Read Clear Write A register bit with this attribute will get cleared after the read The register bit can be written RW1C Read Write 1 Clear A register bit with this attribute can be read or cleared by software In order to clear this bit a one must be written to it Writing a zero will have no effect RWOC Read Write 0 Clear A register bit with this attribute can be read or cleared by software In order to clear this bit a zero must be written to it Writing a one will have no effect RWIS Read Write 1 Set A register bit can be either read or set by software In order to set this bit a one must be written to it Writing a zero to this bit has no effect Hardware will clear this bit RWOS Read Write 0 Set A register bit can be either read or set by software In order to set this bit a zero must be written to it Writing a one to this bit has no effec
486. tatus PRS 0 RO Oh This field indicates the status of protected memory region 0 Protected memory region s not enabled 1 Protected memory region s enabled Datasheet Volume 2 Processor Configuration Registers t 2 15 15 PLMBASE_REG Protected Low Memory Base Register This register is used to setup the base address of DMA protected low memory region The register must be setup before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled When LT CMD LOCK PMRC command is invoked this register is locked treated RO When LT CMD UNLOCK PMRC command is invoked this register is unlocked treated RW This register is always treated as RO for implementations not supporting protected low memory region PLMR field reported as 0 in the Capability register The alignment of the protected low memory region base depends on the number of reserved bits N of this register Software may determine the value of N by writing all 1s to this register and finding most significant zero bit position with O in the value read back from the register Bits N 0 of this register is decoded by hardware as all Os B D F Type 0 0 0 VCOPREMAP Address Offset 68 6Bh Reset Value 00000000h Access RW RO E Reset PP Bit Attr Value Description 31 21 RW 000h Protected Low Memory Base PLMB This register specifies the base of size aligned protected low memory region in sy
487. tatus bit not PCI INTA INTD assert 3 RO Ob and de assert messages The INTA Assertion Disable bit PCICMD1 10 has no effect on this bit Note that INTA emulation interrupts received across the link are not reflected in this bit 2 0 RO 000b Reserved Datasheet Volume 2 119 Processor Configuration Registers intel 2 10 5 RI D1l Revision Identification Register This register contains the revision number of the processor device 1 These bits are read only and writes to this register have no effect This register contains the revision number of the processor The Revision ID RID is a traditional 8 bit Read Only RO register located at offset 08h in the standard PCI header of every PCI PCI Express compatible device and function B D F Type 0 1 0 PCI Address Offset 8h Reset Value 08h Access RO Bit Attr Reset Description Value Revision Identification Number RI D1 This is an 8 bit value that indicates the revision identification number for the 7 0 RO 08h processor Device 0 Refer to the Intel Core i5 600 and i3 500 Desktop Processor Series and Intel Pentium Desktop Processor 6000 Series Specification Update for the value of the Revision ID Register 2 10 6 CC1 Class Code Register This register identifies the basic function of the device a more specific sub class and a register specific programming interface B D F Type 0 1 0 PCI Addr
488. ted Hardwired to 0 7 RO Ob Fast Back to Back Enable FB2BEN Not Applicable or Implemented Hardwired to 0 Secondary Bus Reset SRESET 6 RW Ob Setting this bit triggers a hot reset on the corresponding PCI Express Port This will force the LTSSM to transition to the Hot Reset state using Recovery from LO LOs or L1 states Master Abort Mode MAMODE Does not apply to PCI Express Hardwired to 0 VGA 16 bit Decode VGA16D Enables the PCI to PCI bridge to provide 16 bit decoding of VGA I O address precluding the decoding of alias addresses every 1 KB This bit only has 4 RW Ob meaning if bit 3 VGA Enable of this register is also set to 1 enabling VGA 1 O decoding and forwarding by the bridge 0 Execute 10 bit address decodes on VGA I O accesses 1 Execute 16 bit address decodes on VGA I O accesses VGA Enable VGAEN 3 RW Ob Controls the routing of processor initiated transactions targeting VGA compatible I O and memory address ranges See the VGAEN MDAP table in device 0 offset 97h 0 ISA Enable I SAEN Needed to exclude legacy resource decode to route ISA resources to legacy decode path Modifies the response by the processor to an I O access issued by the processor that target ISA I O addresses This applies only to 1 0 addresses that are enabled by the OBASE and IOLI MIT registers 0 All addresses defined by the IOBASE and IOLIMIT for processor I O transactions will be mapped to PCI Exp
489. tended Capability Register ceecee 260 2 18 4 GCMD_REG Global Command Register s ssssssrrrrrrrrrrrrrrrrrrrrrrrrrirrrrerr 261 2 18 5 GSTS_REG Global Status Register sssrsssresresrrsrrrerrnsrnsrennnnnnennrnernnn 264 2 18 6 RTADDR_REG Root Entry Table Address Register cceeeeeee ee ee eae 266 2 18 7 CCMD_REG Context Command ReGiISter cece ee eee ee ee ee eee eta teen teens 266 2 18 8 FSTS REG Fault Status Register 0 0 eect eeee terre eee tenner ee eea teeta ee eas 268 2 18 9 FECTL_REG Fault Event Control Register sssssssrsrrrrrrrrrrsrrrrrerrerrresinua 270 2 18 10 FEDATA_REG Fault Event Data Register cc ccceecceeee eee ee ee eet a eee a eae 271 2 18 11 FEADDR_REG Fault Event Address Register cccciceeeeeeee cnet nea ee enna ees 271 2 18 12 FEUADDR_REG Fault Event Upper Address Register eeeeee eee es 271 2 18 13 AFLOG_REG Advanced Fault Log Register cccceeteeee cece neta ee ee eee eaed 272 2 18 14 PMEN_REG Protected Memory Enable Register c ceeeeeeeeeeeee ee eaee 273 2 18 15 PLMBASE REG Protected Low Memory Base RegiSter eeeeee tees 274 2 18 16 PLMLIMIT_REG Protected Low Memory Limit Register eeeeees 275 2 18 17 PHMBASE_ REG Protected High Memory Base Register 276 2 18 18 PHMLIMIT_REG Protected High Memory Limit Register accer 277 2 18 19 IQH REG Invalidation Queue Head ReGiSter
490. tes to RANK1 1 ON 0 OFF DODTWRI1RO sd0_cr_wrrank1_rOodt 4 RW Ob Assert rankO ODT during Writes to RANK1 1 ON 0 OFF DODTWROR3 sd0_cr_wrrankO_r3odt 3 RW Ob Assert rank3 ODT during Writes to RANKO 1 ON 0 OFF DODTWROR2 sd0_cr_wrrankO_r2odt 2 RW Ob Assert rank2 ODT during Writes to RANKO 1 ON 0 OFF DODTWROR1 sdO_cr_wrrankO_rlodt 1 RW Ob Assert rank1 ODT during Writes to RANKO 1 ON DODTWRORO sd0O_cr_wrrankO_rOodt 0 RW Ob Assert rankO ODT during Writes to RANKO 1 ON 0 OFF Datasheet Volume 2 83 intel Processor Configuration Registers 2 8 19 COODTCTRL Channel 0 ODT Control Register B D F Type 0 0 0 MCHBAR Address Offset 29C 29Fh Reset Value 0000_0000h Access RW RO Reset PA Bit Attr Value Description 31 12 RO 00000h Reserved DRAM ODT for Read Commands sd0_cr_odt_duration_rd 11 8 RW Oh Specifies the duration in mb2clks to assert DRAM ODT for Read Commands The Async value should be used when the Dynamic Powerdown bit is set Otherwise use the Sync value DRAM ODT for Write Commands sd0O_cr_odt_duration_wr 7 4 RW Oh Specifies the duration in mb2clks to assert DRAM ODT for Write Commands The Async value should be used when the Dynamic Powerdown bit is set Otherwise use the Sync value MCH ODT for Read Commands sd0_cr_mchodt_ duration 3 0 RW Oh This field specifies the duration in mb2clks to assert MCH ODT for Read Commands 2 8 20
491. that reference clock s must not be removed in these link states 18 RO Ob This capability is applicable only in form factors that support clock request CLKREQ capability For a multi function device each function indicates its capability independently Power Management configuration software must only permit reference clock removal if all functions of the multifunction device indicate a 1b in this bit L1 Exit Latency L1ELAT Indicates the length of time this Port requires to complete the transition from L1 to LO The value 010 b indicates the range of 2 us to less than 4 us BIOS Requirement If this field is required to be any value other than the 17 15 RW O 010b default BIOS must initialize it accordingly Both bytes of this register that contain a portion of this field must be written simultaneously in order to prevent an intermediate and undesired value from ever existing Datasheet Volume 2 315 316 Processor Configuration Registers B D F Type Address Offset Reset Value Access 0 6 0 PCI AC AFh 03214C82h RO RW O Bit Attr Reset Value Description 14 12 RO 100b LOs Exit Latency LOSELAT This field indicates the length of time this Port requires to complete the transition from LOs to LO 000 Less than 64 ns 001 64 ns to less than 128 ns 010 128 ns to less than 256 ns 011 256 ns to less than 512 ns 100 512 ns to less than 1 us 101 1 us to
492. that provide exclusive address ranges that is prevent overlap with each other and or with the ranges covered with the main memory There is no provision in the GMCH hardware to enforce prevention of overlap and operations of the system in the case of overlap are not ensured B D F Type 0 6 0 PCI Address Offset 22 23h Reset Value 0000h Access RO RW 7 Reset ae Bit Attr Value Description Memory Address Limit MLI MIT 15 4 RW 000h This field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express G 3 0 RO Oh Reserved Datasheet Volume 2 299 m t 1 Processor Configuration Registers 2 19 17 300 PMBASE6 Prefetchable Memory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB bound
493. the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 6 0 PCI Address Offset 28 2Bh Reset Value 0000_0000h Access RW Reset Beata Bit Attr Value Description Prefetchable Memory Base Address MBASEU This field corresponds to A 63 32 of the lower limit of the prefetchable memory range that will be passed to PCI Express G r 0000_000 31 0 RW OR Datasheet Volume 2 Processor Configuration Registers t 2 19 20 PMLIMITU6 Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are ass
494. the processor will now positively decode this range to DMI This positive decode will ensure any overlapping ranges will be ignored The top 2 MB FFE0_0000h FFFF_FFFFh of the PCI Memory Address Range is reserved for System BIOS High BIOS extended BIOS for PCI devices and the A20 alias of the system BIOS The processor begins execution from the High BIOS after reset This region is positively decoded to DMI Interface so that the upper subset of this region aliases to 16 MB 256 KB range The actual address space required for the BIOS is less than 2 MB but the minimum processor MTRR range for this region is 2 MB so that full 2 MB must be considered Datasheet Volume 2 Processor Configuration Registers 7 t 2 2 3 Note Main Memory Address Space 4 GB to TOUUD The processor will support 36 bit addressing The maximum main memory size supported is 16 GB total DRAM memory A hole between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger As a result TOM and TOUUD registers and REMAPBASE REMAPLIMIT registers become relevant The remap configuration registers exist to remap lost main memory space The greater than 32 bit remap handling will be handled similar to other processors Upstream read and write accesses above 36 bit addressing will be treated as invalid cycles by PEG and DMI Top of Memory TOM The Top of Memory TOM register reflects the total amount of populated physical memory This
495. the resulting Link training must use the modified values If the LTSSM is already in Recovery or Configuration the modified values are not required to affect the Link training that s already in progress Link Disable LD 0 Normal operation 1 Link is disabled Forces the LTSSM to transition to the Disabled state 4 RW Ob using Recovery from LO LOs or L1 states Link retraining happens automatically on 0 to 1 transition just like when coming out of reset Writes to this bit are immediately reflected in the value read from the bit regardless of actual Link state Read Completion Boundary RCB Hardwired to 0 to indicate 64 byte 2 RO Ob Reserved Active State PM ASPM This bit controls the level of active state power management supported on the given link 00 Disabled 01 LOs Entry Supported 10 L1 Entry Enabled 11 LOs and L1 Entry Supported 1 0 RW 00b Note LOs Entry Enabled indicates the Transmitter entering LOs is supported The Receiver must be capable of entering LOs even when the field is disabled 00b ASPM L1 must be enabled by software in the Upstream component on a Link prior to enabling ASPM L1 in the Downstream component on that Link When disabling ASPM L1 software must disable ASPM L1 in the Downstream component on a Link prior to disabling ASPM L1 in the Upstream component on that Link ASPM L1 must only be enabled on the Downstream component if both components on a Link supp
496. this bit as reserved Invalidation Completion Error 1 CE Hardware received an unexpected or invalid Device OTLB invalidation completion This could be due to either an invalid ITag or invalid source id in 5 RO Ob an invalidation completion response At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting Device OTLBs implement this bit as reserved Invalidation Queue Error 1QE Hardware detected an error associated with the invalidation queue This could be due to either a hardware error while fetching a descriptor from the Ob invalidation queue or hardware detecting an erroneous or invalid descriptor in the invalidation queue At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting queued invalidations implement this bit as reserved Advanced Pending Fault APF When this field is Clear hardware sets this field when the first fault record at 3 RO Ob index 0 is written to a fault log At this time a fault event is generated based on the programming of the Fault Event Control register Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as reserved Advanced Fault Overflow AFO Hardware sets this field to indicate advanced fault log overflow condition At Ob this
497. ting of this condition using SCI messaging Datasheet Volume 2 105 intel 2 8 52 106 TINTRCMD Thermal INTR Command Register Processor Configuration Registers This register selects specific errors to generate a INT DMI cycle B D F Type 0 0 0 MCHBAR Address Offset 10E7h Reset Value 00h Access RO RW Reset ee Bit Attr Value Description 7 6 RO 00b Reserved 5 RW Ob INTR on Catastrophic Thermal Sensor Trip CATI NTR 1 AINTR DMI cycle is generated by the processor 4 RW Ob INTR on Hot Thermal Sensor Trip HOTI NTR 1 A INTR DMI cycle is generated by the processor 3 RW Ob INTR on AUX3 Thermal Sensor Trip AUX3I NTR 1 A INTR DMI cycle is generated by the processor 2 RW Ob INTR on AUX2 Thermal Sensor Trip AUX2I NTR 1 AINTR DMI cycle is generated by the processor 1 RW Ob INTR on AUX1 Thermal Sensor Trip AUX1I NTR 1 A INTR DMI cycle is generated by the processor 0 RW Ob INTR on AUXO Thermal Sensor Trip AUXOI NTR 1 AINTR DMI cycle is generated by the processor Datasheet Volume 2 Processor Configuration Registers intel 2 8 53 EXTTSCS External Thermal Sensor Control and Status Register B D F Type 0 0 0 MCHBAR Address Offset 10EC 10EDh Reset Value 0000h Access RO RW O RW L 5 Reset ingi Bit Attr Value Description External Sensor Enable ESE Setting this bit to 1 locks the lockable bits in this
498. tion TLP is generated on the secondary side of the PCI Express link PCI Express Configuration Writes e Internally the processor will translate writes to PCI Express extended configuration space to configuration writes on the backbone Posted writes to extended space are non posted on the PCI Express or DMI that is translated to configuration writes Datasheet Volume 2 Processor Configuration Registers 7 t 2 4 5 2 2 5 DMI Configuration Accesses Accesses to disabled processor internal devices bus numbers not claimed by the Host PCI Express bridge or PCI Bus 0 devices not part of the processor will subtractively decode to the PCH and consequently be forwarded over the DMI using a PCI Express configuration TLP If the Bus Number is zero the processor will generate a Type 0 Configuration cycle TLP on DMI If the Bus Number is non zero and falls outside the range claimed by the Host PCI Express bridge the processor will generate a Type 1 Configuration cycle TLP on DMI The PCH routes configurations accesses in a manner similar to the processor The PCH decodes the configuration TLP and generates a corresponding configuration access Accesses targeting a device on PCI Bus 0 may be claimed by an internal device The PCH compares the non zero Bus Number with the Secondary Bus Number and Subordinate Bus Number registers of its PCI to PCI bridges to determine if the configuration access is meant for Primary PCI or some ot
499. tion Tracking Queue entries equals or falls below the value programmed in this field PEG1 VCO Write VT fetch is throttled until the number of free PEG1 Completion 24 20 RW L 00000b Tracking Queue entries rise above this threshold For example 00000 Throttle PEG1 VCO Write VT Fetch when there is no entry left 00001 Throttle PEG1 VCO Write VT Fetch when there is 1 or less entry left 00010 Throttle PEG1 VCO Write VT Fetch when there is 2 or less entry left 00011 Throttle PEG1 VCO Write VT Fetch when there is 3 or less entry left 00100 Throttle PEG1 VCO Write VT Fetch when there is 4 or less entry left PEG1 VCO Read VT Completion Tracking Queue Resource Threshold PEG1VCORDCTQRTCT This field provides a 1 based minimum threshold value used to throttle PEG1 VCO Read VT fetch When the number of free PEG1 VT Completion Tracking Queue entries equals or falls below the value programmed in this field PEG1 VCO Read VT fetch is throttled until the number of free PEG1 Completion 19 15 RW L 00000b Tracking Queue entries rise above this threshold For example 00000 Throttle PEG1 VCO Read VT Fetch when there is no entry left 00001 Throttle PEG1 VCO Read VT Fetch when there is 1 or less entry left 00010 Throttle PEG1 VCO Read VT Fetch when there is 2 or less entry left 00011 Throttle PEG1 VCO Read VT Fetch when there is 3 or less entry left 00100 Throttle PEG1 VCO Read VT Fetch when there is 4 or less entry left
500. tries need to be selectively invalidated This field must be programmed by software for both domain selective and device selective invalidation requests The Capability register reports the domain id width supported by hardware Software must ensure that the value written to this field is within this limit Hardware ignores and may not implement bits 15 N where N is the supported domain id width reported in the capability register 15 0 RW 0000h Datasheet Volume 2 267 Processor Configuration Registers intel 2 18 8 FSTS_ REG Fault Status Register This register indicates the various error statuses B D F Type 0 2 0 GFXVTBAR Address Offset 34 37h Reset Value 00000000h Access RO RW1C S RO V S Reset inii Bit Attr Value Description 31 16 RO 0000h_ Reserved Fault Record I ndex FRI This field is valid only when the PPF field is Set 15 8 RO V S 00h The FRI field indicates the index from base of the fault recording register to which the first pending fault was recorded when the PPF field was Set by hardware The value read from this field is undefined when the PPF field is Clear 7 RO Ob Reserved Invalidation Time out Error ITE Hardware detected a Device OTLB invalidation completion time out At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting Device OTLBs implement
501. ts an interrupt condition Interrupt condition is defined as e An Invalidation Wait Descriptor with Interrupt Flag IF field Set completed setting the IWC field in the Invalidation Completion Status register e If the IWC field in the Invalidation Completion Status register was already Set at the time of setting this field it is not treated as a new interrupt condition The IP field is kept Set by hardware while the interrupt message is held pending The interrupt message could be held pending due to interrupt mask IM field being set or due to other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field e Software servicing the IWC field in the Invalidation Completion Status register 00 00b Reserved Datasheet Volume 2 245 Processor Configuration Registers intel 2 16 24 EDATA_REG Invalidation Event Data Register This register specifies the Invalidation Event interrupt message data This register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 DMIVC1REMAP Address Offset A4 A7h Reset Value
502. ttling so even if both the Gfx monitor and global monitor are disabled the sampling window must be programmed in order to have EXTTS work as a graphics throttle Force DDR on EXTTS bit EXTTFMX Enables forcing of DDR to specified MX state in registers EXTTSMXST when 11 RW L Ob the selected EXTTS bit 0 or 1 from exttpinsel field is asserted Note PMU looks at all enabled throttling and picks the highest value of Mx for EXTTS or from the global power M state or any other throttling and passes it to the SD unit EXTTSS Programmable MX state EXTTSMXST MX state to which DDR to be forced to if EXTTS bit 0 asserts and Force DDR 10 8 RW L 000b on EXTTS bit EXTTFMX is enabled l l l Note PMU looks at all enabled throttling and picks the highest value of Mx for EXTTS or from the global power M state or any other throttling and passes it to the SD unit Force SD 2X Refresh Rate SD2X 7 RW L Ob When enabled on EXTTS bit 0 getting asserted will force memory into 2X Refresh mode Datasheet Volume 2 107 108 Processor Configuration Registers B D F Type Address Offset Reset Value 0 0 0 MCHBAR 10EC 10EDh 0000h Access RO RW O RW L Reset Be Bit Attr Value Description Throttling Type Select TTS Lockable by EXTTSCS External Sensor Enable If External Thermal Sensor Enable 1 then 0 DRAM throttling based on the settings in the Device 0 6 RW L Ob MCHBAR DRAM Th
503. ttr Reset Value Description Ob Internal Thermal Hardware Throttling Enable I THTE This bit is a master enable for internal thermal sensor based hardware throttling 0 Hardware actions using the internal thermal sensor are disabled 1 Hardware actions using the internal thermal sensor are enabled Ob Reserved Ob Use Direct Catastrophic Trip for HOC UDCTHOC 1 Catastrophic trip output of DTS circuit is used to control THRMTRIP 0 Thermometer comparison to catastrophic trip value is used to control THRMTRIP Ob Throttle Zone Selection TZS This bit determines what temperature zones will enable autothrottling This register applies to internal thermal sensor throttling Lockable by bit 0 of this register 0 Hot Aux2 and Catastrophic 1 Hot and Catastrophic il Ob Halt on Catastrophic HOC When this bit is set THRMTRIP is asserted on catastrophic trip to bring the platform down A system reboot is required to bring the system out of a halt from the thermal sensor Once the catastrophic trip point is reached THRMTRIP will stay asserted even if the catastrophic trip de asserts before the platform is shut down 2 1 RO 00b Reserved Ob Hardware Throttling Lock Bit HTL This bit locks bits 7 1 of this register When this bit is set to a one the register bits are locked It may only be set to a 0 by a hardware reset Writing a 0 to this bit has no effe
504. ttr Value Description Protected High Memory Region PHMR 0 Indicates protected high memory region is not supported 1 Indicates protected high memory region is supported DMA remapping hardware implementations on Intel TXT platforms supporting main memory above 4 GB are required to support protected high memory region Protected Low Memory Region PLMR 0 Indicates protected low memory region is not supported 1 Indicates protected low memory region is supported DMA remapping hardware implementations on Intel TXT platforms are required to support protected low memory region Required Write Buffer Flushing RWBF 0 Indicates no write buffer flushing is needed to ensure changes to memory resident structures are visible to hardware 1 Indicates software must explicitly flush the write buffers to ensure updates made to memory resident remapping structures are visible to hardware Refer to the VTd specification for more details on write buffer flushing requirements Advanced Fault Logging AFL 0 Indicates advanced fault logging is not supported Only primary fault logging is supported 1 Indicates advanced fault logging is supported 2 0 RO 00b Number of domains supported ND 000b 4 bit domain Ds with support for up to 16 domains 001b 6 bit domain IDs with support for up to 64 domains 010b 8 bit domain IDs with support for up to 256 domains 011b 10 bit domain IDs with supp
505. tures in memory B D F Type 0 0 0 DMIVCLREMAP Address Offset 64 67h Reset Value 00000000h Access RW RO Reset opis Bit Attr Value Description Enable Protected Memory EPM This field controls DMA accesses to the protected low memory and protected high memory regions 0 Protected memory regions are disabled 1 Protected memory regions are enabled DMA requests accessing protected memory regions are handled as follows When DMA remapping is not enabled all DMA requests accessing protected memory regions are blocked When DMA remapping is enabled DMA requests processed as pass through Translation Type value of 10b in Context Entry and accessing the protected memory regions are blocked DMA requests with translated address AT 10b and accessing the protected 31 RW Ob memory regions are blocked l l DMA requests that are subject to address remapping and accessing the protected memory regions may or may not be blocked by hardware For such requests software must not depend on hardware protection of the protected memory regions and instead program the DMA remapping page tables to not allow DMA to protected memory regions Remapping hardware access to the remapping structures are not subject to protected memory region checks DMA requests blocked due to protected memory region violation are not recorded or reported as remapping faults Hardware reports the status of the protected memory enable disable op
506. turned on read of this field is undefined Set Root Table Pointer SRTP Software sets this field to set update the root entry table pointer used by hardware The root entry table pointer is specified through the Root entry Table Address register Hardware reports the status of the root table pointer set operation through the RTPS field in the Global Status register The root table pointer set operation must be performed before enabling or re enabling after disabling DMA remapping through the TE field After a root table pointer set operation software must globally invalidate the 30 w Ob context cache followed by global invalidate of OTLB This is required to ensure hardware uses only the remapping structures referenced by the new root table pointer and not any stale cached entries While DMA remapping hardware is active software may update the root table pointer through this field However to ensure valid in flight DMA requests are deterministically remapped software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root table pointer Clearing this bit has no effect Value returned on read of this field is undefined Set Fault Log SFL This field is valid only for implementations supporting advanced fault logging Software sets this field to request hardware to set update the fault log pointer used by hardware
507. ubject to remapping or not at all Hardware implementations must drain any in flight interrupts requests queued in the Root Complex before completing the interrupt remapping enable command and reflecting the status of the command through the IRES field in the Global Status register The value returned on a read of this field is undefined Set Interrupt Remap Table Pointer SIRTP This field is valid only for implementations supporting interrupt remapping Software sets this field to set update the interrupt remapping table pointer used by hardware The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address register Hardware reports the status of the interrupt remapping table pointer set operation through the IRTPS field in the Global Status register The interrupt remap table pointer set operation must be performed before enabling or re enabling after disabling interrupt remapping hardware through the IRE field 24 Ww Ob After an interrupt remap table pointer set operation software must globally invalidate the interrupt entry cache This is required to ensure hardware uses only the interrupt remapping entries referenced by the new interrupt remap table pointer and not any stale cached entries While interrupt remapping is active software may update the interrupt remapping table pointer through this field However to ensure valid in flight interrupt requests are deterministically remapped software
508. ue Description 63 12 RO 00000000 00000h Fault Log Address FLA This field specifies the base of 4KB aligned fault log region in system memory Hardware may ignore and not implement bits 63 HAW where HAW is the host address width Software specifies the base address and size of the fault log region through this register and programs it in hardware through the SFL field in the Global Command register When implemented reads of this field returns value that was last programmed to it 000b Fault Log Size FLS This field specifies the size of the fault log region pointed by the FLA field The size of the fault log region is 2 X 4KB where X is the value programmed in this register 000 4 KB 001 8 KB 010 16 KB 011 32 KB 100 64 KB 101 128 KB 110 256 KB 111 512 KB When implemented reads of this field returns value that was last programmed to it 8 0 RO 000h Reserved Datasheet Volume 2 237 intel Processor Configuration Registers 2 16 14 PMEN_REG Protected Memory Enable Register This register enables the DMA protected memory regions set up through the PLMBASE PLMLIMT PHMBASE PHMLIMIT registers This register is treated as RO for implementations not supporting protected memory regions PLMR and PHMR fields reported as Clear in the Capability register Protected memory regions may be used by software to securely initialize remapping struc
509. ue 0000_0000h Access RO A Reset PS Bit Attr Value Description 31 12 RO 00000h Reserved 11 10 RO 00b Reserved Reserved for Port Arbitration Table Entry Size 9 8 RO 00b Reserved Reserved for Reference Clock 7 RO Ob Reserved Low Priority Extended VC Count LPEVCC Indicates the number of extended Virtual Channels in addition to the 6 4 RO 000b default VC belonging to the low priority VC LPVC group that has the lowest priority with respect to other VC resources in a strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration 3 RO Ob Reserved Extended VC Count EVCC 2 0 RO 000b Indicates the number of extended Virtual Channels in addition to the default VC supported by the device 328 Datasheet Volume 2 Processor Configuration Registers intel 2 20 2 PVCCAP2 Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 6 0 MMR Address Offset 108 10Bh Reset Value 0000_0000h Access RO Reset igi Bit Attr Value Description VC Arbitration Table Offset VCATO This field indicates the location of the VC Arbitration Table This field contains 31 24 RO 00h the zero based offset of the table in DQWORDS 16 bytes from the base address of the Virtual Channel Capability Structure A value of 0 indicates that the table is not present due to fixed VC priority 23 8 RO 0000h
510. ue Description Device Identification Number DID 15 0 RO 0042h This is a 16 bit value assigned to the processor Graphics device 2 13 3 PCI CMD2 PCI Command Register This 16 bit register provides basic control over the IGD ability to respond to PCI cycles The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory B D F Type 0 2 0 PCI Address Offset 4 5h Reset Value 0000h Access RO RW Reset er Bit Attr Value Description 15 11 RO 00h Reserved 10 10 RO Oh Reserved 9 RO Ob Fast Back to Back FB2B Not Implemented Hardwired to 0 SERR Enable SERRE Not Implemented Hardwired to 0 Address Data Stepping Enable ADSTEP Not Implemented Hardwired to 0 Parity Error Enable PERRE Not Implemented Hardwired to 0 Since the IGD belongs to the category of 6 RO Ob devices that does not corrupt programs or data in system memory or hard drives the IGD ignores any parity error that it detects and continues with normal operation Video Palette Snooping VPS RO ob This bit is hardwired to 0 to disable snooping Memory Write and I nvalidate Enable MWIE 4 RO Ob Hardwired to 0 The IGD does not support memory write and invalidate commands 3 RO Ob Special Cycle Enable SCE This bit is hardwired to 0 The IGD ignores Special cycles Bus Master Enable BME 2 RW Ob 0 Disable IGD bus mastering 1 Enable the IGD to function as
511. ue for the Aux3 trip point Lockable by TSTTPA1 31 Aux 2 Trip Point Setting A2TPS 23 1 RW L 00h i Sets the target value for the Aux2 trip point Lockable by TSTTPA1 31 Aux 1 Trip Point Setting A1TPS 15 RW L 00h g Sets the target value for the Aux1 trip point Lockable by TSTTPA1 31 7 0 RW L ooh Aux 0 Trip Point Setting AOTPS Sets the target value for the Aux0 trip point Lockable by TSTTPA1 31 TS10BI TMCTRL Thermal Sensor 10 bit Mode Control Register B D F Type 0 0 0 MCHBAR Address Offset 1018 1019h Reset Value 0000h Access RW L BIOS Optimal Reset Value 00h A Reset Pee Bit Attr Value Description Thermal Sensor 10 bit Mode Enable TS10BI TEN 0 Normal operation DTS 8 bit mode 15 RW L Ob 1 DTS is operating in 10 bit mode ROTS1OBIT calculation is applied to TRI Locked by LBC 14 10 RO Oh Reserved Relative Offset when Thermal Sensor is Operating in 10 bit Mode ROTS10BIT Software needs to program this field such that the following equation is ensured to yield an 8 bit value 9 0 RW L 000h TR ROTSLOBIT Raw Temp Code from DTS TR 9 8 should always be 0 TR 7 0 is reported in the TR1 register Locked by LBC Datasheet Volume 2 Processor Configuration Registers intel 2 8 46 HWTHROTCTRL1 Hardware Throttle Control 1 Register B D F Type Address Offset Reset Value Access 0 0 0 MCHBAR 101Ch 00h RW L RO RW O Bit A
512. uence which must be done in order without any other configuration cycles in between write testtpal 04C1C202 write testtpal 04C15202 write testtpal 04C1C202 It is expected that the Aux x Trip point settings can be changed dynamically when this lock is not set 30 RW L Ob Lock Bit for Catastrophic LBC This bit when written to a 1 locks the Catastrophic programming interface including bits 7 0 of TSTTPA 15 0 bits 15 and 9 of TSC and bits 10 and 8 of TST1 This bit may only be set to a 0 by a hardware reset Writing a 0 to this bit has no effect 29 16 RO 0000h Reserved 15 8 RW L 00h Hot Trip Point Setting HTPS Sets the target value for the Hot trip point Lockable using TSTTPA1 bit 30 7 0 RW L 00h Catastrophic Trip Point Setting CTPS This field sets the target for the Catastrophic trip point See TST Direct DAC Connect Test Enable Lockable using TSTTPA1 bit 30 Datasheet Volume 2 97 intel 2 8 44 2 8 45 98 Processor Configuration Registers TSTTPB1 Thermal Sensor Temperature Trip Point B1 Register This register sets the target values for some of the trip points in the Thermometer mode See also TSTTPAL B D F Type 0 0 0 MCHBAR Address Offset 1014 1017h Reset Value 0000_0000h Access RW L i Reset ae Bit Attr Value Description Aux 3 Trip Point Setting A3TPS 31 24 RW L 00h Sets the target val
513. ueue Head QH This field specifies the offset 128 bit aligned to the invalidation queue for the command that will be fetched next by hardware Hardware resets this field to O whenever the queued invalidation is disabled QIES field Clear in the Global Status register 3 0 RO Oh Reserved Datasheet Volume 2 Processor Configuration Registers intel 2 15 20 IQT_REG Invalidation Queue Tail Register Register indicating the invalidation tail head This register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 88 8Fh Reset Value 0000000000000000h Access RO Reset ar Bit Attr Value Description i 00000000 Reserved 63 19 RO 0000h Queue Tail QT 18 4 RO 0000h This field specifies the offset 128 bit aligned to the invalidation queue for the command that will be written next by software 3 0 RO Oh Reserved 2 15 21 1I1QA_REG Invalidation Queue Address Register Register to configure the base address and size of the invalidation queue This register is treated as reserved by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register When supported writing to this register causes the I nvalidation Queue Head and I nvalidation Queue Tail registers to be reset to Oh B D F Type 0 0 0
514. ulating refreshes 1 X Normal refresh enable 24 RW Ob All Rank Refresh ALLRKREF This configuration bit enables by default that all the ranks are refreshed in a staggered atomic fashion If set the ranks are refreshed in an independent fashion 0 Ranks are refreshed atomically staggered 1 Ranks are refreshed independently 23 RW Ob Refresh Enable REFEN 0 Disabled 1 Enabled 22 RW Ob DDR Initialization Done INI TDONE Indicates that DDR initialization is complete Datasheet Volume 2 79 80 Processor Configuration Registers B D F Type 0 0 0 MCHBAR Address Offset 269 26Eh Reset Value 241830000C30h Access RW RO i Reset E Bit Attr Value Description DRAM Refresh Hysterisis REFHYSTERI SI S Hysterisis level useful for dref _high watermark cases The dref_high flag is set when the dref_high watermark level is exceeded and is cleared when the refresh count is less than the hysterisis level This bit should be set to a value 21 20 RW 00b less than the high watermark level 00 3 01 4 10 5 11 6 DRAM Refresh Panic Watermark REFPANICWM When the refresh count exceeds this level a refresh request is launched to the scheduler and the dref_panic flag is set 19 18 RW 00b 00 5 01 6 10 7 11 8 DRAM Refresh High Watermark REFHIGHWM When the refresh count exceeds this level a refresh request is launched to the scheduler and
515. umed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC that is prefetchable from the processor perspective B D F Type 0 6 0 PCI Address Offset 2C 2Fh Reset Value 00000000h Access RW Reset caer Bit Attr Value Description 31 0 RW 00000000 Prefetchable Memory Address Limit MLI MI TU h This field corresponds to A 63 32 of the upper limit of the prefetchable Memory range that will be passed to PCI Express G 2 19 21 CAPPTR6 Capabilities Pointer Register The capabilities pointer provides the address offset to the location of the first entry in this device s linked list of capabilities B D F Type 0 6 0 PCI Address Offset 34h Reset Value 88h Access RO Reset er Bit Attr Value Description First Capability CAPPTR1 7 0 RO 88h The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability Datasheet Volume 2 303 Processor Configuration Registers intel 2 19 22 INTRLINE6 Interrupt Line Register This register contains interrupt line routing information The device itself does not use this value rather it is used by device drivers and operating systems to det
516. undefined Write Buffer Flush WBF This bit is valid only for implementations requiring write buffer flushing Software sets this field to request hardware to flush the root complex internal write buffers This is done to ensure any updates to the memory resident DMA remapping structures are not held in any internal write posting 27 Ww Ob buffers Refer to the VTd specification for details on write buffer flushing requirements Hardware reports the status of the write buffer flushing operation through the WBFS field in the Global Status register Clearing this bit has no effect Value returned on read of this field is undefined Queued I nvalidation Enable QIE This field is valid only for implementations supporting queued invalidations Software writes to this field to enable or disable queued invalidations 0 Disable queued invalidations 26 RO Ob 1 Enable use of queued invalidations Hardware reports the status of queued invalidation enable operation through QIES field in the Global Status register Refer to the VTd specification for software requirements for enabling disabling queued invalidations The value returned on a read of this field is undefined Interrupt Remapping Enable I RE This field is valid only for implementations supporting interrupt remapping 0 Disable interrupt remapping hardware 1 Enable interrupt remapping hardware Hardware reports the status of the interrupt remapping enable op
517. us Number BUSN 7 0 RW 00h This field is programmed by configuration software with the bus number assigned to PCI Express G 2 19 11 SUBUSN6 Subordinate Bus Number Register This register identifies the subordinate bus if any that resides at the level below PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G B D F Type 0 6 0 PCI Address Offset 1Ah Reset Value 00h Access RW Reset Poe Bit Attr Value Description Subordinate Bus Number BUSN This register is programmed by configuration software with the number of 7 0 RW 00h the highest subordinate bus that lies behind the device 6 bridge When only a single PCI device resides on the PCI Express G segment this register will contain the same value as the SBUSN6 register Datasheet Volume 2 295 intel 2 19 12 2 19 13 296 Processor Configuration Registers 1 OBASE6 I O Base Address Register This register controls the processor to PCI Express G I O access routing based on the following formula 10_BASE lt address lt IO_LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are treated as 0 Thus the bottom of the defined I O address range will be aligned to a 4 KB boundary B D F Type 0 6 0 PCI Address Offset 1Ch Reset Value FOh Access RW RO n Reset Jii Bit Attr Value D
518. ust be written simultaneously in order to prevent an intermediate and undesired value from ever existing ll 14 12 RW O 010b LOs Exit Latency LOSELAT This field indicates the length of time this Port requires to complete the transition from LOs to LO 000 Less than 64 ns 001 64 ns to less than 128 ns 010 128 ns to less than 256 ns 011 256 ns to less than 512 ns 100 512 ns to less than 1 us 101 1 us to less than 2 us 110 2 us 4 us 111 More than 4 us ll ll ll ll 11 10 RO 11b Active State Link PM Support ASLPMS LOs and L1 entry supported 9 4 RO 04h Max Link Width MLW This field indicates the maximum number of lanes supported for this link 3 0 RO 1h Max Link Speed MLS Hardwired to indicate 2 5 Gb s Datasheet Volume 2 Processor Configuration Registers 2 12 19 DMILCTL DMI Link Control Register This register allows control of DMI B D F Type Address Offset Reset Value Access 0 0 0 DMIBAR 88 89h 0000h RO RW Bit Attr Reset Value Description 15 8 RO 00h Reserved Ob Extended Synch EXTSYNC 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state and when in the Recovery state This mode provides external devices such as logic analyzers monitoring the Link time to achieve bit and symbol lock before the
519. validate the context cache followed by global invalidate of IOTLB This is required to ensure hardware uses only the remapping structures referenced by the new root table pointer and not any stale cached entries While DMA remapping hardware is active software may update the root table pointer through this field However to ensure valid in flight DMA requests are deterministically remapped software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root table pointer Clearing this bit has no effect The value returned on read of this field is undefined 29 Ww Ob Set Fault Log SFL This field is valid only for implementations supporting advanced fault logging If advanced fault logging is not supported writes to this field are ignored Software sets this field to request hardware to set update the fault log pointer used by hardware The fault log pointer is specified through Advanced Fault Log register Hardware reports the status of the fault log set operation through the FLS field in the Global Status register The fault log pointer must be set before enabling advanced fault logging through EAFL field Once advanced fault logging is enabled the fault log pointer may be updated through this field while DMA remapping hardware is active Clearing this bit has no effect The value returned on read of this field
520. w or outstanding transactions with the TC labels are targeted at the given Link TCO VCO Map TCOVCOM Traffic Class 0 is always routed to VCO Datasheet Volume 2 331 Processor Configuration Registers intel 2 20 6 VCORSTS VCO Resource Status Register B D F Type 0 6 0 MMR Address Offset 11A 11Bh Reset Value 0002h Access RO A Reset duce Bit Attr Value Description 15 2 RO 0000h Reserved MBZ VCO Negotiation Pending VCONP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control initialization It is 1 RO 1b set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link ill 0 RO Ob Reserved for Port Arbitration Table Status 2 21 Intel Trusted Execution Technology Intel TXT Specific Registers Intel TXT configuration registers are a subset of chipset registers These registers are mapped into two regions of memory representing the public and private configuration spaces Registers in the private space can only be accessed after a
521. ware unit Refer to the VTd specification for software programming requirements Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flush before invalidating the IOTLB Refer to the VTd specification for write buffer flushing requirements IOTLB I nvalidation Request Granularity 11 RG When requesting hardware to invalidate the OTLB by setting the IVT field software writes the requested invalidation granularity through this IIRG field Following are the encodings for the IIRG field 000 Reserved 001 Global invalidation request 010 Domain selective invalidation request The target domain id must be specified in the DID field 011 Domain page selective invalidation request The target address mask and invalidation hint must be specified in the Invalidate Address register and the domain id must be provided in the DID field 100 111 Reserved Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalidation request by clearing the IVT field At this time the granularity at which actual invalidation was performed is reported through the IAIG field 62 60 RW 000b Datasheet Volume 2 249 250 Processor Configuration Registers B D F Type Address Offset Reset Value 0 0 0
522. ware fixed arbitration scheme Datasheet Volume 2 Processor Configuration Registers intel 2 9 5 EPVC1RCTL EP VC 1 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 1 B B D F Type 0 0 0 PXPEPBAR Address Offset 20 23h Reset Value 0100_0000h Access RW RO Reset eae Bit Attr Value Description VC1 Enable VC1E This bit will be ignored by the hardware The bit is RW for specification compliance but writing to it will result in no behavior change in the hardware other than the bit value reflecting the written value 0 Virtual Channel is disabled 1 Virtual Channel is enabled See exceptions in notes below Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete When VC Negotiation Pending bit is cleared a 1 read from this VC Enable bit indicates that the VC is enabled Flow Control 31 RW Ob Initialization is completed for the PCI Express port A 0 read from this bit indicates that the Virtual Channel is currently disabled Notes 1 To enable a Virtual Channel the VC Enable bits for that Virtual Channel must be set in both Components on a Link 2 To disable a Virtual Channel the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link 3 Software must ensure that no traffic is using a Virtual Channel at the time it is disabled 4 Software
523. with a value of Ob Reserved for Electromechanical Interlock Control EIC 11 RO 0b If an Electromechanical Interlock is implemented a write of 1b to this field causes the state of the interlock to toggle A write of Ob to this field has no effect A read to this register always returns a 0 Reserved for Power Controller Control PCC If a Power Controller is implemented this field when written sets the power state of the slot per the defined encodings Reads of this field must reflect the value from the latest write even if the corresponding hotplug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined Depending on the form factor the power is turned on off either to the slot or within the adapter Note that in some cases the power controller may 10 RO Ob autonomously remove slot power or not respond to a power up request based on a detected fault condition independent of the Power Controller Control setting The defined encodings are Ob Power On 1b Power Off If the Power Controller Implemented field in the Slot Capabilities register is set to Ob then writes to this field have no effect and the read value of this field is undefined Reserved Power Indicator Control PIC If a Power Indicator is implemented writes to this field set the Power Indicator to the written state Reads of this field must reflect the value from the latest write even
524. writable bit field becomes Read Only Conceptually this may be a cascaded lock or it may be self locking when in its non default state When self locking it differs from RW O in that writing back the Reset Value will not set the lock RW V Write Volatile bit s These bits can be read and written by software Hardware may set or clear the bit based on internal events possibly sooner than any subsequent software read could retrieve the value written Datasheet Volume 2 15 Table 2 1 16 intel Processor Configuration Registers Register Terminology Sheet 2 of 2 Item Description RW V L Read Write Volatile Lockable bit s These bits can be read and written by software Hardware may set or clear the bit based upon internal events possibly sooner than any subsequent software read could retrieve the value written Additionally there is a bit which is marked RW K or RW L K that when set prohibits this bit field from being writable bit field becomes Read Only RW V L S Read Write Volatile Lockable Sticky bit s These bits can be read and written by software Hardware may set or clear the bit based upon internal events possibly sooner than any subsequent software read could retrieve the value written Additionally there is a bit which is marked RW K or RW L K that when set prohibits this bit field from being writable bit field becomes Read Only These bits return to their
525. y applies to DMA accesses and GMADR translations It serves a purpose of providing a memory range that is only accessible to processor streams The DPR range works independent of any other range including the PMRC checks in VTd It occurs post any VTd translation Therefore incoming cycles are checked against this range after the VTd translation and faulted if they hit this protected range even if they passed the VTd translation The system will set up 1 O to TSEG_BASE DPR size 1 for DMA traffic 2 TSEG_BASE to TSEG_BASE DPR size as no DMA After some time software could request more space for not allowing DMA It will get some more pages and make sure there are no DMA cycles to the new region DPR size is changed to the new value When it does this there should not be any DMA cycles going to DRAM to the new region If there were cycles from a rogue device to the new region then those could use the previous decode until the new decode can ensure PV No flushing of cycles is required On a clock by clock basis proper decode with the previous or new decode needs to be ensured All upstream cycles from 0 to TSEG_BASE 1 DPR size and not in the legacy holes VGA are decoded to dram Pre allocated Memory Voids of physical addresses that are not accessible as general system memory and reside within system memory address range lt TOLUD are created for SMM mode legacy VGA graphics compatibility and graphics GTT stolen
526. ze 64 MB This register is locked by Memory pre allocated for ME lock Datasheet Volume 2 Processor Configuration Registers intel 2 8 4 CODRB1 Channel 0 DRAM Rank Boundary Address 1 Register See CODRBO register description for details B D F Type 0 0 0 MCHBAR Address Offset 202 203h Reset Value 0000h Access RW L RO s Reset peer Bit Attr Value Description 15 10 RO 00h Reserved Channel 0 DRAM Rank Boundary Address 1 CODRBA1 This register defines the DRAM rank boundary for rank1 of Channel 0 64 MB granularity R1 RO 9 0 RW L 000h RO Total rankO memory size 64 MB R1 Total rank1 memory size 64 MB R2 Total rank2 memory size 64 MB R3 Total rank3 memory size 64 MB This register is locked by Memory pre allocated for ME lock 2 8 5 CODRB2 Channel 0 DRAM Rank Boundary Address 2 Register See CODRBO register description for details B D F Type 0 0 0 MCHBAR Address Offset 204 205h Reset Value 0000h Access RO RW L Reset ar Bit Attr Value Description 15 10 RO 00h Reserved Channel 0 DRAM Rank Boundary Address 2 CODRBA2 This register defines the DRAM rank boundary for rank2 of Channel 0 64 MB granularity R2 R1 RO 9 0 RW L 000h RO Total rankO memory size 64 MB R1 Total rankl memory size 64 MB R2 Total rank2 memory size 64 MB R3 Total rank3 memory size 64 MB This register is locked by Memory

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