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10-W Inductor Free Stereo (BTL) Class-D Audio Amplifier with

1. PVCCL PVCCL A PBTL Select OUTPL FB Gate rs Drive X OUTPL FB w _ LK A l L LINP om PWM pk PLIMIT Logic ontrol PVCCL LINN yh WW T OUTNL FB W A VEE OUTNL FB ry T 3D A A k Ingle gt GAIN Buffer SC Detect Gain Control z y DC Detect Ramp Biases and Startup Protection Spread Spectrum _ Generator References Logic M Thermal SSCTRL Control Detect UVLO OVLO LIMITER r LIMRES Recs avon PVCCL AVDD PyccL W LDO AVEC Regulator A GVDD GYDD A H OUTNR FB Wv A OUTNR FB Ly RINN yh F ow Ll Gain PLIMIT Control RINP yh be oe sph WV T PyccL W OUTNR FB Wv o A H Gate FA Drive if PBTL Select _ ke s A OUTPR FB Ly 10 3 Feature Description 10 3 1 Gain Setting via GAIN Pin The gain of the TPA3140D2 is set by a voltage applied to the GAIN pin which is set by a resistor voltage divider with GVDD as supply voltage The resistance of the voltage divider should be a minimum of 100 kQ in order not to overload the GVDD regulator of TPA3140D2 12 Submit Documentation Feedback Product Folder Links TPA3140D2 BSPL OUTPL GND BSNL OUTNL BSN
2. 16 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS www ti com TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 Table 3 LIMTHRES Typical Operation man OUTPUT OUTPUT LIMTHRES POWER W POWER W ae IONS voLTAGE v to GND RtoGVDD UYNCLIPPED 10 THD AGL PLIMIT PVCC 12 V 1 9 33 kQ 82 KQ 4 75 6 A 60 PVCC 12 V 2 2 39 KQ 82 kO 6 5 8 R 60 PVCC 12 V 25 39 kQ 68 kQ 8 10 R 60 PVCC 14 4 2 2 39 KQ 82 KQ 4 75 6 V RL 89 PVCC 14 4 25 39 kO 68 kQ 6 5 8 V R 89 PVCC 14 4 28 47 kQ 68 KQ 8 10 V RL 89 AGL UNCLIPPED 80 PLIMIT 10 THD 8Q AGL UNCLIPPED 60 PLIMIT 10 THD 6Q LIMTHRES V LIMTHRES V 6 Max Output Power W Figure 21 Max Output Power vs LIMTHRES 8 Q PVCC 13 V Max Output Power W Figure 22 Max Output Power vs LIMTHRES 6 Q PVCC 12V 10 3 8 Spread Spectrum and De Phase Control The TPA3140 has built in spread spectrum control of the oscillator frequency and de phase of the PWM outputs to improve EMI performance Two spread spectrum schemes can be selected and for operation without spread spectrum de phase can be turned off De phase inverts the phase of the output PWM such that the idle output PWM waveforms of the two audio channels are
3. 34 022 21 763 45 308 20 387 0 552 56 46 28 872 17 128 39 164 16 836 0 554 56 46 29 574 16 426 40 485 15 515 0 806 56 46 21 341 24 659 29 585 26 415 0 735 56 46 22 652 23 348 3252 23 48 0 95 56 46 22 678 23 322 31 471 24 529 0 918 56 46 22 699 23 301 31 849 24 151 1 485 56 46 22 622 23 378 31 082 24 918 1 402 56 46 23 264 22 736 32 173 23 827 1 976 56 46 20 952 25 048 29 849 26 151 7 806 60 50 28 006 21 994 35 214 24 786 Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 www ti com 12 Power Supply Recommendations 12 1 Power Supply Decoupling Cs The TPA3140D2 is a high performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion THD is as low as possible Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of noise on the power supply leads For higher frequency transients due to parasitic circuit elements such as bond wire and copper trace inductances as well as lead frame capacitance a good quality low equivalent series resistance ESR ceramic capacitor of value between 220 pF
4. mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free ROHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free ROHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 8 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature There may be additional marking which relates to the logo the lot trace code information or the environmental category on the device Multiple Device Markings will be inside parentheses Only one Device Marking contained in parentheses and separated by a will appear on a device If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device 6 ead Ball Finish Orderable Devices may have multiple material finish o
5. 20m 50m100m200m 500m 1 2 5 10 20 Output Power W AVCC PVCC 12 V Load 6 Q 47 UH 20 Hz 1 kHz 6 7 kHz Figure 3 Total Harmonic Distortion Noise vs Output Power 1SPW BTL 10 THD N fo 2 0 01 10m 20m 50m100m200m 500m 1 2 5 10 20 Output Power W AVCC PVCC 13 V Load 8 Q 66 UH 20 Hz 1 kHz 6 7 kHz Figure 4 Total Harmonic Distortion Noise vs Output Power 1SPW BTL 20 18 16 14 12 10 Power 10 THD N W O N A DD 4 5 6 7 8 9 10 11 12 13 14 15 Supply Voltage V AVCC PVCC 4 5 V to 14 4 V Load 6 Q 47 uH AGL PLIM disable LIMRATE GND LIMTHRES GVDD Figure 5 Output Power vs Supply Voltage 1SPW BTL Power 10 THD N W 4 5 6 7 8 9 10 11 12 13 14 15 Supply Voltage V AVCC PVCC 4 5 V to 14 4 V Load 8 Q 66 uH AGL PLIM disable LIMRATE GND LIMTHRES GVDD Figure 6 Output Power vs Supply Voltage 1SPW BTL 8 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 1 TEXAS INSTRUMENTS www ti com Typical Characteristics continued TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 All Measurements taken at 20dB closed loop gain 1 kHz audio T 25 C unless otherwise noted Measurements were made with AES17 filter
6. Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 1 TEXAS INSTRUMENTS TPA3140D2 www ti com SLOS882A JANUARY 2015 REVISED APRIL 2015 Typical Applications continued 11 2 2 Detailed Design Procedure A rising edge transition on SD input allows the device to start switching It is recommended to ramp the PVCC voltage to its desired value before releasing SD for minimum audible artefacts The device is non inverting the audio signal from input to output The GVDD pin is not recommended to be used as a voltage source for external circuitry 11 2 2 1 Ferrite Bead Filter Considerations Using the Advanced Emissions Suppression Technology in the TPA3140D2 amplifier it is possible to design a high efficiency Class D audio amplifier while minimizing interference to surrounding circuits It is also possible to accomplish this with only a low cost ferrite bead filter In this case it is necessary to carefully select the ferrite bead used in the filter One important aspect of the ferrite bead selection is the type of material used in the ferrite bead Not all ferrite material is alike so it is important to select a material that is effective in the 10 to 100 MHz range which is key to the operation of the Class D amplifier Many of the specifications regulating consumer electronics have emissions limits as low as 30 MHz It is important to use the ferrite bead filter to block radiation in the 30 MHz and a
7. specification JESD22 C101 250 1 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process 2 JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links TPA3140D2 TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 8 3 Recommended Operating Conditions over operating free air temperature range unless otherwise noted l TEXAS INSTRUMENTS www ti com PARAMETER TEST CONDITIONS MIN MAX UNIT Vec Supply voltage PVCC AVCC 4 5 14 4 V Vin High level input voltage SD 1SPW 2 AVCC V Vit Low level input voltage SD 1SPW 0 8 V VoL Low level output voltage FAULT Reutt up 100k PVCC 14 4V 0 8 V lin High level input current SD 1SPW V 2V AVCC 12 V 50 yA lit Low level input current SD 1SPW V 0 8 V AVCC 12 V 5 yA Ta Operating free air temperature 40 85 C Tj Operating junction temperature 40 150 C 1 The TPA3140D2 incorporates an exposed thermal pad on the underside of the chip This acts as a heatsink and it must be connected to a thermally dissipating plane for proper power dissipation Failure to do so may result in the device going into thermal protection shutdown See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad 8 4 The
8. 5 REVISED APRIL 2015 www ti com Typical Applications continued 11 2 2 7 Differential Inputs The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel To use the TPA3140D2 with a differential source connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input To use the TPA3140D2 with a single ended source ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply the audio source to either input In a single ended input application the unused input should be ac grounded at the audio source instead of at the device input for best noise performance For good transient performance the impedance seen at each of the two differential inputs should be the same The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible This is to allow the input dc blocking capacitors to become completely charged during the 14 ms power up time If the input capacitors are not allowed to completely charge there will be some additional sensitivity to component matching which can result in pop if the input components are not well matched 11 2 2 8 Using Low ESR Capacitors Low ESR capacitors are recommended throughout this application section A real as opposed to ideal capacitor can be modeled simply as a resistor in series with an ideal capacitor The
9. 8 V 2 5 us GVDD Gate drive supply levpp 2MA 6 4 6 9 7 4 V tocpet DC detect time a 3 1V and Vainn 2 9V or Vainn 2 9V and Vann 950 ms 6 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 1 TEXAS INSTRUMENTS www ti com Electrical Characteristics continued over operating free air temperature range unless otherwise noted TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC CHARACTERISTICS T 25 C AVcc PVcc 12 V R 6 Q using the TPA3140D2 EVM which is available at ti com unless otherwise noted PSRR Power supply ripple rejection 200 mVpp ripple at 1 kHz 65 dB Gain 20 dB Inputs ac coupled to GND Po Continuous output power THD N 10 f 1 kHz 10 WwW Po Continuous output power THD N 10 f 1 kHz PVcc 13V R 80 10 WwW Po Continuous output power PBTL mono THD N 10 f 1 kHz PVcc 13V R 4 0 20 WwW lo Maximum output current f 1kHz R_ 30 3 1 A THD N Total harmonic distortion noise f 1 kHz Po 5 W half power ane Vh Output integrated noise 20 Hz to 22 kHz A weighted filter Gain 20 dB Spread 65 uV Spectrum off 80 JBV Crosstalk Vo 1 Vrms Gain 20 dB f 1 kHz 75 dB SNR Signal to noise ratio Maximum output at THD N lt 1 f 1 kHz 102 dB Gain 20 dB A weighted Spread Spec
10. Automatic Recovery Feature The TPA3140D2 has protection from overcurrent conditions caused by a short circuit on the output stage The short circuit protection fault is reported on the FAULT pin as a low state The amplifier outputs are switched to a Hi Z state when the short circuit protection latch is engaged The latch can be cleared by cycling the SD pin through the low state If automatic recovery from the short circuit protection latch is desired connect the FAULT pin directly to the SD pin This allows the FAULT pin function to automatically drive the SD pin low which clears the short circuit protection latch 10 3 13 Thermal Protection Thermal protection on the TPA3140D2 prevents damage to the device when the internal die temperature exceeds 150 C There is a 15 C tolerance on this trip point from device to device Once the die temperature exceeds the thermal trip point the device enters into the shutdown state and the outputs are disabled This is a latched fault Thermal protection faults are reported on the FAULT pin If automatic recovery from the thermal protection latch is desired connect the FAULT pin directly to the SD pin This allows the FAULT pin function to automatically drive the SD pin low which clears the thermal protection latch 18 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 1 TEXAS INSTRUMENTS TPA3140D2 www ti com SLOS882A JANUA
11. FREQUENCY LIMIT PEAKS Q PEAK MARGIN J en TOWER MHz dBuV m dBuV m dBuV m dB DEGREES cm MHz dBuV m dBuV m dBuV m dB DEGREES cm 166 246 40 457 21 781 21 975 18 482 44 9 100 56 841 40 457 26 213 27 058 13 399 54 100 237 372 47 457 29 330 29 186 18 271 326 9 100 241 9 47 457 19 429 20 430 27 027 01 100 11 2 3 2 EN55022 Conducted Emissions Results TV 40 inch from the major TV manufacturer TPA3140D2 EVM PVCC 12 V 8 O speakers Spread Spectrum enabled Po 1 25 W Quasi Peak Limit 70 Average Limit gt Peak Readings Amplitude dBuV Frequency MHz CISPR Class B 0 150 30MHz Idle Mode SSO Triangular BD 1 25 Watt Figure 32 Conducted Emission Line Quasi Peak Limit 70 Average Limit gt Peak Readings Amplitude dBuV Frequency MHz CISPR Class B 0 150 30MHz Idle Mode SSO Triangular BD 1 25 Watt Figure 33 Conducted Emission Neutral Table 8 Conducted Emission Line Table 9 Conducted Emission Neutral aes nue aie AERbINGe AEN ENEE DARAN R ian ds nuit aes RARES AEN ENES eran dBuv dBpV dBpV dB dBpV dB dBuv dBpV dBpV dB dBpV dB 0 156 65 83 55 83 33 774 22 056 45 956 19 873 0 158 65 785 55 785
12. NTS TPA3140D2 www ti com SLOS882A JANUARY 2015 REVISED APRIL 2015 11 Application and Implementation 11 1 Application Information The TPA3140D2 is designed for use in inductor free applications with limited distance wire length between amplifier and speakers like in TV sets sound docks and Bluetooth speakers The TPA3140D2 can either be configured in stereo or mono mode depending on output power conditions Depending on output power requirements and necessity for speaker load protection the built in AGL or PLIMIT circuit can be used to control system power see functional description of these features 11 2 Typical Applications l PVCC inF 100nF 100uF V GND FB 10k SHUTDOWN ANA SDi o 28 PYCC FAULT 2 27 PVCC Saon 1nF 1uF n IN_LEFTO H LINP g 26 BSPL S LINN 25 QUTPL GND Lono IHF LIMRATE 5 24 LOND NND nF SSCTRL 7 22 LIMTHRES 5 TPA3140D2 91 BSNR GND 9 2o OUTNR 2200F Fg an 10 19 FOND NGND alle u ann i 4g QUTPR Ma BSPR IN_RIGHT 12 17 220nF 1pF 1SPW 1 16 Pvec On GND AVCC 44 15 Pvc GND TPF K J 1nF GND 8 10R I 7 PVCC nF 100nF 100yuF enD Figure 25 Stereo Class D Amplifier with BTL Output and Single Ended Inputs with Spread Spectrum M
13. ODE TIME TFB ATTACK TIME RELEASE TIME GVDD FAST 40us 200ms 400ms 2 3 GVDD MEDIUM 80us 400ms 800ms 1 3 GVDD SLOW 160us 800ms 1600ms GND PLIMIT DISABLED DISABLED DISABLED LIMRATE accepts a 4 level input signal to setup operation When LIMRATE is connected to GND the voltage limiter function is changed to a hard clip action to control the maximum output voltage 10 3 4 SPEAKERGUARD Automatic Gain Limit AGL The TPA3140D2 has a built in SpeakerGuard AGL to limit excessive output voltage to a non clipping output signal When a an excessive level input signal is sent to TPA3140D2 the SpeakerGuard AGL will automatically reduce the amplifier gain to maintain maximum unclipped output signal to preserve high audio quality and to protect the attached speaker from excessive power The AGL works with a fast attack speed and a slower release speed to achieve maximum protection and a minimum number of audible artifacts input signal attackfevel release level output signal Figure 17 AGL Attack and Release Thresholds When the input level multiplied by the TPA3140D2 closed loop gain exceeds the limiter threshold set by the LIMTHRES pin voltage the TPA3140D2 closed loop gain is reduced in a single or by multiple 0 5dB steps until the output signal voltage gets below the level set by the LIMTHRES pin voltage or if a 12 0dB gain reduction limit is reached When the output voltage gets below the release threshold the T
14. PA3140D2 closed loop gain is increased by a single or by multiple 0 5dB steps until the release threshold is reached or the closed loop gain is at its nominal closed loop gain level The AGL gain adjustment is applied with a ramp speed selectable by the LIMRATE pin setting 14 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 TEXAS INSTRUMENTS TPA3140D2 www ti com SLOS882A JANUARY 2015 REVISED APRIL 2015 AN N NAAN AANAANANN N N N I NN ANAA AR AA V fy I TG TG GAGA GAGA TAG AGG TA GA AY AAA A A A A A A A A A A A A A A A input signal UU UAE EEE AAT Ng i W I VVVVVVVVV VV thermal warning 7 attack time AATE gain A i fi Ai h A A AAA VAAN AANANAAAAAR AA AVAL A ATTA ALALLE ENN release level IAA BWP Va VE VE VE AP AY attack level i A WA ATATATATATAT SuEDUESIENAt WAY VV V V Y V VV VA AEE Uf W y Figure 18 AGL Attack and Release Slopes 10 3 5 Thermal Foldback TFB The TPA3140D2 Thermal Foldback TFB is designed to protect the TPA3140D2 from excessive die temperature in case of the device being operated beyond the recommended temperature or power limit or with a weaker thermal system than recommended The TFB works by reducing the on die power dissipation by reducing the TPA3140D2 closed loop gain in step
15. R OUTNR BSPR OUTPR GND Copyright 2015 Texas Instruments Incorporated I TEXAS INSTRUMENTS TPA3140D2 www ti com SLOS882A JANUARY 2015 REVISED APRIL 2015 Feature Description continued ISD C FAULT C LINP C LINN C LIMRATE GAIN C_ SSCTRL C LIMTHRES GVDD AGND C RINN CL RINP 1sPw AVCC Figure 16 GAIN Pin Voltage Programming by GVDD Resistor Divider The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside the amplifier This causes the input impedance Z to be dependent on the gain setting The actual gain settings are controlled by ratios of resistors so the gain variation from part to part is small However the input impedance from part to part at the same gain may shift by 20 due to shifts in the actual resistance of the input resistors The selected input gain is latched at device start up and cannot be changed when SD is high For design purposes the input network discussed in the next section should be designed assuming an input impedance of 7 2 KQ which is the absolute minimum input impedance of the TPA3140D2 At the lower gain settings the input impedance could increase as high as 72 KQ Table 1 Gain Setting AMPLIFIER GAIN dB INPUT IMPEDANCE KQ GAIN PIN VOLTAGE TYP TYP 0 V GND 20 60 2 3 V 1 3 GVDD 26 30 4 6 V 2 3 GVDD 32 15 6 9 V GVDD 36 9 10 3 2 SD O
16. RY 2015 REVISED APRIL 2015 10 4 Device Functional Modes The TPA3140D2 has the option of running in either BD modulation or 1SPW modulation this is set by the 1SPW pin 1SPW GND BD modulation This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load with short speaker wires Each output is switching from O volts to the supply voltage The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the speaker The duty cycle of OUTPx is greater than 50 and OUTN x is less than 50 for positive output voltages The duty cycle of OUTPx is less than 50 and OUTN lt x is greater than 50 for negative output voltages The voltage across the load sits at OV throughout most of the switching period reducing the switching current which reduces any I R losses in the load OUTP l l l OUTN No Output OUTP OUTN wv TT Orn Rrq e eo Speaker l l l l Current OUTN U A o do Positive Output l PVCC OUTP OUTN OV I I l l Speaker a J SLT TOO Current l l l l Negative Output OUTN i 1 OUTP OUTN ov PVCC l Speaker OA SSS SSeS q 2 4 Current eS ee Figure 23 BD Mode Modulation Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 ww
17. S All linear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusions Mold flash and protrusion shall not exceed 0 15 per side This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMA002 for information regarding recommended board layout This document is available at www ti com lt http www ti com gt See the additional figure in the Product Data Sheet for details regarding the exposed thermal pad features and dimensions Falls within JEDEC MO 153 PowerPAD is a trademark of Texas Instruments 3 TEXAS INSTRUMENTS www ti com THERMAL PAD MECHANICAL DATA PWP R PDSO G28 PowerPAD SMALL PLASTIC OUTLINE THERMAL INFORMATION This PowerPAD package incorporates an exposed thermal pad that is designed to be attached to a printed circuit board PCB The thermal pad must be soldered directly to the PCB After soldering the PCB can be used as a heatsink In addition through the use of thermal vias the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device or alternatively can be attached to a special heatsink structure designed into the PCB This design optimizes the heat transfer from the integrated circuit IC For additional information on the PowerPAD package a
18. Support amp Community 4p Tools amp Software Technical Product Sample amp Buy Documents s Folder ee 1 TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 TPA3140D2 10 W Inductor Free Stereo BTL Class D Audio Amplifier with Ultra Low EMI and AGL 1 Features 3 Description e 2x10 W ch into 6 O Loads at 10 THD N from a The TPA3140D2 is an efficient Class D audio power 12 V Supply amplifier for driving bridged tied stereo speakers at 2x10 W ch into 8 Q Loads at 10 THD N from a 13 V Supply Up to 90 Efficient Class D Operation 8 Q Eliminates Need for Heat Sinks lt 0 05 THD N at 1 W 4 O 1 kHz lt 65 uV A wgt Output Noise Wide Supply Voltage Range Allows Operation from 4 5 V to 14 4 V Inductor Free Operation Enhanced EMI Performance with Spread Spectrum and 1SPW Operation SpeakerGuard Speaker Protection Includes Automatic Gain Limit Adjustable Power Limiter and DC Protection Robust Pin to Pin Pin to Ground and Pin to Power Short Circuit Protection and Thermal Protection Four Selectable Fixed Gain Settings Single Ended or Differential Analog Inputs Click and Pop Free Startup Applications Televisions BT Speakers Wireless Speakers Mini Speakers USB Speakers Consumer Audio Equipment Simplified Schematic Audio EE r Source And Control 4 Level Gain Select GAIN Spread Spectrum Mode Select SSCTRL AGL Speed Select Voltage Limiter LIMRATE AGL L
19. a fixed maximum value This limit can be thought of as a virtual voltage rail which is lower than the PVCC supply This virtual rail is 4 times the voltage at the LIMTHRES pin This output voltage can be used to calculate the maximum output voltage unclipped using AGL and clipped using PLIMIT and power for a given LIMTHRES voltage and speaker impedance Gerad Poy ER forunclipped power se 1 Where Rg is the total series resistance including Rpgion and any resistance in the output filter Ru is the load resistance Vp is the peak amplitude of the output possible within the supply rail Vp 4 x LIMTHRES voltage if Vp lt Pycc Pour Maximum unclipped output power 10 THD using PLIMIT 1 25 x PMAX unclipped Increasing the LIMTHRES voltage from a given value increases the maximum output voltage swing until it equals PVCC Adjusting LIMTHRES to a higher value will disable both the AGL and PLIMIT function and will offer highest available output power however it is always advised to use the LIMTHRES function if PVCC is higher than the nominal value to prevent shutdown due to over current protection or to reduce frequency of thermal foldback events To disable the AGL or PLIMIT function the LIMTHRES pin is simply connected to GVDD ISD FAULT LINP LINN C LIMRATE CL GAIN C_ SSCTRL LIMTHRES GVDD AGND C RINN C RINP CE 1sPw avec k Figure 20 LIMHTRES Pin Voltage Programming by GVDD Resistor Divider
20. ample 100uF 100nF m 1 inF FB 2 0 22uF inF Eey z H 5 inF 6 0 22uF FB 7 8 0 22uF FB 9 iuF a0 inF Z 11 0 22uF B fn a 13 inF __ 14 T FB pF H 100nF ees ee EE EE g 100F I Top Layer Ground and Thermal Pad via to Bottom Ground Plane Pad to Top Layer Ground Pour Top Layer Signal Traces Figure 34 BTL Layout Example 30 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 www ti com SLOS882A JANUARY 2015 REVISED APRIL 2015 14 Device and Documentation Support 14 1 Device Support 14 1 1 Third Party Products Disclaimer TI S PUBLICATION OF INFORMATION REGARDING THIRD PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE 14 2 Documentation Support 14 2 1 Related Documentation TPA3140D2EVM User s Guide SLOU405 PowerPAD Thermally Enhanced Package Application Report SLMA002 14 3 Community Resources The following links connect to TI community resources Linked contents are provided AS S by the respective contributors They do not constitute TI specifications and do not necessarily reflect TI s views see TI s Terms of Use TI E2E Online Community TI s Engineer to Engineer E2E Community Created to
21. and 1000 pF works well This capacitor should be placed as close to the device PVCC pins and system ground either GND pins or thermal pad as possible For mid frequency noise due to filter resonances or PWM switching transients as well as digital hash on the line another good quality capacitor typically 0 1 uF to 1 uF placed as close as possible to the device PVCC leads works best For filtering lower frequency noise signals a larger aluminum electrolytic capacitor of 220 uF or greater placed near the audio power amplifier is recommended The 220 uF capacitor also serves as a local storage capacitor for supplying current during large signal transients on the amplifier outputs The PVCC pins provide the power to the output transistors so a 220 uF or larger capacitor should be placed on each PVCC pin A 10 uF capacitor on the AVCC pin is adequate Also a small decoupling resistor between AVCC and PVCC can be used to keep high frequency class D noise from entering the linear input amplifiers 28 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 www ti com SLOS882A JANUARY 2015 REVISED APRIL 2015 13 Layout 13 1 Layout Guidelines The TPA3140D2 can be used with a small inexpensive ferrite bead output filter for most applications However since the Class D switching edges are fast it is necessary to take care when planning the layout of the printed c
22. apacitance size 0603 or 0805 for the bootstrap supply These capacitors ensure sufficient energy storage even during clipped low frequency audio signals to keep the high side power stage FET LDMOS fully turned on during the remaining part of its ON cycle Special attention should be paid to the power stage power supply this includes component selection PCB placement and routing For optimal electrical performance EMI compliance and system reliability it is important that each PVCC pin is decoupled with ceramic capacitors placed as close as possible to each supply pin It is recommended to follow the PCB layout of the TPA3140D2 reference design For additional information on recommended power supply and required components see the application diagrams in this data sheet The PVCC power supply should have low output impedance and low noise The power supply ramp and SD release sequence is not critical for device reliability as facilitated by the internal power on reset circuit but it is recommended to release SD after the power supply is settled for minimum turn on audible artifacts Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links TPA3140D2 TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 10 2 Functional Block Diagram GVDD I TEXAS INSTRUMENTS www ti com
23. ative high side FET OUTNL 23 O Class D H bridge negative output for left channel GND 24 P Power ground for the H bridges OUTPL 25 O Class D H bridge positive output for left channel BSPL 26 Bootstrap I O for left channel positive high side FET PVCC 27 P Power supply for left channel H bridge Right channel and left channel power supply inputs are connected internally PVCC 28 P Power supply for left channel H bridge Right channel and left channel power supply inputs are connected internally Thermal Pad P Connect to GND for best thermal and electrical performance 1 I Input O Output P Power 4 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 www ti com SLOS882A JANUARY 2015 REVISED APRIL 2015 8 Specifications 8 1 Absolute Maximum Ratings over operating free air temperature range unless otherwise noted MIN MAX UNIT Supply voltage AVCC to GND PVCC to GND 0 3 16 V GVDD to GND V GND to GND 0 3 0 3 V Input current To any pin except supply pins 10 mA Voltage SD FAULT 1SPW to GND 0 3 AVGC 0 3 V 10 V ms Voltage GAIN LIMRATE LIMTHRES SSCTRL 0 3 GVDD 0 3 V 100 V ms Voltage RINN RINP LINN LINP 0 3 6 3 V Continuous total power dissipation See the Thermal Information Table Operating free air temperature range Ta 40 85 C Temperat
24. bove range from appearing on the speaker wires and the power supply lines which are good antennas for these signals The impedance of the ferrite bead can be used along with a small capacitor with a value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level For best performance the resonant frequency of the ferrite bead capacitor filter should be less than 10 MHz Also it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected for the amplifier Some ferrite bead manufacturers specify the bead impedance at a variety of current levels In this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier will see If these specifications are not available it is also possible to estimate the bead s current handling capability by measuring the resonant frequency of the filter output at low power and at maximum power A change of resonant frequency of less than fifty percent under this condition is desirable Examples of ferrite beads which have been tested and work well with the TPA3140D2 include NFZ2MSM series from Murata A high quality ceramic capacitor is also needed for the ferrite bead filter A low ESR capacitor with good temperature and voltage characteristics will work best Additional EMC improvements may be obtained by adding snubber networks from each of the class D outputs to ground Sugg
25. c at the same polarity This feature protects the speaker from large DC currents or AC currents less than 2 Hz To avoid nuisance faults due to the DC detect circuit hold the SD pin low at power up until the signals at the inputs are stable Also take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults The minimum differential input voltages required to trigger the DC detect are show in Table 5 The inputs must remain at or above the voltage listed in the table for more than 950 msec to trigger the DC detect Table 5 DC Detect Threshold PVCC 12V AV dB Vin mV differential Vout V differential 20 260 2 6 26 130 2 6 32 65 2 6 36 40 2 6 10 3 11 PBTL Select The TPA3140D2 offers the feature of parallel BTL operation with two outputs of each channel connected directly If the LINP and LINN input pins pin 3 and 4 are tied low the positive and negative outputs of each channel left and right are synchronized and in phase To operate in this PBTL mono mode tie LINP and LINN inputs low to GND and apply the input signal to the RINP and RINN inputs and place the speaker between the LEFT and RIGHT outputs with OUTPL connected to OUTNL and OUTPR connected to OUTNR to parallel the output half bridges for highest power efficiency For an example of the PBTL connection see the schematic in the Typical Applications section 10 3 12 Short Circuit Protection and
26. circuits which are sensitive to noise In these cases a classic second order Butterworth filter similar to those shown in the figures below can be used Some systems have little power supply decoupling from the AC line but are also subject to line conducted interference LCI regulations These include systems powered by wall warts and power bricks In these cases it LC reconstruction filters can be the lowest cost means to pass LCI tests Common mode chokes using low frequency ferrite material can also be effective at preventing line conducted interference 33 uH OUTP LENOEN o L1 a5 C2 1 uF ad 33 uH OUTN ee c3 L2 Z 1 uF Figure 27 Typical LC Output Filter Cutoff Frequency of 27 kHz Speaker Impedance 8 Q 15 uH OUTP 22 ee L1 _ C2 15 uH OUTN IYYY o L2 c3 2 2 uF Figure 28 Typical LC Output Filter Cutoff Frequency of 27 kHz Speaker Impedance 6 Q Ferrite Chip Bead Ferrite Chip Bead Figure 29 Typical Ferrite Chip Bead Filter Chip Bead Example 11 2 2 4 Input Resistance Changing the gain setting can vary the input resistance of the amplifier from its smallest value 9 KQ 20 to the largest value 60 kQ 20 As a result if a single capacitor is used in the input high pass filter the 3 dB or cutoff frequency may change when changing gain steps 24 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Fol
27. der Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 www ti com SLOS882A JANUARY 2015 REVISED APRIL 2015 Typical Applications continued a ae l Ci l Input i IN Zi Signal g l l l The 3 dB frequency can be calculated using Equation 2 Use the Z values given in Table 1 _ 1 2n Z C 2 11 2 2 5 Input Capacitor C In the typical application an input capacitor C is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation In this case C and the input impedance of the amplifier Z form a high pass filter with the corner frequency determined in Equation 3 3 dB fe 3 The value of C is important as it directly affects the bass low frequency performance of the circuit Consider the example where Z is 60 kQ and the specification calls for a flat bass response down to 20 Hz Equation 3 is reconfigured as Equation 4 1 C lO 2nZ f 4 In this example C is 0 13 uF so one would likely choose a value of 0 15 uF as this value is commonly used If the gain is known and is constant use Z from Table 1 to calculate C A further consideration for this capacitor is the leakage path from the input source through the input network Ci and the feedback network to the load This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom especially in high gain applications For this reason a low leakage tanta
28. divider from GVDD to GND to set decay speed Connect directly to GND to disconnect limiter GAIN 6 4 state Amplifier gain select Connect a resistor divider from GVDD to GND to set closed loop gain SSCTRL 7 Spread spectrum control Connect a resistor divider from GVDD to GND to set mode Connect to GND for disable spread spectrum LIMTHR 8 l Voltage limit level for AGL and power limiter Connect a resistor divider from GVDD to GND to set limit ES Connect directly to GVDD to disconnect limiter GVDD 9 o High side FET gate drive supply Nominal voltage is 7V Also should be used as supply for LIMTHRES limit function GND 10 Analog signal ground RINN 11 Negative audio input for right channel Biased at 3V RINP 12 Positive audio input for right channel Biased at 3V 1SPW 13 Modulation scheme select Low BD mode high 1SPW mode AVCC 14 P Analog supply PVCC 15 P Power supply for right channel H bridge Right channel and left channel power supply inputs are connected internally PVCC 16 P Power supply for right channel H bridge Right channel and left channel power supply inputs are connected internally BSPR 17 Bootstrap I O for right channel positive high side FET OUTPR 18 O Class D H bridge positive output for right channel GND 19 P Power ground for the H bridges OUTNR 20 O Class D H bridge negative output for right channel BSNR 21 Bootstrap I O for right channel negative high side FET BSNL 22 Bootstrap I O for left channel neg
29. e safety related applications With such components TI s goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No Tl components are authorized for use in FDA Class III or similar life critical medical equipment unless authorized officers of the parties have executed a special agreement specifically governing such use Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military aerospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of Tl components which have not been so designated is solely at the Buyer s risk and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 requirements mainly for automotive use In any case of use of non designated products TI will not be responsible for any failure to meet ISO TS16949 Products Applications Audio www ti com audio Automotive and Transportation www ti com automotive Amplifiers amplifier ti com Communications and Telecom www ti com communications Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Ap
30. esigned to accommodate the component length Dimension designed to accommodate the component thickness y Overall width of the carrier tape 4 Pitch between successive cavity centers Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O O COO 0 0 Sprocket Holes Q1 1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants All dimensions are nominal Device Package Package Pins SPQ Reel Reel AO B0 KO P1 Ww Pint TPA3140D2PWPR HTSSOP PWP 28 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 Pack Materials Page 1 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 10 Apr 2015 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TPA3140D2PWPR HTSSOP PWP 28 2000 367 0 367 0 38 0 Pack Materials Page 2 MECHANICAL DATA P WP PDSO G28 PowerPAD PLASTIC SMALL OUTLINE Seating Plane oS Seating Plane 4 Sogi i DE am NOTE
31. ested values for a simple RC series snubber network would be 10 Q in series with a 330 pF capacitor although design of the snubber network is specific to every application and must be designed taking into account the parasitic reactance of the printed circuit board as well as the audio amp Take care to evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC Also make sure the layout of the snubber network is tight and returns directly to the GND or the thermal pad beneath the chip 11 2 2 2 Efficiency LC Filter Required with the Traditional Class D Modulation Scheme The main reason that the traditional class D amplifier needs an output filter is that the switching waveform results in maximum current flow This causes more loss in the load which causes lower efficiency The ripple current is large for the traditional modulation scheme because the ripple current is proportional to voltage multiplied by the time at that voltage The differential voltage swing is 2 x Voc and the time at each voltage is half the period for the traditional modulation scheme An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle while any resistance causes power dissipation The speaker is both resistive and reactive whereas an LC filter is almost purely reactive The TPA3140D2 modulation scheme has little loss in the load without a filter because the pulses are short and t
32. foster collaboration among engineers At e2e ti com you can ask questions share knowledge explore ideas and help solve problems with fellow engineers Design Support TI s Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support 14 4 Trademarks SpeakerGuard E2E are trademarks of Texas Instruments All other trademarks are the property of their respective owners 14 5 Electrostatic Discharge Caution A These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam hid during storage or handling to prevent electrostatic damage to the MOS gates 14 6 Glossary SLYZ022 TI Glossary This glossary lists and explains terms acronyms and definitions Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 www ti com 15 Mechanical Packaging and Orderable Information The following pages include mechanical packaging and orderable information This information is the most current data available for the designated devices This data is subject to change without notice and revision of this document For browser based versions of this data sheet refer to the left hand navigation 32 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Pr
33. he change in voltage is Vcc instead of 2 x Voc As the output power increases the pulses widen making the ripple current larger Ripple current could be filtered with an LC filter for increased efficiency but for most applications the filter is not needed An LC filter with a cutoff frequency less than the class D switching frequency allows the switching current to flow through the filter instead of the load The filter has less resistance but higher impedance at the switching frequency than the speaker which results in less power dissipation therefore increasing efficiency Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 www ti com Typical Applications continued 11 2 2 3 When to Use an Output Filter for EMI Suppression The TPA3140D2 has been tested with a simple ferrite bead filter for a variety of applications including long speaker wires up to 100 cm and high power The TPA3140D2 EVM passes FCC Class B specifications under these conditions using twisted speaker wires The size and type of ferrite bead can be selected to meet application requirements Also the filter capacitor can be increased if necessary with some impact on efficiency There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter These circumstances might occur if there are nearby
34. ic Distortion Noise vs Output Power 1SPW PBTL Figure 14 Output Power vs Supply Voltage 1SPW PBTL 100 Efficiency a Oo 40 30 20 PVcc 6V 10 PVcc 13V PVcc 14 4V 0 2 5 5 7 5 10 125 15 175 20 225 25 Total Output Power W AVCC PVCC 6 V 13 V 14 4 V Load 4 Q 33 uH AGL PLIM disable LIMRATE GND LIMTHRES GVDD Figure 15 Efficiency vs Output Power 1SPW PBTL 9 Parameter Measurement Information All parameters are measured according to the conditions described in the Specifications and Typical Characteristics Most audio analyzers will not give correct readings of Class D amplifiers performance due to their sensitivity to out of band noise present at the amplifier output An AES 17 pre analyzer filter is recommended to use for Class D amplifier measurements In absence of such filter a 30kKHz low pass filter 10Q 47nF can be used to reduce the out of band noise remaining on the amplifier outputs 10 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 1 TEXAS INSTRUMENTS TPA3140D2 www ti com SLOS882A JANUARY 2015 REVISED APRIL 2015 10 Detailed Description 10 1 Overview To facilitate system design the TPA3140D2 needs only a single power supply between 4 5 V and 14 4 V for operation An internal voltage regulator provides suitable voltage leve
35. imiter Threshold LIMTHRES TPA3140D2 1SPW Modulation Scheme Select 1SPW up to 10 W 6 Q or 8 Q per channel Advanced EMI Suppression Technology with Spread Spectrum Control and 1SPW modulation scheme enables the use of inexpensive ferrite bead filters at the outputs while meeting EMC requirements for system cost reduction TPA3140D2 is not only fully protected against shorts and overload the SpeakerGuard speaker protection circuitry includes an adjustable Automatic Gain Limit AGL an adjustable power limiter and a DC detection circuit for protection of the connected speakers The AGL allows adjustment of the maximum output voltage without signal clipping for enhanced speaker protection and audio quality The DC detect and Pin to Pin Pin to Ground and Pin to Power Short Circuit protection circuit protect the speakers from output DC and pin shorts caused in production The outputs are also fully protected against shorts to GND PVCC and output to output The short circuit protection and thermal protection includes an auto recovery feature The TPA3140D2 can drive stereo speakers with as low as 4 Q impedance The high efficiency of the TPA3140D2 90 with 8 Q load eliminates the need for an external heat sink and TPA3140D2 will be able to output full power on a 2 layer PCB Device Information PACKAGE BODY SIZE NOM HTSSOP 28 9 70 mm x 4 40 mm PART NUMBER TPA3140D2 1 For all available packages
36. inverted De phase does not affect the audio signal or its polarity Spread spectrum mode and de phase is selected by the applied SSCTRL voltage Table 4 Gain Setting SSCTRL PIN VOLTAGE e HOR DE PHASE 0 V GND OFF OFF 2 3 V 1 3 GVDD OFF ON 4 6 V 2 3 GVDD SS1 MODULATION ON 6 9 V GVDD SS2 MODULATION ON Submit Documentation Feedback 17 Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 www ti com 10 3 9 GVDD Supply The GVDD Supply is used to power the gates of the output full bridge transistors It can also be used to supply the voltage divider circuits for LIMRATE LIMTHRES GAIN and SSCTRL programming voltages Add a 1 yF capacitor to ground at this pin 10 3 10 DC Detect The TPA3140D2 has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs A DC detect fault will be reported on the FAULT pin as a low state The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi Z To clear the DC Detect it is necessary to cycle the PVCC supply Cycling SD will NOT clear a DC detect fault A DC Detect Fault is issued when the output differential duty cycle of either channel exceeds 14 for example 57 43 for more than 950 mse
37. ircuit board The following suggestions will help to meet EMC requirements e Decoupling capacitors The high frequency decoupling capacitors should be placed as close to the PVCC and AVCC pins as possible Large 220 uF or greater bulk power supply decoupling capacitors should be placed near the TPA3140D2 on the PVCCL and PVCCR supplies Local high frequency bypass capacitors should be placed as close to the PVCC pins as possible These caps can be connected to the thermal pad directly for an excellent ground connection Consider adding a small good quality low ESR ceramic capacitor between 220 pF and 1000 pF and a larger mid frequency cap of value between 0 1uF and 1pF also of good quality to the PVCC connections at each end of the chip e Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to GND as small and tight as possible The size of this current loop determines its effectiveness as an antenna e Grounding The AVCC pin 14 decoupling capacitor should be connected to ground GND The PVCC decoupling capacitors should connect to GND Analog ground and power ground should be connected at the thermal pad which should be used as a central ground connection or star ground for the TPA3140D2 e Output filter The ferrite EMI filter Figure 29 should be placed as close to the output pins as possible for the best EMI performance The LC filter Figure 27 and Figure 28 should be placed close t
38. ls for the gate driver digital and low voltage analog circuitry Additionally all circuitry requiring a floating voltage supply that is the high side gate drive is accommodated by built in bootstrap circuitry with integrated boot strap diodes requiring only an external capacitor for each half bridge The audio signal path including the gate drive and output stage is designed as identical independent full bridges Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible In general the physical loop with the power supply pins decoupling capacitors and GND return path to the device pins must be kept as short as possible and with as little area as possible to minimize induction see reference board documentation for additional information For a properly functioning bootstrap circuit a small ceramic capacitor must be connected from each bootstrap pin BSXX to the power stage output pin OUTXX When the power stage output is low the bootstrap capacitor is charged through an internal diode connected between the gate drive power supply pin GVDD and the bootstrap pins When the power stage output is high the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high side gate driver In an application with PWM switching frequencies in the range from 310 kHz it is recommended to use ceramic capacitors with at least 220 nF C
39. lum or ceramic capacitor is the best choice When polarized capacitors are used the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 3 V which is likely higher than the source dc level Note that it is important to confirm the capacitor polarity in the application Additionally lead free solder can create dc offset voltages and it is important to ensure that boards are cleaned properly 11 2 2 6 BSN and BSP Capacitors The full H bridge output stages use only NMOS transistors Therefore they require bootstrap capacitors for the high side of each output to turn on correctly A 0 22 uF ceramic capacitor rated for at least 25 V must be connected from each output to its corresponding bootstrap input Specifically one 0 22 uF capacitor must be connected from OUTPx to BSPx and one 0 22 uF capacitor must be connected from OUTNx to BSNx See the application circuit diagram in Figure 25 The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high side N channel power MOSFET gate drive circuitry During each high side switching cycle the bootstrap capacitors hold the gate to source voltage high enough to keep the high side MOSFETs turned on Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 201
40. mal performance 11 2 1 2 PVCC Capacitor Recommendation The large capacitors used in conjunction with each full bridge are referred to as the PVCC Capacitors These capacitors should be selected for proper voltage margin and adequate capacitance to support the power requirements In practice with a well designed system power supply 100 uF 16 V will support most applications with 12 V power supply 25 V capacitor rating is recommended for power supply voltage higher than 12 V For The PVCC capacitors should be low ESR type because they are used in a circuit associated with high speed switching 11 2 1 3 Decoupling Capacitor Recommendations In order to design an amplifier that has robust performance passes regulatory requirements and exhibits good audio performance good quality decoupling capacitors should be used In practice X7R should be used in this application The voltage of the decoupling capacitors should be selected in accordance with good design practices Temperature ripple current and voltage overshoot must be considered This fact is particularly true in the selection of the ceramic capacitors that are placed on the power supply to each full bridge They must withstand the voltage overshoot of the PWM switching the heat generated by the amplifier during high power output and the ripple current created by high power output A minimum voltage rating of 16 V is required for use with a 12 V power supply 22 Submit Documentation
41. nd how to take advantage of its heat dissipating abilities refer to Technical Brief PowerPAD Thermally Enhanced Package Texas Instruments Literature No SLMAOO2 and Application Brief PowerPAD Made Easy Texas Instruments Literature No SLMAO04 Both documents are available at www ti com a The exposed thermal pad dimensions for this package are shown in the following illustration 6 17 5 27 Top View Exposed Thermal Pad Dimensions 4206332 33 AJ 10 14 NOTE A All linear dimensions are in millimeters AA Exposed tie strap features may not be present PowerPAD is a trademark of Texas Instruments 43 Texas INSTRUMENTS www ti com LAND PATTERN DATA PWP R PDSO G28 PowerPAD PLASTIC SMALL OUTLINE Example Board Layout Stencil Openings Via pattern and copper pad size Based on a stencil thickness may vary depending on layout constraints of 127mm 005inch Reference table below for other Increasing copper area will solder stencil thicknesses enhance thermal performance See Note D 18x1 30 26x0 65 21x00 30 28x0 25 1 55 UUU Example Solder Mask 26x0 65 Defined Pad N Example See Note C D Non Soldermask Defined Pad ler ask pening omm ss 26 4207609 19 U 10 14 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Customers should place a note on the circuit board fabrication drawing not to alter the ce
42. nditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty in Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed Tl assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using TI components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI components or services are used Information published by TI regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of significant po
43. nter solder mask defined pad D This package is designed to be soldered to a thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMA002 SLMA004 and also the Product Data Sheets E For specific thermal information via requirements and recommended board layout These documents are available at www ti com lt http www ti com gt Publication IPC 7351 is recommended for alternate designs Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release Customers should contact their board assembly site for stencil design recommendations Example stencil design based on a 50 volumetric metal load solder paste Refer to IPC 7525 for other stencil F Customers should contact their board fabrication site for solder mask tolerances between and around signal pads WB TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products also referred to herein as components are sold subject to Tl s terms and co
44. o the outputs The capacitors used in both the ferrite and LC filters should be grounded to power ground e Thermal Pad The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability The dimensions of the thermal pad and thermal land should be 6 46 mm by 2 35 mm Seven rows of solid vias three vias per row 0 3302 mm or 13 mils diameter should be equally spaced underneath the thermal land The vias should connect to a solid copper plane either on an internal layer or on the bottom layer of the PCB The vias must be solid vias not thermal relief or webbed vias See the TI Application Report SLMA002 for more information about using the TSSOP thermal pad For recommended PCB footprints see figures at the end of this data sheet For an example layout see the TPA3140D2 Evaluation Module TPA3140D2EVM User Manual Both the EVM user manual and the thermal pad application report are available on the TI Web site at http www ti com Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 www ti com 13 2 Layout Ex
45. oduct Folder Links TPA3140D2 H PACKAGE OPTION ADDENDUM I TEXAS INSTRUMENTS www ti com 10 Apr 2015 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Op Temp C Device Marking Samples a Drawing Qty 2 6 3 4 5 TPA3140D2PWP ACTIVE HTSSOP PWP 28 50 Green RoHS CU NIPDAU Level 3 260C 168 HR 40 to 85 TPA3140D2 Samples l amp no Sb Br amples TPA3140D2PWPR ACTIVE HTSSOP PWP 28 2000 Green RoHS CU NIPDAU Level 3 260C 168 HR 40 to 85 TPA3140D2 Samples E amp no Sb Br amples The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free ROHS Pb Free ROHS Exempt or Green ROHS amp no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free
46. odulation Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 www ti com Typical Applications continued PVCC inF 100nF o0pF 10k ISD PVCC Nenn 1 28 SHUTDOWN WV Faur a7 pvec_ LINP 3 26 BSPL_ 470nF LINN 25 OUTPL g e GND LIMRATE 24 LOND pene E T E WAVAVA GAIN 5 23 OUTNL 39k SSCTAL 7 22 BSNL 1nF LIMTHRES 5 TPA3140D2 24 LBSNR GNO 9 20 OUTNR GNDY GND 49 19 LOND per 1nF 1pF RINN 4 4g LOUTPR ie RINP 4 47 BSPR L 1pF 1SPW 1 46 Pvec 470nF GND PVCC 1inF 100nF 100uF Wend 1 100 kQ resistor is needed if the PVCC slew rate is more than 10 V ms Figure 26 Stereo Class D Amplifier with PBTL Output and Single Ended Input with Spread Spectrum Modulation 11 2 1 Design Requirements 11 2 1 1 PCB Material Recommendation FR 4 Glass Epoxy material with 1 oz 35 um is recommended for use with the TPA3140D2 The use of this material can provide for higher power output improved thermal performance and better EMI margin due to lower PCB trace inductance It is recommended to use several GND underneath the device thermal pad for thermal coupling to a bottom side copper GND plane for best ther
47. osstalk vs Frequency 1SPW BTL Figure 9 Efficiency vs Output Power 1SPW BTL 0 10 10 5 20 2 1 a 30 _ 0 5 x 0 S 02 5 50 lt Od z Q 0 05 8 60 F 2 70 0 02 0 01 Bo 0 005 90 0 002 100 0 001 20 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k Frequency Hz Frequency Hz AVCC PVCC 12 V Load 4 Q 33 uH AVCC PVCC 13 V Load 4 Q 33 UH 1 W 2 5 W 10 W Figure 11 Supply Ripple Rejection Ratio vs Frequency Figure 12 Total Harmonic Distortion Noise vs Frequency BTL 1SPW PBTL Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 www ti com Typical Characteristics continued All Measurements taken at 20dB closed loop gain 1 kHz audio T 25 C unless otherwise noted Measurements were made with AES17 filter using the TPA3140D2 EVM which is available at ti com 10 30 20 Hz 1kHz 27 S 24 z e 1 A x 15 Qa Oo T z 12 m 5 9 ao 6 3 0 01 0 10m 20m 50m100m200m 500m 1 2 5 10 20 4 5 6 7 8 9 10 11 12 13 14 15 Output Power W Supply Voltage V AVCC PVCC 13 V Load 4 Q 33 uH 20 Hz 1 kHz 6 7 kHz AVCC PVCC 4 5 V to 14 4 V Load 4 Q 33 uH AGL PLIM disable LIMRATE GND LIMTHRES GVDD Figure 13 Total Harmon
48. peration The TPA3140D2 employs a shutdown mode of operation designed to reduce supply current lcc to the absolute minimum level during periods of nonuse for power conservation The SD input pin should be held high see specification table for trip point during normal operation when the amplifier is in use Pulling SD low causes the outputs to mute and the amplifier to enter a low current state Never leave SD unconnected because amplifier operation would be unpredictable For the best power off pop performance place the amplifier in the shutdown mode prior to removing the power supply voltage 10 3 3 Gain Limit Control LIMTHRES and LIMRATE The TPA3140D2 has built in gain limiters with two operation modes for load and system protection Voltage limiting and temperature limiting The voltage limiting mode controls the TPA3140D2 voltage gain to limit the output signal without signal clipping and the temperature control mode limits the device power dissipation to keep the die temperature within recommended operating conditions Both voltage limiter and thermal limiter attack and release speeds time per 0 5dB gain step are controlled by the LIMRATE pin Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 www ti com Table 2 Speaker Guard AGL Settings LIMRATE AGL ATTACK AGL TFB VOLTAGE M
49. plications Processors Wireless Connectivity dataconverter ti com www dip com www ti com clocks interface ti com logic ti com microcontroller ti com www ti rfid com www ti com omap Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space Avionics and Defense Video and Imaging TI E2E Community www ti com wirelessconnectivity www ti com computers www ti com consumer apps www ti com energy www ti com industrial www ti com medical www ti com security www ti com space avionics defense www ti com video Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2015 Texas Instruments Incorporated
50. plifier with SpeakerGuard TPA3131D2 7W Filter Free Class D Stereo Amplifier In Space Saving QFN TPA3130D2 15W Filter Free Class D Stereo Amplifier with AM Avoidance TPA3110D2 15W Filter Free Class D Stereo Amplifier with SpeakerGuard 7 Pin Configuration and Functions PWP Package 28 Pin HTSSOP Top View Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 PVCC PVCC BSPL OUTPL GND OUTNL BSNL BSNR OUTNR GND OUTPR BSPR PVCC PVCC Submit Documentation Feedback 3 I TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 www ti com Pin Functions PIN i vo P DESCRIPTION NAME NUMBER Sp 1 Shutdown logic input for audio amp LOW outputs Hi Z HIGH outputs enabled TTL logic levels with compliance to AVCC Open drain output used to display short circuit or dc detect fault status Voltage compliant to AVCC FAULT 2 O Short circuit faults can be set to auto recovery by connecting FAULT pin to SD pin Otherwise both short circuit faults and dc detect faults must be reset by cycling PVCC LINP 3 Positive audio input for left channel Biased at 3V Connect to GND for PBTL mode LINN 4 Negative audio input for left channel Biased at 3V Connect to GND for PBTL mode LIMRATE 5 l Decay speed for clip free power limiter Connect a resistor
51. ptions Finish options are separated by a vertical ruled line Lead Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release Addendum Page 1 H PACKAGE OPTION ADDENDUM IA TEXAS INSTRUMENTS www ti com 10 Apr 2015 In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 2 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 10 Apr 2015 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS Mpapa Reel Diameter Dimension designed to accommodate the component width BO Dimension d
52. rmal Information PWP HTSSOP THERMAL METRIC UNIT 28 PINS Resa Junction to ambient thermal resistance 37 5 ReJc top Junction to case top thermal resistance 19 4 Reus Junction to board thermal resistance 16 6 CW WsT Junction to top characterization parameter 0 6 YJB Junction to board characterization parameter 16 4 ReJc bot Junction to case bottom thermal resistance 2 8 1 8 5 Electrical Characteristics over operating free air temperature range unless otherwise noted For more information about traditional and new thermal metrics see the IC Package Thermal Metrics application report SPRA953 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS T4 25 C AVcc PVec 12 V R 6 Q using the TPA3140D2 EVM which is available at ti com unless otherwise noted Vos Class D output offset voltage measured V 0 V Gain 36 dB 1 5 15 mV differentially loc Quiescent supply current SD 2 V no load 10uF 680nF Output Filter 35 40 mA Icc sp Quiescent supply current in shutdown mode SD 0 8 V no load 40 60 pA fDS on Drain source on state resistance l 500 mA Ty 25 C High Side 240 mQ Bard Wien eae pow Side a G Gain GAIN 0 V GND 19 20 21 dB GAIN 2 3 V 1 3 GVDD 25 26 27 GAIN 4 6 V 2 3 GVDD 31 32 33 GAIN 6 9 V GVDD 35 36 37 ton Turn on time SD 2V 14 ms torr Turn off time SD 0
53. rtions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Buyer acknowledges and agrees that it is solely responsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety critical applications In some cases TI components may be promoted specifically to facilitat
54. s of 0 5dB if the temperature trig point is exceeded Once the die temperature drops below the TFB trig point the TPA3140D2 closed loop gain is increased by a single or by multiple 0 5dB steps until the TFB trig point or a maximum of 12dB attenuation is reached and the closed loop gain will be decreased again or the closed loop gain is at its nominal closed loop gain level The TFB gain adjustment is applied with a ramp speed selectable by the LIMRATE pin setting as shown in Table 2 10 3 6 PLIMIT The PLIMIT operation will if selected limit the output voltage level to a voltage level below the supply rail In this case the amplifier operates as if it was powered by a lower supply voltage and thereby limiting the output power by voltage clipping PLIMIT threshold is set by the LIMTHRES pin voltage LIMTHRESH 6 97 Y Po 102 LIMTHRESH F 2 42V Po 8W LIMTHRIESH 1 94 V Po 6 W LIMTHRESH 1 54 V Po 4 W TPA3140D2 PLimit Function PYoc 14 4 V Rload 8 ohms Figure 19 PLIMIT Circuit Operation Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 www ti com 10 3 7 LIMTHRES The AGL and PLIMIT voltage threshold is set by the applied LIMTHRES voltage The LIMTHRES voltage is set by a voltage divider from GVDD to GND The limiting is done by limiting the amplifier output voltage to
55. see the orderable addendum at the end of the datasheet Ferrite C EFN Filter Ferrite C E T Filter Power Supply 4 5V 14 4V 110VAC gt 240VAC An IMPORTANT NOTICE at the end of this data sheet addresses availability warranty changes use in safety critical applications intellectual property matters and other important disclaimers PRODUCTION DATA TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 I TEXAS INSTRUMENTS www ti com Table of Contents 1 10 See ee eee 1 10 3 Feature Description 2 Applications 2c000ceiedean cnn cweevencien 1 10 4 Device Functional Modes 3 Description 0 0 ccccecccccscesceseeceteseseeteseseseeeeseees 1 11 Application and Implementation 4 Simplified Schematic 0 ccccccccceeseseeeeee 1 11 1 Application Information 5 Revision History ccccssceseeeeeeeeeeeeeee 2 11 2 Typical Applications 6 Device Comparison Table 1111055511111 1 3 12 Power Supply Recommendations 7 Pin Configuration and Functions 3 12 1 Powsr SUppIy DecoupliNg CS sisisastisssso B Specifications ccccccccccccesssssssssssssssessssssssssevereee 5 13 Layout sas eesescnnsneceenanriecesonasecnsousneneesanencee 8 1 Absolute Maximum Ratings 0 cece 5 19 1 Layour GUdENNES rescuers aia ie a R 8 2 ESD Ratings scccccsscccsssssssessssssessvessssesssssssssse
56. seseenees 5 13 2 Layout MUNIN specter yras nsitanrt sannindan 8 3 Recommended Operating Conditions 6 14 Device and Documentation Support a1 8 4 Thermal Information 0 cccccceceeeeseeeetseneeeeseeees 14 1 Device Support Bee ee E R en 8 5 Electrical Characteristics 14 2 Po umentatign Support cs Bi 8 6 Switching Characteristics 14 3 Community Resources nA 8 7 Typical Characteristics cecceesecseesseesteeeteeeeees 14 4 Trademarks ssessceseteees ses 31 Parameter Measurement Information 10 14 51 Elentrostatie Discharge wauti n ae 10 Detailed Description 0 ce eeeeeeereetees 1i 148 GOSSA armanata naaien A VOM OVENIEW anrc air a E ETE 11 15 Mechanical Packaging and Orderable lnformatiOn siiiiiiiecsisissrirsicriireerriesiieriniiriissests 32 10 2 Functional Block Diagram uu eee 12 5 Revision History Changes from Original January 2015 to Revision A Page e Changed from Product Preview to Production Data cecceecceesceeseeteeeeeeeeeeeeteaeeeaeeeseeseaeeeaeeeseeseaeseaeeseessaeseaeesseeeeaeseeesnaeeeas 1 2 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 1 TEXAS INSTRUMENTS www ti com 6 Device Comparison Table TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 DEVICE NAME DESCRIPTION TPA3113D2 6 W Stereo Class D Audio Power Am
57. trum off OTE Thermal trip point 150 C Thermal hysteresis 15 C TFB Thermal foldback trip point 125 C 8 6 Switching Characteristics over operating free air temperature range unless otherwise noted PARAMETER MIN NOM MAX UNIT fosc Oscillator frequency 250 310 350 kHz fosc ss Oscillator frequency Spread Spectrum ON 255 315 355 kHz Copyright 2015 Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links TPA3140D2 TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 8 7 Typical Characteristics I TEXAS INSTRUMENTS www ti com All Measurements taken at 20dB closed loop gain 1 kHz audio T 25 C unless otherwise noted Measurements were made with AES17 filter using the TPA3140D2 EVM which is available at ti com 10 iW 5W 0 1 THD N 0 001 100 200 500 1k 2k 5k 10k 20k Frequency Hz AVCC PVCC 12 V Load 6 Q 47 UH 1 W 2 5 W 5 W 20 50 Figure 1 Total Harmonic Distortion vs Frequency 1SPW 10 iW 5W Zz 0 1 Qa r 0 01 0 001 100 200 500 1k 2k 5k 10k 20k Frequency Hz AVCC PVCC 13 V Load 8 Q 66 UH 1 W 2 5 W 5 W 20 50 Figure 2 Total Harmonic Distortion vs Frequency 1SPW BTL BTL 10 20 Hz 1 kHz _ 1 z z Q E 0 1 0 01 10m
58. ure range 65 150 C Minimum load resistance RL BTL PVCC gt 12 V 4 8 Q BTL PVCC lt 12 V 3 2 PBTL PVCC gt 12 V 2 5 PBTL PVCC lt 12 V 1 8 Storage temperature range Tstg 65 150 C 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 The voltage slew rate of these pins must be restricted to no more than 10 V ms For higher slew rates use a 100 kQ resister in series with the pins 3 The voltage slew rate of these pins must be restricted to no more than 100 V ms For higher slew rates use a 100 KQ resister in series with the pins 4 The TPA3140D2 incorporates an exposed thermal pad on the underside of the chip This acts as a heatsink and it must be connected to a thermally dissipating plane for proper power dissipation Failure to do so may result in the device going into thermal protection shutdown See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad 8 2 ESD Ratings VALUE UNIT n Human body model HBM per ANSI ESDA JEDEC JS 001 1000 Vesp Electrostatic discharge ae 7 V Charged device model CDM per JEDEC
59. using the TPA3140D2 EVM which is available at ti com 28 40 100 90 24 20 80 70 20 0 60 2 3 2 2 g 50 O 16 20 2 40 w 30 Ff 12 40 20 PVcc 6V 10 PVcc 12V PVcc 14 4V 8 60 0 20 50 100 200 500 1k 2k 5k 10k 20k 0 25 5 75 10 125 15 175 20 225 25 Frequency Total Output Power W AVCC PVCC 12 V Load 6 Q 47 UH device pins AVCC PVCC 6 V 12 V 14 4 V Load 6 Q 47 uH AGL PLIM disable LIMRATE GND LIMTHRES GVDD Figure 7 Gain Phase vs Frequency BTL Figure 8 Efficiency vs Output Power 1SPW BTL 100 0 90 10 80 20 30 T S T 40 60 2 50 s x 50 w 60 jr wn 40 3 70 8 30 80 90 20 PVcce 6V 100 10 PVcc 13V Chi PVcc 14 4V Fg Ch2 0 120 0 25 5 75 10 125 15 175 20 225 25 20 50 100 200 500 1k 2k 5k 10k 20k Output Power W Frequency Hz AVCC PVCC 6 V 13 V 14 4 V Load 8 Q 66 uH AGL AVCC PVCC 12 V 1 W Load 6 Q 47 uH PLIM disable LIMRATE GND LIMTHRES GVDD Figure 10 Cr
60. voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor 26 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 I TEXAS INSTRUMENTS www ti com Typical Applications continued 11 2 3 Application Performance Curves 11 2 3 1 EN55013 Radiated Emissions Results TPA3140D2 SLOS882A JANUARY 2015 REVISED APRIL 2015 TPA3140D2 EVM PVCC 12 V 8 Q load up to 1 meter speaker cable Spread Spectrum enabled Po 1 25 W 60 Limit dBu V m 3 8 Limit v Peaks 0 03 0 1 1 Frequency GHz CISPR Class B 3m 30 1000MHz Scan 7 TPA3140D2 EVM with 8R Load Different ferrite choke Murata 601FB 1nF 1 meter cable Battery supply SS TRI BD 1 25W Spkr Wire Config2 Figure 30 Radiated Emission Horizontal Limit dBu V m Frequency GHz CISPR Class B 3m 30 1000MHz Scan 7 TPA3140D2 EVM with 8R Load Different ferrite choke Murata 601FB 1nF 1 meter cable Battery supply SS TRI BD 1 25W Spkr Wire Config2 Figure 31 Radiated Emission Vertical Table 6 Radiated Emission Horizontal Table 7 Radiated Emission Vertical FREQUENCY LIMIT PEAKS Q PEAK MARGIN T A TOWER
61. w ti com Device Functional Modes continued 1SPW HIGH 1SPW modulation The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty in THD degradation and more attention required in the output filter selection In 1SPW mode the outputs operate at 15 modulation during idle conditions When an audio signal is applied one output will decrease and one will increase The decreasing output signal will quickly rail to GND at which point all the audio modulation takes place through the rising output The result is that only one output is switching during a majority of the audio cycle Efficiency is improved in this mode due to the reduction of switching losses The THD penalty in 1SPW mode is minimized by the high performance feedback loop The resulting audio signal at each half output has a discontinuity each time the output rails to GND This can cause ringing in the audio reconstruction filter unless care is taken in the selection of the filter components and type of filter used No Output OUTP OUTN oV OTT Deere eee Speaker l l l Current PVCC OUTP OUTN ov i i i l Speaker l Current l l l 0 l l l Negative Output OUTN I OUTP OUTN OV Speaker OA Sa ee ee Jo gt gt x2 4 Current l i l H Figure 24 1SPW Mode Modulation 20 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated Product Folder Links TPA3140D2 1 TEXAS INSTRUME

10-W Inductor Free Stereo (BTL) Class-D Audio Amplifier with

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