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NEC PD754244 Network Card User Manual

1. A 4 a U D iR oe a iQ f 4 8 8 co x D x iQ Mes i g qe Abe e n Coie t o M2 screw WD Cu b FE B et Pc 0 Pd P AN G Ea 0 IE G a aS bd EM 1 poem d _ 5 CE iO B us ce iO iN Jeff ft K Lb Ww Zz 1JJJ LLLM X Y peto yu it n 1 if i s hi y L 1 Z PII l Protrusion 4 places n m ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES A 18 0 0 709 a 0 5 19 9 5 0 10 0 020x0 748 0 374 0 004 B 11 77 0 463 b 0 25 0 010 C 0 5x19 9 5 0 020x0 748 0 374 95 3 90 209 D 0 5 0 020 d 5 3 60 209 E 0 5x19 9 5 0 020x0 748 0 374 e 1 3 90 051 F 11 77 0 463 f 3 55 60 140 G 18 0 0 709 g 90 3 90 012 H 0 5 0 020 h 1 85 0 2 0 073 0 008 l 1 58 0 062 i 3 5 0 138 J 1 2 0 047 i 2 0 0 079 K 7 64 0 301 k 3 0 0 118 L 1 2 0 047 0 25 0 010 M 1 58 0 062 m 14 0 0 551 N 1 58 0 062 n 1 4 0 2 0 055 0 008 1 2 0 047 1 4 0 2 0 055 0 008 7 64 0 301 h 1 8 1 3 h 0 071 0 051 Q 1 2 0 047 q 0 5 0 000 0 197 R 1 58 0 062 r 5 9 0 232 S 3 55 90 140 S 0 8 0 031 T C 2 0 C 0 079 t 2 4 0 094 U 12 31 0 485 2 7 0 106 V 10 17 0 400 3 9 0 154 Ww 6 8 0 268 TGK 080SDW GOE x 8 24 0 324 Y 14 8 0 583 Z 1 4 0 2 0 055
2. reset ener ntn nenne nnns 172 8 2 16 Bit Timer Event Counter Interval Times sese 173 8 3 16 Bit Timer Event Counter Square Wave Output Ranges ssesseeeenenene 174 8 4 16 Bit Timer Event Counter Configuration nennen nennen nnns 174 8 5 INTPO TIOO Pin Valid Edge and CROO Capture Trigger Valid Edge 177 8 6 16 Bit Timer Event Counter Interval Times sssssseneeeenenenen nennen ennemis 189 8 7 16 Bit Timer Event Count Square Wave Output Ranges eene 203 9 1 8 Bit Timer Event Counter Interval Times sesssssseeeeeeeeeeeeneneneenenen nennen nennen 212 9 2 8 Bit Timer Event Counter Square Wave Output Ranges seen 213 9 3 Interval Times When 8 Bit Timer Event Counters are Used as 16 Bit Timer Event Counter 214 9 4 Square Wave Output Ranges When 8 Bit Timer Event Counters are Used as 16 Bit Tim r Event Counter uet cet lel ee LI ec ee cb Le fed ut dtes 215 9 5 8 Bit Timer Event Counter Configuration sesesssssseseeeeeeeennee nennen nennen nennen 216 9 6 8 Bit Timer Event Counter 1 Interval Time ssssssseseeseeeeeeeeneeenee nene nennen nnne 226 9 7 8 Bit Timer Event Counter 2 Interval Time sssssssssseseeeeeeeeeneneneen nennen nnne nnne 227 9 8 8 Bit
3. Other than above Setting prohibited R 0 Main system clock Rw 0 Internal feedback resistor used R W Main System Clock Oscillation Control 2 0 Oscillation possible 1 Oscillation stopped Notes 1 Bit 5 is Read Only 2 When the CPU is operating on the subsystem clock MCC should be used to stop the main system clock oscillation A STOP instruction should not be used Caution Bit 3 must be set to 0 Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillator frequency 3 fxt Subsystem clock oscillator frequency 4 MCS Bit 0 of oscillation mode selection register OSMS 158 CHAPTER 7 CLOCK GENERATOR The fastest instruction of the uPD78075F and 78075FY Subseries can be executed in two clocks of the CPU clock The relationship between the CPU clock fcPu and the minimum instruction execution time is shown in Table 7 2 Table 7 2 Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock fceu Minimum Instruction Execution Time 2 fceu fx 5 0 MHz fxt 32 768 kHz fx Main system clock oscillation frequency fxr Subsystem clock oscillation frequency 2 Oscillation mode selection register OSMS This register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock or the clock outp
4. 424 18 19 X Operation Timings When Using Busy Control Option BUSYO 0 425 18 20 Busy Signal and Wait Cancel When BUSYO 0 426 18 21 Operation Timings When Using Busy amp Strobe Control Option BUSYO 0 427 18 22 Operation Timing of the Bit Slippage Detection Function Through the Busy Signal When BUSY O ST 3 aen en ALi UR cedit inia pee ou 428 18 23 Automatic Transmit Receive Interval Time ssseeneeenneem eene 429 18 24 Operation Timing with Automatic Data Transmit Receive Function Performed by Internal Clock 430 19 1 Serial Interface Channel 2 Block Diagram 435 19 2 Baud Rate Generator Block Diagram ssssssssseseeeeeeeeennee nennen nennen nnne 436 19 3 Serial Operating Mode Register 2 Format sssssssssssssseeeeeeneneeeneen nene 438 19 4 Asynchronous Serial Interface Mode Register Format seen 439 19 5 Asynchronous Serial Interface Status Register 441 19 6 Baud Rate Generator Control Register Format ccecceesseeseeeeeeeeeeeeeeeeeeeseaeeeneeseaeeseeeseaeeteaeeeaeene 442 19 7 Asynchronous Serial Interface Transmit Receive Data Format
5. 22 P22 Output Latch ARLD Serial Clock Counter SIOI write TO2 OE TCL TCL TCL TCL 37 36 35 34 j gt INTCSH fo 2 to 1 28 4 Timer Clock Select Register 3 Internal Bus 389 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 1 2 3 390 Serial I O shift register 1 SIO1 This is an 8 bit register to carry out parallel serial conversion and to carry out serial transmission reception shift operation in synchronization with the serial clock 5101 is set with an 8 bit memory manipulation instruction When the value in bit 7 CSIE1 of serial operating mode register 1 CSIM1 is 1 writing data to SIO1 starts serial operation In transmission data written to SIO1 is output to the serial output SO1 In reception data is read from the serial input SI1 to SIO1 RESET input makes SIO1 undefined Caution Do not write data to SIO1 while the automatic transmit receive function is activated Automatic data transmit receive address pointer ADTP This register stores value of the number of transmit data bytes 1 while the automatic transmit receive function is activated As data is transferred received it is automatically decremented ADTP is set with an 8 bit memory manipulation instruction The high order 3 bits must be set to 0 RESET input sets ADTP to 00H Caution Do not write da
6. seen nennen 253 12 2 Clock Output Control Circuit Block Diagram sess 254 12 3 Timer Clock Select Register 0 Format c ccesceseseeseeeseeesseeeeaeeeeeseaeeeseeceaeeesaeeeaeeseaeenaeessaeeneeeneees 255 12 4 Port Mode Register 3 Format ceo toe ro dp et e eder td ret re ruat 256 13 1 Buzzer Output Control Circuit Block Diagram sesssssseeeeeeeeeneenneenen nennen 257 13 2 Timer Clock Select Register 2 Format ssssssssesseseeeeeeeneeenee nee 259 13 3 Port Mode Register 3 Format 260 25 LIST OF FIGURES 4 8 Figure No Title Page 14 1 A D Converter Block nnne ennemi n tenete neni 263 14 2 A D Converter Mode Register Format ssssssssssseeeeeeeeeen nennen nennen rennen nens 266 14 3 A D Converter Input Select Register Format sesssssssssesseeeeeeeenen nennen nennen 267 14 4 External Interrupt Mode Register 1 Format eseeeneem eene 268 14 5 A D Gonverter Basic OperatiOri eto e E ARE MEE 270 14 6 Relationship Between Analog Input Voltage and A D Conversion 271 14 7 A D Conversion by Hardware Start sssssssssssssseeeeeeeeneeneen nennen nnne nennen nnne nnn 272 14 8 A D Conversion by Software Start
7. Assembler package C compiler package System simulator Integrated debugger Device file C library source file Device file Tool for PROM writing Embeded software PG 1500 controller Real time OS OS Host machine PC or EWS Interface board PROM writing environment In circuit emulator d ud PROM programmer Programmer adapter Product with on chip PROM Emulation probe Conversion socket Target system Remark The areas shown with dotted lines differ depending on the development environment Refer to B 3 1 Hardware 569 APPENDIX B DEVELOPMENT TOOLS B 1 Language Processing Software RA78K 0 Assembler package Program that converts program written in mnemonic into object codes that can be executed by microcontroller In addition automatic functions to generate symbol table and optimize branch instructions are also provided Used in combination with optional device file DF78054 lt Precautions when using RA78K 0 under PC environment gt This assembler package is a DOS based application However it can also run under Windows environment by using Project Manager included in the assembler package on Windows Part number uS oxxRA78KO0 Program that converts program written in C language into object codes that can be executed by microcontroller Used in combination with optional assembler pa
8. 219 External interrupt mode register 0 INTMO 185 486 External interrupt mode register 1 INTM1 ssessseenenenn emen nre 268 486 I Internal expansion RAM size switching register IXS 539 Interrupt mask flag register OH MKOH sssssessseeseseeeeeeneneenee nnne nnnennne nnne nnns enne testen enne eene nnne 484 Interrupt mask flag register OL MKOL sesssseseesesseeeeeeeeeneennen nnne nnn nnne nnne senten nennen nere 484 Interrupt mask flag register 1L MK1L sssssssesesseeeeenennennnneneennmeennen neret neret rennen 484 503 Interrupt request flag register OH 483 Interrupt request flag register OL IFOL 483 585 APPENDIX D REGISTER INDEX Interrupt request flag register 1L IF1L 483 503 Interrupt timing specify register SINT sse 298 316 351 360 370 K Key return mode register KRM siii into er i eto Per d E EE EYE EXE dE e a gud eye pete ep 151 504 M Memory expansion mode register MM 150 508 Memory size switching register IMS sessseseeneeneenenennenneen enn nennen nnne nnns 509
9. clock set by the bits 0 to 2 PCCO PCC2 of the processor clock control register PCC and bit 0 MCS of the oscillation mode selection register OSMS 431 MEMO 432 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes Operation stop mode Asynchronous serial interface UART mode e 3 wire serial I O mode 1 2 3 Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption Asynchronous serial interface UART mode In this mode one byte of data is transmitted received following the start bit and full duplex operation is possible A dedicated UART baud rate generator is incorporated allowing communication over a wide range of baud rates In addition the baud rate can be defined by scaling the input clock to the ASCK pin The MIDI standard baud rate 31 25 kbps can be used by employing the dedicated UART baud rate generator 3 wire serial I O mode MSB first LSB first switchable In this mode 8 bit data transfer is performed using three lines the serial clock SCK2 and serial data lines 512 SO2 In the 3 wire serial I O mode simultaneous transmission and reception is possible increasing the data transfer processing speed Either the MSB or LSB can be specified as the start bit for an 8 bit data serial transfer allowing connection to devic
10. eee 505 22 2 State of Ports 4 to 6 Pins in External Memory Expansion Mode 505 22 3 Values When the Memory Size Switching Register Is Reset 509 23 1 HALT Mode Operating nennt ener nnns 517 23 2 Operation After HALT Mode Release cecccesceseeeeeeeeceaeeeeeeeeaeecaaeeeaeeseeesaeeseaeeseeseaeesieeeeieeseeeeeaees 519 23 3 STOP Mode Operating Status 520 23 4 Operation After STOP Mode Release sess nnne nennen rennen nene 522 24 1 Hardware Status After Reset 525 25 1 ROM Correction Configuration isseire eii EEE 527 26 1 Differences Between uPD78P058F 78P058FY and Mask ROM Versions 537 26 2 Examples of Memory Size Switching Register Settings sssseeeeen 538 26 3 Value Set to the Internal Expansion RAM Size Switching Register 539 26 4 PROM Programming Operating Modes sese nnns 540 27 1 Operand Identifiers and Description Methods sesseeenenenneneneeeneren nennen 550 A 1 Major Differences Among uPD78054 78058F and 780058 565 B 1 OS Tor BM BG
11. 2 78 1 kHz f 2 39 1 kHz Caution fxx 2 is a clock to be supplied to the CPU and fxx 25 26 and 27 are clocks to be supplied to the peripheral hardware fxx 2N stops in the HALT mode Remarks 1 N Value 0 to 4 at bits 0 to 2 PCCO to PCC2 of processor clock control register 2 fx Main system clock frequency fx or fx 2 3 fx Main system clock oscillation frequency 4 MCS Bit 0 of oscillation mode selection register OSMS 5 Values in parentheses when operated with fx 5 0 MHz 488 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS The noise elimination circuit sets the interrupt request flag PIFO at 1 when the sampled INTPO input level is active twice in succession Figure 21 8 shows the input output timing of the noise elimination circuit Figure 21 8 Noise Elimination Circuit Input Output Timing During Rising Edge Detection a When input is less than the sampling cycle tsmp tsp pem Sampling Clock INTPO i i i l PIFO Since the level of INPO is not high at any time when it is sampled the PIFO output remains at the low level b When input is equal to or twice the sampling cycle tsmp lt 2 gt is the second time in succession that sampling has found the INTPO level to be high so the PIFO flag is set at 1 c When input is twice or more than the cycle frequency tsp Sampling Clock
12. 455 19 8 Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing 457 19 9 Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing 458 19210 Receive Error Timing i eee ee Be eei tee abe e E Vecino iol dats 459 19 11 Receive Buffer Register RXB Status and Receive Completion Interrupt Request INTSR Generation When Receiving Is Terminated ssssssseneeeeeeeneee nennen nennen 460 19 12 3 Wire Serial Mode Timing cceecceeseeeeneeeeeeeeaeeeeeeeeaeeeeaeceaeecaaeeeaeesaaeeeseeesaeesseeseaeeeaeeseaeesseetaes 466 19 13 Circuit of Switching in Transfer Bit Order enne 467 19 14 Receive Completion Interrupt Request Generation Timing When ISRM 1 468 19 15 Period that Reading Receive Buffer Register Is Prohibited seenee 469 20 1 Real time Output Port Block Diagram ssseeseseenenneeneneneennenen eene nennen nennen nnne 472 20 2 Real time Output Buffer Register Configuration sese 473 20 3 Port Mode Register 12 Format a ae er a a e aa a a 474 28 LIST OF FIGURES 7 8 Figure No Title Page 20 4 Real time Output Port Mode Register Format 474 20 5 Real time Output Port Control Register Format sssssseeeeneneeneenene nere
13. Note Under development Remark in the part number differs depending on the host machine and OS used Lu SxxxxID78K0 NS Host Machine Supply Media PC 9800 Series Windows Japanese Note 3 5 inch 2HD FD IBM PC AT and Windows Japanese Note 3 5 inch 2HC FD compatibles Windows English Nete Note Does not support WindowsNT uSxxxxID78K0 Host Machine Supply Media PC 9800 Series Windows Japanese 3 5 inch 2HD FD IBM PC AT and Windows Japanese Note 3 5 inch 2HC FD compatibles Windows English Nete HP9000 series 700 HP UX Rel 9 05 DAT DDS SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 1 4 inch CGMT NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Note Does not support WindowsNT 575 APPENDIX B DEVELOPMENT TOOLS B 4 OS for IBM PC The following OSs for the IBM PC are supported Table B 1 OS for IBM PC Version Ver 5 02 to Ver 6 3 J6 1 V8 to J6 3 VNote IBM DOS J5 02 VNote MS DOS Ver 5 0 to Ver 6 22 5 0 VMote to 6 2 VNete Note Only English mode is supported Caution Although Ver 5 0 or later have a task swap function this function cannot be used with this software B 5 Upgrading Former In circuit Emulators for 78K 0 Series to IE 78001 R A If you have a former in circuit emulator for the 78K 0 Series IE 78000 R or IE 78000 R A your in circuit emulator can be upgraded to be equivalent to the
14. __ ovy sii _Xo7foeXDsXoafosXp2Xoifxoo 1 BUSY 1 CSIIF1 CSIE1 H ERR i poseen 1 1 No Busy Detection Leer Error Interrupt Request Generation es Error Detection CSIIF1 Interrupt Request Flag CSIE1 Bit 7 of serial operation mode register 1 CSIM1 ERR Bit 4 of the auto data send and receive control register ADTC 428 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 5 Automatic transmit receive interval time When using the automatic transmit receive function the read write operations from to the internal buffer RAM are performed after transmitting receiving one byte Therefore an interval is inserted before the next transmit receive Since the read write operations from to the internal buffer RAM are performed in parallel with the CPU processing when using the automatic transmit receive function by the internal clock the interval depends on the value which is set in the automatic transmit receive interval specification register ADTI and the CPU processing at the rising edge of the eighth serial clock Whether it depends on the ADTI or not can be selected by the setting of its bit 7 ADTI7 When it is set to 0 the interval depends only on the CPU processing When it is set to 1 the interval depends on the contents of the ADTI or CPU processing whichever is greater When the automatic transmit receive function is used by an external clock it must be
15. 206 8 34 Timing of One Shot Pulse Output Operation Using External Trigger with Rising Edge Specified 207 8 35 16 Bit Timer Register Start TIMING aea ae n aioe a ra eaa ea nennen nene 208 8 36 Timings After Change of Compare Register during Timer Count Operation 208 8 37 Capture Register Data Retention Timing cccceecceeseeeeeeeeeeeeeeeeeeeeeeeeeseeeeaeeeeeeenaeeseaeeeaeeseaeeseeeeeaeess 209 8 38 Operation Timing of OVFO Flag ieii i e a nnn enne ener 210 9 1 8 Bit Timer Event Counter Block Diagram ssssssseeseeeeeeeeneneneee nene nennen nennen 217 9 2 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 1 218 9 3 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 2 218 9 4 Timer Clock Select Register 1 221 9 5 8 Bit Timer Mode Control Register Format ssessssssssseeeeeeeeneneneee nennen nennen 222 9 6 8 Bit Timer Output Control Register Format ssssssssesseeeeeeeeeeee nennen nennen neni 223 9 7 Port Mode Register 3 Format nna enn Re pi erdt Decree er ive qe at 224 9 8 Interval Timer Operation Timings 225 9 9 External Event Co
16. 5 to PM7 PM12 PM13 146 These registers are used to set port input output in 1 bit units to PM5 to PM7 PM12 and PM13 are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets registers to FFH When port pins are used as the dual function pins set the port mode register and output latch according to Table 6 5 Cautions 1 Pins POO and P07 are input only pins 2 As port 0 has a dual function as external interrupt request input when the port function output mode is specified and the output level is changed the interrupt request flag is set When the output mode is used therefore the interrupt mask flag should be set to 1 beforehand 3 specification for pins P40 to P47 is set using the memory expansion mode register MM CHAPTER 6 PORT FUNCTIONS Table 6 5 Port Mode Register and Output Latch Settings When Using Alternate Functions Alternate Functions Pin Name Name Input Output INTPO Input TIOO Input INTP1 Input P01 TIO1 Input P02 to P06 INTP2 to INTP6 Input Po7Note 1 XT1 Input P10 to P17Note 1 ANIO to ANI7 Input P30 to P32 TOO to TO2 Output P33 P34 TH TI2 Input P35 PCL Output P36 BUZ Output P40 to P47 ADO to AD7 Input Output P50 to P57 A8 to A15 Output P64 RD Output P65 WR Output P66 WAIT Input P67 ASTB Output P120 to P127 RTPO to RTP7 Output P130 P131Note 1 ANO
17. 547 CHAPTER 27 INSTRUC TION SET etre eret caeteri trier 549 27 1 Legends Used in Operation 550 27 1 1 Operand identifiers and description methods sssssseneneeeeneen 550 27 1 2 Description of operation column rre 551 27 1 3 Description of flag nennen nnnm nennen 551 27 2 Operation List erkennen rie Denier 552 27 3 Instructions Listed by Addressing Type 560 APPENDIX A DIFFERENCES AMONG 4 PD78054 78058F AND 780058 SUBSERIES 565 APPENDIX B DEVELOPMENT TOOLS 567 B 1 Language Processing Software 570 B 2 PROM Programming Tool 571 B 24 Hardware e tee e erp a ehe ett tcd 571 B 2 2 cS0ftWale5 conati vanis i t s ters AP Recs edit 571 3 Debugging Tool EE AAEE 572 Hardware niii ore pr ERE EA 572 3 2 Software Y 574 B 4 OS for IBM PG 576 B 5 Upgrading Former In circuit Emulators for 78K 0 Series to
18. eene nnne nnne nnns 468 CHAPTER 20 REAL TIME OUTPUT PORT 471 20 1 Real Time Output Port Functions 471 20 2 Real Time Output Port Configuration eeeeseeeeeseseeee esee ee nennt nennt nnn 472 20 3 Real Time Output Port Control Registers cesses enne nnne 474 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 477 21 1 Interrupt Function Types 477 20 21 2 Interrupt Sources and Configuration eese nennen nennen nnn 478 21 3 Interrupt Function Control enne nnne 482 21 4 Interrupt Servicing Operations 491 21 4 1 Non maskable interrupt acknowledge operation s 491 21 4 2 Maskable Interrupt request reception sseeeeem eene 494 21 4 8 Software interrupt request acknowledge operation 497 21 4 4 Multiple interrupt servicing oerte dicto robe pie e tec rur edu et pe cie en 497 21 4 5 Interrupt request reserve ied tte tret RR Rete MIT REPE HERIDA ri HR EE 501 21 5 Test F nctlohs INI IRIM IRE 502 21 5 1 Registers control
19. P70 S12 RxD P71 SO2 TxD P72 SCK2 ASCK P120 RTPO to P127 RTP7 Input output Connect independently via a resistor Voo or Vss P130 ANOO P131 ANO1 Input output Connect independently via a resistor to Vss RESET Input XT2 AVREFO 1 AVop AVss IC Mask ROM version Ver PROM version Leave open Connect to Vss Connect Connect to a separate power supply with the same potential as Vpp Connect to a separate ground with the same potential as Vss Connect directly to Vss CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES Figure 3 1 List of Pin Input Output Circuit 1 2 pull up enable IN OUT Schmitt Triggered Input with Hysteresis Characteristics Type 10 C AVop E pull up gt Eu pull up f P ch enable enable AVR AVbb sa data MHE Pen IN OUT IN OUT output open drain disable output disable N ch 77 AVss input of enable Type 11 C AVop Type 5 O ef pull up 2o P ch enable AVop pull up enable d AVDD 1 1 DE P data _O IN OUT 4 output disable IN OUT comparator output disable Vner Threshold voltage input enable CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES Fi
20. Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from internal buffer RAM to SIO1 Decrement pointer value Transmission operation Hardware Execution Pointer value 0 Reset ADTP ADTP Automatic data transmit receive address pointer ADTI Automatic data transmit receive interval specify register SIO1 Serial I O shift register 1 420 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6 byte transmission ARLD 1 RE 0 in repeat transmit mode internal buffer RAM operates as follows i Before transmission See Figure 18 16 a After any data has been written to serial I O shift register 1 SIO1 start trigger this data is not transferred transmit data 1 T1 is transferred from the internal buffer RAM to SIO1 When transmission of the first byte is completed automatic data transmit receive address pointer ADTP is decremented Then transmit data 2 T2 is transferred from the internal buffer RAM to SIO1 ii Upon completion of transmission of 6 bytes See Figure 18 16 b Even when sending of the 6th byte is completed the interrupt request flag CSIIF1 is not set The initial pointer value is reset in ADTP iii 7th byte transmission point See Figure 18 16 c Transmit data 1 T1 is transferred from the internal buffer RAM to SIO1 again When transmission of the first byte is completed ADTP is decremented Then tra
21. At the point when the level of INTPO is found to be high the second time in succession the PIFO flag is set at 1 489 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 6 PSW 490 Program status word PSW The program status word is a register to hold the instruction execution result and the current status for interrupt request The IE flag to set maskable interrupt enable disable and the ISP flag to control multiple interrupt processing are mapped In addition to being able to perform read and write operations in 8 bit units operations using bit operation commands and special commands El DI can be performed Also when a vectored interrupt request is received or when a BRK command is executed the contents of the PSW are automatically saved to the stack and the IE flag is set at 0 Also when a maskable interrupt request is received the contents of the received interrupt priority order specification flag are transferred to the ISP flag The contents of the PSW are also saved to the stack by the PUSH PSW command The stack contents are recovered by the RETI RETB and POP PSW commands RESET input sets PSW to 02H Figure 21 9 Program Status Word Format 7 6 5 4 3 2 1 After Reset gt Used when normal instruction is executed ISP Priority of Interrupt Currently Being Received High priority interrupt servicing low priority interrupt disable Interrupt request not acknowledged or low priority interrupt
22. sessssseseeeneeneeneennenenen nnne nnn nnns 331 16 4 5 SCKO P27 pin output manipulation essseseeeeeenenenenenenneneneennnn enne 336 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 337 17 1 Serial Interface Channel 0 Functions eeeeeeeeeeseeseseeeeee eese enne nn nnn nnne 338 17 2 Serial Interface Channel 0 Configuration seen enne 340 17 3 Serial Interface Channel 0 Control Registers esee 345 17 4 Serial Interface Channel 0 Operations esses eese seen nennen nennt nnn 353 17 4 1 Operation stop mode intende edi D Rete dete dite Lec ere edi eoe oa cond 353 17 4 2 3 wire Serial I O mode operation sssssssseeeneeneeeeennenen eene nnne nenne 354 17 4 3 2 wire serial mode operation ssssssseseneeneeneeneeenen nennen nnns 358 17 4 4 FC bus mode operation reg de nare qe p e iid e gas 363 17 4 5 Cautions on use of I C bus mode ceccescsscsscssesecsecsecsesecsesessesacsecsacsecsecsecsscsecsecsscsecsecsecseeas 380 17 4 6 Restrictions in IC bus mode ssssssseseeeeeeeeeee nnne nnne nnne nnn nnne nnne 383 17 4 7 SCKO SCL P27 pin output manipulation essen 385 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 ense nennen nennen nnne nnne nnne
23. 1 Port pins 3 3 Input Output P120 to P127 Function Port 12 8 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software After Reset Alternate Function RTPO to RTP7 P130 P131 Cautions Port 13 2 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software ANOO to ANO1 For pins which have alternate functions as port output do not execute the following operations during A D conversion If performed then the general error standards cannot be maintained during A D conversion lt 1 gt If it is used as a port rewriting the output latch of its output lt 2 gt Even if it is not used as a port changing the output level of pins used as outputs 61 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 2 Non port pins 1 2 Pin Name INTPO INTP1 INTP2 INTP3 INTP4 INTP5 NTP6 Input Output Input Function External interrupt request inputs with specifiable valid edges rising edge falling edge both rising and falling edges After Reset Input Alternate Function P01 TIO1 P02 P04 P05 P06 SIO SH 512 Serial interface serial data input P25 SBO P20 P70 RxD 500 501 502 Output Serial interface serial data output P26 SB1 P21 P71 TxD SBO
24. 5 304 MSB LSB switching as the start bit The 3 wire serial I O mode enables to select transfer to start from MSB or LSB Figure 16 9 shows the configuration of the serial I O shift register 0 SIOO and internal bus As shown in the figure MSB LSB can be read written in reverse form MSB LSB switching as the start bit can be specified with bit 2 CSIMO2 of the serial operating mode register 0 CSIMO Figure 16 9 Circuit of Switching in Transfer Bit Order Internal Bus 4 meq epeMpe 4 WMpmelmc LSB first MSB first gt Read Write Gate Read Write Gate e 500 Latch SIO Serial I O Shift Register 0 5100 500 SCKO Start bit switching is realized by switching the bit order for data write to SIOO The SIOO shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to SIOO Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIOO when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIEO 1 Internal serial clock is stopped or SCKO is a high level after 8 bit serial transfer Caution If CSIEO is set to 1 after data write to SIOO transfer does not start Upon termination of 8 bit transfer se
25. Interrupt request reserve No Interrupt request reserve Vectored interrupt servicing XXIF Interrupt Request Flag XXMK Interrupt Mask Flag XXPR Priority Order Specification Flag 0 No Low Priority Any Simultaneously generated xxPR 0 interrupt requests Interrupt request reserve Any Simultaneously generated high priority interrupt requests No lt gt Yes Interrupt request reserve lt a Yes Interrupt request reserve Vectored interrupt servicing Interrupt request reserve IE Flag which controls reception of maskable interrupt requests 1 permitted 0 prohibited ISP Flag which shows the priority order of the interrupt currently being processed 0 high priority order interrupt being processed 1 interrupt request being received or low priority order interrupt being processed 495 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 14 Interrupt Request Acknowledge Timing Minimum Time 6 Clocks PSW Save Interrupt CPU Processing Instruction Instruction Jump to Interrupt Servicing Servicing Program Wc PET x x PR 1 8 Clocks xx IF L ERES M x x PR 0 al 7 Clocks Remark 1 clock antes fcpu CPU clock fcPu Figure 21 15 Interrupt Request Acknowledge Timing Maximum Time 25 Clocks 6 Clocks PSW and PC Save Interrupt
26. When RESET input is applied R W Used to generate the ACK signal by software when 8 clock wait mode is selected ACKT Keeps SDAO SDA1 low from set instruction ACKT 1 execution to the next falling edge of SCL Also cleared to 0 upon start of serial interface transfer or when CSIEO 0 Note Bits 2 3 and 6 RELD CMDD and ACKD are read only bits Remark CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 349 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Figure 17 5 Serial Bus Interface Control Register Format 2 2 ACKE Acknowledge Signal Output 1 Disables acknowledge signal automatic output However output with ACKT is enabled Used for reception when 8 clock wait mode is selected or for transmission Nete 2 Enables acknowledge signal automatic output Outputs acknowledge signal in synchronization with the falling edge of the 9th SCL clock cycle automatically output when ACKE 1 However not automatically cleared to O after acknowledge signal output Used in reception with 9 clock wait mode selected ACKD Acknowledge Detection Clear Conditions ACKD 0 Set Conditions ACKD 1 While executing the transfer start instruction When acknowledge signal ACK is detected at the e When CSIEO 0 rising edge of SCL clock after completion of When RESET input is applied transfer Control of N ch Open Drain Output for Transmission in IC Bus Mode Outpu
27. ecceeceeeseseeeeeeeeeeeeeeaeeeeeeeeaeeseeeeaeeseeeseaeesaeeseeseeeesaeeseeeeeeeseaeeeeeee 264 T Timer clock select register O TCLO sesssesssssseseeeseeeeseeenen nennen nennen ennnen nennen enne nnne nnne nnns 178 254 Timer clock select register 1 ierit c rre ite re io ae feni ach ee idee pergens 220 Timer clock select register 2 TCL2 eeeeeesceesceeseeeeeeeeeeeeeeeseeeeeaeeseaeeeseesaaeeneeeeeaeeesaeseaeesaeeseaeeeneeee 240 248 258 Timer clock select register TCLS meisies aiea nennen nennen nnne nnne rennen nene 292 345 391 Transmit shift register GEXS ii eter 437 IW Watch timer mode control register TMC2 sssssssssesseseseeeeeennee nennen nennen neret nre e trennen nennen 243 Watchdog timer mode register WDTM sssssesseeneeeenmneeen nennen nennen nennen nene nennen nnne nennen 250 D 2 Register Index Register Symbol A ADCR A D conversion result register ee tee tee ree aee e 264 ADIS A D converter input select register meer nnne nennen 267 ADM A D converter mode register oie pee eerie ER REGERE AED ER epe eR eer Ed aui degno 265 ADTC Automatic data transmit receive control register 394 405 ADTI Automatic data transmit receive interval specify register 395 406 ADTP Autom
28. 182 Capture compare register 00 CROO ssssssessseseeeeeeneennee nennen nnnennnnn teretes etn nennen nen neret 177 Capture compare register 01 CRO1 177 Compare registers 10 CR O x coiere coo eive ee eae tre t ie eg eve Ded enlist e voce dear 219 20 20 iet dal de e tete att etae hat arto be ni d dO C dete eke 219 Correction address register 0 CORADO ssssssssesseeseeeeenenennnee nennen tenen nnne nnrn ernst nennen nnne enne 528 Correction address register 1 CORAD1 sssssssssssesseeeeeeneennee nennen nenne nennt nnne t nennen nennen nnne 528 Correction control register GORGN cis 1 meii pe a Re e P EDU E ER ADU Enn 529 D D A conversion value set register 0 DACSO sssssssssssssseeeee eene enne nenne nennen renes 281 D A conversion value set register 1 DACS1 sssssssssssssssseeeeeneneeenenenneee nennen nnne nnne nenne 281 D A converter mode register DAM 282 E 8 bit timer mode control register TMC1 222 8 bit timer output control register TOC a 223 8 bit timer register 1 TM ues Mle ane i e ee 219 8 bit timer register 2 TM2 iita E TR a LA caet
29. 2 External event counter operations The external event counter counts the number of external clock pulses to be input to the 1 pin with 2 channel 8 bit timer registers 1 and 2 TM1 and TM2 Each time TM1 overflows the overflow signal is used as a counter clock and TM2 is incremented When the TM1 and TM2 counted values match the values of 8 bit compare registers 10 and 20 CR10 and CR20 TM1 and TM2 are cleared to 0 and the interrupt request signal INTTM2 is generated Figure 9 12 External Event Counter Operation Timings with Rising Edge Specified U UUUULUUUUU 1 TM1 TM2 Count Value _ 0000X0001 X0002X 0003X 0004X 0005X X N 1 X_N_X0000X0001 Xo002X 0003X CR10 CR20 N INTTM2 4 Caution Even if the 16 bit timer event counter mode is used when the TM1 count value matches the CR10 value interrupt request INTTM1 is generated and the F F of 8 bit timer event counter output control circuit 1 is inverted Thus when using 8 bit timer event counter as 16 bit interval timer set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment When reading the 16 bit timer register TMS count value use the 16 bit memory manipu lation instruction 233 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 3 Operation as a Square Wave Output Operates as a square wave output at the desired frequency with the values set previously in the 8 bit conveyor registers 10 and 20 CR10 CR20 as the interval
30. 49 CHAPTER 2 OUTLINE uPD78058FY SUBSERIES 2 5 Pin Configuration Top View 1 Normal operating mode 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm UPD78056FYGC xxx 3B9 78058FYGC xxx 3B9 78058FYGC A xxx 3B9 uPD78P058FYGC 3B9 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm uPD78056FYGC ooc8BT 78058FYGC xxx 8BT 78P058FYGC 8BTNote 80 pin plastic TQFP Fine pitch 12 x 12 mm uPD78058FYGK occ BE9 NTP1 TIO1 NTPO TIOO st QN 38829 222226 0 22222 Sa mE SSS5S555 Y4oaqoco ocrcacac aS AFANAT rere re Seer or lt lt gt QOOQC QOOOCOOOQGOOOOOQO0000 80 79 78 77 76 75 74 73 7271 70 69 68 67 66 65 64 63 62 um 15 5 1 RESET P16 ANI6 2 P127 RTP7 P17 ANI7 3 O P126 RTP6 AVss O 4 O P125 RTP5 P130 ANOO O 5 O P124 RTP4 P131 ANO1 O 6 O P123 RTP3 AVner 7 P122 RTP2 P70 SI2 RxD 8 P121 RTP1 P71 SO2 TxD O 9 O P120 RTPO P72 SCK2 ASCK O P37 P20 SM O O P36 BUZ P21 SO1 O O P35 PCL P22 SCK1 O P34 TI2 P23 STB O O P33 TH P24 BUSY O P32 TO2 P25 SIO SBO SDAO P31 TO1 P26 SO0 SB1 SDA1 O P30 TOO P27 SCKO SCL O P67 ASTB P40 ADO O P66 WAIT PA1 AD1 O O P65 WR 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 OO NO Qao lt lt N 4 Y4 Note Under development Vss O O P62 O P56 A14
31. CSIMOO 51 01 2 4 INTCSIO fx 2 to 6 28 Interrupt Timing Specify Register ITCL33 TCLS2 TCL31 TCL30 Timer Clock Select Register 3 Internal Bus Remark Output Control performs selection between CMOS output and N ch open drain output 341 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 1 2 342 Serial I O shift register 0 SIOO This is an 8 bit register to carry out parallel serial conversion and to carry out serial transmission reception shift operation in synchronization with the serial clock SIOO is set with an 8 bit memory manipulation instruction When bit 7 CSIEO of serial operating mode register 0 CSIMO is 1 writing data to SIOO starts serial operation In transmission data written to SIOO is output to the serial output SOO or serial data bus SBO SB1 In reception data is read from the serial input SIO or SBO SB1 to SIOO Note that if a bus is driven in the 12 bus mode or 2 wire serial I O mode the bus pin must serve for both input and output Therefore the transmission N ch open drain output of the device which will start reception of data must be turned off beforehand Consequently write FFH to SIOO in advance In the 12 bus mode set SIOO to FFH with bit 7 BSYE of the serial bus interface control register SBIC set to 0 RESET input makes 5100 undefined Caution Do not execute an instruction that writes
32. FFE8H Priority order specify flag register OL FFE9H Priority order specify flag register OH FFEAH Priority order specify flag register 1L FFECH External interrupt mode register 0 FFEDH External interrupt mode register 1 FFFOH Memory size switching register FFF2H Oscillation mode selection register Je Je FFF3H Pull up resistor option register H FFF4H Internal expansion RAM size switching registerNote 3 ey FFF6H Key return mode register FFF7H Pull up resistor option register L FFF8H Memory expansion mode register FFF9H Watchdog timer mode register FFFAH Oscillation stabilization time select register 4a FFFBH Processor clock control register Notes 1 The external access area cannot be accessed in SFR addressing Access the area with direct addressing 2 The value after reset depends on products UPD78056F 78056FY CCH uPD78058F 78058FY uPD78P058F 78P058FY CFH 3 This register is provided only in the uwPD78058F 78058FY 78P058F and 78PO58FY 111 CHAPTER 5 CPU ARCHITECTURE 5 3 Instruction Address Addressing An instruction address is determined by program counter PC contents The contents of PC are normally incremented 1 for each byte automatically according to the number of bytes of an instruction to be
33. For pins that are to be used for data input output be sure to carry out the following settings before serial transfer of the 1st byte after RESET input lt 1 gt Set the P25 and P26 output latches to 1 2 Set bit 0 RELT of the serial bus interface control register SBIC to 1 3 Reset the P25 and P26 output latches from 1 to O When the SCKO line is high level and the SBO SB1 line changes from low level to high level or from high level to low level this is recognized as a bus release signal or command signal Therefore if there are shifts in the bus change timing due to influences such as the board capacity this may be judged to be a bus release signal or command signal even though data is being sent Thus much care should be taken in wiring CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 16 4 4 2 wire serial I O mode operation The 2 wire serial I O mode can cope with any communication format by program Communication is basically carried out with two lines of serial clock SCKO and serial data input output SBO or SB1 Figure 16 31 Serial Bus Configuration Example Using 2 Wire Serial I O Mode AVop AVop e Master Slave SCKO SCKO SBO SB1 SBO SB1 1 Register setting The 2 wire serial I O mode is set with the serial operating mode register 0 CSIMO serial bus interface control register SBIC and interrupt timing specify register SINT a Serial operating mode r
34. KRMK Standby Mode Control by Key Return Signal 0 Standby mode release enabled 1 Standby mode release disabled Caution When port 4 falling edge detection is used be sure to clear KRIF to 0 not cleared to 0 automatically 21 5 2 Test input signal acknowledge operation 1 Internal test signal INTWT When the clock timer overflows a internal test input signal INTWT is generated and this causes the WTIF flag to be set At this time a standby release signal is generated if not masked by an interrupt mask flag WTMk If the WTIF flag is checked for a shorter period than the clock timer s overflow period the clock function can be realized 2 External test signal INTPT4 When the falling edge is input to the pins of port 4 P40 to P47 an external test input signal INTPT4 is generated and this causes the KRIF flag to be set At this time a standby release signal is generated if not masked by an interrupt mask flag KRMK By using port 4 as the key matrix key return signal input it can be checked if there was key input or not by the status of the KRIF flag 504 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22 1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM RAM and SFR Connection of external devices uses ports 4 to 6 Ports 4 to 6 control address data read write strobe wait address strobe etc Table 22 1 Pin Functio
35. MCS 1 kHz fxx fx 5 0 MHz fx 2 2 5 MHz fxx 2 fx 2 2 5 MHz fx 2 1 25 MHz fxx 2 fx 2 1 25 MHz fx 2 625 kHz fxx 2 fx 2 625 kHz fx 2 313 kHz fxx 2 fx 2 313 kHz fx 2 156 kHz fxx 2 fx 2 156 kHz fx 2 78 1 kHz fxx 2 fx 2 78 1 kHz fx 2 39 1 kHz fxx 2 fx 2 39 1 kHz fx 2 19 5 kHz TIOO Valid edge s Setting prohibited 16 Bit Timer Register Count Clock Selection MCS 1 pecifiable 2fxx Setting prohibited fx 5 0 MHz fxx fx 5 0 MHz fx 2 2 5 MHz fxx 2 fx 2 2 5 MHz fx 2 1 25 MHz fxx 2 fx 2 1 25 MHz fx 2 625 kHz Watch timer output INTTM 3 Setting prohibited Cautions 1 The valid edge of pin TIOO INTPO is set with the external mode register 0 INTMO Also the frequency ofthe sampling clock is selected with the sampling clock selection register SCS 2 When enabling PCL output set TCL0O to TCLO3 then set 1 in CLOE with a 1 bit memory manipulation instruction 3 To read the count value when TIOO has been specified as the TMO count clock the value should be read from TMO not from 16 bit capture compare register 01 CRO1 4 When rewriting TCLO to other data stop the timer operation beforehand 179 CHAPTER 8 16 TIMER EVENT COUNTER Remarks 1 fxx Main sy
36. Watchdog Timer Count Clock Selection MCS 1 fx 2 39 1 kHz fx 2 19 5 kHz fxr 32 768 kHz Buzzer Output Frequency Selection TCL26 MCS 1 Buzzer output disable fxx 2 fx 2 9 8 kHz fx 2 4 9 kHz fxx 2 fx 2 4 9 kHz fx 2 2 4 kHz fxx 2 fx 2 2 4 kHz fx 2 1 2 kHz Setting prohibited Caution When rewriting TCL2 to other data stop the timer operation beforehand Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 fxr Subsystem clock oscillation frequency 4 x Don t care 5 MCS Bit 0 of oscillation mode selection register OSMS 6 Figures in parentheses apply to operation with fx 5 0 MHz or fxr 32 768 kHz 242 CHAPTER 10 WATCH TIMER 2 Watch timer mode control register TMC2 This register sets the watch timer operating mode watch flag set time and prescaler interval time and enables disables prescaler and 5 bit counter operations TMC2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC2 to 00H 10 3 Watch Timer Mode Control Register Format Symbol 7 Address After R W Reset Watch Operating Mode Selection Normal operating mode flag set at fw 2 Fast feed operating mode flag set at fw 2 TMC21 Prescaler Operation Control Clear after operation stop Operation enable Clear after operation stop Operatio
37. bo 25 fx 25 156 kHz fx 28 78 1 kHz fxx 28 26 78 1 kHz fx 27 39 1 kHz fxx 2 fx 27 39 1 kHz fx 28 19 5 kHz fxx 28 fx 28 19 5 kHz fx 29 9 8 kHz Other than above Setting prohibited Caution When rewriting other data to TCL3 stop the serial transfer operation beforehand Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 MCS Bit 0 of oscillation mode selection register OSMS 4 Figures in parentheses apply to operation with fx 5 0 MHz 392 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 2 Serial operating mode register 1 CSIM1 This register sets serial interface channel 1 serial clock operating mode operation enable stop and automatic transmit receive operation enable stop CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to OOH Figure 18 3 Serial Operating Mode Register 1 Format Symbol 5 Address After Reset R W com aeon Dee e o o Serial Interface Channel 1 Clock Selection Clock externally input to SCK1 pinNete 1 CSIM10 8 bit timer register 2 TM2 output Clock specified with bits 4 to 7 of timer clock select register 3 TCL3 EIS Serial Interface Channel 1 Operating Mode Selection 3 wire serial I O mode 3 wire serial I O mode with automatic transmit receive function Start Bit 00000 SH Pin Fun
38. sssssssssssseseseseeeenee nennen nennen enne nnne nnns 273 14 9 Example of Method of Reducing Current Consumption in Standby Mode 274 14 10 Connection of Analog Input Pin essere nnne nnne nnne enne tenens 275 14 11 A D Conversion End Interrupt Request Generation Timing ssseeeee 276 14 12 Connection of AVbb Pin a oc ed HI UR HR RETI UR 277 15 1 D A Converter Block Diagtam trotz pe tenet cade alee tee td ove rede ten oe 280 15 2 D A Converter Mode Register Format ssssssssssseseeeeeeeeennee nennen nennen trennen nnne nennen 282 15 3 Use Example of Buffer Amplifier 284 16 1 Serial Bus Interface SBI System Configuration Example seen 287 16 2 Serial Interface Channel 0 Block Diagram sssesseeeee eene eene 289 16 3 Timer Clock Select Register Format ssssssssssseeeeeneeennee enne nnne nenne nnne nnns 293 16 4 Serial Operating Mode Register 0 Format sesssssssssseeneeeeeeneeneeenneen nene 294 16 5 Serial Bus Interface Control Register Format ssessssssseeeeenenneennneneee nennen nnne 296 16 6 Interrupt Timing Specify Register Format sssssssssseeeeeneeeeenenen nennen nennen nnne 298 16 7 3 Wire Serial 1 Mode Timings 3 n ett rt Le READER e RR ERIS 303 16 8 REL
39. 574 4 us O 5 fsck 577 6 us 1 5 fsck 600 0 us 0 5 fsck 603 2 us 1 5 fsck 625 6 us 0 5 fscx 628 8 us 1 5 fsck 651 2us 0 5 fscx 654 4us 1 5 fsck 676 8 us 0 5 fscx 680 0 us 1 5 fsck 702 4us 0 5 fsck 705 6 us 1 5 fsck 728 0 us 0 5 fsck 731 2us 1 5 fsck 753 6 us 0 5 fscx 756 8 us 1 5 fsck 779 2 us 0 5 fsck 782 4 us 1 5 fsck 804 8 us 0O 5 fsck 808 0 us 1 5 fsck 830 4 us 0 5 833 6 us 1 5 fsck The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value setin ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck Minimum 1 x 26 _28 _0 5 fsck Maximum 1 2 36_ 4 1 5 fxx fsck Cautions 1 Do not write ADTI during operation of automatic data transmit receive function 2 Bits 5 and 6 must be set to zero 3 If the auto send and receive data transmission interval time is controlled using ADTI busy control becomes invalid see 18 4 3 4 a Busy control option Remarks 1 fxx 2 fx 3 fsck Serial clock frequency Main system clock frequency fx or fx 2 Main system clock oscillation frequency 398 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18 4
40. Figure 6 16 P71 and P72 Block Diagram P71 SO2 TxD e WRpeuo PUO7 Jo P ch RD A WRreort Output Latch P71 and P72 2 e WRem PM RD WR E PM71 PM72 e Alternate Function PUO Port mode register Port 7 read signal Port 7 write signal Pull up resistor option register 9 P72 SCK2 ASCK 143 CHAPTER 6 PORT FUNCTIONS 6 2 10 Port 12 This is an 8 bit input output port with output latches Input mode output mode can be specified bit wise by means of port mode register 12 PM12 When pins P120 to P127 are used as input port pins an on chip pull up resistor can be used as an 8 bit unit by means of pull up resistor option register H PUOH Alternate function includes real time output RESET input sets the input mode Figure 6 17 shows a block diagram of port 12 Figure 6 17 P120 to P127 Block Diagram AVop e WRPuo Moa PUO12 P ch RD xl o 2 2 Whronr S P120 RTPO E Output Latch to P120 to P127 P127 RTP7 WRPM 1 120 127 Pull up resistor option register PM Port mode register RD Port 12 read signal WR Port 12 write signal 144 CHAPTER 6 PORT FUNCTIONS 6 2 11 Port 13 This is a 2 bit input output port with output latches Input mode output mode can be specified bit wise by means of port mo
41. In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases In service priority flag ISP This flag manages the priority of acknowledgeable maskable vectored interrupts When ISP 0 acknowledgment of a vector interrupt request specified to be low by the priority order instruction flag register PROL PROH PR1L See 21 3 3 Priority specify flag registers PROL PROH PR1L is prohibited Furthermore whether or not an interrupt request can actually be acknowledged or not is controlled by the status of the interrupt enable IE flag Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution CHAPTER 5 CPU ARCHITECTURE 3 Stack pointer SP This is a 16 bit register to hold the start address of the memory stack area Only the internal high speed RAM area FBOOH to FEFFH can be set as the stack area Figure 5 9 Stack Pointer Format SP 15 0 The SP is decremented ahead of write save to the stack memory and is incremented after read reset from the stack memory Each stack operation saves resets data as shown in Fi
42. Timer Start 2 8 bit compare register 10 and 20 setting The 8 bit compare registers 10 and 20 CR10 and CR20 can be set to 00H Thus when these 8 bit compare registers are used as event counters one pulse count operation can be carried out When the 8 bit compare register is used as 16 bit timer event counter write data to CR10 and CR20 after setting bit 0 TCE1 of the 8 bit timer mode control register 1 TMC1 to 0 and stopping timer operation Figure 9 15 Event Counter Operation Timing TH TI2 Input A NC UE c INS AT CR10 CR20 00H TM1 TM2 Count Value 00H 00H 00H 00H TO1 TO2 AEN x DM au DUM Interrupt Request Flag 236 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 3 Operation after compare register change during timer count operation If the values after the 8 bit compare registers 10 and 20 CR10 and CR20 are changed are smaller than those of 8 bit timer registers TM1 and TM2 TM1 and TM2 continue counting overflow and then restart counting from 0 Thus if the value M after CR10 and CR20 change is smaller than value N before the change it is necessary to restart the timer after changing CR10 and CR20 Figure 9 16 Timing After Compare Register Change During Timer Count Operation feme UE NL ONU Aen UA XC Nu Nes CR10 CR20 N X M Remark N gt X gt M 237 MEMO 238 CHAPTER 10 WATCH TIMER 10 1 Watch Timer Functions The watch timer has the following functions W
43. WRreort WRem NN PM22 PM27 e PUO PM RD WR HL Output Latch i P22 and P27 P22 SCK1 Alternate Function Pull up resistor option register Port mode register Port 2 read signal Port 2 write signal P27 SCKO SCL CHAPTER 6 PORT FUNCTIONS 6 2 5 Port 3 Port 3 is an 8 bit input output port with output latch P30 to P37 pins can specify the input mode output mode in 1 bit units with the port mode register 3 PM3 When P30 to P37 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Alternate functions include timer input output clock output and buzzer output RESET input sets port 3 to input mode Figure 6 9 shows a block diagram of port 3 Figure 6 9 P30 to P37 Block Diagram AVop e WRPuo PUO3 jo P ch RD e jj lt Cee 2 A P30 TOO S Output Latch to a t e P30 to P37 2 ESSE P34 TI2 P35 PCL P36 BUZ WRem P37 cd PM30 to PM37 e Alternate Function PUO Pull up resistor option register PM Port mode register RD Port 3 read signal WR Port 3 write signal 137 CHAPTER 6 PORT FUNCTIONS 6 2 6 Port 4 Port 4 is an 8 bit input output port with output latch P40 to P47 pins can specify the input mode output mode in 8 bit unit
44. ey 5100 lt Address 100 lt Data T munni an po wi 0 5 5 CMDT RELT L o CLC P TEE WREL L sc INTCSIO ppp SCL 1121 B 14 T 1 lal 3 MI 5 SDAO X VASA AS 2 AO NW ACI V D7 AD6D5 D4AD3 SIO0 FFH T 000 CMDD RELD L NN CLD pi _ P27 WUP BSYE T ACKE CMDT RELT CLC WREL SIC INTCSIO CSIEO P25 PM25 PM27 r LL r r r 374 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Figure 17 22 Data Transmission from Master to Slave Both Master and Slave Selected 9 Clock Wait 2 3 b Data Master Device Operation Write SIOO 5100 lt Address 5100 lt Data col LXXXXXAXX X X XX ick CMDD RELD S y qu o i aJ INTCSIQ 1 12 3 M4 bI 16 7 le 9b 1 lal 3 5 SCL SDAO 07 XD6XD5XD4XD3XD2XD1 ADONQI V D7 06 AD5XD4 JD3 NIS SIQU Col VX XX XX KX KL A pM Y O a 4 27 D BERND WUP m BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO CSIEO P25 PM25 PM27 rjir T r r 375 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Figure 17 22 Data Transmission from Master to Slave Both Master and Slave Selected 9
45. 0 Operation stopped 1 Operation enable Notes 1 Tousethe wake up function WUP 1 clear the bit 5 SIC of the interrupt timing specify register SINT to 0 2 When CSIEO 0 COI becomes 0 3 In the SBI mode the operation of serial interface channel 0 should be stopped CSIE lt 0 after clearing WUP to 0 If WUP is not 0 P25 is fixed at high level and it is not possible to use it as a normal port 295 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 3 Serial bus interface control register SBIC This register sets serial bus interface operation and displays statuses SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to OOH Figure 16 5 Serial Bus Interface Control Register Format 1 2 symbol Address After Reset R W SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R WNete R W Used for bus release signal output When RELT 1 SOO latch is set to 1 After SOO latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 Used for command signal output When CMDT 1 SOO latch is cleared to 0 After SOO latch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 RELD Bus Release Detection Clear Conditions RELD 0 Set Conditions RELD 1 When transfer start instruction is executed When bus release signal REL is detected If SIOO and SVA values do not
46. 1 64 ms 3 2 us 6 4 us 25 x 1 fx 28 x 1 fx 213 x 1 fx 214 x 1 fx 25 x 1 fx 28 x 1 fx 6 4 us 12 8 us 1 64 ms 3 28 ms 6 4 us 12 8 us 28 x 1 fx 27 x 1 fx 214 x 1 fx 215 x 1 fx 28 x 1 fx 27 x 1 fx 12 8 us 25 6 us 3 28 ms 6 55 ms 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 215 x 1 fx 216 x 1 fx 27 x 1 fx 28 x 1 fx 25 6 us 51 2 us 6 55 ms 13 1 ms 25 6 us 51 2 us 28 x 1 fx 29 x 1 fx 216 x 1 fx 217 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 us 13 1 ms 26 2 ms 51 2 us 102 4 us 29 x 1 fx 210 x 1 fx 217 x 1 fx 218 x 1 fx 29 x 1 fx 210 x 1 fx 102 4 us 204 8 us 26 2 ms 52 4 ms 102 4 us 204 8 us 211 x 1 fx 212 x 1 fx 219 x 1 fx 220 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 104 9 ms 209 7 ms 409 6 us 819 2 us Remarks 1 fx Main system clock oscillation frequency 2 Bit 0 of oscillation mode selection register OSMS 3 Values in parentheses when operated at fx 5 0 MHz 229 CHAPTER 9 8 BIT TIMER EVENT COUNTERS Figure 9 10 Square Wave Output Operation Timing camcek LJ LE LILI LIL LI LLU I LI LI LJ TM1 Count Value 00 Ko Ko Ko X 4 XNSQCN A Count Start CR10 N AE TO1Note E Note Theinitial value of TO1 output can be set with bits 2 and LVR1 and LVS1 of the 8 bit timer output control register TOC1 9 4 2 16 bit timer event counter mode When bit 2 TMC12 of the 8 bit timer mode control register TMC1
47. 272 14 5 A D Converter Cautions 274 CHAPTER 15 D A CONVERTER a eaa a a a r a aar a a a aera aa aaa aa esinin aiin 279 15 1 D A Converter Functions 279 15 2 D A Converter Configuration ccceeeeseseeeeseeeeeeeeeseseeeeeeseeeeseaaeeeeeeeesecaesaseeaeseeeesesneeneneees 280 15 3 D A Converter Control Registers 282 15 4 Operations of D A Converter 283 15 5 Cautions Related to D A Converter esses 284 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 285 16 1 Serial Interface Channel 0 Functions eese eeeeeeeeee ener nnne nnn 286 16 2 Serial Interface Channel 0 Configuration essersi esent 288 16 3 Serial Interface Channel 0 Control ener 292 16 4 Serial Interface Channel 0 eene nennen nnn nnn 299 16 4 1 _ Operation stop mode ne cct dte pee e te vut e bread c e Ea Eee Ye dupl dcs 299 16 4 2 3 wire serial I O mode operation ssssssseseeneeneenenennenen nennen neret nnns 300 19 16 4 3 SBlmode operation eee tet el ae alae 305 16 4 4 2 wire serial mode operation
48. 3 4 fx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency MCS Bit 0 of oscillation mode selection register OSMS Figures in parentheses apply to operation with fx 2 5 0 MHz 293 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 2 Serial operating mode register 0 CSIMO This register sets serial interface channel 0 serial clock operating mode operation enable stop wake up function and displays the address comparator match signal CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Caution Do not switch the operating mode 3 wire serial I O 2 wire serial l O SBI while operation of serial interface channel 0 is enabled If switching the operation mode first terminate the serial operation then carry out switching Figure 16 4 Serial Operating Mode Register 0 Format 1 2 Symbol CSIMO1 CSIMOO Serial Interface Channel 0 Clock Selection Input Clock to SCKO pin from off chip R W 4 3 1 0 Address After Reset 00H R W R WNete 1 8 bit timer register 2 TM2 output Operation Mode 3 wired serial mode Start Bit Clock specified with bits O to 3 of timer clock select register 3 TCL3 SIO SB0 P25 Pin Function S QNete 2 Input SO0 SB1 P26 Pin Function 500 CMOS output SCKO0 P27 Pin Function SCKO CMOS input output Note 3 x N
49. 3 2 us 52 4 ms 104 9 ms 800 ns 1 6 us 2 x watch timer output cycle 216 x watch timer output cycle Watch timer output edge cycle Remarks 1 fx Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 3 Values in parentheses when operated at fx 5 0 MHz 2 PWM output TMO can generate 14 bit resolution PWM output 3 Pulse width measurement TMO can measure the pulse width of an externally input signal 4 External event counter TMO can measure the number of pulses of an externally input signal 173 CHAPTER 8 16 TIMER EVENT COUNTER 5 Square wave output TMO can output a square wave with any selected frequency Table 8 3 16 Bit Timer Event Counter Square Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS 1 MCS 0 MCS 1 MCS 0 2 x TIOO input cycle 216 x TIOO input cycle TIOO input edge cycle 2 x 1 fx 216 x 1 fx 1 fx 400 ns 13 1 ms 200 ns 2 x 1 fx 22 x 1 fx 216 x 1 fx 217 x 1 fx 1 fx 2 x 1 fx 400 ns 800 ns 13 1 ms 26 2 ms 200 ns 400 ns 22 x 1 fx 23 x 1 fx 217 x 1 fx 218 x 1 fx 2 x 1 fx 22 x 1 fx 800 ns 1 6 us 26 2 ms 52 4 ms 400 ns 800 ns 23 x 1 fx 24 x 1 fx 218 x 1 fx 219 x 1 fx 22 x 1 fx 23 x 1 fx 1 6 us 3 2 us 52 4 ms 104 9 ms 800 ns 1 6 us 2 x watch timer output cycle 216 x watch timer output cycle Watch timer output edge cycle
50. 838 9 ms 223 x 1 fx 1 7 s 26 x 1 fx 12 8 us 2 x 1 fx 25 6 us 2 x 1 fx 25 6 us 28 x 1 fx 51 2 us 223 x 1 fx 1 7 s 224 x 1 fx 8 4 s 27 x 1 fx 25 6 us 28 x 1 fx 51 2 us 28 x 1 fx 51 2 us 29 x 1 fx 102 4 us 224 x 1 fx 3 4 s 225 x 1 fx 6 7 s 28 x 1 fx 51 2 us 29 x 1 fx 102 4 us 29 x 1 fx 102 4 us 210 x 4 fx 204 8 us 225 x 1 fx 6 7 s 226 x 1 fx 13 4 s 29 x 1 fx 102 4 us 210 x 4 fx 204 8 us 211 x 1 fx 409 6 us Remarks 1 fx 212 x 1 fx 819 2 us 227 x 1 fx 26 8 s 228 x 1 fx 53 7 s Main system clock oscillation frequency 211 x 1 fx 409 6 us 2 MCS Bit 0 of oscillation mode selection register OSMS 3 Values in parentheses when operated at fx 5 0 MHz 212 x 1 fx 819 2 us 215 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 9 2 8 Bit Timer Event Counter Configuration The 8 bit timer event counters 1 and 2 consist of the following hardware Table 9 5 8 Bit Timer Event Counter Configuration Timer register 8 bits x 2 TM1 TM2 Register Compare register 8 bits x 2 CR10 CR20 Timer output 2 TO1 TO2 Timer clock select register 1 TCL1 8 bit timer mode control register 1 TMC1 Control register 8 bit timer output control register TOC1 Port mode register 3 PM3 Note Note See Figure 6 9 P30 to P37 Block Diagram 216 CHAPTER 9 8 B
51. CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 2 Communication operation The 3 wire serial I O mode is used for data transmission reception in 8 bit units Bit wise data transmission reception is carried out in synchronization with the serial clock Shift operation of the serial I O shift register 0 SIOO is carried out at the falling edge of the serial clock SCKO The transmitted data is held in the SOO latch and is output from the SOO pin The received data input to the SIO pin is latched in SIOO at the rising edge of SCKO Upon termination of 8 bit transfer 5100 operation stops automatically and the interrupt request flag CSIIFO is set Figure 16 7 3 Wire Serial I O Mode Timings SCKO SIO 500 End of Transfer fies Transfer Start at the Falling Edge of SCKO The SOO pin is a CMOS output pin and outputs current SOO latch statuses Thus the SOO pin output status can be manipulated by setting bit 0 RELT and bit 1 CMDT of serial bus interface control register SBIC However do not carry out this manipulation during serial transfer Control the SCKO pin output level in the output mode internal system clock mode by manipulating the P27 output latch refer to 16 4 5 SCKO0 P27 pin output manipulation 3 Other signals Figure 16 8 shows RELT and CMDT operations Figure 16 8 RELT and CMDT Operations SOO latch RELT CMDT 303 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 4
52. Exe ibt prae ett eet eo E EN EM OUT eae eee e cx REEL ceed 130 146 Port mode register 2 eee ee dee decet 130 146 Port mode register 3 nennen 130 146 184 224 256 260 Port mode reglsterb i inu santet ed ER eua eeu Aon eu 130 146 Port mode register 6 2 utei nv e v tad ipee nt bee epic 130 146 Portmode reglster 27 cett AI UE B OR POE ue LC Ota 130 146 Priority specify flag register OH ccessececesseeeseneeeseeceeeeeceeseeneeeenceneseneesageeesnessenesenerseenersesiaenees 485 Priority specify flag register OL iecore et t ccr a te thc eed a 485 Priority specify flag register ae 485 Program status WOrd aiiis itte re dece ved Ree nla alan 490 Pull up resistor option register i ena 149 Pull up resistor option register L essen enne nnne nennen nnne nnne 149 Real time output buffer register etenim 473 Real time output buffer register L 473 Real time output port control register 475 Real time output port mode register 474 Receive buffer register eite rebote eh ctv Eds e e Bde Ae eet 437 Receive shiftsregister diei ene te a The
53. INTCSI1 End of serial interface channel 1 transfer Serial interface channel 2 UART reception INTSER error generation INTSR End of serial interface channel 2 UART reception INTCSI2 End of serial interface channel 2 3 wired transfer End of serial interface channel 2 UART transfer Notes 1 Default priorities are intended for two or more simultaneously generated maskable interrupts 0 is the highest priority and 18 is the lowest priority 2 Basic configuration types A to E correspond to A to E of Figure 21 1 478 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21 1 Interrupt Source List 2 2 Note 1 Interrupt Default Interrupt Source Internal Vector NE Table Type Priority Trigger External Address INTTM3 Reference time interval signal from Internal watch timer INTTMOO Generation of 16 bit timer register capture compare register CROO match signal INTTMO1 Generation of 16 bit timer register Maskable capture compare register CRO1 match signal INTTM1 Generation of 8 bit timer event counter 1 match signal INTTM2 Generation of 8 bit timer event counter 2 match signal End of A D converter conversion Software BRK instruction execution Notes 1 Default priorities are intended for two or more simultaneously generated maskable interrupts 0 is the highest priority and 18 is the lowest priority 2
54. M A D Converter Samplin A D Conversion Operation png Conversion SAR Undefined Result Conversion Result INTAD A D conversion operations are performed continuously until bit 7 CS of ADM is reset 0 by software ADCR If a write to the ADM is performed during an A D conversion operation the conversion operation is initialized and if the CS bit is set 1 conversion starts again from the beginning After RESET input the value of ADCR is undefined 270 CHAPTER 14 A D CONVERTER 14 4 2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins ANIO to ANI7 and the A D conversion result the value stored in A D conversion result register ADCR is shown by the following expression ADCR INT x 256 0 5 AVREFO or AVREFO AVREFO ADCR 0 V ADCR 0 ADC 0 5 x 256 IN lt ADCR 0 5 x 256 Where INT Function which returns integer parts of value in parentheses ViN Analog input voltage AVnero AVnero pin voltage ADCR Value of A D conversion result register ADCR Figure 14 6 shows the relation between the analog input voltage and the A D conversion result Figure 14 6 Relationship Between Analog Input Voltage and A D Conversion Result 255 c t e e ou 254 LE LE eee A D Conversion 253 UM Result
55. O 5 fsck MaximumNete 224 8 us 1 5 fsck 236 0 us 0 5 fsck 237 6 us 1 5 fsck 248 8 us 0 5 fsck 250 4 us 1 5 fsck 261 6 us 0 5 fsck 263 2 us 1 5 fsck 274 4 us O 5 fsck 276 0 us 1 5 fsck 287 2 us O 5 fsck 288 8 us 1 5 fsck 300 0 us 0 5 fsck 301 6 us 1 5 fsck 312 8 us 0 5 fsck 314 4 us 1 5 fsck 325 6 us 0 5 fsck 327 2 us 1 5 fsck 338 4 us 0 5 fsck 340 0 us 1 5 fsck 351 2 us 0 5 fsck 352 8 us 1 5 fsck 364 0 us 0 5 fsck 365 6 us 1 5 fsck 376 8 us 0 5 fsck 378 4 us 1 5 fsck 389 6 us 0 5 fsck 391 2 us 1 5 fsck 402 4 us 0 5 fsck 404 0 us 1 5 fsck 415 2 us 0 5 fsck 416 8 us 1 5 fsck Note The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value set in ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck Minimum n 1 x 26 1 98 70 5 fxx fxx fsck Maximum n1 x soc uL 145 fxx fxx fsck Cautions 1 Do not write ADTI during operation of automatic data transmit receive function 2 Zero must be set in bits 5 and 6 3 If the auto send and receive data transmission interval time is controlled using ADTI busy control becomes invali
56. Port4 Port5 Port6 Port7 Port12 Port13 PCL RD RESET RTPO to RTP7 RxD SBO SB1 SCKO to SCK2 SCL SDAO SDA1 SIO to SI2 500 to 502 STB TIOO T1014 TH TI2 TOO to TO2 TxD VPP Vss WAIT WR X1 X2 XT1 XT2 Programmable Clock Read Strobe Reset Real Time Output Port Receive Data Serial Bus Serial Clock Serial Clock Serial Data Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Programming Power Supply Ground Wait Write Strobe Crystal Main System Clock Crystal Subsystem Clock 51 CHAPTER 2 OUTLINE uPD78058FY SUBSERIES 2 PROM programming mode 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm UPD78P058FYGC 3B9 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm uPD78PO58FYGC 8BTNote pen pen L a T amp 8 D 284 gt 2 dOo2uo QOOOCOOOOOOOOOOOOOOOQ O A9 O 1 O RESET L lt 2 O O 3 O O Vss 4 5 O 0195 6 5 L Voo 7 O O 8 O O 9 O O O D7 O O D6 O O D5 04 O D4 O O D3 O O D2 O O D1 O O DO O OVW 9 9 0 1 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 OOOOOOOOOOOOOOOOOOOO 22192u2 9r 922 2 gt 3 0 Note Under development Cautions 1 L Connect independenily to Vss via a pull down resistor 2 Vss Connect to the ground 3 RESET Set to the low level 4 Open Do not c
57. Remarks 1 fx Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 3 Values in parentheses when operated at fx 5 0 MHz 6 One shot pulse output TMO is able to output one shot pulse which can set any width of output pulse 8 3 16 Bit Timer Event Counter Configuration The 16 bit timer event counter consists of the following hardware Table 8 4 16 Bit Timer Event Counter Configuration Configuration Timer register 16 bits x 1 TMO Register Capture compare register 16 bits x 2 CROO CRO1 Timer output 1 TOO Control register Timer clock select register 0 TCLO 16 bit timer mode control register TMCO Capture compare control register 0 CRCO 16 bit timer output control register TOCO Port mode register 3 PM3 External interrupt mode register 0 INTMO Sampling clock select register SCS Note Note Refer to the Figure 21 1 Basic Configuration of Interrupt Function 174 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 1 16 Bit Timer Event Counter Block Diagram Internal bus Control Register 0 INTP1 16 Bit Capture Compare ie Register 00 0 PWM Pulse Match Output Note 2 NIME Controller xx 16 Bit Timer Event i 8 TMCO to TMCO3 Counter Output TOO P30 folo 8 16 Bit Timer Register Control Circuit o 00 00 ee Circui
58. Symbol 7 4 3 2 1 0 Address After Reset R W PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120 FF2CH FFH R W PM12n Selects I O Mode of P12n Pin 0 to 7 Output mode output buffer ON Input mode ourput buffer OFF 2 Real time output port mode register RTPM Symbol 7 6 5 4 3 2 1 0 Address This register selects the real time output port mode port mode bit wise RTPM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 20 4 Real time Output Port Mode Register Format After Reset RTPM 6 5 2 1 FF34H 00H R W 474 RTPMn Real time Output Port Selection n 0 to 7 Port mode Real time Output Port Mode Cautions 1 When using these bits as a real time output port set the ports to which real time output is performed to the output mode clear the corresponding bit of the port mode register 12 PM12 to 0 2 In the port specified as a real time output port data cannot be set to the output latch Therefore when setting an initial value data should be set to the output latch before setting the real time output mode CHAPTER 20 REAL TIME OUTPUT PORT 3 Real time output port control register RTPC This register sets the real time output port operating mode and output trigger Table 20 3 shows the relation between the operating m
59. WREL Wait Release Control Indicates that the wait state has been released Releases the wait state Automatically cleared to 0 after releasing the wait state This bit is used to release the wait state set by means of WATO and WAT1 R W Clock Level Control Used in 12 bus mode In cases other than serial transfer SCL pin output is driven low Used in 12 bus mode In cases other than serial transfer SCL pin output is set to high impedance Clock line is held high Used by master device to generate the start condition and stop condition signals RW ee e O 1 Bits 1 to 7 Rw BE e e 1 CSIIFO is set to 1 after end of serial interface channel 0 transfer or when stop condition is detected SCL Pin LevelNote 4 0 Low level 1 High level Notes 1 Bit 6 CLD is read only 2 When the 12 bus mode is used be sure to set 1 and 0 or 1 and 1 in WATO and WAT1 respectively 3 When using the wake up function in 12 mode be sure to set SIC to 1 4 When CSIEO 0 CLD is 0 Remark SVA Slave address register CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 370 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 4 Various signals A list of signals in the 12 bus mode is given in Table 17 4 Start condition Stop condition Acknowledge signal ACK Serial Clock SCL Address A6
60. lt 1 gt gt lt lt 3 gt lt 2 gt When RXE is set to 0 at a time indicated by 1 RXB holds the previous data and does not generate INTSR When RXE is set to 0 at a time indicated by 2 RXB renews the data and does not generate INTSR When RXE is set to 0 at a time indicated by 3 RXB renews the data and generates INTSR 460 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 4 3 3 wire serial I O mode The 3 wire serial I O mode is useful for connection of peripheral I Os and display controllers etc which incorporate a conventional synchronous clocked serial interface such as the 75X XL Series 78K Series 17K Series etc Communication is performed using three lines the serial clock SCK2 serial output SO2 and serial input SI2 1 Register setting The 3 wire serial I O mode is set with the serial operating mode register 2 CSIM2 and serial bus interface control register SBIC a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H Symbol Address After Reset R W FF72H 00H R W CSCK Serial Operating Mode Selection 0 UART mode 1 3 wire serial mode CSIM22 First Bit Specification MSB LSB CSIM2 D 6 5 4 3 2 1 0 CSIM o e o o CSIE2 Operation Control in 3 wire Serial I O Mode 0 Operation stopped 1 Operation enabled Caution Ensure
61. sfr byte Ww wy no sfr lt byte A r Aer r lt saddr lt A A sfr A lt sfr sfr A sfr lt A A laddr16 lt addr16 laddr16 A addr16 lt A PSW byte PSW lt byte A PSW A PSW PSW A m m Cce co c nmj nm rnmij rnmnm PSW A A DE A DE 8 bit data DE A DE A transfer A HL A lt HL HL A HL A A HL byte A lt HL byte HL byte A HL byte A A HL B lt HL B HL A HL lt A A HL A lt HL C HL C A HL C eA Aer BLM oj AJAJAJA 6 A 6 sfr laddr16 10 n m addr16 DE 6 n m DE HL 6 n m HL HL byte 10 n m HL byte HL B 10 n m HL B HL C 10 n m HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Except r A Remarks 1 One instruction clock is the length of 1 clock cycle of the CPU clock fceu selected by the processor clock con
62. 1 A bit A bit 1 PSW bit PSW bit 1 HL bit HL bit lt 1 saddr bit saddr bit lt 0 sfr bit sfr bit 0 A bit A bit lt 0 PSW bit PSW bit 0 HL bit mimmi coj nmj rnjnmj rnmj c rni nm coi nmji coj co nmi coj nmj coj coj nmicoj nmi co c HL bit 0 CY 1 CY lt 0 Notes 1 When the internal high speed RAM area is accessed or instruction with no data access CY CY 2 When an area except the internal high speed RAM area is accessed Remarks 1 One instruction clock is the length of 1 clock cycle of the CPU clock fceu selected by the processor clock control register PCC This clock cycle applies to internal ROM program 3 n is the number of waits when external memory expansion area is read from 4 m is the number of waits when external memory expansion area is written to 557 CHAPTER 27 INSTRUCTION SET Instruction Group Mnemonic Operands Operation SP 1 lt PC 3 SP 2 lt PC 3 PC lt addr16 SP lt SP 2 SP 1 lt PC 2 SP 2 lt PC 2 laddr1 1 PC15 11 00001 PC1o 0 lt addr11 SP SP 2 SP 1 lt PC 1 SP 2 lt PC t lt 00000000 addr5 1 PC lt 00000000 addr5 SP SP 2 SP 1 lt PSW SP 2 lt PC 1 SP 3 lt PC 1 PCH 003FH PC lt 003EH S
63. 186 8 10 Control Register Settings for Interval Timer Operation seseeeeenne 187 8 11 Interval Timer Configuration Diagram essessseeeeenneenenenneen nennen nennen nennen nns 188 8 12 Interval Timer Operation Timings ccccceeceeeceeeneeceeeeeeeseaeeeeeeeaeeceeeeeeeeeaeeseaeeeaeeseaeeseeeeeaeeseaeenaeeesaee 188 8 13 Control Register Settings for PWM Output Operation sssseeeeeeeeeen een 190 8 14 Example of D A Converter Configuration with PWM Output eee 191 8 15 TV Tuner Application Circuit Example sessi 191 8 16 Control Register Settings for PPG Output Operation sese 192 8 17 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register reped eee PERRO DURER 193 8 18 Configuration Diagram for Pulse Width Measurement by Free Running Counter 194 8 19 Timing of Pulse Width Measurement Operation by Free Running Counter and One Capture Register with Both Edges Specified ssssssssseeeeeeeeneneneeenee nennen 194 8 20 Control Register Settings for Two Pulse Width Measurements with Free Running Counter 195 8 21 Timing of Pulse Width Measurement Operation with Free Running Counter with Both Edges Specified irte tee dcn ca t pitt ete t RR ER Re Rx 196 8 22 Control Register Settings for Pulse Width Measur
64. 2 The AVpo pin is used in common as the power supply for the A D converter and port If this device is used in application fields where reduction of noise generated internally in the microprocessor is required please connect to a separate power supply with the same electrical potential as Vpp 3 The AVss pin is used in common as the ground for the A D converter D A converter and port If this device is used in application fields where reduction of noise generated internally in the microprocessor is required please connect it to a ground line which is separate from Vss Remark Pin connection in parentheses is intended for the uPD78P058F 38 CHAPTER 1 OUTLINE uPD78058F SUBSERIES Pin Identifications A8 to A15 ADO to AD7 ANIO to ANI7 ANOO ANO1 ASCK ASTB AVREF 1 AVss BUSY BUZ IC INTPO to INTP6 POO to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 Address Bus Address Data Bus Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected Interrupt from Peripherals Porto Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port12 P130 P131 PCL RD RESET RTPO to RTP7 RxD SBO SB1 SCKO to SCK2 SIO to SI2 SO0 to SO2 STB TIOO TIO1 TH TI2 TOO to TO2 TxD Vpop VpP Vss WAIT WR X1 X2 XT1 XT2 Port13
65. A lt A addr16 CY A HL A CY HL CY A HL byte A CY A HL byte CY A HL B A CY HL CY KR RR oO RI RB A HL A CY lt HL C CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Only when rp BC DE or HL 4 Except r A Remarks 1 One instruction clock is the length of 1 clock cycle of the CPU clock fceu selected by the processor clock control register PCC 2 This clock cycle applies to internal ROM program 3 nis the number of waits when external memory expansion area is read from 4 mis the number of waits when external memory expansion area is written to 553 CHAPTER 27 INSTRUCTION SET Instruction Group Mnemonic Operands A byte Operation A CY A byte saddr byte saddr CY lt saddr A r A CY A r CY r A A saddr A CY lt A saddr A addr16 A CY lt A addr16 A HL A HL byte A CY lt HL byte A HL B A CY A HL A CY lt HL B A HL C A CY HL C A
66. CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 2 Memory size switching register IMS This register specifies the internal memory size In principle use IMS in a default status However when using the external device expansion function with the uPD78058F 78PO58F 78058FY and 78P058FY set IMS so that the internal ROM capacity is 56 Kbytes or lower IMS is set with an 8 bit memory manipulation instruction RESET input sets this register to the value indicated in Table 22 3 Figure 22 3 Memory Size Switching Register Format Symbol 7 6 1 0 Address After 5 4 3 2 Reset IMS RAM2 RAM1 RAMO ROMS ROM2 ROM1 ROMO FFFOH Note ROMO R W R W Internal ROM Size Selection 48 Kbytes 56 Kbytes 60 Kbytes Other than above Setting prohibited RAM2 RAM1 Internal High Speed RAM Size Selection 1 1 0 1024 bytes Other than above Setting prohibited Note The values after reset depend on the product See Table 22 3 Table 22 3 Values When the Memory Size Switching Register Part Number Reset Value uPD78056F 78056FY 78058 78058FY Is Reset 509 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22 3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows 1 2 3 4 5 RD pin Alternate function P64 Read strobe signal output pin The read strobe s
67. CSIEO 1 Internal serial clock is stopped or SCKO is at high level after 8 bit serial transfer Cautions 1 If CSIEO is set to 1 after data write to SIOO transfer does not start 2 It is necessary to set the N ch open drain output in the high impedance state when receiving data so write FFH in SIOO in advance Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIFO is set Error detection In the 2 wire serial I O mode the serial bus SBO SB1 status being transmitted is fetched into the destination device that is serial I O shift register 0 SIOO Thus transmit error can be detected in the following way a Method of comparing SIOO data before transmission to that after transmission In this case if two data differ from each other a transmit error is judged to have occurred b Method of using the slave address register SVA Transmit data is set to both SIOO and SVA and is transmitted After termination of transmission COI bit match signal coming from the address comparator of the serial operating mode register 0 CSIMO is tested If 1 normal transmission is judged to have been carried out If 0 a transmit error is judged to have occurred CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 17 4 4 12 bus mode operation The 12C bus mode is provided for when communication operations are performed between a single master device and mu
68. DDS SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 1 4 inch CGMT NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Notes 1 Can also be operated in DOS environment 2 Does not support WindowsNT 570 APPENDIX B DEVELOPMENT TOOLS B 2 PROM Programming Tool B 2 1 Hardware PG 1500 This is a PROM programmer capable of programming the single chip microcontroller with on chip PROM programmer PROM by manipulating from the stand alone or host machine through connection of the separately available programmer adapter and the attached board It can also program separate PROM ICs with a capacity from 256 Kbits to 4 Mbits PA 78P054GC This is a PROM programmer adapter for the uPD78P058F 78PO58FY and is used connected to PROM programmer the PG 1500 adapter PA 78P054GC 80 pin plastic QFP GC 3B9 GC 8BT type B 2 2 Software PG 1500 controller This program controls the PG 1500 from the host machine through serial and or parallel interface cable s The PG 1500 controller is a DOS based application When using Windows start it from the DOS prompt Part Number uS xxxxPG1500 Remark of the part number differs depending on the host machine and OS used Refer to the table below uSxxxxPG1500 Host Machine Supply Media PC 9800 Series MS DOS 3 5 inch 2HD FD Ver 3 30 to 6 2 IBM PC AT and Refer to B 4 3 5 inch 2HC FD compatibles
69. P25 SIO SBO P26 SOO SB1 P27 SCKO P30 Port 3 TOO P31 8 bit input output port TO1 P32 Input output mode can be specified bit wise TO2 P33 If used as an input port an on chip pull up resistor can be used by software TH P34 TI2 P35 PCL P36 BUZ P37 P40 to P47 Port 4 ADO to AD7 8 bit input output port Input output mode can be specified in 8 bit units If used as an input port an on chip pull up resistor can be used by software Test input flag KRIF is set to 1 by falling edge detection P50 to P57 Port 5 A8 to A15 8 bit input output port LED can be driven directly Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software 126 CHAPTER 6 PORT FUNCTIONS Table 6 1 Port Functions uPD78058F Subseries 2 2 Function Alternate Function N ch open drain input output port 8 bit input output port On chip pull up resistor can be specified by Input output mode can be specified mask option Mask ROM version only bit wise LEDs can be driven directly If used as an input port an on chip pull up resistor can be used by software ASTB Port 7 SI2 RxD 3 bit input output port SO2 TxD Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software SCK2 ASCK P120 to P127 Port 12 RTPO to RTP7 8 bit input output port Input output mode
70. Read mode is entered 2 3 4 5 ve OH Data is output to pins DO through D7 The timing for steps 2 through 5 above is shown in Figure 26 7 Figure 26 7 PROM Read Timing AO to A16 Address Input CE Input N OE Input 3 E ON Hi Z Hi Z DOD SSS e e eem ER Data Output 546 CHAPTER 26 uPD78P058F 78P058FY 26 4 Screening of One Time PROM Versions One time PROM versions cannot be fully tested by NEC before shipment due to the structure of one time PROM Therefore after users have written data into the PROM screening should be implemented by user that is store devices at high temperature for one day as specified below and verify their contents after the devices have returned to room temperature Storage Temperature Storage Time 547 MEMO 548 CHAPTER 27 INSTRUCTION SET This chapter describes each instruction set of the uPD78058F and 78058FY Subseries as list table For details of its operation and operation code refer to the separate document 78K 0 Series USER S MANUAL Instructions U12326E 549 CHAPTER 27 INSTRUCTION SET 27 1 Legends Used in Operation List 27 1 1 Operand identifiers and description methods Operands are described in Operand column of each instruction in accordance with the description method of the instruction operand identifier refer to the assembler specifications for detail When there are two or more description methods
71. Real time Output Buffer Register Configuration Higher Lower 4 Bits 4 Bits Table 20 2 Operation in Real time Output Buffer Register Manipulation Register to be During Read Note 1 During Write Note 2 Manipulated Higher 4 Bits Lower 4 Bits Higher 4 Bits Lower 4 Bits Operating Mode Invalid RTBL 4 bits x 2 channels RTBH Invalid RTBH RTBL 8 bits x 1 channel RTBH RTBL Notes 1 Only the bits set in the real time output port mode can be read When a bit set in the port mode is read 0 is read 2 After setting data in the real time output port output data should be set in RTBL and RTBH by the time a real time output trigger is generated 473 CHAPTER 20 REAL TIME OUTPUT PORT 20 3 Real Time Output Port Control Registers The following three registers control the real time output port Port mode register 12 PM12 Real time output port mode register RTPM Real time output port control register RTPC 1 Port mode register 12 PM12 This register sets the input or output mode of port 12 pins P120 to P127 which are multiplexed with real time output pins RTPO to RTP7 To use port 12 as a real time output port the port pin that performs real time output must be set in the output mode PM12n 0 n 0 to 7 PM12 is set by using a 1 bit or 8 bit memory manipulation instruction This register is set to FFH by RESET input Figure 20 3 Port Mode Register 12 Format
72. SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Symbol 7 3 Address After Reset R W e o ee ee e m mom R W SVAM SVA Bit to be Used as Slave Address 0 Bits 0 to 7 1 Bits 1 to 7 R W INTCSIO Interrupt Source SelectionNete 2 CSIIFO is set upon termination of serial interface channel 0 transfer CSIIFO is set upon bus release detection or termination of serial interface channel 0 transfer R SCKO P27 Pin LevelNete 3 0 Low level 1 High level Caution Be sure to set bits 0 to 3 to 0 Notes 1 Bit 6 CLD is a read only bit 2 When using wake up function in the SBI mode set SIC to 0 3 When CSIEO 0 CLD becomes 0 Remark SVA_ Slave address register CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 316 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 4 Various signals Figures 16 20 to 16 25 show various signals and flag operations in SBI Table 16 3 lists various signals in SBI Figure 16 20 RELT CMDT RELD and CMDD Operations Master Slave address write to SIOO Transfer Start Instruction 5100 A SCKO SBO SB1 R A TEER RELT pum RELD y E IM CMDD N Figure 16 21 RELT and CMDD Operations Slave Write FFH to SIOO Transfer Start Instruction Transfer Start Instruction 500 deu Ss
73. Smi D gt 0 Address After Reset R W ADTC ARLD ERCE STRB BUSY1 BUSY0 FF69H 00H R WNete 1 BUSY1 BUSYO Busy Input Control Not using busy input Busy input enable active high Busy input enable active low STRB Strobe Output Control 0 Strobe output disable 1 Strobe output enable Detection of termination of automatic transmission reception This bit is set to 0 upon suspension of automatic transmission reception or when ARLD 0 During automatic transmission reception This bit is set to 1 when data is written to SIO1 ERR Error Detection of Automatic Transmit Receive Function 0 No error This bit is set to 0 when data is written to SIO1 1 Error occurred ERCE Error Check Control of Automatic Transmit Receive Function 0 Error check disable 1 Error check enable only when BUSY1 1 R W ARLD Operating Mode Selection of Automatic Transmit Receive Function 0 Single operating mode 1 Repetitive operating mode RE Receive Control of Automatic Transmit Receive Function 0 Receive disable 1 Receive enable Notes 1 Bits 3 and 4 TRF and ERR are Read Only bits 2 The end of auto transmission should be determined by TRF not CSIIF1 interrupt request flag Caution Whenan external clock input is selected with bit 1 CSIM11 of the serial operating mode register 1 CSIM1 set to 0 set STRB and BUSY1 of ADTC
74. TMS TMt 2 Count Value XW XovoXooK XN X A A A Count Start Clear Clear CR10 CR20 L E Interrupt Request Acknowledge Interrupt Request Acknowledge E lc MEN i 1 i 1 i 1 T i 1 i 1 i 1 i 1 i 1 i 1 i i 1 i i Interval Time Interval Time Interval Time Remark Interval time N 1 x t N 0000H to FFFFH Caution Even if the 16 bit timer event counter mode is used when the TM1 count value matches the CR10 value interrupt request INTTM1 is generated and the F F of 8 bit timer event counter output control circuit 1 is inverted Thus when using 8 bit timer event counter as 16 bit interval timer set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment When reading the 16 bit timer register TMS count value use the 16 bit memory manipu lation instruction 231 CHAPTER 9 8 BIT TIMER EVENT COUNTERS Table 9 9 Interval Times When 2 Channel 8 Bit Timer Event Counters TM1 and TM2 are Used as 16 Bit Timer Event Counter Minimum Interval Time Maximum Interval Time Resolution TCL12 TCL11 TCL10 TI1 input cycle 28 x TH input cycle input edge cycle TI1 input cycle 28 x TH input cycle TI1 input edge cycle 2 x 1 fx 22 x 1 fx 217 x 1 fx 218 x 1 fx 2 x 1 fx 22 x 1 fx 400 ns 800 ns 26 2 ms 52 4 ms 400 ns 800 ns 22 x 1 fx 23 x 1 fx 218 x 1 fx 219 x 1 fx 22 x 1
75. The interval is dependent only on CPU processing The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value set in ADTIO ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck Minimum n1 x 26 28 0 5 fxx fxx fsck Maximum n1 x 29 _36 _1 5 fsck Do not write ADTI during operation of automatic data transmit receive function 2 Bits 5 and 6 must be set to zero 3 If the auto send and receive data transmission interval time is controlled using ADTI busy control becomes invalid see 18 4 3 4 a Busy control option 1 fx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 fsck Serial clock frequency CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol ADTI 7 6 ADTI7 0 ADTI3 5 4 0 ADTI4 ADTI2 ADTI1 3 2 1 0 ADTI2 ADTI1 ADTIO FF6BH Data Transfer Interval Specification fxx 2 5 MHz Operation Address After Reset 00H R W R W MinimumNete 446 4 us 0 5 fscx MaximumNete 449 6 us 1 5 fsck 472 0 us 0 5 fscx 475 2 us 1 5 fsck 497 6 us 0 5 500 8 us 1 5 fsck 523 2 us 0 5 fscx 526 4 us 1 5 fsck 548 8 us 0 5 fscx 552 0 us 1 5 fsck 574 4 5 0 5 fsck 577 6 1
76. and generates voltages which are compared to analog inputs ANIO to ANI7 pins These are 8 channel analog input pins to input analog signals to undergo A D conversion to the A D converter Pins other than those selected as analog input by the A D converter input select register ADIS can be used as input output ports Cautions 1 Use ANIO to ANI7 input voltages within the specified range If a voltage higher than AVREFO or lower than AVSS is applied even if within the absolute maximum ratings the converted value of the corresponding channel becomes indeterminate and may adversely affect the converted values of other channels 2 Pins ANIO to ANI are also used as 1 0 port port 1 pins If one of pins ANIO to ANI7 is selected to perform A D conversion do not execute an input instruction for port 1 during conversion as this could lower the conversion resolution Also if a digital pulse is applied to a pin that is adjacent to a pin for which A D conversion is being performed it is possible that the A D conversion value will not be as expected due to coupling noise Therefore do no apply a pulse to a pin adjacent to a pin for which A D conversion is being performed CHAPTER 14 A D CONVERTER 7 AVnero pin This pin inputs the A D converter reference voltage It converts signals input to ANIO to ANI7 into digital signals according to the voltage applied between and AVss The current flowing in the series resistor string can
77. is set to 1 the 16 bit timer event counter mode is entered In this mode the count clock is selected with bits 0 to 3 TCL10 to TCL13 of the timer clock select register 1 TCL 1 The overflow signal of the 8 bit timer event counter 1 TM1 is used as the count clock of the 8 bit timer event counter 2 TM2 The count operation in this mode is enabled disabled with bit 0 TCE1 of TMC1 1 Interval timer operations The 8 bit timer event counters 1 and 2 operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset in the 2 channel 8 bit compare registers CR10 and CR20 To set the count value assign the higher 8 bits of the value to CR20 and the lower 8 bits of the value to CR10 For the count values interval times that can be set refer to Table 9 9 When the count value of the 8 bit timer register 1 TM1 matches the value assigned to CR10 and the count value of the 8 bit timer register 2 TM2 matches the value assigned to CR20 counting continues after the 1 and TM2 values are cleared to 0 and the interrupt request signal INTTM2 is generated For the operation timing of the interval timer refer to Figure 9 11 The count clock is selected with bits 0 to 3 TCL10 to TCL13 of the timer clock select register 1 TCL1 The overflow signal of TM1 is used as the count clock of TM2 230 CHAPTER 9 8 BIT TIMER EVENT COUNTERS Figure 9 11 Interval Timer Operation Timing tog lt a
78. mit data is an command Acknowledge signal Low level signal to be output to SBO SB1 during one clock period of SCKO after completion of serial reception Busy signal BUSY Synchronous BUSY signal Low level signal to be output to SBO SB1 following Acknowledge signal Ready signal READY High level signal to be output to SBO SB1 before serial transfer start and after completion of serial transfer Synchronous BUSY output aa BUSY SBO SB1 DO ACK BUSY gt SBO SB1 Do N 1 ACKE 1 2 ACKT set ACKD set Completion of reception BSYE 1 Serial receive disable because of process ing 1 BSYE 0 2 Execution of instruction for data write to SIOO transfer start instruction Serial receive enable 531935905 48S08Zdd 0 TANNVHO 39VJH3lNI VIHIS 91 H3ldVHO cce Table 16 3 Various Signals in SBI Mode 2 2 Output Signal Name Definition Timing Chart pr Effects on Flag Meaning of Signal Condition Synchronous clock to output address command Serial clock data ACK signal synchro SCKO 1 2 7 10 Timing of signal SCKO nous BUSY signal etc output to serial data Address command data are SB1 edo a ae bus transferred with the first eight synchronous clocks 8 bit data to be transferred SCKO 1 2 7 8 When CSIEO 1 Address in
79. port mode 0 1 Output enable 8 Bit Timer Event Counter 1 Timer Output F F Control Inverted operation disable Inverted operation enable LVR1 8 Bit Timer Event Counter 1 Timer Output F F Status Set Unchanged Timer output F F reset 0 Timer output F F set 1 Setting prohibited 8 Bit Timer Event Counter 2 Output Control Output disable port mode Output enable 8 Bit Timer Event Counter 2 Timer Output F F Control Inverted operation disable Inverted operation enable LVR2 8 Bit Timer Event Counter 2 Timer Output F F Status Set Unchanged Timer output F F reset 0 Timer output F F set 1 Setting prohibited Cautions 1 Be sure to stop the timer operation before setting TOC1 2 After data setting 0 can be read from LVS1 LVS2 LVR1 and LVR2 223 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 4 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P31 TO1 and P32 TO2 pins for timer output set PM31 PM32 and output latches of P31 and P32 to 0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 9 7 Port Mode Register 3 Format Symbol 7 6 Address After Reset R W 5 4 3 2 1 0 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W PM3n P3n Pin Input Output Mode Selection n 0 to 7 Output mode output
80. which undergo manipulation during instruction execution 5 4 1 Implied addressing Function The register which functions as an accumulator A and AX in the general register is automatically illicitly addressed Of the uPD78058F and 78058FY Subseries instruction words the following instructions employ implied addressing Register to be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values which become decimal correction targets ROR4 ROL4 A register for storage of digit data which undergoes digit rotation Operand format Because implied addressing can be automatically employed with an instruction no particular operand format is necessary Description example In the case of MULU X With an 8 bit x 8 bit multiply instruction the product of A register and X register is stored in AX In this example the A and AX registers are specified by implied addressing 116 CHAPTER 5 CPU ARCHITECTURE 5 4 2 Register addressing Function This addressing accesses a general register as an operand The general register accessed is specified by the register bank select flags RBSO and RBS1 and register specify code Rn or RPn in an instruction code Register addressing is carried out when an instruction with the following operand format is executed When an 8 bit reg
81. 0 008 Note Product of TOKYO ELETECH CORPORATION 579 MEMO 580 APPENDIX C EMBEDDED SOFTWARE This chapter describes the embedded software that is available for the wPD78058F and 78058FY Subseries to allow users to develop and maintain application programs for these subseries 581 APPENDIX C EMBEDDED SOFTWARE C 1 Real time OS 1 2 RX78K 0 RX78K 0 is real time OS conforming to uITRON specifications Real time OS Tool configurator that generates nucleus of RX78K 0 and plural information tables is supplied Used in combination with an optional assembler package RA78K 0 and device file DF78054 Precautions when using RX78K 0 under PC environment RX78K 0 is a DOS based application Therefore run the RX78K 0 from the DOS prompt under Windows Part number uSxxxxRX78013 AA AA Caution When purchasing the RX78K 0 fill an application form and conclude the contract for use permission in advance Remark The part numbers xxxx and AAAA differ depending on the host machine and OS used RX78013 A Product Outline Upper Limit of Quantity for Mass Production Evaluation object Do not use for mass produced product Object for mass 0 1 million produced product 1 million 10 million Source program Source program for mass produced object Host Machine Supply Media PC 9800 Series Windows Japanese 5 3 5 inch 2HD FD IBM PC AT and Windows
82. 0 5 fsck 173 6 us 1 5 fsck 184 8 us 0 5 fsck 186 4 us 1 5 fsck 197 6 us 0 5 fsck 199 2 us 1 5 fsck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 210 4 us 0 5 fsck 212 0 us 1 5 fsck Notes 1 Cautions Remarks The interval is dependent only on CPU processing The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value set in ADTIO ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 the minimum interval time is 2 fsck Minimum n 1 x 25 28_ 0 5 Maximum n 1 x 28 4 36 1 5 fxx fxx fsck fxx fxx fsck 1 Do not write ADTI during operation of automatic data transmit receive function 2 Zero must be set in bits 5 and 6 3 If the auto send and receive data transmission interval time is controlled using ADTI busy control becomes invalid see 18 4 3 4 a Busy control option 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 fsck Serial clock frequency CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol ADTI 7 6 5 4 3 2 ADTI7 0 0 1 0 ADTIA ADTIS ADTI2 ADTI1T ADTIO FF6BH Data Transfer Interval Specification fxx 5 0 MHz Operation Address After Reset 00H R W R W ADTI3 ADTI2 ADTI1 MinimumNete 223 2 us O 5 fsck Maxim
83. 0 at the falling edge of SCKO 319 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES Figure 16 24 ACKD Operations a When ACK signal is output at 9th clock of SCKO Transfer Start Instruction 5100 QD Transfer Start SCKO 0 SB1 ACKD b When ACK signal is output after 9th clock of SCKO Transfer Start 5 Instruction soo Transfer Start SCKO 6 7 8 9 seo ssi 7 ACKD c Clear timing when transfer start is instructed in BUSY Transfer Start Instruction seo se Co Jor 7 Vr ACKD 7 Figure 16 25 BSYE Operation SCKO 6 7 8 9 SBO SB1 02 X D X Do ACK BUSY A When BSYE 1 at this point ao If reset during this period and BSYE 0 at the falling edge of SCKO 320 Lee Signal Name Bus release signal REL Output Device Definition SBO SB1 rising edge when SCKO 1 Table 16 3 Various Signals in SBI Mode 1 2 Timing Chart SCKO 0 81 Output Condition RELT set Effects on Flag RELD set CMDD clear Meaning of Signal CMD signal is output to indicate that transmit data is an address Command signal CMD Master SBO SB1 falling edge when SCKO 1 SCKO SBO 5 1 CMDT set CMDD set i Transmit data is an address after REL signal output ii REL signal is not output and trans
84. 00H R W TOEO 16 Bit Timer Event Counter Output Control Output disabled Port mode Output enabled In PWM Mode In Other Modes Timer output F F control Active level selection by match of CROO and TMO Active high Inversion operation disabled Active low Inversion operation enabled 16 Bit Timer Event Counter Timer Output F F Status Setting No change Timer output F F reset 0 Timer output F F set 1 Setting prohibited Inversion operation disabled TOCO4 Timer output F F control by match of CRO1 and 0 1 Inversion operation enabled OSPE One Shot Pulse Output Control 0 1 Continuous pulse output One shot pulse output One shot pulse trigger not used OSPT Control of One Shot Pulse Output Trigger by Software 0 1 One shot pulse trigger used Cautions 1 Timer operation must be stopped before setting TOCO except for OSPT 2 If LVSO and LVRO are read after data is set they will be 0 3 OSPT is cleared automatically after data setting and will therefore be 0 if read 183 CHAPTER 8 16 TIMER EVENT COUNTER 5 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P30 TOO pin for timer output set PM30 and output latch of P30 to 0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 value to FFH Figure 8 7 Port Mode Register 3 Forma
85. 1 kHz 39 1 kHz fxx 27 fx 27 39 1 kHz 19 5 kHz IN A A O fxx 28 fx 28 19 5 kHz 9 8 kHz fxx 29 fx 29 9 8 kHz E 4 9 kHz Other than above Setting prohibited Caution If data is written to BRGC during the communication operation the baud rate generator output is disrupted and communication cannot be performed normally Therefore do not write data to BRGC during a communication operation Remarks 1 fx Main system clock oscillation frequency 2 fxx Main system clock frequency fx or fx 2 3 MCS Bit 0 of oscillation mode selection register OSMS 4 n Value set in TPSO to TPS3 1 lt lt 11 5 Figures in parentheses apply to operation with fx 5 0 MHz 443 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit receive clock generated is either a signal scaled from the main system clock or a signal scaled from the clock input from the ASCK pin a Generation of baud rate transmit receive clock by means of main system clock The transmit receive clocks generated by scaling the main system clock The baud rate generated from the main system clock is found from the following expression fxx Baud rate Hz 21 x k 16 where fx Main system clock oscillation frequency fxx Main system clock frequency fx or fx 2 n Value set in TPSO to TPS3 1 lt lt 11 k Value set in MDLO to MDL
86. 2 Lu PC574J 8 2 kQ us 191 CHAPTER 8 16 TIMER EVENT COUNTER 8 5 3 PPG output operations Setting the 16 bit timer mode control register and capture compare control register 0 CRCO as shown in Figure 8 16 allows operation as PPG Programmable Pulse Generator output In the PPG output operation square waves are output from the pin with the pulse width and the cycle that correspond to the count values set beforehand in 16 bit capture compare register 01 CRO1 and in 16 bit capture compare register 00 CROO respectively Figure 8 16 Control Register Settings for PPG Output Operation a 16 bit timer mode control register TMCO TMC03 TMC02 TMC01 OVFO o EE CRGA ECT Clear amp start on match of TMO and CROO b Capture compare control register 0 CRCO CRCO2 CRCO1 CRCO00 CROO set as compare register CR01 set as compare register c 16 bit timer output control register TOCO OSPT OSPE TOC04 LVSO LVRO TOCO1 TOEO TOO Output Enabled Inversion of output on match of TMO and CROO Specified TOO output F F initial value Inversion of output on match of TMO and CRO1 One shot pulse output disabled Remark x Don t care Caution Values in the following range should be set in CROO and CRO01 0000H lt CRO1 lt CROO lt FFFFH 192 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 5 4 Pulse width measureme
87. 2 Mask Options of Mask ROM Versions c cesceeeseeeeeeeeeeceeeeeseeeeeecaeeseeeeeneeseaeseaeeseaeesaeeseaeeseeeeeaeeees 58 3 1 Pin Inp t Output Circuit TVDes dr GHI 73 4 1 Pin Input Output Circuit Types c rtp de nente die Br re Ee debug 91 5 1 Mectot REDDERE A Ld A D abe E oe eda 98 5 2 Corresponding of General Register Absolute Address ccccceesseeeeeeeeseeeeeeeeeseneeeeseeeeeseneeessaes 106 5 3 Special Function Register List 109 6 1 Port Functions uPD78058F Subseries essent nnnm nennen 126 6 2 Port Functions uPD78058FY Subseries ssssssssssseeeeeeneenenen nennen 128 6 3 Port Contigurations d eb Gem 130 6 4 Pull up Resistor of Port 6 oce e t t e dren ese EE a Due x a n LX RR ends 140 6 5 Port Mode Register and Output Latch Settings When Using Alternate Functions 147 6 6 Comparison Between Mask ROM Version and PROM Version 153 7 1 Clock Generator Configuration esessessssseseseeeeeeeeeenene nnne nennen 155 7 2 Relationship Between CPU Clock and Minimum Instruction Execution Time 159 7 8 Maximum Time Required for CPU Clock Switchover seen 168 8 1 Timer Event Counter
88. 216 x 1 fx 13 1 ms 217 x 1 fx 26 2 ms 217 x 1 fxx 6 55 ms 217 x 1 fx 26 2 ms 218 x 1 fx 52 4 ms 219 x 1 fxx Remarks 1 fxx 2 fx Main system clock oscillation frequency 219 x 1 fx 104 9 ms Main system clock frequency fx or fx 2 220 x 1 fx 209 7 ms 3 MCS Bit 0 of oscillation mode selection register OSMS 4 TCL20 to TCL22 Bits 0 to 2 of timer clock select register 2 TCL2 5 Figures in parentheses apply to operation with fx 5 0 MHz 252 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12 1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI Clocks selected with the timer clock select register 0 TCLO are output from the PCL P35 pin Follow the procedure below to output clock pulses 1 Select the clock pulse output frequency with clock pulse output disabled with bits 0 to TCLOO to TCLO3 of TCLO 2 Set the P35 output latch to 0 3 Set bit 5 PM35 of port mode register 3 to 0 set to output mode 4 Set bit 7 CLOE of TCL 0 to 1 Caution Clock output cannot be used when setting P35 output latch to 1 Remark When clock output enable disable is switched the clock output control circuit does not output pulses with narrow width See the port
89. 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition when CMDD 1 matches the slave address register SVA data in I C bus mode Serial Interface Channel 0 Operation Control Operation stopped Operation enabled Notes 1 Bit 6 COI is a read only bit 2 Can be used as P25 CMOS input output when used only for transmission 3 Be sure to set WUP to 0 when the 3 wire serial I O mode is selected Remark x don t care Port Mode Register PXX Port Output Latch 354 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES b Serial bus interface control register SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H symbol gt O Address After Reset R W SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R W R W When RELT 1 500 latch is set to 1 After 500 latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 R W When 1 SOO latch is cleared to 0 After 500 latch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 355 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 2 Communication operation The 3 wire serial I O mode is used for data transmission rec
90. 387 18 1 Serial Interface Channel 1 387 18 2 Serial Interface Channel 1 Configuration esent 388 18 3 Serial Interface Channel 1 Control ene 391 18 4 Serial Interface Channel 1 Operations eese eene nennen nennt nnne 399 18 4 1 Operation stop mode eni edi feeds ce LL etre Ce eoe Ed eee 399 18 4 2 3 wire serial I O mode operation sess 400 18 4 3 3 wire serial I O mode operation with automatic transmit receive function 403 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 433 19 1 Serial Interface Channel 2 Functions eeeeeeeesesseseeeene eee nennen nnn annt nn nnn 433 19 2 Serial Interface Channel 2 Configuration esses eeeenenen nnne 434 19 3 Serial Interface Channel 2 Control 438 19 4 Serial Interface Channel 2 Operation ennt ennt 446 19 4 1 Operation stop mode cei eee dE dec oc LEE Ode dea de Eee 446 19 4 2 Asynchronous serial interface UART mode seem 448 19 4 3 3 wire serial V O mode date ets see e ERE T 461 19 4 4 Restrictions on using UART mode
91. 475 21 1 Basic Configuration of Interrupt Function essssessseeeeeeenenneee nennen nennen 480 21 2 Interrupt Request Flag Register Format sesseeeneennenn emere nennen 483 21 3 Interrupt Mask Flag Register Format escceeeseeeeeseeeeeeneeeeseeeseneeeeeaeeeeeaaeesesaeeessaeeeenaeeeeeeeeseeees 484 21 4 Priority Specify Flag Register Format sese enne nennen nnne nnne nnns 485 21 5 External Interrupt Mode Register 0 Format sessssseeeeeenneem eene nre 486 21 6 External Interrupt Mode Register 1 Format sesessseneemeem eene 487 21 7 Sampling Clock Select Register Format essssssssseeeeeeneennee nennen nennen 488 21 8 Noise Elimination Circuit Input Output Timing During Rising Edge Detection 489 21 9 Program Status Word Format EP REPRE LR POUR DER ARI REE 490 21 10 Flowchart from the Time a Non maskable Interrupt Request Is Generated Until It Is Received 492 21 11 Non Maskable Interrupt Request Acknowledge Timing 492 21 12 Non Maskable Interrupt Request Acknowledge Operation een 493 21 13 Interrupt Request Acknowledge Processing Algorithm 495 21 14 Interrupt Request Acknowledge Timing Minimum Time m 496 21 15 Interrupt Request Acknowledge Timing Maximum Time e
92. 5 4 3 2 1 0 ae e Overrun error generatedNote 1 When next receive operation is completed before data from receive buffer register is read Framing error not generated Framing error generatedNote 2 When stop bit is not detected Parity error not generated Parity error generated When transmit data parity does not match Notes 1 The receive buffer register RXB must be read when an overrun error is generated Overrun errors will continue to be generated until RXB is read 2 Even if the stop bit length has been set as 2 bits by bit 2 SL of the asynchronous serial interface mode register ASIM only single stop bit detection is performed during reception 450 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 d Baud rate generator control register BRGC BRGC is set with an 8 bit memory manipulation instruction RESET input sets BRGC to 00H Symbol 7 6 5 4 3 Address After Reset R W 2 1 0 BRGC TPS3 TPS2 TPS1 TPSO MDL3 MDL2 MDL1 MDLO FF73H 00H R W MDLO Baud Rate Generator Input Clock Selection k 16 fsck 17 fsck 18 fsck 19 fsck 20 fsck 21 fsck 22 fsck 23 fsck 24 fsck 25 fsck 26 fsck 27 fsck 28 fsck 29 fsck 30 continued fsck 5 bit counter source clock k Value set in MDLO to MDL3 0 lt k x 14 451 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 5 Bit Counter Source Clock Selection M
93. 5 fsck 600 005 0 5 fscx 603 2us 1 5 fsck O o o o o o oo 625 6 us 0 5 fsck 628 8 us 1 5 fsck 651 2 us 0 5 fscx 654 4us 1 5 fsck 676 8 us 0 5 fscx 680 0 us 1 5 fsck 702 4 us 0 5 fsck 705 6 us 1 5 fsck 728 0 us 0 5 fscx 731 2us 1 5 fsck 753 6 us 0 5 756 8 us 1 5 fsck 779 2 5 0 5 fsck 782 4 5 1 5 fsck 804 8 us 0 5 fsck 808 0 us 1 5 fsck 830 4uUs 0 5 833 6 us 1 5 fsck The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value setin ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck Minimum n1 x 26 0 28 54 70 5 fxx fxx fsck Maximum n1 x 26 _ 36 s dub fxx fxx fsck Cautions 1 Do not write ADTI during operation of automatic data transmit receive function 2 Bits 5 and 6 must be set to zero 3 If the auto send and receive data transmission interval time is controlled using ADTI busy control becomes invalid see 18 4 3 4 a Busy control option Remarks 1 fxx 2 fx 3 fsck Main system clock frequency fx or fx 2 Main system clock oscillation frequency Serial clock frequency 409 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 2 Automatic transmit receive data setting a Transmit data
94. 5100 in the IC bus mode while WUP bit 5 of the serial operating mode register 0 CSIMO 1 Even if such an instruction is not executed data can be received when the wake up function is used WUP 1 For the detail of the wake up function refer to 17 4 4 1 c Wake up function Slave address register SVA This is an 8 bit register to set the slave address value for connection of a slave device to the serial bus This register is not used in the 3 wire serial I O mode SVA is set with an 8 bit memory manipulation instruction The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the slave address output from the master device and the SVA value are compared with an address comparator If they match the slave device has been selected In that case bit 6 of serial operating mode register 0 CSIMO becomes 1 Also by setting bit 4 SVAM of the interrupt timing instruction register SINT at 1 the address can be compared with the higher order 7 bits with the LSB being masked If a match is not detected during address reception bit 2 RELD of the serial bus interface control register SBIC is cleared to 0 Furthermore when in the I2C bus mode the wake up function can be used by setting bit 5 WUP of CSIMO at 1 In this case the interrupt request signal INTCSIO is generated when the slave address output by the master coincides with the value of
95. ALY 117 54 3 Direct addressitng uon iter thee rh Cede nit das 118 5 4 4 Short direct addressing nee teen te jene ek n cha dte co ro oarak Sa e Rn Ves 119 5 4 5 Special Function Register SFR addressing sees 121 5 4 6 Register indirect addressing cceescceeeeeceeeeeeeeeeeeeeeeeeeenseenenesancenenenensaeenesasensseneneeseeneseeeeneses 122 54 7 Based addressing e i ek Lt HE wi ade dh ied a reir a ee DRE 123 5 4 8 Based indexed addressing teen ace o dee ire t epe De ce E Pre 124 5 4 9 Stack addressing scie LR oe ee ean i eee ee LEUTE 124 CHAPTER 6 PORT FUNCTIONS 5 2 cipe treni eee cere anc es aede ceu 125 6 1 Port F nctlons 2 2 125 6 2 Configuration 1 ceca ces enap eaea aaa scat ssecsnecnceresecedecgetsastuesseecderssactiancteeced 130 6 241 aU te ed aS ae uet on er 130 62 2 Port A es tented pe Net den up reb ee Se 132 6 2 3 Port 2 uPD78058F S bserles atre te cte ie p re F r re n Res 133 6 2 4 Port2 uPD78058FY Subseries 1 em ue RO RUE aaa a EQ 135 6 2 5 POP 82e pem ret ate m te fer te rp e a i eae as 137 EJ EE 138 6 257 cr aii Pl eel een id eee eve eerie 139 6 2 9 SPOFUO 5 ceci ence onte been temet 140 6 2 9 POI a o o
96. BUSYO 1 Active Low CHAPTER 18 SERIAL INTERFACE CHANNEL 1 SCK1 SO A S BUSY CSIIF1 TRF Furthermore in the case that the busy control option is used select the internal clock for the serial clock The busy signal cannot be controlled with an external clock The operation timing when the busy control option is used is shown in Figure 18 19 Caution Busy control cannot be used at the same time as interval timing control using the auto data send and receive interval instruction register ADIT If both are used simultane ously busy control becomes invalid Figure 18 19 Operation Timings When Using Busy Control Option BUSYO 0 EC CJED CO CO ED CONNU NES C2 C2 C2 CO CD C CORN 1 1 Oe 63 C2 C9 C2 CD COPIA zu Busy Input Release Busy Input Valid Caution When TRF is cleared the SO1 pin becomes low level Remark CSIIF1 Interrupt request flag TRF Bit 3 of the auto data send and receive control register ADTC If the busy signal becomes inactive the wait is canceled If the sampled busy signal is inactive sending or receiving of the next 8 bit data begins from the fall of the next serial clock cycle Furthermore the busy signal is asynchronous with the serial clock so even if the slave side inactivates the busy signal it takes nearly 1 clock cycle at the most until it is sampled again Also it takes another 0 5 cloc
97. Basic configuration types A to E correspond to A to E of Figure 21 1 479 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 1 Basic Configuration of Interrupt Function 1 2 A Internal non maskable interrupt Internal Bus Vector Table Interrupt Priority Control Address Request Circuit Generator Standby Release Signal gt B Internal maskable interrupt Internal Bus ee ee Vector Table Address Generator Priority Control Interrupt Circuit Request Standby Release Signal C External maskable interrupt INTPO Internal Bus Sampling Clock Select Register SCS External Interrupt Mode Register INTMO Vector Table Priority Control Interrupt Sampling Edge Circuit Andes Request Clock Detector enerator Standby Release Signal 480 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 1 Basic Configuration of Interrupt Function 2 2 D External maskable interrupt except INTPO Internal Bus Y E NE External Interrupt Mode Register INTMO INTM1 Vector Table Edge Address Generator E Standby Release Signal Interrupt Request E Software interrupt Internal Bus Interrupt Priority Control acor Pendent ae Generator Remark IF Interrupt request flag IE Interrupt enable flag ISP Inservice priority
98. Bit 0 of oscillation mode selection register OSMS 4 n Value set in TPSO to TPS3 1 nx 11 5 Figures in parentheses apply to operation with fx 5 0 MHz 464 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 When the internal clock is used as the serial clock in the 3 wire serial I O mode set BRGC as described below BRGC setting is not required if an external serial clock is used i When the baud rate generator is not used Select a serial clock frequency with TPSO to TPS3 Be sure then to set MDLO to MDL3 to 1 1 1 1 The serial clock frequency is 1 2 the source clock frequency of the 5 bit counter ii When the baud rate generator is used Select a serial clock frequency with TPSO to TPS3 Be sure then to set MDLO to MDL3 to 1 1 1 1 The serial clock frequency is calculated by the following formula fxx Serial clock frequency quenter ea t d Remarks 1 fx Main system clock oscillation frequency 2 Main system clock frequency fx or fx 2 3 n Value set in TPSO to TPS3 1 lt n lt 11 4 k Value set in MDLO to MDL3 Ox k x 14 465 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 2 Communication operation SCK2 512 502 SRIF 466 In the 3 wire serial I O mode data transmission reception is performed in 8 bit units Data is transmitted received bit by bit in synchronization with the serial clock Transmit shift register TXS SIO2 and receive shift register RXS shift
99. Bits 0 to 7 1 Bits 1 to 7 E INTCSIO Interrupt Source SelectionNete 2 CSIIFO is set upon termination of serial interface channel 0 transfer R W CSIIFO is set upon bus release detection or termination of serial interface channel 0 transfer 27 Pin LevelNetes 0 Low level 1 High level Caution Be sure to set bits 0 to 3 to 0 Notes 1 Bit 6 CLD is a read only bit 2 When using wake up function in the SBI mode set SIC to 0 3 When CSIEO 0 CLD becomes 0 Remark SVA Slave address register CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 298 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 16 4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0 Operation stop mode 3 wire serial I O mode SBI mode 2 wire serial I O mode 16 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power consumption can be reduced The serial I O shift register 0 SIOO does not carry out shift operation either and thus it can be used as ordinary 8 bit register In the operation stop mode the P25 SIO SBO P26 SO0 SB1 and P27 SCKO pins can be used as ordinary input output ports 1 Register setting The operation stop mode is set with serial operating mode register 0 CSIMO CSIMO is set with a 1
100. COI becomes 0 Penns Remark x don t care PMXX Port Mode Register PXX Port Output Latch 348 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 3 Serial bus interface control register SBIC This register sets serial bus interface operation and displays statuses SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H Figure 17 5 Serial Bus Interface Control Register Format 1 2 Smo gt Address After Reset R W SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R W Used for stop condition signal output When RELT 1 SOO latch is set to 1 After SOO latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 R W Used for start condition signal output When CMDT 1 SOO latch is cleared to 0 After SOO latch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 R RELD Stop Condition Detection Clear Conditions RELD 0 Set Conditions RELD 1 When transfer start instruction is executed When stop condition signal is detected If SIOO and SVA values do not match in address reception When CSIEO 0 When RESET input is applied CMDD Start Condition Detection Clear Conditions CMDD 0 Set Conditions CMDD 1 When transfer start instruction is executed When start condition signal is detected When stop condition signal is detected When CSIEO 0
101. CRCO00 Ts T9 T9 T5 1 CROO set as compare register CR01 set as capture register Remark 0 1 Setting O or 1 allows another function to be used simultaneously with pulse width measure ment See the description of the respective control registers for details 193 CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 18 Configuration Diagram for Pulse Width Measurement by Free Running Counter 16 Bit Timer Register TMO OVFO 16 Bit Capture Compare Register 01 CRO1 INTTM3 2fxx fxx fxx 2 Selector fxx 2 TIOO POO INTPOO gt INTPO Internal Bus Figure 8 19 Timing of Pulse Width Measurement Operation by Free Running Counter and One Capture Register with Both Edges Specified gt TIOO Pin Input I CRO1 Captured Value Satie Y ps INTPO dul sd se css _ OVFO 194 CHAPTER 8 16 TIMER EVENT COUNTER 2 Measurement of two pulse widths with free running counter When the 16 bit timer register TMO is operated in free running mode see register settings in Figure 8 20 it is possible to simultaneously measure the pulse widths of the two signals input to the TIOO POO pin and the TIO1 PO1 pin When the edge specified by bits 2 and ES10 and ES11 of external interrupt mode register 0 INTMO is input to the TIOO POO pin the value of is taken into 16 bit capture compare register 01 CRO1 and an external interr
102. CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H 403 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol 5 Address After Reset R W com aeon Dee e e Serial Interface Channel 1 Clock Selection Clock externally input to SCK1 pinNete 1 8 bit timer register 2 TM2 output Clock specified with bits 4 to 7 of timer clock select register 3 TCL3 Serial Interface Channel 1 Operating Mode Selection 3 wired serial I O mode 3 wired serial I O mode with automatic transmit receive function SI1 Pin Function 801 Pin Function 511 20 Input un Note 2 x Note 2 Note 2 Note 2 Note 2 x x x x T Shift Register 1 Operation Operation stop Serial Clock Counter Operation Control SI1 P20 Pin Function P20 CMOS input output SO1 P21 Pin Function P21 CMOS input output SCK1 P22 Pin Function P22 CMOS input output Operation enable Count operation SI1 Note 3 Input SO1 CMOS output SCK1 Input Note 3 Note 3 1 x SCK1 CMOS output If the external clock input has been selected with CSIM11 set to 0 set bit 1 BUSY 1 and bit 2 STRB of the automatic data transmit receive control register ADTC to 0 0 2 Can be used freely as port function 3 Can be used as P20 CMOS input output when only transmitter is us
103. Clock Wait 3 3 c Stop Condition Master Device Operation Write sioo 9 00c Pata SIO Address col XXX XOX XO XXX ACKD To RELD L 27 H WUP L Bsye LL _ LLL Al RELT WEE E 7 a c y SIC INTCSIO SCL 2 lal 4 SDAO 07 XD6XD5XD4XD3XD2XD1 ADONI mane Write SIOO see col Oooo 109000 ACKD CMDD Es RELD 27 wur Eu eve H i ACKE B CMDT RELT L INN WREL L p SIC H INTCSIO CSIEO PM25 MEM EM PM27 Lo pe r 376 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Figure 17 23 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait 1 3 a Start Condition to Address Master Device Operation Write SIOO 100 lt Address SIO0 FFH col XXX XX XX XX XX ACKD CMDD TTC RELD L as CLD P27 H COMEE re BSYE ERE ACKE CMDT RELT CLC WREL LI SIC INTCSIO SCL 1 lal B 5 SDAO AN 07 AD6 XD5XD4XD3 Write SIOO GSE Oe e 07 ee ACKD en CLD P27 WUP 1 13 J y rc FARE 5100 lt Data CMDT RELT CLC WREL SIC INTCSIO CSIEO P25 PM25 PM27 rj ir r r 377 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Figure 17 23 Data
104. Correction Functions 527 25 2 ROM Correction Configuration eeeeeeeeeeseieeeeeeeeee seen nnne etna nnn rnnt sinn nnmnnn 527 25 3 ROM Correction Control Registers essen nenne seen nennt nennen nnn 529 25 4 ROM Correction 530 25 5 HOM Correction Example 533 25 6 Program Execution Flow eeeeeeeeeeeeeeee nennen nnne nennen nennen nennen nan nent nnne nnn 534 25 7 Cautions ROM Correction 536 CHAPTER 26 uPD78PO58F 78P058FY 537 26 4 Memory Size Switching Register eese sienne enne nnne nnn nnn 538 26 2 Internal Expansion RAM Size Switching Register eese 539 26 3 PROM Programming eeseeeseeeeeeeeees seen n enne nn snnt nnn nn nnns stis n ase tR nda sa sss etn nanne isse nnn nn saa 540 26 3 1 Operating modes niece cei ie rd e tee ni ede epe vd er Ue uod e ade dg et vu 540 26 3 2 PROMiwrite procedure e cnet e tn pc detis anode 542 21 26 3 83 PROM read procedure sec eet eis lees 546 26 4 Screening of One Time PROM Versions
105. D A Converter Config ration eio pacato eto a ceno V Le 280 16 1 Differences Among Channels 0 1 and 2 ssessssssssssssssssseeeeeeeee nennen 285 16 2 Serial Interface Channel 0 Configuration sessseeeeeeeeeeennen nennen enne 288 16 3 Various Signals in SBI nter nnn nnne nennt inna 321 17 1 Differences Among Channels 0 1 and 2 337 17 2 Serial Interface Channel 0 Configuration sessseseeeeeeeeenennen nennen nennen nennen 340 17 3 Serial Interface Channel 0 Interrupt Request Signal 344 17 4 Signals 11 126 Bus Mode nig aeneo RR OH indi 371 18 1 Serial Interface Channel 1 Configuration esseseseeeeeeeeneneen nennen nennen 388 18 2 Interval Timing Through CPU Processing When the Internal Clock Is Operating 430 18 3 Interval Timing Through CPU Processing When the External Clock Is Operating 431 19 1 Serial Interface Channel 2 Configuration esssssseeeeeneneneen nennen 434 19 2 Serial Interface Channel 2 Operating Mode Settings 440 19 3 Relationship Between Main System Clock and Baud Rate 444 1
106. DE RD ai RR REIR ERA 192 8 5 4 Pulse width measurement operations 193 8 5 5 External event counter operation 200 8 5 6 Square wave output operation ssssssssesseeeneee nennen nennen nennen enne nennen nnns 202 8 5 7 pulse output operation sssssssssesseeeeneeenee nne nennen nnns 204 8 6 16 Bit Timer Event Counter Operating Precautions seen 208 CHAPTER 9 8 BIT TIMER EVENT COUNTERS en nnne nnn nn nnne nnn nnn nnne 211 9 1 8 Bit Timer Event Counter Function 211 9 1 1 8 bit timer event counter mode eeeesssseseseseeeieeee 211 9 1 2 16 bit timer event counter mode sninen aaa re Pet usua itg ne 214 9 2 8 Bit Timer Event Counter Configuration eese eintreten 216 9 3 8 Bit Timer Event Counter Control Registers eres eren 220 9 4 8 Bit Timer Event Counter Operation eeseeeseeeeee esses eenne nennen nennt nnn santet 225 9 4 1 8 bit timer event counter mode tenente nenne 225 9 4 2 16 bit timer event counter 230 9 5 Cautions 8 Bit Timer Event C
107. FF1FH respectively The SFR area FFOOH through FF1FH to which short direct addressing is applied is a part of the entire SFR area To this area ports frequently accessed by the program and the compare registers and capture registers of timer event counters are mapped These SFRs can be manipulated with a short byte length and a few clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at OOH to 1FH bit 8 is set to 1 Refer to Illustration on next page Operand format ent saddr Label of FE20H to FF1FH immediate data saddrp Label of FE20H to FF1FH immediate data even address only 119 CHAPTER 5 CPU ARCHITECTURE Description example MOV OFE30H 50H when setting saddr to FE30H and immediate data to 50H Operation code 00010001 OP code 00110000 30H saddr offset 01 010000 50H immediate data Illustration OP code saddr offset Short Direct Memory Effective Address When 8 bit immediate data is 20H to FFH a 0 When 8 bit immediate data is to 1FH 1 120 CHAPTER 5 CPU ARCHITECTURE 5 4 5 Special Function Register SFR addressing Function The memory mapped special function register SFR is addressed with 8 bit immediate data in an instruction word This addressing is applied to the 240 byte spaces FFOOH to FFCFH and FFEOH to FFFFH However the SFR mapped at FFOOH to FF1FH can be accessed with s
108. Figure 8 37 Capture Register Data Retention Timing AEA Naf ey N ee TMO Count Value Ne wo XY X m 2 Edge Input Interrupt Request Flag Capture Read Signal N Capture Operation Ignored 5 Valid edge setting Set the valid edge of the TIO0 POO INTPO pin after setting bits 1 to 3 TMC01 to TMCO3 of the 16 bit timer mode control register TMCO to 0 0 0 respectively and then stopping timer operation Valid edge setting is carried out with bits 2 and 3 ES10 and ES1 1 of external interrupt mode register 0 INTMO 6 Re trigger of one shot pulse a One shot pulse output using software When outputting one shot pulse do not set bit 6 OSPT of the 16 bit timer output control register TOCO When outputting one shot pulse again wait for interrupt INTTMOO which coincides with CROO to be generated first b One shot pulse output using external trigger When outputting one shot pulses external trigger is ignored if generated again 209 CHAPTER 8 16 TIMER EVENT COUNTER 7 Operation of OVFO flag OF VO flag is set to 1 in the following case The clear amp start mode on match between TMO and CROO is selected CROO is set to FFFFH l When TMO is counted up from FFFFH to 0000H Figure 8 38 Operation Timing of OVFO Flag Count Pulse CROO FFFFH wmm Xem y mm OVFO INTTMOO 210 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 9 1 8 Bit Timer Event Counter
109. Function The on chip 8 bit timer event counters of the uPD78058F 78058FY Subseries have two modes a mode in which the two 8 bit timer event counter channels are separately used 8 bit timer event counter mode and a mode in which the two 8 bit timer event counter channels are used combined as a 16 bit timer event counter 16 bit timer event counter mode 9 1 1 8 bit timer event counter mode The 8 bit timer event counters 1 and 2 TM1 and TM2 have the following functions nterval timer External event counter Square wave output 211 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 8 bit interval timer Interrupt requests are generated at the preset time intervals Table 9 1 8 Bit Timer Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS 1 MCS 0 MCS 1 MCS 0 2 x 1 fx 22 x 1 fx 29 x 1 fx 210 x 4 fx 2 x 1 fx 2 x 1 fx 400 ns 800 ns 102 4 us 204 8 us 400 ns 800 ns 22 x 1 fx 23 x 1 fx 210 x 1 fx 211 x 1 fx 2 x 1 fx 23 x 1 fx 800 ns 1 6 us 204 8 us 409 6 us 800 ns 1 6 us 23 x 1 fx 24 x 1 fx 211 x 1 fx 212 x 1 fx 23 x 1 fx 24 x 1 fx 1 6 us 3 2 us 409 6 us 819 2 us 1 6 us 3 2 us 24 x 1 fx 25 x 1 fx 212 x 1 fx 213 x 1 fx 24 x 1 fx 25 x 1 fx 3 2 us 6 4 us 819 2 us 1 64 ms 3 2 us 6 4 us 25 x 1 fx 26 x 1 fx 213 x 1 fx 214 x 1 fx 25 x 1 fx 26 x 1 fx 6 4 us 12 8 us 1 64 ms 3 28 ms 6 4 us 12 8 us 26 x 1 fx 27 x 1 fx 214 x 1 fx 215 x 1 fx 26
110. Hi Z ADOtoAD7 X owerAddes y ccc ccn Herrn lt Write Data Xe A8 to A15 X Higher Address X WAIT a 513 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ASTB RD WR ADO to AD7 A8 to A15 ASTB RD WR ADO to AD7 A8 to A15 Internal Wait Signal 1 clock wait ASTB RD WR ADO to AD7 A8 to A15 WAIT 514 Figure 22 7 External Memory Read Modify Write Timing a No wait PW1 PWO 0 0 setting S S E A Ml Fe EET IM Lower Address Read Data Write Data Higher Address b Wait PW1 PWO 0 1 setting Read Data Hig Write Data Higher Address c External wait PW1 PWO 1 1 setting N na 7 es Cc X Lower Address XK Read Data E 5 Write Data X X Higher Address X IEEE EST CHAPTER 23 STANDBY FUNCTION 23 1 Standby Function and Configuration 23 1 1 Standby function The standby function is designed to decrease power consumption of the system The following two modes are available 1 2 HALT mode HALT instruction execution sets the HALT mode The HALT mode is intended to stop the CPU operation clock System clock oscillator continues oscillation In this mode current consumption cannot be decreased as in the STOP mode The HALT mode is valid to restart immediately upon interrupt request and to carry out intermittent operations such as in watch applications STOP mode STOP instruction execution sets the STOP mode In t
111. IFOH IF1L The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input IFOL IFOH and IF1L are set with a 1 bit or 8 bit memory manipulation instruction If IFOL and IFOH are used as a 16 bit register IFO use a 16 bit memory manipulation instruction for the setting RESET input sets these registers to 00H Figure 21 2 Interrupt Request Flag Register Format symbol G Q Mie Wa o qoc 6 5 4 3 o Interrupt Request Flag No interrupt request signal Interrupt request signal is generated Interrupt request state Note WTIF is test input flag Vectored interrupt request is not generated Cautions 1 TMIF4 flag is R W enabled only when a watchdog timer is used as an interval timer If a watchdog timer is used in watchdog timer mode 1 set TMIFA flag to O 2 Set always 0 in IF1L bits 3 to 6 483 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 2 Interrupt mask flag registers MKOL MKOH MK1L The interrupt mask flag is used to enable disable the corresponding maskable interrupt service and to set standby clear enable disable MKOL MKOH and MK1L are set with a 1 bit or 8 bit memory manipulation instruction If MKOL and MKOH are used as a 16 bit register MKO use a 16 b
112. INTERFACE 2 A D CONVERTER D A CONVERTER INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT CONTROL 78K 0 CPU CORE ROM RAM Voo Vss AVoo AVss IC VeP PORT 0 PORT 1 PORT2 PORT PORT 4 PORT 5 PORT 6 PORT 7 PORT 12 PORT 13 REAL TIME OUTPUT PORT 9 EXTERNAL ACCESS SYSTEM CONTROL Remarks 1 The internal ROM and RAM capacities depend on the product 2 Pin connection in parentheses is intended for the uPD78P058FY P01 to P06 P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 P130 P131 RTPO P120 to RTP7 P127 ADO P40 to AD7 P47 A8 P50 to A15 P57 RD P64 WR P65 WAIT P66 ASTB P67 RESET xi x2 1 07 XT2 55 CHAPTER 2 OUTLINE uPD78058FY SUBSERIES 2 8 Outline of Function Part Number UPD78056FY HPD78058FY uPD78PO058FY ROM Mask ROM 48 Kbytes 1024 bytes PROM 60 KbytesNote 1 1024 bytesNote 1 Internal memory 60 Kbytes High speed RAM Buffer RAM 32 bytes Expansion RAM None 1024 bytes 1024 bytesNote 2 Memory space 64 Kbytes General register 8 bits x 8 x 4 banks Minimum instruction execution time Instruction set With main system clock selected 0 4 us 0 8 us 1 6 us 3 2 us 6 4 us 12 8 us at 5 0 MHz operation With subsystem
113. In the operation stop mode serial transfer is not performed and therefore power consumption can be reduced In the operation stop mode the P70 SI2 RxD P71 SO2 TxD and P72 SCK2 ASCK pins can be used as normal input output ports 1 Register setting Symbol CSIM2 446 The operation stop mode is set by the serial operating mode register 2 CSIM2 and asynchronous serial interface mode register ASIM a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H D 6 5 4 3 2 1 0 CSIM pee o o o o PAM esed Address After Reset R W FF72H 00H R W CSIE2 Operation Control in 3 wire Serial I O Mode 0 Operation stopped 1 Operation enabled Caution Ensure that bits 0 and 3 to 6 are set to 0 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 b Asynchronous serial interface mode register ASIM ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM to OOH Symbol Address After Reset R W FF70H 00H R W RXE Receive Operation Control Receive operation stopped ASIM 0 5 4 3 2 1 0 foe mers re aoe Receive operation enabled Transmit operation stopped Transmit operation enabled 447 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 4 2 Asynchronous serial interface UART mode In this mode one byte of data is transmitted received following th
114. Instruction Request Standby D EE Release Signal bt eee Operationg Oscillation Stabilization Operating Mode STOP Mode Wait Status Mode Oscillation Oscillation Stop Oscillation gt a a Remark The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged b Release by unmasked test input The STOP mode is cleared by unmasked test input After the lapse of the oscillation stabilization time the instruction at the next address after the STOP instruction is executed 521 CHAPTER 23 STANDBY FUNCTION c Release by RESET input The STOP mode is cleared upon RESET input and after the lapse of the oscillation stabilization time reset operation is performed Figure 23 5 Release by STOP Mode RESET Input STOP Instruction Wait 2 f 26 2 ms RESET Signal Oscillation Operating Reset Stabilization Operating Mode STOP Mode Period Wait Status Mode Oscillation Oscillation Stop Oscillation Clock e a Remarks 1 fx main system clock oscillation frequency 2 y fx 5 0 MHz Table 23 4 Operation After STOP Mode Release Release Source Operation Maskable interrupt request Next address instruction execution Interrupt service execution Next address instruction execution Interrupt service execution STOP mode hold Test input Next address instruction execution STOP mode
115. It is suspended upon completion of 8 bit data transfer When suspended bit 3 TRF of the automatic data transmit receive control register ADTC is set to 0 after transfer of the 8th bit and all the port pins used with the serial interface pins for dual function P20 SI1 P21 SO1 P22 SCK1 P23 STB and P24 BUSY are set to the port mode To restart auto send and receive set CSIE1 at 1 and write the desired value in serial I O shift register 1 SIO1 The remaining can be transmitted in this way Cautions 1 If the HALT instruction is executed during automatic transmission reception trans fer is suspended and the HALT mode is set if during 8 bit data transfer When the HALT mode is cleared automatic transmission reception is restarted from the suspended point 2 When suspending automatic transmission reception do not change the operating mode to 3 wire serial I O mode while TRF 1 Figure 18 17 Automatic Transmission Reception Suspension and Restart CSIE1 0 Suspended Command Suspend Restart Command CSIE1 1 Write to SIO1 Aozipejpsipejpsjosjp ioo prjpejpsip4jpsjpejptpo CSIE1 Bit 7 of serial operation mode register 1 CSIM1 423 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 4 Synchronization control 424 Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device By using these functions it is possible to detect bi
116. Main system clock frequency fx or fx 2 Main system clock oscillation frequency Subsystem clock oscillation frequency Don t care Bit 0 of oscillation mode selection register OSMS Figures in parentheses apply to operation with fx 5 0 MHz or fxt 32 768 kHz 249 CHAPTER 11 WATCHDOG TIMER 2 Watchdog timer mode register WDTM This register sets the watchdog timer operating mode and enables disables counting WDTM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets WDTM to OOH Figure 11 3 Watchdog Timer Mode Register Format symbol 6 5 4 Address ter R W Reset 3 2 1 0 WDTM RM WDTM4 WDTM3 ENSE FFF9H 00H R W 250 WDTM4 WDTM3 Watchdog Timer Operation Mode SelectionNote 1 Interval timer modeNete Maskable interrupt request occurs upon generation of an overflow Watchdog timer mode 1 Non maskable interrupt request occurs upon generation of an overflow Watchdog timer mode 2 Reset operation is activated upon generation of an overflow RUN Watchdog Timer Operation Mode SelectionNete3 Count stop Counter is cleared and counting starts Notes 1 Once set to 1 WDTM3 and WDTM4 cannot be cleared to 0 by software 2 The watchdog timer starts operating as an interval timer as soon as RUN has been set to 1 3 Once set to 1 RUN cannot be cleared to 0 by software Thus once counting starts it can only be stopped by RESET input Cau
117. Note The task swap function cannot be used with this software although this function is provided in MS DOS version 5 0 or later 571 APPENDIX B DEVELOPMENT TOOLS B 3 Debugging Tool B 3 1 Hardware 1 2 1 When using in circuit emulator IE 78K0 NS IE 78K0 NSNete In circuit emulator The in circuit emulator serves to debug hardware and software when developing application systems using a 78K 0 Series product It corresponds to integrated debugger ID78K0 NS This emulator should be used in combination with power supply unit emulation probe and interface adapter which is required to connect this emulator to the host machine IE 70000 MC PS B Power supply unit This adapter is used for supplying power from a receptacle of 100 V to 240 V AC IE 70000 98 IF CNete Interface adapter This adapter is required when using the PC 9800 Series computer except notebook type as the IE 78K0 NS host machine IE 70000 CD FNete PC card Interface This is PC card and interface cable requied when using the PC 9800 Series notebook type computer as the IE 78K0 NS host machine IE 70000 PC IF CNete Interface adapter This adapter is required when using the IBM PC AT and their compatible machine as the IE 78K0 NS host machine IE 780308 NS EM 1 Nete Emulation board This board emulates the operations of the peripheral hardware peculiar to a device It should be used in combination with an in circuit emulator
118. O P63 P44 AD4 O P45 AD5 O P46 AD6 O P47 AD7 O P50 A8 O P51 A9 O P52 A10 O P53 A11 O P54 A12 O P55 A13 P57 A15 O P60 O P61 P64 RD O Cautions 1 Be sure to connect Internally Connected IC pin to Vss directly 2 The AVpo pin is used in common as the power supply for the A D converter and port If this device is used in application fields where reduction of noise generated internally in the microprocessor is required please connectto a separate power supply with the same electrical potential as Vpp 3 The AVss pin is used in common as the ground for the A D converter D A converter and port If this device is used in application fields where reduction of noise generated internally in the microprocessor is required please connect it to a ground line which is separate from Vss Remark Pin connection in parentheses is intended for the uPD78PO058FY 50 CHAPTER 2 OUTLINE uPD78058FY SUBSERIES Pin Identifications A8 to A15 ADO to AD7 ANIO to ANI7 ANOO ANO1 ASCK ASTB AVREFo 1 AVss BUSY BUZ IC INTPO to INTP6 POO to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 P130 P131 Address Bus Address Data Bus Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected Interrupt from Peripherals Porto Port1 Port2 Port3
119. One Place Is 534 25 10 Program Transition Diagram When Two Places Are 535 26 1 Memory Size Switching Register Format sese nennen enne nnne 538 26 2 Internal Expansion RAM Size Switching Register 539 26 3 Page Program Mode Flowchliart teet erdt ied e D ree aea 542 26 4 Page Program Mode Timing arises iea aneii i a e Naa Erai ado Naaa 543 26 5 Byte Program Mode Flowchart 544 26 6 Byte Program Mode TIMING rie der teint E 545 26 7 PROM Read Timingi eni e e ev ep serate e pU aad 546 B 1 Development Tool Configuration 568 B 2 EV 9200GC 80 Drawings For Reference Only sss nennen 577 B 3 EV 9200GC 80 Footprints For Reference Only seen 578 B 4 TGK 080SDW Drawings For Reference unit 579 30 LIST OF TABLES 1 3 Table No Title Page 1 1 Differences Between the uPD78058F and uPD78058F A seme 45 1 2 Mask Options of Mask POM Versions ssssseseeneeeeeneeennee nennen nennen neret nnne 46 2 1 Differences Between the uPD78058FY and uPD78058FY A es 57 2
120. Pm On chip Pull up Resistor Selection m 0 to 7 12 13 0 On chip pull up resistor not used 1 On chip pull up resistor used Caution Bits 0 to 3 6 and 7 of PUOH should be set to 0 149 CHAPTER 6 PORT FUNCTIONS 3 Memory expansion mode register MM This register is used to set input output of port 4 MM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 10H Figure 6 21 Memory Expansion Mode Register Format After Symbol 7 6 5 4 3 2 1 0 Address Reset R W MM 0 0 PW1 PWO 0 MM2 MM1 MMO FFF8H 10H R W Single chip Memory P40 to P47 P50 to P57 P64 to P67 Pin State Expansion Mode Selection P40 to P47 P50 to P53 P54 P55 P56 P57 P64 to P67 Single chip mode Port Input mode Out put Memory 256 byte ADO to AD7 Port mode P64 RD expansion mode E mode P65 WR 4 Kbyte A8 to A11 Port mode P66 WAIT mode P67 ASTB 16 Kbyte A12 A13 Port mode mode Full A14 A15 address modeNete Other than above Setting prohibited No wait Wait one wait state insertion Setting prohibited Wait control by external wait pin Note The full address mode allows external expansion for all areas of the 64 Kbyte address space except the internal ROM RAM SFR and use prohibited areas Remarks 1 P60to P63 pins enter the port mode in both the single chip mode and memory expan
121. Programmable Clock Read Strobe Reset Real Time Output Port Receive Data Serial Bus Serial Clock Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Programming Power Supply Ground Wait Write Strobe Crystal Main System Clock Crystal Subsystem Clock 39 CHAPTER 1 OUTLINE uPD78058F SUBSERIES 2 PROM programming mode 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm uPD78PO58FGC 3B9 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm uPD78P058FGC 8BT 5 S a gt ETETE gt gt 0 gt 0 gt lt QOOOOOOOOOOOOOOOOOOQOQ A 1 RESET L lt 2 O O 3 O O Vss O 4 O 5 L O 6 5 L Voo O 7 8 O 9 O O O D7 O O D6 O O D5 L lt O O D4 O O D3 O O D2 O O D1 O O DO AO S 5j 0 O O A1 20 41 O CE 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 OOOOOOOOOOOOOOOOOOOO 22i192u2 9r 00 222 EXXExExXx2xax a Cautions 1 L Connect independenily to Vss via a pull down resistor 2 Vss Connect to the ground 3 RESET Set to the low level 4 Open Do not connect anything AO to A16 Address Bus RESET Reset CE Chip Enable VoD Power Supply DO to D7 Data Bus Vpp Programming Power Supply OE Output Enable Vss Ground PGM Program 40 CHAPTER 1 OUTLINE uPD78058F SUBSERIES 1 6 78K 0 Series Expansion The 78K 0 Series expansi
122. RELD Set When SVA SIOO 531935905 48S08Zdd 0 TIANNVHO 39VJH3LlNI TVINSS 91 H3ldVHO 9c Figure 16 28 Command Transmission from Master Device to Slave Device Master Device Processing Transmitter Write Interrupt Servicing Hardware Operation Transfer Line SCKO Pin SBO SB1 Pin Slave Device Processing Receiver 531938905 48S08Zdd 0 TANNVHO SOVSYSLNI 1ViH3S 91 YALdVHO Lee Figure 16 29 Data Transmission from Master Device to Slave Device Master Device Processing Transmitter Program Processing OI IOI III Next Serial Transfer Hardware Operation SCKO Pin SBO SB1 Pin Slave Device Processing Receiver Program Processing I II LI LLL LLL LLL LLL LL LLL LLL LLL LLL m VALLE Nit LLL Hardware Operation Serial Reception INTCSIO BUSY BUSY eneration _ Output Output __ Clear 531935905 48S08Zdd 0 TIANNVHO SOVSYSLNI TVINSS 91 H3ldVHO 8c Figure 16 30 Data Transmission from Slave Device to Master Device Master Device Processing Receiver Program Processing Sa Paco data processing Hardware Operation SCKO Transfer Line SCKO Pin SBO SB1 Pin BUSY READY Slave Device processing Transmitter Serial Reception 531935905 48S08Zdd 0 TANNVHO SOVSYSLNI VIHIS 91 YALdVHO CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 9 Transfer st
123. Register Format was changed Cautions were added to 16 4 3 2 a Bus release signal REL and b Command signal CMD CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES CSCK was deleted from Figure 19 1 Serial Interface Channel 2 Block Diagram and Figure 19 2 Baud Rate Generator Block Diagram Figure 19 3 Serial Operating Mode Register 2 Format was changed Table 19 2 Serial Interface Channel 2 Operating Mode Settings 2 3 Wire serial I O mode was changed Figure 19 10 Receive Error Timing was changed 19 4 4 Restrictions on using UART mode was added CHAPTER 19 SERIAL INTERFACE CHANNEL 2 APPENDIX A DIFFERENCES AMONG THE 4PD78054 78058F AND 780058 SUBSERIES was added APPENDIX A DIFFERENCES AMONG uPD78054 78058F AND 780058 SUBSERIES Overall revision Contents were adapted to correspond with in circuit emulators IE 78K0 NS and IE 78001 R A APPENDIX B DEVELOPMENT TOOLS Overall revision Fuzzy inference development support system was deleted APPENDIX C EMBED DED SOFTWARE 591 MEMO Although NEC has taken all possible steps essag e to ensure thatthe documentation supplied to our customers is complete bug free and up to date we readily accept that From b errors may occur Despite all the care and precautions we ve taken you may Name encounter problems in the documentation Please complete this form whenever Comp
124. Remark For special function register symbols refer to Table 5 3 Special Function Register List 550 CHAPTER 27 INSTRUCTION SET 27 1 2 Description of operation column A X BC DE HL PC SP PSW CY AC RBS IE NMIS XH XL V vi addr16 jdisp8 A register 8 bit accumulator X register B register C register D register Eregister H register L register AX register pair 16 bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data 16 bit immediate data or label Signed 8 bit data displacement value 27 1 3 Description of flag column Blank Not affected Cleared to 0 Set to 1 Set cleared according to the result Previously saved value is restored 551 CHAPTER 27 INSTRUCTION SET 27 2 Operation List Instruction Group Mnemonic Operands r byte Clock Note 1 Note 2 Operation r byte saddr byte saddr byte
125. SVA the interrupt request signal is also generated when the stop condition is detected and it can be learned by this interrupt request that the master requests for communication To use the wake up function set SIC to 1 Further when in the 2 wire serial I O mode or in the 12 bus mode when sending as a master or as a slave SVA can be used to detect errors RESET input makes SVA undefined CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 3 4 5 6 7 800 latch This latch holds SIO SBO SDAO P25 and SO0 SB1 SDA1 P26 pin levels It can be directly controlled by software Serial clock counter This counter counts the serial clocks to be output and input during transmission reception and to check whether 8 bit data has been transmitted received Serial clock control circuit This circuit controls serial clock supply to the serial I O shift register 0 SIOO When the internal system clock is used the circuit also controls clock output to the SCKO SCL P27 pin Interrupt signal generator This circuit controls interrupt request signal generation It generates interrupt request signals according to the settings of interrupt timing specification register SINT bits 0 and 1 WAT1 and serial operation mode register 0 CSIMO bit 5 WUP as shown in Table 17 3 Acknowledge output circuit and stop condition start condition acknowledge detector These two circuits output and detect various control
126. System Clock Oscillator 161 7 7 External Circuit of Subsystem Clock Oscillator eeeeeeneeeneenen 162 7 8 Examples of Resonator with Incorrect Connection 162 7 9 Main System Clock Stop Function ssesssseeseeeeeeene nennen nennen nennen nnne nnne 166 7 10 System Clock and CPU Clock Switching eecceeeceeeeeeeneeeeeeeeeeeseaeeeeeeseeeeeaeeseaeeseeseaeeeneeseeeteeeeeaeess 169 8 1 16 Bit Timer Event Counter Block Diagram 175 8 2 16 Bit Timer Event Counter Output Control Circuit Block Diagram 176 8 3 Timer Clock Selection Register 0 Format sssssssessesseeeeneneenen nene 179 8 4 16 Bit Timer Mode Control Register Format sssssssssssseeeeeeeneneneen nennen nnne 181 8 5 Capture Compare Control Register 0 Format sesssesseeeeeeneennen nennen nennen 182 8 6 16 Bit Timer Output Control Register Format sssssssssseeeeeneneeneeen een rennen nennen 183 8 7 Port Mode Register Format 184 8 8 External Interrupt Mode Register 0 Format 185 8 9 Sampling Clock Select Register Format ssssssssssseeeeeeeneeeee nennen
127. TMO and CRO1 Match between TMO and CROO match between and or TIOO valid edge Clear amp start on TIOO valid edge Match between TMO and CROO or match between TMO and CRO1 Match between TMO and CROO match between and or TIOO valid edge Clear amp start on match between TMO and CROO Cautions 1 Remarks TOO TIOO TMO Match between TMO and CROO or match between TMO and CRO1 Match between TMO and CROO match between and or TIOO valid edge Generated on match between TMO and CROO and match between TMO and CRO1 Switch the clear mode and the TOO output timing after stopping the timer operation by setting 1 to TMCO3 to 0 0 0 The valid edge of pin TIOO INTPO is set with the external mode register 0 INTMO Also the frequency of the sampling clock is selected with the sampling clock selection register SCS When using the PWM mode set the PWM mode and then set data to CROO If clear amp start mode on match between TMO and CROO is selected when the set value of CROO is FFFFH and the TMO value changes from FFFFH to 0000H OVFO flag is set to 1 16 bit timer register CROO Compare register 00 CRO1 Compare register 01 16 bit timer event counter output pin 16 bit timer event counter input pin 181 CHAPTER 8 16 TIMER EVENT COUNTER 3 Capture compare conirol register 0 CRCO This reg
128. The area 0800H to OFFFH can perform a direct subroutine call with a 2 byte call instruction CALLF 5 1 2 Internal data memory space The uPD78058F and 78058FY Subseries units incorporate the following RAMs 1 2 3 Internal high speed RAM This RAM has a 1024 x 8 bit configuration In this area four banks of general registers each bank consisting of eight 8 bit registers are allocated in the 32 byte area FEEOH to FEFFH The internal high speed RAM can also be used as a stack memory Internal buffer RAM Internal buffer RAM is allocated to the 32 byte area from FACOH to FADFH The internal buffer RAM is used to store transmit receive data of serial interface channel 1 in 3 wire serial I O mode with automatic transfer receive function If the 3 wire serial I O mode with automatic transfer receive function is not used the internal buffer RAM can also be used as normal RAM Internal buffer RAM can also be used as normal RAM Internal expansion RAM uPD78058F 78058FY 78P058F 78P058FY only Internal expansion RAM is allocated to the 1024 byte area from F400H to F7FFH 5 1 3 Special Function Register SFR area An on chip peripheral hardware special function register SFR is allocated in the area FFOOH to FFFFH Refer to Table 5 3 Special Function Register List in Section 5 2 3 Special Function Register SFR Caution Do not access addresses where the SFR is not assigned 5 1 4 External memory space The external memory s
129. Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait 2 3 b Data Master Device Operation Write SIOO jSI00 lt FFH S100 lt FFH BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO SCL YES OTN 1 lal BI 5 SDAO 07 XD8XDSXD4X 03 Slave Device Operation Device Slave Device Operation r r cr Write SIOO lt Data ee lt lt lt a a C P27 f WUP BSYE ACKE CMDT RELT CLE WREL SIC INTCSIO CSIEO P25 PM25 PM27 r7 378 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Figure 17 23 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait 3 3 c Stop Condition Master Device Operation Write 5100 45100 lt 9100 lt Address col CX XXX XX KNOX ACKD CMDD RELD L CLD P27 H WUP L BSYE ACKE CMDT RELT CLC WREL L sic L INTCSIO SCL SDAO 07 XD8XD5XD4XD3XD2XD1 X00 NAK Slave Device Operation Write SIOO CMDD RELD CLD P27 WUP BSYE ACKE CMDT L RELT L CLC L WREL SIC H INTCSIO CSIEO P25 PM25 PM27 r 379 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 17 4 5 Cautions on use of 12 bus mode 1 Start condition output master 380 The SCL pin normally outputs a low level signal when no ser
130. When setting the count value the value of the upper 8 bits is set in CR20 and the value of the lower 8 bits is set in CR10 The TO2 P32 pin output status is reversed at intervals of the count value preset to CR10 and CR20 by setting bit 4 TOE2 of the 8 bit timer output control register TOC1 to 1 This enables a square wave with any selected frequency to be output Table 9 10 Square Wave Output Ranges When 2 Channel 8 Bit Timer Event Counters TM1 and TM2 are Used as 16 Bit Timer Event Counter Minimum Pulse Width Maximum Pulse Width Resolution MCS 1 MCS 0 MCS 1 MCS 0 2 x 1 fx 22 x 1 fx 217 x 1 fx 218 x 1 fx 2 x 1 fx 2 x 1 fx 400 ns 800 ns 26 2 ms 52 4 ms 400 ns 800 ns 2 x 1 fx 23 x 1 fx 218 x 1 fx 219 x 1 fx 2 x 1 fx 23 x 1 fx 800 ns 1 6 us 52 4 ms 104 9 ms 800 ns 1 6 us 23 x 1 fx 24 x 1 fx 219 x 1 fx 220 x 1 fx 23 x 1 fx 24 x 1 fx 1 6 us 8 2 us 104 9 ms 209 7 ms 1 6 us 8 2 us 24 x 1 fx 25 x 1 fx 220 x 1 fx 221 x 1 fx 24 x 1 fx 25 x 1 fx 3 2 us 6 4 us 209 7 ms 419 4 ms 3 2 us 6 4 us 25 x 1 fx 26 x 1 fx 221 x 1 fx 222 x 1 fx 25 x 1 fx 26 x 1 fx 6 4 us 12 8 us 419 4 ms 838 9 ms 6 4 us 12 8 us 26 x 1 fx 27 x 1 fx 222 x 1 fx 223 x 1 fx 26 x 1 fx 27 x 1 fx 12 8 us 25 6 us 838 9 ms 1 7 s 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 223 x 1 fx 224 x 1 fx 2 x 1 fx 28 x 1 fx 25 6 us 51 2 us 1 7 s 3 4 s 25 6 us 51 2 us 28 x
131. after start condition signal Function Indicates address value for specification of slave on serial bus Signaled by Master Signaled when See Note 2 below Affected flag s Definition CSIIFO Also see Note 3 below 1 bit data output in synchronization with SCL after address output Function Indicates whether data transmission or reception is to be performed Signaled by Master Signaled when See Note 2 below Affected flag s Definition CSIIFO Also see Note 3 below 8 bit data synchronized with SCL not immediately after start condition Function Contains data actually to be sent Signaled by Master or slave Signaled when See Note 2 below Affected flag s CSIIFO Also see Note 3 below Notes 1 The serial clock level can be controlled by bit 3 CLC of the interrupt timing specify register SINT 2 Execution of instruction to write data to SIOO when CSIEO 1 serial transfer start directive In the wait state the serial transfer operation will be started after the wait state is released 3 If the 8 clock wait is selected when WUP 0 CSIIFO is set at the rising edge of the 8th clock cycle of SCL If the 9 clock wait is selected when WUP 0 CSIIFO is set at the rising edge of the 9th clock cycle of SCL CSIIFO is set if an address is received and that address coincides with the value of the slave address regis
132. are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins adjacent to the pin undergoing A D conversion AVrero pin input impedance A series resistor string of approximately 10 is connected between the AVnero pin and the AVss pin Therefore if the output impedance of the reference voltage source is high this will result in parallel connection to the series resistor string between the AVrero pin and the AVss pin and there will be a large reference voltage error 275 CHAPTER 14 A D CONVERTER 6 Interrupt request flag ADIF The interrupt request flag ADIF is not cleared even if the A D converter mode register ADM is changed Caution is therefore required since if a change of analog input pin is performed during A D conversion the A D conversion result and ADIF for the analog input before the change may be set just before the ADM rewrite If ADIF is read immediately after the ADM rewrite ADIF will be set regardless of whether A D conversion of the analog input after the change has been completed When the A D conversion is stopped and then resumed clear the ADIF before it is resumed Figure 14 11 A D Conversion End Interrupt Request Generation Timing ADM Rewrite ADIF is set but ANIm Start of ANIm Conversion conversion has not ended ADM Rewrite Start of ANIn Conversion A D Conversi
133. as serial data If the data length is specified as 7 bits bits 0 to 6 of the data written in TXS are transferred as transmit data Writing data to TXS starts the transmit operation TXS is written to with an 8 bit memory manipulation instruction It cannot be read TXS value is FFH after RESET input Caution TXS must not be written to during a transmit operation TXS and the receive buffer register are allocated to the same address and when a read is performed the value of RXB is read Receive shift register RXS This register is used to convert serial data input to the RxD pin to parallel data When one byte of data is received the receive data is transferred to the receive buffer register RXB RXS cannot be directly manipulated by a program Receive buffer register RXB This register holds receive data Each time one byte of data is received new receive data is transferred from the receive shift register RXS If the data length is specified as 7 bits the receive data is transferred to bits 0 to 6 of RXB and the MSB of RXB is always set to O RXB is read with an 8 bit memory manipulation instruction It cannot be written to RXB value is FFH after RESET input Caution RXB and the transmit shift register TXS are allocated to the same address so that even when a write instruction to RXB is performed the value is written to TXS Transmission control circuit This circuit performs transmit operation control su
134. be reduced by setting the voltage to be input to the pin to AVss level in standby mode Caution A series resistor string of approximately 10 is connect between the AVnero pin and the AVss pin Therefore if the output impedance of the reference voltage source is high this will result in an active line connected in parallel to the series resistor string between the AVnero pin and the AVss pin causing a large reference voltage error 8 AVss pin This is a GND potential pin of the A D converter Keep it at the same potential as the Vss pin when not using the A D converter 9 pin This is an A D converter analog power supply pin Keep it at the same potential as the Von pin when not using the A D converter 14 3 A D Converter Control Registers The following three types of registers are used to control the A D converter A D converter mode register ADM A D converter input select register ADIS External interrupt mode register 1 INTM1 1 A D converter mode register ADM This register sets the analog input channel for A D conversion conversion time conversion start stop and external trigger ADM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADM to 01H 265 CHAPTER 14 A D CONVERTER Figure 14 2 A D Converter Mode Register Format After A ddress Reset Symbol D 5 4 3 2 R W 1 0 ADM CS TRG FR1 FRO ADM3 ADM2 ADM1 FF80H 01H R W ADM1 Analog Inp
135. bits other than the manipulated bit 6 5 Selection of Mask Option The following mask option is provided in mask ROM version The PROM versions have no mask options Table 6 6 Comparison Between Mask ROM Version and PROM Version Mask ROM Version PROM Version Mask option for pins P60 to P63 Bit wise selectable on chip pull up resistors No on chip pull up resistor 153 MEMO 154 CHAPTER 7 CLOCK GENERATOR 7 1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware The following two types of system clock oscillators are available 1 Main system clock oscillator This circuit oscillates at frequencies of 1 to 5 0 MHz Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register PCC 2 Subsystem clock oscillator The circuit oscillates at a frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used not using the internal feedback resistor can be set by the processor clock control register PCC This enables to decrease power consumption in the STOP mode 7 2 Clock Generator Configuration The clock generator consists of the following hardware Table 7 1 Clock Generator Configuration Control register Processor clock control register PCC Oscillation mode selection register OSMS Oscillator Main system clock oscillator Subsystem clock oscillator
136. both rising and falling edge capture compare register 00 CROO cannot perform the capture operation Figure 8 22 Control Register Settings for Pulse Width Measurement with Free Running Counter and Two Capture Registers a 16 bit timer mode control register TMCO TMC03 TMC02 TMCO1 OVFO b Capture compare control register 0 Free Running Mode CRC02 CRC01 CRCOO Paru E ERE CROO set as capture register Captured in CROO on invalid edge of TIOO PO0 Pin CRO01 set as capture register Remark 0 1 Setting O or 1 allows another function to be used simultaneously with pulse width measure ment See the description of the respective control registers for details 197 CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 23 Timing of Pulse Width Measurement Operation by Free Running Counter and Two Capiure Registers with Rising Edge Specified TMO Count Value Koo X 1 X9 X EKo 1 Y ras T100 Pin Input 1 _ CRO01 Captured Value 1 ber CROO Captured Value IX Di X D3 INTPO OVFO 198 CHAPTER 8 16 TIMER EVENT COUNTER 4 Pulse width measurement by means of restart When input of a valid edge to the TIOO POO0 pin is detected the count value of the 16 bit timer register is taken into 16 bit capture compare register 01 CRO1 and then the pulse width of the signal input to the TI00 P00 pin is measured
137. buffer ON Input mode output buffer OFF 224 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 9 4 8 Bit Timer Event Counter Operation 9 4 1 8 bit timer event counter mode 1 Interval timer operations Operates as an interval timer which generates interrupt requests repeatedly with the count values set previously in the 8 bit conveyor registers 10 and 20 CR10 CR20 as the interval When the count values of the 8 bit timer registers 1 and 2 TM1 and TM2 match the values set to CR10 and CR20 counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signals INTTM1 and INTTM2 are generated Count clock of TM1 can be selected with bits 0 to TCL10to TCL13 ofthe timer clock select register 1 1 Count clock of TM2 can be selected with bits 4 to 7 TCL14to TCL17 of the timer clock select register 1 TCL1 For the operation when the value of the compare register has been changed during timer count operation refer to section 9 5 3 Operation after compare register change during timer count operation Figure 9 8 Interval Timer Operation Timings t lt gt Count Clock de par de s SE esa ope Tut 0 Y or X X 8 X9 X 9 X9 X KNX A A A Count Start Clear Clear Interrupt Request Acknowledge INTTM1 Interrupt Request Acknowledge TO1 5 4 B _ Interval Time Interval Time Interval Time i Remark Interval time N 1 x t N 00H to FFH 225 CHAPTER 9
138. byte A CY amp A byte CY saddr byte saddr CY lt saddr A r A CY A r CY r CY r A CY A saddr A CY lt A A addr16 NIN W M NM NM PM A CYe A A HL A CY A HL A HL byte A CY lt A HL byte A HL B A CY HL A HL C A CY A HL C A byte A lt A byte saddr byte saddr lt saddr byte A r lt A r r r A A saddr A lt A saddr A laddr 6 lt A addr16 A HL lt A HL HL byte A lt AA HL byte A HL B A lt A HL A HL 0 0 0 i 0 RI O oO o HR oO HR HRI RL oO SR hp Mw N lt A HL byte byte CY CY CY Notes 1 2 When an area except the internal high speed RAM area is accessed 3 Except r A When the internal high speed RAM area is accessed or instruction with no data access Remarks 1 One instruction clock is the length of 1 clock cycle of the CPU clock fceu selected by the processor clock control register PCC 2 This clock cycle applies to internal ROM program 3 nis the numb
139. cde bear io Eee dE epe eite nr Ae hee 366 17 20 end eeu Eee 367 17 21 Pin Gonfiguration eere patte eld bestie e t e n RU 372 17 22 Data Transmission from Master to Slave Both Master and Slave Selected 9 Clock Wait 374 17 23 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait 377 17 24 Start Condition Output cei uh oet eet tete eee tit rede ae ce exe Beene 380 17 25 Slave Wait Release Transmission esses nennen nnne nnne ns 381 17 26 Slave Wait Release Reception 382 17 27 SCKO SCL P27 Pin Configuration sss 385 17 28 SCKO SCL P27 Pin Configuration essent nnne nnns 385 17 29 Logic Circuit OF SCL Signal oe x ee mt e p cet ae ee e diee etudes 386 18 1 Serial Interface Channel 1 Block Diagram sssssseseeeeeeeeneneenenenene nennen nnne 389 18 2 Timer Clock Select Register nnne nnne nennen 392 18 3 Serial Operating Mode Register 1 Format sssssssssssseeeeeeeeneneneee nennen nnne nnne enne 393 18 4 Automatic Data Transmit Receive Control Register Format 394 27 LIST OF FIGURES 6 8 Figure No Title Page 18 5 Automatic Data Transmit Receive Interval Specify Re
140. configuration of the serial I O shift register 0 SIOO and internal bus As shown in the figure MSB LSB can be read written in reverse form MSB LSB switching as the start bit can be specified with bit 2 CSIMO2 of the serial operating mode register 0 CSIMO Figure 17 9 Circuit of Switching in Transfer Bit Order Internal Bus 4 emu rpg GR ea Horse en a a a cana LSB first MSB first Read Write Gate Read Write Gate Start bit switching is realized by switching the bit order for data write to SIO0 The SIOO shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to the shift register Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIOO when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIEO 1 Internal serial clock is stopped or SCKO is a high level after 8 bit serial transfer Caution If CSIEO is set to 1 after data write to SIOO transfer does not start Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIFO is set 357 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 17 4 3 2 wire serial I O mode operation The 2 wire serial I O mode can cope
141. fall of the next serial clock If WUP z 1 is set during this interval by mistake it will be impossible to reset BUSY Therefore after resetting the BUSY signal confirm that the level of the SBO SB1 pin has gone high before setting WUP to 1 3 Register setting 312 The SBI mode is set with serial operating mode register 0 CSIMO the serial bus interface control register SBIC and the interrupt timing specify register SINT a Serial operating mode register 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES Symbol D 6 4 Address After Reset R W Meme Serial Interface Channel 0 Clock Selection Input Clock to SCKO pin from off chip R W 8 bit timer register 2 TM2 output Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 CSIM Operation Start Bit SIO SBO P25 SOO SB1 P26 SCKO0 P27 03 Mode Pin Function Pin Function Pin Function 3 wired serial I O mode 16 4 2 3 wire serial I O mode operation Note 2 Note 2 SB1 N ch x x P25 CMOS open drain input output input output SCKO CMOS input output SBI mode ere SBO N ch P26 CMOS x x open drain input output input output 2 wired serial mode see section 16 4 4 2 wire serial I O mode operation Interrup
142. fetched each time another instruction is executed When a branch instruction is executed the branch destination information is set to the PC and branched by the following addressing For details of instructions refer to 78K 0 Series User s Manual Instruction U12326E 5 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In the relative addressing modes execution branches in a relative range of 128 to 127 from the first address of the next instruction This function is carried out when the BR addr16 instruction or a conditional branch instruction is executed Illustration PC indicates the start address PC of the instruction T after the BR instruction 15 8 7 6 0 o 8 8 jdisp8 15 0 S When S 0 all bits of are 0 When S 1 all bits of are 1 112 CHAPTER 5 CPU ARCHITECTURE 5 3 2 Immediate addressing Function Immediate data in the instruction word is transferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR addr16 or CALLF addr11 instruction is executed The CALL addr16 and BR addr16 instruction can branch in the entire memory
143. flag MK Interrupt mask flag PR Priority specify flag 481 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions Interrupt request flag register IFOL IFOH IF1L Interrupt mask flag register MKOL MKOH MK1L Priority specify flag register PROL PROH PR1L External interrupt mode register INTMO INTM1 Sampling clock select register SCS Program status word PSW Table 21 2 gives a listing of interrupt request flags interrupt mask flags and priority specify flags corresponding to interrupt request sources Table 21 2 Various Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Order Specification Flag Register Register Register INTWDT TMIF4 TMMK4 TMPR4 INTPO PIFO PMKO PPRO INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTP4 PIF4 PMK4 PPR4 INTP5 PIFS PMK5 PPR5 INTP6 PIF6 PMK6 PPR6 INTCSIO CSIIFO CSIMKO CSIPRO INTCSI1 CSIIF1 CSIMK1 CSIPR1 INTSER SERIF SERMK SERPR INTSR INTCSI2 SRIF SRMK SRPR INTST STIF STMK STPR INTTMS TMIF3 TMMK3 TMPR3 INTTMOO TMIFOO TMMKOO TMPROO INTTMO1 TMIFO1 TMMKO1 TMPRO1 INTTM1 TMIF1 TMMK1 TMPR1 INTTM2 TMIF2 TMMK2 TMPR2 INTAD ADIF ADMK ADPR 482 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 1 Interrupt request flag registers IFOL
144. fx 23 x 1 fx 800 ns 1 6 52 4 ms 104 9 ms 800 ns 1 6 us 23 x 1 fx 24 x 1 fx 219 x 4 fx 220 x 1 fx 23 x 1 fx 24 x 1 fx 1 6 us 3 2 us 104 9 ms 209 7 ms 1 6 us 3 2 us 24 x 1 fx 25 x 1 fx 220 x 1 fx 221 x 1 fx 24 x 1 fx 25 x 1 fx 8 2 us 6 4 us 209 7 ms 419 4 ms 8 2 us 6 4 us 25 x 1 fx 26 x 1 fx 221 x 1 fx 222 x 1 fx 25 x 1 fx 26 x 1 fx 6 4 us 12 8 us 419 4 ms 838 9 ms 6 4us 12 8 us 26 x 1 fx 27 x 1 fx 222 x 4 fx 223 x 1 fx 26 x 1 fx 27 x 1 fx 12 8 us 25 6 us 838 9 ms 1 7 s 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 223 x 1 fx 224 x 1 fx 27 x 1 fx 28 x 1 fx 25 6 us 51 2 us 1 7 s 8 4 s 25 6 us 51 2 us 28 x 1 fx 29 x 1 fx 224 x 1 fx 225 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 us 3 4 s 6 7 s 51 2 us 102 4 us 29 x 1 fx 210 x 1 fx 225 x 1 fx 226 x 1 fx 29 x 1 fx 210 x 1 fx 102 4 us 204 8 us 6 7 s 13 4 s 102 4 us 204 8 us 211 x 1 fx 212 x 1 fx 227 x 1 fx 228 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 26 8 s 53 7 s 409 6 us 819 2 us Other than above Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 3 TCL10 to TCL13 Bits 0 to 3 of timer clock selection register 1 TCL1 4 Values in parentheses when operated at fx 5 0 MHz 232 CHAPTER 9 8 BIT TIMER EVENT COUNTERS
145. grounding line signal line of the resonator potential at points A B and C fluctuate AVop Pnm X2 X1 IC X2 X1 IC High Current IE C High Current 777 777 Signals are fetched i IBI B 77 Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side Cautions 2 If XT2 and X1 are wired in parallel the crosstalk noise of X1 may be transmitted along XT2 and cause malfunctions To prevent that from occurring it is recommended to wire XT2 and X1 so that they are not in parallel and to correct the IC pin between XT2 and X1 directly to Vss 163 CHAPTER 7 CLOCK GENERATOR 7 4 3 Scaler The scaler divides the main system clock oscillator output fxx and generates various clocks 7 4 4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations connect the XT1 and XT2 pins as follows XT1 Connect to XT2 Leave open In this state however some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops To suppress the leakage current disconnect the above internal feedback resistor by using the bit 6 FRC of the processor clock control register PCC In this case also connect the XT1 and XT2 pins as described above 164 CHAPTER 7 CLOCK GENERAT
146. iet obo di Rire ane 437 SUCCESSIVE approximation register sessessesesseseeeeeeenne enne nnne nnne trennen nenne 264 Serial bus interface control register 296 302 314 333 349 355 360 369 Sampling clock select register ikii a aid aein deen a i eaea ie nnne 186 488 Special function register iversen e eet 108 Interrupt timing specify register ssse e 298 316 351 360 370 Serial O shift register 0 e e mx iei Od eR 290 342 Serial l O shiftregister 1 uie dee UE E e c te e ERG 390 Slave add ESS EgO O 290 342 362 373 Timer clock select register 0 178 254 Timer clock select register 1 aet eerie n DUX ite oneal 220 Timer clock select register 2 eee Ricette dana adeecnsnsaizcagaseeanscaieees 240 248 258 Timer clock select register sssssssssssssssesseeeeeeneee rennen rens 292 345 391 16 bit timer regiSter o iecit bare o t be deter e soma dee rete rt m dete 178 e bit timer register 4 5 es eds uie i a e da ees 219 esbittimier register 2 aia daten or ih da bre cud tm tds 219 16 bit timer mode control register 180 8 bit timer mode control register eeeesesseseseeeeseeseneeee nennen
147. it is used as a capture register or as a compare register is set by bit O CRCOO of capture compare control register 0 When CROO is used as a compare register the value set in CROO is constantly compared with the 16 bit timer register TMO count value and an interrupt request INTTMOO is generated if they match It can also be usedasthe register which holds the interval time when TMO is setto interval timer operation and as the register which sets the pulse width when TMO is set to PWM operating mode When CROO is used as a capture register it is possible to select the valid edge of the INTPO TIOO pin or the INTP1 TIO1 pin as the capture trigger The valid edge of INTPO TIOO and INTP1 TIO1 are set by external interrupt mode register 0 INTMO If CROO is specified as a capture register and capture trigger is specified to be the valid edge of the INTPO TIOO pin the situation is as shown in the following table Table 8 5 INTPO TIOO Pin Valid Edge and CROO Capture Trigger Valid Edge ES11 ES10 INTPO TIOO Pin Valid Edge CROO Capture Trigger Valid Edge Falling edge Rising edge Rising edge Falling edge Setting prohibited Both rising and falling edges No capture operation Remark ES10 ES11 Bits 2 and of external interrupt mode register 0 INTMO CROO is set by a 16 bit memory manipulation instruction After RESET input the value of CROO is undefined Cautions 1 Set the data of PWM 14 bits to the higher 14 bits
148. low interrupt priority group by setting the priority specify flag register PROL PROH PR1L Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupts has a predetermined priority see Table 21 1 A standby release signal is generated There are 7 external interrupt request source and 13 internal interrupt request source in maskable interrupts Software interrupt This is a vectored interrupt that occurs when the BRK instruction is executed It is acknowledged even in a disabled state The software interrupt does not undergo interrupt priority control 477 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 2 Interrupt Sources and Configuration Combining all the factors in interrupts non maskable interrupts maskable interrupts and software interrupts there are a total of 22 source see Table 21 1 Table 21 1 Interrupt Source List 1 2 Note 1 Interrupt Default Interrupt Source Internal vector SR Table Type Priority Trigger External Address Non Watchdog timer overflow Internal maskable EIDE with watchdog timer mode 1 selected INTWDT Watchdog timer overflow with interval timer mode selected INTPO Pin input edge detection External INTP1 INTP2 INTP3 INTP4 INTP5 Maskable INTER INTCSIO End of serial interface channel 0 transfer Internal
149. mm Resin thickness 2 7 mm uPD78056FGOC xxx 3B9 78058FGC xxx 3B9 78058FGC A xxx 3B9 78P058FGC 3B9 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm uPD78056FGOC xxx 8BT 78058FGC xxx 8BT 78P058FGC 8BT 80 pin plastic TQFP Fine pitch 12 x 12 mm uUPD78058FGK xxx BE9 NTP1 TIO1 NTPO TIOO st CO QN 38829 ERE 22222 22222 A SS Sn eS gt Sa 4oaqcocacac oQi43oqa co gt gt aoocooooo D n n a xxcxx nu tu ntnunnn QOOOGOGOOOCCHQOQOOOCOOOCGCOOZQO 80 79 78 77 76 75 74 73 72 T1 70 69 68 67 66 65 64 63 62 610 15 5 1 RESET P16 ANI6 2 P127 RTP7 17 7 3 O P126 RTP6 AVss O 4 O P125 RTP5 P130 ANOO O 5 O P124 RTP4 P131 ANO1 O 6 O P123 RTP3 1 7 P122 RTP2 P70 SI2 RxD 8 O P121 RTP1 P71 SO2 TxD 9 O P120 RTPO P72 SCK2 ASCK O O P37 P20 SH O P36 BUZ P21 SO1 O O P35 PCL P22 SCKT 4 2 P23 STB P24 BUSY P32 TO2 P25 SI0 SBO P31 TO1 P26 SO0 SB1 P30 TOO P27 SCKO P67 ASTB P40 ADO P66 WAIT P41 AD1 P65 WR 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 OO e lt lt SS aa P44 AD4 O P45 AD5 O P46 AD6 O P47 AD7 O P50 A8 O P51 A9 O P52 A10 O P53 A11 O P54 A12 O P55 A13 O Vss O P56 A14 O P57 A15 O P60 O P61 O Pe2 O P63 O P64 RD O Cautions 1 Be sure to connect Internally Connected IC pin to Vss directly
150. nnne nnne nennen nennen 222 Watch timer mode control register eeseeesseseeeeeeieee nensem nennen nnne nnne 243 16 bit time TegIster xi a e ce IEEE EE EC IY CERE ERREUR ORE eB Eau vela 219 16 bit timer output control register ecce it ite tr Ce pibe Rice derer de n IR A 182 589 APPENDIX D REGISTER INDEX TOC1 TXS W WDTM 590 8 bit timer output control register Transmit shift register Watchdog timer mode register APPENDIX E REVISION HISTORY Major revisions by edition and revised chapters are shown below Edition Major Revisions from Previous Edition The following products have already been developed uPD78056GC ooc8BT 78058FGC xxx 8BT 78P058FGC 8BT 78056FYGC ooc 8BT 78058FYGC xxx 88BT Revised Chapters Throughout The block diagrams of the following ports were changed Figures 6 5 and 6 7 P20 P21 P23 to P26 Block Diagram Figures 6 6 and 6 8 P22 and P27 Block Diagram Figure 6 9 P30 to P37 Block Diagram Figure 6 16 P71 and P72 Block Diagram CHAPTER 6 PORT FUNCTIONS Table 7 2 Relationship between CPU Clock and Minimum Instruction Execution Time was added CHAPTER 7 CLOCK GENERATOR Figures 9 10 and 9 13 Square Wave Output Operation Timing were added CHAPTER 9 8 BIT TIME EVENT COUNTER Note related to operation control in the SBI mode for serial interface channel 0 was added Note related to BSYE in Figure 16 5 Serial Bus Interface Control
151. operations are performed in synchronization with the fall of the serial clock SCK2 Then transmit data is held in the SO2 latch and output from the SO2 pin Also receive data input to the SI2 pin is latched in the receive buffer register RXB SIO2 on the rise of SCK2 At the end of an 8 bit transfer the operation of the TXS SIO2 or RXS stops automatically and the interrupt request flag SRIF is set Figure 19 12 3 Wire Serial I O Mode Timing End of Transfer Transfer Start at the Falling Edge of SCK2 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 3 MSB LSB switching as the start bit 4 The 3 wire serial I O mode enables to select transfer to start from MSB or LSB Figure 19 13 shows the configuration of the transmit shift register TXS SIO2 and internal bus As shown in the figure MSB LSB can be read written in reverse form MSB LSB switching as the start bit can be specified with bit 2 CSIM22 of the serial operating mode register 2 CSIM2 Figure 19 13 Circuit of Switching in Transfer Bit Order Internal Bus 4 Sp ee ae ee cedem LSB first MSB first Read Write Gate gt Read Write Gate Start bit switching is realized by switching the bit order for data write to SIO2 The SIO2 shift order remains unchanged Thus switching between MSB first and LSB first must be performed before wr
152. or one shot pulse output 2 8 bit timers event counters 1 and 2 TM1 and TM2 TM1 and TM2 can be used to serve as an interval timer and an external event counter and to output square waves with any selected frequency Two 8 bit timer event counters can be used as one 16 bit timer event counter See CHAPTER 9 8 BIT TIMER EVENT COUNTER 3 Watch timer TM3 This timer can set a flag every 0 5 sec and simultaneously generates interrupts request at the preset time intervals See CHAPTER 10 WATCH TIMER 4 Watchdog timer WDTM WDTM can perform the watchdog timer function or generate non maskable interrupts maskable interrupts request and RESET at the preset time intervals See CHAPTER 11 WATCHDOG TIMER 5 Clock output control circuit This circuit supplies other devices with the divided main system clock and the subsystem clock See CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 6 Buzzer output control circuit This circuit outputs the buzzer frequency obtained by dividing the main system clock See CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 171 CHAPTER 8 16 TIMER EVENT COUNTER Table 8 1 Timer Event Counter Operation Interval timer 16 bit Timer event Counter 2 channelsNote 3 8 bit Timer event Counters 1 and 2 2 channels Watch Timer 1 channelNote 1 Watchdog Timer 1 channelNote 2 External event counter Function Timer output 4 PWM output Pulse width measur
153. receive control register ADTC If receive operation busy control and strobe control are not executed the P20 SI1 P23 STB and P24 BUSY pins can be used as normal input ports Figure 18 11 shows the basic transmission mode operation timings and Figure 18 12 shows the operation flowchart Figure 18 13 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted or received Figure 18 11 Basic Transmission Mode Operation Timings Interval E32 C9 C2 C2 C2 CD CONI CD 02 C2 PANES CD QD COSI Cautions 1 Because in the basic transmission mode the automatic transmit receive function reads data from the internal buffer RAM after 1 byte transmission an interval is inserted till the next transmission As the internal buffer RAM read is performed at the same time as CPU processing the maximum interval is dependent upon CPU processing and the value of the automatic data transmit receive interval specify register ADTI see 5 Automatic transmit receive interval time 2 When TRF is cleared the SO1 pin becomes low level CSIIF1 Interrupt request flag TRF Bit 3 of the auto data send and receive control register ADTC 415 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 12 Basic Transmission Mode Flowchart Write transmit data in internal buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Software Execution Set the transm
154. register ADCR Undefined Input select register ADIS 00H D A converter Mode register DAM 00H Conversion value setting register DACSO DACS1 00H Real time output port Mode register RTPM 00H Control register RTPC 00H Buffer register RTBL RTBH 00H ROM correction Correction address register CORADO CORAD1 Nete 0000H Correction control register CORCN Nete 00H Interrupt Request flag register IFOL IFOH IF1L 00H Mask flag register MKOL MKOH MK1L FFH Priority specify flag register PROL PROH PR1L FFH External interrupt mode register INTMO INTM1 00H Key return mode register KRM 02H Sampling clock select register SCS 00H Note Incorporated only the uwPD78058F 78058FY 78P058F 78PO58FY 526 CHAPTER 25 ROM CORRECTION 25 1 ROM Correction Functions The uPD78058F 78058FY Subseries can replace part of a program in the mask ROM with a program in the internal expansion RAM Instruction bugs found in the mask ROM can be avoided and program flow can be changed by using the ROM correction The ROM correction can correct two places max of the internal ROM program Caution The ROM correction cannot be emulated by the in circuit emulator IE 78000 R IE 78000 R A IE 78K0 NS and IE 78001 R A 25 2 ROM Correction Configuration The ROM correction is executed by the following hardware Table 25 1 ROM Correction Configuration Configuration Register Co
155. register 0 STOO data R W Operation stopped Operation enabled Notes 1 Bit 6 COI is a read only bit 2 Can be used freely as port function 3 Be sure to set WUP to 0 when the 2 wire serial I O mode 4 When CSIEO 0 COI becomes 0 Remark x don t care PMXX Port Mode Register PXX Port Output Latch 332 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES b Serial bus interface control register SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H symbol gt O Address After Reset R W SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R W R W RELT When RELT 1 500 latch is set to 1 After 500 latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 R W cMpT When 1 500 latch is cleared to 0 After 500 latch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO c Interrupt timing specify register SINT SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Symbol 7 3 Address After Reset R W ow Lo Teo mE Lee To nomme R W SIC INTCSIO Interrupt Source Selection CSIIFO is set upon termination of serial interface channel 0 transfer CSIIFO is set upon bus release detection or termination of serial interface channel 0 transfer
156. register 12 Port mode register 13 Real time output buffer register L Real time output buffer register H Real time output port mode register 2 2 2 2 2 Real time output port control register 109 CHAPTER 5 CPU ARCHITECTURE Table 5 3 Special Function Register List 2 3 Manipulatable Bit Unit Address Special Function Register SFR Name After Reset 1 bit 8 bits 16 bits Correction address register oNote CORADO i Note Correction address register 1 CORAD1 Timer clock select register 0 TCLO Timer clock select register 1 TCL1 Timer clock select register 2 TCL2 Timer clock select register 3 TCL3 Sampling clock select register SCS 16 bit timer mode control register TMCO 8 bit timer mode control register 1 TMC1 Watch timer mode control register TMC2 Capture compare control register 0 CRCO 16 bit timer output control register TOCO 8 bit timer output control register TOC1 Serial operating mode register 0 CSIMO Serial bus interface control register SBIC Undefined 00H Slave address register SVA Interrupt timing specify register SINT Serial operating mode register 1 CSIM1 Automatic data tra
157. resolution A D converter 8 channels 8 bit resolution D A converter 2 channels Serial interface 3 channels e 3 wire serial I O 2 wire serial 2 bus mode 1 channel e 9 wire serial I O mode Automatic transmit receive function 1 channel e 3 wire serial I O UART mode 1 channel Timer 5 channels 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel 22 vectored interrupts Two test inputs Two types of on chip clock oscillators main system clock and subsystem clock Supply voltage 2 7 to 6 0 V 47 CHAPTER 2 OUTLINE uPD78058FY SUBSERIES 2 2 Applications In the case of the uPD78056FY 78058FY and 78P058FY Cellular phones pagers printers AV equipment air conditioners cameras PPCs fuzzy home appliances vending machines etc In the case of the u PD78058FY Controllers for car electronics gas detection and shut off devices various safety devices etc 2 3 Ordering Information Part Number Package Internal ROM uPD78056FYGC xxx 3B9 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm Mask ROM uPD78056FYGC xxx 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Mask ROM uPD78058FYGC xxx 3B9 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm Mask ROM uPD78058FYGC xxx 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Mask ROM uPD78058FYGK xxx BE9 80 pin plastic TQFP Fine pitch 1
158. select one of them Alphabetic letters in capitals and symbols and are key words and must be described as they are Each symbol has the following meaning Immediate data specification Absolute address specification Relative address specification Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below RO R1 R2 etc can be used for description Table 27 1 Operand Identifiers and Description Methods Identifier Description Method X RO A R1 C R2 B R3 E R4 D R5 L R6 H R7 AX RPO BC RP1 DE RP2 HL RP3 Special function register symbolNote Special function register symbol 16 bit manipulatable register even addresses only Note FE20H FF1FH Immediate data or labels FE20H FF1FH Immediate data or labels even address only 0000H FFFFH Immediate data or labels Only even addresses for 16 bit data transfer instructions 0800H OFFFH Immediate data or labels 0040H 007FH Immediate data or labels even address only 16 bit immediate data or label 8 bit immediate data or label 3 bit immediate data or label RBO to RB3 Note Addresses from FFDOH to FFDFH cannot be accessed with these operands
159. selected so that the interval may be longer than the value indicated in Table 18 3 Figure 18 23 Automatic Transmit Receive Interval Time CSIIF1 Interrupt request flag Interval lt gt SCK1 so __ 7 5 jojpejpsjp jpejpe pt 4Do Si pzjpejpsjpejosjpejp 4po CSIIF1 429 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 a When the automatic transmit receive function is used by the internal clock If bit 1 CSIM11 of serial operation mode register 1 CSIM1 is set at 1 the internal clock operates If the auto send and receive function is operated by the internal clock interval timing by CPU processing is as follows When bit 7 ADTI7 of automatic data transmit receive interval specify register ADTI is set to 0 the interval depends on the CPU processing When ADTI7 is set to 1 it depends on the contents of the ADTI or CPU processing whichever is greater Refer to Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format for the intervals which are set by the ADTI Table 18 2 Interval Timing Through CPU Processing When the Internal Clock Is Operating CPU Processing Interval Time When using multiplication instruction 2 5Tsck 13TcPu External access 1 wait mode 2 5Tsck 9TcPu 2 5Tsck 7TcPu When using division instruction 2 5Tsck 20TcPu a Other than above Tsck 1 fscK fsck Serial clock frequency TcP
160. setting lt 1 gt Write transmit data from the least significant address FACOH of internal buffer RAM up to FADFH at maximum The transmit data should be in the order from high order address to low order address 2 Set to the automatic data transmit receive address pointer ADTP the value obtained by subtracting 1 from the number of transmit data bytes b Automatic transmit receive mode setting 1l Set bit 7 CSIE1 and bit 5 ATE of serial operating mode register 1 CSIM1 to 1 2 Set bit 7 RE of the automatic data transmit receive control register ADTC to 1 9 Seta data transmit receive interval in the automatic data transmit receive interval specify register ADTI 4 Write any value to the serial I O shift register 1 5101 transfer start trigger Caution Writing any value to SIO1 orders the start of automatic transmit receive operation and the written value has no meaning The following operations are automatically carried out when a and b are set e After the internal buffer RAM data specified with ADTP is transferred to 5101 transmission is carried out start of automatic transmission reception The received data is written to the buffer RAM address specified with ADTP ADTP is decremented and the next data transmission reception is carried out Data transmission reception continues until the ADTP decremental output becomes 00H and address FACOH data is output end of automatic transm
161. setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 Used for command signal output When CMDT 1 SOO latch is cleared to 0 After SOO latch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 R RELD Bus Release Detection Clear Conditions RELD 0 Set Conditions RELD 1 When transfer start instruction is executed When bus release signal REL is detected If SIOO and SVA values do not match in address reception only when WUP 1 When CSIEO 0 When RESET input is applied R Command Detection Clear Conditions CMDD 0 Set Conditions CMDD 1 When transfer start instruction is executed When command signal CMD is detected When bus release signal REL is detected When CSIEO 0 When RESET input is applied R W Acknowledge signal is output in synchronization with the falling edge clock of SCKO just after execution ofthe instruction to be set to 1 and after acknowledge signal output automatically cleared to 0 Used as ACKE 0 Also cleared to 0 upon start of serial interface transfer or when CSIEO 0 R W ACKE Acknowledge Signal Automatic Output Control Acknowledge signal automatic output disable output with ACKT enable Before completion of Acknowledge signal is output in synchronization with the 9th clock falling edge of transfer SCKO automatically output when ACKE 1 Acknowledge signal is output in synchron
162. signals in the I2C mode These do not operate in the 3 wire serial I O mode and 2 wire serial I O mode 343 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Table 17 3 Serial Interface Channel 0 Interrupt Request Signal Generation Serial Transfer mode Description 3 wire or 2 wire serial I O An interrupt request signal is generated each mode time 8 serial clocks are counted Other than above Setting prohibited 12C bus mode transmit 0 0 1 An interrupt request signal is generated each time 8 serial clocks are counted 8 clock wait Normally during transmission the settings WAT21 WATO 1 0 are not used They are used only when wanting to coordinate receive time and processing systematically using software ACK information is generated by the receiving side thus ACKE should be set to 0 disable An interrupt request signal is generated each time 9 serial clocks are counted 9 clock wait ACK information is generated by the receiving side thus should be set to 0 disable Other than abov Setting prohibited 12 bus mode receive 1 0 1 An interrupt request signal is generated each time 8 serial clocks are counted 8 clock wait ACK information is output by manipulating ACKT by software after an interrupt request is generated An interrupt request signal is generated each time 9 serial clocks are counted 9 clock wait To automatically generate ACK information preset ACKE
163. space The CALLF addr11 instruction branches to an area of addresses 0800H through OFFFH Illustration In the case of CALL addr16 and BR addr16 instructions 7 0 CALL or BR Low Addr High Addr 15 8 7 0 PC In the case of CALLF addr11 instruction 113 CHAPTER 5 CPU ARCHITECTURE 5 3 3 Table indirect addressing Function Table contents branch destination address of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter PC and branched Before the CALLT addr5 instruction is executed table indirect addressing is performed This instruction references an address stored in the memory table at addresses 40H through 7FH and can branch in the entire memory space Illustration 7 6 5 1 0 15 8 7 6 5 10 1 10 1M 7 Memory Table 0 Low Addr Effective Address 1 High Adar 15 8 7 0 PC 114 CHAPTER 5 CPU ARCHITECTURE 5 3 4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Illustration 115 CHAPTER 5 CPU ARCHITECTURE 5 4 Operand Address Addressing The following various methods are available to specify the register and memory addressing
164. specified bit wise 1 2 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with a port mode register 1 PM1 If used as input ports on chip pull up resistors can be used to these ports by defining the pull up resistor option register L PUOL Control mode These ports function as A D converter analog input pins ANIO to ANI7 The on chip pull up resistor is automatically disabled when the pins specified for analog input 4 2 3 P20 to P27 Port 2 These are 8 bit input output ports Besides serving as input output ports they function as data input output to from the serial interface clock input output automatic transmit receive busy input and strobe output functions The following operating modes can be specified bit wise 1 2 84 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 2 PM2 When they are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL Control mode These ports function as serial interface data input output clock input output automatic transmit receive busy input and strobe output functions 10 SH SOO SO1 SBO SB1 SDAO SDA1 Serial interface serial data input output pins b SCKO SCK1 SCL Serial interface serial clock input output pins c BUSY S
165. switching register IMS 507 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22 2 External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register MM and memory size switching register IMS 1 Memory expansion mode register MM MM sets the wait count and external expansion area and also sets the input output of port 4 MM is set with an 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 10H Figure 22 2 Memory Expansion Mode Register Format After Symbol 7 6 5 Address Reset R W 4 3 2 1 0 Single chip P40 to P47 P50 to P57 P64 to P67 Pin state Memory Expansion Mode Selection P40 to 47 50 to P53 P54 P55 P56 P57 P64 to P67 Single chip mode Port mode 256 byte mode Port mode P64 RD 4K byte Port mode P65 WR Memory mode expansion P66 WAIT mode 16 Kbyte Port mode P67 ASTB mode Full address modeete Othe Setting prohibited No wait Wait one wait state insertion Setting prohibited Wait control by external wait pin Note The full address mode allows external expansion to the entire 64 Kbyte address space except for the internal ROM RAM and SFR areas and the reserved areas Remark P60 to P63 enter the port mode without regard to the mode single chip mode or memory expansion mode 508
166. that bits 0 and 3 to 6 are set to 0 461 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 b Asynchronous serial interface mode register ASIM ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM to OOH When the 3 wire serial I O mode is selected 00H should be set in ASIM Symbol 5 4 3 2 1 0 Address After Reset R W SCK Clock Selection in Asynchronous Serial Interface Mode Input clock from off chip to ASCK pin Dedicated baud rate generator output ISRM Control of Reception Completion Interrupt Request in Case of Error Generation Reception completion interrupt request generated in case of error generation Reception completion interrupt request not generated in case of error generation Transmit Data Stop Bit Length Specification 0 1 bit 1 2 bits Character Length Specification 0 7 bits 1 8 bits PSO Parity Bit Specification No Parity 0 parity always added in transmission No parity test in reception parity error not generated Odd parity Even parity Receive operation stopped Receive operation enabled Transmit operation stopped Transmit operation enabled 462 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 c Baud rate generator control register BRGC BRGC is set with an 8 bit memory manipulation instruction RESET input sets BRGC to 00H Symbol 7 6 5 4 3 Address After Reset R W 2 1 0 BRG
167. to 0 0 handshake control cannot be executed when the external clock is input Remark x Don t care 394 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 4 Automatic data transmit receive interval specify register ADTI This register sets the automatic data transmit receive function data transfer interval ADTI is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets ADTI to 00H Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format 1 4 Symbol 7 0 6 Address After Reset R W 5 4 3 2 1 0 ADTI ADTI7 0 ADTIS ADTIZ ADTH ADTIO FFeBH 00H R W Data Transfer Interval Control No control of interval by ADT Note 1 1 Control of interval by ADTI ADTIO to ADTI4 Data Transfer Interval Specification fxx 5 0 MHz Operation ADTI3 ADTI2 ADTI1 MinimumNete 2 MaximumNete 2 18 4 us 0 5 fsck 20 0 us 1 5 fsck 31 2 us 0 5 fsck 32 8 us 1 5 fsck 44 0 us 0 5 fsck 45 6 us 1 5 fsck 56 8u s 0 5 fscx 58 4 5 1 5 fsck 69 6 us 0 5 fsck 71 2 us 1 5 fsck 82 4 us 0 5 fsck 84 0 us 1 5 fsck 95 2 us 0 5 fsck 96 8 us 1 5 fsck 108 0 us 0 5 fsck 109 6 us 1 5 fsck 120 8 us 0 5 fsck 122 4 us 1 5 fsck 133 6 us 0 5 fsck 135 2 us 1 5 fsck 146 4 us 0 5 fsck 148 0 us 1 5 fsck 159 2 us 0 5 fsck 160 8 us 1 5 fsck 172 0 us 0 5 fsck 173 6 us 1 5 fsck
168. to Figure 17 22 Figure 17 26 Slave Wait Release Reception Master Device Operation Writing Software Operation data to 5100 pen Setting Hardware Operation 1 m CSIIFO NAE Serial Transmission y SCL 1 2 3 TRUE LX SN o Slave Device Slave Device Operation A P27 Write P27 Software Operation output FFH output ss 0 to a lach 1 ACK Setting Wait dS EE SERIE NN Md 382 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 4 Reception completion of salve In the reception completion processing of the slave check the bit 3 CMDD of the serial bus interface control register SBIC and bit 6 COI of the serial operation mode register 0 CSIMO when CMDD 1 This is to avoid the situation where the slave cannot judge which of the start condition and data comes first and therefore the wake up condition cannot be used when the slave receives the undefined number of data from the master 17 4 6 Restrictions in I2C bus mode The following restrictions are applied to the uPD78058FY Subseries e Restrictions when used as slave device in 12C bus mode Subject Description Preventive measure uPD78056FY 78058FY 78PO058FY IE 78064 R EMNete E 780308 R EM IE 780308 NS EM1 Note Maintenance product If the wake up function is executed by setting the bit 5 of the serial operating mode register 0 CSIMO to 1 in the serial transfer statusNete the u PD78058FY subseries checks the address
169. use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety e
170. where reduction of noise generated internally in the microprocessor is required please connect to a separate power supply with the same electrical potential as 2 The AVss pin is used as the ground potential for the A D converter and D A converter and also as the ground potential for the ports If this device is used in application fields where reduction of noise generated internally in the microprocessor is required please connect it to a ground line which is separate from Vss 63 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 3 1 2 PROM programming mode pins PROM versions only PROM programming mode setting When 5 V or 12 5 V is applied to the Ver pin or a low level voltage is applied to the RESET pin the PROM programming mode is set VPP Input High voltage application for PROM programming mode setting and program write verify AO to A16 Input Address bus to D7 Input output Data bus Input PROM enable input program pulse input Input Read strobe input to PROM Input Program program inhibit input in PROM programming mode Positive power supply Ground potential 64 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 3 2 Description of Pin Functions 3 2 1 POO to P07 Port 0 These are 8 bit input output ports Besides serving as input output ports they function as an external interrupt request input an external count clock input to the timer a capture trigger sign
171. with any communication format by program Communication is basically carried out with two lines of serial clock SCKO and serial data input output SBO or SB1 Figure 17 10 Serial Bus Configuration Example Using 2 Wire Serial I O Mode AVop AVop Master Slave SCKO SCKO SBO SB1 SBO SB1 1 Register setting The 2 wire serial I O mode is set with the serial operating mode register 0 CSIMO serial bus interface control register SBIC and interrupt timing specify register SINT 358 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES a Serial operating mode register 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Symb 5 4 3 Address After Reset R W 2 1 0 CSIMO CSIEO COI CSIMO03 CSIMO2 FF60H 00H R W Note 1 R W Serial Interface Channel 0 Clock Selection Input Clock to SCKO pin from off chip 8 bit timer register 2 TM2 output Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 CSIM Operation SIO SBO SDAO SOO SB1 SDA1 SCKO SCL P27 PM25 P25 26 P26 PM27 P27 Start Bit 2 03 P25 Pin Function P26 Pin Function Pin Function 3 wired serial I O mode see section 17 4 2 3 wire serial I O mode operation Note 2 Note 2 2 wire serial P25 CMOS SB1 SDA1 SCKO SCL mode input output N ch open drain N ch open drain or input output input ou
172. with output latch It can specify the input mode output mode in 1 bit units with a port mode register 1 PM1 When P10 to P17 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Alternate function includes an A D converter analog input RESET input sets port 1 to input mode Figure 6 4 shows a block diagram of port 1 Caution An on chip pull up resistor cannot be used for pins used as A D converter analog input Figure 6 4 P10 to P17 Block Diagram e WRPuo i 4 PUO1 34 m PR RD 3 1 a8 WRPonRT PERENNE 5 Output Latch ge P10 to P17 ae WRem E d PM10 to PM17 e PUO Pull up resistor option register Port mode register RD Port 1 read signal WR Port 1 write signal 132 CHAPTER 6 PORT FUNCTIONS 6 2 3 Port 2 uPD78058F Subseries Port 2 is an 8 bit input output port with output latch P20 to P27 pins can specify the input mode output mode in 1 bit units with the port mode register 2 PM2 When P20 to P27 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Alternate functions include serial interface data input output clock input output automatic transmit receive busy input and strobe output RESET input sets port 2 to input mode Figures 6 5 and 6 6 show bl
173. 058 uPD78058F A uPD78058FY uPD78058FY A O When you want to understand the functions in general Read this manual in the order of the contents O To know the uPD78058F and 78058FY Subseries instruction function in detail Refer to the 78K 0 Series User s Manual Instructions U12326E O How to interpret the register format For the circled bit number the bit name is defined as a reserved word in RA78K 0 and in CC78K 0 already defined in the header file named sfrbit h O To learn the function of a register whose register name is known Refer to APPENDIX D REGISTER INDEX O To know the electrical specifications of the uPD78058F and 78058FY Subseries Refer to separately available Data Sheet To know the details regarding the functions of the uPD78058F and 78058FY Subseries Refer to separately available Application Notes Caution Examples used in this manual are prepared for Standard product quality grade products for general electronic equipment If the examples of use in this manual are utilized in applications where a Special product quality grade is required please study concern ing the quality grade of each part and each circuit that will actually be used Chapter Organization This manual divides the descriptions for the uPD78058F and 78058FY Subseries into different chapters as shown below Read only the chapters related to the device you use Chapter uPD78058F Subseries uPD780
174. 0780924 n On chip inverter control circuit and UART EMI noise reduced version 78K 0 Series FIP drive 100 pin LPD780208 and FIP C D of the LPD78044F were enhanced Display output total 53 100 pin E 0780228 l O and FIP C D of the L PD78044H were enhanced Display output total 48 80 pin uPD78044H N ch open drain I O was added to the uPD78044F Display output total 34 80 pin LPD78044F Basic subseries for driving FIP Display output total 34 LCD drive 100 pin uPD780308 uPD780308Y SIO of the 78064 was enhanced ROM size and RAM size were expanded 100 pin LIPD78064B EMI noise reduced version of the L PD78064 100 pin 078064 uPD78064Y Subseries for driving LCDs On chip UART IEBus supported 80 pin LPD78098B EMI noise reduced version of the L PD78098 80 pin LPD78098 IEBus controller was added to the LPD78054 Meter control L 80 pin uPD780973 4 On chip controller driver for driving automobile meters Note Under planning 41 CHAPTER 1 OUTLINE uPD78058F SUBSERIES The differences between the major functions of each subseries are shown below Control ROM Timer Capacity uPD78075B 32K to 40 K 4 ch uPD78078 48Kt0 60K uPD78070A uPD780058 24K to 60 K 2 ch uPD78058F 48Kto 60 K uPD78054 16 K to 60K uPD780034 8 K to 32K uPD780024 uPD78014H uPD78018F 8 K to 60 K uPD78014 16 bit Watch Serial Interface 3 ch UAR
175. 1 fx 29 x 1 fx 224 x 1 fx 225 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 ps 8 4 s 6 7 s 51 2 us 102 4 us 29 x 1 fx 210 x 1 fx 225 x 1 fx 226 x 1 fx 29 x 1 fx 210 x 1 fx 102 4 ps 204 8 ps 6 7 s 13 4 s 102 4 us 204 8 ps 234 211 x 1 fx 212 x 1 fx 227 x 1 fx 228 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 26 8 s 53 7 s 409 6 us 819 2 us Remarks 1 fx Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 3 Values in parentheses when operated at fx 5 0 MHz CHAPTER 9 8 BIT TIMER EVENT COUNTERS Figure 9 13 Square Wave Output Operation Timing Count Clock FLELFLFLFLFLFLFLFLELFELTLELFLELELTELTLTLTLTLTLTLTLTLITTI 1 TM1 OOH 1019 INMI _ H E TE 1 TM2 00H OH DH 00H nex CR10 N CR20 TO2 Interval Time Count Start Level Inversion Counter Clear 235 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 9 5 Cautions on 8 Bit Timer Event Counters 1 Timer start errors An error of one clock maximum may occur concerning the time required for a match signal to be generated after timer start This is because the 8 bit timer registers 1 and 2 TM1 and TM2 are started asynchronously with the count pulse Figure 9 14 8 Bit Timer Registers Start Timing Count Pulse dA ey aa eee AA NR TM1 TM2 Count Value 00H 01H 02H 03H 04H
176. 12C Bus Multi Master compatible Vpop MIN Value uPD780058Y 24 K to 60 K 3 wire 2 wire l2C 3 wire with automatic send receive function 3 wire Time division UART uPD78058FY 48 K to 60 K uUPD78054Y 16 K to 60 K 3 wire 2 wire I C 3 wire with automatic send receive function 3 wire UART uPD780034Y 0780024 8 K to 32 UART 3 wire 12C Bus Multi Master compatible HPD78018FY 8 K to 60 K 3 wire 2 wire l2C 3 wire with automatic send receive function uPD78014Y 8Kto32K 3 wire 2 wire SBI I2C 3 wire with automatic send receive function uPD78002Y uPD780308Y 8Kto 16K 48 K to 60 K 3 wire 2 wire SBI I2C 3 wire 2 wire I C 3 wire Time division UART 3 wire 078064 16 K to 32 3 wire 2 wire I C 3 wire UART CHAPTER 2 OUTLINE uPD78058FY SUBSERIES 2 7 Block TOO P30 TIOO INTPO POO TIO1 INTP1 PO1 TO1 P31 TH P33 TO2 P32 TI2 P34 SIO SBO SDA0 P25 SO0 SB1 SDA1 P26 SCKO SCL P27 SI1 P20 SO1 P21 SCK1 P22 STB P23 BUSY P24 SI2 RxD P70 SO2 TxD P71 SCK2 ASCK P72 ANIO P10 to ANI7 P17 AVnero ANOO P130 ANO1 P131 AVss AVner INTPO POO to INTP6 P06 BUZ P36 PCL P35 Diagram 16 bit TIMER EVENT COUNTER 8 bit TIMER EVENT COUNTER 1 8 bit TIMER EVENT COUNTER 2 WATCHDOG TIMER WATCH TIMER SERIAL INTERFACE 0 SERIAL INTERFACE 1 SERIAL
177. 14 illustrates the operation above Figure 19 14 Receive Completion Interrupt Request Generation Timing When ISRM 1 fsck INTSER when Framing or Overrun Error is Generated a Error Flag Internal Flag Cleared Upon INTSR Reading RXB Interrupt Servicing Routine on CPU Side RXB Reading Judged no receive error has been generated and INTSR is generated Remark ISRM Bit 1 of asynchronous serial interface mode register ASIM fsck 5 bit counter source clock of baud rate generator RXB Receive buffer register To avoid this phenomenon implement the following countermeasures Countermeasures In the case of framing error or overrun error Prohibit the reading of the receive buffer register RXB for a certain period T2 in Figure 19 15 after the generation of a receive error interrupt request INTSER n the case of parity error Prohibit the reading of the receive buffer register RXB for a certain period T1 T2 in Figure 19 15 after the generation of a receive error interrupt request INTSER 468 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19 15 Period that Reading Receive Buffer Register Is Prohibited soo Y fX Xe Neeley START INTSR Lae INTSER when Framing or Overrun Error is Generated INTSER when Parity Error is Generated T1 T2 T1 The amount of time for one unit of data sent in the baud rate sele
178. 14 x 1 fx 3 28 ms 215 x 4 fxx 216 x 1 fx 13 1 ms 216 x 4 fxx 216 x 1 fx 13 1 ms 217 x 1 fx 26 2 ms 217 x 4 fxx 215 x 1 fx 6 55 ms 217 x 1 fx 26 2 ms 219 x 1 fx 6 55 ms 218 x 1 fx 52 4 ms 219 x 4 fxx Remarks 1 fxx 2 fx 219 x 1 fx 104 9 ms Main system clock frequency fx or fx 2 Main system clock oscillation frequency 220 x 1 fx 209 7 ms 3 MCS Bit 0 of oscillation mode selection register OSMS 4 Figures in parentheses apply to operation with fx 2 5 0 MHz 246 CHAPTER 11 WATCHDOG TIMER 11 2 Watchdog Timer Configuration The watchdog timer consists of the following hardware Table 11 3 Watchdog Timer Configuration Timer clock select register 2 TCL2 Control register Watchdog timer mode control register WDTM Figure 11 1 Watchdog Timer Block Diagram Internal Bus Prescaler fxx 2 INTWDT Maskable Interrupt Request RESET INTWDT 1 Non Maskable Interrupt Request 8 Bit Counter Control Circuit Selector Timer Clock Select Register 2 Watchdog Timer Mode Register 2 Internal Bus 247 CHAPTER 11 WATCHDOG TIMER 11 3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer Timer clock select register 2 TCL2 Watchdog timer mode register WDTM 1 Time
179. 155 CHAPTER 7 CLOCK GENERATOR 156 Figure 7 1 Block Diagram of Clock Generator FRC XT1 P07 XT2 Subsystem Watch Timer Clock T Clock Output Oscillator Function Pesci 1 2 Clock to Peripheral Hardware X1 2 Selector Standby Wait Control Control Circuit Circuit CPU Clock fcPu Selector To INTPO Sampling Clock iar aslo Processor Clock Control Register STOP MCS 4 Oscillation Mode Selection Register Internal Bus CHAPTER 7 CLOCK GENERATOR 7 3 Clock Generator Control Register The clock generator is controlled by the following two registers Processor clock control register PCC Oscillation mode selection register OSMS 1 Processor clock control register PCC The PCC sets whether to use CPU clock selection the ratio of division main system clock oscillator operation stop and subsystem clock oscillator internal feedback resistor The PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the PCC to 04H Figure 7 2 Subsystem Clock Feedback Resistor FRC P ch Feedback resistor Mi d M 157 CHAPTER 7 CLOCK GENERATOR Figure 7 3 Processor Clock Control Register Format After Symbol 0 3 2 1 Address Reset R W 0 MCC FRC CLS CSS PCC2 FFFBH 04H CPU Clock Selection fceu MCS 1 R W
180. 17 2 Serial Interface Channel 0 Configuration Serial I O shift register 0 SIOO Register Slave address register SVA Timer clock select register 3 TCL3 Serial operating mode register 0 CSIMO Control register Serial bus interface control register SBIC Interrupt timing specify register SINT Port mode register 2 PM2 Nete Note See Figure 6 7 P20 P21 P23 to P26 Block Diagram and Figure 6 8 P22 and P27 Block Diagram 340 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Figure 17 2 Serial Interface Channel 0 Block Diagram Internal Bus Serial Operating Mode Register 0 CSIM CSIM CSIM CSIM CSIM Slave Address Register SVA SVAM Match BSYE 510 5 0 SDAO P25 800 581 o PM25 Output Control P25 Output Latch O LN Serial I O Shift Register 0 SIOO Serial Bus Interface Control Register BSYE ACKD ACKT CMDD RELD CMDT RELT CLRSET D Q SDA1 P26 Selector PM26 Output Control 6 CLD P26 Output Latch SCKO e ScLip27 gt PM27 Stop Condition Start Condition Acknowledge Detector CE Output Control Acknowledge Output Circuit Interrupt Request A P27 Output Latch CSIMOO CSIMO1
181. 184 8 us 0 5 fsck 186 4 us 1 5 fsck 197 6 us 0 5 fsck 199 2us 1 5 fsck Notes 1 2 Cautions Remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 210 4 us 0 5 fscx 212 0 us 1 5 fsck The interval is dependent only on CPU processing The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value set in ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck Minimum n 1 x 25 28 05 Maximum n 1 x 26 36 15 fxx fxx fsck fxx fxx fsck Do not write ADTI during operation of automatic data transmit receive function 2 Bits 5 and 6 must be set to zero 3 Ifthe auto send and receive data transmission interval time is controlled using ADTI busy control becomes invalid see 18 4 3 4 a Busy control option 1 Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 fsck Serial clock frequency 395 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format 2 4 Symbol 7 6 5 4 3 2 1 0 Address After Reset R W ADTI JADTI7 0 0 JADTI4 ADTIS ADTI2 ADTH ADTIO FFEBH 00H R W Data Transfer Interval Specification fxx 5 0 MHz Operation ADTIS ADTI2 ADTI1 MinimumNete 223 2 us
182. 2 3 5 inch 2HC FD compatibles Windows English Netes 1 2 HP9000 series 700 HP UX Rel 9 05 DAT DDS SPARCstation SunOS Rel 4 1 4 8 5 inch 2HC FD 1 4 inch COMT NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD 1 4 inch CGMT Notes 1 Can be operated in DOS environment 2 Does not support WindowsNT 582 APPENDIX C EMBEDDED SOFTWARE Real time OS 2 2 MX78K0 HI TRON specification subset OS Nucleus of MX78KO0 is supplied OS This OS performs task management event management and time management It controls the task execution sequence for task management and selects the task to be executed next lt Precautions when using MX78KO under PC environment MX78KO0 is a DOS based application Therefore run the MX78KO0 from the DOS prompt under Windows Part number uS oxMX78K0 AAA Remark and AAA in the part number differ depending on the host machine and OS used LS xxxxMX78KO0 A A A Product Outline Evaluation object Upper Limit of Quantity for Mass Production Use for trial product Object for mass produced product Source program Host Machine Use for mass produced product Can be purchased only when object for mass produced product is purchased Supply Media PC 9800 Series Windows Japanese 5 2 35 inch 2HD FD IBM PC AT and compatibles Windows 2 3 5 inch 2HC FD Windows English Netes 1
183. 2 HP9000 series 700 HP UX Rel 9 05 SunOS Rel 4 1 4 DAT DDS 3 5 inch 2HC FD SPARCstation 1 4 inch CGMT 3 5 inch 2HC FD NEWS RISC NEWS OS Rel 6 1 Notes 1 Can be operated in DOS environment 2 Does not support WindowsNT 583 MEMO 584 APPENDIX D REGISTER INDEX D 1 Register Index Register Name A A D conversion result register ADCR ssessssssssssseseeeeenee eene nennen nnne nene nren nennt nnne enne nnns 264 A D converter input select register ADIS sssessssesseeeeeeene enne nennen nennt nennen nnne nnn nnns 267 A D converter mode register ADM nennen nennen nennen nennen nennen nnne 265 Asynchronous serial interface mode register ASIM 439 447 449 462 Asynchronous serial interface status register ASIS sssssssssssseeeeneneeeee nnne 441 450 Automatic data transmit receive address pointer ADTP seen 390 Automatic data transmit receive control register ssssssseeeeeeeeneneneenenene 394 405 Automatic data transmit receive interval specify register ADTI 395 406 B Baud rate generator control register BRGC sssssssssseeseeeeennneen enne 442 451 463 C Capture compare control register 0 sssssssssssssseseeeeeeneneeneee nennen nennt inns
184. 2 7 mm Mask ROM uPD78P058FGC 3B9 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm One time PROM HPD78P058FGC 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm One time PROM Remark xxx indicates ROM code suffix 36 CHAPTER 1 OUTLINE uPD78058F SUBSERIES 1 4 Quality Grade Part Number Package Quality Grade uPD78056FGC xxx 3B9 uUPD78056F GC xxx 8BT uPD78058FGC xxx 3B9 uUPD78058F GC xxx 8BT UPD78058F GK xxx BE9 78058 9 uPD78P058FGC 3B9 HPD78PO58FGC 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness Remark xxx indicates ROM code suffix 2 7 mm 1 4 mm 2 7 mm 1 4 mm 2 7 mm 2 7 mm 1 4 mm Standard Standard Standard Standard Standard Special Standard Standard Please refer to Quality grade on NEC Semiconductor Devices Document number C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 37 CHAPTER 1 OUTLINE uPD78058F SUBSERIES 1 5 Pin Configuration Top View 1 Normal operating mode 80 pin plastic QFP 14 x 14
185. 2 8 us 25 6 us 3 28 ms 6 55 ms 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 215 x 1 fx 218 x 1 fx 27 x 1 fx 28 x 1 fx 25 6 us 51 2 us 6 55 ms 13 1 ms 25 6 us 51 2 us 28 x 1 fx 29 x 1 fx 216 x 1 fx 217 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 us 13 1 ms 26 2 ms 51 2 us 102 4 us 29 x 1 fx 210 x 1 fx 217 x 1 fx 218 x 1 fx 29 x 1 fx 210 x 1 fx 102 4 us 204 8 us 26 2 ms 52 4 ms 102 4 us 204 8 us 211 x 1 fx 212 x 4 fx 219 x 4 fx 220 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 104 9 ms 209 7 ms 409 6 us 819 2 us Other than above Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 3 TCL14 to TCL17 Bits 4 to 7 of timer clock selection register 1 TCL1 4 Values in parentheses when operated at fx 5 0 MHz 227 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1 P33 and TI2 P34 pins with 8 bit timer registers 1 and 2 TM1 and TM2 TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register TCL1 is input Either the rising or falling edge can be selected When the TM1 and TM2 counted values match the values of 8 bit compare registers CR10 and CR20 TM1 and TM2 are cleared to 0 and th
186. 2 x 1 fx 22 x 1 fx 800 ns 1 6 us 26 2 ms 52 4 ms 400 ns 800 ns 23 x 1 fx 24 x 1 fx 218 x 1 fx 219 x 1 fx 22 x 1 fx 23 x 1 fx 1 6 us 3 2 us 52 4 ms 104 9 ms 800 ns 1 6 us 2 x watch timer output cycle 218 x watch timer output cycle Watch timer output edge cycle Remarks 1 fx Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 3 Values in parentheses when operated at fx 5 0 MHz 203 CHAPTER 8 16 TIMER EVENT COUNTER 8 5 7 One shot pulse output operation It is possible to output one shot pulses synchronized with a software trigger or an external trigger TIOO POO input 1 One shot pulse output using software trigger If the 16 bit timer mode control register TMCO capture compare control register 0 CRCO and the 16 bit timer output control register TOCO are set as shown in Figure 8 31 and 1 is set in bit 6 OSPT of TOCO by software a one shot pulse is output from the TOO P30 pin By setting 1 in OSPT the 16 bit timer event counter is cleared and started and output is activated by the count value set beforehand in 16 bit capture compare register 01 CRO1 Thereafter output is inactivated by the count value set beforehand in 16 bit capture compare register 00 CROO TMO continues to operate after one shot pulse is output To stop TMO 00H must be set to TMCO Caution When outputting one shot pulse do not set 1 in OSP
187. 2 x 12 mm Mask ROM uPD78058FYGC A xxx 3B9 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm Mask ROM uPD78P058FYGC 3B9 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm One time PROM uPD78PO58FYGC 8BTNote 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm One time PROM Note Under development Remark xxx indicates ROM code suffix 48 CHAPTER 2 OUTLINE uPD78058FY SUBSERIES 2 4 Quality Grade Part Number Package Quality Grade UPD78056FYGC xxx 3B9 UPD78056FYGC xxx 8BT UPD78058FYGC xxx 3B9 UPD78058FYGC xxx 8BT HPD78058FYGK xxx BE9 UPD78058FYGC A xxx 3B9 UPD78P058FYGC 3B9 uPD78P058FYGC 8BTNote Note Under development 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness Remark xxx indicates ROM code suffix 2 7 mm 1 4 mm 2 7 mm 1 4 mm 2 7 mm 2 7 mm 1 4 mm Standard Standard Standard Standard Standard Special Standard Standard Please refer to Quality grade on NEC Semiconductor Devices Document number C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications
188. 3 Ox k x 14 Table 19 3 Relationship Between Main System Clock and Baud Rate fx 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error 96 BRGC Set Value Error 96 MCS Oscillation mode selection register OSMS bit 0 444 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 b Generation of baud rate transmit receive clock by means of external clock from ASCK pin The transmit receive clock is generated by scaling the clock input from the ASCK pin The baud rate generated from the clock input from the ASCK pin is obtained with the following expression fasck Baud rate Hz 2 x 16 fasck Frequency of clock input to ASCK pin k Value set in MDLO to MDL3 0 lt k x 14 Table 19 4 Relationship Between ASCK Pin Input Frequency and Baud Rate When BRGC Is Set to 00H Baud Rate bps ASCK Pin Input Frequency 2 4 kHz 3 52 kHz 4 8 kHz 9 6 kHz 19 2 kHz 38 4 kHz 76 8 kHz 153 6 kHz 307 2 kHz 614 4 kHz 1000 0 kHz 1228 8 kHz 445 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes Operation stop mode Asynchronous serial interface UART mode 3 wire serial I O mode 19 4 1 Operation stop mode
189. 3 7 s 409 6 us 819 2 us Remarks 1 fx Main system clock oscillation frequency 2 MCS BitO of oscillation mode selection register OSMS 3 Values in parentheses when operated at fx 5 0 MHz 214 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 2 External event counter The number of pulses of an externally input signal can be measured 3 Square wave output A square wave with any selected frequency can be output Table 9 4 Square Wave Output Ranges When 8 Bit Timer Event Counters are Used as 16 Bit Timer Event Counter Minimum Pulse Width Maximum Pulse Width Resolution 2 x 1 fx 400 ns 22 x 1 fx 800 ns MCS 1 217 x 1 fx 26 2 ms MCS 0 218 x 1 fx 52 4 ms MCS 1 2 x 1 fx 400 ns MCS 0 22 x 1 fx 800 ns 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 218 x 1 fx 52 4 ms 219 x 1 fx 104 9 ms 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 23 x 1 fx 1 6 us 24 x 1 fx 3 2 us 219 x 1 fx 104 9 ms 220 x 1 fx 209 7 ms 23 x 1 fx 1 6 us 24 x 1 fx 3 2 us 24 x 1 fx 3 2 us 25 x 1 fx 6 4 us 220 x 1 fx 209 7 ms 221 x 1 fx 419 4 ms 24 x 1 fx 3 2 us 25 x 1 fx 6 4 us 25 x 1 fx 6 4 us 26 x 1 fx 12 8 us 221 x 1 fx 419 4 ms 222 x 1 fx 838 9 ms 25 x 1 fx 6 4 us 26 x 1 fx 12 8 us 26 x 1 fx 12 8 us 2 x 1 fx 25 6 us 222 x 4 fx
190. 3 wire serial 500 SCKO CMOS mode CMOS output input output SBI mode see section 16 4 3 SBI mode operation 2 wire serial mode see section 16 4 4 2 wire serial I O mode operation Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the slave address register SVA data in SBI mode Operation stopped Operation enabled Notes 1 Bit 6 COI is a read only bit 2 Can be used as P25 CMOS input output when used only for transmission 3 Be sure to set WUP to 0 when the 3 wire serial I O mode is selected Remark x don t care Port Mode Register PXX Port Output Latch 301 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES b Serial bus interface control register SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H symbol gt Address After Reset R W SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R W R W When RELT 1 SOO latch is set to 1 After 500 latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 CMDT When 1 500 latch is cleared to 0 After SOO latch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 302
191. 320 16 25 BSYE Operation Uere ae Beta 320 16 26 Pin iGonfigurationis i ico e ep e ab DE EEG ee 323 26 LIST OF FIGURES 5 8 Figure No Title Page 16 27 Address Transmission from Master Device to Slave Device WUP 1 325 16 28 Command Transmission from Master Device to Slave Device 326 16 29 Data Transmission from Master Device to Slave Device 327 16 30 Data Transmission from Slave Device to Master Device ssseeee 328 16 31 Serial Bus Configuration Example Using 2 Wire Serial I O Mode 331 16 32 2 Wire Serial Mode Timings essen nennen nnne nnne nnne nnne 334 16 33 REET and GMBT Operations e ae E a e 335 10 347 SCKO P27 Pin Corifigurati n 5 e Re eta np idet an t ed ict 336 17 1 Serial Bus Configuration Example Using 1 Bus cecceceeceeceeeeeeeceeeceecaeeaeeaecaesaeeaseateeeeeseeteeeeees 339 17 2 Serial Interface Channel 0 Block Diagram ssssessssseseeeeeeenenennennenennene nennen nnne 341 17 3 Timer Clock Select Register Format ccccseceeeeeeeeeeeeeecneeeeeeeeneeeeaeeeeeseaeeseeeseaeeseeeeeaeessaeeneeeneees 346 17 4 Serial Operating Mode Register 0 Format c cceeceeeeeseeseeeeeeeeeene
192. 454 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 2 Communication operation a Data format The transmit receive data format is as shown in Figure 19 7 Figure 19 7 Asynchronous Serial Interface Transmit Receive Data Format Data Frame gt Character Bits 1 data frame is composed of each of the bits shown below Start bits 1 bit Character bits 7 bits 8 bits e Parity bits Even parity odd parity O parity no parity Stop bit s 1 bit 2 bits The character bit length parity selection and stop bit length for each data frame is specified with the asynchronous serial interface mode register ASIM When 7 bits are selected as the number of character bits only the lower 7 bits bits O to 6 are valid in transmission the most significant bit bit 7 is ignored and in reception the most significant bit bit 7 is always 0 The serial transmission rate is set by ASIM and the baud rate generator control register BRGC If a serial data receive error is generated the receive error contents can be determined by reading the status of the asynchronous serial interface status register ASIS 455 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 456 b Parity types and operation The parity bit is used to detect a bit error in the communication data Normally the same kind of parity bit is used on the transmitting side and the receiving side With
193. 535 CHAPTER 25 ROM CORRECTION 25 7 536 Cautions on ROM Correction Address values set in correction address registers 0 and 1 CORADO and CORAD1 must be addresses where instruction codes are stored Correction address registers 0 and 1 CORADO and CORAD1 should be set when the correction enable flags CORENO COREN1 0 when correction branch processing is disabled If address is set to CORADO or CORAD1 when CORENO or COREN is 1 when the correction branch is in enabled state the correction branch may start with the different address from the set address value Do not set the address value of instruction immediately after the instruction that sets the correction enable flag CORENO COREN1 to 1 to correction address register 0 or 1 CORADO CORAD 1 the correction branch may not start Do not set the address value in table area of table reference instruction CALLT instruction 0040H to 007FH and the address value in vector table area 0000H to 003FH to correction address registers 0 and 1 CORADO CORAD 1 Do not set two addresses immediately after the instructions shown below to correction address registers 0 and 1 CORADO CORAD1 that is when the mapped terminal address of these instructions is N do not set the address values of N 1 and N 2 RET RETI RETB BR addr16 STOP HALT CHAPTER 26 uPD78P058F 78P058FY The uPD78P058F and 78P058FY are products which have one time PROM inco
194. 538 Oscillation mode selection register OSMS cecceeeceseeeeeeeeeeeeeeneeeeeeecaeeseeeeeaeesaeesaeeseaeeseeeseaeesaeeeeaeesieeseeeeeees 159 Oscillation stabilization time select register OSTS 516 P Port O uiu BUE EIL M 130 PORT cit oto cim aet ode o rte tis coena os eet 132 Port 12 P 12 itte t oe dde e abe RR ed p aet a ong 144 Port 19 ao cct Ds coe nacer rca ah erage diete eet E 145 Port 24B2 icon een ae meinem utate 133 Port 3 B3 esee e UR a ed eate atio e e e ir eei eene 137 Port E 138 Port S dE TE a cc tete A t sd ee a es 139 Porte zi eee ce ate ree eae A ee ae 140 Port 7 B7 pe ede ents ee ee eee 142 Poft mode register 0 PMQ teen tetti er De ea Te EU ea e nebat dion alte ceux tutu 130 146 Port mode register T PMT iiia isi cene REB UE OR HU HORE ER EHE AR 130 146 Port mode register 12 PM12 cpm e evi cR Te DEP Le ntti Re ET a YR Se cnet 130 146 474 Port mode register T9 PM T3 aient eret ttt lee ent tuer rt aca tle Eds 130 146 Port mode register 2 PM e ree der Ete ei e voca co Y Tete eee Ye elena alee 130 146 Portmode register 3 PMS s ttc e te ie neun eed 130 146 184 224 256 260 Portimode register 5 PMB iiio eco te LEER 130 146
195. 58FY SUBSERIES 17 4 2 3 wire serial I O mode operation The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K Series Communication is carried out with three lines of serial clock SCKO serial output SOO and serial input SIO 1 Register setting The 3 wire serial I O mode is set with the serial operating mode register 0 CSIMO and serial bus interface control register SBIC a Serial operating mode register 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Symb 75 4 Address After Reset R W com em repe mm om R W Serial Interface Channel 0 Clock Selection Input Clock to SCKO pin from off chip 8 bit timer register 2 TM2 output Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 CSIM CSIM CSIM Operation SIO SBO SDAO SO0 SB1 SDA1 SCKO SCL P27 PM25 P25 PM26 P26 PM27 P27 Start Bit 04 03 02 Mode P25 Pin Function P26 Pin Function Pin Function 3 wire serial silo Noe Soo SCKO CMOS mode Input CMOS output input output 2 wired serial mode see the section 17 4 3 2 wire serial I O mode operation or C bus mode see the section 17 4 4 bus mode operation Wake up Function Control
196. 58FY Subseries Chapter 1 Outline uPD78058F Subseries Chapter 2 Outline uPD78058FY Subseries Chapter 3 Pin Function uPD78058F Subseries Chapter 4 Pin Function uPD78058FY Subseries Chapter 5 CPU Architecture Chapter 6 Port Functions Chapter 7 Clock Generator Chapter 8 16 Bit Timer Event Counter Chapter 9 8 Bit Timer Event Counter Chapter 10 Watch Timer Chapter 11 Watchdog Timer Chapter 12 Clock Output Control Circuit Chapter 13 Buzzer Output Control Circuit Chapter 14 A D Converter Chapter 15 D A Converter Chapter 16 Serial Interface Channel 0 uPD78058F Subseries Chapter 17 Serial Interface Channel 0 uPD78058FY Subseries Chapter 18 Serial Interface Channel 1 Chapter 19 Serial Interface Channel 2 Chapter 20 Real Time Output Port Chapter 21 Interrupt and Test Functions Chapter 22 External Device Expansion Function Chapter 23 Standby Function Chapter 24 Reset Function Chapter 25 ROM Correction Chapter 26 uPD78P058F uPD78P058FY ay ae ey ay ae ey Chapter 27 Instruction Set Differences between PD78058F and uPD78058FY Subseries The uPD78058F and uPD78058FY Subseries are different in the following functions of the serial interface channel 0 Modes of Serial Inte
197. 61 PM60 FF26H FFH R W PM12 JPM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120 FF2CH FFH R W PMmn Pmn Pin Input Output Mode Selection m 0 to 3 5 to 7 12 13 n 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF 148 CHAPTER 6 PORT FUNCTIONS 2 Pull up resistor option register PUOH PUOL This register is used to set whether to use an internal pull up resistor at each port or not A pull up resistor is internally used at bits which are set to the input mode at a port where on chip pull up resistor use has been specified with PUOH PUOL No on chip pull up resistors can be used to the bits set to the output mode or to the bits used as an analog input pin irrespective of PUOH or PUOL setting PUOH and PUOL are set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to Cautions 1 P00 and P07 pins do not incorporate a pull up resistor 2 When ports 1 4 5 and P64 to P67 pins are used as dual function pins an on chip pull up resistor cannot be used even if 1 is set in PUOm bit of PUOH PUOL m 1 4 to 6 3 Pins P60 to P63 can be connected with pull up resistor by mask option only for mask ROM version Figure 6 20 Pull Up Resistor Option Register Format After Symbol 7 6 Qe 3 2 Address Reset R W 1 0 PUOH 0 PUOI3PUOI2 0 FFF3H 00H R W 0 o PUOL PUO7 PUO6 PUO5 PUO4 PUO3 PUO2 PUO1 PUOO FFF7H 00H R W
198. 8 Figure B 3 EV 9200GC 80 Footprints For Reference Only Based on EV 9200GC 80 2 Pad drawing in mm EV 9200GC 80 P1 ITEM MILLIMETERS INCHES A 19 7 0 776 B 15 0 0 591 C 0 6550 02 x 19 12 35 0 05 0 026 0002 x 0 748 0 486 5 553 D 0 65 0 02 x 19 12 35 0 05 0 026090 x 0 748 0 486 0 002 E 15 0 0 591 F 19 7 0 776 G 6 0 0 05 0 236099 H 6 00 05 0 236 0005 0 35 0 02 0 014090 02 36 0 03 90 093090 K 2 3 90 091 L 01 57 0 03 0 062 0003 Caution Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer to SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL C10535E APPENDIX B DEVELOPMENT TOOLS Drawing of Conversion Adapter TGK O80SDW Figure B 4 TGK 080SDW Drawings For Reference unit mm Reference diagram TGK 080SDW Package dimension unit mm
199. 8 BIT TIMER EVENT COUNTERS Table 9 6 8 Bit Timer Event Counter 1 Interval Time Minimum Interval Time Maximum Interval Time Resolution TCL12 TCL11 TCL10 TI1 input cycle 28 x TI1 input cycle TI input edge cycle TI1 input cycle 28 x TH input cycle TI1 input edge cycle 2 x 1 fx 2 x 1 fx 29 x 1 fx 210 x 1 fx 2 x 1 fx 22 x 1 fx 400ns 800ns 102 4 us 204 8 us 400ns 800 ns 22 x 1 fx 23 x 1 fx 210 x 1 fx 211 x 1 fx 22 x 1 fx 23 x 1 fx 800ns 1 6 204 8 us 409 6 us 800ns 1 6 us 23 x 1 fx 24 x 1 fx 211 x 1 fx 212 x 1 fx 23 x 1 fx 24 x 1 fx 1 6 us 3 2 us 409 6 us 819 2 us 1 6 us 8 2 us 24 x 1 fx 25 x 1 fx 212 x 1 fx 213 x 1 fx 24 x 1 fx 25 x 1 fx 8 2 us 6 4 us 819 2 us 1 64 ms 3 2 us 6 4 us 25 x 1 fx 26 x 1 fx 213 x 1 fx 214 x 1 fx 25 x 1 fx 26 x 1 fx 6 4 us 12 8 us 1 64 ms 3 28 ms 6 4us 12 8 us 26 x 1 fx 27 x 1 fx 214 x 1 fx 215 x 1 fx 26 x 1 fx 27 x 1 fx 12 8 us 25 6 us 8 28ms 6 55 ms 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 215 x 1 fx 218 x 1 fx 27 x 1 fx 28 x 1 fx 25 6 us 51 2 us 6 55 ms 13 1 ms 25 6 us 51 2 us 28 x 1 fx 29 x 1 fx 216 x 1 fx 217 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 us 13 1 ms 26 2 ms 51 2 us 102 4 us 29 x 1 fx 210 x 1 fx 217 x 1 fx 218 x 1 fx 29 x 1 fx 210 x 1 fx 102 4 us 204 8 us 26 2 ms 52 4 ms 102 4 us 204 8 us 211 x 1 fx 212 x 4 f
200. 88H R W R W Serial Interface Channel 0 Serial Clock Selection bo 25 Serial Clock in IPC Bus Mode MCS 1 Setting prohibited MCS 0 fx 28 78 1 kHz Serial Clock in 2 Wire or 3 Wire Serial I O Mode MCS 1 Setting prohibited MCS 0 fx 22 1 25 MHz bo 25 fx 28 78 1 kHz fx 27 39 1 kHz fx 22 1 25 MHz fx 23 625 kHz fxx 27 fx 27 39 1 kHz fx 28 19 5 kHz fx 23 625 kHz fx 24 313 kHz bo 28 fx 28 19 5 kHz fx 29 9 77 kHz fx 24 313 kHz fx 25 156 kHz fxw 29 fx 29 9 77 kHz fx 210 4 88 kHz fx 25 156 kHz fx 28 78 1 kHz bo 210 fx 210 4 88 kHz fx 2 2 44 kHz fx 25 78 1 kHz fx 27 39 1 kHz bo 2 fx 211 2 44 kHz fx 2 1 22 kHz fx 27 39 1 kHz 5 28 19 5 kHz bo 21 fx 21 1 22 kHz fx 213 0 61 kHz fx 28 19 5 kHz fx 29 9 8 kHz Setting prohibited Serial Interface Channel 1 Serial Clock Selection MCS 1 bo 2 Setting prohibited MCS 0 fx 22 1 25 MHz fxx 22 fx 22 1 25 MHz fx 23 625 kHz fxw 23 fx 23 625 kHz fx 24 313 kHz fxw 24 fx 2 313 kHz fx 25 156 kHz fxx 25 fx 25 156 kHz fx 28 78 1 kHz fxx 28 fx 26 78 1 kHz fx 27 39 1 kHz fxw 2 fx 2 39 1 kHz fx 28 19 5 kHz fxx 28 fx 28 19 5 kHz fx 29 9 8 kHz Remarks 1 O
201. 9 4 Relationship Between ASCK Pin Input Frequency and Baud Rate When BRGC Is Set to OOH 445 19 5 Relationship Between Main System Clock and Baud Rate 453 19 6 Relationship Between ASCK Pin Input Frequency and Baud Rate When BRGC Is Set to OOH 454 19 7 Receive Error Calls6s e el riae Meh ets eg lac ile POE ERR RH DR Ie nay 459 20 1 Real time Output Port Configuration esessssssessseeseeeeeeeneenee enne nennen 472 32 LIST OF TABLES 3 3 Table No Title Page 20 2 Operation in Real time Output Buffer Register Manipulation 473 20 3 Real time Output Port Operating Mode and Output Trigger 475 21 1 Interrupt Source List 25 modera es tutta deba edt fot LL de tote tus 478 21 2 Various Flags Corresponding to Interrupt Request Sources ssesseeene 482 21 3 Times from Maskable Interrupt Request Generation to Interrupt Service 494 21 4 Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing 498 21 5 Test Input gr oo E 502 21 6 Flags Corresponding to Test Input Signals ecceeeeeeeeeeeeeeeeseeeeeeeeeaeesaeeseaeeseeeeaeeseeeeeaeeseaeeeaeeeaas 502 22 1 Pin Functions in External Memory Expansion Mode
202. APTER 5 CPU ARCHITECTURE inen 95 5 1 USATE REED 95 5 1 1 Internal program memory space 98 5 1 2 Internal data memory 99 5 1 3 Special Function Register SFR area ssssssssssssseeeeeeenennee nennen nnne nennen nennen 99 5 1 4 Externalmemory space 99 5 1 5 Data memory addressing A 100 5 2 Ptocessor Registers ecciesie 103 16 52 1 Control registers siate dete d e iet eta eel 103 5 22 Generaliregisters idee p e DARE eR ie E RR IRL MEE NEP pan obe d 106 5 2 9 Special Function Register SER aire ee e E 108 5 3 Instruction Address Addressing eese eene nena 112 5 81 Relative addressing ie repond e E EO Ep C 112 5 3 2 Imimediate addressirig senile ie ese e ee 113 5 9 9 Tabl indirect addressing aene ree P e rtt te ee 114 5 3 4 Register addressing OE RHENUM RUTAS TETT 115 5 4 Operand Address Addressing 116 bt Implied addressing resar e aaeeea te aa RI qi ia DIEA 116 542 Register addressirig 5 nn atta deine ec
203. ASCK P120 to P127 Port 12 RTPO to RTP7 8 bit input output port Input output mode can be specified bit wise If used as an input port on chip pull up resistor can be used by software Port 13 ANOO ANO1 2 bit input output port Input output mode can be specified bit wise If used as an input port on chip pull up resistor can be used by software Cautions For pins which have alternate functions as port output See 4 1 1 Normal operating mode pins 1 Port Pins do not execute the following operations during A D conversion If performed then the general error standards cannot be maintained during A D conversion 1 If it is used as a port rewriting the output latch of its output 2 Even if it is not used as a port changing the output level of pins used as outputs 129 CHAPTER 6 PORT FUNCTIONS 6 2 Port Configuration A port consists of the following hardware Table 6 3 Port Configuration Control register Port mode register PMm m 0 to 3 5 to 7 12 13 Pull up resistor option register PUOH PUOL Memory expansion mode register MM Nete Key return mode register KRM Port Total 69 ports 2 inputs 67 inputs outputs Pull up resistor Mask ROM version Total 67 Software control 63 Mask option control 4 PROM version Total 63 Note specifies I O for port 4 6 2 1 Port 0 Port 0 is an 8 bit input output port with output latch P01 to PO6 pins can specify th
204. BC AX 15 0 FEFFH FEF8H FEF7H FEFOH FEEFH FEE8H FEE7H FEEOH 107 CHAPTER 5 CPU ARCHITECTURE 5 2 3 Special Function Register SFR Unlike a general register each special function register has special functions It is allocated in the FFOOH to FFFFH area The special function register can be manipulated like the general register with the operation transfer and bit manipulation instructions Manipulatable bit units 1 8 and 16 depend on the special function register type Each manipulation bit unit can be specified as follows 1 bit manipulation Describe the symbol reserved with assembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified with an address 8 bit manipulation Describe the symbol reserved with assembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 5 3 gives a list of special function registers The meaning of items in the table is as follows Symbol Symbols indicating the addresses of special function register These symbols are reserved words for the RA78K 0 and defined by header file sfrbit h for the CC78K 0 and can be used as the operands of instructions when
205. Bus Notes 1 Selector to select the number of channels to be used for analog input 2 Selector to select the channel for A D conversion 3 Bits 0 and 1 of External Interrupt Mode Register 1 INTM1 263 CHAPTER 14 A D CONVERTER 1 2 3 4 5 6 264 Successive approximation register SAR The analog input voltage value and the voltage tap comparative voltage value from the serial resistance string are compared and the results are stored in this register from the most significant bit MSB If values are stored to the least significant bit LSB after A D conversion the contents of the SAR are transferred to the A D conversion results register ADCR A D conversion result register ADCR This register holds the A D conversion result Each time A D conversion terminates the conversion result is loaded from the successive approximation register SAR ADCR is read with an 8 bit memory manipulation instruction RESET input makes ADCR undefined Sample amp hold circuit The sample amp hold circuit samples each analog input signal sequentially applied from the input circuit and sends it to the voltage comparator This circuit holds the sampled analog input voltage value during A D conversion Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage Series resistor string The serial resistance string is connected between AVrero and AVss
206. C TPS3 TPS2 51 TPSO MDL3 MDL2 MDL1 MDLO FF73H 00H R W MDLO Baud Rate Generator Input Clock Selection k 16 fsck 17 fsck 18 fsck 19 fsck 20 fsck 21 fsck 22 fsck 23 fsck 24 fsck 25 fsck 26 fsck 27 fsck 28 fsck 29 fsck 30 fsck continued fsck 5 bit counter source clock k Value set in MDLO to MDL3 0 lt k x 14 463 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 5 Bit Counter Source Clock Selection MCS 1 MCS 0 XX X i 2 2 fxx 210 fx 210 4 9 kH 2 4 kH fxx fx 5 0 MHz 2 5 MHz fxx 2 fx 2 2 5 MHz 1 25 MHz 22 fx 2 1 25 MHz 625 kHz fxx 23 fx 23 625 kHz 313 kHz 156 kHz 156 kHz 78 1 kHz fxx 25 fx 25 fxx 26 fx 26 78 1 kHz 39 1 kHz 27 fx 27 39 1 kHz 19 5 kHz o IO A A N fxx 28 fx 28 19 5 kHz 9 8 kHz fxx 24 fx 2 313 kHz fxx 29 fx 29 9 8 kHz 4 9 kHz E Other than above Setting prohibited Note f data is written to BRGC during a communication operation the baud rate generator output is disrupted and communication cannot be performed normally Therefore do not write data to BRGC during a communication operation Remarks 1 fx Main system clock oscillation frequency 2 fx Main system clock frequency fx or fx 2 3 MCS
207. CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand laddr16 laddri 1 addr5 addr16 First Operand Basic instruction Compound instruction 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP El DI HALT STOP 563 MEMO 564 APPENDIX A DIFFERENCES AMONG 4PD78054 78058F AND 780058 SUBSERIES The major differences among the uPD78054 78058F and 780058 Subseries are shown in Table 1 Table 1 Major Differences Among uPD78054 78058F and 780058 Subseries 1 2 Product Name EMI noise countermeasure uPD78054 Subseries No UPD78058F Subseries Yes uPD780058 Subseries Yes Power supply voltage Voo 2 0 to 6 0 V Voo 2 7 to 6 0 V Voo 1 8 5 5 V PROM versions UPD78P054 78P058 uPD78P058F No Flash memory versions No No uPD78F0058 Internal ROM size uPD78052 uPD78053 uPD78054 uPD78P054 uuPD78056 uPD78058 16 Kbytes 24 Kbytes 32 Kbytes 32 Kbytes 48 Kbytes 60 Kbytes HPD78P058 60 Kbytes LPD78056F 48 Kbytes HPD78058F 60 Kbytes LuPD78P058F 60 Kbytes uPD780053 uPD780054 uPD780055 HPD780056 48 Kbytes HPD780058 60 Kbytes HPD78F0058 60 Kbytes 24 Kbytes 32 Kbytes 40 Kbytes Internal high speed RAM size HPD78052 512 bytes 078053 78054 78P054 78056 78058 78P058 1024 bytes 1024 bytes 1024 bytes port Total CM
208. CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 fxt Subsystem clock oscillation frequency 4 TIOO 16 bit timer event counter input pin 5 TMO 16 bit timer register 6 MCS Bit 0 of oscillation mode selection register OSMS 7 Figures in parentheses apply to operation with fx 5 0 MHz or fxr 32 768 kHz 2 Port mode register 3 PM3 This register set port 3 input output in 1 bit units When using the P35 PCL pin for clock output function set PM35 and output latch of P35 to 0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 12 4 Port Mode Register 3 Format After Symbol 7 6 Reset Address R W 5 4 3 2 1 0 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W PM3n P3n Pin Input Output Mode Selection n 0 to 7 Output mode output buffer ON Input mode output buffer OFF 256 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13 1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1 2 kHz 2 4 kHz 4 9 kHz or 9 8 kHz frequency square waves The buzzer frequency selected with timer clock select register 2 TCL2 is output from the BUZ P36 pin Follow the procedure below to output the buzzer frequency 1 Select the buzzer output frequency with bits 5 to 7 TCL25 to TCL27 of TCL2 2 Set
209. CPU Processing Instruction Divide Instruction Jump to Interrupt Servicing Servicing Program x x PR 1 33 Clocks EL 5 5 55 queque o x x PR 0 32 Clocks Remark 1 clock a fcpu CPU clock fcPu 496 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 4 3 Software interrupt request acknowledge operation A software interrupt request is received by the execution of a BRK command A software interrupt cannot be prohibited If a software interrupt request is received the contents of the program status word PSW and the program counter PC are saved to the stack in that order the IE flag is reset 0 and the contents of the vector table OO3EH 003FH are loaded in the PC and branched Return from the software interrupt is possible with the RETB instruction Caution Do not use the RETI instruction for returning from the software interrupt 21 4 4 Multiple interrupt servicing During interrupt processing the capacity to receive other distinct interrupt requests is called multiple interrupts Multiple interrupts are not generated except for nonmaskable interrupts unless reception of an interrupt request is permitted IE 1 Also at the point when an interrupt request is received further reception of an interrupt request is prohibited IE 0 Therefore to permit multiple interrupts it is necessary to set the IE flag at 1 by the IE command during interrupt processing and permit interrupt reception Al
210. CS 1 MCS 0 4 9 kHz 2 4 kHz 5 0 MHz 2 5 MHz 2 5 MHz fxx 210 fx 210 fxx fx fxx 2 fx 2 1 25 MHz fxx 22 fx 22 1 25 MHz 625 kHz 313 kHz 156 kHz 156 kHz 78 1 kHz fxx 23 fx 23 625 kHz fxx 25 fx 25 fxx 28 fx 26 78 1 kHz 39 1 kHz 19 5 kHz 9 8 kHz 4 9 kHz 27 fx 27 39 1 kHz o IO A A N fxx 28 fx 28 19 5 kHz fxx 24 fx 2 313 kHz fxx 29 fx 29 9 8 kHz E Other than above Setting prohibited Caution If data is written to BRGC during a communication operation the baud rate generator output is disrupted and communication cannot be performed normally Therefore do not write data to BRGC during a communication operation Remarks 1 fx Main system clock oscillation frequency 2 fx Main system clock frequency fx or fx 2 3 MCS Bit 0 of oscillation mode selection register OSMS 4 n Value set in TPSO to TPS3 1 nx 11 5 Figures in parentheses apply to operation with fx 5 0 MHz 452 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit receive clock generated is either a signal scaled from the main system clock or a signal scaled from the clock input from the ASCK pin i Generation of baud rate transmit receive clock by means of main system clock The transmit receive clock is generated by scaling the main system clock The baud rate
211. D conversion operation and starts A D conversion on the newly written data If data with CS set to 0 is written to ADM during A D conversion the A D conversion operation stops im mediately Figure 14 8 A D Conversion by Software Start Conversion Start ADM Rewrite ADM Rewrite CS 1 TRG 0 CS 1 TRG 0 CS 0 TRG 0 A D Conversion ANIn ANIn ANIm ANIm I Conversion suspended Conversion results are Stop not stored lI ada INTAD Remarks 1 n 0 1 7 2 m 0 1 7 273 CHAPTER 14 A D CONVERTER 14 5 A D Converter Cautions 1 Power consumption in standby mode The A D converter operates on the main system clock Therefore its operation stops in STOP mode or in HALT mode with the subsystem clock As a current still flows in the AVrero pin at this time this current must be cut in order to minimize the overall system power dissipation In Figure 14 9 the power dissipation can be reduced by outputting a low level signal to the output port in standby mode However there is no precision to the actual AVrero voltage and therefore the conversion values themselves lack precision and can only be used for relative comparison Figure 14 9 Example of Method of Reducing Current Consumption in Standby Mode AVopb Output Port 77T 4 PD78058F 78058FY AVss AVnero 5 Series Resistor String AVss 2 Input range of ANIO to ANI7 274 The input v
212. D78058FY SUBSERIES Figure 4 1 List of Pin Input Output Circuit 2 2 Mask T pullup enable 0 IN OUT data output disable J gt N ch 77 AVss output disable input enable analog output voltage gnum medium breakdown input buffer feedback gt 9IN OUT cut off data output disable LI po N ch P ch 77 AVss AW o medium breakdown input buffer 94 CHAPTER 5 CPU ARCHITECTURE 5 1 Memory Spaces 64 Kbyte memory spaces can be accessed in the u PD78058F 78058FY Subseries Figures 5 1 to 5 3 show memory maps Figure 5 1 Memory Map uPD78056F 78056FY Special Function Registers SFRs 256 x 8 bits General Registers 32 x 8 bits Internal High speed RAM 1024 x 8 bits FBOOH FAFFH Reserved FAEOH FADFH BFFFH Internal Buffer RAM 32 x 8 bits Program Area FACOH Data memory FABFH R d 1000H eserve space OFFFH FA7FH CALLF Entry Area 0800H External Memory 07FFH 14976 x 8 bits Program Area Program memory 0080H Te 007FH C000H CALLT Table Area Internal ROM 49152 x 8 bits Vector Table Area Y Y 0000H 0000H 95 CHAPTER 5 CPU ARCHITECTURE Figure 5 2 Memory Map uPD78058F 78058FY Special Function Registers SFRs 256 x 8 bits General Registers 32 x 8 bits Internal
213. D78058FY SUBSERIES Part Number Vectored Maskable interrupt uPD78056FY uPD78058FY uPD78P058FY Internal 13 External 7 sources Internal 1 Software 1 Test input Internal 1 External 1 Supply voltage Voo 2 7 to 6 0 V Operating ambient temperature Ta 40 to 85 C Package Note 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Nete 80 pin plastic TQFP Fine pitch 12 x 12 mm uPD78058FY only Under development for the uPD78PO058FY only 2 9 Differences Between the uPD78058FY and uPD78058FY A Table 2 1 Differences Between the uPD78058FY and uPD78058FY A Hu Part Number Quality grade uPD78058FY Standard uPD78P058FY A Special Package 80 pin Plastic QFP 14 x 14 mm Resin thickness 2 7 mm 80 pin Plastic QFP 14 x 14 mm Resin thickness 1 4 mm 80 pin Plastic TQFP Fine Pitch 12 x 12 mm 80 pin Plastic QFP 14 x 14 mm Resin thickness 2 7 mm 57 CHAPTER 2 OUTLINE uPD78058FY SUBSERIES 2 10 Mask Options The mask ROM versions uPD78056FY 78058FY provide pull up resistor mask options which allow users to specify whether to connect a pull up resistor to a specific port pin when the user places an order for the device production Using this mask option when pull up resistors are required reduces th
214. E e S orte ipee E 164 7 4 4 When no subsystem clocks are used esssssssssseeeeeeeeeeee meer 164 7 5 Clock Generator Operations 165 7 59 15 MainisystemiclockoperatiOlis et He km E FU esta E ER 166 7 5 2 Subsystem clock operations 167 7 6 Changing System Clock and CPU Clock Settings esee 167 7 6 1 Time required for switchover between system clock and CPU clock 167 7 6 2 System clock and CPU clock switching procedure ssssseeeneenene 169 CHAPTER 8 16 BIT TIMER EVENT 171 8 1 Overview of the PD78058F and 78058FY Subseries On Chip Timers 171 8 2 16 Bit Timer Event Counter Functions 173 8 3 16 Bit Timer Event Counter Configuration esses 174 8 4 16 Bit Timer Event Counter Control Registers esee ennt 178 8 5 16 Bit Timer Event Counter 187 8 5 1 Interval timer 187 8 5 2 PWM o tp t Operatlons oi eec pie re ricette cete pet deb e eed ee 189 8 5 8 PPG output operatlOn annee iu e e C
215. EVENT COUNTER 1 8 bit TIMER EVENT COUNTER 2 WATCHDOG TIMER WATCH TIMER SERIAL INTERFACE 0 SERIAL INTERFACE 1 SERIAL INTERFACE 2 A D CONVERTER D A CONVERTER INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT CONTROL 78K 0 CPU CORE ROM RAM Voo Vss AV AVss IC Ver PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 12 PORT 13 REAL TIME OUTPUT PORT EXTERNAL ACCESS SYSTEM CONTROL Remarks 1 The internal ROM and RAM capacities depend on the product 2 Pin connection in parentheses is intended for the uPD78PO058F P01 to P06 P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 P130 P131 RTPO P120 to RTP7 P127 ADO P40 to AD7 P47 A8 P50 to A15 P57 RD P64 WR P65 WAIT P66 ASTB P67 RESET xi x2 1 07 XT2 43 CHAPTER 1 OUTLINE uPD78058F SUBSERIES 1 8 Outline of Function Part Number Internal memory uPD78056F uPD78058F uPD78P058F Mask ROM PROM 48 Kbytes 60 Kbytes 60 KbytesNote 1 High speed RAM 1024 bytes 1024 bytesNote 1 Buffer RAM 32 bytes Expansion RAM None 1024 bytes 1024 bytesNote 2 Memory space 64 Kbytes General register 8 bits x 8 x 4 banks Minimum m With mai
216. FUNCTION uPD78058F SUBSERIES d BUSY Serial interface automatic transmit receive busy input pins e STB Serial interface automatic transmit receive strobe output pins Caution When this port is used as a serial interface pin the I O and output latches must be set according to the function the user requires For the setting refer to Figure 16 4 Serial Operating Mode Register 0 Format and Figure 18 3 Serial Operating Mode Register 1 Format 3 2 4 P30 to P37 Port 3 These are 8 bit input output ports Beside serving as input output ports they function as timer input output clock output and buzzer output The following operating modes can be specified bit wise 1 2 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 3 PM3 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL Control mode These ports function as timer input output clock output and buzzer output a TI1 and TI2 Pin for external count clock input to the 8 bit timer event counter b TOO to TO2 Timer output pins c PCL Clock output pin d BUZ Buzzer output pin 67 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 3 2 5 P40 to P47 Port 4 These are 8 bit input output ports Besides serving as input output ports they function as an address data bus Th
217. H 292 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES Symbol 7 6 TCL32 TCL31 Figure 16 3 Timer Clock Select Register 3 Format 5 4 3 1 0 TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H fxx 2 2 Address After Reset R W 88H R W Serial Interface Channel 0 Serial Clock Selection MCS 1 Setting prohibited MCS 0 fx 22 1 25 MHz fxx 22 fx 22 1 25 MHz fx 29 625 kHz fxx 23 fx 23 625 kHz fx 24 313 kHz fxx 24 fx 24 313 kHz fx 25 156 kHz fxx 25 fx 25 156 kHz fx 26 78 1 kHz 26 fx 28 78 1 kHz fx 27 39 1 kHz fxx 27 fx 27 39 1 kHz fx 28 19 5 kHz fxx 28 fx 28 19 5 kHz fx 29 9 8 kHz TCL36 Setting prohibited fxx 2 Serial Interface Channel 1 Serial Clock Selection MCS 1 Setting prohibited MCS 0 fx 22 1 25 MHz fxx 22 fx 22 1 25 MHz fx 29 625 kHz fxx 23 fx 23 625 kHz fx 24 313 kHz fxx 24 fx 24 313 kHz fx 25 156 kHz fxx 25 fx 25 156 kHz fx 26 78 1 kHz fxx 28 fx 28 78 1 kHz fx 27 39 1 kHz fxx 27 fx 27 39 1 kHz fx 28 19 5 kHz 1 fxx 28 fx 28 19 5 kHz fx 29 9 8 kHz Other than above Setting prohibited Caution When rewriting TCL3 to other data stop the serial transfer operation beforehand Remarks 1 2
218. H by the RESET signal input Figure 21 19 Format of Interrupt Request Flag Register 1L After Symbol 3 Address Reset R W Lo e Ts Watch Timer Overflow Detection Flag Not detected Detected Caution Be sure to set bits 3 through 6 to 0 2 Interrupt mask flag register 1L MK1L It is used to set the standby mode enable disable at the time the standby mode is released by the watch timer It is set by a 1 bit memory manipulation instruction and 8 bit memory manipulation instruction It is set to FFH by the RESET signal input Figure 21 20 Format of Interrupt Mask Flag Register 1L After Symbol 3 2 Address Reset ay MK1L WTMK E TMMK2 FFE6H FFH R W WTMK Standby Mode Control by Watch Timer 0 1 Enables releasing the standby mode Disables releasing the standby mode Caution Be sure to set bits 3 through 6 to 1 503 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 3 Key return mode register KRM This register is used to set enable disable of standby function clear by key return signal port 4 falling edge detection KRM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets KRM to 02H Figure 21 21 Key Return Mode Register Format After Symbol 7 6 5 4 3 2 Address eser PW eao 8 o o o pa mm mom Key Return Signal Not detected Detected port 4 falling edge detection
219. HISTORY was added The mark shows major revised points Readers Purpose Organization PREFACE This manual has been prepared for user engineers who want to understand the functions of the uPD78058F and 78058FY Subseries and design and develop its application systems and programs Affected versions are each of the versions in the following Subseries uPD78058F Subseries uPD78056F 78058F 78P058F 78058F A uPD78058FY Subseries uPD78056FY 78058FY 78P058FY 78058FY A This manual is intended for users to understand the functions described in the Organization below The uPD78058F 78058FY Subseries manual is organized by two volumes this manual and the instruction edition common to the 78K 0 Series UPD78058F 78058FY Subseries 78K 0 Series User s Manual User s Manual This Manual Instructions e Pin functions CPU functions e Internal block functions e Instruction set e Interrupt e Explanation of each instruction Other on chip peripheral functions How to Read This Manual Before reading this manual you should have general knowledge of electric and logic circuits and microcontrollers O For persons who use this manual as the manual for the uPD78058F A and 78058FY A The uPD78058F and 78058FY differ from the uPD78058F A and 78058FY A only in their quality grades For products with A please change the readings for the product name as follows 78
220. High speed RAM 1024 x 8 bits FBOOH FAFFH Reserved FAEOH FADFH EFFFH Internal Buffer RAM 32 x 8 bits Program Area FACOH Data memory FABFH 1000H Space F800H Reserved OFFFH F7FFH CALLF Entry Area Internal Expansion RAM 0800H 1024 x 8 bits 07FFH P F400H rogram Area F3FFH Anat Reserved F000H 007FH CALLT Table Area Program Internal ROM ane memory 61440 x 8 bits space Vector Table Area Y 0000H 0000H Note When internal ROM size is 60 Kbytes the area FOOOH to F3FFH cannot be used F000H to F3FFH can be used as external memory by setting the internal ROM size to less than 56 Kbytes by the memory size switching register IMS 96 CHAPTER 5 CPU ARCHITECTURE Figure 5 3 Memory Map uPD78P058F u PD78P058FY Data memory space Special Function Registers SFRs 256 x 8 bits General Registers 32 x 8 bits Internal High speed RAM 1024 x 8 bits FBOOH FAFFH Reserved FAEOH FADFH EFFFH Internal Buffer RAM 32 x 8 bits Program Area FACOH FABFH eee 1000H F800H OFFFH F7FFH CALLF Entry Area Internal Expansion RAM 0800H 1024 x 8 bits 07FFH Program Area F400H F3FFH Reserved FOOOH EREDI CALLT Table Area Program 0040H memon a wur space Vector Table Area 0000H 0000H Note When internal PROM size is 60 Kbytes the area FOOOH to F3FFH cannot be used F000H to F3FFH can be used as ext
221. IE 78001 R A 576 APPENDIX C EMBEDDED SOFTWARE 581 LT Iu Nerve c 582 APPENDIX D REGISTER INDEX 1 21 eee rinse creant ct aane i ustedes snedescuseeesWidevencccted 585 DA Register Index ue nid 585 APPENDIX E REVISION HISTORY 591 22 LIST OF FIGURES 1 8 Figure No Title Page 3 1 List of Pin Inpat OUtpUt Circuit he eddie a ee acini 75 4 1 List of Pin Input Output Circuit ssc cle ce tees haves cette dee sce 93 5 1 Memory Map uPD78056F 78056FY eccceeceeeseeeeeeeeeeceeeeeeeeeeeecaeeseeeseaeeseeeseaeeseaeeseeseaeeseeeeeaeene 95 5 2 Memory Map uPD78058F 78058FY nennen nennen nnne nnne nnne nnne 96 5 3 Memory Map uPD78P058F uPD78P058FY 97 5 4 Data Memory Addressing uPD78056F 78056FY 100 5 5 Data Memory Addressing uPD78058F 78058FY 101 5 6 Data Memory Addressing uPD78P058F 78P058FY sse nennen 102 5 7 Program Co ntei Formati x cnet ERU nna aah ee ee 103 5 8 Program Status Word Format cccsccccssccceeseeceeenceeceneeeeceaeeeesneeecee
222. IE 78001 R A in circuit emulator by simply replacing the break board with the IE 78001 R BK under development Table B 2 Upgrading Former In circuit Emulator for 78K 0 Series to IE 78001 R A In circuit Emulator Cabinet Upgrading ete Board to be Purchased IE 78000 R Required IE 78001 R BK IE 78000 R A Not required Note upgrade your cabinet bring it to NEC 576 APPENDIX B DEVELOPMENT TOOLS Drawing and Footprint for Conversion Socket EV 9200GC 80 Figure B 2 EV 9200GC 80 Drawings For Reference Only Based on EV 9200GC 80 1 Package drawing in mm E J dx S G Htio TT lt D C No 1 pin index we LN O p gt x a E E c L LP EV 9200GC 80 G1E ITEM MILLIMETERS INCHES A 18 0 0 709 B 14 4 0 567 C 14 4 0 567 D 18 0 0 709 E 4 C 2 0 4 C 0 079 F 0 8 0 031 G 6 0 0 236 H 16 0 0 63 18 7 0 736 J 6 0 0 236 K 16 0 0 63 L 18 7 0 736 M 8 2 0 323 N 8 0 0 315 2 5 0 098 2 0 0 079 Q 0 35 0 014 R 2 3 0 091 S 1 5 00 059 577 APPENDIX B DEVELOPMENT TOOLS 57
223. IM11 of the serial operating mode register 1 CSIM1 set to 0 set STRB and BUSY1 of ADTC to 0 0 handshake control cannot be executed when the external clock is input Remark Don t care 405 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 406 c Automatic data transmit receive interval specify register ADTI This register sets the automatic data transmit receive function data transfer interval ADTI is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADTI to 00H 5 4 3 2 1 0 Address After Reset R W ADTI ADTI7 0 o ADTI3 ADTI2 ADTIT ADTIO FF6BH 00H R W No control of interval by ADT note 1 Data Transfer Interval Control 0 1 ADTIS ADTI2 ADTI1 Control of interval by ADTI ADTIO to ADTI4 Data Transfer Interval Specification xx 5 0 MHz Operation MinimumNote 2 18 4 us 0 5 fsck MaximumNete 2 20 0 us 1 5 fsck 31 2 us O 5 fsck 32 8 us 1 5 fsck 44 0 us 0 5 fsck 45 6 us 1 5 fsck 56 8 us O 5 fsck 58 4 us 1 5 fsck 69 6 us O 5 fsck 71 2 us 1 5 fsck 82 4 us 0 5 84 0 us 1 5 fsck 95 2 us 0 5 fsck 96 8 us 1 5 fsck o 1o o o o o o o 108 0us 0 5 fsck 109 6 us 1 5 fsck 120 8 us 0 5 fsck 122 4 us 1 5 fsck 133 6 us 0 5 fsck 135 2 us 1 5 fsck 146 4 us 0 5 fsck 148 0 us 1 5 fsck 159 2 us 0 5 fsck 160 8 us 1 5 fsck 172 0 us
224. ION 23 1 2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register OSTS OSTS is set with an 8 bit memory manipulation instruction RESET input sets OSTS to 04H However it takes 2 7 fx not 2 8 fx until the STOP mode is cleared by RESET input Figure 23 1 Oscillation Stabilization Time Select Register Format After Symbol 7 6 0 Address Reset R W 5 4 3 2 1 oms o o s rre nm Selection of Oscillation Stabilization Time when STOP Mode is Released OSTS1 MCS 1 MCS 0 2 fx 819 us 2 fx 1 64 ms 2 fx 3 28 ms 2 5 fx 6 55 ms 2 fx 6 55 ms 2 fx 13 1 ms 2 fx 13 1 ms 2 7 fx 26 2 ms 2 fx 26 2 ms 2 fx 52 4 ms Other than above Setting prohibited Caution The wait time when clearing the STOP mode does not include the time until clock oscillation starts after the STOP mode is cleared a in the figure below This applies to STOP mode clearance by RESET input as well as STOP mode clearance by interrupt request generation STOP Mode Clear X1 Pin Voltage Waveform Vss Remarks 1 fxx system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 MCS Bit 0 of oscillation mode select register OSMS 4 Values in parenthe
225. IT TIMER EVENT COUNTERS Figure 9 1 8 Bit Timer Event Counter Block Diagram Internal Bus fio 2 bo 2 f2 TH P33 Selector fxo 2 bod2 8 Bit Compare Register 10 CR10 Match 8 Selector Selector 2 TI2 P34 Register 20 8 Bit Compare CR20 Match 8 Bit Timer Register 2 TM2 Clear Selector Timer Clock Select Register 1 TCLITCL ITCL TCL TCL TCL TCL 17 16 15 14 13 12 11 10 8 Bit Timer Mode Control Register 8 Bit Timer Event Counter Output Control Circuit 1 8 Bit Timer INTTM1 Note Event Counter TO2 P32 Output Control Circuit 2 gt INTTM2 TO1 P31 i n sl eel 8 Bit Timer Output Control Register Internal Bus Note Refer to Figures 9 2 and 9 3 for details of 8 bit timer event counters 1 and 2 output control circuits 1 and 2 respectively 217 CHAPTER 9 8 BIT TIMER EVENT COUNTERS Figure 9 2 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 1 Level F F LV1 TO1 P31 Remark The section in the broken line is an output control circuit Figure 9 3 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 2 Level F F LV2 TO2 P32 Remarks 1 The section in the br
226. Input Output Function After Reset Alternate Function ADO to 07 Input Output Low order address data bus when expanding external memory P40 to P47 A8 to A15 Output High order address bus when expanding external memory P50 to P57 Output Strobe signal output for read operation from external memory P64 Strobe signal output for write operation to external memory Input Wait insertion when accessing external memory Output Strobe output externally latching address information output to ports 4 5 to access external memory Input A D converter analog input P10 to P17 Output D A converter analog output P130 P131 AVntro Input A D converter reference voltage input AVntr Input D A converter reference voltage input AVop 2m A D converter analog power supply Common with the port power supply AVss Ground potential common with the port s ground potential of the A D converter and D A converter RESET System reset input Crystal connection for main system clock oscillation Crystal connection for subsystem clock oscillation Positive power supply Except the port High voltage application for program write verify Connect directly to Vss in the normal operating mode Ground potential Except the port Internally connected Connect directly to Vss Cautions 1 The pin is used in common as the power supply for the A D converter
227. Input output Circuits and Recommended Connection of Unused Pins Table 4 1 shows the input output circuit types of pins and the recommended connection for unused pins Refer to Figure 4 1 for the configuration of the input output circuit of each type Table 4 1 Pin Input Output Circuit Types 1 2 Input Output Circuit Type POO INTPO TIOO Input Connect to Vss Pin Name Input Output Recommended Connection of Unused Pins PO1 INTP1 TIO1 Input output Connect independently via a resistor to Vss PO2 INTP2 PO4 INTP4 POS INTP5 PO6 INTP6 PO7 XT1 Input Connect to P10 ANIO to P17 ANI7 Input output Connect independently via a resistor P20 SI1 Input output to Voo or Vss P21 SO1 P22 SCK1 P23 STB P24 BUSY P25 SIO SBO SDAO P26 SO0 SB1 SDA1 P27 SCKO SCL P30 TOO Input output P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 P40 ADO to P47 AD7 Input output Connect independently via a resistor to P50 A8 to P57 A15 Input output Connect independently via a resistor or Vss CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 92 Table 4 1 Pin Input Output Circuit Types 2 2 Input Output Circuit Type P60 to P63 Mask ROM version Input Output Input output Recommended Connection of Unused Pins Connect independently via a resistor to Voo P60 to P63 PROM version
228. Internal High speed RAM 1024 x 8 bits dz ERE Y FE1FH FBOOH FAFFH Reserved FAEOH Direct Addressing Internal Buffer RAM 32 x 8 bits Register Indirect FACOH Addressing FABFH Reserved Based Addressing FA80H FA7FH Based Indexed Addressing External Memory 14976 x 8 bits CO00H BFFFH Internal ROM 49152 x 8 bits 0000H Y 100 CHAPTER 5 CPU ARCHITECTURE Figure 5 5 Data Memory Addressing uPD78058F 78058FY A Special Function Registers SFRs SFR Addressing 256 x 8 bits iU General Registers Register Addressing 32 x 8 bits Short Direct Addressing Internal High speed RAM 1024 x 8 bits FE20H 0 e LLL Y FE1FH FBOOH FAFFH Reserved FAEOH Direct Addressing Internal Buffer RAM 32 x 8 bits Register Indirect FACOH Addressing FABFH Reserved Based Addressing F800H F7FFH Based Indexed Addressing Internal Expansion RAM 1024 x 8 bits F400H F3FFH Reserved F000H EFFFH Internal ROM 61440 x 8 bits 0000H Y Note When internal ROM size is 60 Kbytes the area FOOOH to F3FFH cannot be used F000H to F3FFH can be used as external memory by setting the internal ROM size to less than 56 Kbytes by the memory size switching register 101 CHAPTER 5 CPU ARCHITECTURE 102 Figure 5 6 Data Memory Addressing uPD78P058F 78P058FY A Special Function Registers SFR
229. NEC User s Manual uPD78058F 78058FY Subseries 8 Bit Single Chip Microcontrollers uPD78056F uPD78058F uPD78P058F uPD78058F A uPD78056FY uPD78058FY uPD78P058FY uPD78058FY A Document No U12068EJ2VOUMOO 2nd edition Date Published April 1998 CP NEC Corporation 1997 Printed in Japa MEMO NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due
230. NEL 0 uPD78058F SUBSERIES 10 How to determine the slave busy state When a device is in the master mode use the following procedure to determine if the slave is in the busy state or not lt 1 gt Detect the generation of an acknowledge signal ACK or interrupt request signal 2 Set the port mode register PM25 or PM26 of pin SBO P25 or SB1 P26 in the input mode lt 3 gt Read the terminal s status the pin is in the ready state if it is in the high level After detecting the ready state set 0 in the port mode register and return to the output mode 11 SBI mode precautions 330 a Slave selection non selection is detected by match detection of the slave address received after bus release RELD 1 For this match detection match interrupt INTCSIO of the address to be generated with WUP 1 is normally used Thus execute selection non selection detection by slave address when WUP 1 When detecting selection non selection without the use of interrupt with WUP 0 do so by means of transmission reception of the command preset by program instead of using the address match detection method In SBI after specifying reset of BUSY the BUSY signal is output until the fall of the next serial clock If WUP 1 is set during this interval by mistake it will be impossible to reset BUSY Therefore after resetting the BUSY signal confirm that the level of the SBO SB1 pin has gone high before setting WUP to 1
231. NP 80GC Emulation probe This probe is used to connect the in circuit emulator to the target system and is designed for 80 pin plastic QFP GC 3B9 GC 8BT types EV 9200GC 80 Conversion socket Refer to Figure B 2 This conversion socket connects the NP 80GC to the target system board designed to mount a 80 pin plastic QFP GC 3B9 GC 8BT types NP 80GK Emulation probe This probe is used to connect the in circuit emulator to the target system and is designed for 80 pin plastic GK BE9 type TGK 0808DW Conversion adapter Refer to Figure B 3 Note Under development This conversion adapter connects the TGK 080SDW to the target system board designed to mount a 80 pin plastic QFP GK BE9 type Remarks 1 NP 80GC is a product of Naitou Densei Machidaseisakusho Co Ltd Phone 044 822 3813 2 TGK 080SDW is a product of TOKYO ELETECH CORPORATION Inquiries Daimaru Kougyou Co Ltd Phone 03 3820 7112 Tokyo Electronic Component Division 06 244 6672 Osaka Electronic Component Division 3 TGK 080SDW is sold on a unit basis 4 EV 9200GC 80 is sold in sets of five units 572 APPENDIX B DEVELOPMENT TOOLS B 3 1 Hardware 2 2 2 When using in circuit emulator IE 78001 R A IE 78001 R ANete 1 The in circuit emulator serves to debug hardware and software when In circuit emulator developing application systems using a 78K 0 Series product It corresponds to integrated de
232. O ANO1 Output Notes 1 If these ports are read out when these pins are used in the alternate function mode undefined values are read 2 When the P40 to P47 pins P50 to P57 pins and P64 to P67 pins are used for alternate functions set the function by the memory expansion mode register MM Cautions 1 2 Remarks x When notusing external wait in the external memory extension mode the P66 pin can be used as an I O port When port 2 and port 7 are used for serial interface pin the I O latch or output latch must be set according to its function For the setting methods see Figure 16 4 Serial Operation Mode Register 0 Format Figure 17 4 Serial Operating Mode Register 0 Format Figure 18 3 Serial Operating Mode Register 1 Format and Table 19 2 Serial Interface Channel 2 Operating Mode Settings of List don t care PMxx port mode register Pxx port output latch 147 CHAPTER 6 PORT FUNCTIONS Figure 6 19 Port Mode Register Format After Symbol 7 6 5 4 3 2 1 0 Address Reset R W PMO 1 PMO6 PM05 PM04 PMOS3 PM02 PMO1 1 FF20H FFH R W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R W PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FF25H FFH R W PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM
233. OR 7 5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode Main system clock fxx e Subsystem clock fxr e CPU clock fcPu Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register PCC and the oscillation mode selection register OSMS a Upon generation of RESET signal the lowest speed mode of the main system clock 12 8 us when operated at 5 0 MHz is selected PCC 04H OSMS 00H Main system clock oscillation stops while low level is applied to RESET pin With the main system clock selected one of the six CPU clock types 0 4us 0 8us 1 6us 3 2us 6 4us 12 8us 5 0 MHz can be selected by setting the PCC and OSMS With the main system clock selected two standby modes the STOP and HALT modes are available In a system where the subsystem clock is not used the current consumption in the STOP mode can be further reduced by specifying with bit 6 FRC of the PCC not to use the feedback resistor The PCC can be used to select the subsystem clock and to operate the system with low current consumption 122 us when operated at 32 768 kHz With the subsystem clock selected main system clock oscillation can be stopped with the PCC The HALT mode can be used However the STOP mode cannot be used Subsystem clock oscillatio
234. OS input CMOS input output N ch open drain input output Total 68 CMOS input CMOS input output 62 N ch open drain input output AVpbp pin Supply power for A D converter Supply power for A D con verter and port output buffer None The supply power for the port output buffer is Vono AVnero pin Reference voltage input for A D converter Reference voltage input and analog power supply for A D converter Serial interface channel 2 On chip 3 wire serial I O UART mode 3 wire serial I O UART mode with time sharing function External maskable interrupt 6 565 APPENDIX A DIFFERENCES AMONG 4PD78054 78058F AND 780058 SUBSERIES Table 1 Major Differences Among uPD78054 78058F and 780058 Subseries 2 2 Product Name Emulation probe uPD78054 Subseries EP 78230GC R EP 78054GK R UPD78058F Subseries uUPD780058 Subseries EP 780058GC R EP 780058GK R Device file DF78054 DF780058 Package 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm 80 pin ceramics WQFN 14 x 14 mm uPD78P054 and 78P058 only 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm 80 pin plastic TQFP Fine pitch 12 x 12 mm uPD78058F only 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 m
235. P lt SP 3 IE 0 PCH SP 1 PC lt SP SP SP 2 PCH SP 1 PCL SP PSW lt SP 2 SP SP 3 NMIS 0 PCH SP 1 PC SP PSW lt SP 2 SP lt SP 3 SP 1 lt PSW SP lt SP 1 SP 1 lt SP 2 lt rp SP e SP 2 PSW c SP SP SP 1 lt SP 1 rp lt SP SP lt SP 2 laddr16 addr5 Call return rp SP word SP AX AX SP SP lt word SP AX AX SP PC lt addr16 PC lt PC 2 jdisp8 PCH A PCL lt X PC lt PC 2 jdisp8 if CY 1 PC c PC 2 jdisp8 if CY 0 PC c PC 2 jdisp8 if Z 1 PC c PC 2 jdisp8 if Z 0 Uncondi laddr16 tional addr16 branch AX addr16 Conditional addr16 pranen addr16 addr16 MP MLM MIM MH oO MM FA Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remarks 1 One instruction clock is the length of 1 clock cycle of the CPU clock fceu selected by the processor clock control register PCC 2 This clock cycle applies to internal ROM program 3 nis the number of waits when external memory expansion area is read from 4 mis the number of waits when external memory expansion area is written to 558 CHAPTER 27 INSTRUCTION SET Inst
236. P120 to PT27 Port12 2 atop UR i ta EGER 70 3 2 10 P130 and P181 Port 13 ni entere qp repo tp ev i YE UE due 70 93 2 a CAVRERO i 5 3t ce UC mentam A A 70 5 212 VIII CDU 70 S PEN EC RS VIP 71 15 3 2 14 ine AN i aii ih Sri eee da eese teet Ets 71 eS NS HESBI ere ee rene ae ales Dn SPE MICI OM DO IUS IM MUI 71 3 246 XTand X2 iie det menti ERR ina ema 71 3 217 XT kand XTZ anche qnte temere eae diede Pe diserte tq eats 71 9 2 18 VBD gis seeds emere eie e f err d ed eu i mtb rad den ctas 71 3 2 19 V 8 dta b ede et 71 3 2 20 VPP PROM versions only iid ie tinet cr ect E ed Doe Roter d See ec ae iens 71 3 2 21 IG Mask ROM version only iacet I MER RR CREARI OR 72 3 3 Input output Circuits and Recommended Connection of Unused Pins 73 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 77 4 1 Pin Function LIST cdgesececersscttecessssucectedisvececssansccuecetevsencceeds 77 4 1 1 Normal operating mode PINS rissies anepi ta nnne enne nnne nene 77 4 1 2 PROM programming mode pins PROM versions only sse 82 4 2 Description of Pin Functions 83 4 241 POO tO POZPOITt 0 tienen cla Dt qe cort ede tec ae ena eto 83 4 2 2 P10 to P17 Port T iine eet en
237. P64 RD P65 WR P66 WAIT P67 ASTB P70 SI2 RxD P71 SO2 TxD P72 SCK2 ASCK P120 RTPO to P127 RTP7 Input output Connect independently via a resistor to Voo or Vss P130 ANOO to P131 ANO1 Input output Connect independently via a resistor to Vss RESET Input XT2 AVREFO 1 AVop IC Mask ROM version Ver PROM version Leave open Connect to Vss Connect to Connect to a separate power supply with the same potential as VDD Connect to a separate ground with the same potential as Vss Connect directly to Vss CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES Figure 4 1 List of Pin Input Output Circuit 1 2 v enable Schmitt Triggered Input with IN OUT Hysteresis Characteristics output disable Type 10 C AVop E pullup D o p P ch pullup D o P ch enable enable AVDD AVop oe DE data MH EPen IN OUT IN OUT output E open drain disable output disable 7 AVss input enable Type 11 C AVDD pullup I P ch pullup o nee AVbp enable AVDD data gt P ch data O N OUT DAH output disable IN OUT comparator Type 5 O output i disable Vner Threshold voltage CHAPTER 4 PIN FUNCTION uP
238. PD78058F 78058FY 538 CHAPTER 26 uPD78P058F 78P058FY 26 2 Internal Expansion RAM Size Switching Register The internal expansion RAM size of the uPD78P058F and 78P058FY can be defined using the internal expansion RAM size switching register IXS thus enabling memory mapping that is the same as that of mask ROM products with different internal expansion RAM The IXS is set by an 8 bit memory manipulation instruction RESET signal input sets IXS to OAH Figure 26 2 Internal Expansion RAM Size Switching Register Format After Reset Symbol 7 6 1 0 Address R W 5 4 3 2 IXS fo IXRAMS IXRAM2 IXRAM1 IXRAMO FFFAH OAH IXRAM2 IXRAM1 IXRAMO Internal Extension RAM Capacity Selection 1 0 0 O bytes 0 1 0 1024 bytes Other than above Setting prohibited The value in the IXS that has the identical memory map to the mask ROM versions is given in Table 26 3 Table 26 3 Value Set to the Internal Expansion RAM Size Switching Register Pertinent Mask ROM Versions Value Set to IXS UPD78056F 78056FY UPD78058F 78058FY Remark If a program for the uPD78PO058F or 78P058FY which includes MOV IXS 0CH is implemented with the uPD78056F or 78056FY this instruction is ignored and causes no malfunction 539 CHAPTER 26 078 58 78P058FY 26 3 PROM Programming The uPD78P058F and 78P058FY include on chip PROM in a 60 Kbyte configuration as program memory To
239. PIFO is set 3 16 bit timer register TMO 8 4 TMO is a 16 bit register which counts the count pulses is read by a 16 bit memory manipulation instruction When is read capture compare register CRO1 should first be set as a capture register RESET input sets TMO to 0000H Caution As reading of the value of TMO is performed via CRO1 the previously set value of CRO1 is lost 16 Bit Timer Event Counter Control Registers The following seven types of registers are used to control the 16 bit timer event counter Timer clock select register 0 TCLO 16 bit timer mode control register TMCO Capture compare control register 0 CRCO 16 bit timer output control register TOCO Port mode register 3 PM3 External interrupt mode register O INTMO Sampling clock select register SCS 1 Timer clock select register 0 TCLO 178 This register is used to set the count clock of the 16 bit timer register TCLO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TCLO value to OOH Remark TCLO has the function of setting the PCL output clock in addition to that of setting the count clock of the 16 bit timer register CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 3 Timer Clock Selection Register 0 Format Symbol D 6 5 4 3 2 1 0 Address After Reset R W TCLO CLOE TCLO6 TCLO5 TCLO4 TCLO3 TCLO2 TCLO1 TCLOO FF40H 00H R W TCLO2 TCLO1 fxr 32 768 PCL Output Clock Selection
240. PSW bit CY HL bit saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY wm wo nm wo o Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remarks 1 One instruction clock is the length of 1 clock cycle of the CPU clock fceu selected by the processor clock control register PCC 2 This clock cycle applies to internal ROM program 3 nis the number of waits when external memory expansion area is read from 4 mis the number of waits when external memory expansion area is written to 556 CHAPTER 27 INSTRUCTION SET Instruction Group Mnemonic Operands CY saddr bit Operation CY e CY saddr bit CY sfr bit CY lt CY stfr bit CY A bit CY lt CY A bit CY PSW bit CY CY PSW bit CY HL bit CY CY HL bit CY saddr bit CY lt CYV saddr bit CY sfr bit CY lt CY V sfr bit CY A bit CY lt CYVA bit CY PSW bit CYVPSW bit CY HL bit CY V HL bit CY saddr bit CY lt CY Y saddr bit CY sfr bit CY lt CY sfr bit CY A bit CY CY A bit CY PSW bit CY v PSW bit CY HL bit CY lt CY v HL bit saddr bit saddr bit lt 1 sfr bit sfr bit
241. Place Is Corrected FFFFH F7FFH BR JUMP F7FDH z 2 Correction Program JUMP 1 3 Internal ROM Correction Place XXXXH Internal ROM 0000H 1 Branches to address F7FDH when fetch address matches correction address 2 Branches to correction program 3 Returns to internal ROM program Remark Area filled with diagonal lines Internal expansion RAM JUMP Correction program start address 534 CHAPTER 25 ROM CORRECTION Figure 25 10 Program Transition Diagram When Two Places Are Corrected FFFFH F7FFH He 6 F7FDH 2 yyyyH 7 XXXXH JUMP E 8 4 5 Internal ROM 1 Correction Place 2 Internal ROM Correction Place 1 Internal ROM 0000H 1 2 3 4 5 6 7 8 Branches to address F7FDH when fetch address matches correction address Branches to branch destination judgment program Branches to correction program 1 by branch destination judgment program BTCLR CORSTO xxxxH Returns to internal ROM program Branches to address F7FDH when fetch address matches correction address Branches to branch destination judgment program Branches to correction program 2 by branch destination judgment program BTCLR CORST1 yyyyH Returns to internal ROM program 5 wae wa wa YS Remark Area filled with diagonal lines Internal expansion RAM JUMP Destination judge program start address
242. Port mode register 6 PM eee e seth e 130 146 Port mode register 7 BM ise pes oni aea ur te e RE e D 130 146 Priority specify flag register OH 485 Priority specity flag register OL PROL tcd sete ite ce ctt vs ae gusce te d cece 485 Priority specify flag register 1L PR1L 485 Processor clock control register PCC nnne nnne ennt nennen nnns 157 Program stat s word eh EUER RR RR RENE REIR RAN OR EE 490 Pull up resistor option register H PUOH sssssssssessseseeeeeeeennnee nnne 149 Pull up resistor option register L PUOL esssssesssseseeeeeeeeenneenen nennen nennen nennen nennen sentes 149 R Real time output buffer register RTBH sssssseeenenenn nennen nnne nennen nre 473 Real time output buffer register L RTBL sssssseeeeeeeneeennnnen nennen nnne nnne nennen nennen 473 Real time output port control register RTPC ssessssssssseseeeeeeeeeenene nennen nnne nennen nennen nns 475 Real time output port mode register RTPM nennen rnnt 474 Receive buffer register RAB ceci tede nette Eee adire Er der tended Ud 437 Receive shift register RXS eie ha
243. R CLD SCKO P27 Pin LevelNote 2 0 Low level 1 High level Caution Be sure to set bits 0 to 3 to 0 Notes 1 Bit 6 CLD is a read only bit 2 When CSIEO 0 CLD becomes 0 Remark CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 333 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 2 Communication operation The 2 wire serial I O mode is used for data transmission reception in 8 bit units Data transmission reception is carried out bit wise in synchronization with the serial clock Shift operation of the serial I O shift register 0 SIOO is carried out in synchronization with the falling edge of the serial clock SCKO The transmit data is held in the SOO latch and is output from the SBO P25 or SB1 P26 pin on an MSB first basis The receive data input from the SBO or SB1 pin is latched into the shift register at the rising edge of SCKO Upon termination of 8 bit transfer the shift register operation stops automatically and the interrupt request flag CSIIFO is set Figure 16 32 2 Wire Serial I O Mode Timings SCKO 1 2 3 4 5 6 7 80 CSIIFO 334 End of Transfer Transfer Start at the Falling Edge of SCKO Since the SBO SB1 pin specified in the serial data bus is an N ch open drain input output it is necessary for it to be pulled up externally Also it is necessary for the N ch open drain output to be set in the high imped
244. RXB must be read even if a receive error is generated If RXB is not read an overrun error will be generated when the next data is received and the receive error state will continue indefinitely CHAPTER 19 SERIAL INTERFACE CHANNEL 2 e Receive errors Three kinds of errors can occur during a receive operation a parity error framing error or overrun error The data reception result error flag is set in the asynchronous serial interface status register ASIS and at the same time a receive error interrupt request INTSER is generated Receive error causes are shown in Table 19 7 It is possible to determine what kind of error was generated during reception by reading the contents of ASIS in the reception error interrupt servicing INTSER see Figures 19 9 and 19 10 The contents of ASIS are reset 0 by reading the receive buffer register RXB or receiving the next data if there is an error in the next data the corresponding error flag is set Table 19 7 Receive Error Causes Receive Errors Parity error Transmission time parity specification and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next data is completed before data is read from receive register buffer Figure 19 10 Receive Error Timing oma X fee Xe XXX START INTSRNete INTSER when a framing error or an overrun error is generated INTSER when a parity error is generated Note f a rece
245. SB1 Input output Serial interface serial data input output P25 SIO P26 SO0 SCKO SCK1 SCK2 Input output Serial interface serial clock input output P27 P22 P72 ASCK STB Output Serial interface automatic transmit receive strobe output P23 BUSY Input Serial interface automatic transmit receive busy input P24 RxD Input Asynchronous serial interface serial data input P70 SI2 TxD Output Asynchronous serial interface serial data output P71 SO2 ASCK Input Asynchronous serial interface serial clock input P72 SCK2 TIOO TIO1 TH TI2 Input External count clock input to 16 bit timer TMO Capture trigger signal input to capture register CROO External count clock input to 8 bit timer TM1 External count clock input to 8 bit timer TM2 POO INTPO P01 INTP1 P33 P34 TOO TO1 TO2 Output 16 bit timer TMO output also used for 14 bit PWM output 8 bit timer TM1 output 8 bit timer TM2 output P30 P31 P32 PCL Output Clock output for main system clock and subsystem clock trimming P35 BUZ Output Buzzer output P36 to RTP7 62 Output Real time output port outputting data in synchronization with trigger P120 to P127 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 2 Non port pins 2 2 Input Output Function After Reset Alternate Func
246. SCKO 2 7 o SBO 81 Slave Address When Addresses Match 4 When Addresses do not Match RELD 317 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 318 Figure 16 22 ACKT Operation SCKO 6 7 8 9 SBO SB1 D2 X Do ACK ACK signal is output for a period of one clock just after setting ACKT wm lt _ lt gt When set during this period Caution Do not set ACKT before termination of transfer CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES Figure 16 23 ACKE Operations a When ACKE 1 upon completion of transfer SCKO 1 2 seo ssi ACKE ACK signal is output at 9th clock When 1 at this point b When set after completion of transfer SCKO 6 7 8 9 SBO 581 D2 X D1 X Do ACK ACK signal is output for a period of one clock just after setting ACKE T gt If set during this period 1 at the falling edge of the next SCKO c When ACKE 0 upon completion of transfer SCKO 1 2 7 8 9 SBO SB1 X D7 X De 02 X D1 X Do ACK signal is not output A When 0 at this point d When ACKE 1 period is short _ _ inv SBO SB1 02 X D1 X Do ACK signal is not output ACKE lt gt If set and cleared during this period and ACKE
247. SIM PS1 PSO ISRM FF70H 00H R W SCK Clock Selection in Asynchronous Serial Interface Mode Input clock from off chip to ASCK pin Dedicated baud rate generator outputNote ISRM Control of Reception Completion Interrupt Request in Case of Error Generation Reception completion interrupt request generated in case of error generation Reception completion interrupt request not generated in case of error generation Transmit Data Stop Bit Length Specification Character Length Specification Length Character Length Specification 7 bits 8 bits No Parity 0 parity always added in transmission No parity test in reception parity error not generated Odd parity Even parity RXE Receive Operation Control 0 Receive operation stopped 1 Receive operation enabled Transmit Operation Control 0 Transmit operation stopped 1 Transmit operation enabled Note When SCK is set to 1 and the baud rate generator output is selected the ASCK pin can be used as an input output port Caution The serial transmit receive operation must be stopped before changing the operating mode 449 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 c Asynchronous serial interface status register ASIS ASIS is set with 8 bit memory manipulation instruction RESET input sets ASIS to 00H Address After Reset R W ASIS FF71H 00H R OVE Overrun Error Flag Overrun error not generated
248. Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1 Operation stop mode e 3 wire serial I O mode e 3 wire serial I O mode with automatic transmit receive function 18 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power consumption can be reduced The serial I O shift register 1 SIO1 does not carry out shift operation either and thus it can be used as an ordinary 8 bit register In the operation stop mode the P20 SI1 P21 SO1 P22 SCK1 P23 STB and P24 BUSY pins can be used as ordinary input output ports 1 Register setting The operation stop mode is set with the serial operating mode register 1 CSIM1 CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H Symbol D 6 CSIM1 DIR CSIMt1 Note 1 x Note 1 x Note 1 x 4 Note 1 x 3 Note 1 x 2 1 0 9 ests Shift Register 1 Operation Operation stop Address FF68H Serial Clock Counter Operation Control After Reset 00H SH P20 Pin Function P20 CMOS input output R W R W SO1 P21 Pin Function P21 CMOS input output SCK1 P22 Pin Function P22 CMOS input output Note 2 1 Notes 1 Note 2 x Operation enable Can be used freely as port function Count operation Sli Note 2 Inp
249. T 1 ch Vop MIN value 3 ch time division UART 1 ch 3 ch UART 1 ch 3 ch UART 1 ch time division 3 wire 1 ch 2ch uPD780001 Inverter uPD78002 uPD78083 uPD780988 32K to 60 K 3 ch External extension control uPD780964 8 K to 32K uPD780924 uPD780208 32Kto 60 K 2 ch 1 ch UART 1 ch 8 ch UART 2 ch 2 ch UART 2 ch uPD780228 48K to 60 K 3 ch uPD78044H 32K to 48K 2 ch uPD78044F 16Kto 40K uPD780308 48Kto 60 K 2 ch uPD78064B 32K IEBus uPD78064 16Kto32K uPD78098B 40 K to 60 K 2 ch support uPD78098 32Kt060K 3 ch time division UART 1 ch 2 ch UART 1 ch 3 ch UART 1 ch Meter uPD780973 24 2 3ch 1ch 1ch 1ch 5ch 2 ch UART 1 ch 56 45V control Notes 42 1 16 bit timer 2 channels 10 bit timer 1 channel 2 10 bit timer 1 channel CHAPTER 1 OUTLINE uPD78058F SUBSERIES 1 7 Block Diagram TOO P30 TIOO INTPO PO0 TIO1 INTP1 PO1 TO1 P31 TH P33 TO2 P32 TI2 P34 SIO SBO P25 SOO SB1 P26 SCKO0 P27 511 20 SO1 P21 SCK1 P22 STB P23 BUSY P24 SI2 RxD P70 SO2 TxD P71 SCK2 ASCK P72 ANIO P10 to ANI7 P17 AVnero ANOO P130 ANO1 P131 AVnrert INTPO POO to INTP6 P06 BUZ P36 PCL P35 16 bit TIMER EVENT COUNTER 8 bit TIMER
250. T When outputting one shot pulse again execute after INTTMOO interrupt match signal with CROO is generated Figure 8 31 Control Register Settings for One Shot Pulse Output Operation Using Software Trigger a 16 bit timer mode control register TMCO TMC03 TMCO2 TMCO1 OVFO E EHESKESEEESESENES Clear amp start with match of and CROO b Capture compare control register 0 CRCO CRC02 CRCO1 CRCOO JG ESETESENENKZESES CROO set as compare register CR01 set as compare register c 16 bit timer output control register TOCO OSPT OSPE TOCO4 LVSO LVRO TOCO1 TOEO US FECERO EU E UT LL TOO Output Enabled Inversion of output on match of and CROO Specified TOO output F F initial value Inversion of output on match of and CRO1 One shot pulse output mode Set 1 in case of output Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with one shot pulse output See the description of the respective control registers for details Caution Values in the following range should be set in CROO and CRO1 0000H lt CRO1 lt CROO lt FFFFH 204 CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 32 Timing of One Shot Pulse Output Operation Using Software Trigger Set OCH to TMCO TMO count start OSPT INTTMO1 INTTMOO TOO Pin Output Te Caution The 16 bit timer register starts operatio
251. T and MDT Operatioris x et t Ee ate ae tte Dre Ene beni 303 16 9 Circuit of Switching in Transfer Bit Order ssssssssesseeeeeeeenene nennen nennen nennen 304 16 10 Example of Serial Bus Configuration with SBI sse 305 16 11 ee ASE 307 16 12 BUS Release Signal iO uibem iie 308 16 19 Command Signal iet ater etae miden e ee ewe 308 16 14 Addresses ae REPORTAR AREE REPRISE RR HARI 309 16 15 Slave Selection with enne enne tenete entes nnns ense nnns 309 16 16 Commards 5 x minm atc aiv tot aie m ardet re eate 310 16 17 de hei ete teet t 310 16 18 Acknowledge Signal t de c sacle e le ddl Tee i tese Pond 311 16 19 BUSY and READY Signals eee peo eee 312 16 20 RELT CMDT RELD and CMDD Operations Master 317 16 21 and CMDD Operations Slave sessssssssseseeeeeneeeee nennen nennen nennen enne nenne 317 16 22 ACKT Operation eicere eit eror tee e EE eo HY EE eee Ie vod Ecos ed 318 16 23 sACKE Operations nre itte qe ib OD o e a at 319 16 24 ACKD Operations reed d OU EAT eg Oi EN
252. The offset data is first expanded as a positive number to 16 bits and then added A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format dentin Pp Description example MOV A HL 10H when setting byte to 10H Operation code 10101110 00010000 123 CHAPTER 5 CPU ARCHITECTURE 5 4 8 Based indexed addressing Function This addressing addresses the memory by adding the contents of the HL register which is used as a base register to the contents of the B or C register specified in the instruction word and by using the result of the addition The HL B and C registers to be accessed are registers in the register bank specified by the register bank select flags RBSO and RBS1 The contents of the B register or C register are expanded to 16 bits as a positive number and then added from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier BEA HL B HL C Description example In the case of MOV A HL Operation code 10101041 1 5 4 9 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register is saved reset upon generation of an interrupt request Stack addressing enables to addre
253. The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data During the wait state the slave device continues to output the wait signal by keeping the SCL pin low to delay subsequent transfers When the wait state is released the master device can start the next trans fer For the releasing operation of slave devices see section 17 4 5 Cautions on Use of 12 Bus Mode Figure 17 20 Wait Signal a Wait of 8 Clock Cycles Set low because slave device drives low though master device returns to Hi Z state No wait is inserted after 9th clock cycle and before master device starts next transfer SCL of Master Device SCL of Slave Device SCL mx fo foe YoY p Output by manipulating ACKT b Wait of 9 Clock Cycles Set low because slave device drives low though master device returns to Hi Z state SCL of Master Device SCL of Slave Device SCL sem Tuypspepe V9 aye t Output based on the value set in ACKE in advance 367 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 3 Register setting The I C bus mode is set by the serial operating mode register 0 CSIMO serial bus interface control register SBIC and interrupt timing specify register SINT a Serial operating mode register 0 CSIMO CSIMO is set by a 1 bit or 8 bit memory manipulation instruction RESET
254. Timer Event Counter Square Wave Output Ranges seen 229 9 9 Interval Times When 2 Channel 8 Bit Timer Event Counters TM1 and TM2 are Used as 16 Bit Timer Event Counter cimier aoaeiaa eai 232 31 LIST OF TABLES 2 3 Table No Title Page 9 10 Square Wave Output Ranges When 2 Channel 8 Bit Timer Event Counters TM1 and TM2 are Used as 16 Bit Timer Event Counter 234 10 1 Interval Timer Interval TIME wc ect ae de ed et tla 239 10 2 Watch Timer Configuration 2 ode ne RIORUM REPREHENE GIO dete etus 240 10 3 Interval Timer Interval Time ceeececeeceeeseeeeeeeneeeeeeceseseeeneseaceaeenseseseeeeesneesnseaeessoneneseneeeeeneeessoeens 244 11 1 Watchdog Timer Runaway Detection Times ssseeeeeenn enne 245 11 2 Interval TIMES citet eoe ege e rb tte Pte o P 246 11 3 Watchdog Timer Configuration 247 11 4 Watchdog Timer Runaway Detection Time 251 11 5 Interval Timer Interval Time 2 irri tre terea ERR eerte x apice 252 12 1 Clock Output Control Circuit Configuration nennen 254 13 1 Buzzer Output Control Circuit Configuration esesssssseeeeneeneenenen enne 257 14 1 A D Converter Configuration vise cic cece dec coire tim eo Deep tee bk cana d de eL PELA Dx eara scene 262 15 1
255. Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 1 SIO1 when the following two conditions are satisfied Serial interface channel 1 operation control bit CSIE1 1 Internal serial clock is stopped or SCK1 is a high level after 8 bit serial transfer Caution If CSIE1 is set to 1 after data write to SIO1 transfer does not start Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIF1 is set CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18 4 3 3 wire serial I O mode operation with automatic transmit receive function This 3 wire serial mode is used for transmission reception of a maximum of 32 byte data without the use of software Once transfer is started the data prestored in the RAM can be transmitted by the set number of bytes and data can be received and stored in the RAM by the set number of bytes Handshake signals STB and BUSY are supported by hardware to transmit receive data continuously OSD On Screen Display LSI and peripheral LSI including LCD controller driver can be connected without difficulty 1 Register setting The 3 wire serial I O mode with automatic transmit receive function is set with the serial operating mode register 1 CSIM1 automatic data transmit receive control register ADTC and automatic data transmit receive interval specify register ADTI a Serial operating mode register 1
256. TxD CMOS output ASCK input Other than above Notes 1 Can be used freely as port function 2 Can be used as P70 CMOS input output when only transmitter is used Remark x Don t care PMXX Port Mode Register PXX 440 Port Output Latch Setting prohibited CHAPTER 19 SERIAL INTERFACE CHANNEL 2 3 Asynchronous serial interface status register ASIS This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode ASIS is read with 8 bit memory manipulation instruction In 3 wire serial mode the contents of the ASIS are undefined RESET input sets ASIS to 00H Figure 19 5 Asynchronous Serial Interface Status Register Format Symbol 7 6 Address After Reset R W ASIS 5 4 3 2 1 0 71 00H R OVE Overrun Error Flag Overrun error not generated Overrun error generatedNote 1 When next receive operation is completed before data from receive buffer register is read Framing error not generated Framing error generatedNete 2 When stop bit is not detected Parity error not generated Parity error generated When transmit data parity does not match Notes 1 The receive buffer register must be read when an overrun error is generated Overrun errors will continue to be generated until RXB is read 2 Even if the stop bit length has been set as 2 bits by bit 2 SL
257. X XOXOXO X X Koo Ves 8susv V Data Remark The dotted line indicates READY status The bus release signal and the command signal are output by the master device BUSY is output by the slave signal ACK can be output by either the master or slave device normally the 8 bit data receiver outputs Serial clocks continue to be output by the master device from 8 bit data transfer start to BUSY reset 307 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 308 a b Bus release signal REL The bus release signal is a signal with the SBO SB1 line which has changed from the low level to the high level when the line is at the high level without serial clock output This signal is output by the master device Figure 16 12 Bus Release Signal The bus release signal indicates that the master device is going to transmit an address to the slave device The slave device incorporates hardware to detect the bus release signal Caution When the SCKO line is high level and the SBO SB1 changes from low level to high level this is recognized as a bus release signal Therefore if there are shifts in the bus change timing due to influences such as the board capacity this may be judged to be a bus release signal even though data is being sent Thus much care is requiring in wiring Command signal CMD The command signal is a signal with the SBO SB1 line which has changed from the high level to
258. a Before transmission reception FADFH FAC5H Transmit data 1 T1 2 Receive data 1 R1 SIO1 Transmit data 2 T2 Lr 2x Transmit data 4 T4 Transmit data 5 T5 FACOH Transmit data 6 T6 CSIIF1 413 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 414 Figure 18 10 Internal Buffer RAM Operation in 6 Byte Transmission Reception in Basic Transmit Receive Mode 2 2 FADFH FAC5H FACOH FADFH FAC5H FACOH b 4th byte transmission reception Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 Receive data 4 R4 SIO1 c Completion of transmission reception Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Receive data 4 R4 Receive data 5 R5 Receive data 6 R6 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 b SCK1 SO CSIIF1 TRF Basic transmission mode In this mode the specified number of 8 bit unit data are transmitted Serial transmission is started by writing the desired data to serial I O shift register 1 SIO1 when bit 7 CSIE1 of serial operation mode register 1 CSIM1 is set at 1 When the final byte has been sent an interrupt request flag CSIIF1 is set However judge the termination of auto send and receive not by CSIIF1 interrupt request flag but by bit 3 TRF of the auto data send and
259. a Input Data Output gt ee jf a 543 CHAPTER 26 uPD78P058F 78P058FY Figure 26 5 Byte Program Mode Flowchart Remark Address G G Start address N Last address of program 6 5 V Ver 12 5 V X 0 X X 1 No 1 Ise Address Address 1 Gels program puls 4 5 to 5 5 V Vep Fail All bytes verified End of write Defective product 544 CHAPTER 26 uPD78P058F 78P058FY Figure 26 6 Byte Program Mode Timing Program Program Verify M VET oe Vep Vep Voo Voo 1 5 Voo ee Vop Vit Vin PGM Vi Vit Cautions 1 Be sure to apply Voo before applying Vpr and remove it after removing Vpp 2 Vpp must not exceed 13 5 V including overshoot voltage 3 Disconnecting inserting the device from to the on board socket while 12 5 V is being applied to the Vr pin may have an adverse affect on device reliability 545 CHAPTER 26 uPD78P058F 78P058FY 26 3 3 PROM read procedure PROM contents can be read onto the external data bus DO to D7 using the following procedure 1 Fix the RESET pin low and supply 5 V to the Ver pin Unused pins are handled as shown in paragraph 2 PROM programming mode in section 1 5 or 2 5 Pin Configuration Top View Supply 5 V to the Von and Vp pins Input the address of data to be read to pins AO through A16
260. a ba ano eet 84 4 2 9 P20 t0 B27 ROM dace tt rh n ei otn ec rcm e c o m e cds 84 4 2 4 P30 to PS7 POM deters ee nelle tui B tme i detis 85 4 2 5 SPAO TOPAZ anc Resta dte ote pet aie itia 86 4 2 6 P50to P57 by acest ere bere ER ERR MAR b A RAE 86 42 7 P60 to POZ POM O eed ee Ee c eth ed 86 4 2 8 P70 t0 P 72 POI nien ca e dert Ge teca beber sett beta ine ie Eg eR ee 87 4 2 9 P120 to P127 Port 12 nuoto een e ce eed t dg etaient 88 4 2 10 P190 and P 191 Port 19 uu tL t it Does EC p eave iti ee ER TRE 88 Ae Ail AVRBEEU na Ie E REPE E UL E ILI c 88 A224 AN RET Site M 88 4 21S SAV Doct 89 42 04 save y eee dain iawn ign atin sien cen eal ae H I 89 4 215 RESE 89 ADAG KV ANG Ke 5 itii anf HAEC DERE DRE O 89 4 217 eee e e eir ORE ER EE ER AR E eb oC 89 ASO TB GN DD zx ntum etti A etn Im E 89 4 2 19 ec E eU e etae RE e pd deve ea eds 89 4 2 20 VEP PROM ctn cnc tr ien iei eet d e oct ttc hts 89 4 2 21 IC Mask ROM version only 90 4 3 Input output Circuits and Recommended Connection of Unused Pins 91 CH
261. a etaa aani 49 2 5 Pin Configuration Top 50 2 6 78K 0 Series Expansion cesses 53 2 7 Block Dlagram 5 itid edere tee eias ferien 55 2 8 Outline of Functioh nnne aea aaa ae Aaaa e aes aae aoa hae dads 56 2 9 Differences Between the uPD78058FY and uPD78058FY A 57 2 10 MasICOptIOUS acne neu LE MUI 58 CHAPTER PIN FUNCTION uPD78058F SUBSERIES eese esee nnne 59 3 1 Pin Function List erede e Rene 59 3 1 1 Normal operating mode pins sssesssseeeeneeeenneeen nennen nnne nnne nennen nennen 59 3 1 2 PROM programming mode pins PROM versions only 64 3 2 Description of Pin Functions nennen nennen nnne nennen annee nnn nannten nan 65 3 21 POO tO POZ PORO eset e etta reti eee cei cete t ete cedet i ce ee 65 3 2 2 PTO PIV Port T de DR Dt He EL RE 66 3 2 9 P20 to P2 7 Port 2 i oer nca ei eig ea a esee tere 66 3 2 4 P30 to P37 POMS iit e HR PUR ER AM REGARD ROBAR RNC E 67 3 2 5 P40 to PA7 Port4 enki i ee UE e p Ded ere pee 68 3 2 65 P50 to P57 POIDS ieir ee aute Dua te ee urere d tuba eee eth ate 68 3 277 POOTO P67 POFtO aoc ae ne Ee ede Rent edet ec et 68 3 2 8 PZO P72 POI aen t pet tert ote cea S et tht e c ede 69 3 2 9
262. ad the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction enabled Note Whether the ROM correction is used or not should be judged by the port input level For example when the P20 input level is high the ROM correction is used otherwise it is not used After reset store the contents that have been previously stored in the external nonvolatile memory with initialization routine for ROM correction of the user to internal expansion RAM see Figure 25 6 Set the start address of the instruction to be corrected to CORADO and CORAD1 and set bits 1 and 3 CORENO COREN 1 of the correction control register CORCN to 1 Set the entire space branch instruction BR addr16 to the specified address F7FDH of the internal expansion RAM with the main program After the main program is started the fetch address value and the values set in CORADO and CORAD1 are always compared by the comparator in the ROM correction circuit When these values match the correction branch request signal is generated Simultaneously the corresponding correction status flag CORSTO or CORST1 is set to 1 Branch to the address F7FDH by the correction branch request signal Branch to the internal expansion RAM address set with the main program by the entire space branch instruction of the address F7FDH When one place is corrected the correction program is executed When two places
263. address set to SVA when the wake up function specify bit WUP 1 If the bit 5 SIC of the interrupt timing specify register SINT is set the wake up function cannot be used even if WUP is set an interrupt request signal is generated when bus release is detected To use the wake up function clear SIC to 0 Cautions 1 Slave selection non selection is detected by matching of the slave address received after bus release RELD 1 For this match detection match interrupt request INTCSIO of the address to be generated with WUP 1 is normally used Thus execute selection non selection detection by slave address when WUP 1 2 When detecting selection non selection without the use of interrupt request with WUP z 0 do so by means of transmission reception of the command preset by program instead of using the address match detection method Error detection In the SBI mode the serial bus SBO SB1 status being transmitted is fetched into the destination device that is the serial I O shift register O 5100 Thus transmit errors can be detected in the following way a Method of comparing SIOO data before transmission to that after transmission In this case if two data differ from each other a transmit error is judged to have occurred b Method of using the slave address register SVA Transmit data is set to both SIOO and SVA and is transmitted After termination of transmission COI bit match signal coming from the address c
264. al input and crystal connection for subsystem oscillation The following operating modes can be specified bit wise 1 Port mode POO and P0O7 function as input only ports and P01 to P06 function as input output ports P01 to P06 can be specified for input or output ports bit wise with a port mode register 0 When they are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL 2 Control mode In this mode these ports function as an external interrupt request input an external count clock input to the timer and crystal connection for subsystem clock oscillation a INTPO to INTP6 INTPO to INTP6 are external interrupt request input pins which can specify valid edges rising edge falling edge and both rising and falling edges INTPO or INTP1 becomes a 16 bit timer event counter capture trigger signal input pin with a valid edge input b TIOO Pin for external count clock input to 16 bit timer event counter c TIO1 Pin for capture trigger signal to capture register CROO of 16 bit timer event counter d XT1 Crystal connect pin for subsystem clock oscillation 65 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 3 2 2 P10 to P17 Port 1 These are 8 bit input output ports Besides serving as input output ports they function as an A D converter analog input The following operating modes can be specified bit wise 1 2 Port mode T
265. an be used as an input output port Cautions 1 When the 3 wire serial I O mode is selected 00H should be set in ASIM 2 The operation mode should be switched after stopping the serial transmission operation 439 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Table 19 2 Serial Interface Channel 2 Operating Mode Settings 1 Operation Stop Mode CSIE2 70 P70 PM71 CSIM22 CSCK x x x Note 1 P71 PM72 P72 Start Bit x x x Note 1 Note 1 Note Shift Clock P70 SI2 RxD Pin P71 SO2 TxD Pin P72 SCK2 ASCK Pin Functions Functions Functions Other than above 2 3 wire Serial I O Mode CSIM2 CSIE2 CSIM22 Internal clock Setting prohibited P70 SI2 RxD Pin Functions P71 SO2 TxD Pin Functions 02 CMOS output 02 CMOS output P72 SCK2 ASCK Pin Functions SCk2 output Other than above 3 Asynchronous Serial Interface Mode CSIM2 CSIE2 CSIM22 External clock Note 1 x Internal clock Setting prohibited P70 SI2 RxD Pin Functions P71 SO2 TxD Pin Functions TxD CMOS output P72 SCK2 ASCK Pin Functions ASCK input P72 Note 1 Note External clock Internal clock External clock Internal clock ASCK input P72
266. an input port an on chip pull up resistor can be used by software STB P24 BUSY P25 SIO SBO SDAO P26 SOO SB1 SDA1 P27 SCKO SCL P30 Port 3 TOO P31 8 bit input output port TO1 P32 Input output mode can be specified bit wise TO2 P33 If used as an input port an on chip pull up resistor can be used by software TH P34 Tl2 P35 PCL P36 BUZ P37 P40 to P47 Port 4 ADO to AD7 8 bit input output port Input output mode can be specified in 8 bit units If used as an input port an on chip pull up resistor can be used by software Test input flag KRIF is set to 1 by falling edge detection P50 to P57 Port 5 A8 to A15 8 bit input output port LED can be driven directly Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software 128 CHAPTER 6 PORT FUNCTIONS Table 6 2 Port Functions uPD78058FY Subseries 2 2 Function Alternate Function N ch open drain input output port 8 bit input output port On chip pull up resistor can be specified by Input output mode can be specified mask option Mask ROM version only bit wise LEDs can be driven directly If used as an input port an on chip pull up resistor can be used by software ASTB Port 7 SI2 RxD 3 bit input output port SO2 TxD Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software SCK2
267. ance state when receiving data so write FFH in SIOO in advance The SBO or SB1 pin generates the SOO latch status and thus the SBO or SB1 pin output status can be manipulated by setting bit 0 RELT and bit 1 CMDT of serial bus interface control register SBIC However do not carry out this manipulation during serial transfer Control the SCKO pin output level in the output mode internal system clock mode by manipulating the P27 output latch refer to 16 4 5 SCK0 P27 pin output manipulation CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 3 Other signals Figure 16 33 shows RELT and CMDT operations Figure 16 33 RELT and CMDT Operations 800 Latch RELT CMDT 4 5 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIOO when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIEO 1 Internal serial clock is stopped or SCKO is at high level after 8 bit serial transfer Cautions 1 If CSIEO is set to 1 after data write to SIOO transfer does not start 2 It is necessary to set the N ch open drain output in the high impedance state when receiving data so write FFH in SIOO in advance Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIFO is set Error detection In the 2 wire serial I O mode the serial bus SBO SB1 status be
268. and data identify function Serial data is distinguished into addresses commands and data Chip select function by address transmission The master executes slave chip selection by address transmission Wake up function The slave can easily judge address reception chip select judgement with the wake up function which can be set or cleared by the software When the wake up function is set the interrupt request signal INTCSIO is generated upon reception of a match address Thus when communication is executed with two or more devices the CPU except the selected slave devices can operate regardless of underway serial communications Acknowledge signal ACK control function The acknowledge signal to check serial data reception is controlled Busy signal BUSY control function The busy signal to report the slave busy state is controlled CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 2 SBI definition The SBI serial data format and the signals to be used are defined as follows Serial data to be transferred with SBI consists of three kinds of data address command and data Figure 16 11 shows the address command and data transfer timings Figure 16 11 SBI Transfer Timings Address Transfer SBO SB1 BUSY Bus Release Y Signal Address Command Transfer Command Signal d crease SBO SB1 MCK BUSY Command Data Transfer SCKO LEE E epe p 5 0 SB
269. and fxr 32 768 kHz 1 instruction 1 instruction One instruction is the minimum instruction execution time with the pre switchover CPU clock Selection of the CPU clock cycle scaling factor PCCO to PCC2 and switchover from the main system clock to the subsystem clock changing CSS from 0 to 1 should not be performed simultaneously Simultaneous setting is possible however for selection of the CPU clock cycle scaling factor PCCO to PCC2 and switchover from the subsystem clock to the main system clock changing CSS from 1 to 0 HOLVH3N3O 190109 Z4HdldVHO CHAPTER 7 CLOCK GENERATOR 7 6 2 Th System clock and CPU clock switching procedure is section describes switching procedure between system clock and CPU clock Figure 7 10 System Clock and CPU Clock Switching Vpop RESET Interrupt Request Signal System Clock fxx fxx fxr fxx CPU Clock um t Speed Subsystem Clock High Speed Operation Operation Operation E Wait 26 2 ms 5 0 MHz Internal Reset Operation The CPU is reset by setting the RESET signal to low level after power on After that when reset is released by setting the RESET signal to high level main system clock starts oscillation At this time oscillation stabilization time 2 fx is secured automatically After that the CPU starts executing the instruction at the minimum speed of the main system clock 12 8 us when operated at 5 0 MHz After the lapse o
270. and port If this device is used in application fields where reduction of noise generated internally in the microprocessor is required please connect to a separate power supply with the same electrical potential as Vpp 2 The AVss pin is used as the ground potential for the A D converter and D A convertor and as the ground potential for the ports If this device is used in application fields where reduction of noise generated internally in the microprocessor is required please connect it to a ground line which is separate from Vss 81 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 4 1 2 PROM programming mode pins PROM versions only PROM programming mode setting When 5 V or 12 5 V is applied to the Ver pin or a low level voltage is applied to the RESET pin the PROM programming mode is set VPP Input High voltage application for PROM programming mode setting and program write verify AO to A16 Input Address bus to D7 Input output Data bus Input PROM enable input program pulse input Input Read strobe input to PROM Input Program program inhibit input in PROM programming mode Positive power supply Ground potential 82 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 4 2 Description of Pin Functions 4 2 1 to P07 Port 0 These are 8 bit input output ports Besides serving as input output ports they function as an external interrupt request input an external coun
271. and the output disable mode is set Therefore if multiple uPD78P058Fs or 78P058FYs are connected to the data bus data can be read from any one device by controlling the OE pin 540 CHAPTER 26 PD78P058F 78P058FY 3 4 5 6 7 8 Standby mode Setting CE to H sets the standby mode In this mode data output becomes high impedance irrespective of the status of OE Page data latch mode Setting CE to H PGM to H and OE to L at the start of the page write mode sets the page data latch mode In this mode 1 page 4 byte data is latched in the internal address data latch circuit Page write mode After a 1 page 4 byte address and data are latched by the page data latch mode a page write is executed by applying a 0 1 ms program pulse active low to the PGM pin while CE H and OE H After this program verification can be performed by setting CE to L and OE to L If programming is not performed by one program pulse repeated write and verify operations are executed X times X x 10 Byte write mode A byte write is executed by applying a 0 1 ms program pulse active low to the PGM pin while CE L and OE H After this program verification can be performed by setting OE to L If programming is not performed by one program pulse repeated write and verify operations are executed X times X x 10 Program verify mode Setting CE to L PGM to H and OE to L sets the program verify mode After writing is performed thi
272. any you d like to report errors or suggest improvements to us Tel FAX Address Thank you for your kind support North America Hong Kong Philippines Oceania Asian Nations except Philippines NEC Electronics Inc NEC Electronics Hong Kong Ltd NEC Electronics Singapore Pte Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 65 250 3583 Fax 1 800 729 9288 1 408 588 6130 cea tronics Hong Kong Ltd Nees iconductor Technical Hotli ectronics Hong Kong Ltd emiconductor Technical Hotline PEG ACTES UOS OTON lt apni Branch Fax 044 548 7900 Technical Documentation Dept Fax 02 528 4411 Fax 49 211 6503 274 South America Taiwan NEC do Brasil S A NEC Electronics Taiwan Ltd Fax 455 11 6465 6829 Fax 02 719 5951 would like to report the following error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Excellent Clarity Technical Accuracy Organization
273. are corrected the correction status flag is checked with the branch destination judgment program and branches to the correction program 531 CHAPTER 25 ROM CORRECTION 532 Figure 25 7 ROM Correction Operation Internal ROM program start Does fetch address No match with correction address Correction branch branch to address F7FDH Correction program execution ROM correction CHAPTER 25 ROM CORRECTION 25 5 ROM Correction Example The example of ROM correction when the instruction at address 1000H ADD A 1 is changed to ADD A 2 is as follows Figure 25 8 ROM Correction Example Internal ROM Internal Expansion RAM 0000H 0080H Program start ADD A 2 BR 1002 1000H ADD A 1 1002H MOV B A BR F702H EFFFH 1 Branches to address F7FDH when the preset value 1000H in the correction address register 0 1 CORADO CORAD 1 matches the fetch address value after the main program is started 2 Branches to any address address F702H in this example by setting the entire space branch instruction BR laddr16 to address F7FDH with the main program 3 Returns to the internal ROM program after executing the substitute instruction ADD A 2 533 CHAPTER 25 ROM CORRECTION 25 6 Program Execution Flow Figures 25 9 and 25 10 show the program transition diagrams when the ROM correction is used Figure 25 9 Program Transition Diagram When One
274. art Serial transfer is started by setting transfer data to the serial I O shift register 0 SIOO when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIEO 1 Internal serial clock is stopped or SCKO is at high level after 8 bit serial transfer Cautions 1 If CSIEO is set to 1 after data write to SIOO transfer does not start 2 When receiving data it is necessary to set the N ch open drain output in the high impedance state so please write FFH in SIOO in advance However in the case of the wake up function instruction bit WUP z 1 the N ch open drain output is always in the high impedance state so it is not necessary to write FFH SIOO before reception 3 If data is written to SIOO when the slave is busy the data is not lost When the busy state is cleared and SBO or SB1 input is set to the high level READY state transfer starts Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIFO is set Furthermore after inputting RESET in the pin used as the data input and output SBO or SB1 be sure to make the following settings before serial transmission of the first byte of data 1 Set 1 to the P25 and P26 output latches 2 Set 1 to bit 0 RELT of the serial bus interface control register SBIC 39 Set 0 to the P25 and P26 output latches to swhich 1 was set 329 CHAPTER 16 SERIAL INTERFACE CHAN
275. atch timer nterval timer The watch timer and the interval timer can be used simultaneously 1 Watch timer When the 32 768 kHz subsystem clock is used a flag WTIF is set at 0 5 second or 0 25 second intervals When the 4 19 MHz standard 4 194304 MHz main system clock is used a flag WTIF is set at 0 5 second 2 or 0 25 second intervals Caution 0 5 second intervals cannot be generated with the 5 0 MHz main system clock You should Switch to the 32 768 kHz subsystem clock to generate 0 5 second intervals Interval timer Interrupt requests INTTM3 are generated at the preset time interval Table 10 1 Interval Timer Interval Time When operated at Interval Time fxx 2 5 0 MHz 24 x 1 fw When operated at fxx 2 4 19 MHz When operated at fxr 32 768 kHz 25 x 1 fw 28 x 1 fw 27 x 1 fw 28 x 1 fw fx fw 29 x 1 fw Main system clock frequency fx or fx 2 Main system clock oscillation frequency Subsystem clock oscillation frequency Watch timer clock frequency 27 or fxr 239 CHAPTER 10 WATCH TIMER 10 2 Watch Timer Configuration The watch timer consists of the following hardware Table 10 2 Watch Timer Configuration Counter 5 bits x 1 Timer clock select register 2 TCL2 Watch timer mode control register TMC2 Control register 10 3 Watch Timer Control Registers The following two types of registers are used
276. atic data transmit receive address pointer 390 ASIM Asynchronous serial interface mode register ssssssssssssssss 439 447 449 462 ASIS Asynchronous serial interface status register esssssssseeeeenen 441 450 B BRGC Baud rate generator control register ccecsscceeeseeeeseeeeeeseeeeeeeeeeseeeeeseeeeeseeeensnseeeees 442 451 463 C CORADO Correction address register O cceseeseeteseeeseeeeeeceeeeeaeeesaeeeaeecaeeseaeesaeeseaeeseaeeeaeeseaeeeaeeseaesneeeeaeee 528 CORAD1 Correction address register 1 nennen nnne nnne nnne nne nnne nnne 528 CORCN Correction control register 529 587 APPENDIX D REGISTER INDEX CROO CR10 CR20 CRCO CSIMO CSIM1 CSIM2 D DACSO DACS1 DAM I IFOH IFOL IF1L IMS INTMO INTM1 IXS KRM M MKOH MKOL MK1L MM O OSMS OSTS P PO P12 P13 P1 P2 P3 P4 P5 P6 P7 588 GCapture compare register 00 esee ee Eines 177 Capture compare register OF oed ead M 177 Cormpare registers 10 nier o Ee A ED a aE Eaa A eA IE I i e d RELIEF oxic 219 Compare registers 20 2 dete ee Peer acte eae dad aad re e bp tear 219 Capture compare control register 0 ssssssssssssssssseeee eene nnn
277. b Capture compare control register 0 CRCO PWM mode CRC02 CRCO1 CRCOO emo CROO set as compare register c 16 bit timer output control register TOCO OSPT OSPE TOC04 LVSO LVRO TOCO1 TOEO TOO Output Enabled Specifies Active Level Remarks 1 0 1 Setting O or 1 allows another function to be used simultaneously with PWM output See the description of the respective control registers for details 2 x Don t care 190 CHAPTER 8 16 TIMER EVENT COUNTER By integrating 14 bit resolution PWM pulses with an external low pass filter they can be converted to an analog voltage and used for electronic tuning and D A converter applications etc The analog output voltage Van used for D A conversion with the configuration shown in Figure 8 14 is as follows arcs ares capture compare register 00 CROO value 216 Vner External switching circuit reference voltage Figure 8 14 Example of D A Converter Configuration with PWM Output LA PD78058F 78058FY PWM signal Analog Output Switching Circuit Low Pass Filter Figure 8 15 shows an example in which PWM output is converted to an analog voltage and used in a voltage synthesizer type TV tuner Figure 8 15 TV Tuner Application Circuit Example 110 V uPD78058F 78058FY 22 kQ 47kQ 4A7kQ 47 100 pF 2SC 0 22 uF j 0 22uF 0 22uF Electronic TOO P30 10 22 uF 022uF 0 221 8
278. be prepared To be prepared IE 78064 R EM EEU 905 EEU 1443 IE 780308 R EM U11362J U11362E EP 78230 EEU 985 EEU 1515 EP 78054GK R EEU 932 EEU 1468 SM78KO System Simulator Windows Base Reference U10181J U10181E SM78K Series System Simulator External component user open interface specifications U10092J U10092E ID78KO0 NS Integrated Debugger U12900J To be prepared ID78KO Integrated Debugger EWS Base Reference U11151J ID78KO Integrated Debugger PC Base Reference U11539J ID78KO Integrated Debugger Windows Base Caution The above documents are subject to change without prior notice Be sure to document for designing 12 Guide U11649J use the latest Documents for Embedded Software User s Manual Document Name 78K 0 Series Real Time OS Basics Document No Japanese U11537J English U11537E Installation U11536J U11536E OS for 78K 0 Series MX78K0 Basics e Other Documents Document Name IC PACKAGE MANUAL U12257J U12257E Document No Japanese C10943X English Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531E Reliability Quality Control on NEC Semiconductor Devices C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Elec
279. bit 6 FRC of the processor clock control register PCC to 1 do not use the feedback resistor internal to the subsystem clock oscillator When using pins P10 ANIO to P17 ANI7 as analog input for the A D converter set port 1 to the input mode The on chip pull up resistor will be automatically disabled 77 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 1 Port pins 2 3 Pin Name P37 Input Output Function Port 3 8 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software After Reset Alternate Function P40 to P47 Port 4 8 bit input output port Input output mode can be specified in 8 bit units If used as an input port an on chip pull up resistor can be used by software Test input flag KRIF is set to 1 by falling edge detection ADO to AD7 P50 to P57 Port 5 8 bit input output port LED can be driven directly Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software A8 to A15 Port 6 N ch open drain input output port On chip pull up resistor can be specified by mask option Input output mode can be Mask ROM version only LEDs can be driven directly 8 bit input output port specified bit wise If used as an input port an on chip pull up resistor can be used by software ASTB 78 P
280. bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Symbol D 4 Address After Reset R W cmo peso meer mm m R W CSIEO Serial Interface Channel 0 Operation Control 0 Operation stopped 1 Operation enabled 299 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 16 4 2 3 wire serial I O mode operation The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K Series Communication is carried out with three lines of serial clock SCKO serial output 00 and serial input S10 1 Register setting 300 The 3 wire serial I O mode is set with serial operating mode register 0 CSIMO and the serial bus interface control register SBIC a Serial operating mode register 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES Symbol D 4 Address After Reset R W wo eee ree mm se R W Serial Interface Channel 0 Clock Selection Input Clock to SCKO pin from off chip 8 bit timer register 2 TM2 output Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 CSIM Operation SIO SBO P25 SO0 SB1 P26 SCKO0 P27 03 Mode Pin Function Pin Function Pin Function
281. ble interrupt Multiple Interrupt Request Non maskable Interrupt Request Maskable Interrupt Request PR 0 PR 1 IE 1 0 IE 1 Maskable interrupt ISP 0 ISP 1 Software interrupt Remarks 1 2 3 E Multiple interrupt enable D Multiple interrupt disable ISP and IE are the flags contained in PSW ISP 0 An interrupt with higher priority is being serviced ISP 1 An interrupt request is not accepted an interrupt with lower priority is being serviced IE 0 Interrupt request acknowledge is disabled IE 1 Interrupt request acknowledge is enabled PR is a flag contained in PROL PROH and PR1L PR 0 Higher priority level PR 1 Lower priority level CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 16 Multiple Interrupt Example 1 2 Example 1 Example of multiple interrupt requests being generated twice Main Processing INTxx INTyy INTzz Servicing Servicing Servicing IE 0 IE 0 Y Y INTxx INTyy gt INTzz PR 1 PR 0 PR 0 Y RETI Y RETI RETI During processing of interrupt INTxx 2 interrupt requests INTyy and INTzz are received and multiple interrupts are generated Before reception of each interrupt request the IE command must be issued and the interrupt request reception permitted status must exist Example 2 Example of multiple interrupts not being generated due to priority order contr
282. bugger ID78K0 This emulator should be used in combination with emulation probe and interface adapter which is required to connect this emulator to the host machine IE 70000 98 IF B or This adapter is required when using the PC 9800 Series computer except IE 70000 98 IF CNete 1 notebook type as the IE 78001 R A host machine Interface adapter IE 70000 PC IF B or This adapter is required when using the IBM PC AT and their compatible IE 70000 PC IF CNete 1 machine as the IE 78001 R A host machine Interface adapter IE 78000 R SV3 This is an adapter and cable necessary when using EWS as a host Interface adapter machine for the IE 78000 R A As Ethernet 10Base 5 is supported With other mode commercially available conversion adapter is necessary IE 780308 NS EM 1 Note 1 This board emulates the operations of the peripheral hardware peculiar to Emulation board a device It should be used in combination with an in circuit emulator and emulation probe conversion IE 78K0 R EX1Nete 1 This board is required when using the IE 780308 NS EM1 with the Emulation probe IE 78001 R A conversion board IE 78064 R EMNete 2 This is a board for emulation of peripheral hardware inherent to this device IE 780308 R EM IE 78064 R EM is for 3 0 to 6 0 V and IE 780308 R EM is for 2 0 to 5 0 V Emulation board Use in combination with a IE 78001 R A NP EP 78230GC R This probe is used to connect the in circuit emulator to the target
283. buzzer output function set PM36 and output latch of P36 to 0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 13 3 Port Mode Register 3 Format After Symbol 7 6 5 Address Reset R W 4 3 2 1 0 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W PM3n P3n Pin Input Output Mode Selection n 0 to 7 Output mode output buffer ON Input mode output buffer OFF 260 CHAPTER 14 A D CONVERTER 14 1 A D Converter Functions The A D converter converts an analog input into a digital value It consists of 8 channels ANIO to ANI7 with an 8 bit resolution The conversion method is based on successive approximation and the conversion result is held in the 8 bit A D conversion result register ADCR The following two methods are used for starting an A D conversion operation 1 Hardware start Conversion is started by trigger input INTP3 2 Software start Conversion is started by setting the A D converter mode register ADM Select 1 channel from the analog inputs ANIO to ANI7 and execute A D conversion An A D conversion operation ends after the A D conversion operation at hardware start is completed and an interrupt request INTAD is generated In the case of software start the A D conversion operation is repeated Each time an A D conversion ends an interrupt request INTAD is generated Cautions For pins which have common fu
284. by clearing and restarting the count see register settings in Figure 8 24 The edge specification can be selected from two types rising and falling edges by external interrupt mode register 0 INTMO bits 2 and 3 ES10 and ES11 In a valid edge detection the sampling is performed by a cycle selected by the sampling clock selection register SCS and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Caution Ifthe valid edge of TIO0 POO is specified to be both rising and falling edge the 16 bit capture compare register 00 CROO cannot perform the capture operation Figure 8 24 Control Register Settings for Pulse Width Measurement by Means of Restart a 16 bit timer mode control register TMCO TMC03 TMC02 TMC01 OVFO RE SECO b Capture compare control register 0 CRCO Clear amp start with valid edge of TIOO PO0 pin CRC02 CRCO01 CRCOO oe ee ee CROO set as capture register Captured in CROO on invalid edge of TIOO PO0 Pin CR01 set as capture register Remark 0 1 Setting O or 1 allows another function to be used simultaneously with pulse width measure ment See the description of the respective control registers for details Figure 8 25 Timing of Pulse Width Measurement Operation by Means of Restart with Rising Edge Specified Countclock J LJ L gl deed S as A e EST 1 1 1 Count Val
285. can be specified bit wise If used as an input port on chip pull up resistor can be used by software P130 and P131 Port 13 ANOO ANO1 2 bit input output port Input output mode can be specified bit wise If used as an input port on chip pull up resistor can be used by software Cautions For pins which have alternate functions as port output See 3 1 1 Normal operating mode pins 1 Port Pins do not execute the following operations during A D conversion If performed then the general error standards cannot be maintained during A D conversion 1 If it is used as a port rewriting the output latch of its output 2 Even if it is not used as a port changing the output level of pins used as outputs 127 CHAPTER 6 PORT FUNCTIONS Table 6 2 Port Functions uPD78058FY Subseries 1 2 Pin Name Function Alternate Function POO Port 0 Input only INTPO TIOO P01 8 bit input output port Input output mode can be specified INTP1 TIO1 P02 bit wise INTP2 If used as an input port an on chip pull up INTP3 P04 resistor can be used by software INTP4 P05 INTP5 P06 INTP6 P07 Input only XT1 P10 to P17 Port 1 ANIO to ANI7 8 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software P20 Port 2 SH P21 8 bit input output port SO1 P22 Input output mode can be specified bit wise SCK1 P23 If used as
286. cases In the 3 wire serial I O mode and 2 wire serial I O mode This circuit generates an interrupt request signal every eight serial clocks n the SBI mode When WUPNete is Q Generates an interrupt request signal every eight serial clocks When WUPNete is 1 Generates an interrupt request signal when the serial I O shift register 0 SIOO value matches the slave address register SVA value after address reception Note WUP is the wake up function specify bit It is bit 5 of serial operating mode register 0 CSIMO To use the wake up function WUP 1 clear bit 5 SIC of the interrupt timing specify register SINT to 0 Busy acknowledge output circuit and bus release command acknowledge detector These two circuits output and detect various control signals in the SBI mode These do not operate in the 3 wire serial I O mode and 2 wire serial I O mode 291 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 16 3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0 Timer clock select register 3 TCL3 Serial operating mode register 0 CSIMO Serial bus interface control register SBIC Interrupt timing specify register SINT e 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 0 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88
287. ceive address pointer ADTP is reset to the value it was at when transmission was started and the contents of the internal buffer s RAM are resent When a reception operation busy control and strobe control are not performed the P20 SI1 P23 STB and P24 BUSY pins can be used as ordinary input output ports The repeat transmission mode operation timing is shown in Figure 18 14 and the operation flowchart in Figure 18 15 Figure 18 16 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted in the repeat transmission mode Figure 18 14 Repeat Transmission Mode Operation Timing Interval Interval sor AD7ADGADSAD4ADSAD2AD ADO AD7ADOADSAD4AD3AD2ADTADO 7 Caution Since in the repeat transmission mode a read is performed on the internal buffer RAM after the transmission of one byte the interval is included in the period up to the next transmission As the internal buffer RAM read is performed at the same time as CPU processing the maximum interval is dependent upon the CPU operation and the value of the automatic data transmit receive interval specify register ADTI see 5 Auto matic transmit receive interval time 419 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 15 Repeat Transmission Mode Flowchart Write transmit data in internal buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Software Execution
288. ception and requires more waiting time the slave device outputs a wait signal on the bus to inform the master device of the wait status 2 12 bus definition 364 This section describes the format of serial data communications and functions of the signals used in the 12 bus mode First the transfer timings of the start condition data and stop condition signals which are output onto the signal data bus of the 12 bus are shown in Figure 17 14 Figure 17 14 12 Bus Serial Data Transfer Timing s VTA SN AVAL ss I PCa Sur 2 RAW ACK CO Data ACK Data Stop Condition Condition The start condition slave address and stop condition signals are output by the master The acknowledge signal ACK is output by either the master or the slave device normally by the device which has received the 8 bit data that was sent A serial clock SCL is continuously supplied from the master device CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES a Start condition When the SDAO SDA1 pin level is changed from high to low while the SCL pin is high this transition is recognized as the start condition signal This start condition signal which is created using the SCL and SDAO or SDA1 pins is output from the master device to slave devices to initiate a serial transfer See section 17 4 5 Cautions on use of I2C bus mode for details of the start condition output The start condition signal is detected by hardwa
289. cessing 424 0 us 1 5 fsck 2 Thedatatransfer intervalincludes an error The datatransfer minimum and maximum intervals are found from the following expressions n Value set in ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck Minimum 1 x 20 28 0 5 fxx fxx fsck Maximum n1 x 26 _36 15 fxx fsck Cautions 1 Do not write ADTI during operation of automatic data transmit receive function 2 Bits 5 and 6 must be set to zero 3 If the auto send and receive data transmission interval time is controlled using ADTI busy control becomes invalid see 18 4 3 4 a Busy control option Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 fsck Serial clock frequency 397 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format 4 4 Symbol 7 6 5 3 2 1 0 Address After Reset R W ADTI ADTI7 0 0 ADTIA ADTIS ADTI2 ADTI ADTIO FF6BH 00H R W ADTIS ADTI2 ADTI1 Data Transfer Interval Specification fxx 2 5 MHz Operation MinimumNete 446 4 us O 5 fsck MaximumNete 449 6 us 1 5 fsck 472 0 us 0 5 fsck 475 2 us 1 5 fsck 497 6 us 0 5 fscx 500 8 us 1 5 fsck 523 2 us 0 5 fscx 526 4 us 1 5 fsck 548 8 us 0 5 fscx 552 0 us 1 5 fsck
290. ch as the addition of a start bit parity bit and stop bit to data written in the transmit shift register TXS in accordance with the contents set in the asynchronous serial interface mode register ASIM Reception control circuit This circuit controls receive operations in accordance with the contents set in the asynchronous serial interface mode register ASIM It performs error checks for parity errors etc during a receive operation and if an error is detected sets a value in the asynchronous serial interface status register ASIS in accordance with the error contents 437 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers Serial operating mode register 2 CSIM2 Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Baud rate generator control register BRGC 1 Serial operating mode register 2 CSIM2 This register is set when serial interface channel 2 is used in the 3 wire serial I O mode CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to OOH Figure 19 3 Serial Operating Mode Register 2 Format D 6 5 4 3 2 1 0 CSIM Symbol Address After Reset R W CSIM2 FF72H 00H R W 0 UART mode 0 MSB LSB CSIE2 Operation Control in 3 wire Serial I O Mode 0 Operation stopped 1 Operatio
291. ckage and device file Precautions when using CC78K 0 under PC environment This C compiler package is a DOS based application However it can also run under Windows environment by using Project Manager included in the assembler package on Windows Part number uSxxxxCC78K0 File containing information peculiar to the device Used in combination with optional tools RA78K 0 CC78K 0 SM78KO0 ID78KO NS or ID78K0 Compatible OS and host machine differ depending on tools to be used Part number uSxxxxDF78054 Source program of functions for generating object library included in C compiler package Necessary for changing object library included in C compiler package according to customer s specifications Being a source file its operating environment does not depend on OS Part number uS xoxxCC78K0 L CC78K 0 C compiler package DF78054Nete Device file CC78K 0 L C library source file Note DF78054is common file that can be used with the RA78K 0 CC78K 0 SM78KO ID78KO NS and ID78KO0 Remark in part number differs depending the host machine and OS used LSxxxxRA78K0 LS xxxxCC78K0 uSxxxxDF78054 USxxxxCC78K0 L Host Machine Supply Media PC 9800 Series Windows Japanese etes 1 2 3 5 inch 2HD FD IBM PC AT and compatibles Windows Japanese etss 1 2 Windows English tes 1 2 3 5 inch 2HC FD HP9000 series 700 HP UX Rel 9 05 DAT
292. clock selected 122 us at 32 768 kHz operation 16 bit operation Multiply divide 8 bits x 8 bits 16 bits 8 bits Bit manipulate set reset test and Boolean operation BCD adjust etc port Total 69 CMOS input 2 CMOS I O 63 N ch open drain 4 A D converter 8 bit resolution x 8 channels D A converter 8 bit resolution x 2 channels Serial interface e 3 wire serial I O 2 wire serial bus mode selection possible 1 channel 3 wire serial I O mode Max 32 byte on chip auto transmit receive 1 channel 3 wire serial I O UART mode selectable 1 channel 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Timer output Three outputs 14 bit PWM output enable 1 Clock output 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz 5 0 MHz at 5 0 MHz operation with main system clock 32 768 kHz at 32 768 kHz operation with subsystem clock Buzzer output 1 2 kHz 2 4 kHz 4 9 kHz 9 8 kHz at 5 0 MHz operation with main system clock Notes 1 The capacities of the internal PROM and the internal high speed RAM can be changed using the memory switching register IMS 2 The capacity of the internal expansion RAM can be changed using the internal expansion RAM size switching register IXS 56 CHAPTER 2 OUTLINE uP
293. control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank Table 5 2 Corresponding Table of General Register Absolute Address Register Register Bank Function Absolute Absolute Address Bank Name Function Absolute Absolute Address Name Name Name Name F E D C B A 9 8 7 6 5 4 3 2 mco o lov lo lo min ST WEE ES ES Se ES E gt Trj r m m m mim mim mim mimm mim mim IT ITI ITI ITI m m m m mim mim mim mimm mim mm ID Es uL oq IL LI coz I pu a gt LO cr om im mim im m m mimimimimqim mimm TTE ITI ITI ITI Tl m m m ym TTE ITI Tl ITI TI m m m ym 106 CHAPTER 5 CPU ARCHITECTURE Figure 5 12 General Register Configuration a Absolute Name 16 Bit Processing 8 Bit Processing FEFFH RP3 FEF8H FEF7H RP2 FEEOH FEEFH RP1 FEE8H FEE7H RPO FEEOH 15 0 b Function Name 16 Bit Processing 8 Bit Processing E HL DE
294. cted with the baud rate generator control register BRGC 1 baud rate The amount of time for 2 clocks of 5 bit counter source clock fsck selected with BRGC 2 Example of countermeasures An example of the countermeasures is shown below Condition fx 5 0 MHz Processor clock control register PCC 00H Oscillation mode selection register OSMS 01H Baud rate generator control register BRGC BOH when 2400 bps is selected for baud rate Tcy 0 4 us tcy 0 2 us 1 sao 4197 us T1 T2 12 8 x 2 25 6 us SEO 3 clock tcy 469 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Example Main Processing UART Receive Error Interrupt INTSER Servicing INTSER is Generated Instructions for 2205 clocks MIN of CPU clock are required 7 Clocks MIN of CPU Clock Time from Interrupt Request to Servicing MOV A RXB 470 CHAPTER 20 REAL TIME OUTPUT PORT 20 1 Real Time Output Port Functions Data set previously in the real time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt request or external interrupt request generation then output externally This is called the real time output function The pins that output data externally are called real time output ports By using a real time output a signal that has no jitter can be output This port is therefore suitable for control of stepping mo
295. ction SO 1 Pin Function SH P20 Input ucc dU Note 2 x Note 2 x Note 2 x Note 2 x Note 2 x Shift Register 1 Operation Operation stop Serial Clock Counter Operation Control SI1 P20 Pin Function P20 CMOS input output SO1 P21 Pin Function P21 CMOS input output SCK1 P22 Pin Function P22 CMOS input output Note 3 1 Note 3 Operation enable Count operation 511 Note input of the automatic data transmit receive control register ADTC to 0 0 2 Can be used freely as port function SO1 CMOS output SCK1 Input SCK1 CMOS output If the external clock input has been selected with CSIM11 set to 0 set bit 1 BUSY1 and bit 2 STRB 3 Can be used as P20 CMOS input output when only transmitter is used clear bit 7 RE of ADTC to 0 Remark Don t care PMXX Port Mode Register PXX Port Output Latch 393 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 3 Automatic data transmit receive control register ADTC This register sets automatic receive enable disable the operating mode strobe output enable disable busy input enable disable error check enable disable and displays automatic transmit receive execution and error detection ADTC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADTC to 00H Figure 18 4 Automatic Data Transmit Receive Control Register Format
296. ctions When clock timer overflow occurs and when the port 4 falling edge is detected a corresponding test input flag is set 1 and a standby release signal is generated Unlike the interrupt function vector processing is not executed There are two test input factors as shown in Table 21 5 The basic configuration is shown in Figure 21 18 Table 21 5 Test Input Factors Test Input Factors Internal INTWT Watch timer overflow Internal INTPT4 Falling edge detection at port 4 External Figure 21 18 Basic Configuration of Test Function Internal bus Test input signal Standby release signal Remark IF test input flag MK test mask flag 21 5 1 Registers controlling the test function The test function is controlled by the following three registers Interrupt request flag register 1L IF1L Interrupt mask flag register 1L MK1L Key return mode register KRM The names of the test input flags and test mask flags corresponding to the test input signals are listed in Table 21 6 Table 21 6 Flags Corresponding to Test Input Signals Test Input Signal Name Test Input Flag Test Mask Flag INTWT WTIF WTMK INTPT4 KRIF KRMK 502 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 1 Interrupt request flag register 1L IF1L It indicates whether a watch timer overflow is detected or not It is set by a 1 bit memory manipulation instruction and 8 bit memory manipulation instruction It is set to OO
297. cument No Japanese U12142J English U12142E uPD78P058FY Data Sheet U12076J U12076E uPD78058F 78058FY Subseries User s Manual U12068J This manual 78K 0 Series User s Manual Instructions U12326J U12326E 78K 0 Series Instruction Table U10903J 78K 0 Series Instruction Set U10904J 78K 0 Series Application Note Basic III U10182J U10182E Caution The above documents are subject to change without prior notice Be sure to use the latest document for designing 11 Development Tool Documents User s Manuals Document No Document Name RA78KO Assembler Package Operation Japanese U11802J English U11802E Assembly language U11801J U11801E Structured assembler language U11789J U11789E RA78K Series Structured Assembler Preprocessor U12323J EEU 1402 CC78KO0 C Compiler Operation U11517J U11517E Language U11518J U11518E CC78KO0 C Compiler Application Note Programming know how U13034J EEA 1208 CC78K Series Library Source File U12322J PG 1500 PROM Programmer U11940J U11940E PG 1500 Controller PC 9800 Series MS DOS Base EEU 704 EEU 1291 PG 1500 Controller IBM PC Series PC DOS Base EEU 5008 U10540E IE 78K0 NS To be prepared To be prepared IE 78001 R A To be prepared To be prepared IE 780308 NS EM1 To
298. d From serial clock controller SCKO SCL P27 gt To Internal Logic CSIEO 1 and CSIMO1 CSIMOO are 1 0 or 1 1 respectively 2 In 2 bus mode The output level of the SCKO SCL P27 pin is manipulated by bit 3 CLC of the interrupt timing specify register SINT 1 Set the serial operating mode register 0 CSIMO SCL pin is set in the output mode and serial opera tion is enabled Set 1 to the P27 output latch SCL 0 while serial transfer is stopped 2 Manipulate the CLC bit of SINT by executing the bit manipulation instruction Figure 17 28 SCKO SCL P27 Pin Configuration Set 1 P27 output latch M Gin ScL ee p serial _ SCKO SCL P27 gt Internal Logic CSIEO 1 and CSIMO1 and CSIMOO are 1 0 or 1 1 respectively controller Note The level of the SCL signal is in accordance with the contents of the logic circuits shown in Figure 17 29 385 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Figure 17 29 Logic Circuit of SCL Signal CLC manipulated by bit manipulation instruction SCL Wait request signal Serial clock low while transfer is stopped Remarks 1 This figure indicates the relation of the signals and does not indicate the internal circuit 2 CLC Bit 3 of interrupt timing specify register SINT 386 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18 1 Serial Interface Channel 1 Functions Serial interface chann
299. d see 18 4 3 4 a Busy control option Remarks 1 fxx Main system clock frequency or fx 2 2 fx Main system clock oscillation frequency 3 fsck Serial clock frequency 396 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format 3 4 Symbol 7 Address After Reset R W ADTI ADTI7 Do qum ADTI3 ADTI2 ADTH ADTIO FF6BH 00H R W ADTI7 Data Transfer Interval Control No control of interval by ADT Note 1 Control of interval by ADTI ADTIO to ADTI4 Data Transfer Interval Specification fxx 2 5 MHz Operation ADTI2 ADTI1 MinimumNete 2 36 8 us O 5 fsck MaximumNete 2 40 0 us 1 5 fsck 62 4 us 0 5 fsck 65 6us 1 5 fsck 88 0 us 0 5 fsck 91 2us 1 5 fsck 113 6 us 0 5 fsck 116 8 us 1 5 fsck 139 2 us 0 5 fsck 142 4 us 1 5 fsck 164 8 us 0 5 fsck 168 0 us 1 5 fsck 190 4 us 0 5 fsck 193 6 us 1 5 fsck 216 0 us 0O 5 fsck 219 2 us 1 5 fsck 241 6 us O 5 fsck 244 8 us 1 5 fsck 267 2 us O 5 fsck 270 4 us 1 5 fsck 292 8 us 0 5 fsck 296 0 us 1 5 fsck 318 4 us 0O 5 fsck 321 6 us 1 5 fsck 344 0 us 0 5 fsck 347 2 us 1 5 fsck 369 6 us 0 5 fsck 372 8 us 1 5 fsck 395 2 us 0 5 fsck 398 4 us 1 5 fsck 420 8 us 0O 5 fsck The interval is dependent only on CPU pro
300. d Connection of Unused Pins Table 3 1 shows the input output circuit types of pins and the recommended conditions for unused pins Refer to Figure 3 1 for the configuration of the input output circuit of each type Table 3 1 Pin Input Output Circuit Types 1 2 Input Output Circuit Type Input Connect to Vss Pin Name Input Output Recommended Connection of Unused Pins PO1 INTP1 TI01 Input output Connect independently via a resistor to Vss PO2 INTP2 PO4 INTP4 POS INTP5 PO6 INTP6 PO7 XT1 Input Connect to P10 ANIO to P17 ANI7 Input output Connect independently via a resistor P20 SI1 Input output to Voo or Vss P21 SO1 P22 SCK1 P23 STB P24 BUSY P25 SIO SBO P26 SO0 SB1 P27 SCKO P30 TOO Input output P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 P40 ADO to P47 AD7 Input output Connect independently via a resistor to P50 A8 to P57 A15 Input output Connect independently via a resistor to or Vss CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 74 Table 3 1 Pin Input Output Circuit Types 2 2 Input Output Circuit Type P60 to P63 Mask ROM version P60 to P63 PROM version Input Output Input output Recommended Connection of Unused Pins Connect independently via a resistor to Voo P64 RD P65 WR P66 WAIT P67 ASTB
301. d DACS are set with 8 bit memory manipulation instructions RESET input sets these registers to Analog voltage output to the ANOO and ANO pins is determined by the following expression DACSn 256 ANOn output voltage AVner1 where n 0 1 Cautions 1 In the real time output mode when data that are set in DACSO and DACS1 are read before an output trigger is generated the previous data are read rather than the set data 2 In the real time output mode data should be set to DACSO and DACS 1 after an output trigger and before the next output trigger 281 CHAPTER 15 D A CONVERTER 15 3 D A Converter Control Registers The D A converter mode register DAM controls the D A converter This register sets D A converter operation enable stop The DAM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 15 2 D A Converter Mode Register Format After Symbol 7 6 Address Reset R W 5 4 3 2 DAM DAM5 DAM4 o DACE1 DACE0 FF98H 00H R W DACEO D A Converter Channel 0 Control D A conversion stop D A conversion enable D A conversion stop D A conversion enable DAM4 D A Converter Channel 0 Operating Mode Normal mode Real time output mode DAMS D A Converter Channel 1 Operating Mode 0 1 Normal mode Real time output mode Cautions 1 When using the D A converter a dual function port pin should b
302. d when pull up resistors are required the number of parts can be reduced and package area can be shrunk The mask option provided for the uPD78058F Subseries is shown in Table 1 2 Table 1 2 Mask Options of Mask POM Versions P60 to P63 Pull up resistors can be incorporated in 1 bit units 46 CHAPTER 2 OUTLINE uPD78058FY SUBSERIES 2 1 Features O00 0 Compared to the conventional uPD78054Y Subseries EMI Electro Magnetic Interference noise has been reduced On chip high capacity ROM and RAM Program Memory Data Memory ROM Part Number Internal High Speed RAM Internal Buffer RAM Internal Expansion RAM uPD78056FY 48 Kbytes 1024 bytes 32 bytes None uPD78058FY 60 Kbytes 1024 bytes uPD78PO58FY KbytesNote 1 1024 bytesNote 1 1024 byesNote 2 Notes 1 The capacities of internal PROM and internal high speed RAM can be changed by means of the memory size switching register IMS 2 The capacity of internal expansion RAM can be changed by means of the internal expansion RAM size switching register IXS External Memory Expansion Space 64 Kbytes Minimum instruction execution time changeable from high speed 0 4 us In main system clock 5 0 MHz operation to ultra low speed 122 us In subsystem clock 32 768 kHz operation Instruction set suited to system control Bit manipulation possible in all address spaces Multiply and divide instructions I O ports 69 N ch open drain ports 4 8 bit
303. dde aee e Ue eee ie enia ELE ete dexter RS cene 437 586 APPENDIX D REGISTER INDEX S Sampling clock select register SCS sssssssssssssessseseeeee eene nennen nennen nennen nnns 186 488 Serial bus interface control register SBIC 296 302 314 333 349 355 360 369 Seriall O shift register 0 SIQ0 terret t D leot tg e dr em 290 342 Serial I O shift register T SIQT au cadit crt trei td te ic nente ede ca 390 Serial operating mode register 0 CSIMO 294 300 312 331 347 354 359 368 Serial operating mode register 1 CSIM1 ssssssssseeeeeeeenneeenneen nene 393 403 Serial operating mode register 2 CSIM2 ssssssssseeneeeeneeeneennen nennen 438 446 448 461 16 bit time register a ee T e bebe et aee nee 219 16 bit timer mode control register 180 16 bit timer output control register TOCO ssessssssssseseeeeneeneeenene nennen nennen nnne nnn 182 T6 bit timer register T MO teat tele rtm re Piet eii td tone e ied tee 178 Slave address register SVA oss e seme dee pte ignea de e eee TR decre EET edid 290 342 362 373 Special f rction register SER roten redegi Pai eade ime ono dr er pd parre eren 108 Successive approximation register SAR
304. de register 13 PM13 When pins P130 and P131 are used as input port pins an on chip pull up resistor can be used as a 2 bit unit by means of pull up resistor option register H PUOH Alternate function includes D A converter analog output RESET input sets the input mode Figure 6 18 shows a block diagram of port 13 Caution When only either one of the D A converter channels is used with AVreri lt Vpp the other pins that are not used as analog outputs must be set as follows Set PM13 x bit of the port mode register 13 PM13 to 1 input mode and connect the pin to Vss Set PM13 x bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low level from the pin Figure 6 18 P130 and P131 Block Diagram AVop e WRPuo f A PUO13 RD re o km e g Hs Output Latch P130 ANOO S P130 and P131 131 ANO1 WRem PM130 PM131 PS es b PUO Pull up resistor option register Port mode register RD Port 13 read signal WR Port 13 write signal 145 CHAPTER 6 PORT FUNCTIONS 6 3 Port Function Control Registers The following four types of registers control the ports Port mode registers PMO to PM3 PM5 to PM7 PM12 PM13 Pull up resistor option register PUOH PUOL Memory expansion mode register MM Key return mode register KRM 1 Port mode registers
305. detected CORSTO 0 1 Detected ORENO Correction address register 0 and fetch address match detection control Disabled Enabled CORST1 Correction address register 1 and fetch address match detection Not detected Detected Note Bits 0 and 2 are read only bits COREN Correction address register 1 and fetch address match detection control 529 CHAPTER 25 ROM CORRECTION 25 4 ROM Correction Application 1 Store the correction address and instruction after correction patch program to nonvolatile memory such as outside the microcontroller When two places should be corrected store the branch destination judgment program as well The branch destination judgment program checks which one of the addresses set to correction address register 0 1 CORADO or CORAD1 generates the correction branch Figure 25 4 Storing Example to EEPROM When One Place Is Corrected EEPROM Source program 00H CSEG AT 1000H 01H 02H ADD A 2 RA78K 0 BR 11002H FFH Figure 25 5 Connecting Example with EEPROM Using 2 Wire Serial I O Mode AL PD78058F 78058FY EEPROM Voo SCKO SCL SB1 SDA P32 cs 530 CHAPTER 25 ROM CORRECTION 2 Assemble in advance the initialization routine as shown in Figure 25 6 to correct the program Figure 25 6 Initialization Routine Initialization ROM correction Is ROM N correction used ote e Lo
306. e 13 2 Timer Clock Select Register 2 Format 5 4 Address After R W Reset FF42H 00H R W Watchdog Timer Count Clock Selection MCS 1 fx 2 625 kHz fx 2 813 kHz fx 2 313 kHz fx 2 156 kHz fx 2 156 kHz fx 2 78 1 kHz fx 29 78 1 kHz fx 2 39 1 kHz fx 2 39 1 kHz fx 2 19 5 kHz fx 2 19 5 kHz fx 2 9 8 kHz fx 2 9 8 kHz fx 2 4 9 kHz fxx 2 fx 2 2 4 kHz Watch Timer Count Clock Selection fx 2 1 2 kHz MCS 1 fx 2 39 1 kHz fx 2 19 5 kHz 32 768 kHz TCL26 Buzzer Output Frequency Selection Buzzer output disable MCS 1 fxx 2 fx 2 9 8 kHz fx 2 4 9 kHz fxx 2 fx 2 4 9 kHz fx 2 2 4 kHz fxx 2 fx 2 2 4 kHz fx 2 1 2 kHz Setting prohibited Caution When rewriting TCL2 to other data stop the timer operation beforehand Remarks 1 2 9m x fx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency fxr Subsystem clock oscillation frequency x don t care MCS Bit 0 of oscillation mode selection register OSMS Figures in parentheses apply to operation with fx 5 0 MHz or fxr 32 768 kHz 259 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 2 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P36 BUZ pin for
307. e 16 bit timer mode control register TMCO capture compare control register 0 CRCO and the 16 bit timer output control register TOCO as shown in Figure 8 13 allows operation as PWM output Pulses with the duty rate determined by the value set in 16 bit capture compare register 00 CROO beforehand are output from the TOO P30 pin Set the active level width of the PWM pulse to the high order 14 bits of CROO Select the active level with bit 1 TOCO01 of the 16 bit timer output control register This PWM pulse has a 14 bit resolution The pulse can be converted to an analog voltage by integrating it with an external low pass filter LPF The PWM pulse is formed by a combination of the basic cycle determined by 28 and the sub cycle determined by 214 so that the time constant of the external LPF can be shortened Count clock can be selected with bits 4 to 6 TCLO4 to 1 06 of the timer clock select register 0 TCLO PWM output enable disable can be selected with bit 0 TOEO of TOCO Cautions 1 PWM operation mode should be selected before setting CROO 2 Be sure to write 0 to bits 0 and 1 of CROO Do not select PWM operation mode for external clock input from the TIOO POO INTPO pin 189 CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 13 Control Register Settings for PWM Output Operation a 16 bit timer mode control register TMCO TMC03 TMC02 1 OVFO
308. e 182 Serial operating mode register 0 294 300 312 331 347 354 359 368 Serial operating mode register 1 nennen nennen 393 403 Serial operating mode register 2 sssssssssseeeneeneennennnns 438 446 448 461 D A conversion value set register O 281 D A conversion value set register 1 281 D A converter mode register nnne nnn nnne nnne nennen inneren nnne 282 Interrupt request flag register OH ssssssssesseneeeneeneennneen nennen nnne nnen nennen nnne 483 Interrupt request flag register OL 483 Interrupt request flag register 1L emen menn 483 503 Memory size switching 1 a N aai 509 538 External interrupt mode register 0 ccesesceseseeeteseeeeseeneeeceeeeneseneesensesseeeenenenseseeneeessenens 185 486 External interrupt mode register 1 sse 268 486 Internal expansion RAM size switching register 539 Key return mode 151 504 Interrupt mask flag register OH eene nennen nennen 484 Interr pt mask flag register OL uicu iier eee tee deat che tir eed 484 Interru
309. e after 8 clock pulses are input Used 1 C bus mode 9 clock wait Generates interrupt service request at rising edge of 9th SCKO clock cycle In the case of master device makes SCL output low to enter wait state after 9 clock pulses are output In the case of slave device makes SCL output low to request wait state after 9 clock pulses are input R W Wait Sate Cancellation Control Wait state has been cancelled Cancels wait state Automatically cleared to 0 when the state is cancelled Used to cancel wait state by means of WATO and WAT1 R W Clock Level 2 Used in I C bus mode Make output level of SCL pin low unless serial transfer is being performed Used in 2 bus mode Make SCL pin enter high impedance state unless serial transfer is being performed except for clock line which is kept high Used to enable master device to generate start condition and stop condition signals Notes 1 Bit 6 CLD is a read only bit 2 When not using the I C mode set CLC to 0 351 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Figure 17 6 Interrupt Timing Specify Register Format 2 2 R W SVAM SVA Bit to be Used as Slave Address 0 Bits 0 to 7 1 Bits 1 to 7 R W INTCSIO Interrupt Source Selection CSIIFO is set to 1 upon termination of serial interface channel 0 transfer CSIIFO is set to 1 upon stop condition detection or termination of serial
310. e input mode output mode in 1 bit units with the port mode register 0 POO and 07 pins are input only ports When P01 to P06 pins are used as input ports an on chip pull up resistor can be used to them in 6 bit units with a pull up resistor option register L PUOL Alternate functions include external interrupt request input external count clock input to the timer and crystal connec tion for subsystem clock oscillation RESET input sets port 0 to input mode Figures 6 2 and 6 3 show block diagrams of port 0 Caution Because port 0 also serves for external interrupt request input when the port function output mode is specified and the output level is changed the interrupt request flag is set Thus when the output mode is used set the interrupt mask flag to 1 130 CHAPTER 6 PORT FUNCTIONS Figure 6 2 P00 and P07 Block Diagram Internal bus A D e o lt q POU INTPO TIOO PO7 XT1 gn Figure 6 3 P01 to P06 Block Diagram AVop WRpuo 4 PUOO Jo P ch RD o 8 WRport 1 1 101 Output Latch POZ INTP2 tz d P01 to PO6 to PO6 INTP6 WRem 1 to 6 in m PUO Pull up resistor option register Port mode register RD Port 0 read signal WR Port 0 write signal 131 CHAPTER 6 PORT FUNCTIONS 6 2 2 Port 1 Port 1 is an 8 bit input output port
311. e interrupt request signals INTTM1 and INTTM2 are generated Figure 9 9 External Event Counter Operation Timings with Rising Edge Specified mPinnpt LI LJ LI LI LILI LI LILI LILI LII TMH Count Value X 00 X01 X o2 X 03 y 04 y 05 X XNAK N X 90 Ko X 02 X 09 X CR10 N INTTM1 Remark N 00H to FFH 228 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 3 Operation as a Square Wave Output Operates as a square wave output at the desired frequency with the values set previously in the 8 bit conveyor registers 10 and 20 CR10 CR20 as the interval The TO1 P31 or TO2 P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20 by setting bit O TOE1 or bit 4 TOE2 of the 8 bit timer output control register TOC1 to 1 This enables a square wave with any selected frequency to be output Table 9 8 8 Bit Timer Event Counter Square Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS 1 MCS 0 MCS 1 MCS 0 2 x 1 fx 22 x 1 fx 29 x 1 fx 210 x 1 fx 2 x 1 fx 22 x 1 fx 400 ns 800 ns 102 4 us 204 8 us 400 ns 800 ns 22 x 1 fx 23 x 1 fx 210 x 1 fx 211 x 1 fx 22 x 1 fx 23 x 1 fx 800 ns 1 6 us 204 8 us 409 6 us 800 ns 1 6 us 23 x 1 fx 24 x 1 fx 211 x 1 fx 212 x 1 fx 23 x 1 fx 24 x 1 fx 1 6 us 3 2 us 409 6 us 819 2 us 1 6 us 3 2 us 24 x 1 fx 25 x 1 fx 212 x 1 fx 213 x 1 fx 24 x 1 fx 25 x 1 fx 3 2 us 6 4 us 819 2 us
312. e number of components to add to the device resulting in board space saving The mask options provided in the uPD78058FY Subseries are shown in Table 2 2 Table 2 2 Mask Options of Mask ROM Versions P60 to P63 Pull up resistor connection can be specified in 1 bit units 58 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 3 1 Pin Function List 3 1 1 Normal operating mode pins 1 Port pins 1 3 Input Output Port 0 POO P06 8 bit input output port Po7Note 1 Function Input only After Reset Alternate Function INTPO TIOO Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software INTP1 TIO1 INTP6 Input only XT1 P10 to P17 Port 1 8 bit input output port Input output mode can be specified bit wise If used as input port an on chip pull up resistor can be used by softwareNote 2 ANIO to ANI7 Port 2 8 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software SIO SBO SOO SB1 When the PO7 XT1 pin is used as an input port set the bit 6 FRC of the processor clock control register PCC to 1 do not use the feedback resistor internal to the subsystem clock oscillator When using pins P10 ANIO to P17 ANI7 as analog input for the A D converter set port 1 to the input mode The
313. e set to the input mode and a pull up resistor should be disconnected 2 Always set bits 2 3 6 and 7 to 0 3 When D A conversion is stopped the output state is high impedance 4 The output triggers are INTTM1 and INTTM2 for channel 0 and channel 1 respectively in the real time output mode 282 CHAPTER 15 D A CONVERTER 15 4 Operations of D A Converter 1 Select the operation mode for channel 0 using bit 4 DAM4 of the D A converter mode register DAM and select the operation mode for channel 1 using bit 5 DAM5 2 Set data corresponding to the analog voltage values output respectively to pins ANOO P130 and ANO1 P131 in D A conversion setting registers 0 and 1 DACSO and DACS1 3 It is possible to start A D conversion operation for channels 0 and 1 by setting bits 0 and 1 DACEO DACE1 of DAM 4 After D A conversion when in the normal mode analog voltages are output immediately to pins ANOO P130 and ANO1 P131 Whenin the realtime output mode analog voltages are output in sync with the output trigger 5 In the normal mode the analog voltage signals to be output are held until new data are set in DACSO and DACS1 In the realtime output mode new data are set in DACSO and DACS1 and then they are held until the next trigger is generated Caution Set DACEO and DACE1 after setting data in DACSO and DACS1 283 CHAPTER 15 D A CONVERTER 15 5 Cautions Related to D A Converter 1 Output impedance of D A conv
314. e start bit and full duplex operation is possible A dedicated UART baud rate generator is incorporated allowing communication over a wide range of baud rates In addition the baud rate can be defined by scaling the input clock to the ASCK pin MIDI standard baud rate 31 25 kbps can be used by employing the dedicated UART baud rate generator The 1 Register setting The UART mode is set by the serial operating mode register 2 CSIM2 asynchronous serial interface mode register ASIM asynchronous serial interface status register ASIS and baud rate generator control register BRGC a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H When the UART mode is selected 00H should be set in CSIM2 symbol D 6 5 4 3 2 1 Address AfterReset came ese o o o o o 448 CSCK Serial Operating Mode Selection 0 UART mode 1 3 wire serial I O mode CSIM22 First Bit Specification MSB LSB CSIE2 Operation Control in 3 wire Serial Mode 0 Operation stopped 1 Operation enabled Caution Ensure that bits 0 and 3 to 6 are set to 0 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 b Asynchronous serial interface mode register ASIM ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM to OOH Symb D 5 4 3 2 1 0 Address After Reset R W A
315. e test input flag KRIF can be set to 1 by detecting a falling edge The following operating mode can be specified in 8 bit units 1 Port mode These ports function as 8 bit input output ports They can be specified in 8 bit units for input or output ports by using the memory expansion mode register MM When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as low order address data bus pins ADO to AD7 in external memory expansion mode When pins are used as an address data bus the on chip pull up resistor is automatically disabled 3 2 6 P50 to P57 Port 5 These are 8 bit input output ports Besides serving as input output ports they function as an address bus Port 5 can drive LEDs directly The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input output ports with port mode register 5 PM5 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as high order address bus pins A8 to A15 in external memory expansion mode When pins are used as an address bus the on chip pull up resistor is automatically disabled 3 2 7 P60 to P67 Port 6 These are 8 bit input output ports Besides serving as input out
316. ector table area 0000H to 003FH 2 Comparator 528 The comparator always compares the correction address value set in correction address registers 0 and 1 CORADO CORAD 1 with the fetch address value When bit 1 CORENO or bit 3 COREN1 of the correction control register CORCN is 1 and the correction address matches the fetch address value the correction branch request signal BR F7FDH is generated from the ROM correction circuit CHAPTER 25 ROM CORRECTION 25 3 ROM Correction Control Registers The ROM correction is controlled with the correction control register CORCN 1 Correction control register CORCN This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1 The correction control register consists of correction enable flags CORENO COREN 1 and correction status flags CORSTO CORST1 The correction enable flags enable or disable the comparator match detection signal and correction status flags show the values are matched CORON is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CORCN to 00H Figure 25 3 Correction Control Register Format After Symbol 7 5 4 0 Address Reset R W CORCN COREN1 CORST1 CORENO CORSTO FF8AH 00H R W Note Correction address register 0 and fetch address match detection Not
317. ecution of the next command is completed The commands of this type interrupt request hold commands are shown below PSW byte MOV A PSW MOV PSW A e MOV1 PSW bit CY MOV1 CY PSW bit AND1 CY PSW bit OR1 CY PSW bit XOR1 CY PSW bit e SET1 PSW bit e CLR1 PSW bit RETB RETI PUSH PSW POP PSW BT PSW bit addr16 BF PSW bit addr16 BTCLR PSW bit addr16 El DI Manipulate instructions for IFOL IFOH IF1L MKOL MKOH MK1L PROL PROH PR1L INTMO INTM1 registers Caution The BRK command is not an interrupt request hold command like those above However in a software interrupt that is started by execution of the BRK command the IE flag is cleared to 0 Therefore even if a maskable interrupt is generated during execution of the BRK command the interrupt request is not received However a non maskable interrupt request is accepted The timing for holding an interrupt request is shown in Figure 21 17 CPU processing Figure 21 17 Interrupt Request Hold Instruction N Instruction M Save PSW and PC Interrupt service Jump to interrupt service program xx IF Remarks 1 Instruction N Instruction that holds interrupts requests 2 Instruction M Instructions other than instruction N 3 ThexxIF interrupt request operation does not receive the effect of the value of x xPR priority order level 501 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 5 Test Fun
318. ed clear bit 7 RE of ADTC to 0 Notes 1 Remark x Don t care PMXX Port Mode Register PXX Port Output Latch 404 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 b Automatic data transmit receive control register ADTC ADTC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADTC to 00H symbol gt D D Address AfterReset R W ADTC ARLD ERCE STRB BUSY1BUSYO FF69H 00H R Wrete 1 BUSY1 BUSYO Busy Input Control Not using busy input Busy input enable active high Busy input enable active low STRB Strobe Output Control 0 Strobe output disable 1 Strobe output enable Detection of termination of automatic transmission reception This bit is set to 0 upon suspension of automatic transmission reception or when ARLD 0 During automatic transmission reception This bit is set to 1 when data is written to SIO1 No error This bit is set to 0 when data is written to SIO1 Error occurred ERCE Error Check Control of Automatic Transmit Receive Function Error check disable Error check enable only when BUSY1 1 Receive Function 0 Single operating mode Function 0 Receive disable Notes 1 Bits 3 and 4 TRF and ERR are Read Only bits 2 The end of auto transmission should be determined by TRF not CSIIF1 interrupt request flag Caution When an external clock input is selected with bit 1 CS
319. eeeeeseaeeseaeeeaeeseaeeeeeseeeeeieeeeaeeeaeees 348 17 5 Serial Bus Interface Control Register Format cccccsceeeceeeeeeseeeeeeeeseaeeseeeeeaeeseaeeeaeesneeeeieeseeeeeeess 349 17 6 Interrupt Timing Specify Register Format esssseseeeeneeeeeneren nennen nennen 351 17 7 3 Wire 5 1 amp 4 amp eene nennen nnne neret nnne nnn nnne nnn nnne ener 356 17 8 RELT and GMBT Operations 3 ien Ua OLDER ER EO S e e Matres 356 17 9 Circuit of Switching in Transfer Bit Order sessssssssssseeeeeee enne nnne nnne 357 17 10 Serial Bus Configuration Example Using 2 Wire Serial I O Mode 358 17 11 2 Wire Serial Mode Timings sessesesseeeeenenenennenen nennen nennen nnne nnne nennen nes 361 17 12 BEET and GMDT Operations e aee e adito p e ceder cine Hee d dos 362 17 13 Example of Serial Bus Configuration Using 2 363 17 14 1 Bus Serial Data Transfer Timing c cccccccescesesceccseeeeseesesesseseesesecsesesaesessesessesessecessesaesesaeesatees 364 17 15 Start Condition o doni een US eitis uius 365 17 16 Address eiecerunt edd aba ee ee 365 17 17 Transfer Direction Specification i isisisi iensen esia 365 17 18 Acknowledge Sigrial odio ds de ER ei einen 366 17 19 Stop Condition 3 59e
320. eeeseaeeeeseeeeescaeeesceseesscureessneeesensees 103 5 9 Stack Pointer Format De ERU PROS ip Veg uit ee te ed 105 5 10 Data to Be Saved to Stack Memory ssssssssssssssseeeseeeeneeneee 105 5 11 Data to Be Reset from Stack Memory ssssssssssseseeeeenenenee nennen neret enne nnne nnns 105 5 12 General Register Configuration sesssssssesseeeeneneneee nennen neret nennt nennen 107 6 1 Port TyP S sedated edie ee eves et ee Ge ee eee le ee 125 6 2 P00 and P07 Block Diagram ett RI iei EAEE RESE OAE inani 131 6 3 PO to PO6 Block Diagram e co ain nls iii sae nd Fe epe UTE des 131 6 4 P10 to P17 Block Diagram assis ee Rp Aetna itt 132 6 5 P20 P21 P23 to P26 Block Diagram ssssssssseseeeeeneneneeeneeenneen nennt nennen nennen nnns 133 6 6 P22 and P27 Block Diagram oett dera 134 6 7 20 21 23 10 26 ree e ue sd 135 6 8 P22 and P27 Block Diagram nere reget ea dere evi ated 136 6 9 P30 to P37 BlockiDIagralmiz s t tees te qutt 137 6 10 P40 to P47 Block Diagrami iiia aet RU e te tet 138 6 11 Block Diagram of Falling Edge Detection Circuit ssseeeeenenneee 138 6 12 5010 57 ni oerte ERE ORNARE REIR 139 6 13 P60 to P63 Block Diagram e teet te uk e e
321. een received This signal is used between the sending side and receiving side devices for confirmation of correct data transfer In principle the receiving side device returns an acknowledge signal to the sending device each time it receives 8 bit data The only exception is when the receiving side is the master device and the 8 bit data is the last transfer data the master device outputs no acknowledge signal in this case The sending side that has tranferred 8 bit data waits for the acknowledge signal which will be sent from the receiving side If the sending side device receives the acknowledge signal which means a success ful data transfer it proceeds to the next processing If this signal is not sent back from the slave device this means that the data sent has not been received by the slave device and therefore the master device outputs a stop condition signal to terminate subsequent transmissions Figure 17 18 Acknowledge Signal SCL 1 2 3 4 5 6 7 8 9 om X 366 e Stop condition If the SDAO SDA1 pin level changes from low to high while the SCL pin is high this transition is defined as a stop condition signal The stop condition signal is output from the master to the slave device to terminate a serial transfer The stop condition signal is detected by hardware incorporated in the slave device Figure 17 19 Stop Condition SCL CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES f Wait signal WAIT
322. egister 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H 331 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES Symbol 4 3 2 1 0 Address After Reset R W R W Serial Interface Channel 0 Clock Selection Input Clock to SCKO pin from off chip 8 bit timer register 2 TM2 output Clock specified with bits O to 3 of timer clock select register 3 TCL3 Operation SIO SBO P25 SO0 SB1 P26 SCKO0 P27 25 P25 PM26 P26 PM27 P27 Start Bit Mode Pin Function Pin Function Pin Function 3 wire Serial I O mode see section 16 4 2 3 wire serial I O mode operation SBI mode see section 16 4 3 SBI mode operation Note 2 Note 2 SB1 N ch P25 CMOS open drain input output 2 wire serial input output Note 2 Note 2 mode SBO N ch SCKO N ch open drain P26 CMOS input output input output x x open drain input output Wake up Function ControlN Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the slave address register SVA data SBI mode Slave Address Comparison Result Flag Nete4 Slave address register SVA not equal to serial I O shift register 0 STOO data Slave address register SVA equal to serial I O shift
323. el 1 employs the following three modes Operation stop mode e 3 wire serial I O mode e 3 wire serial I O mode with automatic transmit receive function 1 2 3 Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption 3 wire serial mode MSB LSB first switchable This mode is used for 8 bit data transfer using three lines each for serial clock SCK1 serial output SO1 and serial input 511 The 3 wire serial I O mode enables simultaneous transmission reception and so decreases the data transfer processing time Since the start bit of 8 bit data to undergo serial transfer is switchable between MSB and LSB connection is enabled with either start bit device The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X XL 78K and 17K Series 3 wire serial I O mode with automatic transmit receive function MSB LSB first switchable This is the mode that an automatic transmit receive function is appended to the above mode 2 3 wire serial mode The automatic transmit receive function is used to transmit receive data with a maximum of 32 bytes This function enables the hardware to transmit receive data to from the OSD On Screen Display device and a device with built in display controller driver independently of the CPU thus the software load can be a
324. em 496 21 16 Multiple Interr pt Example 2 1 tet c b ce ee deii eon c oe Da ederet dust 499 21 17 Interrupt Request Hold e eee I ie etes 501 21 18 Basic Configuration of Test Function esssssssseeeeeneeeeeneee enne 502 21 19 Format of Interrupt Request Flag Register 1L emen 503 21 20 Format of Interrupt Mask Flag Register 11 503 21 21 Key Return Mode Register Format sesssssssseeeeneeeneene nenne nnne nnne nre nnne 504 22 1 Memory Map When Using External Device Expansion Function 506 22 2 Memory Expansion Mode Register Format sssseeeeeeeeeeen eene nennen 508 22 3 Memory Size Switching Register Format sse nennen 509 22 4 Instruction Fetch from External Memory sseseeeeneneen eene nennen nre 511 22 5 External Memory Read Timing 0 cccccceeceseeeeeeeceeeeeeceeeneeeeesseeeeaeeeseseeeneseeeeeseneeseseeeseseneesneesensseeeees 512 22 6 External Memory Write ridai ai aeii 513 22 7 External Memory Read Modify Write Timing ene 514 23 1 Oscillation Stabilization Time Select Register Format sseeeeeeneenen 516 23 2 HALT Mode Clear upon Interrupt Request Generation seeeeenee 518 23 3 HALT Mode Release by RESET Input cccccccccccccsesesscscsesesesecsesesesesecscseses
325. ement Square wave output One shot pulse output Interrupt request Test input Notes 1 Watch timer can perform both watch timer and interval timer functions at the same time 2 Watchdog timer can perform either the watchdog timer function or the interval timer function 3 When capture compare registers 00 01 CROO CRO01 are specified as compare registers 172 CHAPTER 8 16 TIMER EVENT COUNTER 8 2 16 Bit Timer Event Counter Functions The 16 bit timer event counter TMO has the following functions Interval timer PWM output Pulse width measurement External event counter Square wave output One shot pulse output PWM output and pulse width measurement can be used at the same time 1 Interval timer TMO generates interrupts request at the preset time interval Table 8 2 16 Bit Timer Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS 1 MCS 0 MCS 1 MCS 0 2 x TIOO input cycle 216 x TIOO input cycle TIOO input edge 2 x 1 fx 216 x 1 fx 1 fx 400 ns 13 1 ms 200 ns 2 x 1 fx 22 x 1 fx 216 x 1 fx 217 x 1 fx 1 fx 2 x 1 fx 400 ns 800 ns 13 1 ms 26 2 ms 200 ns 400 ns 22 x 1 fx 23 x 1 fx 217 x 1 fx 218 x 1 fx 2 x 1 fx 22 x 1 fx 800 ns 1 6 us 26 2 ms 52 4 ms 400 ns 800 ns 23 x 1 fx 24 x 1 fx 218 x 1 fx 219 x 1 fx 22 x 1 fx 23 x 1 fx 1 6 us
326. ement with Free Running Counter and Two Gapture Registers cerrada dene eee edd ere e Se o Ad Red Leda ea 197 8 23 Timing of Pulse Width Measurement Operation by Free Running Counter and Two Capture Registers with Rising Edge Specified ssssssseeeeeneeenenen eene 198 8 24 Control Register Settings for Pulse Width Measurement by Means of Restart 199 8 25 Timing of Pulse Width Measurement Operation by Means of Restart with Rising Edge Specifled tete eee i edle EE deed 199 8 26 Control Register Settings in External Event Counter Mode sese 200 8 27 External Event Counter Configuration Diagram essen eene 201 8 28 External Event Counter Operation Timings with Rising Edge Specified 201 8 29 Control Register Settings in Square Wave Output Mode sssseeeeneneenene 202 8 30 Square Wave Output Operation Timing sessssssessseeeeeeeenenennen nennen nennen nnne nnn 203 24 LIST OF FIGURES 3 8 Figure No Title Page 8 31 Control Register Settings for One Shot Pulse Output Operation Using Software Trigger 204 8 32 Timing of One Shot Pulse Output Operation Using Software 205 8 33 Control Register Settings for One Shot Pulse Output Operation Using External Trigger
327. ency fx or fx 2 fx Main system clock oscillation frequency 160 CHAPTER 7 CLOCK GENERATOR 7 4 System Clock Oscillator 7 4 1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator standard 5 0 MHz connected to the X1 and X2 pins External clocks can be input to the main system clock oscillator In this case input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin Figure 7 6 shows an external circuit of the main system clock oscillator Figure 7 6 External Circuit of Main System Clock Oscillator a Crystal and ceramic oscillation b External clock External lock Clock PD74HCUO4 Crystal or Ceramic Resonator Caution When an external clock is input do not execute the STOP instruction or set MCC bit 7 of the processor clock conirol register PCC to 1 If the STOP instruction is executed or MCC is set to 1 the main system clock will stop operating so that pin X2 can be pulled up to Vpp 161 CHAPTER 7 CLOCK GENERATOR 7 4 2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator standard 32 768 kHz connected to the XT1 and XT2 pins External clocks can be input to the main system clock oscillator In this case input a clock signal to the XT1 pin and an antiphase clock signal to the XT2 pin Figure 7 7 shows an external circuit of the subsystem clock oscillator Fig
328. eption in 8 bit units Bit wise data transmission reception is carried out in synchronization with the serial clock Shift operation of the serial I O shift register 0 SIOO is carried out at the falling edge of the serial clock SCKO The transmitted data is held in the SOO latch and is output from the SOO pin The received data input to the SIO pin is latched in SIOO at the rising edge of SCKO Upon termination of 8 bit transfer SIOO operation stops automatically and the interrupt request flag CSIIFO is set Figure 17 7 3 Wire Serial I O Mode Timings SCKO SIO 500 End of Transfer t Transfer Start at the Falling Edge of SCKO The SOO pin is a CMOS output pin and outputs current SOO latch statuses Thus the SOO pin output status can be manipulated by setting bit 0 RELT and bit 1 CMDT of serial bus interface control register SBIC However do not carry out this manipulation during serial transfer Control the SCKO pin output level in the output mode internal system clock mode by manipulating the P27 output latch refer to 17 4 7 SCKO SCL P27 pin output manipulation 3 Other signals Figure 17 8 shows RELT and CMDT operations Figure 17 8 RELT and CMDT Operations SOO latch RELT CMDT 356 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 4 MSB LSB switching as the start bit 5 The 3 wire serial I O mode enables to select transfer to start from MSB or LSB Figure 17 9 shows the
329. equest signal INTCSIO is generated only when the slave address output by the master coincides with the value of SVA and it can be learned by this interrupt request that the master requests for communication If the bit 5 SIC of the interrupt timing specify register SINT is setto 1 the wake up function cannot be used even if WUP is setto 1 an interrupt request signal is generated when bus release is detected To use the wake up function clear SIC to 0 Further errors can be detected using the SVA when sending data as a master or slave while in the SBI mode or the 2 wire serial I O mode RESET input makes SVA undefined CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 3 4 5 6 7 500 latch This latch holds the SIO SBO P25 and SOO SB1 P26 pin levels It can be directly controlled by software In the SBI mode this latch is set upon termination of the 8th serial clock Serial clock counter This counter counts the serial clocks to be output and input during transmission reception and to check whether 8 bit data has been transmitted received Serial clock control circuit This circuit controls serial clock supply to the serial I O shift register 0 5100 When the internal system clock is used the circuit also controls clock output to the SCKO P27 pin Interrupt request signal generator This circuit controls interrupt request signal generation It generates the interrupt request signal inthe following
330. er of waits when external memory expansion area is read from 554 CHAPTER 27 INSTRUCTION SET Instruction Group Mnemonic Operands A byte Operation lt AVbyte saddr byte saddr lt saddr Vbyte A r lt Avr lt saddr lt AV saddr A addr16 A lt AV addr16 A HL A HL byte lt AV HL byte A HL B lt AV HL A lt AV HL A HL A lt AV HL 8 bit operation A byte lt AN byte saddr byte saddr lt saddr v byte A r lt lt saddr lt A saddr A laddr 6 NIM W M NM NM M lt A addr16 A HL A lt A HL A HL byte lt AN HL byte A HL B A lt AX HL A HL C A lt AN HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access A byte A byte saddr byte saddr byte A r saddr A addr16 A HL A HL byte A HL B A HL C hm hw RIL DO RHR ojojoj AJo HR 0o L1 ojo o 2 0 2 2 0 AR 2 When an area except t
331. erial interface automatic transmit receive busy input pins d STB Serial interface automatic transmit receive strobe output pins Caution When this port is used as a serial interface pin the I O and output latches must be set according to the function the user requires For the setting refer to Figure 17 4 Serial Operating Mode Register 0 Format and Figure 18 3 Serial Operating Mode Register 1 Format CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 4 2 4 P30 to P37 Port 3 These are 8 bit input output ports Beside serving as input output ports they function as timer input output clock output and buzzer output The following operating modes can be specified bit wise 1 2 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 3 PM3 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL Control mode These ports function as timer input output clock output and buzzer output a TI1 and TI2 Pin for external count clock input to the 8 bit timer event counter b TOO to TO2 Timer output pins c PCL Clock output pin d BUZ Buzzer output pin 85 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 4 2 5 P40 to P47 Port 4 These are 8 bit input output ports Besides serving as input output ports they function as an address data bus The
332. ernal memory by setting the internal PROM size to less than 56 Kbytes by the memory size switching register IMS 97 CHAPTER 5 CPU ARCHITECTURE 5 1 1 Internal program memory space The uPD78056F and uPD78056FY are Mask ROM with a 49152 x 8 bit configuration the uPD78058F and UPD78058FY are Mask ROM with a 61440 x 8 bit configuration and the uPD78P058F and uPD78P058FY are PROM with a 61440 x 8 bit configuration They store program and table data etc Normally they are addressed by the program counter PC The areas shown below are allocated to the internal program memory space 1 Vector table area The 64 byte area 0000H to 00 is reserved as a vector table area The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area Of the 16 bit address low order 8 bits are stored at even addresses and high order 8 bits are stored at odd addresses Table 5 1 Vector Table Vector Table Address Interrupt Sources RESET input INTWDT INTPO INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSIO INTCSH INTSER INTSR INTCSI2 INTST INTTM3 INTTMOO INTTMO1 INTTM1 INTTM2 INTAD BRK 98 CHAPTER 5 CPU ARCHITECTURE 2 3 CALLT instruction table area The 64 byte area 0040H to 007FH can store the subroutine entry address of a 1 byte call instruction CALLT CALLF instruction entry area
333. erter Because the output impedance of the D A converter is high use of current flowing from the ANOn pins n 0 1 is prohibited If the input impedance of the load for the converter is low insert a buffer amplifier between the load and the ANOn pins In addition wiring from the ANOn pins to the buffer amplifier or the load should be as short as possible because of high output impedance If the wiring may be long design the ground pattern so as to be close to those lines or use some other expedient to achieve shorter wiring Figure 15 3 Use Example of Buffer Amplifier a Inverting amplifier C R2 UPD78058F 78058FY Ri ANOn The input impedance of the buffer amplifier is R b Voltage follower UPD78058F 78058FY ANOn i 4 I i The input impedance of the buffer amplifier is R1 If R1is not connected the output becomes undefined when RESET is low 2 Output voltage of D A converter Because the output voltage of the converter changes in steps use the D A converter output signals in general by connecting a low pass filter 3 AVner pin When only either one of the D A converter channels is used with AVner lt Vpp the pin that is not used as an analog output must be set as follows Set PM13 x bit of the port mode register 13 PM13 to 1 input mode and connect the pin to Vss Set PM13 x bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low
334. es using either as the start bit The 3 wire serial I O mode is useful for connection to peripheral I Os and display controllers etc which incorporate a conventional synchronous clocked serial interface such as the 75X XL Series 78K Series 17K Series etc Caution In the 3 wire serial I O mode of serial interface channel 2 only the output of the internal baud rate generator can be used for the operation clock It is not possible to use a clock that is input to pin SCK2 from the outside 433 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware Table 19 1 Serial Interface Channel 2 Configuration Register Transmit shift register TXS Receive shift register RXS Receive buffer register RXB Control register Serial operating mode register 2 CSIM2 Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Baud rate generator control register BRGC Port Mode Register 7 PM7 Note Note See Figure 6 15 P70 Block Diagram and Figure 6 16 P71 and P72 Block Diagram 434 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19 1 Serial Interface Channel 2 Block Diagram RxD SI2 P70 Internal Bus Asynchronous Asynchronous Serial Interface Serial Interface Status Register Mode Register Receive Buffer Direction RXB SIO2 Direction Control Ci
335. esacsesesecsesesesecseseseseceeaees 519 23 4 STOP Mode Release by Interrupt Request 521 23 5 Release by STOP Mode RESET Input cccccccscscsssscscscsesecscsesesesececsesesecaescseseseescsesesecsesesececseseeees 522 24 1 Block Diagram of Reset Function nennen nnne nre 523 24 2 Timing of Reset Input by RESET Input nnne nnne 524 24 3 Timing of Reset due to Watchdog Timer Overflow 524 24 4 Timing of Reset Input in STOP Mode by RESET Input tnter tnnt es 524 29 LIST OF FIGURES 8 8 Figure No Title Page 25 1 Block Diagram of ROM Correction sss nnne 527 25 2 Correction Address Registers 0 and 1 Format nennen nennen 528 25 3 Correction Control Register Format cccescceesceseeeeeeeeceeeeeeeeeeeecaeeeeeeesaeeseaeeseeeseaeesaeeseeseaeeseeeenaees 529 25 4 Storing Example to EEPROM When One Place Is 530 25 5 Connecting Example with EEPROM Using 2 Wire Serial l O Mode 530 25 6 Initialization Routine uiuit Gece ee pte eere epe dE Aue edet 531 25 7 ROM Correction Operation s ioc cecidi iene pac ce dr tete nin sb edv S e s 532 25 8 ROM Gorrection Example 2 2 2 eee t ede Ld ee eo ce ee ls 533 25 9 Program Transition Diagram When
336. even parity and odd parity a one bit odd number error can be detected With 0 parity and no parity an error cannot be detected i Even parity Transmission The number of bits with a value of 1 including the parity bit in the transmit data is controlled to be even The value of the parity bit is as follows Number of bits with a value of 1 in transmit data is odd 1 Number of bits with a value of 1 in transmit data is even 0 Reception The number of bits with a value of 1 including the parity bit in the receive data is counted If it is odd a parity error occurs ii Odd parity Transmission Conversely to the situation with even parity the number of bits with a value of 1 including the parity bit in the transmit data is controlled to be odd The value of the parity bit is as follows Number of bits with a value of 1 in transmit data is odd 0 Number of bits with a value of 1 in transmit data is even 1 Reception The number of bits with a value of 1 including the parity bit in the receive data is counted If it is even a parity error occurs iii 0 Parity When transmitting the parity bit is set to 0 irrespective of the transmit data When receiving the parity bit is not checked Therefore a parity error is not generated irrespective of whether the parity bit is set to 0 or 1 iv No parity A parity bit is not added to the transmit data At reception data i
337. f Sun Microsystems Inc Ethernet is a trademark of XEROX Corporation NEWS and NEWS OS are trademarks of SONY Corporation OSF Motif is a trademark of Open Software Foundation Inc TRON is an abbreviation of The Realtime Operating System Nucleus ITRON is an abbreviation of Industrial TRON The export of this product from Japan is regulated by the Japanese government To export this product may be prohibited without governmental license the need for which must be judged by the customer The export or re export of this product from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative The application circuits and their parameters are for reference only and are not intended for use in actual design ins Purchase of NEC I C components conveys a license under the Philips IPC Patent Rights to use these components in an l C system provided that the system conforms to the IC Standard Specification as defined by Philips The information in this document is subject to change without notice No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from
338. f a sufficient time for the voltage to increase to enable operation at maximum speeds the processor clock control register PCC and oscillation mode selection register OSMS are rewritten and the maximum speed operation is carried out Upon detection of a decrease of the voltage due to an interrupt request signal the main system clock is switched to the subsystem clock which must be in an oscillation stable state Upon detection of voltage reset due to an interrupt request signal 0 is set to the bit 7 MCC of PCC and oscillation of the main system clock is started After the lapse of time required for stabilization of oscillation the PCC and OSMS are rewritten and the maximum speed operation is resumed Caution When subsystem clock is being operated while main system clock was stopped if switching to the main system clock is made again be sure to switch after securing oscillation stable time by software 169 MEMO 170 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 1 Overview of the u PD78058F and 78058FY Subseries On Chip Timers This chapter describes the 16 bit timer event counter and begins with an overview of the on chip timers and related devices of the wPD78058F and 78058FY Subseries 1 16 bit timer event counter TMO The TMO can be used for an interval timer PWM output pulse widths measurement infrared ray remote control receive function external event counter square wave output of any frequency
339. f reset vector tables 0000H and 0001H are set Stack pointer SP Undefined Program status word PSW 02H RAM Data memory Undefined Nete 2 General register Undefined Note 2 Port Output latch Ports 0 to 3 Port 7 12 13 PO to P3 P7 P12 P13 00H Ports 4 to 6 P4 to P6 Undefined Port mode register PMO to PM3 PM5 to PM7 PM12 PM13 FFH Pull up resistor option register PUOH PUOL 00H Processor clock control register PCC 04H Oscillation mode selection register OSMS 00H Memory size switching register IMS Note 3 Internal expansion RAM size switching register IXS Nete 4 OAH Memory expansion mode register MM 10H Oscillation stabilization time select register OSTS 04H 16 bit timer event counter Timer register TMO 00H Capture compare register CROO CRO01 Undefined Clock selection register TCLO 00H Mode control register TMCO 00H Capture compare control register 0 CRCO 04H Output control register TOCO 00H 8 bit timer event counter Timer register TM1 TM2 00H Compare registers CR10 CR20 Undefined Clock select register TCL1 00H Mode control registers TMC1 00H Output control register TOC1 00H Notes 1 During reset input or oscillation stabilization time wait only the PC contents among the hard
340. f the 16 bit timer mode control register TMCO to 0 0 and 0 respectively and then stopping timer operation 486 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 6 External Interrupt Mode Register 1 Format After symbol 7 6 5 4 3 2 1 0 Address Reset INTM1 ES71 ES70 ES61 ES60 ES51 ES50 ES41 ES40 FFEDH 00H R W ES41 ES40 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges 487 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 5 Sampling clock select register SCS This register is used to set the valid edge clock sampling clock to be input to INTPO When remote controlled data reception is carried out using INTPO digital noise is removed with sampling clocks SCS is set with an 8 bit memory manipulation instruction RESET input sets SCS to 00H Figure 21 7 Sampling Clock Select Register Format After Symbol 7 6 0 Address Reset R W 5 4 3 2 1 soso o soso rm INTPO Sampling Clock Selection MCS 1 MCS 0 27 39 1 kHz 28 19 5 kHz 2 156 3 kHz f 29 78 1 kHz
341. fx 1 6 us 23 x 1 fx 1 6 us 24 x 1 fx 3 2 us 211 x 1 fx 409 6 us 212 x 1 fx 819 2 us 23 x 1 fx 1 6 us 24 x 1 fx 3 2 us 24 x 1 fx 3 2 us 25 x 1 fx 6 4 us 212 x 1 fx 819 2 us 213 x 1 fx 1 64 ms 24 x 1 fx 3 2 us 25 x 1 fx 6 4 us 25 x 1 fx 6 4 us 26 x 1 fx 12 8 us 213 x 1 fx 1 64 ms 214 x 1 fx 3 28 ms 25 x 1 fx 6 4 us 26 x 1 fx 12 8 us 26 x 1 fx 12 8 us 27 x 1 fx 25 6 us 214 x 1 fx 3 28 ms 215 x 1 fx 6 55 ms 26 x 1 fx 12 8 us 27 x 1 fx 25 6 us 2 x 1 fx 25 6 us 28 x 1 fx 51 2 us 215 x 1 fx 6 55 ms 216 x 1 fx 13 1 ms 2 x 1 fx 25 6 us 28 x 1 fx 51 2 us 28 x 1 fx 51 2 us 29 x 1 fx 102 4 us 216 x 1 fx 13 1 ms 217 x 1 fx 26 2 ms 28 x 1 fx 51 2 us 29 x 1 fx 102 4 us 29 x 1 fx 102 4 us 210 x 1 fx 204 8 us 217 x 1 fx 26 2 ms 218 x 1 fx 52 4 ms 29 x 1 fx 102 4 us 210 x 1 fx 204 8 us 211 x 1 fx 409 6 us Remarks 1 fx 3 Values in parentheses when operated at fx 5 0 MHz 212 x 1 fx 819 2 us 219 x 1 fx 104 9 ms 220 x 1 fx 209 7 ms Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 211 x 1 fx 409 6 us 212 x 1 fx 819 2 us 213 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 9 1 2 16 bit timer event counter
342. g the pull up resistor option register L PUOL Control mode Port 7 functions as serial interface data input output and clock input output a SI2 SO2 Serial interface serial data input output pins b SCK2 Serial interface serial clock input output pin c RxD TxD Asynchronous serial interface serial data input output pins d ASCK Asynchronous serial interface serial clock input output pin Caution When this port is used as a serial interface pin the I O and output latches must be set according to the function the user requires For the setting refer to Table 19 2 Serial Interface Channel 2 Operating Mode Settings of List 87 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 4 2 9 P120 to P127 Port 12 These are 8 bit input output ports Besides serving as input output ports they function as a real time output port The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 12 PM12 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register H PUOH 2 Control mode These ports function as real time output ports RTPO to RTP7 outputting data in synchronization with a trigger 4 2 10 P130 and P131 Port 13 These are 2 bit input output ports Besides serving as input output ports they are used for D A con
343. ge us os Interval Time Interval Time Interval Time Remark Interval time N 1 x t N 0001H to FFFFH 188 CHAPTER 8 16 TIMER EVENT COUNTER Table 8 6 16 Bit Timer Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS 1 MCS 0 2 x TIOO input cycle MCS 1 216 x TIOO MCS 0 input cycle MCS 1 TIOO input MCS 0 edge cycle 2 x 1 fx 400 ns Setting prohibited Setting prohibited 216 x 1 fx 13 1 ms Setting prohibited 1 fx 200 ns 22 x 1 fx 800 ns 2 x 1 fx 400 ns 216 x 1 fx 13 1 ms 217 x 1 fx 26 2 ms 1 fx 200 ns 2 x 1 fx 400 ns 23 x 1 fx 1 6 us 22 x 1 fx 800 ns 217 x 1 fx 26 2 ms 218 x 1 fx 52 4 ms 2 x 1 fx 400 ns 22 x 1 fx 800 ns 24 x 1 fx 3 2 us 23 x 1 fx 1 6 us 218 x 1 fx 52 4 ms 219 x 1 fx 104 9 ms 2 x 1 fx 800 ns 23 x 1 fx 1 6 us 1 1 2 x watch timer output cycle 216 x watch timer output cycle Watch timer output edge cycle Other than above Setting prohibited Remarks 1 fx 2 MCS 3 TCLO4 to TCLO6 Main system clock oscillation frequency Bit 0 of oscillation mode selection register OSMS Bits 4 to 6 of timer clock selection register 0 TCLO 4 Figures in parentheses apply to operation with fx 2 5 0 MHz 8 5 2 PWM output operations Setting th
344. generated from the main system clock is obtained with the following expression Baud rate Px 2 x k 16 fx Main system clock oscillation frequency Main system clock frequency fx or fx 2 n Value set in TPSO to TPS3 1 lt lt 11 k Value set in to MDL3 0 lt k lt 14 Table 19 5 Relationship Between Main System Clock and Baud Rate fx 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error MCS Oscillation mode selection register OSMS bit 0 453 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 ii Generation of baud rate transmit receive clock by means of external clock from ASCK pin The transmit receive clock is generated by scaling the clock input from the ASCK pin The baud rate generated from the clock input from the ASCK pin is obtained with the following expression fasck 4 Baud tate lt A fasck Frequency of clock input to ASCK pin k Value set in MDLO to MDL3 0 lt k lt 14 Table 19 6 Relationship Between ASCK Pin Input Frequency and Baud Rate When BRGC Is Set to 00H Baud Rate bps ASCK Pin Input Frequency 2 4 kHz 3 52 kHz 4 8 kHz 9 6 kHz 19 2 kHz 38 4 kHz 76 8 kHz 153 6 kHz 307 2 kHz 614 4 kHz 1000 0 kHz 1228 8 kHz
345. gister 395 18 6 3 Wire Serial I O Mode MINIS isn miin ara ee e a nennen aai a enne nnns 401 18 7 Circuit of Switching in Transfer Bit 402 18 8 Basic Transmission Reception Mode Operation Timings eseeeeneennnn 411 18 9 Basic Transmission Reception Mode Flowchart 412 18 10 Internal Buffer RAM Operation in 6 Byte Transmission Reception in Basic Transmit Receive MOd6 es betont uten nin 413 18 11 Basic Transmission Mode Operation Timings esessseeeeeenennenen enne 415 18 12 Basic Transmission Mode Flowchart eene eene nennen rennen 416 18 13 Internal Buffer RAM Operation in 6 Byte Transmission in Basic Transmit Mode 417 18 14 Repeat Transmission Mode Operation Timing cceecceesceeeeeeeeeeeeeeeeeeseeeeeaeeeeeeeceeseeeeeaeeseaeeennenaes 419 18 15 Repeat Transmission Mode Flowchart sese eene nennen 420 18 16 Internal Buffer RAM Operation in 6 Byte Transmission in Repeat Transmit Mode 421 18 17 Automatic Transmission Reception Suspension and Restart 423 18 18 System Configuration When the Busy Control Option Is
346. gure 3 1 List of Pin Input Output Circuit 2 2 Mask p as pullup d legion enable 1 9 IN OUT data output disable J gt N ch zr AVss output disable input enable analog output voltage medium breakdown input buffer feedback cut off data output disable j gt N ch AVss l 7o gt gt IN OUT medium breakdown input buffer 76 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 4 1 Pin Function List 4 1 1 Normal operating mode pins 1 Port pins 1 3 Input Output Port 0 POO P06 8 bit input output port po7Note 1 Function Input only After Reset Alternate Function INTPO TIOO Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software INTP1 TIO1 INTP6 Input only XT1 P10 to P17 Port 1 8 bit input output port Input output mode can be specified bit wise If used as input port an on chip pull up resistor can be used by softwareNote 2 ANIO to ANI7 Port 2 8 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software SIO SBO SDAO SOO SB1 SDA1 SCKO SCL When the 7 pin is used as an input port set the
347. gures 5 10 and 5 11 Caution Since RESET input makes SP contents indeterminate be sure to initialize the SP before instruction execution Figure 5 10 Data to Be Saved to Stack Memory PUSH rp Instruction CALL CALLF and CALLT Instruction SP 98 A SP SP 2 SP SP 2 SP 3 t SP 2 Register Pair Lower SP 2 PC7 PCO SP 2 SP 1 Register Pair Upper SP 1 PC15 PC8 SP 1 t SP gt SP SP gt Figure 5 11 Data to Be Reset from Stack Memory POP rp Instruction RET Instruction SP Register Pair Lower SP gt PC7 PCO SP gt SP 1 Register Pair Upper SP 1 PC15 PC8 SP 1 SP 2 SP 2 2 SP SP 3 Interrupt BRK Instruction PC7 PCO PC15 PC8 PSW RETI and RETB Instruction PC7 PCO PC15 PC8 PSW 105 CHAPTER 5 CPU ARCHITECTURE 5 2 2 General registers A general register is mapped at particular addresses FEEOH to FEFFH of the data memory It consists of 4 banks each bank consisting of eight 8 bit registers X A C B E D L and H Each register can also be used as an 8 bit register Two 8 bit registers can be used in pairs as a 16 bit register AX BC DE and HL They can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names RO to R7 and RPO to RP3 Register banks to be used for instruction execution are set with the CPU
348. h an 8 bit memory manip ulation instruction When TM1 and TM2 are used as 16 bit timer x 1 channel mode 16 bit timer register TMS is read with a 16 bit memory manipulation instruction RESET input sets TM1 and TM2 to 219 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 9 3 8 Bit Timer Event Counter Control Registers The following four types of registers are used to control the 8 bit timer event counter Timer clock select register 1 TCL1 8 bit timer mode control register 1 TMC1 8 bit timer output control register TOC1 Port mode register 3 PM3 1 Timer clock select register 1 TCL1 This register sets count clocks of 8 bit timer registers 1 and 2 TCL1 is set with an 8 bit memory manipulation instruction RESET input sets TCL1 to 00H 220 CHAPTER 9 8 BIT TIMER EVENT COUNTERS Symbol 7 6 TCL12 5 TCL11 Figure 9 4 Timer Clock Select Register 1 Format 4 3 2 1 0 TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL 11 TCL 10 TH falling edge Address FF41H After Reset 00H R W R W 8 Bit Timer Register 1 Count Clock Selection TI1 rising edge fxx 2 fx 2 2 5 MHz 1 25 MHz fxx 2 fx 2 1 25 MHz 625 kHz fxx 2 fx 2 625 kHz 313 kHz fxx 2 fx 24 313 kHz 156 kHz fxx 2 fx 2 156 kHz 78 1 kHz fxx 2 fx 2 78 1 kHz 39 1 kHz fxx 2 fx 2 39 1 kHz 19 5 kH
349. hannels 3 wire serial I O SBI 2 wire serial mode 1 channel e 9 wire serial I O mode Automatic transmit receive function 1 channel 3 wire serial I O UART mode 1 channel Timer 5 channels 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel 22 vectored interrupt sources Two test inputs Two types of on chip clock oscillators main system clock and subsystem clock Supply voltage Vpop 2 7 to 6 0 V 35 CHAPTER 1 OUTLINE uPD78058F SUBSERIES 1 2 Applications In the case of the uPD78056F 78058F and 78P058F Cellular phones pagers printers AV equipment air conditioners cameras PPC s fuzzy home appliances vending machines etc In the case of the uPD78058F A Controllers for car electronics gas detection and shut off devices various safety devices etc 1 3 Ordering Information Part Number Package Internal ROM uUPD78056F GC xxx 3B9 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm Mask ROM UPD78056F GC xxx 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Mask ROM LPD78058F GC xxx 3B9 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm Mask ROM LPD78058FGC xxx 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Mask ROM uPD78058FGK oocc BE9 80 pin plastic TQFP Fine pitch 12 x 12 mm Mask ROM 78058 3 9 80 plastic 14 x 14 mm Resin thickness
350. he STOP mode the main system clock oscillator stops and the whole system stops CPU current consumption can be considerably decreased Data memory low voltage hold down to Voo 1 8 V is possible Thus the STOP mode is effective to hold data memory contents with ultra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processing immediately upon interrupt request In any mode all the contents of the register flag and data memory just before standby mode setting are held The input output port output latch and output buffer statuses are also held Cautions 1 The STOP mode can be used only when the system operates with the main system clock subsystem clock oscillation cannot be stopped The HALT mode can be used with either the main system clock or the subsystem clock 2 When proceeding to the STOP mode be sure to stop the peripheral hardware operation and execute the STOP instruction 3 The following sequence is recommended for power consumption reduction of the A D converter when the standby function is used first clear bit 7 CS of A D converter mode register ADM to 0 to stop the A D conversion operation and then execute the HALT or STOP instruction 515 CHAPTER 23 STANDBY FUNCT
351. he internal high speed RAM area is accessed 3 Except r A Remarks 1 2 3 nis the number of waits when external memory expansion area is read from One instruction clock is the length of 1 clock cycle of the CPU clock fceu selected by the processor clock control register PCC This clock cycle applies to internal ROM program 555 CHAPTER 27 INSTRUCTION SET Instruction Group Mnemonic Operands Operation AX CY lt AX word AX CY lt AX word AX word AX lt AxX AX Quotient C Remainder AX C A n oa rer 1 saddr lt saddr 1 rer 1 lt saddr 1 Increment decrement rp lt rp 1 rp lt 1 A lt Ao Am 1 lt Am x 1 time CY lt lt Am x 1 time lt Ao A7 CY Am 1 lt Am x 1 time CY amp Ao Am 1 Am x 1 time Aa o lt HL s o HL z 4 lt As o HL s o lt HL z 4 Aa o lt HL z 4 HL s o As o HL z 4 lt HL s o mim mi nm B B RI DM RI DD Aa E Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract CY lt saddr bit CY lt sfr bit CY lt A bit CY lt PSW bit CY c HL bit saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY N CY saddr bit CY sfr bit CY A bit CY
352. hese ports function as 8 bit input output ports They can be specified bit wise as input or output ports with a port mode register 1 PM1 If used as input ports on chip pull up resistors can be used to these ports by defining the pull up resistor option register L PUOL Control mode These ports function as A D converter analog input pins ANIO to ANI7 The on chip pull up resistor is automatically disabled when the pins specified for analog input 3 2 3 P20 to P27 Port 2 These are 8 bit input output ports Besides serving as input output ports they function as data input output to from the serial interface clock input output automatic transmit receive busy input and strobe output functions The following operating modes can be specified bit wise 1 2 66 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 2 PM2 When they are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL Control mode These ports function as serial interface data input output clock input output automatic transmit receive busy input and strobe output functions 10 SH SOO SO1 Serial interface serial data input output pins b SCKO and SCK1 Serial interface serial clock input output pins c SBO and SB1 NEC standard serial bus interface input output pins CHAPTER 3 PIN
353. hold RESET input Reset processing Remark x Don t care 522 CHAPTER 24 RESET FUNCTION 24 1 Reset Function The following two operations are available to generate the reset signal 1 External reset input with RESET pin 2 Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences In both cases program execution starts at the address at 0000H and 0001H by RESET input When a low level is input to the RESET pin or the watchdog timer overflows a reset is applied and each hardware is set to the status as shown in Table 24 1 Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear When a high level is input to the RESET input the reset is cleared and program execution starts after the lapse of oscillation stabilization time 2 fx The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time 2 7 fx see Figure 24 2 to 24 4 Cautions 1 For an external reset input a low level for 10 us or more to the RESET pin 2 During reset input main system clock oscillation remains stopped but subsystem clock oscillation continues When the STOP mode is cleared by reset the STOP mode contents are held during reset input However the port pin becomes high impedance Figure 24 1 Block Diagra
354. hort direct addressing Operand format enter sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PMO A when selecting PMO FF20H as sfr Operation code 1111011 0 OP code 0 0 1 0 0 O 0 20H sfr offset 0 8 1 Illustration OP code sfr offset SFR 15 7 0 1 1177777 f 121 CHAPTER 5 CPU ARCHITECTURE 5 4 6 Register indirect addressing Function This addressing addresses the memory with the contents of a register pair specified as an operand The register pair to be accessed is specified by the register bank select flags RBSO and RBS1 and register pair specify code in an instruction code This addressing can be carried out for all the memory spaces Operand format ente m Description example MOV A DE when selecting DE as register pair Operation code 10000101 Illustration Memory address specified by register pair DE Contents of addressed memory are transferred 7 122 CHAPTER 5 CPU ARCHITECTURE 5 4 7 Based addressing Function This addressing addresses the memory by adding 8 bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition The HL register pair to be accessed is in the register bank specified by the register bank select flags RBSO and RBS1
355. ial clock is output It is necessary to change the SCL pin to high in order to output a start condition signal To set pin SCL to high level set bit 3 CLC of the interrupt timing specification register SINT to 1 After setting CLC clear CLC to 0 and return the SCL pin to low If CLC remains 1 no serial clock is output To output the start condition or stop condition from the master set CLC to 1 then make sure that bit 6 CLD of SINT is 1 This procedure must be followed because there is a possibility that the slave has set SCL to low level wait status Figure 17 24 Start Condition Output SCL SDAO SDA1 CLC CMDT CLD CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 2 Slave wait release slave transmission Slave wait status is released by WREL flag bit 2 of interrupt timing specify register SINT setting or execution of an serial I O shift register 0 SIOO write instruction If the slave sends data the wait is immediately released by execution of an SIOO write instruction and the clock rises without the start transmission bit being output in the data line Therefore as shown in Figure 17 25 data should be transmitted by manipulating the P27 output latch through the program At this time control the low level width a in Figure 17 25 of the first serial clock at the timing used for setting the P27 output latch to 1 after execution of an SIOO write instruction In addition if the ackn
356. ial interface Other than Operable Operable when automatic external SCK is used transmit receive function Automatic Operation stops transmit receive function External interrupt INTPO INTPO is operable when clock supplied for peripheral hardware is selected Operation stops as sampling clock bo 25 6 29 fxx 27 INTP1 to INTP6 Operable Bus line for ADO to AD7 High impedance external to A15 Status before HALT mode setting is held expansion ASTB Low level WR RD High level WAIT High impedance Notes 1 Including when external clock is not supplied 2 Including when external clock is supplied 517 CHAPTER 23 STANDBY FUNCTION 2 HALT mode clear The HALT mode can be cleared with the following four types of sources a Clear upon unmasked interrupt request The HALT mode is cleared when an unmasked interrupt request is generated If interrupt acknowledge is enabled vectored interrupt servicing is performed If disabled the next address instruction is executed Figure 23 2 HALT Mode Clear upon Interrupt Request Generation HALT Instruction Interrupt Request Standby Release Signal Operating Mode HALT Mode Wait Operating Mode Oscillation Clock Remarks 1 line indicates the case when the interrupt request which has cleared the standby status is acknowledged 2 Wait time will be as follows When
357. ic transmit receive function writes reads data to from the internal buffer RAM after 1 byte transmission reception an interval is inserted till the next transmission reception As the internal buffer RAM write read is performed at the same time as CPU processing the maximum interval is dependent upon CPU processing and the value of the automatic data transmit receive interval specify register ADTI see 5 Automatic transmit receive interval time 2 When TRF is cleared the SO1 pin becomes low level CSIIF1 Interrupt request flag TRF Bit 3 of the auto data send and receive control register ADTC 411 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 9 Basic Transmission Reception Mode Flowchart Write transmit data in internal buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Software Execution Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from internal buffer RAM to SIO1 Transmission reception operation Decrement pointer value Hardware Execution Write receive data from SIO1 to internal buffer RAM Pointer value 0 Software Execution ADTP Automatic data transmit receive address pointer ADTI Automatic data transmit receive interval specify register SIO1 Serial I O shift register 1 TRF Bit 3 of automatic da
358. ics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r 1 Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore 1130 Tel 65 253 8311 Fax 65 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 719 2377 Fax 02 719 5951 NEC do Brasil S A Cumbica Guarulhos SP Brasil Tel 011 6465 6810 Fax 011 6465 6829 J98 2 MAJOR REVISIONS IN THIS EDITION Page Major Revision from Previous Edition Throughout The following products have already been developed uPD78056FGC xxx 8BT 78058FGC xxx 8BT 78P058FGC 8BT 78056FYGC xxx 8BT 78058FYGC xxx 8BT P133 to The block diagrams of the following ports were changed P137 P143 F
359. ie 142 2 10 2 2 uu ees it NE E SE bete ts 144 6 2 11 145 6 3 Port Function Control Registers ccccccsssceeseeeeeeseeeeseeeeeeeneeesnaeseeeeeeescaeseneeeeeseesenseaenes 146 6 4 Port Function 152 6 4 1 Writing to input outp t DOrL ee ee li D dene ra cer 152 6 4 2 Reading from input output nennen mnes 152 6 4 3 Operations on input output port esssssesesseeeeeeeeeenneeen nennen nenne nennen nennen nnne nenne 153 6 5 Selection of Mask Option 153 CHAPTER 7 CLOCK GENERATOR 155 7 1 Clock Generator 155 7 2 Clock Generator Configuration esee nennen nnnm nnne nnne nnns nnn 155 7 3 Clock Generator Control 157 7 4 System Clock Oscillator seen nenne nns annt nnn 161 T41 Mainisystem clock oscillator iieri eet e etie Ce eti cepe Hg e irat ups 161 17 74 2 Subsystem clock oscillator edd aceites ets 162 TAO Scaler uut nade a LR a a in peel eta
360. ignal is output in data accesses and instruction fetches from external memory During internal memory access the read strobe signal is not output maintains high level WR pin Alternate function P65 Write strobe signal output pin The write strobe signal is output in data access to external memory During internal memory access the write strobe signal is not output maintains high level WAIT pin Alternate function P66 External wait signal input pin When the external wait is not used the WAIT pin can be used as an input output port During internal memory access the external wait signal is ignored ASTB pin Alternate function P67 Address strobe signal output pin Timing signal is output without regard to the data accesses and instruction fetches from external memory The ASTB signal is also output when the internal memory is accessed ADO to AD7 A8 to A15 pins Alternate function P40 to P47 P50 to P57 Address data signal output pin Valid signal is output or input during data accesses and instruction fetches from external memory These signals change when the internal memory is accessed output values are undefined Timing charts are shown in Figure 22 4 to 22 7 510 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ASTB RD ADO to AD7 A8 to A15 ASTB RD ADO to AD7 A8 to A15 Internal Wait Signal 1 clock wait ASTB RD ADO to AD7 A8 to A15 WAIT Figure 22 4 Instruction Fetch from E
361. igures 6 5 and 6 7 P20 P21 P23 to P26 Block Diagram Figures 6 6 and 6 8 P22 and P27 Block Diagram Figure 6 9 P30 to P37 Block Diagram Figure 6 16 P71 and P72 Block Diagram P159 Table 7 2 Relationship between CPU Clock and Minimum Instruction Execution Time was added P230 P235 Figures 9 10 and 9 13 Square Wave Output Operation Timing were added P295 Note related to operation controls when using the SBI mode of serial interface channel 0 was added P297 Note related to BSYE in Figure 16 5 Serial Bus Interface Control Register Format was changed P308 Cautions were added to 16 4 3 2 a Bus release signal REL and b Command signal CMD P435 P436 CSCK was deleted from Figure 19 1 Serial Interface Channel 2 Block Diagram and Figure 19 2 Baud Rate Generator Block Diagram P438 Figure 19 3 Serial Operating Mode Register 2 Format was changed P440 Table 19 2 Serial Interface Channel 2 Operating Mode Settings 2 3 wire serial I O mode was changed P459 Figure 19 10 Receive Error Timing was changed P468 19 4 4 Restrictions on using UART mode was added P565 APPENDIX A DIFFERENCES AMONG 4PD78054 78058F AND 780058 SUBSERIES was added P567 APPENDIX B DEVELOPMENT TOOLS Overall revision Contents were adapted to correspond to in circuit emulators IE 78K0 NS and IE 78001 R A APPENDIX C EMBEDDED SOFTWARE Overall revision Fuzzy inference development support system was deleted APPENDIX E REVISION
362. iie ER eh a a 141 6 14 P64 to P67 Block Diagram 141 6 15 PZ0 Block Diagram e ean ee e eb eee ee 142 6 16 Pil and P72 Block Dlagtatm crt cd tete re ue dea xp ue 143 6 17 12010 P127 Block Diagram mide cR d dre caede dace eaa 144 6 18 P130 and P131 Block Diagram cat dase eid rect 145 6 19 Port Mode Register Format ir ee RR RE LEAST 148 6 20 Pull Up Resistor Option Register Format ssssseeeeneeeeeeneneee nennen rennen nnne 149 6 21 Memory Expansion Mode Register Format eterne tenent 150 6 22 Key Return Mode Register Format cccceescceseseeeeeeneeeeseeeeseneeeeneneeeesaaeesesaeeeseaeeeesaaeeesnaeeeseneeeneaaes 151 7 1 Block Diagram of Clock Generator ssssssseeeeeeeeeeneneen nennen neret nennen 156 7 2 Subsystem Clock Feedback Resistor sessssssssssssseeeeeee enne nnne nnne nni 157 7 8 Processor Clock Control Register Format ssssssssseseeeeeenenneennen nennen nennen 158 23 LIST OF FIGURES 2 8 Figure No Title Page 7 4 Oscillation Mode Selection Register Format cccesceseceeeseeeeeeeeneeeeaeeeeeeeeaeeseeeeeaeeseaeeseeseaeeeeeeeeaees 159 7 5 Main System Clock Waveform due to Writing to OSMS ssssseneeeeeeneen 160 7 6 External Circuit of Main
363. ing transmitted is fetched into the destination device that is serial I O shift register 0 SIOO Thus transmit error can be detected in the following way a Method of comparing 100 data before transmission to that after transmission In this case if two data differ from each other a transmit error is judged to have occurred b Method of using the slave address register SVA Transmit data is set to both SIOO and SVA and is transmitted After termination of transmission COI bit match signal coming from the address comparator of the serial operating mode register 0 CSIMO is tested If 1 normal transmission is judged to have been carried out If 0 a transmit error is judged to have occurred 335 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 16 4 5 SCK0 P27 pin output manipulation Because the SCKO P27 pin incorporates an output latch static output is also possible by software in addition to normal serial clock output P27 output latch manipulation enables any value of SCKO to be set by software SI0 SBO and SOO SB1 pin to be controlled with the RELT and CMDT bits of serial bus interface control register SBIC SCKO P27 pin output manipulating procedure is described below 1 Set the serial operating mode register 0 CSIMO pin enabled for serial operation in the output mode SCKO 1 with serial transfer suspended lt 2 gt Manipulate the P27 output latch with a bit manipulatio
364. input sets Symbol Address After Reset R W D 4 ano eel R W CSIMO1 CSIMOO Serial Interface Channel 0 Clock Selection Input clock from off chip to SCL pin 8 bit timer register 2 TM2 outputNote 2 wire seria Operation Mode Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 SIO SBO SDAO P25 Pin Function S00 SB1 SDA1 P26 Pin Function SCKO SCL P27 Pin Function x Note 3 2 wire serial I O or 12C bus mode P25 CMOS 1 0 SB1 SDA1 N ch open drain I O SCKO SCL N ch open drain I O x Note 3 0 Note 3 2 wire serial I O or SBO SDAO N ch open P26 CMOS 1 0 SCKO SCL N ch open 12C bus mode drain drain Wake up Function ControlNote 4 Interrupt request signal generation with each serial transfer in any mode In I2C bus mode interrupt request signal is generated when the address data received after start condition detection when CMDD 1 matches data in slave address SVA register Slave address register SVA not equal to data in serial I O shift register 0 SIOO Slave address register SVA equal to data in serial I O shift register 0 SIOO R W CSIEO Serial Interface Channel 0 Operation Control Stops operation 1 Enables operation Bit 6 is a read only bit 2 In the 12C bus mode the clock frequency is 1 16 of the clock freq
365. interface channel 0 transfer R SCKO SCL Pin Level ete 0 Low level 1 High level Notes 1 When using wake up function in the I2C mode set SIC to 1 2 When CSIEO 0 CLD becomes 0 Remark SVA Slave address register CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 352 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 17 4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0 Operation stop mode e 3 wire serial I O mode 2 wire serial I O mode 12 Inter IC bus mode 17 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power consumption can be reduced The serial I O shift register 0 SIOO does not carry out shift operation either and thus it can be used as ordinary 8 bit register In the operation stop mode the P25 SIO SBO SDAO P26 SO0 SB1 SDA1 and P27 SCKO SCL pins can be used as general input output ports 1 Register setting The operation stop mode is set with the serial operating mode register 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Symbol D 4 Address After Reset R W ce ee mm mom R W CSIEO Serial Interface Channel 0 Operation Control 0 Operation stopped 1 Operation enabled 353 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD780
366. ions marked with in Figure 12 1 Figure 12 1 Remote Controlled Output Application Example PCL P35 Pin Output 253 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12 2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware Table 12 1 Clock Output Control Circuit Configuration Timer clock select register 0 TCLO Control register Port mode register Figure 12 2 Clock Output Control Circuit Block Diagram fxx 24 8 5 Synchronizing fxx 2 Circuit PCL P35 25 be fxr 4 l CLOE TCLOS TCLO2 TCLO1 TCLOO P35 PM35 Output Latch Timer Clock Select Register 0 Port Mode Register 3 Y Y Internal Bus 12 3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function Timer clock select register 0 TCLO Port mode register 3 PM3 1 Timer clock select register 0 TCLO This register sets PCL output clock TCLO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TCLO to 00H Remark Besides setting PCL output clock TCLO sets the 16 bit timer register count clock 254 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT D 6 Symbol TCL02 TCLO1 Figure 12 3 Timer Clock Select Register 0 Format 5 4 3 2 Address R W Reset FF40H 00H R W fx
367. ire serial I O mode MSB first This mode is used for 8 bit data transfer using two lines of serial clock SCKO and serial data bus SBO or SB1 This mode enables to cope with any one of the possible data transfer formats by controlling the SCKO level and the SBO or SB1 output level Thus the handshake line previously necessary for connection of two or more devices can be removed resulting in the increased number of available input output ports CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 4 12C Inter IC bus mode MSB first This mode is used for 8 bit data transfer with two or more devices using two lines of serial clock SCL and serial data bus SDAO or SDA1 This mode is in compliance with the 12C bus format In this mode the transmitter outputs three kinds of data onto the serial data bus start condition data and stop condition to be actually sent or received The receiver automatically distinguishes the received data into start condition data or stop condition by hardware Figure 17 1 Serial Bus Configuration Example Using 2 Bus AVop AVop Master CPU Slave CPU1 SCL SCL SDAO SDA1 t SDAO SDA1 Slave CPU2 SCL SDAO SDA1 Slave CPUn SCL SDAO SDA1 339 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 17 2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware Table
368. is used with optional device file DF78054 Part Number uSxxxxSM78K0 Remark of the part number differs depending the host machine and OS used Refer to the table below USxxxxSM78KO Host Machine Supply Media PC 9800 Series Windows Japanese s 3 5 inch 2HD FD compatibles IBM PC AT and Windows Japanese N 3 5 inch 2HC FD Windows English Nete Note Does not support WindowsNT 574 APPENDIX B DEVELOPMENT TOOLS B 3 2 Software 2 2 ID78K0 NSNete This is a control program that is used to debug the 78K 0 Series Integrated debugger It uses Windows on a personal computer and OSF Motif on EWS as a Supports the in circuit graphical user interface and hasthe appearance and operability conforming emulator IE 78K0 NS to these interfaces Moreover debugging functions supporting C language are reinforced and the trace result can be displayed in C language level by using a window integrating function that associates the source program ID78KO disassemble display and memory display with the trace result In addition Integrated debugger it can enhance the debugging efficiency of a program using a real time OS Supports the in circuit by incorporating function expansion modules such as a task debugger and emulator IE 78001 R A system performance analyzer This debugger is used in combination with an optional device file DF 78054 Part number wSxxxxID78KO NS uSxxxxID78KO
369. ission reception When automatic transmission reception is terminated TRF bit 3 of ADTC is cleared to O 410 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 3 Communication operation a SCK1 501 Sit CSIIF1 TRF Basic transmission reception mode This transmission reception mode is the same as the 3 wire serial I O mode in which specified number of data are transmitted received in 8 bit units Serial transmission is started by writing the desired data to serial I O shift register 1 SIO1 when bit 7 CSIE1 of serial operation mode register 1 CSIM1 is set at 1 When the final byte has been sent an interrupt request flag CSIIF1 is set However judge the termination of auto send and receive not by CSIIF1 interrupt request flag but by bit 3 TRF of the auto data send and receive control register ADTC If busy control and strobe control are not executed the P23 STB and P24 BUSY pins can be used as normal input output ports Figure 18 8 shows the basic transmission reception mode operation timings and Figure 18 9 shows the operation flowchart Figure 18 10 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted or received Figure 18 8 Basic Transmission Reception Mode Operation Timings Interval lt gt 5e CD Cautions 1 Because in the basic transmission reception mode the automat
370. ission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from internal buffer RAM to SIO1 Decrement walle Transmission operation Hardware Execution Pointer value 0 Software Execution ADTP Automatic data transmit receive address pointer ADTI Automatic data transmit receive interval specify register 5101 Serial I O shift register 1 TRF Bit 3 of automatic data transmit receive control register ADTC 416 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6 byte transmission ARLD 0 RE 0 in basic transmit mode internal buffer RAM operates as follows i Before transmission See Figure 18 13 a After any data has been written to serial I O shift register 1 SIO1 start trigger this data is not transferred transmit data 1 T1 is transferred from the internal buffer RAM to SIO1 When transmission of the first byte is completed automatic data transmit receive address pointer ADTP is decremented Then transmit data 2 T2 is transferred from the internal buffer RAM to SIO1 ii 4th byte transmission point See Figure 18 13 b Transmission of the third byte is completed and transmit data 4 T4 is transferred from the internal buffer RAM to SIO1 When transmission of the fourth byte is completed ADTP is decremented iii Completion of transmission See Figure 18 13 c When transmission of the sixth byte is completed the interr
371. ister WDTM is set to 0 A count clock interval time can be selected by the bits 0 through 2 TCL20 through TCL22 of the timer clock select register 2 TCL2 By setting the bit 7 RUN of WDTM to 1 the watchdog timer starts operating as an interval timer When the watchdog timer operated as interval timer the interrupt mask flag TMMK4 and priority specify flag TMPRA are validated and the maskable interrupt request INTWDT can be generated Among maskable interrupt requests the INTWDT default has the highest priority The interval timer continues operating in the HALT mode but it stops in STOP mode Thus set bit 7 RUN of WDTM to 1 before the STOP mode is set clear the interval timer and then execute the STOP instruction Cautions 1 Once bit4 WDTM4 of WDTM is set to 1 with the watchdog timer mode selected the interval timer mode is not set unless RESET input is applied 2 Theinterval time just after setting with WDTM may be shorter than the set time by a maximum of 0 5 3 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 11 5 Interval Timer Interval Time 211 x 1 fxx 21 x 1 fx 410 us 212 x 1 fx 819 us 212 x 1 fxx 212 x 1 fx 819 us 213 x 1 fx 1 64 ms 213 x 1 fxx 213 x 1 fx 1 64 ms 214 x 1 fx 3 28 ms 214 x 1 fxx 214 x 1 fx 3 28 ms 215 x 1 fx 6 55 ms 215 x 1 fxx 215 x 1 fx 216 x 1 fx 13 1 ms 216 x 1 fxx
372. ister controls the operation of the capture compare registers 00 01 CROO CRO1 CRCO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CRCO value to 04H Figure 8 5 Capture Compare Control Register 0 Format Symbol 7 6 Address After Reset R W 5 4 3 2 1 0 owes nm Operates as compare register Operates as capture register Operates as compare register Operates as capture register Cautions 1 The timer operation must be stopped before setting CRCO 2 When clear amp start mode on a match between TMO and CROO is selected with the 16 bit timer mode control register TMCO CROO should not be specified as a capture register 4 16 bit timer output control register TOCO This register controls the operation of the 16 bit timer event counter output control circuit It sets R S type flip flop LVO setting resetting the active level in PWM mode inversion enabling disabling in modes other than PWM mode 16 bit timer event counter timer output enabling disabling one shot pulse output operation enabling disabling and output trigger for a one shop pulse by software TOCO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TOCO value to 00H 182 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 6 16 Bit Timer Output Control Register Format Symbol 7 Address After Reset R W 4 1 Q9 TOCO 0 osPT OSPE FF4EH
373. ister is specified one of the eight registers is specified with 3 bits in the operation code Operand format dente r X A C D L H rp AX BC DE HL r and rp can be described with function names X A C B E D L H AX BC DE and HL as well as absolute names RO to R7 and RPO to RP3 Description example MOV A C when selecting C register as r Operation code 01100010 Register specify code INCW DE when selecting DE register pair as rp Operation code 10000100 Register specify code 117 CHAPTER 5 CPU ARCHITECTURE 5 4 3 Direct addressing Function This addressing directly addresses the memory indicated by the immediate data in an instruction word Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A OFEOOH when setting addr16 to FE00H Operation code 1000111 0 OP code 0000000 0 OOH 11 11 11 1 0 FEH Illustration OP code saddr16 low saddr16 high Memory 118 CHAPTER 5 CPU ARCHITECTURE 5 4 4 Short direct addressing Function The memory to be manipulated in the fixed space is directly addressed with 8 bit data in an instruction word The fixed space to which this address is applied is a 256 byte space of addresses FE20H through FF1FH An internal RAM and a special function register SFR are mapped at FE20H to FEFFH and FFOOH to
374. it memory manipulation instruction for the setting RESET input sets these registers to FFH Figure 21 3 Interrupt Mask Flag Register Format Smo OD G Address 09 09 0 06 Q 6 5 4 3 o OO 0 fame t t 1 JADMK MMG MK FRESH Interrupt Servicing Control Interrupt servicing enabled Interrupt servicing disabled Note WTMK controls enable disable of cancellation of the standby mode It does not control the interrupt function Cautions 1 If TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1 MKO value becomes undefined 2 Because port 0 has an alternate function as the external interrupt request input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore 1 should be set in the interrupt mask flag before using the output mode 3 Set always 1 in MK1L bits 3 to 6 484 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 3 Priority specify flag registers PROL PROH and PR1L The priority specify flag is used to set the corresponding maskable interrupt priority orders PROL PROH and PR1L are set with a 1 bit or 8 bit memory manipulation instruction If PROL and PROH are used as a 16 bit register PRO use a 16 bit memory manipulation instruction for the setting RESET input sets these registers to FFH Figure 21 4 Priority Specify Flag Register F
375. ith a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC1 to OOH Figure 9 5 8 Bit Timer Mode Control Register Format Symbol 7 6 Address After Reset R W 5 4 3 2 me o o o o rez re rw 8 Bit Timer Register 1 Operation Control Operation stop TM1 clear to 0 Operation enable Operation stop TM2 clear to 0 TCE2 8 Bit Timer Register 2 Operation Control 0 1 Operation enable 8 Bit timer register x 2 channel mode TM1 TM2 2 Operating Mode Selection 0 1 16 Bit timer register x 1 channel mode TMS Cautions 1 Before switching the operation mode stop the timer operation 2 When 8 bit timer registers 1 and 2 are used as a 16 bit timer register operation enable stop should be set with TCE1 222 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 3 8 bit timer output control register TOC1 This register controls operation of 8 bit timer event counter output control circuits 1 and 2 It sets resets the R S flip flops LV1 and LV2 and enables disables inversion and 8 bit timer output of 8 bit timer registers 1 and 2 TOC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TOC1 to 00H Symbol TOC1 Figure 9 6 8 Bit Timer 2 Control Register Format 5 0 1 LVS2 LVR2 LVS1 LVR1 11 TOE1 Address After Reset R W FFAFH 00H R W 8 Bit Timer Event Counter 1 Outptut Control Output disable
376. iting data to the shift register Transfer start Serial transfer is started by setting transfer data to the transmission shift register TXS SIO2 when the following two conditions are satisfied Serial interface channel 2 operation control bit CSIE2 1 Internal serial clock is stopped or SCK 2 is a high level after 8 bit serial transfer Caution If CSIE2 is set to 1 after data write to TXS SIO2 transfer does not start Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag SRIF is set 467 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 4 4 Restrictions on using UART mode In the UART mode a receive completion interrupt request INTSR is generated after a certain period of time following the generation and clearing of the receive error interrupt request INTSER Thereby the phenomenon shown below may occur Details If the bit 1 ISRM of the asynchronous serial interface mode register ASIM is set to 1 the setting is made such that receive completion interrupt request INTSR will not be generated upon the generation of a receive error However in the receive error interrupt request INTSER servicing if the receive buffer register RXB is read within a certain timing in Figure 19 14 internal error flag is cleared to 0 Therefore no receive error is judged to have been generated and INTSR which is not supposed to be generated will be generated Figure 19
377. ive error is generated while bit 1 ISRM of the asynchronous serial interface mode register ASIM is set to 1 INTSR is not generated Cautions 1 The contents of the asynchronous serial interface status register ASIS are reset 0 by reading the receive buffer register RXB or receiving the next data To ascertain the error contents ASIS must be read before reading RXB 2 The receive buffer register must be read even if a receive error is generated If RXB is not read an overrun error will be generated when the next data is received and the receive error state will continue indefinitely 459 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 3 UART mode cautions a If bit 7 TXE of the asynchronous serial interface mode register ASIM is cleared to 0 during transmission and sending operation is halt be sure to set the transmit shift register TXS to FFH then set TXE to 1 before executing the next transmission b Ifbit6 RXE of ASIM is cleared 0 during reception and receiving operation is halt the status of the receive buffer register RXB and whether or not a receive completion interrupt INTSR is generated differ depending on the timing The timing is shown in Figure 19 11 Figure 19 11 Receive Buffer Register RXB Status and Receive Completion Interrupt Request INTSR Generation When Receiving Is Terminated PM om RXB 1 1 INTSR 1 1 l 1 1
378. ive operation noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock At this time if the strobe control option is not used this bit slippage will have an effect on sending of the next byte In such a case the busy control option can be used on the master device side and by checking the busy signal during sending bit slippage can be detected Bit slippage detection through the busy signal is accomplished as follows The slave side outputs a busy signal after the serial clock rises on the 8th cycle of data sending or receiving at this time if application of the wait state by the busy signal is not desired the busy signal is made inactive within 2 clock cycles The master device side samples the busy signal in sync with the fall of the serial clock s front side If no bit slippage is occurring the busy signal will be inactive in sampling for 8 clock cycles If the busy signal is found to be active in sampling it is regarded as an occurrence of bit slippage error processing is executed bit 4 ERR of the auto data send and receive control register ADTC is set at 1 The operation timing of the bit slippage detection function through the busy signal is shown in Figure 18 22 Figure 18 22 Operation Timing of the Bit Slippage Detection Function Through the Busy Signal When BUSYO 1 SCK1 Master Side SO1 Slave Side 7 _ 7 5
379. ization with falling edge clock of SCKO just after execution of the instruction to be set to 1 automatically output when ACKE 1 However not automatically cleared to 0 after acknowledge signal output After completion of transfer Continued Note Bits 2 3 and 6 RELD CMDD and ACKD are read only bits Remarks 1 Bits 0 1 and 4 RELD CMDT and ACKT are 0 when read after data setting 2 CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 314 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES R ACKD Acknowledge Detection Clear Conditions ACKD 0 Set Conditions ACKD 1 SCKO fall immediately after the busy mode is When acknowledge signal ACK is detected at the released during the transfer start instruction execution rising edge of SCKO clock after completion of When CSIEO 0 transfer When RESET input is applied R W Synchronizing Busy Signal Output Control Disables busy signal which is output in synchronization with the falling edge of SCKO clock just after execution of the instruction to be cleared to 0 sets READY status Outputs busy signal at the falling edge of SCKO clock following the acknowledge signal Note Busy mode can be cleared by starting serial interface transfer Remark CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 315 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES c Interrupt timing specify register SINT
380. k Output Control Circuit Functions eese eene nnne 253 12 2 Clock Output Control Circuit Configuration nnns 254 12 3 Clock Output Function Control Registers enne 254 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT nennen nennen nnn 257 13 1 Buzzer Output Control Circuit Functions eeeseeseeeeeeeeeee esee nennen 257 13 2 Buzzer Output Control Circuit Configuration 257 13 3 Buzzer Output Function Control Registers ennt 258 CHAPTER 14 A D CONVERTER 261 14 1 A D Converter Functions eese eeeseeeeee eene n nnne nnn nass assa tnn usan 261 14 2 A D Converter Configuration 262 14 3 A D Converter Control Registers 265 14 4 A D Converter Operations eeeeeseeiseeeeeeeee sienne nennen nne n nant nain nna sinit nini nn ennnen nenn 269 14 4 1 Basic operations of A D converter 269 14 4 2 Input voltage and conversion results essseseeeeeen mener 271 14 4 8 A D converter operating mode
381. k cycle after sampling until data transmission resumes Therefore in order to definitely cancel a wait state it is necessary for the slave side to keep the busy signal for at least 1 5 clock cycles Figure 18 20 shows the timing of the busy signal and wait cancel In this figure an example of the case where the busy signal becomes active when sending or receiving starts is shown 425 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 426 Active High In the case where the busy Figure 18 20 Busy Signal and Wait Cancel When BUSYO 0 Scki SO AD7XDeADSAD4XDSADZAD ADO AD7XDOADSAD4ADSAD2AD ADO Sh VD7ADOADSADAADSAD2ADIADO AD7ADOADSAD4ADSAD2AD ADO BUSY LT 1 5 clocks min signal becomes inactive directly when sampled ef eee BUSY Input Release BUSY Input Valid b Busy amp strobe control option Strobe control is a function for synchronizing the sending and receiving of data between a master device and slave device When sending or receiving of 8 bit data ends the strobe signal is output by the master device from pin STB P23 By doing this itis possible for the slave device to know the master transmission end timing Therefore even if there is noise in the serial clock and bit slippage occurs synchronization is maintained and bit slippage has no effect on transmission of the next byte In the case that the strobe control option is used the conditions shown below are neces
382. ke P2 5 and PM2 5 in the program example below as P2 6 and PM2 6 For the timing of each signal when this program is executed refer to Figure 17 22 383 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Example of program releasing serial transfer status 384 SET1 SET1 SET1 CLR1 SET1 SET1 CLR1 CLR1 CLR1 1 2 3 4 5 6 lt 7 gt lt 8 gt lt 9 gt P2 5 1 PM2 5 2 PM2 7 3 CSIEO 4 CSIEO 5 RELT 6 PM2 7 7 P2 5 8 PM2 5 9 This instruction prevents the SDAO pin from outputting a low level when the I2C bus mode is restored by instruction 5 The output of the SDAO pin goes into a high impedance state This instruction sets the P25 SDAO pin in the input mode to protect the SDAO line from adverse influence when the port mode is set by instruction 4 The P25 pin is set in the input mode when instruction 2 is executed This instruction sets the P27 SCL pin in the input mode to protect the SCL line from adverse influ ence when the port mode is set by instruction 4 The P27 pin is set in the input mode when instruction 3 is executed This instruction changes the mode from I C bus mode to port mode This instruction restores the 12C bus mode from the port mode This instruction prevents the SDAO pin from outputting a low level when instruction 8 is executed This instruction sets the P27 pin in the outpu
383. latch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO c Interrupt timing specify register SINT SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Symbol 7 1 Address After Reset R W 5 Teo mele ren nme CSIIFO is set upon termination of serial interface channel 0 transfer CSIIFO is set upon bus release detection or termination of serial interface channel 0 transfer R CLD CKOPinLevelM F Pin CKOPinLevelM F Low level High level Notes 1 Bit 6 CLD is a read only bit 2 When CSIEO 0 CLD becomes 0 Caution Be sure to set bits 0 to 3 to 0 in the 2 wire serial I O mode is used CSIIFO Interrupt request flag corresponding to INTCSIO 360 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 2 Communication operation The 2 wire serial I O mode is used for data transmission reception in 8 bit units Data transmission reception is carried out bit wise in synchronization with the serial clock Shift operation of the serial I O shift register 0 SIOO is carried out in synchronization with the falling edge of the serial clock The transmit data is held in the SOO latch and is output from the SBO SDAO P25 or SB1 SDA1 P26 pin on an MSB first basis The receive data input from the SBO or SB1 pin is latched into the shift register a
384. level from the pin 284 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES The uPD78058F Subseries incorporates three channels of serial interfaces Differences between channels 0 1 and 2 are as follows Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1 2 Table 16 1 Differences Among Channels 0 1 and 2 Serial Transfer Mode 3 wire serial Clock selection Channel 0 fxx 2 fxx 22 fxx 23 fxx 24 fxx 25 26 fxx 27 fxx 28 external clock TO2 output Channel 1 fxx 2 fxx 22 fxx 23 fxx 24 fxx 25 26 fxx 2 fxx 28 external clock TO2 output Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel Channel 2 Baud rate generator output Transfer method MSB LSB switchable as the start bit MSB LSB switchable as the start bit Automatic transmit receive function MSB LSB switchable as the start bit Transfer end flag Serial transfer end interrupt request flag CSIIFO Serial transfer end interrupt request flag CSIIF1 Serial transfer end interrupt request flag SRIF SBI serial bus interface 2 wire serial I O Enable UART Asynchronous serial interface None None 285 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 16 1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following fou
385. ling the test function eme 502 21 5 2 Test input signal acknowledge operation sesee me 504 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION nnn nnne 505 22 4 External Device Expansion 505 22 2 External Device Expansion Function Control Register eese 508 22 3 External Device Expansion Function Timing eere 510 CHAPTER 23 STANDBY FUNCTION 515 23 4 Standby Function and Configuration 515 aeta E Standby f nctiori RD E AEEA 515 23 1 2 Standby function control 516 23 2 Standby Function Operations seen nnne nn annnm rne nnn nn nnn n 517 23 24 HALI mode iei ede E eaten Lene a eoe e te ec ae inae iate 517 23 225 STOP modes tette ult dett tte MD 520 CHAPTER 24 RESET FUNCTION 2 5 iret teer eret cadre irre ene 523 24 1 Reset Functlon 1212 E 523 CHAPTER 25 ROM CORRECTION c ccscecsceeeeeeseeeesneeeeeneeeeneeeeseeesesaaeeeneeeeesaaeseneeeeeseaeseasneeesseeseeseeaenes 527 25 1 ROM
386. lleviated 387 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18 2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware Table 18 1 Serial Interface Channel 1 Configuration Configuration Serial I O shift register 1 S101 Register Automatic data transmit receive address pointer ADTP Timer clock select register 3 TCL3 Serial operating mode register 1 CSIM1 Control register Automatic data transmit receive control register ADTC Automatic data transmit receive interval specify register ADTI Port mode register 2 PM2 Note Note See Figure 6 5 and Figure 6 7 P20 P21 P23 to P26 Block Diagram and Figure 6 6 and Figure 6 8 P22 and P27 Block Diagram 388 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 1 Serial Interface Channel 1 Block Diagram Internal Bus Automatic Data Buffer RAM HORE Spo o 1 A bun Latch PM23 9s B Hand shake pi STB P23 BUSY P24 SCK1 P22 Serial Internal Bus Automatic Data Transmit Receive Interval Specify Register DIR ADTI ADTI ADTI ADTI ADTI ADTI pe lanto Erce 7 4 3 2 1 0 Match ADTIO to ADTI4 5 Bit Counter Automatic Data Transmit Receive Control Register Serial Operating Mode Register 1 CSIM CSIM IE1 ATE Ese oe we Selector 9
387. lock input output pin 1 Master CMOS and push pull output 2 Slave Schmitt input b SBO SB1 Serial data input output dual function pin Both master and slave devices have an N ch open drain output and a Schmitt input Because the serial data bus line has an N ch open drain output an external pull up resistor is necessary Figure 16 26 Pin Configuration Slave Device Master Device Clock Output gt Serial Clock Clock Output gt Clock Input Clock Input AVop N ch Open Drain SBO SB1 tn SBO 81 N ch Open Drain Serial Data Bus gt 500 777 AVss sio Caution When receiving data it is necessary to set the N ch open drain output in the high impedance state so please write in serial I O shift register 0 5100 in advance This will keep it in the high impedance state at all times during transmission However in the case of the wake up function instruction bit WUP z 1 the N ch open drain output is always in the high impedance state so it is not necessary to write FFH in SIOO before reception 323 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 6 7 8 324 Address match detection method In the SBI mode the master transmits a slave address to select a specific slave device Coincidence of the addresses can be automatically detected by hardware CSIIFO is set only when the slave address transmitted by the master coincides with the
388. lows another function to be used simultaneously with the external event CROO set as compare register counter See the description of the respective control registers for details 200 CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 27 External Event Counter Configuration Diagram 16 Bit Capture Compare Register 00 CROO INTTMOO Clear rR 16 Bit Timer Register TMO gt INTPO 16 Bit Capture Compare Register 01 CRO1 Internal Bus Figure 8 28 External Event Counter Operation Timings with Rising Edge Specified moPnmu O LT LILI LILI LI LT LT LT LT LT I TMO Count Value Xooooyoooryooozyooos y Ww ooo yoooz INTTMO Caution When reading the external event counter count value TMO should be read 201 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 5 6 Square wave output operation Operates as a square wave output at the desired frequency with the count value set previously in the 16 bit capture conveyor register 00 CROO as the interval The TOO P30 pin output status is reversed at intervals of the count value preset to CROO by setting bit 0 TOEO and bit 1 TOC01 of the 16 bit timer output control register to 1 This enables a square wave with any selected frequency to be output 202 Figure 8 29 Control Register Settings in Square Wave Output Mode a 16 bit timer mode cont
389. ltiple slave devices This mode configures a serial bus that includes only a single master device and is based on the clocked serial I O format with the addition of bus configuration functions which allows the master device to communicate with a number of slave devices using only two lines serial clock SCL line and serial data bus SDAO or SDA1 line Consequently when the user plans to configure a serial bus which includes multiple microcontrollers and peripheral devices using this configuration results in reduction of the required number of port pins and on board wires In the 12 bus specification the master sends start condition data and stop condition signals to slave devices through the serial data bus while slave devices automatically detect and distinguish the type of signals due to the signal detection function incorporated as hardware This simplifies the application program controlling the I C bus An example of a serial bus configuration is shown in Figure 17 13 This system below is composed of CPUs and peripheral ICs having serial interface hardware that complies with the 12 bus specification Note that pull up resistors are required to connect to both serial clock line and serial data bus line because open drain buffers are used for the serial clock pin SCL and the serial data bus pin SDAO or SDA1 on the I C bus The signals used in the 12C bus mode are described in Table 17 4 Figure 17 13 Example of Serial Bus Config
390. lue cleared to 0 and the interrupt request signal INTTMOO is generated Count clock of the 16 bit timer event counter can be selected with bits 4 to 6 TCLO4 to TCLO6 of the timer clock select register 0 TCLO For the operation when the value of the compare register has been changed during timer count operation refer to section 8 6 3 Operation after compare register change during timer count operation Figure 8 10 Control Register Settings for Interval Timer Operation a 16 bit timer mode control register TMCO TMC03 TMC02 TMC01 OVFO ea b Capture compare control register 0 CRCO Clear amp start on match TMO and CROO 2 CRC01 Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with the interval timer See CROO set as compare register the description of the respective control registers for details 187 CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 11 Interval Timer Configuration Diagram 16 Bit Capture Compare Register 00 CROO INTTM3 INTTMOO 2fxx fxx fxx 2 fxx 2 TIOO POO INTPO Selector 16 Bit Timer Register TMO Clear Circuit Figure 8 12 Interval Timer Operation Timings t 1 c22 i 1 1 1 TMO Count Value JC yowoyoooy Count Start Clear Clear Request Acknowledge MM Request Acknowled
391. m 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm 80 pin plastic TQFP Fine pitch 12 x 12 mm Electrical specifications Recommended soldering conditions 566 Refer to the respective data sheet of each output APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the uPD78058F and 78058FY Subseries Figure B 1 shows the configuration of the development tools 567 APPENDIX B DEVELOPMENT TOOLS Figure B 1 Development Tool Configuration 1 2 1 When using in circuit emulator IE 78K0 NS Language processing software Debugging tools Assembler package C compiler package System simulator Integrated debugger Device file C library source file Device file Tool for PROM writing Embeded software PG 1500 controller Real time OS OS Host machine PC Interface adapter PC card interface etc PROM writing environment In circuit emulator PROM programmer Emulation board Power supply unit Programmer adapter Emulation probe Product with on chip PROM Conversion socket or conversion adapter Target system 568 APPENDIX B DEVELOPMENT TOOLS Figure B 1 Development Tool Configuration 2 2 2 When using in circuit emulator IE 78001 R A Language processing software Debugging tools
392. m of Reset Function Reset Reset Control Circuit Signal Over flow Interrupt Count Clock Watchdog Timer 523 CHAPTER 24 RESET FUNCTION Figure 24 2 Timing of Reset Input by RESET Input DID Dw VI i Oscillation Normal Operation Reset Period EAE chet Normal Operation P oo Sasa ria Reset Processing RESET Nf Internal Reset Signal a a o Delay Delay Port Pin a eee EA es ar T Figure 24 3 Timing of Reset due to Watchdog Timer Overflow PN NE Normal Operation gt Reset Period gt Oscillation Normal Operation Watchdog Oscillation Stabilization Reset Processing Timer Stop Time Wait Overflow IEEE SNP DUM Internal Reset Signal A Port Pin Figure 24 4 Timing of Reset Input in STOP Mode by RESET Input x1 STOP Instruction Execution Stop Status Reset Period Oscillation 1 Normal Operation ass Oscillation Oscillation Stabilization Normal Operation Stop Stop Time Wait Reset Processing RESET IN Internal Reset Signal gt gt Delay Delay Hi Z PotPin ee ee ee ee ee eee ee eee ee 524 CHAPTER 24 RESET FUNCTION Table 24 1 Hardware Status After Reset 1 2 Hardware Status after Reset Program counter PC Note 1 The contents o
393. main system clock operation MCC css y CLS lt Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock b Operation when MCC is set in case of main system clock operation MCC CSS CLS Oscillation does not stop Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock PLILI LILI LILI LILI LILI LS 166 CHAPTER 7 CLOCK GENERATOR Figure 7 9 Main System Clock Stop Function 2 2 c Operation when CSS is set after setting MCC with main system clock operation MCC CSS CLS A Main System Clock Oscillation N Subsystem Clock Oscillation CPU Clock 7 5 2 Subsystem clock operations When operated with the subsystem clock with bit 5 CLS of the processor clock control register PCC set to 1 the following operations are carried out a The minimum instruction execution time remains constant 122 us when operated at 32 768 kHz irrespective of bits 0 to 2 PCCO to PCC2 of the PCC b Watchdog timer counting stops Caution Do not execute the STOP instruction while the subsystem clock is in operation 7 6 Changing System Clock and CPU Clock Settings 7 6 1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bits 0 to 2 PCCO to PCC2 and bit 4 CSS of the processor clock control register PCC The actual switchover operation is not performed directly after writing to the PCC but
394. match in address reception When CSIEO 0 When RESET input is applied Command Detection Clear Conditions CMDD 0 Set Conditions CMDD 1 When transfer start instruction is executed When command signal CMD is detected When bus release signal REL is detected When CSIEO 0 When RESET input is applied Acknowledge signal is output in synchronization with the falling edge clock of SCKO just after execution ofthe instruction to be set to 1 and after acknowledge signal output automatically cleared to 0 Used as ACKE O Also cleared to 0 upon start of serial interface transfer or when CSIEO 0 Note Bits 2 3 and 6 RELD CMDD and ACKD are read only bits Remarks 1 Bits 0 1 and 4 RELD CMDT and ACKT are 0 when read after data setting 2 CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 296 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES Figure 16 5 Serial Bus Interface Control Register Format 2 2 R W ACKE Acknowledge Signal Automatic Output Control Acknowledge signal automatic output disable output with ACKT enable Before completion of Acknowledge signal is output in synchronization with the 9th clock transfer falling edge of SCKO automatically output when ACKE 1 Acknowledge signal is output in synchronization with the falling edge of After completion of SCKO just after execution of the instruction to be set to 1 transfer automaticall
395. memory manipulation instruction RESET input sets SCS value to 00H Figure 8 9 Sampling Clock Select Register Format Symbol 7 6 Address After Reset R W 5 4 3 2 1 0 scs o o o o oo cem ERST INTPO Sampling Clock Selection MCS 1 MCS 0 fx 2 39 1 kHz fx 2 19 5 kHz fx 2 156 3 kHz fx 2 78 1 kHz fx 2 78 1 kHz 1 2 39 1 kHz Caution fxx 2N is the clock supplied to the CPU and fxx 25 26 and fxx 27 are clocks supplied to peripheral hardware fxx 2N is stopped in HALT mode Remarks 1 N Value set in bits 0 2 PCCO to PCC2 of the processor clock control register PCC N 0 to 4 2 bx Main system clock frequency fx or fx 2 3 fx Main system clock oscillation frequency 4 MCS Bit 0 of oscillation mode selection register OSMS 5 Figures in parentheses apply to operation with fx 2 5 0 MHz 186 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 5 16 Bit Timer Event Counter Operations 8 5 1 Interval timer operations Setting the 16 bit timer mode control register and capture compare control register 0 CRCO as shown in Figure 8 10 allows operation as an interval timer Interrupt requests are generated repeatedly using the count value set in 16 bit capture compare register 00 CROO beforehand as the interval When the count value of the 16 bit timer register matches the value set to CROO counting continues with the TMO va
396. mer 8 bit timer event counter Operable when TI1 and TI2 are selected for the count clock Watch timer Operable when fxr is selected for the Operation stops count clock Watchdog timer Operation stops A D converter D A converter Operable Real time output port Operable when external trigger is used or 1 and TI2 are selected for the 8 bit timer event counter count clock Serial interface Other than Operable when externally supplied clock is specified as the serial clock automatic transmit receive function and UART Automatic Operation stops transmit receive function and UART External interrupt INTPO Not operable INTP1 to INTP6 Operable Bus line for ADO to AD7 High impedance external AO to A15 Status before STOP mode setting is held expansion ASTB Low level WR RD High level WAIT High impedance 520 CHAPTER 23 STANDBY FUNCTION 2 STOP mode release The STOP mode can be cleared with the following three types of sources a Release by unmasked interrupt request The STOP mode is cleared upon generation of an unmasked interrupt request If interrupt acknowledge is enabled vectored interrupt servicing is performed after the lapse of the oscillation stabilization time If interrupt acknowledge is disabled the next address instruction is executed Figure 23 4 STOP Mode Release by Interrupt Request Generation Wait STOP Time set by OSTS
397. mination of A D conversion 5 Bit 7 of the sequential conversion register SAR is set The serial resistance string s voltage tap is set at 1 2 AVnero by the tap selector 6 The difference in voltages between the serial resistance string s voltage tap and the analog input is compared by the voltage comparator If the analog input is greater than 1 2 AVrero the of SAR remains set as is Also if it is less than 1 2 AVrero the MSB is reset 7 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison In this case the series resistor string voltage tap is selected according to the preset value of bit 7 as described below e Bit7 1 3 4 AVREFo Bit7 0 1 4 AVnerFo The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated with the result as follows Analog input voltage gt Voltage tap Bit 6 1 Analog input voltage lt Voltage tap Bit 6 0 8 Comparison of this sort continues up to bit 0 of SAR 9 Upon completion of the comparison of 8 bits any effective digital resultant value remains in SAR and the resultant value is transferred to and latched in the A D conversion result register ADCR At the same time the A D conversion termination interrupt request INTAD can also be generated 269 CHAPTER 14 A D CONVERTER Figure 14 5 A D Converter Basic Operation Conversion t Sampling Time
398. mode 1 16 bit interval timer Interrupt requests can be generated at the preset time intervals Table 9 3 Interval Times When 8 Bit Timer Event Counters are Used as 16 Bit Timer Event Counter Minimum Interval Time Maximum Interval Time Resolution MCS 1 MCS 0 1 MCS 0 2 x 1 fx 22 x 1 fx 217 x 1 fx 218 x 1 fx 2 x 1 fx 22 x 1 fx 400 ns 800 ns 26 2 ms 52 4 ms 400 ns 800 ns 22 x 1 fx 23 x 1 fx 218 x 1 fx 219 x 1 fx 22 x 1 fx 23 x 1 fx 800 ns 1 6 us 52 4 ms 104 9 ms 800 ns 1 6 us 23 x 1 fx 24 x 1 fx 219 x 1 fx 220 x 1 fx 23 x 1 fx 24 x 1 fx 1 6 us 3 2 us 104 9 ms 209 7 ms 1 6 us 3 2 us 24 x 1 fx 25 x 1 fx 220 x 1 fx 221 x 1 fx 24 x 1 fx 25 x 1 fx 3 2 us 6 4 us 209 7 ms 419 4 ms 3 2 us 6 4 us 25 x 1 fx 26 x 1 fx 221 x 1 fx 222 x 1 fx 25 x 1 fx 26 x 1 fx 6 4 us 12 8 us 419 4 ms 838 9 ms 6 4 us 12 8 us 26 x 1 fx 27 x 1 fx 222 x 1 fx 223 x 1 fx 28 x 1 fx 27 x 1 fx 12 8 us 25 6 us 838 9 ms 1 7 s 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 223 x 1 fx 224 x 1 fx 27 x 1 fx 28 x 1 fx 25 6 us 51 2 us 1 7 s 3 4 s 25 6 us 51 2 us 28 x 1 fx 29 x 1 fx 224 x 1 fx 225 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 us 3 4 s 6 7 s 51 2 us 102 4 us 29 x 1 fx 210 x 1 fx 225 x 1 fx 226 x 1 fx 29 x 1 fx 210 x 1 fx 102 4 us 204 8 us 6 7 s 13 4 s 102 4 us 204 8 us 211 x 1 fx 212 x 1 fx 227 x 1 fx 228 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 26 8 s 5
399. n at the momenta value other than 0 0 0 operation stop mode is set to 1 to TMCO3 respectively 205 CHAPTER 8 16 TIMER EVENT COUNTER 2 One shot pulse output using external trigger If the 16 bit timer mode control register TMCO capture compare control register 0 CRCO and the 16 bit timer output control register TOCO are set as shown in Figure 8 33 a one shot pulse is output from the TOO P30 pin with a TIOO POO valid edge as an external trigger Any of three edge specifications can be selected rising falling or both edges as the valid edges for the TIOO PO0 pin by means of bits 2 and ES10 and 511 of external interrupt mode register 0 INTMO When a valid edge is inputto the TIOO POO pin the 16 bit timer event counter is cleared and started and output is activated by the count values set beforehand in 16 bit capture compare register 01 CRO1 Thereafter output is inactivated by the count value set beforehand in 16 bit capture compare register 00 CROO Caution When outputting one shot pulses external trigger is ignored if generated again Figure 8 33 Control Register Settings for One Shot Pulse Output Operation Using External Trigger a 16 bit timer mode control register TMCO TMC03 TMC02 TMCO1 OVFO UE RE ee ee b Capture compare control register 0 CRCO Clear amp start with valid edge of TI00 P00 pin CRC02 CRCO1 CRCOO CROO set as com
400. n cannot be stopped The main system clock is divided and supplied to the peripheral hardware The subsystem clock is supplied to 16 bittimer event counter the watch timer and clock output functions only Thus 16 bit timer event counter when selecting watch timer output for count clock operating with subsystem clock the watch function and the clock output function can also be continued in the standby state However since all other peripheral hardware operate with the main system clock the peripheral hardware also stops if the main system clock is stopped Except external input clock operation 165 CHAPTER 7 CLOCK GENERATOR 7 5 1 Main system clock operations When operated with the main system clock with bit 5 CLS of the processor clock control register PCC set to 0 the following operations are carried out by PCC setting a Because the operation guarantee instruction execution speed depends on the power supply voltage the minimum instruction execution time can be changed by bits 0 to 2 PCCO to PCC2 of the PCC b If bit 7 MCC of the PCC is set to 1 when operated with the main system clock the main system clock oscillation does not stop When bit 4 CSS of the PCC is set to 1 and the operation is switched to subsystem clock operation CLS 1 after that the main system clock oscillation stops see Figure 7 9 Figure 7 9 Main System Clock Stop Function 1 2 a Operation when MCC is set after setting CSS with
401. n enable Watch Flag Set Time Selection fxx 5 0 MHz Operation fxx 4 19 MHz Operation fxt 32 768 kHz Operation 2 fw 0 4 sec 2 fw 0 5 sec 2 fw 0 5 sec 2 5 tw 0 2 sec 2 fw 0 25 sec 2 fw 0 25 sec Prescaler Interval Time Selection TMC25 fxx 5 0 MHz Operation fxx 4 19 MHz Operation fxt 32 768 kHz Operation 2 fw 410 us 2 fw 488 us 2 fw 488 us 2 fw 819 us 2 fw 977 us 2 fw 977 us 2 fw 1 64 ms 2 fw 1 95 ms 2 fw 1 95 ms 2 fw 3 28 ms 2 fw 3 91 ms 2 fw 3 91 ms 28 fw 6 55 ms 2 fw 7 81 ms 2 fw 7 81 ms 2 fw 13 1 ms 2 fw 15 6 ms 2 fw 15 6 ms Other than above Setting prohibited Caution When the watch timer is used the prescaler should be cleared frequently Remarks fw Watch timer clock frequency 27 or fxr Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency fxr Subsystem clock oscillation frequency 243 CHAPTER 10 WATCH TIMER 10 4 Watch Timer Operations 10 4 1 Watch timer operation When the 32 768 kHz subsystem clock or 4 19 MHz main system clock is used the timer operates as a watch timer with a 0 5 second or 0 25 second interval The watch timer sets the test input flag WTIF to 1 at the constant time interval The standby state STOP mode HALT mode can be cleared by setting WTIF to 1 When bit 2 TIMC22 of the wa
402. n enabled Cautions 1 Ensure that bits 0 and 3 to 6 are set to 0 2 When UART mode is selected CSIM2 should be set to 00H 438 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 2 Asynchronous serial interface mode register ASIM This register is set when serial interface channel 2 is used in the asynchronous serial interface mode ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM to OOH Figure 19 4 Asynchronous Serial Interface Mode Register Format Symbl 75 5 4 3 2 1 0 Address After Reset R W ASIM PS1 PSO ISRM FF70H 00H R W SCK Clock Selection in Asynchronous Serial Interface Mode Input clock from off chip to ASCK pin Dedicated baud rate generator outputNete ISRM Control of Reception Completion Interrupt Request in Case of Error Generation Reception completion interrupt request generated in case of error generation Reception completion interrupt request not generated in case of error generation Character Length Character Length Specification Parity Bit Parity Bit Specification No Parity 0 parity always added in transmission No parity test in reception parity error not generated Odd parity Even parity 0 Receive operation stopped Receive operation enabled 0 Transmit operation stopped Transmit operation enabled Note When SCK is set to 1 and the baud rate generator output is selected the ASCK pin c
403. n instruction Figure 16 34 SCKO0 P27 Pin Configuration Manipulated by bit manipulation instruction SCKO P27 gt gt Internal P27 Output Circuit Latch SCKO 1 while transfer is stopped From Serial Clock Control Circuit When CSIEO 1 and CSIMO1 and CSIMOO are 1 and 0 or 1 and 1 336 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES The uPD78058FY Subseries incorporates three channels of serial interfaces Differences between channels 0 1 and 2 are as follows Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1 Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel 2 Table 17 1 Differences Among Channels 0 1 and 2 Serial Transfer Mode 3 wire serial I O Clock selection Channel 0 fxx 2 fxx 22 fxx 23 fxx 24 fxx 25 26 27 fxx 28 external clock TO2 output Channel 1 fxx 2 fxx 22 fxx 23 fxx 24 fxx 25 26 fxx 27 fxx 28 external clock TO2 output Channel 2 Baud rate generator output Transfer method MSB LSB switchable as the start bit MSB LSB switchable as the start bit Automatic transmit receive function MSB LSB switchable as the start bit Transfer end flag Serial transfer end interrupt request flag CSIIFO Serial transfer end interrupt request flag CSIIF1 Serial transfer end interrupt request flag SRIF 2 wi
404. n system clock selected instruction 0 4 us 0 8 us 1 6 us 3 2 us 6 4 us 12 8 us at 5 0 MHz operation execution time With subsystem clock selected 122 us at 32 768 kHz operation Instruction set 16 bit operation Multiply divide 8 bits x 8 bits 16 bits 8 bits Bit manipulate set reset test and Boolean operation BCD adjust etc port Total 69 CMOS input 2 e CMOS I O 63 N ch open drain 4 A D converter 8 bit resolution x 8 channels D A converter 8 bit resolution x 2 channels Serial interface 3 wire serial I O SBI 2 wire serial I O mode selection possible 1 channel e 3 wire serial I O mode 32 byte on chip auto transmit receive 1 channel e 3 wire serial I O UART mode selectable 1 channel 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Timer output Three outputs 14 bit PWM output enable 1 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz 5 0 MHz at 5 0 MHz operation with main system clock 32 768 kHz at 32 768 kHz operation with subsystem clock Clock output Notes 1 The capacities of the internal PROM and the internal high speed RAM can be changed using the memory size switching register IMS 2 The capacity of the internal expansion RAM can be changed using the internal expansion RAM
405. n the A D converter and D A converter are not used always use the same potential as that of the Vss pin 4 2 15 RESET This is a low level active system reset input pin 4 2 16 X1 and X2 Crystal resonator connect pins for main system clock oscillation For external clock supply input it to X1 and its inverted signal to X2 4 2 17 XT1 and XT2 Crystal resonator connect pins for subsystem clock oscillation For external clock supply input it to XT1 and its inverted signal to XT2 4 2 18 Vpp Positive power supply pin Except the port 4 2 19 Vss Ground potential pin Except the port 4 2 20 Vpr versions only High voltage apply pin for PROM programming mode setting and program write verify Connect directly to Vss in normal operating mode When in the normal operating mode connect directly to Vss 89 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 4 2 24 IC Mask ROM version only The IC Internally Connected pin is provided to set the test mode to check the uPD78058FY Subseries at delivery Connect it directly to the Vss with the shortest possible wire in the normal operating mode When a voltage difference is produced between the IC pin and Vss pin because the wiring between those two pins is too long or an external noise is input to the IC pin the user s program may not run normally O Connect IC pins to Vss pins directly As short as possible 90 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 4 3
406. nctions with a port See 3 1 1 or 4 1 1 Normal operating mode pins 1 Port pins do not execute the following operations during A D conversion f performed then the general error standards cannot be maintained during A D conversion 1 If it is used as a port rewriting the output latch of its output 2 Even if it is not used as a port changing the output level of pins used as outputs 261 CHAPTER 14 A D CONVERTER 14 2 A D Converter Configuration The A D converter consists of the following hardware Table 14 1 A D Converter Configuration Analog input 8 Channels ANIO to ANI7 A D converter mode register ADM Control register A D converter input select register ADIS External interrupt mode register 1 INTM1 Successive approximation register SAR Register A D conversion result register ADCR 262 CHAPTER 14 A D CONVERTER Figure 14 1 A D Converter Block Diagram Internal Bus A D Converter Input Select Register Series Resistor String ANIO P10 1 11 mO o ANI2 P12 Voltage m AVhtro ANI3 P13 Comparator 2 ANIA P14 ANI5 P15 ANI6 P16 Successive 6 ANI7 P17 Approximation bue ee AVss Register SAR 3 ADM1 to ADM3 Edge INTP3 P03 8 Control gt INTAD Detector Circuit ES40 541 gt INTP3 Trigger Enable A D Conversion SO pons ADCR A D Converter Mode Register Internal
407. ng is shown in Figure 21 11 and reception operations in cases where multiple non maskable interrupt requests are generated are shown in Figure 21 12 491 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 10 Flowchart from the Time a Non maskable Interrupt Request Is Generated Until It Is Received WDTM4 with watchdog timer mode selected Interval timer Overflow in WDT WDTM3 0 with non maskable interrupt selected Reset processing Interrupt request generation WDT interrupt servicing Interrupt request held pending Interrupt control register unaccessed Yes Interrupt Service start WDTM Watchdog timer mode register WDT Watchdog timer Figure 21 11 Non Maskable Interrupt Request Acknowledge Timing WwW P ici _ memoron _ WE TMIF4 Interrupt requests generated during this time are received at the timing indicated by T TMIF4 Watchdog Timer Interrupt Request Flag 492 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 12 Non Maskable Interrupt Request Acknowledge Operation a If a new non maskable interrupt request is generated during non maskable interrupt servicing program execution NMI Request 1 NMI Request lt 2 gt NMI Request 1 executed NMI Request lt 2 gt held 1 Instruction Execution Held NMI Reque
408. ns in External Memory Expansion Mode Pin Function at External Device Connection Alternate Function Name Function ADO to AD7 Multiplexed address data bus P40 to P47 A8 to A15 Address bus P50 to P57 RD Read strobe signal P64 WR Write strobe signal P65 WAIT Wait signal P66 ASTB Address strobe signal P67 Table 22 2 State of Ports 4 to 6 Pins in External Memory Expansion Mode Ports and bits External Expansion Modes Single chip mode Port Port 256 byte expansion mode Address data WR WAIT ASTB 4 Kbyte expansion mode Address data Address WR WAIT ASTB 16 Kbyte expansion mode Address data Address WR WAIT ASTB Full address mode Address data Address RD WR WAIT ASTB Caution When the external wait function is not used the WAIT pin can be used as a port in all modes 505 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Memory maps when using the external device expansion function are as follows 506 Figure 22 1 Memory Map When Using External Device Expansion Function 1 2 a Memory of the u PD78056F and 78056FY and of the 78 58 and 78P058FY when the internal PROM is 48 Kbytes FFFFH FFOOH FEFFH Internal High Speed RAM FBOOH FAFFH Reserved FAEOH FADFH Internal Buffer RAM FACOH FABFH Reserved FA80H FA7FH Full Address Mode when MM2 to MMO 111 or 16 Kbyte Expansion Mode when MM2 t
409. nsmit data 2 T2 is transferred from the internal buffer RAM to SIO1 Figure 18 16 Internal Buffer RAM Operation in 6 Byte Transmission in Repeat Transmit Mode 1 2 a Before transmission FADFH FAC5H Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 FACOH Transmit data 6 T6 421 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 422 FADFH FAC5H FACOH FADFH FAC5H FACOH Figure 18 16 Internal Buffer RAM Operation in 6 Byte Transmission in Repeat Transmit Mode 2 2 b Upon completion of transmission of 6 bytes Transmit data 1 T1 eos SIO1 Transmit data 2 T2 Transmit data 3 T3 f Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 o CSIIF1 c 7th byte transmission point Transmit data 1 T1 Transmit data 2 T2 L4 d Transmit data 3 T3 dT s PUE 5 ADTP 1 Transmit data 4 4 Transmit data 5 5 25 Transmit data 6 T6 CSIIF1 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 d Automatic transmission reception suspending and restart SCK1 501 S 1 Automatic transmission reception can be temporarily suspended by setting bit 7 CSIE1 of the serial operating mode register 1 CSIM1 to 0 If during 8 bit data transfer the transmission reception is not suspended if bit 7 CSIE1 is set to O
410. nsmit receive control register ADTC Automatic data transmit receive address pointer ADTP Automatic data transmit receive interval specify register ADTI Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Serial operating mode register 2 CSIM2 Baud rate generator control register BRGC Transmit shift register TXS 8102 25 Receive buffer register RXB A D converter mode register ADM A D converter input select register ADIS Correction control registerNote CORCN D A conversion value set register 0 DACSO D A conversion value set register 1 DACS1 D A converter mode register DAM Note This register is provided only in the uPD78058F 78058FY 78P058F and 78PO58FY 110 CHAPTER 5 CPU ARCHITECTURE Table 5 3 Special Function Register List 3 3 Manipulatable Bit Unit Address Special Function Register SFR Name After Reset 1 bit 8 bits 16 bits FFDOH to External access areaNote 1 Undefined FFDFH ae E FFEOH Interrupt request flag register OL 00H FFE1H Interrupt request flag register OH FFE2H Interrupt request flag register 1L FFE4H Interrupt mask flag register OL FFE5H Interrupt mask flag register OH FFE6H Interrupt mask flag register 1L
411. nt operations It is possible to measure the pulse width of the signals input to the TIOO POO pin and TIO1 PO1 pin using the 16 bit timer register TMO There are two measurement methods measuring with TMO used in free running mode and measuring by restarting the timer in synchronization with the edge of the signal input to the TIOO POO pin 1 Pulse width measurement with free running counter and one capture register When the 16 bit timer register TMO is operated in free running mode see register settings in Figure 8 17 and the edge specified by external interrupt mode register 0 INTMO is input to the TIOO POO pin the value of TMO is taken into 16 bit capture compare register 01 CRO1 and an external interrupt request signal INTPO is set Any of three valid edge specifications can be selected rising falling or both edges by means of bits 2 and 3 ES10 and ES11 of INTMO For valid edge detection sampling is performed at the interval selected by means of the sampling clock selection register SCS and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Figure 8 17 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register a 16 bit timer mode control register TMCO TMC03 TMCO2 TMCO1 OVFO LESHURRCHIECSIE S S BEER SES b Capture compare control register 0 CRCO Free Running Mode CRC02 CRC01
412. number of available input output ports Figure 16 1 Serial Bus Interface SBI System Configuration Example AVop Master CPU Slave CPU1 SCKO SCKO SBO SBO Slave CPU2 SCKO 7 SBO Slave CPUn 287 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 16 2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware Table 16 2 Serial Interface Channel 0 Configuration Serial I O shift register 0 SIOO Register Slave address register SVA Timer clock select register 3 TCL3 Serial operating mode register 0 CSIMO Control register Serial bus interface control register SBIC Interrupt timing specify register SINT Port mode register 2 PM2 Nete Note See Figure 6 5 P20 P21 P23 to P26 Block Diagram and Figure 6 6 P22 and P27 Block Diagram 288 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES Figure 16 2 Serial Interface Channel 0 Block Diagram Internal Bus Serial Operating Mode Register 0 CSIM CSIM CSIM CSIM Serial Bus Interface Control Register Slave Address BSYE ACKT CMDD RELD CMDT RELT Register SVA y I SVAM Match LN SIO SBO p25 9 PM25 P25 Output Latch Output Control SO0 SB1 o P26 Y PM26 Output Control CLD P26 Ou
413. o 4 PUO6 Yo P ch RD e i T x lt 2 A 2 WRpPorT Lo e EM Rs P64 RD 5 Output Latch P65MR P64 to P67 P66 WAIT P67 ASTB WRem 64 to PM67 e UIN al PUO Pull up resistor option register PM Port mode register RD Port 6 read signal WR Port 6 write signal 141 CHAPTER 6 PORT FUNCTIONS 6 2 9 Port 7 This is a 3 bit input output port with output latches Input mode output mode can be specified bit wise by means of port mode register 7 PM7 When pins P70 to P72 are used as input port pins an on chip pull up resistor can be used as a 3 bit unit by means of pull up resistor option register L PUOL Alternate functions include serial interface channel 2 data input output and clock input output RESET input sets the input mode Figures 6 15 and 6 16 show block diagrams of port 7 Caution When used as a serial interface pin set the input output and output latch according to its functions For the setting method refer to Table 19 2 Serial Interface Channel 2 Operating Mode Seitings of List Figure 6 15 P70 Block Diagram AVop e WRpeuo Mmo PUO7 RD eC a A 2 WRrort 8 E Output Latch P70 SI2 RxD E P0 70 512 WRem PM70 hd PUO Pull up resistor option register PM Port mode register RD Port 7 read signal WR Port 7 write signal 142 CHAPTER 6 PORT FUNCTIONS Internal bus
414. o MMO 101 DOOOH CFFFH 4 Kbyte Expansion Mode when MM2 to MMO 100 C100H COFFH 256 byte Expansion Mode CoooH when 2 to 011 BFFFH Single chip Mode 0000H CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22 1 Memory Map When Using External Device Expansion Function 2 2 b uPD78058F 78058FY 78P058F 78PO58FY Memory uPD78058F 78058FY 78P058F 78PO58FY Memory map when internal ROM PROM size is 56 Kbytes map when internal ROM PROM size is 60 Kbytes FFFFH FFFFH FFOOH FFOOH FEFFH FEFFH Internal High Speed RAM Internal High Speed RAM FBOOH FBOOH FAFFH FAFFH Reserved Reserved FAEOH FAEOH FADFH FADFH Internal Buffer RAM Internal Buffer RAM FACOH FACOH FABFH FABFH Reserved Reserved F800H F800H F7FFH F7FFH Internal Expansion RAM Internal Expansion RAM F400H F400H F3FFH F3FFH Full Address Mode when 2 to 111 or R d 16 Kbyte Expansion Mode when 2 101 FOOOH 4 Kbyte Expansion Mode FOOOH E100H when MM2 to 100 EFFFH FOFFH 256 byte Expansion Mode E000H when MM2 to 011 DFFFH Single chip Mode Single chip Mode 0000H 0000H Caution When the internal ROM PROM size is 60 Kbytes the area from F000H F3FFH cannot be used F000H to F3FFH can be used as external memory by setting the internal ROM PROM size to less than 56 Kbytes by the memory size
415. ock diagrams of port 2 Cautions 1 When used as a serial interface pin set the input output and output latch according to its functions For the setting method refer to Figure 16 4 Serial Operating Mode Register 0 Format and Figure 18 3 Serial Operating Mode Register 1 Format 2 When reading the pin state in SBI mode set PM2n bit of PM2 to 1 n 5 6 See 16 4 3 10 How to determine the slave busy state Figure 6 5 P20 P21 P23 to P26 Block Diagram AVop e WRPuo 4 PUO2 34 P ch RD e p lt C re g A WRport 4 P20 SM g P21 SO1 5 Output Latch P23 STB t P20 P21 P23 to P26 poapusy P25 SIO SBO P26 SO0 SB1 WRem 20 21 4 x PM23 to PM26 ntm Alternate Function PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal 133 CHAPTER 6 PORT FUNCTIONS Figure 6 6 P22 and P27 Block Diagram AVop 2 Jo P on RD 8 WRport b oa xx D Output Latch P22 P27 a WRem os PM22 PM27 e m m Alternate Function PUO Pull up resistor option register Port mode register RD Port 2 read signal WR Port 2 write signal 134 CHAPTER 6 PORT FUNCTIONS 6 2 4 Port 2 uPD78058FY Subseries Port 2 is an 8 bit input o
416. ode of the real time output port and output trigger RTPC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 20 5 Real time Output Port Control Register Format After Symbol 7 6 5 4 3 2 oO Address Reset R W we e T Ts T T s elen con EXTR Real time Output Control by INTP2 0 INTP2 not specified as real time output trigger 1 INTP2 specified as real time output trigger BYTE Real time Output Port Operating Mode 0 4 Bits x 2 Channels 1 8 Bits x 1 Channel Table 20 3 Real time Output Port Operating Mode and Output Trigger BYTE EXTR Operating Mode RTBH gt Port Output RTBL gt Port Output 4 bits x 2 channels INTTM2 INTTM1 INTTM1 INTP2 8 bits x 1 channel INTTM1 INTP2 475 MEMO 476 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 1 Interrupt Function Types The following three types of interrupt functions are used 1 2 3 Non maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status It does not undergo interrupt priority control and is given top priority over all other interrupt requests It generates a standby release signal A non maskable interrupt contains one source of the watchdog timer interrupt request Maskable interrupts These interrupts undergo mask control Maskable interrupts can be divided into a high interrupt priority group and a
417. of CROO Atthis time clear the lower 2 bits to 00 2 Setavalue other than 0000H to CROO When the event counter function is used therefore one pulse cannot be counted 3 If the new value of CROO is less than the value of the 16 bit timer register TMO TMO continues counting overflows and then starts counting again from 0 If the new value of CROO is less than the old value the timer must be restarted after changing the value of CROO 2 Capture compare register 01 CRO1 CRO01 is a 16 bit register which has the functions of both a capture register and a compare register Whether itis used as a capture register or a compare register is set by bit 2 2 of capture compare control register 0 When CR01 is used as a compare register the value set in the CRO1 is constantly compared with the 16 bit timer register count value and an interrupt request INTTMO1 is generated if they match When CR01 is used as a capture register it is possible to select the valid edge of the INTPO TIOO pin as the capture trigger The valid edge of INTPO TIOO is set by interrupt mode register 0 INTMO CR01 is set with a 16 bit memory manipulation instruction After RESET input the value of CRO1 is undefined 177 CHAPTER 8 16 TIMER EVENT COUNTER Caution If the valid edge of the TIOO POO pin is input while CRO1 is read CRO1 does not perform the capture operation and retains the current data However the interrupt request flag
418. of the asynchronous serial interface mode register ASIM only single stop bit detection is performed during reception 441 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 4 Baud rate generator control register BRGC This register sets the serial clock for serial interface channel 2 BRGC is set with an 8 bit memory manipulation instruction RESET input sets BRGC to 00H Figure 19 6 Baud Rate Generator Control Register Format 1 2 Symo 7 5 4 3g Address After Reset R W 2 1 0 BRGC TPS3 TPS2 TPS1 TPSO MDL3 MDL2 MDL1 MDLO FF73H 00H R W MDLO Baud Rate Generator Input Clock Selection k fsck 16 fsck 17 fsck 18 fsck 19 fsck 20 fsck 21 fsck 22 fsck 23 fsck 24 fsck 25 fsck 26 fsck 27 fsck 28 fsck 29 fsck 30 fscKNote Note Can only be used in 3 wire serial I O mode Remarks 1 fsck 5 bit counter source clock 2 k Value set in MDLO to MDL3 0 lt k lt 14 442 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19 6 Baud Rate Generator Control Register Format 2 2 5 Bit Counter Source Clock Selection MCS 1 MCS 0 fxx 210 fxx 210 4 9 kHz 2 4 kHz fxx fx 5 0 MHz 2 5 MHz fxx 2 fx 2 2 5 MHz 1 25 MHz fxx 2 fx 2 1 25 MHz 625 kHz fxx 23 fx 23 625 kHz 313 kHz fxx 24 fx 24 313 kHz 156 kHz 156 kHz 78 1 kHz fxx 25 fx 25 26 fx 26 78
419. of the data between the other slave and master If that data hap pens to coincide with the slave address of the uPD78058FY subseries the uPD78058FY subseries takes part in communication destroying the communication data Note The serial transfer status is the status since data has been written to the serial 1 O shift register 0 SIOO until the interrupt request flag CSIIFO is set to 1 by completion of the serial transfer The above phenomenon can be avoided by modifying the program Before executing the wake up function execute the following program that clears the serial transfer status When executing the wake up function do not execute an instruc tion that writes data to SIOO Even if such an instruction is not executed data can be received while the wake up function is executed This program releases the serial transfer status To release the serial transfer status the serial interface channel 0 must be once disabled by clearing the CSIEO flag bit 7 of the serial operating mode register CSIMO to 0 If the serial interface channel 0 is disabled in the IC bus mode however the SCL pin outputs a high level and SDAO SDA1 pin outputs a low level affecting communication of the I C bus Therefore this program makes the SCL and SDAO SDA1 pins go into a high impedance state to pre vent the 12 bus from being affected In this example the SDAO P25 pin is used as a serial data input output pin When the SDA1 P26 is used ta
420. oken line is an output control circuit 2 fsck Serial clock frequency 218 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 Compare registers 10 and 20 CR10 CR20 These are 8 bit registers to compare the value set to CR10 to the 8 bit timer register 1 TM1 count value and the value set to CR20 to the 8 bit timer register 2 TM2 count value and if they match generate an interrupt request INTTM1 and INTTM2 respectively CR10 and CR20 are set with an 8 bit memory manipulation instruction They cannot be set with a 16 bit memory manipulation instruction When the compare register is used as 8 bit timer event counter the OOH to FFH values can be set When the compare register is used as 16 bit timer event counter the 0000H to FFFFH values can be set RESET input makes CR10 and CR20 undefined Cautions 1 When using the compare register as a 16 bit timer event counter be sure to stop the timer operation before setting data 2 If the values after CR10 and CR20 are changed smaller than those of the 8 bit timer registers TM1 and TM2 TM1 and TM2 continue counting overflow and then restart counting from 0 Thus if the values after CR10 and CR20 change are smaller than the values before the change it is necessary to restart the timer after changing CR10 and CR20 2 8 bit timer registers 1 2 TM1 TM2 These are 8 bit registers to count count pulses When 1 and 2 are used in the 8 bit timer x 2 channel mode they are read wit
421. ol Main Processing INTxx INTyy Servicing Servicing Y 1 Instruction Execution IE 0 RETI During processing of interrupt INTxx interrupt request INTyy was generated but the priority order of this interrupt was lower than that of INTxx so it was not received and multiple interrupts were not generated Interrupt request INTyy was held and received after 1 main processing command was executed PR 0 High Priority Order Level PR 2 1 Low Priority Order Level IE 0 Interrupt Request Reception Prohibited 499 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Example 3 Example of a multiple interrupt not being generated because an interrupt was not permitted Main Processing INTxx INTyy Servicing Servicing Y INTyy _ INTxx PR 0 PR 0 RETI 5 1 Instruction Execution Y In processing of interrupt INTxx interrupt reception was not permitted the IE command was not issued so interrupt request INTyy was not received and multiple interrupts were not generated Interrupt request INTyy was held and received after 1 main processing command was executed PR 0 High Priority Order Level IE 0 Interrupt Request Reception Prohibited 500 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 4 5 Interrupt request reserve Among the commands there are some for which even if an interrupt request is generated while they are being executed reception of the interrupt request is held until ex
422. oltages of ANIO to ANI7 should be within the specification range In particular if a voltage above AVnero or below AVss is input even if within the absolute maximum rating range the conversion value for that channel will be indeterminate The conversion values of the other channels may also be affected CHAPTER 14 A D CONVERTER 3 4 5 Noise countermeasures In order to maintain 8 bit resolution attention must be paid to noise on pins AVrero and ANIO to ANI7 Since the effect increases in proportion to the output impedance of the analog input source it is recommended that a capacitor be connected externally as shown in Figure 14 10 in order to reduce noise Figure 14 10 Connection of Analog Input Pin If there is possibility that noise whose level is AVrero or higher or AVss or lower may be input clamp with a diode with a small Vr 0 3 V or less Reference Voltage Input Bi a AVntro ANIO to ANI7 C 100 to 1000 pF Note order to realize EMI noise reduction supply power separately and AVpp and connect separate grounds to Vss and AVss Pins ANIO P10 to ANI7 P17 The analog input pins ANIO to ANI7 also function as input output port PORT1 pins If one of pins ANIO to ANI7 is selected to perform A D conversion do not execute an input instruction for port 1 during conversion as this could lower the conversion resolution Also if digital pulses
423. omparator of the serial operating mode register 0 CSIMO is tested If 1 normal transmission is judged to have been carried out If 0 a transmit error is judged to have occurred Communication operation In the SBI mode the master device selects normally one slave device as communication target from among two or more devices by outputting an address to the serial bus After the communication target device has been determined commands and data are transmitted received and serial communication is realized between the master and slave devices Figures 16 27 to 16 30 show data communication timing charts Shift operation of the serial I O shift register 0 SIOO is carried out at the falling edge of serial clock SCKO Transmit data is latched into the SOO latch and is output with MSB set as the first bit from the SBO P25 or SB1 P26 pin Receive data input to the SBO or SB1 pin at the rising edge of SCKO is latched into the SIOO Sze Figure 16 27 Address Transmission from Master Device to Slave Device WUP 1 Master Device Processing Transmitter CMDT RELT cMpT Write Interrupt Servicing TONS eneraion _____________ Seti ii euer tribut Stop SCKO Pin N 7 SBO SB1 Pin Y AY Slave Device Processing Receiver Program Processing II LI LLL LIL LI LLL ATP Am LLL i CMDD CMDD CHDD E i INTCSIO idm ACK BUSY Mmm mcm BUSY Hardware Operation vi Serial Reception m
424. on ADCR INTAD 276 CHAPTER 14 A D CONVERTER 7 8 AVbp pin The AVpp pin is the analog circuit power supply pin and supplies power to the input circuits of ANIO P10 to 7 17 Therefore be sure to apply the same voltage as Voo to this pin even when the application circuit is designed so as to switch to a backup battery Figure 14 12 Connection of Pin gt Note Main power Capacitor supply for back up Note order to realize EMI noise reduction supply power separately and AVpp and connect separate grounds to Vss and AVss Port Operations Among A D Converter Operations For pins which have common functions with a port See 3 1 1 or 4 1 1 Normal operating mode pins 1 Port pins do not execute the following operations during A D conversion If performed then the general error standards cannot be maintained during A D conversion 1 If itis used as a port rewriting the output latch of its output 2 Even if it is not used as a port changing the output level of pins used as outputs 277 MEMO 278 CHAPTER 15 D A CONVERTER 15 1 D A Converter Functions The D A converter converts a digital input into an analog value It consists of two 8 bit resolution channels of voltage output type D A converter The conversion method used is the R 2R resistor ladder method D A conversion is started by setting the DACEO and DACE1 of the D A conver
425. on In addition a pull up resistor must be connected to the serial data bus line When the SBI mode is used refer to 11 SBI mode precautions d described later Figure 16 10 Example of Serial Bus Configuration with SBI AVop yol Serial Clock EA SCKO SCKO Slave CPU Master CPU Serial Data Bus SBO SB1 SBO SB1 Address 1 SCKO Slave CPU SBO SB1 Address 2 SCKO Slave IC SBO SB1 Address N Caution When exchanging the master CPU slave CPU a pull up resistor is necessary for the serial clock line SCKO as well because serial clock line SCKO input output switching is carried out asynchronously between the master and slave CPUs 305 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 1 SBI functions In the conventional serial I O format when a serial bus is configured by connecting two or more devices many ports and wiring are necessary to provide chip select signal to identify command and data and to judge the busy state because only the data transfer function is available If these operations are to be controlled by software the software must be heavily loaded In SBI a serial bus can be configured with two signal lines of serial clock SCKO and serial data bus SBO SB1 Thus use of SBI leads to reduction in the number of microcontroller ports and that of wiring and routing on the board The SBI functions are described below 306 a b c d e Address comm
426. on chip pull up resistor will be automatically disabled 59 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 1 Port pins 2 3 Pin Name Input Output P37 Function Port 3 8 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software After Reset Alternate Function P40 to P47 Port 4 8 bit input output port Input output mode can be specified in 8 bit units If used as an input port an on chip pull up resistor can be used by software Test input flag KRIF is set to 1 by falling edge detection ADO to AD7 P50 to P57 Port 5 8 bit input output port LED can be driven directly Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software 8 to A15 Port 6 N ch open drain input output port u On chip pull up resistor can be 8 bit input output port specified by mask option Mask ROM version only Input output mod b dispen dede LEDs can be driven directly specified bit wise If used as an input port an on chip pull up resistor can be used by software ASTB 60 Port 7 3 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software 512 SO2 TxD SCK2 ASCK CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES
427. on is shown below The names in frames are subseries Lo Products in mass production SSS nace arr n Products under development Y subseries products are compatible with bus _ Control 100 pin EMI noise reduced version of the uPD78078 100 pin Timer was added to the PD78054 and the external interface function was enhanced 100 pin uPD78070AY ROM less versions of the PD78078 100 pin 80 pin 80 pin LPD78058F uPD78058FY EMl noise reduced version of the PD78054 80 pin 078054 uPD78054Y J UART and D A converter were added to the PD78014 and I O was enhanced 64 pin 0780034 J2HPD780034Y A D converter of the 44PD780024 was enhanced t 44 TT 64 pin 2 0780024 uPD780024Y Serial I O of the LPD78018F was enhanced 64 uPD78014H 7 EMl noise reduced version of the PD78018F 64 7 uPD78018F Low voltage 1 8 V operation versions of the wPD78014 with choice of several ROM and RAM capacities 64 pin A D converter and 16 bit timer were added to the PD78002 64 pin A D converter was added to the 78002 64 pin Basic subseries for control 42 44 pin On chip UART capable of operation at a low voltage 1 8 V Inverter control see 64 pin D LPD780988 The inverter control timer and SIO of thej PD780964 were enhanced ROM size and RAM size were expanded 64 pin uPD780964 f A D converter of the PD780924 was enhanced 64 pin 1
428. onnect anything to A16 Address Bus RESET Reset CE Chip Enable VoD Power Supply DO to D7 Data Bus Vpp Programming Power Supply OE Output Enable Vss Ground PGM Program 52 CHAPTER 2 OUTLINE uPD78058FY SUBSERIES 2 6 78K 0 Series Expansion The 78K 0 Series expansion is shown below The names in frames are subseries 100 pin 100 pin 100 pin 100 pin 80 pin 80 pin 80 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 42 44 pin 64 pin 64 pin 64 pin 78K 0 Series E 100 pin 100 pin 80 pin 80 pin 100 100 100 80 pin 80 pin L 80 pin EN Products in mass production Y subseries ronds are compatible with I C bus Control EMI noise reduced version of the uPD78078 LPD78078 Timer was added to the PD78054 and the external interface function was enhanced LPD78070A uPD78070AY versions of the uPD78078 EMI noise reduced version of theu PD78018F LPD78018F uPD78018FY Low voltage 1 8 V operation versions of the zPD78014 with choice of several ROM and RAM capacities uPD78014 uPD78014Y A D converter and 16 bit timer were added to the PD78002 uPD780001 A D converter was added to the uPD78002 LPD78002 Basic subseries for control LPD78083 On chip UART capable of operation at a low voltage 1 8 V The inverter control timer and SIO of thej PD780964 were enhanced ROM size and RAM size we
429. ontrol option Remarks 1 fxx 2 fx 3 fsck Main system clock frequency fx or fx 2 Main system clock oscillation frequency Serial clock frequency 407 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 408 5 4 3 2 1 0 Address After Reset R W ADTI 0 ADTI3 ADTI2 ADTIT ADTIO FF6BH 00H R W No control of interval by ADT note 1 Data Transfer Interval Control 0 1 ADTIS ADTI2 ADTI1 Control of interval by ADTI ADTIO to ADTIA Data Transfer Interval Specification fxx 2 5 MHz Operation MinimumNote 2 36 8 us 0O 5 fsck MaximumNete 2 40 0 us 1 5 fsck 62 4us 0 5 fsck 65 6us 1 5 fsck 88 0 us 0 5 91 2 us 1 5 fsck 113 6 us O 5 fsck 116 8 us 1 5 fsck 139 2 us 0O 5 fsck 142 4 us 1 5 fsck 164 8 us O 5 fsck 168 0 us 1 5 fsck 190 4 us 0 5 fscK 193 6 us 1 5 fsck o o o o 216 0 us 0 5 fsck 219 2 us 1 5 fsck 241 6 us 0 5 fsck 244 8 ws 1 5 fsck 267 2 us O 5 fsck 270 4 us 1 5 fsck 292 8 us 0 5 fsck 296 0 us 1 5 fsck 318 4 us 0 5 321 6 us 1 5 344 0 us 0 5 fsck 347 2 us 1 5 fsck 369 6 us 0 5 fsck 372 8 us 1 5 fsck 395 2 us 0 5 fsck 398 4 us 1 5 fsck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Notes 1 2 Cautions Remarks 420 8 us 0 5 fsck 424 0 us 1 5 fsck
430. operation continues on the pre switchover clock for several instructions see Table 7 3 Whether the system is operating on the main system clock or the subsystem clock can be determined with bit 5 CLS of the PCC register 167 891 Set Values before Switchover Table 7 3 Maximum Time Required for CPU Clock Switchover Set Values After Switchover PCC2 PCC1 PCCO PCC2 16 instructions 0 1 0 16 instructions 0 16 instructions 16 instructions fx 2fxt instruction 77 instructions fx 4fxt instruction 39 instructions 8 instructions 8 instructions 8 instructions 8 instructions fx 4fxt instruction 39 instructions fx 8fxr instruction 20 instructions 4 instructions 4 instructions 4 instructions 4 instructions fx 8fxt instruction 20 instructions fx 16fxr instruction 10 instructions 2 instructions 2 instructions 2 instructions 2 instructions fx 16fxr instruction 10 instructions fx 32fxr instruction 5 instructions 1 instruction 1 instruction 1 instruction 1 instruction fx 32fxt instruction 5 instructions fx 64fxr instruction 8 instructions Remarks 1 Caution 1 instruction 1 instruction 1 instruction 2 MCS Oscillation mode selection register OSMS bit 0 3 Figures in parentheses apply to operation with fx 5 0 MHz
431. ormat Smo 0 Address R W Reset PROL PPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPRO TMPR4 FFE8H FFH R W e PROH TMPR01 TMPROOTMPR3 STPR SRPR SERPRCSIPR1 CSIPRO FFE9H FFH R W 7 6 5 4 0 0 PRIL 1 1 1 1 1 ADPR TMPR2 TMPR1 FFEAH FFH R W Priority Level Selection 0 High priority level 1 Low priority level Cautions 1 If a watchdog timer is used in watchdog timer mode 1 set TMPR4 flag to 1 2 Set always 1 in PR1L bits 3 to 7 485 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 4 External interrupt mode register INTMO INTM1 These registers set the valid edge for INTPO to INTP6 INTMO and INTM1 are set by 8 bit memory manipulation instructions RESET input sets these registers to 00H Figure 21 5 External Interrupt Mode Register 0 Format After Symbol 7 6 5 4 3 Address Reset R W 2 1 0 INTMO ES31 ES30 ES21 ES20 ES11 ES10 o FFECH 00H R W ES11 ES10 INTPO Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges INTP2 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges Caution Set the valid edge of the INTPO TIOO POO pin after setting bits 1 to 3 TMC01 to o
432. ort 7 3 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software 512 SO2 TxD SCK2 ASCK CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 1 Port pins 3 3 Pin Name input Output Function After Reset Alternate Function Port 12 RTPO to RTP7 8 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software P130 to P131 Port 13 ANOO to ANO1 2 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software Cautions For pins which have alternate functions as port output do not execute the following operations during A D conversion If performed then the general error standards cannot be maintained during A D conversion lt 1 gt If it is used as a port rewriting the output latch of its output lt 2 gt Even if it is not used as a port changing the output level of pins used as outputs 79 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 2 Non port pins 1 2 Pin Name Input Output Function External interrupt request inputs with specifiable valid edges rising edge falling edge both rising and falling edges After Reset Input Alternate Function POO0 TIOO P01 TIO1 P02 P04 P05 P06 Serial in
433. ote 2 x Note 2 x Note 2 x Note 2 x CSIE1 CSIMI1 PM20 P20 PM21 P21 22 P22 Note 2 x Shift Register 1 Operation Operation stop Serial Clock Counter Operation Control SH P20 Pin Function P20 CMOS input output SO1 P21 Pin Function P21 CMOS input output SCK1 P22 Pin Function P22 CMOS input output Note 3 1 Notes Note 3 x Operation enable Count operation S 1 Note 3 Input SO1 CMOS output of the automatic data transmit receive control register ADTC to 0 0 to 0 Remark x 400 PXX Don t care PMXX Port Mode Register Can be used freely as port function Can be used as P20 CMOS input output when only transmitter is used clear bit 7 RE of ADTC Port Output Latch SCK1 Input SCK1 CMOS output If the external clock input has been selected with CSIM1 1 setto 0 set bit 1 BUSY1 and bit 2 STRB CHAPTER 18 SERIAL INTERFACE CHANNEL 1 2 Communication operation The 3 wire serial I O mode is used for data transmission reception in 8 bit units Bit wise data transmission reception is carried out in synchronization with the serial clock CK1 Shift operation of the serial I O shift register 1 SIO1 is carried out at the falling edge of the serial clock S The transmit data is held in the SO1 latch and is output from the SO1 pin The receive data input to the 511 pin is la
434. ote 3 x Note 3 x Note 3 x SBI mode P25 CMOS input output SB1 N ch open drain input output SBO N ch open drain input output P26 CMOS input output SCKO CMOS input output Note 3 x Note 3 x Note 3 x Note 3 x 2 wired serial mode Notes 1 Bit 6 COI is a read only bit 2 Can be used as P25 CMOS input output when used only for transmission 3 Can be used freely as port function Remark x don t care PMXX Port Mode Register Port Output Latch PXX 294 P25 CMOS input output SB1 N ch open drain input output SBO N ch open drain input output P26 CMOS input output SCKO N ch open drain input output Continued CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES Figure 16 4 Serial Operating Mode Register 0 Format 2 2 R W Wake up Function ControlNete 1 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the slave address register SVA data in SBI mode R Slave Address Comparison Result FlagNete 2 Slave address register SVA not equal to serial I O shift register 0 SIOO data Slave address register SVA equal to serial I O shift register 0 SIOO data R W CSIEO Serial Interface Channel 0 Operation ControlNote
435. ote If an interrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request specified for higher priority with the priority specify flag is acknowledged first Also when the priority order specification flag specifies the same priority order for two interrupts the interrupt request with the higher default priority order is received first Any reserved interrupts request are acknowledged when they become acknowledgeable Figure 21 13 shows interrupt request acknowledge processing algorithms If amaskable interrupt request is received the contents of the program status word PSW and the program counter PC are saved to the stack in that order the IE flag is reset 0 and the content of the received interrupt s priority order specification flag is saved to the ISP flag Further for each interrupt request data from the predetermined vector table are loaded to the PC and branched Return from the interrupt is possible with the RETI instruction 494 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 13 Interrupt Request Acknowledge Processing Algorithm Start i Yes Interrupt Request Generation No Interrupt request reserve Yes High priority Does one of the simultaneously generated XXPR2 0 interrupt request have a high priority
436. ounters esee eeeeeeeeeee nennen nnn nante 236 CHAPTER 10 WATCH TIMER 11 eere ecce cesse eer rese nasse sons assa n nnaman 239 10 1 Watch Timer Functions seen nnne nnnm nnne nnn innen nne sanae nnns innen 239 10 2 Watch Timer 240 10 3 Watch Timer Control Registers 240 10 4 Watch Timer Operations 244 10 4 1 Watch timer operation erinnere ipe LC tere ve Rex geb cen He eek Uo 244 10 4 2 Interval timer operation rette irte 244 18 CHAPTER 11 WATCHDOG TIMER 245 11 1 Watchdog Timer Functions esee 245 11 2 Watchdog Timer Configuration 247 11 3 Watchdog Timer Control Registers leeeeeeeeseeeeeseeeeeeeee nennen nennen nennen 248 11 4 Watchdog Timer 251 11 4 1 Watchdog timer operation a ennt nnn nnn nnns 251 11 4 2 Interval timer operation eite rnt ttr DRE ERAS TRE RI Ren 252 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 253 12 1 Cloc
437. output of the acknowledge signal after normal data reception 4 The busy mode can be released by the start of a serial interface transfer or reception of an address signal However the BSYE flag is not cleared 5 When using the wake up function be sure to set BSYE to 1 CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 369 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES c Interrupt timing specification register SINT SINT is set by the 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H symbol 7 Q 1 Address After Reset R W o P R W WAT1 WATO Interrupt Control by WaitNote 2 Interrupt service request is generated on rise of 8th SCKO clock cycle clock output is high impedance Setting prohibited Used 12C bus mode 8 clock wait Generates an interrupt service request on rise of 8th SCL clock cycle In case of master device SCL pin is driven low after output of 8 clock cycles to enter the wait state In case of slave device SCL pin is driven low after input of 8 clock cycles to require the wait state Used in 12C bus mode 9 clock wait Generates an interrupt service request on rise of 9th SCL clock cycle In case of master device SCL pin is driven low after output of 9 clock cycles to enter the wait state In case of slave device SCL pin is driven low after input of 9 clock cycles to require the wait state R W
438. owledge signal from the master is not output if data transmission from the slave is completed set 1 in the WREL flag of SINT and release the wait For these timings see Figure 17 23 Figure 17 25 Slave Wait Release Transmission Master Device Operation Writing Software Operation t 0 dn SORS SG 100 oon BEEN iui oe Transfer Line SCL 9 a 2 3 sasono Kom fom XX i Slave Device Operation P27 Write P27 Software Operation output data output latch 0 to 5100 latch 1 Po Hardware Operation ACK Setting Wait aed 381 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 3 Slave wait release slave reception The slave is released from the wait status when the WREL flag bit 2 of the interrupt timing specify register SINT is set or when an instruction that writes data to the serial I O shift register 0 SIOO is executed When the slave receives data the first bit of the data sent from the master may not be received if the SCL line immediately goes into a high impedance state after an instruction that writes data to SIO has been executed This is because SIOO does not start operating if the SCL line is in the high impedance state while the instruction that writes data to SIOO is executed until the next instruction is executed Therefore receive the data by manipulating the output latch of P27 by program as shown in Figure 17 26 For this timing refer
439. pace is accessible by setting the memory expansion mode register MM External memory space can store program table data etc and allocate peripheral devices 99 CHAPTER 5 CPU ARCHITECTURE 5 1 5 Data memory addressing The method to specify the address of the instruction to be executed next or the address of a register or memory to be manipulated when an instruction is executed is called addressing The address of the instruction to be executed next is addressed by the program counter PC for details refer to Section 5 3 Instruction Address Addressing On the other hand concerning addressing of memory which is the object of operations during execution of a command in the uPD78058F and uPD78058FY Subseries abundant addressing modes have been provided in consideration of operability etc Particularly in areas FBOOH to FFFFH where data memory is incorporated special addressing which matches the respective functions of the special function register SFR general purpose register etc is possible Figure 5 4 to 5 6 show the data memory addressing modes For details of each addressing refer to Section 5 4 Operand Address Addressing Figure 5 4 Data Memory Addressing uPD78056F 78056FY Special Function Registers SFRs SFR Addressing 256 x 8 bits des General Registers A Register Addressing 32 x 8 bits Y Short Direct Addressing
440. pare register CRO01 set as compare register c 16 bit timer output control register TOCO OSPT OSPE TOC04 LVSO LVRO TOCO1 TOEO co TOO Output Enabled Inversion of output on match of and CROO Specified TOO output F F initial value Inversion of output on match of and CRO1 One shot pulse output mode Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with one shot pulse output See the description of the respective control registers for details Caution Values in the following range should be set in CROO and CRO1 0000H lt CRO1 lt CROO lt FFFFH 206 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 34 Timing of One Shot Pulse Output Operation Using External Trigger with Rising Edge Specified Set 08H to TMCO TMO count start TMO Count Value 0000 XKX KN 2 Xo xu X v ez pues TIOO Pin Input INTTMO1 oo a INTTMOO TOO Pin Output __ a Caution The 16 bit timer register starts operation at the moment value other than 0 0 0 operation stop mode is set to 1 to TMCO3 respectively 207 CHAPTER 8 16 TIMER EVENT COUNTER 8 6 16 Bit Timer Event Counter Operating Precautions 1 2 3 Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be genera
441. pt mask flag register 1L emnes 484 503 Memory expansion mode 150 508 Oscillation mode selection register s sess nnne nre nnne nenne 159 Oscillation stabilization time select register 516 Pr ein dated 130 et Emm A eee 144 Port T3 nisu tute gr pae tutu ue NOU tute ete ust s 145 POIL cus inde vate tete aiuta du tus aces a ED E o peri Sn 132 nene ui tepida sd en e 133 PONS Vetere ht esce hat t e toad t f et tS tr de eec 137 medius 138 POM D mis E 139 PONG isch iced fue HERREN EB BM 140 xpo 142 APPENDIX D REGISTER INDEX PCC PMO PM12 PM13 PM1 2 5 PM6 7 PROH PROL PRIL PSW PUOH PUOL R RTBH RTBL RTPC RTPM RXB RXS S SAR SBIC SCS SFR SINT 5100 5101 SVA T TCLO TCL1 TCL2 TCL3 TMO TM1 TM2 TMCO TMC1 TMC2 TMS TOCO Processor clock control register eeeiesssieseeseeseeeseeeene 157 Port mode register ee ERU e ette ed Re ads eg EO S Ade d 130 146 Port mode register ine sen id euin eee ales 130 146 474 Port mode register 13 35 zi niet E dede ole 130 146 Portamode reglster Vix du
442. put ports they are used for control in external memory expansion mode P60 to P63 can drive LEDs directly The following operating modes can be specified bit wise 68 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 1 2 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 6 PM6 P60 to P63 are N ch open drain outputs Mask ROM version can contain pull up resistors with the mask option When P64 to P67 are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL Control mode These ports function as control signal output pins RD WR WAIT ASTB in external memory expansion mode When a pin is used as a control signal output the on chip pull up resistor is automatically disabled Caution When external wait is not used in external memory expansion mode P66 can be used as an input output port 3 2 8 P70 to P72 Port 7 This is a 3 bit input output port In addition to its use as an input output port it also has serial interface data input output and clock input output functions The following operating modes can be specified bit wise 1 2 Port mode Port 7 functions as a 3 bit input output port Bit wise specification as an input port or output port is possible by means of port mode register 7 PM7 When used as input ports on chip pull up resistors can be used b
443. quipment and medical equipment not specifically designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices is Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact an NEC sales representative in advance Anti radioactive design is not implemented in this product M7 96 5 Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electron
444. r 32 768 kHz 1 0 TCLO CLOE TCLOG TCLOS TCLO4 TCLOS TCLO2 TCLO1 TCLOO PCL Output Clock Selection MCS 1 fxx fx 5 0 MHz fx 2 2 5 MHz fxx 2 fx 2 2 5 MHz fx 2 1 25 MHz fxx 2 fx 2 1 25 MHz fx 2 625 kHz fxx 2 fx 2 625 kHz fx 2 313 kHz 2 fx 2 313 kHz fx 2 156 kHz fxx 2 fx 2 156 kHz fx 2 78 1 kHz 2 fx 2 78 1 kHz fx 2 39 1 kHz fxx 2 fx 2 39 1 kHz fx 2 19 5 kHz Setting prohibited 16 Bit Timer Register Count Clock Selection MCS 1 TIOO Valid edge specifiable 2fxx Setting prohibited fx 5 0 MHz bx fx 5 0 MHz fx 2 2 5 MHz fxx 2 fx 2 2 5 MHz fx 2 1 25 MHz fxx 2 fx 2 1 25 MHz fx 2 625 kHz Watch Timer Output INTTM3 Setting prohibited Cautions 1 The valid edge of pin TIOO POO INTPO is set with the external mode register 0 INTMO Also the frequency of the sampling clock is selected with the sampling clock selection register SCS When enabling PCL output set TCLOO to TCLO3 then set 1 in CLOE with a 1 bit memory manipulation instruction To read the count value when TIOO has been specified as the TMO count clock the value should be read from TMO not from 16 bit capture compare register 01 CRO1 When rewriting TCLO to other data stop the clock operation beforehand 255
445. r 3 TCL3 SIO SBO SDAO P25 Pin Function S ONote 3 Input SOO SB1 SDA1 P26 Pin Function 500 CMOS output SCKO SCL P27 Pin Function SCKO CMOS input output Note 4 x Note 4 x 2 wire serial mode or P25 CMOS input output SB1 SDA1 N ch open drain input output SCKO SCL N ch open drain input IC Bus Mode Note 4 Note 4 output SBO SDAO N ch open drain input output P26 CMOS x x input output Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition when CMDD 1 matches the slave address register SVA data in IPC bus mode Slave Address Comparison Result Flag Slave address register SVA not equal to serial I O shift register SIO0 0 data 1 Slave address register SVA equal to serial I O shift register SIOO 0 data Operation stopped Operation enabled Bit 6 is a read only bit 12 bus mode the clock frequency becomes 1 16 of that output TO2 Can be used as P25 CMOS input output when used only for transmission Can be used freely as port function To use the wake up function WUP 1 set the bit 5 SIC of the interrupt timing specify register SINT to 1 Do not execute an instruction that writes the serial I O shift register 0 S100 while WUP 1 6 When CSIEO 0
446. r D A converter analog output The following operating modes can be specified bit wise 1 Port mode These ports function as 2 bit input output ports They can be specified bit wise as input or output ports with port mode register 13 PM13 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register H PUOH 2 Control mode These ports allow D A converter analog output ANOO and ANO1 Caution When only either of the D A converter channels is used with AVrer1 gt the other pins that are not used as analog outputs must be set as follows Set PM13x bit of the port mode register 13 PM13 to 1 input mode and connect the pin to Vss Set PM13x bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low level from the pin 3 2 11 AVREFo A D converter reference voltage input pin When A D converter is not used connect this pin to Vss 3 2 12 AVREF1 D A converter reference voltage input pin When D A converter is not used connect this pin to 70 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 3 2 13 AVDD This is the analog power supply pin of the A D converter and the port s power supply pin Always use the same voltage as that of the Voo pin even when the A D converter is not used 3 2 14 AVss This is the ground potential pin for the A D converter and D A converter and the ground potential pin for
447. r clock select register 2 TCL2 This register sets the watchdog timer count clock TCL2 is set with 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the watchdog timer count clock TCL2 sets the watch timer count clock and buzzer output frequency 248 CHAPTER 11 WATCHDOG TIMER Symbol 7 6 5 Figure 11 2 Timer Clock Select Register 2 Format 4 3 2 1 0 TCOL22 TCL21 TCL20 TCL2 TCL27 TCL26 TCL25 TCL24 TCL21 After Reset 00H R W R W Watchdog Timer Count Clock Selection fx 2 625 kHz MCS 1 fx 2 313 kHz fx 2 313 kHz fx 2 156 kHz fx 2 156 kHz fx 2 78 1 kHz fx 2 78 1 kHz fx 2 39 1 kHz fx 2 39 1 kHz fx 2 19 5 kHz fx 2 19 5 kHz fx 2 9 8 kHz fx 2 9 8 kHz fx 2 4 9 kHz fxx 2 fx 2 2 4 kHz Watch Timer Count Clock Selection fx 2 1 2 kHz MCS 1 fx 2 39 1 kHz fx 29 19 5 kHz fxr 32 768 kHz TCL26 Buzzer Output Frequency Selection MCS 1 Buzzer output disable fxx 2 fx 2 9 8 kHz fx 2 4 9 kHz fxx 2 fx 2 4 9 kHz fx 2 2 4 kHz fxx 2 fx 2 2 4 kHz fx 2 1 2 kHz Caution When rewriting TCL2 to other data stop the timer operation beforehand Remarks 1 MCS Setting prohibited
448. r modes Operation stop mode e 3 wire serial I O mode SBI serial bus interface mode 2 wire serial I O mode Caution Do switch the operating mode 3 wire serial I O 2 wire serial l O SBI while operation of serial 1 2 3 286 interface channel 0 is enabled If switching the operation mode first terminate the serial operation then carry out switching Operation stop mode This mode is used when serial transfer is not carried out Power consumption can be reduced 3 wire serial mode MSB LSB first selectable RM This mode is used for 8 bit data transfer using three lines one each for serial clock SCKO serial output 500 and serial input SIO This mode enables simultaneous transmission reception and therefore reduces the data transfer processing time The start bit of transferred 8 bit data is switchable between MSB and LSB so that devices can be connected regardless of their start bit recognition This mode should be used when connecting with peripheral I O devices or display controllers that incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K series SBI serial bus interface mode MSB first This mode is used for 8 bit data transfer with two or more devices using two lines of serial clock SCKO and serial data bus SBO or SB1 The SBI mode is compatible with the NEC Serial Bus Format and sends and receives data distinguishing bet
449. r start instruction is executed When start condition is detected When stop condition is detected When CSIE0 0 When RESET input is applied SDAO SDA1 is set to low after the Set instruction execution ACKT 1 before the next SCL falling edge Used for generating an ACK signal by software if the 8 clock wait mode is selected Cleared to 0 if CSIE 0 when a transfer by the serial interface is started ACKE Acknowledge Signal Automatic Output ControlNete 2 Disabled with ACKT enabled Used when receiving data in the 8 clock wait mode or when transmitting data Note 3 Enabled After completion of transfer acknowledge signal is output in synchronization with the 9th falling edge of SCL clock automatically output when ACKE 1 However not automatically cleared to 0 after acknowl edge signal output Used for reception when the 9 clock wait mode is selected Clear Conditions ACKD 0 Setting Condition ACKD 1 When transfer start instruction is executed When acknowledge signal is detected at the rising When CSIEO 0 edge of SCL clock after completion of transfer When RESET input is applied tue Control of N ch Open Drain Output for Transmission IC Bus ModeNote 5 Output enabled transmission Output disabled reception Notes 1 Bits 2 3 and 6 RELD CMDD ACKD are read only bits 2 This setting must be performed prior to transfer start 3 In the 8 clock wait mode use ACKT for
450. rcuit Receive Shift Register RXS TxD SO2 p71 71 72 Transmit Shift Register TXS SIO2 EC gt INTSER Reception Control Circuit INTSR INTCSI2 ISRM ASCK SCK2 P72 Transmission Control Circuit SCK Output gt INTST Serial Operating Mode Register 2 to fxx 210 SCK MDL3 MDL2 MDL1 MDLO TPS3 TPS2 TPS1 TPSO Baud Rate Generator Control Register Internal Bus Note See Figure 19 2 for the baud rate generator configuration 435 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19 2 Baud Rate Generator Block Diagram CSIE2 J Transmit Clock Selector Receive Clock 1 2 Selector RXE Start Bit Detection 436 Y 5 Bit Counter Start Bit Sampling Clock ASCK SCK2 P72 Selector Match 2 MDLO to MDL3 to fxx 210 Selector 4 TPS0 to TPS3 SCK Selector Decoder 4 Match 5 Bit Counter iz TPSS3 TPS2 TPS1 TPSO MDL3 MDL2 MDL1 MDLO Baud Rate Generator Control Register Internal Bus CHAPTER 19 SERIAL INTERFACE CHANNEL 2 1 2 3 4 5 Transmit shift register TXS This register is used to set the transmit data The data written in TXS is transmitted
451. re expanded A D converter of the 44PD780924 was enhanced On chip inverter control circuit and UART EMI noise reduced version FIP drive LPD780208 The I O and FIP C D of the uPD78044F were enhanced Display output total 53 E 0780228 The I O and FIP C D of the 78044 were enhanced Display output total 48 f uPD78044H N ch open drain I O was added to the uPD78044F Display output total 34 Lu PD78044F Basic subseries for driving FIP Display output total 34 LCD drive 0780308 uPD780308Y SIO of the wPD78064 was enhanced ROM size and RAM size were expanded LPD78064B EMI noise reduced version of the L PD78064 078064 uPD78064Y Subseries for driving LCDs On chip UART IEBus supported LPD78098B EMI noise reduced version of the L PD78098 LPD78098 IEBus controller was added to the uPD78054 Meter control 1 LPD780973 On chip controller driver for driving automobile meters Note Under planning 53 CHAPTER 2 OUTLINE uPD78058FY SUBSERIES The differences between the major functions of each subseries are shown below es Function Control Remark Functions other than the serial interface are common with Subseries without the Y 54 uPD78078Y ROM Capacity 48 K to 60 K HPD78070AY Serial Interface 3 wire 2 wire I C 3 wire with automatic send receive function 3 wire UART HPD780018AY 48 K to 60 K 3 wire with automatic send receive function Time division 3 wire
452. re incorporated in slave devices Figure 17 15 Start Condition b Address The 7 bits following the start condition signal are defined as an address The 7 bit address data is output by the master device to specify a specific slave from among those connected to the bus line Each slave device on the bus line must therefore have a different address Therefore after a slave device detects the start condition it compares the 7 bit address data received and the data of the slave address register SVA After the comparison only the slave device in which the data are a match becomes the communication partner and subsequently performs communication with the master device until the master device sends a start condition or stop condition signal Figure 17 16 Address SCL 1 2 3 4 5 6 7 ow Address c Transfer direction specification The 1 bit that follows the 7 bit address data will be sent from the master device and it is defined as the transfer direction specification bit If this bit is 0 it is the master device which will send data to the slave If it is 1 it is the slave device which will send data to the master Figure 17 17 Transfer Direction Specification SCL 1 2 3 4 5 6 7 8 A A A A A A Transfer direction specification 365 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES d Acknowledge signal ACK The acknowledge signal indicates that the transferred serial data has definitely b
453. re serial I O 12 bus Inter IC Bus Use possible UART Asynchronous serial interface None None Use possible 337 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 17 1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes Operation stop mode 3 wire serial I O mode 2 wire serial I O mode 12 Inter IC bus mode Caution Do not switch the operating mode 3 wire serial I O 2 wire serial I O I2C bus while operation of 1 2 3 338 serial interface channel 0 is enabled The operation mode should be switched after stopping the serial operation Operation stop mode This mode is used when serial transfer is not carried out Power consumption can be reduced 3 wire serial I O mode MSB LSB first selectable This mode is used for 8 bit data transfer using three lines one each for serial clock SCKO serial output SOO and serial input SIO This mode enables simultaneous transmission reception and therefore reduces the data transfer processing time The start bit of transferred 8 bit data is switchable between MSB and LSB so that devices can be connected regardless of their start bit recognition This mode should be used when connecting with peripheral I O devices or display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K series 2 w
454. rement Operation with Free Running Counter with Both Edges Specified Figure 8 21 X A Do X V V TMO Count Value D3 CRO01 Captured Value TIO1 Pin Input INTP1 OVFO 196 CHAPTER 8 16 TIMER EVENT COUNTER 3 Pulse width measurement with free running counter and two capture registers When the 16 bit timer register TMO is operated in free running mode see register settings in Figure 8 22 it is possible to measure the pulse width of the signal input to the TIOO POO pin When the edge specified by bits 2 and ES10 and ES11 of external interrupt mode register 0 INTMO is input to the TIOO POO pin the value of is taken into 16 bit capture compare register 01 CRO1 and an external interrupt request signal INTPO is set Also on the inverse edge input of that of the capture operation into CRO1 the value of is taken into 16 bit capture compare register 00 CROO Either of two edge specifications can be selected rising or falling as the valid edges for the TIOO POO pin by means of bits 2 and 3 ES10 and ES11 of INTMO For TIOO POO pin valid edge detection sampling is performed at the interval selected by means of the sampling clock selection register SCS and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Caution If the valid edge of TIOO POO is specified to be
455. resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Port 5 can drive LEDs directly Alternate function includes address bus function in external memory expansion mode RESET input sets port 5 to input mode Figure 6 12 shows a block diagram of port 5 Figure 6 12 P50 to P57 Block Diagram AVop WRruo i dnm a eran RD gt o 2 2 Wheonr 4 c g Output Latch 5 a P50 to P57 WRem PM50 to 57 e PN e zi PUO Pull up resistor option register PM Port mode register RD Port 5 read signal WR Port 5 write signal 139 CHAPTER 6 PORT FUNCTIONS 6 2 8 Port 6 Port 6 is an 8 bit input output port with output latch P60 to P67 pins can specify the input mode output mode in 1 bit units with the port mode register 6 PM6 This port has functions related to pull up resistors as shown below These functions depending on whether the higher 4 bits or lower 4 bits of a port are used and whether the mask ROM model or PROM model is used Table 6 4 Pull up Resistor of Port 6 Higher 4 Bits P64 through P67 pins Lower 4 bits P60 through P63 pins Mask ROM Pull up resistor can be connected in 1 bit units by On chip pull up resistor can be connected in 4 bit version mask option units PUO6 PROM version Pull up resistor is not connected PUOS Bit 6 of pull up resistor option regis
456. rface Channel 0 78058 Subseries uPD78058FY Subseries 3 wire serial I O mode 2 wire serial I O mode SBI serialbus interface mode I C bus mode Y Supported Not supported Conventions Data significance Higher digits on the left and lower digits on the right Active low representations Xxx overscore over pin or signal names Note Footnotes for item marked with Note in the text Caution Information requiring particular attention Remarks Supplementary information Numeral representations Binary or xxxxB Decimal xxxx Hexadecimal xxxxH 10 Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such e Related Documents for u PD78058F Subseries Document Name uPD78056F 78058F Data Sheet Document No Japanese U11795J English U11795E uPD78P058F Data Sheet U11796J U11796E uPD78058F A Data Sheet U12325J U12325E uPD78058F 78058FY Subseries User s Manual U12068J This manual 78K 0 Series User s Manual Instruction U12326J U12326E 78K 0 Series Instruction Table U10903J 78K 0 Series Instruction Set U10904J 78K 0 Series Application Note Basic III Related Documents for uPD78058FY Subseries Document Name uPD78056FY 78058FY Data Sheet U10182J U10182E Do
457. rial transfer automatically stops and the interrupt request flag CSIIFO is set CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 16 4 3 SBI mode operation SBI Serial Bus Interface is a high speed serial interface in compliance with the NEC serial bus format SBI uses a single master device and employs the clocked serial I O format with the addition of a bus configuration function This function enables devices to communicate using only two lines Thus when making up a serial bus with two or more microcontrollers and peripheral ICs the number of ports to be used and the number of wires on the board can be decreased The master device outputs three kinds of data to slave devices on the serial data bus addresses to select a device to be communicated with commands to instruct the selected device and data which is actually required The slave device can identify the received data into address command or data by hardware Through this function the application program which controls serial interface channel 0 can be simplified The SBI function is incorporated into various devices including 75X XL Series and 78K Series Figure 16 10 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI and peripheral ICs are used In SBI the SBO SB1 serial data bus pin is an open drain output pin and therefore the serial data bus line behaves in the same way as the wired OR configurati
458. ritten to ADM again during A D conversion the converter suspends its A D conversion operation and waits for a new external trigger signal to be input When the external trigger input signal is reinput A D conversion is carried out from the beginning If data with CS set to 0 is written to ADM during A D conversion the A D conversion operation stops immediately Figure 14 7 A D Conversion by Hardware Start INTP3 ADM Rewrite ADM Rewrite CS 1 TRG 1 CS 1 TRG 1 Standby Standby Standby A D Conversion ANIn ANIn State ANIn State ANIm ANIm ANIm kolek V EET YN Pee INTAD Remarks 1 n 0 1 7 2 m 0 1 7 272 CHAPTER 14 A D CONVERTER 2 A D conversion operation in software start When bit 6 TRG and bit 7 CS of A D converter mode register ADM are set to 0 and 1 respectively the A D conversion starts on the voltage applied to the analog input pins specified with bits 1 to ADM1 to ADMS of ADM Upon termination of the A D conversion the conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is generated After one A D conversion operation is started and terminated the next A D conversion operation starts immediately The A D conversion operation con tinues repeatedly until new data is written to ADM If data with CS set to 1 is written to ADM again during A D conversion the converter suspends its A
459. rohibited 267 CHAPTER 14 A D CONVERTER 3 External interrupt mode register 1 INTM1 This register sets the valid edge for INTP3 to INTP6 INTM1 is set with an 8 bit memory manipulation instruction RESET input sets INTM1 to OOH Figure 14 4 External Interrupt Mode Register 1 Format After Symbol 7 6 5 4 3 2 1 0 Address Reset R W INTM1 ES71 ES70 ES61 ES60 ES51 ES50 ES41 ES40 FFEDH 00H R W ES41 ES40 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges 268 CHAPTER 14 A D CONVERTER 14 4 A D Converter Operations 14 4 1 Basic operations of A D converter 1 Set the number of analog input channels with A D converter input select register ADIS 2 From among the analog input channels set with ADIS select one channel for A D conversion with A D converter mode register ADM 3 The voltage input to the selected analog input channel is sampled by the sample amp hold circuit 4 Sampling for the specified period of time sets the sample amp hold circuit to the hold state so that the circuit holds the input analog voltage until ter
460. rol register TMCO TMC03 TMCO2 TMCO1 OVFO LILENREBEGENENEEE b Capture compare control register 0 CRCO Clear amp start on match of TMO and CROO CRC02 CRCO01 CRCOO e Te CROO set as compare register c 16 bit timer output control register TOCO OSPT OSPE TOCO4 LVSO LVRO TOCO1 TOEO Ex TOO Output Enabled Inversion of output on match of and CROO Specified TOO output F F initial value No inversion of output on match of and CRO1 One shot pulse output disabled Remark 0 1 Setting O or 1 allows another function to be used simultaneously with square wave output See the description of the respective control registers for details CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 30 Square Wave Output Operation Timing cutcok LJ LJ LI LJ LI LI LI LJ LI LI LI LW vu TWO Count Value X 0000 y 0007 X X N1 X N Y ooo Koo 0002K X NIX N Yoo TOO Pin Output Table 8 7 16 Bit Timer Event Count Square Wave Output Ranges INTTMOO Minimum Pulse Width Maximum Pulse Width Resolution MCS 1 MCS 0 MCS 1 MCS 0 2 x TIOO input cycle 216 x TIOO input cycle TIOO input edge cycle 2 x 1 fx 216 x 1 fx 1 fx 400 ns 13 1 ms 200 ns 2 x 1 fx 2 x 1 fx 216 x 1 fx 217 x 1 fx 1 fx 2 x 1 fx 400 ns 800 ns 13 1 ms 26 2 ms 200 ns 400 ns 22 x 4 fx 23 x 1 fx 217 x 1 fx 218 x 1 fx
461. rporated into them which it is only possible to write to once The differences between PROM products uPD78P058F and 78P058FY and ROM products uPD78056F 78056FY 78058F and 78058FY are shown in Table 26 1 Table 26 1 Differences Between uPD78P058F 78P058FY and Mask ROM Versions 78 58 78P058FY Mask ROM version Internal ROM structure One time PROM Mask ROM Internal ROM capacity 60 Kbytes UPD78056F 78056FY 48 Kbytes HPD78058F 78058FY 60 Kbytes Internal expansion RAM capacity 1024 bytes uPD78056F 78056FY None HPD78058F 78058FY 1024 bytes Changing internal ROM and internal high EnableNote 1 Disable speed RAM capacities with memory size switching register Changing of internal expansion RAM EnableNote 2 Disable capacity by internal expansion RAM size switching register IC pin None Available VPP pin Available None Pins P60 to P63 pull resistance on chip None Available mask option Electrical characteristics Refer to the separate Data Sheet Notes 1 Through the RESET input the internal PROM capacity becomes 60 Kbytes and the internal high speed RAM capacity becomes 1024 bytes 2 Through the RESET input the internal expansion RAM capacity becomes 1024 bytes Caution In PROM products and mask ROM products the noise resistance and noise emissions differ In the process from prototype production to volume production if the switchover from PROM product to ROM product is s
462. rrection address registers 0 and 1 CORADO CORAD1 Control register Correction control register CORCN Figure 25 1 shows a block diagram of the ROM correction Figure 25 1 Block Diagram of ROM Correction Program counter PC Correction address register n CORADn Correction branch request signal BR 7FDH CORENn CORSTn Correction control register Internal bus Remark 0 1 527 CHAPTER 25 ROM CORRECTION 1 Correction address registers 0 and 1 CORADO CORAD1 These registers set the start address correction address of the instruction s to be corrected in the mask ROM The ROM correction corrects two places max of the program Addresses are set to two registers CORADO and CORAD1 If only one place needs to be corrected set the address to either of the registers CORADO and CORAD1 are set with a 16 bit memory manipulation instruction RESET input sets CORADO and CORAD1 to 0000H Figure 25 2 Correction Address Registers 0 and 1 Format After Symbol 15 0 Address Reset R W Cautions 1 Set the CORADO and CORAD 1 when bit 1 CORENO and bit 3 COREN1 of the correction control register CORCN see Figure 25 3 are 0 2 Only addresses where operation codes are stored can be set in CORADO and CORAD1 3 Do not set the following addresses to CORADO and CORAD1 Address value in table area of table reference instruction CALLT instruction 0040H to 007FH Address value in v
463. ruction Cautions 1 The actual runaway detection time may be shorter than the set time by a maximum of 0 5 2 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 11 4 Watchdog Timer Runaway Detection Time TCL20 Runaway Detection Time MCS 1 MCS 0 211 x 1 fxx 211 x 1 fx 410 us 212 x 1 fx 819 us 212 x 1 fxx 212 x 1 fx 819 us 213 x 1 fx 1 64 ms 213 x 1 fxx 213 x 1 fx 1 64 ms 214 x 1 fx 3 28 ms 214 x 1 fxx 214 x 1 fx 3 28 ms 215 x 1 fx 6 55 ms 215 x 1 fxx 215 x 1 fx 216 x 1 fx 13 1 ms 216 x 1 fxx 216 x 1 fx 13 1 ms 217 x 1 fx 26 2 ms 217 x 1 fxx 6 55 ms 217 x 1 fx 26 2 ms 218 x 1 fx 52 4 ms 219 x 1 fxx Remarks 1 fxx oO PLN 219 x 1 fx 104 9 ms Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency MCS Bit 0 of oscillation mode selection register OSMS TCL20 to TCL22 Bits O to 2 of timer clock select register 2 TCL2 Figures in parentheses apply to operation with fx 2 5 0 MHz 220 x 1 fx 209 7 ms 251 CHAPTER 11 WATCHDOG TIMER 11 4 2 Interval timer operation The watchdog timer operates as an interval timer which generate interrupt request repeatedly at an interval of the preset count value when bit 4 WDTM4 of the watchdog timer mode reg
464. ruction Group Mnemonic Operands saddr bit addr16 Operation PC lt PC 3 jdisp8 if saddr bit 1 sfr bit addr16 PC amp PC 4 jdisp8 if sfr bit 1 A bit addr16 PC amp PC 3 jdisp8 if A bit 1 PSW bit addr16 PC amp PC 3 jdisp8 if PSW bit 1 HL bit addr16 PC lt PC 3 jdisp8 if HL bit 1 saddr bit addr16 PC lt PC 4 jdisp8 if saddr bit 0 sfr bit addr16 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 PC lt PC 3 jdisp8 if A bit 0 PSW bit addr16 PC PC 4 jdisp8 if PSW bit 0 HL bit addr16 w lt PC 3 jdisp8 if HL bit 0 saddr bit addr16 PC amp PC 4 jdisp8 if saddr bit 1 then reset saddr bit sfr bit addr16 PC PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr16 PC amp PC 3 jdisp8 if A bit 1 then reset A bit PSW bit addr16 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit HL bit addr16 PC c PC 3 jdisp8 if HL bit 1 then reset HL bit B addr16 B lt B 1 then PC PC 2 jdisp8 if Bz 0 C addr16 C C 1 then PC PC 2 jdisp8 if C 0 saddr addr16 saddr saddr 1 then PC amp PC 3 jdisp8 if saddr 0 RBn RBS1 0 lt n No Operation IE 1 Enable Interrupt IE O Disable In
465. s ADCR T eas Sei Ss S ng 1 1 3 2 5 3 507 254 509 255 511 1 512 256 512 256 512 256 512 256 512 256 512 Input Voltage AVnero 271 CHAPTER 14 A D CONVERTER 14 4 3 A D converter operating mode Select 1 analog input channel from ANIO ANI7 by the A D converter input select register ADIS and the A D converter mode register ADM and begin A D conversion The following two methods are used for starting an A D conversion operation Hardware start Conversion is started by trigger input INTP3 Software start Conversion is started by setting ADM The A D conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is simultaneously generated 1 A D conversion by hardware start When bit 6 TRG and bit 7 CS of A D converter mode register ADM are set to 1 the A D conversion standby state is set When the external trigger signal INTP3 is input the A D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 ADM1 to ADM3 of ADM Upon termination of the A D conversion the conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is generated After one A D conversion operation is started and terminated another operation is not started until a new external trigger signal is input If data with CS set to 1 is w
466. s SFR Addressing 256 x 8 bits sro ca cs age ce ce peewee gst Trip iU General Registers A Register Addressing 32 x 8 bits Short Direct Addressing Internal High speed RAM 1024 x 8 bits FE20H 2 5 5 Y FE1FH FBOOH FAFFH Reserved FAEOH Direct Addressing Internal Buffer RAM 32 x 8 bits Register Indirect FACOH Addressing FABFH Reserved Based Addressing F800H F7FFH Based Indexed Addressing Internal Expansion RAM 1024 x 8 bits F400H F3FFH Reserved FOOOH EFFFH Internal PROM 61440 x 8 bits 0000H Y Note When internal PROM size is 60 Kbytes the area FOOOH to F3FFH cannot be used F000H to F3FFH can be used as external memory by setting the internal PROM size to less than 56 Kbytes by the memory size switching register IMS CHAPTER 5 CPU ARCHITECTURE 5 2 Processor Registers The uPD78058F and 78058FY Subseries units incorporate the following processor registers 5 2 1 Control registers The control registers control the program sequence statuses and stack memory The control registers consist of a program counter PC a program status word PSW and a stack pointer SP 1 Program counter PC The program counter is a 16 bit register which holds the address information of the next program to be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register con
467. s mode should be used to check whether the data was written correctly Program inhibit mode The program inhibit mode is used when the OE pins Vee pins and pins DO to D7 of multiple uPD78P058Fs or 78P058FYs are connected in parallel and any one of these devices must be written to The page write mode or byte write mode described above is used to perform a write At this time the write is not performed on the device which has the PGM pin driven high 541 CHAPTER 26 uPD78P058F 78PO58FY 26 3 2 PROM write procedure Figure 26 3 Page Program Mode Flowchart Start Address G Voo 6 5 V Vep 12 5 V Address Address 1 No Latch Address Address 1 Latch Address Address 1 Latch Address Address 1 Latch G Start address N Last address of program 1 X X 1 0 1 ms program pulse Verify 4 Bytes lt gt Pass Address N 542 Yes Vop 4 5 to 5 All bytes verified All Pass End of write Fail 5 V Fail Yes Defective product CHAPTER 26 078 58 78P058FY A2 to A16 AO A1 DO to D7 Vep Vep Voo Vop4 1 5 Voo Vit Vin PGM Vit Vit Figure 26 4 Page Program Mode Timing Page Page Data Latch Program Verify E AE Hi Z 0000 Dat
468. s received assuming that there is no parity bit Since there is no parity bit a parity error is not generated CHAPTER 19 SERIAL INTERFACE CHANNEL 2 c Transmission A transmit operation is started by writing transmit data to the transmit shift register TXS The start bit parity bit and stop bit s are added automatically When the transmit operation starts the data in the transmit shift register TXS is shifted out and when the transmit shift register TXS is empty a transmission completion interrupt request INTST is generated Figure 19 8 Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing a Stop bit length 1 START INTST b Stop bit length 2 PES AT AT AAT AT Ae vo START INTST Caution Rewriting of the asynchronous serial interface mode register ASIM should not be performed during a transmit operation If rewriting of the ASIM register is performed during transmission subsequent transmit operations may not be possible the normal state is restored by RESET input It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt request INTST or the interrupt request flag STIF set by the INTST 457 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 d Reception When bit 6 RXE of the asynchronous serial interface mode register ASIM is set 1 a receive operation is enabled and sampling of the R
469. s with the memory expansion mode register MM When P40 to P47 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with pull up resistor option register L PUOL The test input flag KRIF can be set to 1 by detecting falling edges Alternate functions include address data bus function in external memory expansion mode RESET input sets port 4 to input mode Figures 6 10 and 6 11 show a block diagram of port 4 and block diagram of falling edge detection circuit respectively Figure 6 10 P40 to P47 Block Diagram AVop e WReuo PUO4 P ch RD e 2 m 5 oO c 3 Output Latch i a m P40 to P47 PA7 AD7 WRwmu ie Wer PUO Pull up resistor option register MM Memory expansion mode register RD Port 4 read signal WR Port 4 write signal Figure 6 11 Block Diagram of Falling Edge Detection Circuit P40 7 P41 P42 9 Falling Edge P43 Q P44 __ P45 9 P46 G Standby Release Signal P47 138 CHAPTER 6 PORT FUNCTIONS 6 2 7 Port 5 Port 5 is an 8 bit input output port with output latch P50 to P57 pins can specify the input mode output mode in 1 bit units with the port mode register 5 PM5 When P50 to P57 pins are used as input ports an on chip pull up
470. sary Set bit 5 ATE of serial operation mode register 1 CSIM1 at 1 Set bit 2 STRB of the auto data send and receive control register ADTC at 1 Normally busy control and strobe control are used simultaneously as handshake signals In this case together with output of the strobe signal from pin STB P23 pin BUSY P24 can be sampled and sending or receiving can wait while the busy signal is being input If strobe control is not carried out pin P23 STB can be used as a normal I O port Operation timing when busy and strobe control are used is shown in Figure 18 21 Furthermore if strobe control is used the interrupt request flag CSIIF1 set when sending or receiving ends is set after the strobe signal is output CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 21 Operation Timings When Using Busy amp Strobe Control Option BUSYO 0 eck aoe aes LJ Mo eae 1 1 sor OOOO COME RIO OOOO 1 1 __ jpzjpejpsjpeypaypeiotiDo STB ig A EE CSIIF1 1 1 Busy Input Release 1 1 per t Busy Input Valid TRF Caution When TRF is cleared the SO1 pin becomes low level Remarks CSIIF1 Interrupt request flag TRF Bit 3 of the auto data send and receive control register ADTC 427 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 c Bit Slippage Detection Function Through the Busy Signal During an auto send and rece
471. servicing all maskable interrupts enable Interrupt request Acknowledge Enable Disable Disable Enable CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 4 Interrupt Servicing Operations 21 4 4 Non maskable interrupt acknowledge operation A non maskable interrupt request is received without condition even when in the interrupt request reception prohibited state It does not undergo interrupt priority control and has highest priority over all other interrupts If a non maskable interrupt request is acknowledged the acknowledged interrupt is saved in the program status word PSW and then program counter PC the IE and ISP flags are reset to 0 and the vector table contents are loaded into PC and branched A new non maskable interrupt request generated during execution of a non maskable interrupt service program is received after the execution of the non maskable interrupt service program that is currently processing is completed after the RETI command is executed and 1 command of the main routine is executed If a new non maskable interrupt request is generated twice or more during non maskable interrupt service program execution only one non maskable interrupt request is acknowledged after termination of the non maskable interrupt service program execution The flowchart from the time a non maskable interrupt request is generated until it is received is shown in Figure 21 10 the non maskable interrupt request acknowledge timi
472. ses apply to operating at fx 5 0 MHz 516 CHAPTER 23 STANDBY FUNCTION 23 2 Standby Function Operations 23 2 1 HALT mode 1 HALT mode set and operating status The HALT mode is set by executing the HALT instruction It can be set with the main system clock or the subsystem clock The operating status in the HALT mode is described below Table 23 1 HALT Mode Operating Status Setting of HALT Mode On Execution of HALT Instruction during Main On Execution of HALT Instruction during System Clock Operation Subsystem Clock Operation Without subsystem With subsystem When main system clock When main system clockNote 1 clockNote 1 continues oscillation clock stops oscillation Clock generator Both main system and subsystem clocks can be oscillated Clock supply to the CPU stops CPU Operation stops Port output latch Status before HALT mode setting is held 16 bit timer event counter Operable Operable when watch timer output is selected as count clock fxr is selected as count clock of watch timer or when TIOO is selected 8 bit timer event counter Operable Operable when TI1 or TI2 is selected as count clock Watch timer Operable when fx 27 is Operable Operable when fx is selected as count clock selected as count clock Watchdog timer Operable Operation stops A D converter Operable Operation stops D A converter Operable Real time output port Operable Ser
473. shot pulse to be generated at the falling edge of SCKO after 8 bit data transfer It can be positioned anywhere and can be synchronized with any clock SCKO After 8 bit data transmission the transmitter checks whether the receiver has returned the acknowledge signal If the acknowledge signal is not returned for the preset period of time after data transmission it can be judged that data reception has not been carried out correctly 311 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES f Busy signal BUSY and ready signal READY The BUSY signal is intended to report to the master device that the slave device is preparing for data transmission reception The READY signal is intended to report to the master device that the slave device is ready for data transmission reception Figure 16 19 BUSY and READY Signals SCKO le lef LILI LI LI r SBO SB1 BUSY READY In SBI the slave device notifies the master device of the busy state by setting SBO SB1 line to the low level The BUSY signal output follows the acknowledge signal output from the master or slave device It is set reset at the falling edge of SCKO When the BUSY signal is reset the master device automatically terminates the output of SCKO serial clock When the BUSY signal is reset and the READY signal is set the master device can start the next transfer Caution In SBI after specifying reset of BUSY the BUSY signal is output until the
474. sion mode 2 Besides setting port 4 input output MM also sets the wait count and external expansion area 150 CHAPTER 6 PORT FUNCTIONS 4 Key return mode register KRM This register sets enabling disabling of standby function release by a key return signal falling edge detection of port 4 KRM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets KRM to 02H Figure 6 22 Key Return Mode Register Format After Symbol 7 6 5 4 3 2 0 Address Reset R W ees o o KRIF Key Return Signal Detection Flag 0 Not Detected 1 Detected Falling edge detection of port 4 KRMK Standby Mode Control by Key Return Signal 0 Standby mode release enabled 1 Standby mode release disabled Caution When falling edge detection of port4 is used KRIF should be cleared to 0 not cleared to 0 automatically 151 CHAPTER 6 PORT FUNCTIONS 6 4 Port Function Operations Port operations differ depending on whether the input or output mode is set as shown below 6 4 1 Writing to input output port 1 2 Output mode A value is written to the output latch by a transfer instruction and the output latch contents are output from the pin Once data is written to the output latch it is retained until data is written to the output latch again Input mode A value is written to the output latch by a transfer instruction but since the output buffer is OFF
475. size switching register IXS 44 CHAPTER 1 OUTLINE uPD78058F SUBSERIES Part Number Buzzer output uPD78056F uPD78058F uPD78P058F 1 2 kHz 2 4 kHz 4 9 KHz 9 8 kHz main system clock at 5 0 MHz operation Vectored Maskable interrupt Internal 13 External 7 sources Non maskable Internal 1 Software 1 Test input Internal 1 External 1 Supply voltage Voo 2 7 to 6 0 V Operating ambient temperature Ta 40 to 85 C Package 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm 80 pin plastic TQFP Fine pitch 12 x 12 mm uPD78058F only 1 9 Differences Between the PD78058F and uPD78058F A Table 1 1 Differences Between the PD78058F and PD78058F A Part Number Quality grade uPD78058F Standard uPD78058F A Special Package 80 pin Plastic QFP 14 x 14 mm Resin thickness 2 7 mm 80 pin Plastic QFP 14 x 14 mm Resin thickness 1 4 mm 80 pin Plastic TQFP Fine Pitch 12 x 12 mm 80 pin Plastic QFP 14 x 14 mm Resin thickness 2 7 mm 45 CHAPTER 1 OUTLINE uPD78058F SUBSERIES 1 10 Mask Options There are mask options in the mask ROM versions uPD78056F 78058F By specifying the mask option when ordering you can have the pull up resistors shown in Table 1 2 incorporated on chip If a mask option is use
476. so even if interrupt reception is permitted there are some cases where multiple interrupts are not permitted but that is controlled by the interrupts priority order There are two types of interrupt priority order the default priority order and the programmable priority order but control of multiple interrupts is controlled by programmable priority order In the interrupt permitted state if an interrupt request is generated with the same level as or a higher level of priority order than the interrupt currently being processed it is received as a multiple interrupt If an interrupt request with a lower priority order than the interrupt currently being processed is generated itis not received as a multiple interrupt An interrupt request generated while interrupts are prohibited or when multiple interrupts are not permitted due to the interrupt request s low priority order is held Then when the interrupt processing currently in progress is completed the interrupt request is received after 1 main processing command has been executed Furthermore multiple interrupts are not permitted during processing of a nonmaskable interrupt Table 21 4 shows interrupt requests which can be multiple interrupts and Figure 21 16 shows a multiple interrupt example 497 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 498 Table 21 4 Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing Interrupt Currently Being Processed Non maska
477. ss the internal high speed RAM area only Description example In the case of PUSH DE Operation code 10110101 124 CHAPTER 6 PORT FUNCTIONS 6 1 Port Functions The uPD78058F and 78058FY Subseries units incorporate two input ports and sixty seven input output ports Figure 6 1 shows the port configuration Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serve as on chip hardware input output pins Figure 6 1 Port Types Port 5 Port 0 Port 6 Port 1 Port 7 Port 2 Port 12 Port 3 Port 13 P37 P40 to P47 Port 4 125 CHAPTER 6 PORT FUNCTIONS Table 6 1 Port Functions uPD78058F Subseries 1 2 Pin Name Function Alternate Function POO Port 0 Input only INTPO TIOO P01 8 bit input output port Input output mode can be specified INTP1 TIO1 P02 bit wise INTP2 If used as an input port an on chip pull up INTP3 P04 resistor can be used by software INTP4 P05 INTP5 P06 INTP6 P07 Input only XT1 P10 to P17 Port 1 ANIO to ANI7 8 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software P20 Port 2 SH P21 8 bit input output port SO1 P22 Input output mode can be specified bit wise SCK1 P23 If used as an input port an on chip pull up resistor can be used by software STB P24 BUSY
478. st 2 processed b If two non maskable interrupt requests are generated during non maskable interrupt servicing program execution NMI Request 1 eee NMI Request 1 executed NMI Request 2 NMI Request 2 held NMI Request 3 held 1 Instruction Execution NMI Request 3 Held NMI Request 2 processed NMI Request 3 is not received Even if more than 2 NMI requests are generated they can only be received 1 time 493 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 4 2 Maskable Interrupt request reception For a maskable interrupt request the interrupt request flag is set at 1 and if the mask Mk flag of that interrupt is cleared 0 it is possible for it to be received A vector interrupt request is received if an interrupt enable state exists when the IE flag is set at 1 However if a high priority order interrupt is being processed when the ISP flag is reset 0 an interrupt request which has a low priority order specified for it is not received The timing from the time when a maskable interrupt request is generated until the interrupt is processed is shown in Table 21 3 For the timing of interrupt request reception see Figures 21 14 and 21 15 Table 21 3 Times from Maskable Interrupt Request Generation to Interrupt Service P inn Time Maximum Timorese When xxPRx 0 7 clocks 32 clocks When xxPRx 1 8 clocks 33 clocks N
479. stem clock frequency or fx 2 2 fx Main system clock oscillation frequency 3 fxr Subsystem clock oscillation frequency 4 TIOO 16 bit timer event counter input pin 5 TMO 16 bit timer register 6 MCS Bit 0 of oscillation mode selection register OSMS 7 Figures in parentheses apply to operation with fx 5 0 MHz of fxr 32 768 kHz 2 16 bit timer mode control register TMCO 180 This register sets the 16 bit timer operating mode the 16 bit timer register clear mode and output timing and detects an overflow TMCO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMCO value to 00H Caution The 16 bit timer register starts operation at the moment a value other than 0 0 0 operation stop mode is set in TMCO1 to TMCOS3 respectively Set 0 0 0 in TMCO1 to TMCOS to stop the operation CHAPTER 8 16 TIMER EVENT COUNTER Symbol 7 6 Figure 8 4 16 Bit Timer Mode Control Register Format 5 4 3 2 1 o o pwesspueszuen oves Address FF48H 00H After Reset R W R W OVFO 16 Bit Timer Register Overflow Detection Overflow not detected Overflow detected TMC02 TMCO1 Operating Mode Clear Mode Selection Operation stop TMO cleared to 0 TOO Output Timing Selection No change Interrupt Generation Not Generated PWM mode free running PWM pulse output Free running mode Match between TMO and CROO or match between
480. synchronization with 1 Master y execution of slave device on the A7 to A KO af f REL yu ToO tpi PME 5 0 SB1 EEBGEEG EE instruction for CSIIFO set rising serial bus and CMD signals REL CMD data write to edge of 9th clock 5100 serial of SCKO Nete 1 7 M transfer start 8 bit data to be transferred 1 2 7 8 instruction Nete 2 1 d in synchronization with 2 Instructions and Master SCKO after output of only messages to the 79 90 CMD signal without REL 5 0 SB1 i ca Xu X slave device CMD signal output 8 bit data to be transferred 3 P SCKO 1 2 7 8 Numeric values to be Data Master in synchronization with processed with slave D7 to DO slave SCKO without output of a ee REL and CMD signals SBO SB1 EE ue 00 M Notes 1 When WUP 0 CSIIFO is set at the rising edge of the 9th clock of SCKO When WUP 1 an address is received Only when the address matches the slave address register SVA value CSIIFO is set ifthe address does not coincide with the value of SVA RELD is cleared 2 In BUSY state transfer starts after the READY state is set 531935905 48S08Zdd 0 TANNVHO 39VJH3LlNI 1ViH3S 91 H3ldVHO CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 5 Pin configuration The serial clock pin SCKO and serial data bus pin SBO SB1 have the following configurations a SCKO Serial c
481. system Emulation probe and is designed for 80 pin plastic QFP GC 3B9 GC 8BT types EV 9200GC 80 This conversion socket connects the EP 78230GC R to the target system Conversion socket board designed to mount a 80 pin plastic QFP GC 3B9 GC 8BT types Refer to Figure B 2 NP EP 78054GK R This probe is used to connect the in circuit emulator to the target system Emulation probe and is designed for 80 pin plastic TOFP GK BE9 type TGK 080SDW This conversion adapter connects the EP 78054GK R to the target system Conversion adapter board designed to mount a 80 pin plastic TQFP GK BE9 type Refer to Figure B 3 Notes 1 Under development 2 Maintenance product Remarks 1 TGK 080SDW is a product of TOKYO ELETECH CORPORATION Inquiries Daimaru Kougyou Co Ltd Phone 03 3820 7112 Tokyo Electronic Component Division 06 244 6672 Osaka Electronic Component Division 2 EV 9200GC 80 is sold in sets of five units 3 TGK 080SDW is sold on a unit basis 573 APPENDIX B DEVELOPMENT TOOLS B 3 2 Software 1 2 SM78K0 This simulator can debug target system at C source level or assembler level while System simulator simulating operation of target system on host machine SM78KO0 runs on Windows By using SM78KO logic and performance of application can be verified without in circuit emulator independently of hardware development so that development efficiency and software quality can be improved This simulator
482. t Symbol 7 6 Address After Reset R W 5 4 3 2 1 0 PM3n P3n Pin Input Output Mode Selection n 0 to 7 Output mode output buffer ON Input mode output buffer OFF 184 CHAPTER 8 16 BIT TIMER EVENT COUNTER 6 External interrupt mode register 0 INTMO This register is used to set INTPO to INTP2 valid edges INTMO is set with an 8 bit memory manipulation instruction RESET input sets INTMO value to 00H Symbol 7 6 Figure 8 8 External Interrupt Mode Register 0 Format Address 5 4 3 2 1 0 me EssTEssesnTEsm en w e e After Reset 00H R W R W ES11 ES10 INTPO Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Caution Before setting the valid edge of the INTPO TIOO POO pin stop the timer operation by clearing bits 1 through 3 TMC01 through TMCO3 of the 16 bit timer mode control register TMCO to 0 0 0 185 CHAPTER 8 16 TIMER EVENT COUNTER 7 Sampling clock select register SCS This register sets clocks which undergo clock sampling of valid edges to be input to INTPO When remote controlled reception is carried out using INTPO digital noise is removed with sampling clock SCS is set with an 8 bit
483. t communication with the master device continues until a release instruction is received from the master device Figure 16 15 Slave Selection with Address Slave 1 Not Selected Slave 2 Address Transmission Slave 2 Selected Slave 3 Not Selected Slave 4 Not Selected TUI 309 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 310 d Command and data The master device transmits commands to and transmits receives data to from the slave device selected by address transmission Figure 16 16 Commands SCKO 1f lef la la sf lef 7 le SBO SB1 Command Signal Command Figure 16 17 Data SCKO 1 lol laf 4 Is lel Iz la SB0 S81 07 X05 X bs X SX 2K DIK bo wo Data 8 bit data following a command signal is defined as command data 8 bit data without command signal is defined as data Command and data operation procedures are allowed to determine by user according to communications specifications CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES e Acknowledge signal ACK The acknowledge signal is used to check serial data reception between transmitter and receiver Figure 16 18 Acknowledge Signal When output in synchronization with 11th clock SCKO SCKO ler Hor 11 When output in synchronization with 9th clock SCKO PLL ees Remark The dotted line indicates READY status The acknowledge signal is one
484. t TMCO1 to Match INTTMO1 3 1 gt INTPO 16 Bit Capture Com Register 01 CRO OSPTOSP TOC04 LVSO LVRO TOCO1 TOEO 16 Bit Timer Output 1 TMCO2 TMC01 OVFO 16 Bit Timer Mode pare TCLO6 TCLO5 TCLO4 Timer Clock Selection CRCO0 2 Control Register Control Register Register 0 Internal Bus Notes 1 Edge detection circuit 2 The configuration of the 16 bit timer event counter output control circuit is shown in Figure 8 2 175 CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 2 16 Bit Timer Event Counter Output Control Circuit Block Diagram PWM Pulse Output Control Circuit CRC02 INTTMO1 CRCO0 i 8 INTTMOO 8 g o o Ed 2 ge i Detection One Shot Pulse Circuit i Output Control Circuit P30 Output External Interrupt 16 Bit Timer Output 16 Bit Timer Mode Port Mod Mode Register 0 Control Register Control Register Register 3 y Internal Bus Remark The circuitry enclosed by the dotted line is the output control circuit 176 CHAPTER 8 16 TIMER EVENT COUNTER 1 Capture compare register 00 CROO CRO0 is a 16 bit register which has the functions of both a capture register and a compare register Whether
485. t clock input to the timer a capture trigger signal input and crystal connection for subsystem oscillation The following operating modes can be specified bit wise 1 Port mode POO and 07 function as input only ports and P01 to P06 function as input output ports P01 to P06 can be specified for input or output ports bit wise with a port mode register 0 When they are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL 2 Control mode In this mode these ports function as an external interrupt request input an external count clock input to the timer and crystal connection for subsystem clock oscillation a INTPO to INTP6 INTPO to INTP6 are external interrupt request input pins which can specify valid edges rising edge falling edge and both rising and falling edges INTPO or INTP1 becomes a 16 bit timer event counter capture trigger signal input pin with a valid edge input b TIOO Pin for external count clock input to 16 bit timer event counter c TIO1 Pin for capture trigger signal to capture register CROO of 16 bit timer event counter d XT1 Crystal connect pin for subsystem clock oscillation 83 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 4 2 2 P10 to P17 Port 1 These are 8 bit input output ports Besides serving as input output ports they function as an A D converter analog input The following operating modes can be
486. t enabled transmission Output disabled reception Notes 1 Setting should be performed before transfer 2 If 8 clock wait mode is selected the acknowledge signal at reception time must be output using ACKT 3 The busy mode can be canceled by start of serial interface transfer or reception of address signal However the BSYE flag is not cleared to 0 4 When using the wake up function be sure to set BSYE to 1 Remark CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 350 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 4 Interrupt timing specify register SINT This register sets the bus release interrupt and address mask functions and displays the SCKO SCL pin level status SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Figure 17 6 Interrupt Timing Specify Register Format 1 2 Symbol 7 1 Address After Reset R W sor o vac rum mh m R W WAT1 WATO Wait and Interrupt Control Generates interrupt service request at rising edge of 8th SCKO clock cycle keeping clock output in high impedance Setting prohibited Used 1 C bus mode 8 clock wait Generates interrupt service request at rising edge of 8th SCKO clock cycle In the case of master device makes SCL output low to enter wait state after 8 clock pulses are output In the case of slave device makes SCL output low to request wait stat
487. t mode because the P27 pin must be in the output mode in the 12C bus mode This instruction clears the output latch of the P25 pin to 0 because the output latch of the P25 pin must be set to 0 in the I2C bus mode This instruction sets the P25 pin in the output mode because the P25 pin must be in the output mode in the 12C bus mode Remark Bit 0 of serial bus interface control register SBIC CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 17 4 7 SCKO SCL P27 pin output manipulation The SCKO SCL P27 pin can execute static output via software in addition to outputting the normal serial clock The value of serial clocks can also be arbitrarily set by software the SIO SBO SDAO and SOO SB1 SDAt pins are controlled with the RELT and CMDT bits of serial bus interface control register SBIC The SCKO SCL P27 pin output should be manipulated as described below 1 In 3 wire serial I O mode and 2 wire serial I O mode The output level of the SCKO SCL P27 pin is manipulated by the P27 output latch 1 Set the serial operating mode register 0 CSIMO SCKO pin is set in the output mode and serial opera tion is enabled SCKO 1 while serial transfer is stopped 2 Manipulate the content of the P27 output latch by executing the bit manipulation instruction Figure 17 27 SCKO SCL P27 Pin Configuration Manipulated by bit manipulation instruction P27 output latch A a SCKO 1 while transfer is stoppe
488. t ports they are used for control in external memory expansion mode P60 to P63 can drive LEDs directly The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 6 PM6 P60 to P63 are N ch open drain outputs Mask ROM version can contain pull up resistors with the mask option When P64 to P67 are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as control signal output pins RD WR WAIT ASTB in external memory expansion mode When a pin is used as a control signal output the on chip pull up resistor is automatically disabled Caution When external wait is not used in external memory expansion mode P66 can be used as an input output port 86 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 4 2 8 P70 to P72 Port 7 This is a 3 bit input output port In addition to its use as an input output port it also has serial interface data input output and clock input output functions The following operating modes can be specified bit wise 1 2 Port mode Port 7 functions as a 3 bit input output port Bit wise specification as an input port or output port is possible by means of port mode register 7 PM7 When used as input ports on chip pull up resistors can be used by definin
489. t request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the slave address register SVA data in SBI mode Slave address register SVA not equal to serial I O shift register SIO0 0 data Slave address register SVA equal to serial I O shift register SIOO 0 data Operation stopped Operation enabled Notes 1 Bit 6 COI is a read only bit 2 Can be used as a port 3 To use the wake up function WUP 1 clear the bit 5 SIC of the interrupt timing specify register SINT to 0 4 When CSIEO 0 COI becomes 0 5 In the SBI mode the operation of serial interface channel 0 should be stopped after WUP is cleared to 0 If WUP is not cleared to 0 P25 is fixed to high level and it may become impossible to use it as a normal port Remark x don t care Port Mode Register PXX Port Output Latch 313 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES b Serial bus interface control register SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H The shaded area is used in the SBI mode symbol gt Address After Reset R W SBIC BSYE ACKT CMDD RELD CMDT RELT FF61H 00H R WNete R W Used for bus release signal output When RELT 1 SOO latch is set to 1 After SOO latch
490. t serve for both input and output Thus in the case of a device for reception write FFH to SIOO in advance except when address reception is carried out by setting bit 5 WUP of CSIMO to 1 In the SBI mode the busy state can be cleared by writing data to SIOO In this case bit 7 BSYE of the serial bus interface control register SBIC is not cleared to 0 RESET input makes SIOO undefined Slave address register SVA This is an 8 bit register to set the slave address value for connection of a slave device to the serial bus This register is not used in the 3 wire serial I O mode SVA is set with an 8 bit memory manipulation instruction The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the slave address output from the master device and the SVA value are compared with an address comparator If they match the slave device has been selected In that case bit 6 COI of serial operating mode register 0 CSIMO becomes 1 Also by setting bit 4 SVAM of the interrupt timing instruction register SINT at 1 the address can be compared with the higher order 7 bits with the LSB being masked If no match is detected when the address is received bit 2 RELD of the serial bus interface control register SBIC is cleared to 0 Furthermore when in the SBI mode the wake up function can be used by setting bit 5 WUP of CSIMO at 1 In this case the interrupt r
491. t slippage during sending and receiving a Busy control option Busy control is a function which causes the master device s serial transmission to wait when the slave device outputs a busy signal to the master device and maintain the wait state while that busy signal is active When the busy control option is used the conditions shown below are necessary Bit 5 ATE of serial operation mode register 1 CSIM1 should be set at 1 Bit 1 BUSY1 of the auto data send and receive control register ADTC should be set at 1 The system configuration between the master device and slave device in cases where the busy control option is used is shown in Figure 18 18 Figure 18 18 System Configuration When the Busy Control Option Is Used Master Device uPD78058F 78058FY Subseries Slave Device The master device inputs the busy signal output by the slave device to pin BUSY P24 In sync with the fall of the serial clock the master device samples the input busy signal Even if the busy signal becomes active during sending or receiving of 8 bit data the wait does not apply If the busy signal becomes active at the rise of the serial clock 2 clock cycles after sending or receiving of 8 bit data ends the busy input first becomes effective at that point and thereafter sending or receiving of data waits during the period that the busy signal is active The busy signal s active level is set in bit 0 BUSYO of ADTC BUSYO 0 Active High
492. t the rising edge of SCKO Upon termination of 8 bit transfer the shift register operation stops automatically and the interrupt request flag CSIIFO is set Figure 17 11 2 Wire Serial I O Mode Timings SCKO 1 2 3 4 5 6 7 8 Q End of Transfer Transfer Start at the Falling Edge of SCKO Pin SBO or SB1 specified in the serial data bus is an N ch open drain input and output so it is necessary to pull it up externally It is also necessary to set the N ch open drain output in the high impedance state when CSIIFO receiving data so write FFH in SIOO in advance The SBO or SB1 pin generates the SOO latch status and thus the SBO or SB1 pin output status can be manipulated by setting bit 0 RELT and bit 1 CMDT of serial bus interface control register SBIC However do not carry out this manipulation during serial transfer Control the SCKO pin output level in the output mode internal system clock mode by manipulating the P27 output latch refer to 17 4 7 SCKO SCL P27 pin output manipulation 361 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 3 Other signals Figure 17 12 shows RELT and CMDT operations Figure 17 12 RELT and CMDT Operations 800 Latch RELT CMDT 4 5 362 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIOO when the following two conditions are satisfied Serial interface channel 0 operation control bit
493. t the same time 1 Watchdog timer mode An inadvertent program loop runaway is detected Upon detection of the runaway a non maskable interrupt request or RESET can be generated Table 11 1 Watchdog Timer Runaway Detection Times Runaway Detection Time 211 x 1 fxx 21 x 1 fx 410 us 21 x 1 fx 819 us 212 x 4 fxx 21 x 1 fx 819 us 213 x 1 fx 1 64 ms 213 x 4 fxx 213 x 1 fx 1 64 ms 214 x 1 fx 3 28 ms 214 x 4 fxx 214 x 1 fx 3 28 ms 215 x 1 fx 6 55 ms 215 x 4 fxx 216 x 4 fxx 216 x 1 fx 13 1 ms 217 x 1 fx 26 2 ms 217 x 4 fxx 217 x 1 fx 26 2 ms 218 x 1 fx 52 4 ms 219 x 4 fxx Remarks 1 fxx 2 fx 215 x 1 fx 6 55 ms 219 x 1 104 9 ms Main system clock frequency fx or fx 2 Main system clock oscillation frequency 216 x 1 fx 13 1 ms 220 x 1 fx 209 7 ms 3 MCS Bit 0 of oscillation mode selection register OSMS 4 Figures in parentheses apply to operation with fx 2 5 0 MHz 245 CHAPTER 11 WATCHDOG TIMER 2 Interval timer mode Interrupt requests are generated at the preset time intervals Table 11 2 Interval Times Interval Time 211 x 1 fxx 211 x 1 fx 410 us 21 x 1 fx 819 us 212 x 4 fxx 21 x 1 fx 819 us 213 x 1 fx 1 64 ms 213 x 4 fxx 213 x 1 fx 1 64 ms 214 x 1 fx 3 28 ms 214 x 4 fxx 2
494. ta to ADTP while the automatic transmit receive function is activated Serial clock counter This counter counts the serial clocks to be output and input during transmission reception to check whether 8 bit data has been transmitted received CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18 3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1 Timer clock select register 3 TCL3 Serial operating mode register 1 CSIM1 Automatic data transmit receive control register ADTC Automatic data transmit receive interval specify register ADTI 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 1 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88H Remark Besides setting the serial clock of serial interface channel 1 TCL3 sets the serial clock of serial interface channel 0 391 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol TCL36 TCL35 Figure 18 2 Timer Clock Select Register 3 Format 7 6 5 4 3 2 1 0 Address After Reset R W TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H 88H R W Serial Interface Channel 1 Serial Clock Selection MCS 1 fxx 2 Setting prohibited MCS 0 fx 22 1 25 MHz fxx 22 fx 2 1 25 MHz fx 23 625 kHz fxx 28 fx 23 625 kHz fx 24 313 kHz fxx 24 fx 24 313 kHz fx 25 156 kHz
495. ta transmit receive control register ADTC 412 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6 byte transmission reception ARLD 0 RE 1 in basic transmit receive mode internal buffer RAM operates i Before transmission reception See Figure 18 10 a After any data has been written to serial I O shift register 1 SIO1 start trigger this data is not transferred transmit data 1 T1 is transferred from the internal buffer RAM to SIO1 When transmission of the first byte is completed the receive data 1 R1 is transferred from SIO1 to the internal buffer RAM and automatic data transmit receive address pointer ADTP is decremented Then transmit data 2 T2 is transferred from the internal buffer RAM to 5101 ii 4th byte transmission reception point See Figure 18 10 b Transmission reception of the third byte is completed and transmit data 4 T4 is transferred from the internal buffer RAM to SIO1 When transmission of the fourth byte is completed the receive data 4 R4 is transferred from SIO1 to the internal buffer RAM and ADTP is decremented iii Completion of transmission reception See Figure 18 10 c When transmission of the sixth byte is completed the receive data 6 R6 is transferred from SIO1 to the internal buffer RAM and the interrupt request flag CSIIF1 is set INTCSI1 generation Figure 18 10 Internal Buffer RAM Operation in 6 Byte Transmission Reception in Basic Transmit Receive Mode 1 2
496. tch timer mode control register TMC2 is set to 0 the 5 bit counter is cleared and the count operation stops For simultaneous operation of the interval timer zero second start can be achieved by setting TMC22 to 0 maximum error 26 2 ms when operated at fxx 5 0 MHz 10 4 2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the preset count value The interval time can be selected with bits 4 to 6 TMC24 to TMC26 of the watch timer mode control register TMC2 Table 10 3 Interval Timer Interval Time When operated at When operated at When operated at Tame fxx 5 0 MHz fxx 4 19 MHz fxt 32 768 kHz 24 x 1 fw 25 x 1 fw 26 x 1 fw 27 x 1 fw 28 x 1 fw 0 29 x 1 fw Other than above Setting prohibited fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency fxr Subsystem clock oscillation frequency fw Watch timer clock frequency fxx 2 or TMC24 to TMC26 Bits 4 to 6 of watch timer mode control register TMC2 244 11 1 Watchdog Timer Functions CHAPTER 11 The watchdog timer has the following functions Watchdog timer nterval timer WATCHDOG TIMER Caution Selectthe watchdog timer mode or the interval timer mode with the watchdog timer mode register WDTM The watchdog timer and interval timer cannot be used a
497. tched into SIO1 at the rising edge of SCK1 Upon termination of 8 bit transfer the SIO1 operation stops automatically and the interrupt request flag CSIIF1 is set Figure 18 6 3 Wire Serial I O Mode Timings SCK1 SI SO1 CSIIF1 End of Transfer te Transfer Start at the Falling Edge of SCK1 SIO1 Write Caution SO1 pin becomes low level by SIO1 write 3 MSB LSB switching as the start bit The 3 wire serial I O mode enables to select transfer to start from MSB or LSB Figure 18 7 shows the configuration of the serial I O shift register 1 SIO1 and internal bus As shown i figure MSB LSB can be read written in reverse form nthe MSB LSB switching as the start bit can be specified with bit 6 DIR of the serial operating mode register 1 CSIM1 401 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 4 402 Figure 18 7 Circuit of Switching in Transfer Bit Order Internal Bus 4 Dey ee an ewe ver eeu pce MEAE gei e use eo LSB first MSB first Read Write Gate Read Write Gate SO1 Latch SI Serial Shift Register 1 SIO1 a 501 SCK1 Start bit switching is realized by switching the bit order write to SIO1 The SIO1 shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to SIO1
498. ted after timer start This is because the 16 bit timer register TMO is started asynchronously with the count pulse Figure 8 35 16 Bit Timer Register Start Timing Count Pulse A vues N TMO Count Value 0000H 0001H 0002H 0003H 0004H Timer Start 16 bit compare register setting Set a value other than 0000H to the 16 bit capture compare register 00 CROO Thus when using the 16 bit capture compare register as event counter one pulse count operation cannot be carried out Operation after compare register change during timer count operation If the value after the 16 bit capture compare register CROO is changed is smaller than that of the 16 bit timer register TMO TMO continues counting overflows and then restarts counting from 0 Thus if the value M after CROO change is smaller than that N before change it is necessary to restart the timer after changing CROO Figure 8 36 Timings After Change of Compare Register during Timer Count Operation x CROO N X M TMO Count Value X x X 4 FFFFH 0000H 0001H 0002H 208 Remark N gt X gt M CHAPTER 8 16 BIT TIMER EVENT COUNTER 4 Capture register data retention timings If the valid edge of the TIOO POO pin is input during 16 bit capture compare register 01 CRO1 read CRO1 holds data without carrying out capture operation However the interrupt request flag PIFO is set upon detection of the valid edge
499. tents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 5 7 Program Counter Format 2 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB RETI and POP PSW instructions RESET input sets the PSW to 02H Figure 5 8 Program Status Word Format 7 0 103 CHAPTER 5 CPU ARCHITECTURE 104 a b c d e f Interrupt enable flag IE This flag controls the interrupt request acknowledge operations of the CPU When IE 0 all interrupts except non maskable interrupt requests are disabled DI status When IE 1 interrupts are enabled El status At this time acknowledgment of interrupts is controlled with an inservice priority flag ISP an interrupt mask flag for various interrupt sources and a priority specify flag This flag is reset 0 when the DI command is executed or when an interrupt request is acknowledged and is set 1 when the El command is executed Zero flag Z When the operation result is zero this flag is set 1 It is reset 0 in all other cases Register bank select flags RBSO and RBS1 These are 2 bit flags to select one of the four register banks
500. ter OSMS 266 CHAPTER 14 A D CONVERTER 2 A D converter input select register ADIS This register determines whether the ANIO P10 to ANI7 P17 pins should be used for analog input channels or ports Pins other than those selected as analog input can be used as input output ports ADIS is set with an 8 bit memory manipulation instruction RESET input sets ADIS to 00H Cautions 1 Set the analog input channel in the following order 1 Set the number of analog input channels with ADIS 2 Using A D converter mode register ADM select one channel to undergo A D conversion from among the channels set for analog input with ADIS 2 No internal pull up resistor can be used to the channels set for analog input with ADIS irrespective of the value of bit 1 PUO1 of the pull up resistor option register L PUOL Figure 14 3 A D Converter Input Select Register Format After Reset R W Symbol 7 6 3 2 1 0 Address 5 4 ADIS aiss ADIS2 ADIS1 ADISO FF84H 00H R W ADIS2 ADIS1 ADISO Number of Analog Input Channel Selection No analog input channel P10 to P17 1 channel ANIO P11 to P17 2 channel ANIO ANI1 P12 to P17 3 channel ANIO to ANI2 P13 to P17 4 channel ANIO to ANI3 P14 to P17 5 channel ANIO to ANI4 P15 to P17 6 channel ANIO to ANI5 P16 P17 7 channel ANIO to ANI6 P17 8 channel ANIO to ANI7 Other than above Setting p
501. ter SVA when WUP 1 or if the stop condition is detected 371 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 5 Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDAO SDA1 are shown below a SCL Pin for serial clock input output dual function pin 1 Master N ch open drain output 2 Slave Schmitt input b SDAO SDA1 Serial data input output dual function pin Uses N ch open drain output and Schmitt input buffers for both master and slave devices Note that pull up resistors are required to connect to both serial clock line and serial data bus line because open drain buffers are used for the serial clock pin SCL and the serial data bus pin SDAO or SDA1 on the I C bus Figure 17 21 Pin Configuration AVop Slave Devices Master Device SCL SCL AVopb Clock Output 77 AVss Clock Output AVss z7 Clock Input Clock Input SDAO SDA1 SDAO SDA1 Data Output 77 AVss Data Output l AVss 77 Data Input Data Input Caution It is necessary for the N ch open drain output to be set in the high impedance state when receiving data so set 1 in bit 7 BSYE of the serial bus interface control register SBIC in advance and write FFH in serial I O shift register 0 SIOO However when the wake up function is used when bit 5 WUP of serial opera
502. ter L PUOL Pins P60 to P63 can drive LEDs directly Pins P64 to P67 also serve as the control signal output in external memory expansion mode RESET input sets port 6 to input mode Figures 6 13 and 6 14 show block diagrams of port 6 Cautions 1 When external wait is not used in external memory expansion mode P66 can be used as an input output port 2 The value of the low level input leakage current flowing to the P60 through P63 pins differ depending on the following conditions Mask ROM version When pull up resistor is connected always 3 uA MAX When pull up resistor is not connected For duration of 1 5 clock no wait when instruction to read port 6 P6 and port mode register 6 PM6 is executed 200 uA MAX Other than above 3 uA MAX PROM version For duration of 1 5 clock no wait when instruction to read port 6 P6 and port mode register 6 PM6 is executed 200 uA MAX Other than above 3 uA MAX 140 CHAPTER 6 PORT FUNCTIONS Figure 6 13 P60 to P63 Block Diagram 4 AVop a RD i Mask Option Resistor Mask ROM products only PROM versions have pull up resistor eo 2 a D Output Latch P60 to P63 P60 to P63 WRem NNNM PM60 to PM63 2 PM Port mode register RD Port 6 read signal WR Port 6 write signal Figure 6 14 P64 to P67 Block Diagram AVop e WReu
503. ter mode register DAM There are two types of modes for the D A converter as follows 1 Normal mode Outputs an analog voltage signal immediately after the D A conversion 2 Real time output mode Outputs an analog voltage signal synchronously with the output trigger after the D A conversion Since a sine wave can be generated in this mode it is useful for an MSK modem for cordless telephone sets 279 CHAPTER 15 D A CONVERTER 15 2 D A Converter Configuration The D A converter consists of the following hardware Table 15 1 D A Converter Configuration D A conversion value set register 0 DACSO D A conversion value set register 1 DACS1 Control register D A converter mode register DAM Figure 15 1 D A Converter Block Diagram Internal Bus D A Conversion Value Set Register 1 INTTM2 m D DACS1 DACSO Write Ed S D A Conversion Value DACS1 Write Set Register 0 INTTM1 I DACSO AVreF1 ANO1 P131 AVss ANOO P130 Selector DAMS5 DACE 1 DACEO D A Converter Mode Register Internal Bus 280 CHAPTER 15 D A CONVERTER 1 D A conversion value set register 0 1 DACSO DACS1 DACSO and DACS1 are registers where values are set for determining the analog voltage output respectively to pins ANOO and ANO1 DACSO an
504. terface serial data input P25 SBO SDAO P20 P70 RxD Output Serial interface serial data output P26 SB1 SDA1 P21 P71 TxD Serial interface serial data input output P25 SIO0 SDAO P26 SO0 SDA1 P25 SI0 SBO P26 SO0 SB1 Serial interface serial clock input output P27 SCL P22 P72 ASCK P27 SCKO Output Serial interface automatic transmit receive strobe output P23 Input Serial interface automatic transmit receive busy input P24 Input Asynchronous serial interface serial data input P70 SI2 Output Asynchronous serial interface serial data output P71 SO2 Input Asynchronous serial interface serial clock input P72 SCK2 Input External count clock input to 16 bit timer TMO Capture trigger signal input to capture register CROO External count clock input to 8 bit timer TM1 External count clock input to 8 bit timer TM2 POO INTPO PO1 INTP1 P33 P34 TO2 Output 16 bit timer TMO output also used for 14 bit PWM output 8 bit timer TM1 output 8 bit timer TM2 output P30 P31 P32 PCL Output Clock output for main system clock and subsystem clock trimming P35 BUZ Output Buzzer output P36 RTPO to RTP7 Output 80 Real time output port outputting data in synchronization with trigger P120 to P127 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 2 Non port pins 2 2
505. terrupt Set HALT Mode Notes 1 When the internal high speed RAM area is accessed or instruction with no data access Set STOP Mode 2 When an area except the internal high speed RAM area is accessed Remarks 1 One instruction clock is the length of 1 clock cycle of the CPU clock fceu selected by the processor clock control register PCC 2 This clock cycle applies to internal ROM program 559 CHAPTER 27 INSTRUCTION SET 27 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ 560 CHAPTER 27 INSTRUCTION SET Second Operand First Operand laddr16 HL byte HL B HL C addr16 HL byte HL B HL C X C Note Exceptr A 561 CHAPTER 27 INSTRUCTION SET 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW Second Operand laddri6 First Operand Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand sfr bit saddr bit PSW bit HL bit addr16 First Operand saddr bit 562 CHAPTER 27 INSTRUCTION SET 4 Call instructions branch instructions CALL
506. test input flag KRIF can be set to 1 by detecting a falling edge The following operating mode can be specified in 8 bit units 1 Port mode These ports function as 8 bit input output ports They can be specified in 8 bit units for input or output ports by using the memory expansion mode register MM When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as low order address data bus pins ADO to AD7 in external memory expansion mode When pins are used as an address data bus the on chip pull up resistor is automatically disabled 4 2 6 P50 to P57 Port 5 These are 8 bit input output ports Besides serving as input output ports they function as an address bus Port 5 can drive LEDs directly The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input output ports with port mode register 5 PM5 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as high order address bus pins A8 to A15 in external memory expansion mode When pins are used as an address bus the on chip pull up resistor is automatically disabled 4 2 7 P60 to P67 Port 6 These are 8 bit input output ports Besides serving as input outpu
507. the low level when the SCKO line is at the high level without serial clock output This signal is output by the master device Figure 16 13 Command Signal SCKO H The command signal indicates that from this point the master will send a command to the slave however command signals following bus release signals indicate that an address will be sent The slave has incorporated the hardware for detecting command signals Caution When the SCKO line is high level and the SBO SB1 changes from high level to low level this is recognized as a command signal Therefore if there are shifts in the bus change timing due to influences such as the board capacity this may be judged to be a command signal even though data is being sent Thus much care is requiring in wiring CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES c Address An address is 8 bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device Figure 16 14 Addresses SCKO 1 2 3 4 5 6 7 8 0 SB1 Address Bus Release Signal Command Signal 8 bit data following bus release and command signals is defined as an address In the slave device this condition is detected by hardware and whether or not 8 bit data matches the own specification number slave address is checked by hardware If the 8 bit data matches the slave address the slave device has been selected After tha
508. the P36 output latch to 0 3 Set bit 6 PM36 of port mode register 3 to 0 Set to output mode Caution Buzzer output cannot be used when setting P36 output latch to 1 13 2 Buzzer Output Control Circuit Configuration The buzzer output control circuit consists of the following hardware Table 13 1 Buzzer Output Control Circuit Configuration i Timer clock select register 2 TCL2 Control register Port mode register 3 PM3 Figure 13 1 Buzzer Output Control Circuit Block Diagram fxx 29 fxx 2 fu2 gt BUZ P36 Selector PM36 Port Mode Register 3 P36 Output Latch Internal Bus 1 TCL27 TCL26 TCL25 Timer Clock Select Register 2 257 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13 3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function Timer clock select register 2 TCL2 Port mode register 3 PM3 1 Timer clock select register 2 TCL2 This register sets the buzzer output frequency TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the buzzer output frequency TCL2 sets the watch timer count clock and the watchdog timer count clock 258 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT Symbol 7 6 3 2 1 0 TCL2 TCL27 TCL26 TCL25 TCL24 TCL22TCL21 TCL20 TCL21 Figur
509. the RA78K 0 ID78K0 NS ID78K0 and SM78KO are used R W Indicates whether the corresponding special function register can be read or written R W Read write enable R Read only W Write only Manipulatable bit units indicates bit units 1 8 or 16 bits in which the register can be manipulated indicates that the register cannot be manipulated in the indicated bit units After reset Indicates each register status upon RESET input 108 CHAPTER 5 CPU ARCHITECTURE Table 5 3 Special Function Register List 1 3 Manipulatable Bit Unit Address Special Function Register SFR Name After Reset 1 bit 8 bits 16 bits LN PortO Port1 Port2 Port3 Port4 Port5 Undefined Port6 Port7 Port12 Port13 Capture compare register 00 Undefined Capture compare register 01 16 bit timer register Compare register 10 Undefined Compare register 20 8 bit timer register 1 8 bit timer register 2 Serial I O shift register 0 Undefined Serial I O shift register 1 A D conversion result register Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 Port mode register 5 Port mode register 6 Port mode register 7 Port mode
510. the pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined except for the manipulated bit 6 4 2 Reading from input output port 1 2 152 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change Input mode The pin status is read by a transfer instruction The output latch contents do not change CHAPTER 6 PORT FUNCTIONS 6 4 3 Operations on input output port 1 Output mode An operation is performed on the output latch contents and the result is written to the output latch The output latch contents are output from the pins Once data is written to the output latch it is retained until data is written to the output latch again 2 Input mode The output latch contents are undefined but since the output buffer is OFF the pin status does not change Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined even for
511. the port Even when the A D converter and D A converter are not used always use the same potential as that of the Vss pin 3 2 15 RESET This is a low level active system reset input pin 3 2 16 X1 and X2 Crystal resonator connect pins for main system clock oscillation For external clock supply input it to X1 and its inverted signal to X2 3 2 17 XT1 and XT2 Crystal resonator connect pins for subsystem clock oscillation For external clock supply input it to XT1 and its inverted signal to XT2 3 2 18 VoD Positive power supply Except the port 3 2 19 Vss Ground potential pin Except the port 3 2 20 Vpr PROM versions only High voltage apply pin for PROM programming mode setting and program write verify When in the normal operating mode connect directly to Vss 71 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 3 2 21 IC Mask ROM version only The IC Internally Connected pin is provided to set the test mode to check the uPD78058F Subseries at delivery Connect it directly to the Vss with the shortest possible wire in the normal operating mode When a voltage difference is produced between the IC pin and Vss pin because the wiring between those two pins is too long or an external noise is input to the IC pin the user s program may not run normally O Connect IC pins to Vss pins directly As short as possible 72 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 3 3 Input output Circuits and Recommende
512. ther than above fxx 2 fx 3 MCS Setting prohibited Main system clock frequency fx or fx 2 Main system clock oscillation frequency Bit 0 of oscillation mode selection register OSMS 4 Figures in parentheses apply to operation with fx 2 5 0 MHz Caution When rewriting TCL3 to other data stop the serial transfer operation beforehand CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 2 Serial operating mode register 0 CSIMO This register sets serial interface channel 0 serial clock operating mode operation enable stop wake up function and displays the address comparator match signal CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Caution Do not switch the operating mode 3 wire serial I O 2 wire serial l O I2C bus while operation of serial interface channel 0 is enabled The operation mode should be switched after stopping the serial operation 347 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Symbol Figure 17 4 Serial Operating Mode Register 0 Format D 4 Address After Reset R W ome oe cor vur on a mem mem R W Serial Interface Channel 0 Clock Selection Input Clock to SCKO SCL pin from off chip 8 bit timer register 2 TM2 output Note Note 3 1 Note 3 x Operation Mode 3 wire serial mode Start Bit Clock specified with bits 0 to 3 of timer clock select registe
513. tion HALT mode hold RESET input Reset processing Remark x Don t care 519 CHAPTER 23 STANDBY FUNCTION 23 2 2 STOP mode 1 STOP mode set and operating status The STOP mode is set by executing the STOP instruction It can be set only with the main system clock Cautions 1 When the STOP mode is set the X2 pin is internally connected to Von viaa pull up resistor to minimize the leakage current at the crystal oscillator Thus do notuse the STOP mode in a system where an external clock is used for the main system clock 2 Because the interrupt request signal is used to clear the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the standby mode is immediately cleared if set Thus the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction After the wait set using the oscillation stabilization time select register OSTS the operating mode is set The operating status in the STOP mode is described below Table 23 3 STOP Mode Operating Status Sting at STOF Mode With Subsystem Clock Without Subsystem Clock Clock generator Only main system clock stops oscillation CPU Operation stops Port output latch Status before STOP mode setting is held 16 bit timer event counter Operable when watch timer output is Operation stops selected as count clock fxr is selected as count clock of watch ti
514. tion ADO to 07 Input Output Low order address data bus when expanding external memory P40 to P47 A8 to A15 Output High order address bus when expanding external memory P50 to P57 Output Strobe signal output for read operation from external memory P64 Strobe signal output for write operation to external memory Input Wait insertion when accessing external memory Output Strobe output externally latching address information output to ports 4 5 to access external memory Input A D converter analog input P10 to P17 Output D A converter analog output P130 P131 AVntro Input A D converter reference voltage input AVntr Input D A converter reference voltage input AVop 2m A D converter analog power supply Common with the port power supply AVss Ground potential common with the port s ground potential of the A D converter and D A converter RESET System reset input Crystal connection for main system clock oscillation Crystal connection for subsystem clock osicllation Positive power supply Except the port High voltage application for program write verify Connect directly to Vss in the normal operation mode Ground potential Except the port Internally connected Connect directly to Vss Cautions 1 The AVpp pin is used common as the power supply for the A D converter and port If this device is used in application fields
515. tion mode register 0 CSIMO is set do not write FFH in SIOO before reception Even if FFH is not written in SIOO the N ch open drain output is always in the high impedance state 6 Address match detection method 372 In the 12C mode the master can select a specific slave device by sending slave address data CSIIFO is set if the slave address transmitted by the master coincides with the value set to the slave address register SVA when a slave device address has a slave register SVA and the wake up function specify bit WUP 1 CSIIFO is also set when the stop condition is detected When using the wake up function set SIC to 1 Caution sure to set the WUP bit to 1 before the master device sends slave address data to slave devices Each slave device recognizes whether the slave device is selected or not by master device by comparing the content of the SVA register which is in each slave device and the slave address data which is sent by master device immediately after the start condition signal Only if the WUP bit has been set to 1 when they match the slave device generates INTCSIO signal CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 7 8 9 Error detection In the IC bus mode transmission error detection can be performed by the following methods because the serial bus SDAO SDA1 status during transmission is also taken into the serial I O shift register 0 SIOO register of the transmi
516. tions 1 When 1 is set in RUN so that the watchdog timer is cleared the actual overflow time is up to 0 5 shorter than the time set by timer clock select register 2 TCL2 2 To use watchdog timer modes 1 and 2 make sure that the interrupt request flag TMIF4 is 0 and then set WDTM4 to 1 If WDTM4 is set to 1 when TMIF4 is 1 the non maskable interrupt request occurs regardless of the contents of WDTM3 Remark Don t care CHAPTER 11 WATCHDOG TIMER 11 4 Watchdog Timer Operations 11 4 1 Watchdog timer operation When bit 4 WDTMA of the watchdog timer mode register WDTM is set to 1 the watchdog timer is operated to detect any runaway The watchdog timer count clock runaway detection time interval can be selected with bits 0 to 2 TCL20 to TCL22 of the timer clock select register 2 TCL2 Watchdog timer starts by setting bit 7 RUN of WDTM to 1 After the watchdog timer is started set RUN to 1 within the set runaway detection time interval The watchdog timer can be cleared and counting is started by setting RUN to 1 If RUN is not set to 1 and the runaway detection time is past system reset or a non maskable interrupt request is generated according to the WDTM bit 3 WDTM3 value By setting RUN to 1 the watchdog timer can be cleared The watchdog timer continues operating in the HALT mode but it stops in the STOP mode Thus set RUN to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP inst
517. tions have been satisfied The serial interface channel 0 operation control bit CSIEO 1 After an 8 bit serial transfer the internal serial clock is stopped or SCL is low Cautions 1 Be sure to set CSIEO to 1 before writing data in SIOO Setting CSIEO to 1 after writing data in SIOO does not initiate transfer operation 2 Itis necessary for the N ch open drain output to be set in the high impedance state when receiving data so set 1 in bit 7 BSYE of the serial bus interface control register SBIC in advance and write FFH in serial I O shift register 0 SIOO However when the wake up function is used when bit 5 WUP of serial operation mode register 0 CSIMO is set do not write FFH in SIOO before reception Even if FFH is not written in SIOO the N ch open drain output is always in the high impedance state 3 If datais written to SIOO while the slave is in the wait state that data is held The transfer is started when SCL is output after the wait state is cleared When an 8 bit data transfer ends serial transfer is stopped automatically and the interrupt request flag CSIIFO is set 373 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Figure 17 22 Data Transmission from Master to Slave Both Master and Slave Selected 9 Clock Wait 1 3 a Start Condition to Address Master Device Operation Write SIOO AA ACA ACA AAA ACKD GE VEN CMDD RELD L
518. to Transfer direction R W Data D7 to DO Table 17 4 Signals I2C Bus Mode Signal Name Description Definition SDAO SDA1 falling edge when SCL is high Note 1 Function Indicates that serial communication starts and subsequent data are address data Signaled by Master Signaled when CMDT is set Affected flag s Definition CMDD is set SDAO SDA1 rising edge when SCL is high Note 1 Function Indicates end of serial transmission Signaled by Master Signaled when RELT is set Affected flag s Definition RELD is set and CMDD is cleared Low level of SDAO SDA1 pin during one SCL clock cycle after serial reception Function Indicates completion of reception of 1 byte Signaled by Master or slave Signaled when ACKT is set with ACKE 1 Affected flag s Definition ACKD is set Low level signal output to SCL Function Indicates state in which serial reception is not possible Signaled by Slave Signaled when WAT1 WATO 1x Affected flag s Definition None Synchronization clock for output of various signals Function Serial communication synchronization signal Signaled by Master Signaled when See Note 2 below Affected flag s Definition CSIIFO Also see Note 3 below 7 bit data synchronized with SCL immediately
519. to 1 before transfer start However in the case of the master set ACKE to 0 disable before receiving the last data After address is received if the values of the serial I O shift register 0 5100 and the slave address register SVA match and if the stop condition is detected an interrupt request signal is generated To automatically generate ACK information preset ACKE to 1 enable before transfer start Other than above Setting prohibited BSYE Bit 7 of serial bus interface control register SBIC ACKE Bit 5 of serial bus interface control register SBIC 344 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 17 3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0 Timer clock select register 3 TCL3 Serial operating mode register 0 CSIMO Serial bus interface control register SBIC Interrupt timing specify register SINT 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 0 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88H 345 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Symbol 7 6 Figure 17 3 Timer Clock Select Register 3 Format 5 4 3 2 1 0 L31 TCL30 Address TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TC FF43H 346 TCL32 TCL31 After Reset
520. to control the watch timer Timer clock select register 2 TCL2 Watch timer mode control register TMC2 1 Timer clock select register 2 TCL2 Refer to Figure 10 2 This register sets the watch timer count clock TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the watch timer count clock TCL2 sets the watchdog timer count clock and buzzer output frequency 240 CHAPTER 10 WATCH TIMER Figure 10 1 Watch Timer Block Diagram 5 Bit Counter Selector Selector INTWT Selector Selector gt INTTM3 To 16 Bit Timer Event Counter 1 26 TMC25 TMC24 23 22 21 20 Watch Timer Mode Control Register TCL24 Timer Clock Select Register 2 e Internal Bus 241 CHAPTER 10 WATCH TIMER Figure 10 2 Timer Clock Select Register 2 Format After Symbol 7 6 5 4 3 2 1 0 Address Reset R W TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 FF42H 00H R W TCL21 Watchdog Timer Count Clock Selection fx 2 625 kHz MCS 1 fx 2 313 kHz fx 2 313 kHz fx 2 156 kHz fx 2 156 kHz fx 2 78 1 kHz fx 2 78 1 kHz fx 2 39 1 kHz fx 2 39 1 kHz fx 2 19 5 kHz fx 2 19 5 kHz fx 2 9 8 kHz fx 2 9 8 kHz fx 2 4 9 kHz fx 2 2 4 kHz fx 2 1 2 kHz
521. to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function FIP EEPROM and IEBus are trademarks of NEC Corporation MS DOS Windows and WindowsNT are either registered trademarks or trademarks of Microsoft Corpo ration in the United States and or other countries IBM DOS PC AT and PC DOS are trademarks of International Business Machines Corporation HP9000 Series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a trademark of SPARC International Inc SunOS is a trademark o
522. tors etc Port mode real time output port mode can be specified bit wise 471 CHAPTER 20 REAL TIME OUTPUT PORT 20 2 Real Time Output Port Configuration The real time output port consists of the following hardware Table 20 1 Real time Output Port Configuration Register Real time output buffer register RTBL RTBH Control register Port mode register 12 PM12 Real time output port mode register RTPM Real time output port control register RTPC Figure 20 1 Real time Output Port Block Diagram Internal Bus Real time Output Port Control Register Port Mode Register 12 PM12 INES Real time Output Real time Output INTTM1 Output Trigger Buffer Register Buffer Register Control Circuit Higher 4 Bits Lower 4 Bits INTTM2 RTBH RTBL Real time Output port Mode Register RTPM Output Latch P127 P120 472 CHAPTER 20 REAL TIME OUTPUT PORT 1 Real time output buffer register RTBL RTBH Addresses of RTBL and RTBH are mapped individually in the Special function register SFR area as shown in Figure 20 2 When specifying 4 bits x 2 channels as the operating mode data are set individually in RTBL and RTBH When specifying 8 bits x 1 channel as the operating mode data are set to both RTBL and RTBH by writing 8 bit data to either RTBL or RTBH Table 20 2 shows operations during manipulation of RTBL and RTBH Figure 20 2
523. tput bus mode x x Note 2 Note 2 SBO SDAO P26 CMOS N ch open drain input output EE input output Wake up Function Control 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition when CMDD 1 matches the slave address register SVA data in IC bus mode Slave address register SVA not equal to serial I O shift register 0 SIOO data Slave address register SVA equal to serial I O shift register 0 SIOO data R W Operation stopped Operation enabled Notes 1 Bit 6 COI is a read only bit 2 Can be used freely as port function 3 Be sure to set WUP to 0 when the 2 wire serial I O mode 4 When CSIE0 0 COI becomes 0 Remark x don t care Port Mode Register PXX Port Output Latch 359 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES b Serial bus interface control register SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H symbol gt Address After Reset R W SBIC BSYE ACKT CMDD RELD CMDT RELT FF61H 00H R W R W When 1 800 latch is set to 1 After SOO latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 R W CMDT When CMDT 1 SOO latch is cleared to 0 After SOO
524. tput Latch CLRSET D Q VO Shift r 0 5100 Serial Registe Busy Acknowledge Output Circuit Bus Release i Command Acknowledge Detector Interrupt Request SCKO o gt CE PM27 Output Control P27 Output Latch Serial Clock ki ce INTCSIO Counter TO2 Serial Clock foi 2 28 CSIMOO CSIMOO CSIMO1 CSIMO1 LLL SVAM TCL33 TCL32 TCL31 TCL30 Interrupt Timing Timer Clock Specify Register Select Register 3 Y Internal Bus Remark Output Control performs selection between CMOS output and N ch open drain output 289 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 1 2 290 Serial I O shift register 0 SIOO This is an 8 bit register to carry out parallel serial conversion and to carry out serial transmission reception shift operation in synchronization with the serial clock SIOO is set with an 8 bit memory manipulation instruction When bit 7 CSIEO of serial operating mode register 0 CSIMO is 1 writing data to SIOO starts serial operation In transmission data written to SIOO is output to the serial output SOO or serial data bus SBO SB1 In reception data is read from the serial input SIO or SBO SB1 to SIOO Note that if a bus is driven in the SBI mode or 2 wire serial I O mode the bus pin mus
525. trol register PCC 2 This clock cycle applies to internal ROM program 3 n is the number of waits when external memory expansion area is read from 4 m is the number of waits when external memory expansion area is written to 552 CHAPTER 27 INSTRUCTION SET Instruction Group Mnemonic Operands rp word Operation lt word saddrp word saddrp lt word sfrp word sfrp lt word AX saddrp AX lt saddrp saddrp AX saddrp AX AX sfrp AX c sfrp sfrp AX sfrp lt AX AX rp AX lt rp rp AX AIR lt AX laddr16 A AX lt addr16 laddr16 AX E addr16 AX AX rp AX rp 8 bit A byte A CY amp byte saddr byte saddr CY lt saddr byte A r A CY A r r CYcr A A saddr A CY amp A saddr A addr16 A CY A addr16 A HL A HL byte A CY lt A HL byte A HL B A CY A HL A CY HL B A HL C A CY lt HL operation A byte A CY amp A byte CY saddr byte saddr CY lt saddr byte CY A CY lt saddr A lt A saddr CY A laddr 6 NMI NM
526. trostatic Discharge ESD C11892J C11892bE Guide to Quality Assurance for Semiconductor Devices MEI 1202 Microcontroller Related Product Guide Third Party Manufacturers U11416J Caution The above documents are subject to change without prior notice Be sure to use the latest document for designing 13 MEMO 14 CONTENTS CHAPTER 1 OUTLINE uPD78058F SUBSERIES 35 M ENI C c 35 1 2 Applications ee eae ete eee eee 36 1 3 Ordering Information 36 1 4 Quality Grade oun eI SEM 37 1 5 Pin Configuration Top 38 1 6 78K 0 Series Expansion 41 1 7 Block Diagram A E 43 1 8 Outline of FUNCHON 44 1 9 Differences Between the uPD78058F and UPD78058F A 45 INIUEC Se nre 46 CHAPTER 2 OUTLINE uPD78058FY SUBSERIES nennen nnn nante 47 2 1 Features oes uae uus eL 47 PALA OUp uppnIEe C RE 48 23 Ordering Informalion 48 2 4 Quality Grade a oue rure ectetur aa a aaa e eaaa an rean
527. tting device a Comparison of SIOO data before and after transmission In this case a transmission error is judged to have occurred if the two data values are different b Using the slave address register SVA Transmit data is set in SIOO and SVA before transmission is performed After transmission the COI bit match signal from the address comparator of serial operating mode register 0 CSIMO is tested 1 indicates normal transmission and 0 indicates a transmission error Communication operation In the I C bus mode the master selects the slave device to be communicated with from among multiple devices by outputting address data onto the serial bus After the slave address data the master sends the R W bit which indicates the data transfer direction and starts serial communication with the selected slave device Data communication timing charts are shown in Figures 17 22 and 17 23 In the transmitting device the serial I O shift register 0 SIOO shifts transmission data to the SO latch in synchronization with the falling edge of the serial clock SCL the SOO latch outputs the data on an MSB first basis from the SDAO or SDA1 pin to the receiving device In the receiving device the data input from the SDAO or SDA1 pin is taken into the SIOO in synchroniza tion with the rising edge of SCL Start of transfer A serial transfer is started by setting transfer data in serial I O shift register 0 SIOO if the following two condi
528. tudied carry out a thorough evaluation of the CS products not ES products among the mask ROM products Remark Only the PD78058F and 78058FY 78P058F 78P058FY are provided with an internal expansion RAM size switching register 537 CHAPTER 26 uPD78P058F 78PO58FY 26 1 Memory Size Switching Register In the PD78P058F and 78P058FY internal memory can be selected through the memory size select register IMS The same memory mapping as that of mask ROM versions that have a different internal memory can be done by setting IMS IMS is set with an 8 bit memory manipulation instruction RESET input sets IMS to CFH Figure 26 1 Memory Size Switching Register Format After Symbol 7 6 1 0 Address Reset R W 5 4 3 2 IMS RAM2 1 RAMO ROM2 ROM 1 ROMO FFFOH CFH R W ROMO Internal ROM Capacity Selection 48 Kbytes 56 Kbytes 60 Kbytes Other than above Setting prohibited RAM2 RAMO Internal High Speed RAM Capacity Selection 1 1 0 1024 bytes Other than above Setting prohibited Note When using the external device expansion function with uPD78058F 78P058F 78058FY and 78PO58FY the capacity of the internal ROM should be less than 56 Kbytes The IMS settings to give the same memory map as mask ROM versions are shown in Table 26 2 Table 26 2 Examples of Memory Size Switching Register Settings Relevant Mask ROM Version IMS Setting UPD78056F 78056FY U
529. u gt d fceu fcPu CPU clock set by bits 0 to 2 PCCO to PCC2 of the processor clock control register PCC and bit 0 MCS of the oscillation mode selection register OSMS MAX a b aor b whichever is greater Figure 18 24 Operation Timing with Automatic Data Transmit Receive Function Performed by Internal Clock Tsck k Interval sor K o K X s K oe XY os XY oe Yor Xoo X sn X o K os K os X os XY os X oe Xoo XY v E fx Main system clock oscillation frequency fcpu CPU clock set by bit 0 to bit 2 to PCC2 of the processor clock control register PCC and bit 0 MCS of the oscillation mode select register OSMS 1 fcpu Tsck 1 fsck fsck Serial clock frequency 430 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 b When the automatic transmit receive function is used by the external clock If bit 1 CSIM11 of serial operation mode register 1 CSIM1 is cleared to 0 external clock operation is set When the automatic transmit receive function is used by the external clock it must be selected so that the interval may be longer than the values shown as follows Table 18 3 Interval Timing Through CPU Processing When the External Clock Is Operating CPU Processing When using multiplication instruction Interval Time 13TcPu When using division instruction 20T cpu External access 1 wait mode 9TcPu Other than above 1 fcPu 7TcPu
530. ue X 0000 X 0001 X DO X 0001 X D1 X X X D2 X 0000 X 0001 X TIOO Pin Input i ks i 5 Ws CRO1 Captured Value ee CROO Captured Value Foor gt TIT CREE LES DEN D2xt 199 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 5 5 External event counter operation The external event counter counts the number of external clock pulses to be input to the TIOO PO0 pin with the 16 bit timer register TMO TMO is incremented each time the valid edge specified with the external interrupt mode register 0 INTMO is input When the TMO counted value matches the 16 bit capture compare register 00 CROO value TMO is cleared to 0 and the interrupt request signal INTTMOO is generated Set a value for CROO other than 0000H 1 pulse count operation is not possible The rising edge the falling edge or both edges can be selected with bits 2 and 3 ES10 and ES11 of INTMO Because operation is carried out only after the valid edge is detected twice by sampling at the interval selected with the sampling clock select register SCS noise with short pulse widths can be removed Figure 8 26 Control Register Settings in External Event Counter Mode a 16 bit timer mode control register TMCO TMC03 TMCO2 TMCO1 OVFO b Capture compare control register 0 CRCO Clear amp start with match of TMO and CROO CRC02 CRCO1 CRC00 ERR HEC Remark 0 1 Setting 0 or 1 al
531. uency output by TO2 3 Can be used freely as a port 4 Tousethe wake up function WUP 1 set the bit 5 SIC of the interrupt timing specify register SINT to 1 Do not execute an instruction that writes the serial I O shift register 0 SIOO while WUP 1 5 When CSIEO 0 COI is 0 Remark x don t care PMXX Port Mode Register PXX Port Output Latch 368 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES Symbol b Serial bus interface control register SBIC SBIC is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H D o Oo Address After Reset R W SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H Rw e R W R W R R W R W R W Use for stop condition output When RELT 1 SOO latch is set to 1 After SOO latch setting automati cally cleared to 0 Also cleared to 0 when CSIEO 0 Use for start condition output When CMDT 1 SOO latch is cleared to 0 After clearing SOO latch automatically cleared to 0 Also cleared to 0 when CSIEO 0 RELD Stop Condition Detection Clear Conditions RELD 0 Setting Condition RELD 1 When transfer start instruction is executed When stop condition is detected If SIOO and SVA values do not match in address reception e When CSIEO 0 When RESET input is applied CMDD Start Condition Detection Clear Conditions CMDD 0 Setting Condition CMDD 1 When transfe
532. umNete 224 8 us 1 5 fsck 236 0 us 0 5 fscK 237 6 us 4 1 5 fsck 248 8 us O 5 fsck 250 4 us 1 5 fsck 261 6 us 0 5 263 2 us 1 5 fsck 274 4 us 4 O 5 fsck 276 0 us 1 5 fsck 287 2 us 4 O 5 fsck 288 8 us 1 5 fsck 300 0 us 0 5 fsck 301 6 us 1 5 fsck o o oio 312 8 us 0 5 fscK 314 4 us 1 5 fsck 325 6 us 0 5 fscK 327 2 us 1 5 fsck 338 4 us 0 5 fscK 340 0 us 1 5 fsck 351 2 us 0 5 fscK 352 8 us 1 5 fsck 364 0 us 0 5 fscK 365 6 us 1 5 fsck 376 8 us 0 5 fscK 378 4 us 1 5 fsck 389 6 us 0 5 fscK 391 2 us 1 5 fsck 402 4 us O 5 fsck 404 0 us 1 5 fsck 415 2 us O 5 fsck 416 8 us 1 5 fsck The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value setin ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck Minimum n 1 x 2 28 40 5 fxx fxx fsck Maximum n 1 x 28 36 15 fxx fxx fsck Cautions 1 Do not write ADTI during operation of automatic data transmit receive function 2 Bits 5 and 6 must be set to zero 3 If the auto send and receive data transmission interval time is controlled using ADTI busy control becomes invalid see 18 4 3 4 a Busy c
533. unter Operation Timings with Rising Edge Specified 228 9 10 Square Wave Output Operation Timing 230 9 11 Interval Timer Operation Timing 231 9 12 External Event Counter Operation Timings with Rising Edge Specified 233 9 13 Square Wave Output Operation Timing nennen nennen enne 235 9 14 8 Bit Timer Registers Start TIMING ansien nnne nnn enne neni 236 9 15 Event Counter Operation Timing nnne nennen rennen enn nennen enne 236 9 16 Timing After Compare Register Change During Timer Count Operation 237 10 1 Watch Timer Block Diagram 241 10 2 Timer Clock Select Register 2 Format cccesceseseeeceeeeeeseeeeaeeeaeeseaeeeeeseaeessaeseaeeseaeenaeesaeeeaeeeeees 242 10 3 Watch Timer Mode Control Register Format esssssssseeeeeenenen nennen nnne trennen 243 11 1 Watchdog Timer Block Diagram 247 11 2 Timer Clock Select Register 2 Format cecceesceeeeeeeeeeeeeeeeeseaeeeeeseaeeeeeseaeeseaeeeaeesaeseaeesneeseeeeneees 249 11 3 Watchdog Timer Mode Register Format essceeeseeeeeeneeeeeneeeeeeneeeeeaeeeeeaeeeesaeeessaeeeeesaeeeseneeeseneeees 250 12 1 Remote Controlled Output Application Example
534. upt request flag CSIIF1 is set INTCSI1 generation Figure 18 13 Internal Buffer RAM Operation in 6 Byte Transmission in Basic Transmit Mode 1 2 a Before transmission FADFH FAC5H Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 FACOH Transmit data 6 T6 417 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 418 Figure 18 13 Internal Buffer RAM Operation in 6 Byte Transmission in Basic Transmit Mode 2 2 FADFH FAC5H FACOH FADFH FAC5H FACOH b 4th byte transmission point Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 c Completion of transmission Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 c Repeat transmission mode In this mode data stored in the internal buffer RAM is transmitted repeatedly Serial transmission is started by writing the desired data to serial I O shift register 1 SIO1 when bit 7 CSIE1 of serial operation mode register 1 CSIM1 is set at 1 Unlike the case of the basic transmission mode an interrupt request flag CSIIF1 is not set after sending the final byte FACOH address data but the auto data send and re
535. upt request signal INTPO is set Also when the edge specified by bits 4 and 5 ES20 and ES21 of INTMO is input to the TIO1 PO1 pin the value of TMO is taken into 16 bit capture compare register 00 CROO and an external interrupt request signal INTP1 is set Any of three edge specifications can be selected rising falling or both edges as the valid edge for the TIOO POO0 pin and the TIO1 PO1 pin by means of bits 2 ESO1 and ES11 and bits 4 and 5 ES20 and ES21 of INTMO respectively For TIOO POO pin valid edge detection sampling is performed at the interval selected by means of the sampling clock selection register SCS and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Figure 8 20 Control Register Settings for Two Pulse Width Measurements with Free Running Counter a 16 bit timer mode control register TMCO TMC03 TMCO2 TMCO1 OVFO b Capture compare control register 0 CRCO Free Running Mode CRC02 1 CRCOO ZU Aa cae RE SE ZEE CROO set as capture register Captured in CROO on valid edge of TIO1 PO1 Pin CR01 set as capture register Remark 0 1 Setting O or 1 allows another function to be used simultaneously with pulse width measure ment See the description of the respective control registers for details 195 CHAPTER 8 16 TIMER EVENT COUNTER Timing of Pulse Width Measu
536. uration Using I2C Bus AVop AVop Master CPU Slave CPU1 SCL Serial clock SCL Serial data bus SDAO SDA1 SDAO SDA1 Slave CPU2 SCL SDAO SDA1 Slave IC SCL SDA 363 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78058FY SUBSERIES 1 12C bus mode functions In the I2C bus mode the following functions are available a Automatic identification of serial data Slave devices automatically detect and identifies start condition data and stop condition signals sent in series through the serial data bus b Chip selection by specifying device addresses The master device can select a specific slave device connected to the 12 bus and communicate with it by sending in advance the address data corresponding to the destination device c Wake up function During a slave operation if the received address matches the value in the slave address register SVA an interrupt request is generated an interrupt request is generated even when the stop condition is detected Therefore CPUs other than the selected slave device on the I C bus can perform independ ent operations during the serial communication d Acknowledge signal ACK control function The master device and a slave device send and receive acknowledge signals to confirm that the serial communication has been executed normally e Wait signal WAIT control function When a slave device is preparing for data transmission or re
537. ure 7 7 External Circuit of Subsystem Clock Oscillator a Crystal oscillation b External clock External Clock u PD74HCUO4 Cautions 1 Whenusing a main system clock oscillator and a subsystem clock oscillator carry out wiring in the broken line area in Figures 7 6 and 7 7 to prevent any effects from wiring capacities e Minimize the wiring length e Do notallow wiring to intersect with other signal lines Do not allow wiring to come near changing high current e Set the potential of the grounding position of the oscillator capacitor to that of Vss Do not ground to any ground pattern where high current is present e Do not fetch signals from the oscillator Take special note of the fact that the subsystem clock oscillator is a circuit with low level amplification so that current consumption is maintained at low levels Figure 7 8 shows examples of resonator having incorrect connection Figure 7 8 Examples of Resonator with Incorrect Connection 1 2 a Wiring of connection b Signal lines intersect each other circuits is too long PORTn n 0 to 7 12 13 2 X1 IC Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Further insert resistors in series on the side of XT2 162 CHAPTER 7 CLOCK GENERATOR Figure 7 8 Examples of Resonator with Incorrect Connection 2 2 c Changing high current is too near a d Current flows through the
538. urhe e tat eb tari finie re enm alite utu 576 B 2 Upgrading Former In circuit Emulators for 78K 0 Series to IE 78001 R A 576 33 MEMO 34 CHAPTER 1 OUTLINE uPD78058F SUBSERIES 1 1 Features Q O Compared to the conventional uPD78054 Subseries EMI Electro Magnetic Interference noise has been reduced On chip high capacity ROM and RAM Data Memory Program Memory Part Number ROM Internal High Speed RAM Internal Buffer RAM Internal Expansion RAM LPD78056F 48 Kbytes 1024 bytes 32 bytes None HPD78058F 60 Kbytes 1024 bytes uPD78PO058F 60 KbytesNote 1 1024 bytesNote 1 1024 bytesNote 2 Notes 1 The capacities of internal PROM and internal high speed RAM can be changed by means of the memory size switching register IMS 2 The capacity of internal expansion RAM can be changed by means of the internal expansion RAM size switching register IXS External Memory Expansion Space 64 Kbytes Minimum instruction execution time changeable from high speed 0 4 us In main system clock 5 0 MHz operation to ultra low speed 122 us In subsystem clock 32 768 kHz operation Instruction set suited to system control Bit manipulation possible in all address spaces Multiply and divide instructions 69 I O ports 4 N ch open drain ports 8 bit resolution A D converter 8 channels 8 bit resolution D A converter 2 channels Serial interface 3 c
539. ut SO1 CMOS output SCK1 Input SCK1 CMOS output 2 Can be used as P20 CMOS input output when only transmitter is used clear bit 7 RE of the automatic data transmit receive control register ADTC to 0 Remark x PXX Don t care PMXX Port Mode Register Port Output Latch 399 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18 4 2 3 wire serial I O mode operation The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers that incorporate a conventional synchronous serial interface such as the 75X XL 78K and 17K Series Communication is carried out with three lines of serial clock SCK1 serial output SO1 and serial input 511 1 Register setting The 3 wire serial I O mode is set with the serial operating mode register 1 CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H Symbol 6 5 4 3 2 1 0 Address After Reset R W CSIM1 CSIE1 DIR ATE jose osmo FF68H 00H R W Serial Interface Channel 1 Clock Selection Clock externally input to SCK1 pinNote 1 CSIM10 8 bit timer register 2 TM2 output Clock specified with bits 4 to 7 of timer clock select register 3 TCL3 3 wire serial I O mode 3 wire serial I O mode with automatic transmit receive function DIR Start Bit 801 Pin Function MSB SH P20 LSB Input 501 Pin Function SO1 CMOS output 0 1 N
540. ut Channel Selection gt gt gt gt gt gt gt gt A D Conversion Time fx 5 0 MHz Operation fx 4 19 MHz Operation MCS 1 MCS 0 MCS 1 MCS 0 80 fx Setting prohibited 160 fx 32 05 80 fx 19 105 160 fx 38 128 40 fx Setting prohibited 2 80 fx Setting prohibited e 2 40 fx Setting prohibited 80 fx 19 105 50 fx Setting prohibited 100 fx 20 005 50 fx Setting prohibited 100 fx 23 8 us 100 fx 20 005 200 fx 40 005 100 fx 23 848 200 fx 47 78 Setting prohibited External Trigger Selection No external trigger software starts Conversion started by external trigger hardware starts A D Conversion Operation Control Operation stop Operation start Notes 1 Set so that the A D conversion time is 19 1 us or more 2 Setting prohibited because A D conversion time is less than 19 1 us Cautions 1 The following sequence is recommended for power consumption reduction of A D converter when the standby function is used Clear bit 7 CS to 0 first to stop the A D conversion operation and then execute the HALT or STOP instruction 2 When restarting the stopped A D conversion operation start the A D conversion operation after clearing the interrupt request flag ADIF to 0 Remarks fx Main system clock oscillation frequency MCS Bit 0 of oscillation mode selection regis
541. ut via the scaler is used as the main system clock OSMS is set with 8 bit memory manipulation instruction RESET input sets OSMS to 00H Figure 7 4 Oscillation Mode Selection Register Format After Symbol 7 6 5 4 3 2 1 0 Address Reset R W oss 10 0 w 0 Scaler used Caution 1 Writing to OSMS should be performed only immediately after reset signal release and before peripheral hardware operation starts As shown in Figure 7 5 below writing data including same data as previous to OSMS cause delay of main system clock cycle up to 2 fx during the write operation Therefore if this register is written during the operation in peripheral hardware which operates with the main system clock a temporary error occurs in the count clock cycle of timer etc Also when switching the oscillation mode the clock supplied to the CPU is switched as well as the clock supplied to the peripheral hardware Therefore it is recommended that the instruction for writing to OSMS be executed only once after releasing the reset and before operating the peripheral hardware 159 CHAPTER 7 CLOCK GENERATOR Figure 7 5 Main System Clock Waveform due to Writing to OSMS Write to OSMS MCS 0 Operating at fxx fx 2 MCS 0 operating at fxx fx 2 MCS 0 Caution 2 When writing 1 to MCS must be 2 7 V or higher before the write execution Remarks fxx Main system clock frequ
542. utput port with output latch P20 to P27 pins can specify the input mode output mode in 1 bit units with the port mode register 2 PM2 When P20 to P27 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Alternate functions include serial interface data input output clock input output automatic transmit receive busy input and strobe output RESET input sets port 2 to input mode Figures 6 7 and 6 8 show block diagrams of port 2 Caution When used as a serial interface pin set the input output and output latch according to its functions For the setting method refer to Figure 17 4 Serial Operating Mode Register 0 Format and Figure 18 3 Serial Operating Mode Register 1 Format Figure 6 7 P20 P21 P23 to P26 Block Diagram AVopb WRPuo 4 PUO2 34 m B RD e e 8 WRport n E Output Latch 2 A P20 P21 P23 to P26 313 n EEUU P23 STB P24 BUSY P25 SIO SBO SDAO WRem P26 SO0 SB1 SDA1 A PM20 PM21 l vw PM23 to PM26 m Alternate Function PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal 135 CHAPTER 6 PORT FUNCTIONS Internal bus 136 WReuo D Figure 6 8 P22 and P27 Block Diagram AVop DE
543. vectored interrupt service is carried out 8 to 9 clocks When vectored interrupt service is not carried out 2 to 3 clocks b Clear upon non maskable interrupt request When an unmasked interrupt request is generated the HALT mode is cleared and vectored interrupt servicing is performed whether interrupt acknowledge is enabled or disabled c Clear upon unmasked test input The HALT mode is cleared by unmasked test input and the next address instruction of the HALT instruction is executed 518 CHAPTER 23 STANDBY FUNCTION d Clear upon RESET input The HALT mode is cleared upon RESET signalinput Asis the case with normal reset operation a program is executed after branching to the reset vector address Figure 23 3 HALT Mode Release by RESET Input Wait HALT 2 f 26 2 ms Instruction RESET _ Signal Oscillation Operating Reset Stabilization Operating Mode HALT Mode Period Wait Status Mode Oscillation Oscillation Stop Oscillation Clock a a Remarks 1 fx main system clock oscillation frequency 2 y fx 5 0 MHz Table 23 2 Operation After HALT Mode Release Release Source Operation Maskable interrupt Next address instruction execution request Interrupt service execution Next address instruction execution Interrupt service execution HALT mode hold Non maskable interrupt Interrupt service execution request Test input Next address instruction execu
544. verter analog output The following operating modes can be specified bit wise 1 Port mode These ports function as 2 bit input output ports They can be specified bit wise as input or output ports with port mode register 13 PM13 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register H PUOH 2 Control mode These ports allow D A converter analog output ANOO and ANO1 Caution When only either one of the D A converter channels is used with AVner Voo the other pins that are not used as analog outputs must be set as follows Set PM13x bit of the port mode register 13 PM13 to 1 input mode and connect the pin to Vss Set PM13x bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low level from the pin 4 2 11 AVREFo A D converter reference voltage input pin When A D converter is not used connect this pin to Vss 4 2 12 AVREF1 D A converter reference voltage input pin When D A converter is not used connect this pin to 88 CHAPTER 4 PIN FUNCTION uPD78058FY SUBSERIES 4 2 13 AVpp This is the analog power supply pin of the A D converter and the port s power supply pin Always use the same voltage as that of the Voo pin even when the A D converter is not used 4 2 14 AVss This is the ground potential pin for the A D converter and D A converter and the ground potential pin for the port Even whe
545. ware statuses become undefined All other hardware statuses remains unchanged after reset 2 If there is a reset while in the standby mode the status before reset is maintained even after reset is performed 3 The values after reset depend on the product LuPD78056F 78056FY CCH LPD78058F 78058FY CFH uPD78PO058F 78P058FY 4 Incorporated only in the uPD78058F 78058FY 78P058F and 78PO58FY 525 CHAPTER 24 RESET FUNCTION Table 24 1 Hardware Status after Reset 2 2 Hardware Status after Reset Watch timer Mode control register TMC2 00H Clock select register TCL2 00H Mode register WDTM 00H Serial interface Clock select register TCL3 88H Shift registers SIOO SIO1 Undefined Mode registers CSIMO CSIM1 CSIM2 00H Serial bus interface control register SBIC 00H Watchdog timer Slave address register SVA Undefined Automatic data transmit receive control register ADTC 00H Automatic data transmit receive address pointer ADTP 00H Automatic data transmit receive interval specify register ADTI 00H Asynchronous serial interface mode register ASIM 00H Asynchronous serial interface status register ASIS 00H Baud rate generator control register BRGC 00H Transmit shift register TXS Receive buffer register RXB Interrupt timing specify register SINT 00H A D converter Mode register ADM 01H Conversion result
546. ween different types Address Command and Data Address Data used to select a device which is the target of serial communications Command Data which gives a command to the target device Data Data which are actually transmitted In actual transmission first the master device outputs the address on the serial bus and selects the slave device which is the target of the transmission from among multiple devices After that by transmitting Commands and Data between the master device and slave device serial transmission is possible The receiving side can determine automatically through its hardware whether transmission data are address command or data This function enables the input output ports to be used effectively and the application program serial interface control portions to be simplified In this mode the wake up function for handshake and the output function of acknowledge and busy signals can also be used CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 4 2 wire serial I O mode MSB first This mode is used for 8 bit data transfer using two lines of serial clock SCKO and serial data bus SBO or SB1 This mode enables to cope with any one of the possible data transfer formats by controlling the SCKO level and the SBO or SB1 output level Thus the handshake line previously necessary for connection of two or more devices can be removed resulting in the increased
547. write a program into the uPD78P058F or 78PO58FY PROM make the device enter the PROM programming mode by setting the levels of the Ver and RESET pins as specified For the connection of unused pins see paragraph 2 PROM programming mode in section 1 5 or 2 5 Pin Configuration Top View Caution Write the program in the range of addresses 0000H to EFFFH specify the last address as EFFFH The program cannot be correctly written by a PROM programmer which does not have a write address specification function 26 3 1 Operating modes When 5 V or 12 5 V is applied to the Ver pin and a low level signal is applied to the RESET pin the uPD78P058F and uPD78P058FY are set to the PROM programming mode This is one of the operating modes shown in Table 26 4 below according to the setting of the CE OE and PGM pins The PROM contents can be read by setting the read mode Table 26 4 PROM Programming Operating Modes DO to D7 Operating Mode Page data latch Data input Page write High impedance Byte write Data input Program verify Data output Program inhibit High impedance Read Data output Output disabled ee r aE High impedance Standby x High impedance Remark x LorH 1 Read mode Read mode is set by setting CE to L and OE to L 2 Output disable mode If OE is set to H data output becomes high impedance
548. x 1 fx 27 x 1 fx 12 8 us 25 6 us 3 28 ms 6 55 ms 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 215 x 1 fx 216 x 1 fx 27 x 1 fx 28 x 1 fx 25 6 us 51 2 us 6 55 ms 13 1 ms 25 6 us 51 2 us 28 x 1 fx 29 x 1 fx 216 x 1 fx 217 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 us 13 1 ms 26 2 ms 51 2 us 102 4 us 29 x 1 fx 210 x 1 fx 217 x 1 fx 218 x 1 fx 29 x 1 fx 210 x 1 fx 102 4 us 204 8 us 26 2 ms 52 4 ms 102 4 us 204 8 us 211 x 1 fx 212 x 1 fx 219 x 1 fx 220 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 104 9 ms 209 7 ms 409 6 us 819 2 us Remarks 1 fx Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 3 Values in parentheses when operated at fx 5 0 MHz 212 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 2 External event counter The number of pulses of an externally input signal can be measured 3 Square wave output A square wave with any selected frequency can be output Minimum Pulse Width Maximum Pulse Width Table 9 2 8 Bit Timer Event Counter Square Wave Output Ranges Resolution 2 x 1 fx 400 ns 22 x 1 fx 800 ns MCS 1 29 x 1 fx 102 4 us MCS 0 210 x 4 fx 204 8 us MCS 1 2 x 1 fx 400 ns MCS 0 22 x 1 fx 800 ns 2 x 1 fx 800 ns 23 x 1 fx 1 6 us 210 x 1 fx 204 8 us 211 x 1 fx 409 6 us 2 x 1 fx 800 ns 23 x 1
549. x 219 x 4 fx 220 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 104 9 ms 209 7 ms 409 6 us 819 2 us Other than above Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 3 TCL10 to TCL13 Bits 0 to 3 of timer clock selection register 1 TCL1 4 Values in parentheses when operated at fx 5 0 MHz 226 CHAPTER 9 8 BIT TIMER EVENT COUNTERS Table 9 7 8 Bit Timer Event Counter 2 Interval Time Minimum Interval Time Maximum Interval Time Resolution TCL16 TCL15 TCL14 TI2 input cycle 28 x TI2 input cycle TI2 input edge cycle TI2 input cycle 28 x TI2 input cycle TI2 input edge cycle 2 x 1 fx 2 x 1 fx 29 x 1 fx 210 x 1 fx 2 x 1 fx 22 x 1 fx 400ns 800ns 102 4 us 204 8 us 400ns 800 ns 22 x 1 fx 23 x 1 fx 210 x 1 fx 211 x 1 fx 22 x 1 fx 23 x 1 fx 800ns 1 6 204 8 us 409 6 us 800ns 1 6 us 23 x 1 fx 24 x 1 fx 211 x 1 fx 212 x 1 fx 23 x 1 fx 24 x 1 fx 1 6 us 3 2 us 409 6 us 819 2 us 1 6 us 8 2 us 2 x 1 fx 25 x 1 fx 212 x 1 fx 213 x 1 fx 2 x 1 fx 25 x 1 fx 3 2 us 6 4 us 819 2 us 1 64 ms 3 2 us 6 4 us 25 x 1 fx 26 x 1 fx 213 x 1 fx 214 x 1 fx 25 x 1 fx 26 x 1 fx 6 4 us 12 8yus 1 64 ms 3 28 ms 6 4us 12 8 us 26 x 1 fx 27 x 1 fx 214 x 1 fx 215 x 1 fx 26 x 1 fx 27 x 1 fx 1
550. xD pin input is performed RxD pin input sampling is performed using the serial clock specified by ASIM When the RxD pin input becomes low the baud rate generator s 5 bit counter see Figure 19 2 starts counting and at the time when the half time determined by specified baud rate has passed the data sampling start timing signal is output If the RxD pin input sampled again as a result of this start timing signal is low it is identified as a start bit the 5 bit counter is initialized and starts counting and data sampling is performed When character data a parity bit and one stop bit are detected after the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to the receive buffer register RXB and a reception completion interrupt request INTSR is generated Even if an error occurs the receive data for which the error occurred is transferred to RXB When an error occurs if bit 1 ISRM of ASIM is cleared 0 INTSR is generated If ISRM is set 1 INTSR is not generated If the RXE bit is reset 0 during the receive operation the receive operation is stopped immediately In this case the contents of RXB and ASIS are not changed and INTSR and INTSER are not generated Figure 19 9 Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing 458 nome XX START INTSR Caution The receive buffer register
551. xternal Memory a No wait PW1 PWO 0 0 setting a CE Lower Address X Operation Code Higher Address b Wait PW1 PWO 0 1 setting Lower Address Operation Code Higher Address c External wait PW1 PWO 1 1 setting NEN Gc MM NM EUER X Lower Address X Address Operation Code X X Higher Address X 511 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 512 ASTB RD ADO to AD7 A8 to A15 ASTB RD ADO to AD7 A8 to A15 Internal Wait Signal 1 clock wait ASTB ADO to AD7 A8 to A15 WAIT Figure 22 5 External Memory Read Timing a No wait PW1 PWO 0 0 setting a Lower Address Read Data X Higher Address b Wait PW1 PWO 0 1 setting Lower Address Read Data X Higher Address c External wait PW1 PWO 1 1 setting X Lower Address X Address Read Data X Higher Address CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22 6 External Memory Write Timing a No wait PW1 PWO 0 0 setting ASTB WR Hi Z ADO to AD7 Lower Address gt 7 7 7 Write Data A8 to A15 Higher Address b Wait PW1 PWO 0 1 setting ASTB N _ _ _ _ ee WR Hi Z ADOtoAD7 __ Write Data A8 to A15 Higher Address Internal Wait Signal n 1 clock wait c External wait PW1 PWO 1 1 setting ASTB _ WR
552. y defining the pull up resistor option register L PUOL Control mode Port 7 functions as serial interface data input output and clock input output a SI2 SO2 Serial interface serial data input output pins b SCK2 Serial interface serial clock input output pin c RxD TxD Asynchronous serial interface serial data input output pins d ASCK Asynchronous serial interface serial clock input output pin Caution When this port is used as a serial interface pin the I O and output latches must be set according to the function the user requires For the setting refer to Table 19 2 Serial Interface Channel 2 Operating Mode Settings of List 69 CHAPTER 3 PIN FUNCTION uPD78058F SUBSERIES 3 2 9 P120 to P127 Port 12 These are 8 bit input output ports Besides serving as input output ports they function as a real time output port The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 12 PM12 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register H PUOH 2 Control mode These ports function as real time output ports RTPO to RTP7 outputting data in synchronization with a trigger 3 2 10 P130 and P131 Port 13 These are 2 bit input output ports Besides serving as input output ports they are used fo
553. y output when ACKE 1 However not automatically cleared to 0 after acknowledge signal output R ACKD Acknowledge Detection Clear Conditions ACKD 0 Set Conditions ACKD 1 Falling edge of the SCKO immediately after the busy When acknowledge signal ACK is detected at the mode is released while executing the transfer rising edge of SCKO clock after completion of start instruction transfer When CSIE0 0 When RESET input is applied R W Synchronizing Busy Signal Output Control Disables busy signal which is output in synchronization with the falling edge of SCKO clock just after execution of the instruction to be cleared to 0 Outputs busy signal at the falling edge of SCKO clock following the acknowledge signal Note The busy mode can be canceled by starting serial interface transfer However the BSYE flag is not cleared to 0 Remark CSIEO Bit 7 of Serial Operation Mode Register 0 CSIMO 297 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78058F SUBSERIES 4 Interrupt timing specify register SINT This register sets the bus release interrupt and address mask functions and displays the SCKO0 P27 pin level status SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Figure 16 6 Interrupt Timing Specify Register Format Symbol 7 3 Address After Reset R W Tee h R W SVAM SVA Bit to be Used as Slave Address 0
554. z 28 fx 2 19 5 kHz 9 8 kHz fxx 2 fx 2 9 8 kHz 4 9 kHz fxx 2 fx 2 2 4 kHz 1 2 kHz Setting prohibited 8 Bit Timer Register 2 Count Clock Selection TI2 falling edge TI2 rising edge fxx 2 fx 2 2 5 MHz 1 25 MHz fxx 2 fx 2 1 25 MHz 625 kHz fxx 2 fx 2 625 kHz 313 kHz fxx 2 fx 24 313 kHz 156 kHz fxx 2 fx 2 156 kHz 78 1 kHz fxx 2 fx 2 78 1 kHz 39 1 kHz fxx 2 fx 2 39 1 kHz 19 5 kHz 28 fx 2 19 5 kHz 9 8 kHz fxx 2 fx 2 9 8 kHz 4 9 kHz fxx 2 fx 2 2 4 kHz 1 2 kHz Other than above Setting prohibited Caution When rewriting TCL1 to other data stop the timer operation beforehand Remarks 1 D fxx fx TH TI2 Main system clock frequency fx or fx 2 Main system clock oscillation frequency 8 bit timer register 1 input pin 8 bit timer register 2 input pin MCS Bit 0 of oscillation mode selection register OSMS Figures in parentheses apply to operation with fx 2 5 0 MHz CHAPTER 9 8 BIT TIMER EVENT COUNTERS 2 8 bit timer mode control register TMC1 This register enables stops operation of 8 bit timer registers 1 and 2 and sets the operating mode of 8 bit timer register 1 and 2 TMC1 is set w

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