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Maxim DS87C530 Clock User Manual

1. M2 M1 MOVX CYCLES tucs 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles default 4 0 1 0 4 machine cycles 8 0 1 1 5 machine cycles 12 1 0 0 6 machine cycles 16 1 0 1 7 machine cycles 20 1 1 0 8 machine cycles 24 1 1 1 9 machine cycles 28 EXTERNAL CLOCK CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS Clock High Time tcucx 10 ns Clock Low Time 10 ns Clock Rise Time terc 5 ns Clock Fall Time tcucr 5 ns SERIAL PORT MODE 0 TIMING CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN UNITS Clock SM2 0 12 clocks per cycle 12tcrcr Time SM2 1 4 clocks cycle Output Data Setup to SM2 0 12 clocks per cycle 10 Glock Rising SM2 1 4 clocks cycle Output Data Hold from SM2 0 12 clocks per cycle a Glock Rising i SM2 1 4 clocks per cycle Data Hold after SM2 0 12 clocks per cycle M SM2 1 4 clocks per cycle Clodi Rising dee to SM2 0 12 clocks per cycle lltcercr SM2 1 4 clocks per cycle d H 886 3 5753170 HEJ 86 21 54151736 WEAR TI Hi 86 755 83298787 Http www 10
2. DMEI DMEO DATA MEMORY ADDRESS MEMORY FUNCTION 0 0 0000h FFFFh External Data Memory default condition 0 0000h 03FFh Internal SRAM Data Memory 0400h FFFFh External Data Memory 1 0 Reserved Reserved 0000h 03FFh Internal SRAM Data Memory 0400h FFFBh Reserved no external access FFFCh Read access to the status of lock bits FFFDh FFFh Reserved no external access Notes on the status byte read at FFFCh with 0 1 Bits 2 0 reflect the programmed status of the security lock bits LB2 LBO They are individually set to a logic 1 to correspond to a security lock bit that has been programmed These status bits allow software to verify that the part has been locked before running if desired The bits are read only Note After internal MOVX SRAM has been initialized changing bits DEMO 1 has no effect on the contents of the SRAM STRETCH MEMORY CYCLE The DS87C530 DS83C530 allow software to adjust the speed of off chip data memory access The microcontrollers can perform the MOVX in as few as two instruction cycles The on chip SRAM uses this speed and any MOVX instruction directed internally uses two cycles However the time can be stretched for interface to external devices This allows access to both fast memory and slow memory or peripherals with no glue logic Even in high speed systems it may not be necessary or desirable to perform off chip data memory access at full speed In addition
3. WD1 TIME 33MHz RESET TIMEOUT TIME 33MHz 0 0 2 clocks 3 9718ms 2 7 512 clocks 3 9874ms 0 1 2 clocks 31 77ms 2 512 clocks 31 79ms 1 0 2 clocks 254 20ms 2 512 clocks 254 21ms 1 1 226 clocks 2033 60ms 27 512 clocks 2033 62ms As shown above the Watchdog Timer uses the crystal frequency as a time base A user selects one of four counter values to determine the timeout These clock counter lengths are 2 131 072 clocks 220 1 048 576 2 8 388 608 clocks and 27 67 108 864 clocks The times shown in Table 7 are with a 33MHz crystal frequency Once the counter chain has completed a full interrupt count hardware will set an interrupt flag Regardless of whether the user enables this interrupt there are then 512 clocks left until the reset flag is set Software can enable the interrupt and reset individually Note that the Watchdog is a free running timer and does not require an enable P 550 8 5753170 WEE 86 21 54151736 JJ t GR 86 755 83298787 Http www 100y com tw 26 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock There are five control bits in special function registers that affect the Watchdog Timer and two status flags that report to the user WDIF WDCON 3 is the interrupt flag that is set at timer termination when there are 512 clocks remaining until the reset flag is set WTRF WDCON 2 is the flag that is set whe
4. 2 2 2 See IPD JEDEC J STD 020 Specification This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods of time may affect reliability DC ELECTRICAL CHARACTERISTICS Vcc 4 5V to 5 5V 40 C to 85 Note 2 PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage 4 5 5 0 5 5 V 3 Power Fail Warning 4 25 4 38 4 5 V 3 Minimum Operating Voltage 4 0 4 13 4 25 V 3 Backup Battery Voltage 2 5 3 0 0 7 V Supply Current Active Mode at 33MHz Icc 30 46 mA 4 Supply Current Idle Mode at 33MHz 15 25 mA 5 Supply Current Stop Mode Bandgap Disabled 0 to 70 250 pa Supply Current Stop Mode Bandgap Disabled 1 150 6 40 to 85 H Supply Current Stop Mode Bandgap Enabled 0 C to 70 gt 59 uA 6 Supply Current Stop Mode Bandgap Enabled s 50 195 A 6 40 to 85 P Backup Supply Current Data Retention Mode 0 C to 70 04 uA 1 Backup Supply Current Data Retention Mode 0 1 7 40 C to 85 C H Input Low Level Vit 0 3 0 8 V 3 Input High Level Vin 2 0 0 3 V 3 Input High Level XTAL1 and RST Vin 3 5 0 3 V 3 Output Low Voltage at Io 1
5. 7 886 3 5753170 WER HAE 86 21 54151736 Ji 47 86 755 83298787 Http www 100y com tw E ob DS87C530 DS83C530 AVIA AIA EPROM ROM Microcontrollers with Real Time Clock FR ice IC Cae SRR LRT ERT ca FEATURES PIN CONFIGURATIONS 80 52 Compatible 8051 Instruction Set Compatible TOP VIEW Four 8 Bit I O Ports Three 16 Bit Timer Counters 256 Bytes Scratchpad RAM Large On Chip Memory 16kB EPROM OTP 1kB Extra On Chip SRAM for MOVX ROMSIZE Features Selects Effective On Chip ROM Size from DALLAS 0 to 16kB DS87C530 Allows Access to Entire External Memory Map DS83C530 Dynamically Adjustable by Software Useful as Boot Block for External Flash Nonvolatile Functions On Chip Real Time Clock with Alarm Interrupt Battery Backup Support of 1kB SRAM High Speed Architecture 4 Clocks Machine Cycle 8051 12 Runs DC to 33MHz Clock Rates Single Cycle Instruction in 121ns Dual Data Pointer Optional Variable Length MOVX to Access DALLAS Fast Slow RAM Peripherals DS87C530 Power Management Mode DS83C530 Programmable Clock Source Saves Power Runs from crystal 64 or crystal 1024 Provides Automatic Hardware and Software Exit Reduction Mode Disables ALE Two Full Duplex Hardware Serial Ports High Integration Controller Includes Power Fail Reset Early Warning Power Fail Interrupt The High Speed Microcontroller User s Guide must Programmable Watchdog Timer
6. ns 24 gt 0 Data Hold After Read 0 ns t 5 ns 0 Data Float After Read 7 e S 2tcrcr 5 gt 0 2 5 31 tucs 0 ALE Low to Valid Data In ns 26 gt 0 3t 29 tucs 0 Port 0 Address to Valid Data In tavpvi ns x tucst2crcr 29 gt 0 3 5 37 tucs 0 Port 2 Address to Valid Data In tavpv2 ns es tucs 2 5rcr 37 gt 0 0 5 10 0 5 2 1 0 ALE Low to RD or WR Low ns 5 5 gt 0 _ EI 9 tmcs 0 Port 0 Address to RD or WR Low tAVWLI ns 2tcrci 7 870 1 17 s 0 Port 2 Address to RD or WR Low tAVWL2 ns 2 1 6 5 gt 0 Data Valid to WR Transition tovwx 6 ns t 5 tucs 0 Data Hold After Write ns MS 2tcrcr 6 tucs gt 0 RD Low to Address Float tRLAZ Note 1 ns 4 10 tucs 0 RD or WR High to ALE High twHLH ns tcrcr 5 5 gt 0 Note 1 tucs is a time period related to the Stretch memory cycle selection The following table shows the value of tucs for each Stretch selection ME 7 886 3 5753170 Wd TI 86 21 54151736 WE 45 E GI 86 755 83298787 Http www 100 com tw 36 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock MOVX CHARACTERISTICS USING STRETCH MEMORY CYCLES continued
7. 1 or 1024 2 clocks This means software cannot go directly from PMM1 to 2 or visa versa It must return to a 4 clock rate first te d OZ d 886 3 5753170 WERT 86 21 54151736 WEE 86 755 83298787 Http www 100y com tw 18 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock Switchback To return to a 4 clock rate from PMM software can simply select the CD1 and CDO clock control bits to the 4 clocks per cycle state However the DS87C530 DS83C530 provide several hardware alternatives for automatic Switchback If Switchback 1s enabled then the device will automatically return to a 4 clock per cycle speed when an interrupt occurs from an enabled valid external interrupt source A Switchback will also occur when a UART detects the beginning of a serial start bit if the serial receiver is enabled REN 1 Note the beginning of a start bit does not generate an interrupt this occurs on reception of a complete serial word The automatic Switchback on detection of a start bit allows hardware to correct baud rates in time for a proper serial reception A Switchback will also occur when a byte is written to the SBUFO or SBUFI for transmission Switchback is enabled by setting the SWB bit PMR 5 to a 1 in software For an external interrupt Switchback will occur only if the interrupt source could really generate the interrupt For example if INTO is enabled but has a low priori
8. vs FREQUENCY 7 886 3 5753170 MEJ 86 21 54151736 ERED 86 755 83298787 Http www 100y com tw 30 33 MHz FREQUENCY 34 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock AC ELECTRICAL CHARACTERISTICS Note 1 PARAMETER SYMBOL VARISPUE UNITS MIN MAX MIN MAX i External Oscillator 0 33 0 33 F 1 External Crystal 1 33 1 33 MH ALE Pulse Width tig 40 1 5 2 ns Port 0 Address Valid to ALE Low tAVLL 10 0 5 2 ns Address Hold after ALE Low rrAxi Note 2 Note 2 ns ALE low to Valid Instruction In triv 43 2 5terci 33 ns ALE Low to PSEN Low 4 0 5 11 ns PSEN Pulse Width tp pn 55 2tercr 5 ns PSEN Low to Valid Instruction In 37 2tcrci 24 ns Input Instruction Hold after PSEN 0 0 ns Input Instruction Float after PSEN tpxiz 26 5 ns Port 0 Address to Valid Instruction In tAVIVI 59 32 ns Port 2 Address to Valid Instruction In taviv2 68 3 5 38 ns PSEN Low to Address Float Note 2 Note 2 ns Note 1 All parameters apply to both commercial and industrial temperature range operation unless otherwise noted Specifications to 40 are guaranteed by design and are not production tested AC electrical characteristics are not 10096 tested but are characterized and guaranteed by design All signa
9. there are a variety of memory mapped peripherals such as LCDs or UARTS that are slow The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below It allows the user to select a Stretch value between 0 and 7 A Stretch of 0 will result in a two machine cycle MOVX A Stretch of 7 will result in a MOVX of nine machine cycles Software can dynamically change this value depending on the particular memory or peripheral On reset the Stretch value will default to a 1 resulting in a three cycle MOVX for any external access Therefore off chip RAM access is not at full speed This is a convenience to existing designs that may not have fast RAM in place Internal SRAM access is always at full speed regardless of the Stretch setting When desiring maximum speed software should select a Stretch value of 0 When using very slow RAM or peripherals select a larger Stretch value Note that this affects data memory only and the only way to slow program memory access is to use a slower crystal OZ 5 886 3 5753170 7 86 21 54151736 WE ey 86 755 83298787 15 of 47 Http www 100y com tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock Using a Stretch value between 1 and 7 causes the microcontroller to stretch the read write strobe and all related timing Also setup and hold times are increased by 1 clock when using any Stretch greater than 0
10. 0 SYNCHRONOUS MODE HIGH SPEED OPERATION SM2 1 gt TXD CLOCK XTAL 4 WRITE TO SBUF RXD DATA OUT TXD TRANSMIT CLOCK TI RXD Xon DATA IN TXD RECEIVE CLOCK SERIAL PORT 0 SYNCHRONOUS MODE SM2 0 gt TXD CLOCK XTAL 12 LINSNVHL WRITE TO SCON TO CLEAR Ri RXD DATA IN TXD CLOCK Bed H 886 3 5753170 86 21 54151736 7 HA 86 755 83298787 Http www 100y com tw 42 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock POWER CYCLE TIMING INTERRUPT SERVICE ROUTINE M tesu XTAL1 DANAI INTERNAL RESET 4 EPROM PROGRAMMING AND VERIFICATION WAVEFORMS PROGRAMMING VERIFICATION ADDRESS ADDRESS DATA IN DATA OUT EA Vpp ZONTROL SIGNALS 7 886 3 5753170 MEJ 86 21 54151736 WEED 86 755 83298787 Http www 100y com tw 43 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock PACKAGE INFORMATION The package drawing s in this data sheet may not reflect the most current specifications For the latest package outline information go to www maxim ic com DallasPacklnfo _____ NOTE PIN 1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED NEW DRAWNG t MJ
11. 2 CONTROLLING DIMENSIONS ARE IN INCHS B PER ECN 4 9779 52 PIN QUAD PLCC SUGGESTED PAD LAYOUT 0 2 2 2 2 p 2 2 Lt 070 d D 17 Lee onne a m noe sa mU n zr 56 64005 00 2 DO NOT SCALE DWG A 5 5 5 er 1 ew 1 44 7 886 3 5753170 WERE 7J HL 86 21 54151736 WERE 7 E FREI 86 755 83298787 Http www 100y com tw 44 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock PACKAGE INFORMATION continued The package drawing s in this data sheet may not reflect the most current specifications For the latest package outline information go to www maxim ic com DallasPacklnfo 350 DIA GLASS LENS 2 MN AT 040 B 026 032 B 1 013 021 D 780 800 01 750 760 iss NOTES 1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED 2 ALL DIMENSIONS SHOWN ARE IN INCHES N 52 sme IDDALLAS AVLAXL VI MFG ENGR WITH GLASS LENS SIZE PART NO fame Wwe fea Al 7 56 64007 001 DO NOT SCALE DWG sae N A 1 1 OZ 886 3 5753170 86 21 54151736 WERE 7 86 755 83298787 45 of 47 MARKETING
12. 33MHz clock source on XTAL1 Vcc 5 5V RST at ground other pins disconnected Note 6 Stop mode current measured with XTAL1 and RST grounded Vcc 5 5V all other pins disconnected Note 7 Voc OV 3 3V 32 768kHz crystal with 12 5pF load capacitance between RTCX1 and 2 pins RTCE bit set to 1 Note 8 RST Vcc This condition mimics operation of pins in I O mode Port 0 is tri stated in reset and when at a logic high state during mode Note 9 During a 0 0 1 transition a one shot drives the ports hard for two clock cycles This measurement reflects port in transition mode Note 10 When addressing external memory This specification only applies to the first clock cycle following the transition Note 11 This is the current required from an external circuit to hold a logic low level on an I O pin while the corresponding port latch bit is set to 1 This is only the current required to hold the low level transitions from 1 to 0 on an I O pin will also have to overcome the transition current Note 12 Ports 1 2 and 3 source transition current when being pulled down externally It reaches its maximum at approximately 2V Note 13 0 45 lt Vn Voc RST Vcc This condition mimics operation of pins in I O mode Note 14 0 45 lt Vn lt Voc Not a high impedance input This port is a weak address holding latch in Bus Mode Peak current occurs near the input transition point of the latch approximately 2V TYPICAL
13. H H L L L H H Program Encryption Array Address 0 3Fh H L PL 12 75V L H H L H Program Lock LBI H L PL 12 75V H H H H H pus LB2 H L PL 12 75V H H H L L LB3 H L PL 12 75V H L H H L Program Option Register Address FCh p A EH rad H E X Read Signature or Option Registers 30 H L H H L L L L L 31 60 FCh PL indicates pulse to a logic low Table 10 EPROM Lock Bits LOCK BITS LEVEL PROTECTION LB1 LB2 LB3 1 U U U No program lock Encrypted verify if encryption table was programmed Prevent MOVC instructions in external memory from reading 2 P U U program bytes in internal memory EA is sampled and latched on reset Allow no further programming of EPROM 3 P P U Level 2 plus no verify operation Also prevent MOVX instructions in external memory from reading SRAM MOV X in internal memory 4 P P P Level 3 plus no external execution 7 886 3 5753170 Wd 86 21 54151736 Wi HRI 86 755 83298787 Http www 100y com tw 30 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock Figure 7 EPROM Programming Configuration A0 A7 45V PROG VERIFY DATA FO 7 XN TN 6 wN 1 7 6 5 4 3 2 50 49 48 47 oO 8 EAVpp PROGRAM SIGNALS 4 40 ALE PROG PROGRAM SIGNALS BSEN CONTROL SIGNALS CONTROL SIGNALS p26 CONTROL SIGNALS 35 34 27 28 29 30 31 32 33 A8 A13 ROM S
14. High to Vpp 48tci Setup to PROG Low 10 us Vpp Hold after PROG 10 us PROG Width toron 90 110 us Address to Data Valid tavev 48tci cr Enable Low to Data Valid teLov 48tcrcr Data Float after Enable tenoz 0 48tcrcr PROG High to PROG Low tau 10 Note 1 All voltages are referenced to ground A J B 886 3 5753170 WEE 86 21 54151736 86 755 83298787 38 of 47 Http www 100y com tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock EXTERNAL PROGRAM MEMORY READ CYCLE ADDRESS INSTRUCTION ADDRESS 7 IN 7 ADDRESS A8 A15 OUT ADDRESS A8 A15 OUT EXTERNAL DATA MEMORY READ CYCLE WHLH traxi wj ALRH T S INSTRUCTION ADDRESS Y DATA IN ADDRESS IN AO A7 0 tavpv2 tavwL2 4 7 9 886 3 5753170 MEJ H i 86 21 54151736 WERE V 86 755 83298787 Http www 100y com tw 39 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock DATA MEMORY WRITE CYCLE tuu INSTRUCTION ADDRESS ADDRESS IN 0 7 DATA OUT 0 tavwLi ADDRESS 8 15 OUT DATA MEMORY WRITE WITH STRETCH 1 Last Cycle of First Second Third Need Previous Machine gt Machine Instruction gt Instruction Cycle Cycle Cycle Machine Cyc
15. None LIP STATUS 5 Status 1 indicates low priority interrupt in service 0 None XTUP STATUS 4 Status 1 indicates that the crystal has stabilized 1 None SPTAI STATUS 3 Status Serial transmission on serial port 1 0 None SPRAI STATUS 2 Status Serial word reception on serial port 1 0 None SPTAO STATUS 1 Status Serial transmission on serial port 0 0 None SPRAO STATUS 0 Status Serial word reception on serial port 0 0 None d 886 3 5753170 86 21 54151736 86 755 83298787 Http www 100y com tw 21 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock Figure 5 Invoking and Clearing PMM ENTER POWER MANAGEMENT MODE EXITING POWER MANAGEMENT MODE ALLOW HARDWARE TO CAUSE A SNITCPIBACK SOFTWARE DECIDES SWB 1 AND EXTERNAL TO EXIT ACTIVITY OCCURS HARDWARE AUTOMATICALLY CD1 CDO 01 FOR 4 SWITCHES CD1 CDO SET SWB 1 N CHECK AND CLEAR IMPENDING ACTIVITY INVOKE PMM CLOCK SPEED 64 OR 1024 CD1 00 10 FOR 64 CDt CDd 11 FOR 1024 OPERATE WITHOUT CRYSTAL DISABLE CRYSTAL NO FAST SWITCH TO XTAL LOWEST POWER OPERATING STATE 4 788635753170 86 21 54151736 HA VE 86 755 83298787 Http www 100 com tw 22 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock IDLE MODE Setting the Isb of the Power Control register PCON 87h invokes the Idle mode Idle will leav
16. OUTLINE 52 PIN CERQUAD Http www 100 com tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock PACKAGE INFORMATION continued The package drawing s in this data sheet may not reflect the most current specifications For the latest package outline information go to www maxim ic com DallasPacklnfo NOTES 1 DIMENSIONS 01 AND E1 INCLUDE MOLD MISMATCH BUT DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 254 MM ON 01 AND DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED ALLOWABLE DAMBAR PROTRUSION IS 0 08 MM TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION PROTRUSION NOT TO BE LOCATED ON LOWER RADIUS OR FOOT OF LEAD GUAGE PLANE 68277 1 00 REF DETAIL DIMENSIONS ARE IN MILLIMETERS SUGGESTED PAD LAYOUT 52 PIN TQFP 0 10 11 70 1 00 0 32 12 00 10 00 BSC 12 00 10 00 BSC 0 65 BSC 0 60 7 f 886 3 5753170 Wi JJ 86 21 54151736 46 of 47 WERE 86 755 83298787 Http www 100 com tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock DATA SHEET REVISION SUMMARY REVISION DESCRIPTION 070505 1 Added Pb free RoHS compliant part numbers to Ordering Information table 2 Deleted the A from the IPC JEDEC J STD 020 specification in the Absolute Maximum Ratings 3 Removed
17. Preliminary status 4 Soldering temperature parameter now references JEDEC specification 5 Added note to absolute maximums clarifying voltages referenced to ground and storage temperature 6 Updated Icc lite Istop 5 lii and Ir to incorporate errata conditions 040104 7 Added note clarifying DC electrical test conditions 8 Added note clarifying specification applies to first clock cycle following the transition 9 Updated AC and MOVX electrical characteristics with final characterization values 10 Added tayr 2 specification and corrected MOVX timing diagrams to show instead of 11 Updated Igar to incorporate errata conditions 112299 Contact factory for details 1 Added DS83C530 to data sheet 2 Updated PMM operating current estimates 3 Added note to clarify Ij specification 4 Added note to prevent accidental corruption of Watchdog Timer count while changing counter length 070798 5 Changed Igar specification to 1A over extended temperature range 6 Changed minimum oscillator frequency to IMHz when using external crystal 7 Changed RST pulldown resistance from 170kQ to 200kO maximum 8 Corrected Data memory write with stretch diagrams to show falling edge of ALE coincident with rising edge of C3 clock 1 Updated ALE pin description 2 Added note pertaining to erasure window 3 Added note pertaining to internal MOVX SRAM 022097 4 Changed Note 6 fr
18. available with 6pF and 12 5pF load capacitance The tradeoff is that the 6pF uses less power giving longer life while Vcc is off but is more sensitive to noise and board layout The 11 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock 12 5pF crystal uses more power giving a shorter battery backed life but produces a more robust oscillator Bit 6 in the RTC Trim register TRIM 96h must be programmed to specify the crystal type for the oscillator When TRIM 6 1 the circuit expects a 12 5pF crystal When TRIM 6 0 it expects a 6pF crystal This bit will be nonvolatile so these choices will remain while the backup source is present A guard ring connected to the RTC ground should encircle the RTCX1 and RTCX2 pins Backup Energy Source The DS87C530 DS83C530 use an external energy source to maintain timekeeping and SRAM data without Vcc This source can be either a battery or 0 47F super cap and should be connected to the pin The nominal battery voltage is The pin will not source current Therefore a super cap requires an external resistor and diode to supply charge The backup lifetime is a function of the battery capacity and the data retention current drain This drain is specified in the electrical specifications The circuit loads the Vgar only when Vcc has fallen below Thus the actual lifetime depends not only on the current and battery capacity but also on the portion of
19. family M 886 3 5753170 86 21 54151736 ERE 86 755 83298787 Http www 100y com tw 6 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock COMPATIBILITY The 0587 530 0583 530 are fully static CMOS 8051 compatible microcontrollers designed for high performance While remaining familiar to 8051 users the devices have many new features In general software written for existing 8051 based systems works without modification on the DS87C530 DS83C530 The exception is critical timing since the high speed microcontrollers perform its instructions much faster than the original for any given crystal selection The DS87C530 DS83C530 run the standard 8051 instruction set They are not pin compatible with other 8051s due to the timekeeping crystal The DS87C530 DS83C530 provide three 16 bit timer counters full duplex serial port 2 256 bytes of direct RAM plus 1kB of extra MOVX RAM I O ports have the same operation as a standard 8051 product Timers will default to a 12 clock per cycle operation to keep their timing compatible with original 8051 systems However timers are individually programmable to run at the new 4 clocks per cycle if desired The PCA is not supported The DS87C530 DS83C530 provide several new hardware features implemented by new Special Function Registers A summary of these SFRs is provided below PERFORMANCE OVERVIEW The DS87C530 DS83C530 featu
20. indicates it is running from the ring When operating from the ring disable the crystal amplifier by setting the XTOFF bit PMR 3 to a 1 This can only be done when XT RG 0 When changing the clock source the selection will take effect after a one instruction cycle delay This applies to changes from crystal to ring and vise versa However this assumes that the crystal amplifier is running In most cases when the ring is active software previously disabled the crystal to save power If ring operation is being used and the system must switch to crystal operation the crystal must first be enabled Set the XTOFF bit to 0 At this time the crystal oscillation will begin The DS87C530 DS83C530 then provide a warm up delay to make certain that the frequency is stable Hardware will set the XTUP bit STATUS 4 to 1 when the crystal is ready for use Then software should write XT RG to 1 to begin operating from the crystal Hardware prevents writing XT RG to 1 before XTUP 1 The delay between XTOFF 0 and XTUP 1 will be 65 536 crystal clocks in addition to the crystal cycle startup time Switchback has no affect on the clock source If software selects a reduced clock divider and enables the ring a Switchback will only restore the divider speed The ring will remain as the time base until altered by software If there 18 serial activity Switchback usually occurs with enough time to create proper baud rates This is not true if the crystal is off
21. time without power very small lithium cell provides a lifetime of more than 10 years Figure 3 Internal Backup Circuit Wd 7 886 3 5753170 86 21 54151736 ZRH 86 755 83298787 Http www 100y com tw SRAM AND RTC IMPORTANT APPLICATION NOTE The pins on the DS87C530 DS83C530 are generally as resilient as other CMOS circuits They have no unusual susceptibility to electrostatic discharge ESD or other electrical transients However no pin on the DS87C530 DS83C530 should ever be taken to a voltage below ground Negative voltages on any pin can turn on internal parasitic diodes that draw current directly from the battery If a device pin is connected to the outside world where it may be handled or come in contact with electrical noise protection should be added to prevent the device pin from going below 0 3V Some power supplies can give a small undershoot on power up which should be prevented Application Note 93 Design Guidelines for Microcontrollers Incorporating NV RAM discusses how to protect the DS87C530 DS83C530 against these conditions MEMORY RESOURCES Like the 8051 the DS87C530 DS83C530 use three memory areas The total memory configuration of the device is 16kB of ROM 1kB of data SRAM and 256 bytes of scratchpad or direct RAM The 1kB of data 12 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock space SRAM is read write accessible and is memo
22. to a 1 Serial Port 0 Transmit Activity SPTA0 STATUS 1 indicates that the serial port 1s still shifting out a serial transmission STATUS 2 and STATUS 3 provide the same information for Serial Port 1 respectively These bits should be interrogated before entering PMM1 or PMM2 to ensure that no serial port operations are in progress Changing the clock divisor rate during a serial transmission or reception will corrupt the operation MEM 7 886 3 5753170 86 21 54151736 HL G3 86 755 83298787 Http www 100y com tw 19 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock Crystal Ring Operation The DS87C530 DS83C530 allow software to choose the clock source as an independent selection from the instruction cycle rate The user can select crystal based or ring oscillator based operation under software control Power on reset default is the crystal or external clock source The ring may save power depending on the actual crystal speed To save still more power software can then disable the crystal amplifier This process requires two steps Reversing the process also requires two steps The XT RG bit EXIF 3 selects the crystal or ring as the clock source Setting XT RG 1 selects the crystal Setting XT RG 0 selects the ring The EXIF 2 bit serves as a status bit by indicating the active clock source RGMD 0 indicates the CPU is running from the crystal RGMD 1
23. tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock DS87C530 SECURITY OPTIONS The DS87C530 employs a standard three level lock that restricts viewing of the EPROM contents A 64 byte Encryption Array allows the authorized user to verify memory by presenting the data in encrypted form Lock Bits The security lock consists of 3 lock bits These bits select a total of 4 levels of security Higher levels provide increasing security but also limit application flexibility Table 10 shows the security settings Note that the programmer cannot directly read the state of the security lock User software has access to this information as described in the Memory section Encryption Array The Encryption Array allows an authorized user to verify EPROM without allowing the true memory to be dumped During a verify each byte is Exclusive NORed XNOR with a byte in the Encryption Array This results in a true representation of the EPROM while the Encryption is unprogrammed FFh Once the Encryption Array is programmed in a non FFh state the verify value will be encrypted For encryption to be effective the Encryption Array must be unknown to the party that is trying to verify memory The entire EPROM also should be a non FFh state or the Encryption Array can be discovered The Encryption Array is programmed as shown in Table 9 Note that the programmer cannot read the array Also note that the verify operation always uses the En
24. 0 156 25 6 25 390 6 244 33 825 515 6 32 2 Table 5 Typical Operating Current PMMI PMM2 EED hir jp 64 CLOCKS 1024 CLOCKS mA mA mA 11 0592 13 1 5 3 4 8 16 172 6 4 36 25 25 7 8 1 70 33 32 8 9 8 82 OZ d 886 3 5753170 86 21 54151736 HA EI 86 755 83298787 Http www 100y com tw 17 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock CRYSTAL LESS PMM A major component of power consumption in PMM is the crystal amplifier circuit The DS87C530 DS83C530 allow the user to switch CPU operation to an internal ring oscillator and turn off the crystal amplifier The CPU would then have a clock source of approximately 2MHz to 4MHz divided by either 4 64 or 1024 The ring is not accurate so software cannot perform precision timing However this mode allows an additional saving of between 0 5mA and 6 0mA depending on the actual crystal frequency While this saving is of little use when running at 4 clocks per instruction cycle it makes a major contribution when running in or 2 PMM OPERATION Software invokes the PMM by setting the appropriate bits in the SFR area The basic choices are divider speed and clock source There are three speeds 4 64 and 1024 and two clock sources crystal ring Both the decisions and the controls are separate Software will typically select the clock speed firs
25. 0y com tw 37 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock EXPLANATION OF AC SYMBOLS In an effort to remain compatible with the original 8051 family this device specifies the same parameters as such devices using the same symbols For completeness the following is an explanation of the symbols t Time I Instruction W WRsignal A Address P PSEN X No longer a valid logic C Clock Q Output data level D Input data X RD signal Z Tri State H Logic level high V Valid L Logic level low POWER CYCLE TIMING CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNIIS NOTES Cycle Startup Time tesu 1 8 ms 1 Power On Reset Delay tpor 65 536 2 Note 1 Startup time for crystals varies with load capacitance and manufacturer Time shown is for 11 0592MHz crystal manufactured by Fox Note 2 Reset delay is a synchronous counter of crystal oscillations after crystal startup At 33MHz this time is 1 99ms EPROM PROGRAMMING AND VERIFICATION Voc 4 5V to 5 5V Ta 21 C to 27 C PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Programming Voltage Vpp 12 5 13 0 V 1 Programming Supply Current Ipp 50 mA Oscillator Frequency l tcicr 4 6 MHz Address Setup to PROG Low 48tci Address Hold after PROG GHAX 48tci Data Setup to PROG Low 48tci cr Data Hold after PROG 48tci cr Enable
26. 530 EPROM ROM Microcontrollers with Real Time Clock DS83C530 ROM Verification The DS83C530 memory contents can be verified using a standard EPROM programmer The memory address to be verified is placed on the pins shown in Figure 7 and the programming control pins are set to the levels shown in Table 9 The data at that location is then asserted on port 0 DS83C530 Signature The Signature bytes identify DS83C530 to EPROM programmers This information is at programming addresses 30h 31h and 60h Because Mask ROM devices are not programmed in device programmers most designers will find little use for the feature and it is included only for compatibility ADDRESS VALUE MEANING 30h DAh Manufacturer 31h 31h Model 60h Olh Extension W H 886 3 5753170 86 21 54151736 86 755 83298787 Http www 100y com tw 32 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock ABSOLUTE MAXIMUM RATINGS Voltage Range on Pin Relative to 0 3V to 0 5V Voltage Range on Vcc Relative to 0 3V to 6 0V Operating Temperature 2 2 2 22 2 9 0 C to 70 C Storage emperature Range AN a see 55 C to 125 C Note 1 Soldering
27. 6mA 0 15 0 45 V 3 Output Low Voltage Ports 0 2 ALE and PSEN at Io 3 2mA Vor 0 15 0 45 V 3 Output High Voltage Ports 1 2 3 ALE PSEN at Ios 3 S0UA 2 4 V 3 8 Output High Voltage Ports 1 2 3 at 1 5mA Vom 24 Output High Voltage Port 0 in Bus Mode 8mA Vous 2 4 V 3 10 Input Low Current Ports 1 2 3 at 0 45V In 70 11 Transition Current from 1 to 0 Ports 1 2 3 at 2V 800 12 B H 886 3 5753170 Wd 86 21 54151736 WE 7J FREYI 86 755 83298787 33 of 47 Http www 100y com tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock DC ELECTRICAL CHARACTERISTICS continued Vcc 4 5V to 5 5V 40 C to 85 C PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Port 0 EA Pins I O Mode I 10 10 uA 13 Input Leakage Port 0 Bus Mode Ij 300 300 14 RST Pulldown Resistance Rest 50 200 kQ Note 1 Storage temperature is defined as the temperature of the device when Vcc and Vear OV In this state the contents of SRAM are not battery backed and are undefined Note 2 All parameters apply to both commercial and industrial temperature operation unless otherwise noted Note 3 All voltages are referenced to ground Note 4 Active current measured with 33MHz clock source on XTAL1 Vcc RST 5 5V other pins disconnected Note 5 Idle mode current measured with
28. 7 8051 SCONI TH or from Serial Port 1 3Bh 8 DALLAS INT2 External Interrupt 2 43h 9 DALLAS INT3 External Interrupt 3 4Bh 10 DALLAS INT4 External Interrupt 4 53h 11 DALLAS INTS External Interrupt 5 5Bh 12 DALLAS WDTI Watchdog Timeout Interrupt 63h 13 DALLAS RTCI RTC Interrupt 6Bh 14 DALLAS 7 4 886 3 5753170 JJ H i 86 21 54151736 WE E VE 86 755 83298787 Http www 100y com tw 27 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock TIMED ACCESS PROTECTION It is useful to protect certain SFR bits from an accidental write operation The Timed Access procedure stops an errant CPU from accidentally changing these bits It requires that the following instructions precede a write of a protected bit MOV 0C7h MOV OC7h 55h Writing an AAh and then a 55h to the Timed Access register location C7h opens a three cycle window for write access The window allows software to modify a protected bit s If these instructions do not immediately precede the write operation then the write will not take effect The protected bits are 0 BGS Bandgap Select WDCON 6 POR Power On Reset flag WDCON 1 EWT Enable Watchdog Reset WDCON 0 RWT Restart Watchdog WDCON 3 WDIF Watchdog Interrupt Flag ROMSIZE 2 RMS2 ROM Size Select 2 ROMSIZE 1 RMSI ROM Size Select 1 ROMSIZE 0 RMSO ROM Size Select 0 TRIM 7 0 Trim Functions RTCC 2 RTCWE RTC W
29. LCC TQFP 52 45 5 Processor Power Supply 1 25 18 46 GND Processor Digital Circuit Ground 29 22 Veco 5V RTC Supply is isolated from to isolate the RTC from digital noise 26 19 GND2 RTC Circuit Ground Reset Input This pin contains a Schmitt voltage input to recognize external active 12 5 RST high reset inputs The pin also employs an internal pulldown resistor to allow for a combination of wired OR external reset sources An RC is not required for power up as the device provides this function internally 23 16 XTAL2 Crystal Oscillator Pins XTAL1 and XTAL2 provide support for parallel resonant AT cut crystals XTALI acts also as an input if there is an external clock source in 24 17 XTALI place of a crystal XTAL2 is the output of the crystal amplifier he H 886 3 5753170 86 21 54151736 WERE HA RHI 86 755 83298787 4 of 47 Http www 100y com tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock PIN DESCRIPTION continued FIN NAME FUNCTION PLCC TQFP Program Store Enable Output This active low signal is a chip enable for optional 38 31 PSEN external ROM memory PSEN provides an active low pulse and is driven high when external ROM is not being accessed Address Latch Enable Output This pin latches the external address LSB from the multiplexed address data bus on Port 0 This signal is c
30. PECIFIC FEATURES DS83C530 The DS83C530 supports a subset of the EPROM features found on the DS87C530 CONTROL SIGNALS ap E o CONTROL SIGNALS 77 14 7 15 CONTROL SIGNALS CONTROL SIGNALS SECURITY OPTIONS Lock Bits The DS83C530 employs a lock that restricts viewing of the ROM contents When set the lock will prevent MOVC instructions in external memory from reading program bytes in internal memory When locked the EA pin is sampled and latched on reset The lock setting is enabled or disabled when the devices are manufactured according to customer specifications The lock bit cannot be read in software and its status can only be determined by observing the operation of the device Encryption Array The DS83C530 Encryption Array allows an authorized user to verify ROM without allowing the true memory contents to be dumped During a verify each byte is Exclusive NORed XNOR with a byte in the Encryption Array This results in a true representation of the ROM while the Encryption is unprogrammed FFh Once the Encryption Array is programmed in a non FFh state the Encryption Array is programmed or optionally left unprogrammed when the devices are manufactured according to customer specifications 7 4 886 3 5753170 WERE 86 21 54151736 86 755 83298787 Http www 100y com tw 31 of 47 DS87C530 DS83C
31. T1 BITO ADDRESS PO P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 80h SP 8th DPL 82h DPH 83h DPLI 84h DPHI 85h DPS 0 0 0 0 0 0 0 SEL 86h PCON SMOD 0 SMODO X STOP IDLE 87h TCON 1 TRI 0 0 IE ITI IEO ITO 88h TMOD GATE C T MI MO GATE C T M1 MO 89h TLO 8Ah TL1 8Bh THO 8Ch THI 8Dh CKCON WDI WD0 T2M TIM TOM MD2 MD1 8Eh P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 90h EXIF IES 4 IE3 IE2 XT RG RGMD RGSL BGS 91h TRIM E4K X12 6 TRM2 TRM2 TRMO 96h SCONO SMOFE 0 SMIO SM20 RENO TB80 RB8 0 TI 0 RI 0 98h SBUFO 99h 2 2 7 2 6 2 5 P2 4 P2 3 P2 2 P2 1 P2 0 0 IE EA ESI ET2 ESO ETI EXI ETO A8h SADDRO A9h SADDRI AAh P3 P3 7 P3 6 P3 5 P34 P3 3 P3 2 P3 1 P3 0 BOh IP PSI PT2 PSO PTO 8 SADENO B9h SADENI BAh SCONI 5 0 1 5 1 1 SM21 REN1 TB81 RB8 1 TI 1 RI 1 COh SBUF1 Clh ROMSIZE RMS2 RMSI 50 C2h PMR CDI SWB XTOFF ALEOFF DME1 DMEO C4h STATUS PIP HIP LIP XTUP 1 SPRA1 SPTAO SPRAO C5h TA C7h T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RI2 C8h T2MOD T20E DCEN C9h RCAP2L CAh RCAP2H CBh d OZ 886 3 5753170 WEE 7 86 21 54151736 9 of 47 MEJ GE 86 755 83298787 Http www 100 com tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock Table 1 Special Functio
32. This results in a wider read write strobe and relaxed interface timing allowing more time for memory peripherals to respond The timing of the variable speed MOVX is in the Electrical Specifications section Table 3 shows the resulting strobe widths for each Stretch value The memory Stretch uses the Clock Control Special Function Register at SFR location 8Eh The Stretch value is selected using bits CKCON 2 0 In the table these bits are referred to as M2 through MO The first Stretch default allows the use of common 120ns RAMs without dramatically lengthening the memory access Table 3 Data Memory Cycle Stretch Values MEMORY CYCLES RD OR WR STROBE Se eM M2 MI M0 WIDTH IN CLOCKS ns 0 0 0 2 forced internal 2 60 0 0 1 3 default external 4 121 0 1 0 4 8 242 0 1 1 5 12 364 1 0 0 6 16 485 1 0 1 7 20 606 1 1 0 8 24 727 1 1 1 9 28 848 DUAL DATA POINTER The timing of block moves of data memory is faster using the Dual Data Pointer DPTR The standard 8051 DPTR is a 16 bit value that is used to address off chip data RAM or peripherals In the DS87C530 DS83C530 the standard data pointer is called DPTR located at SFR addresses 82h and 83h These are the standard locations Using DPTR requires no modification of standard code The new DPTR at SFR 84h and 85h is called DPTR1 The DPTR Select bit DPS chooses the active pointer Its location is the Isb of the SFR locat
33. and the CPU is running from the ring If sending a serial character that wakes the system from crystal less PMM then it should be a dummy character of no importance with a subsequent delay for crystal startup Table 6 is a summary of the bits relating to PMM and its operation The flow chart below illustrates a typical decision set associated with PMM Wed 7 886 3 5753170 86 21 54151736 86 755 83298787 Http www 100 com tw 20 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock Table 6 PMM Control and Status Bit Summary NAME LOCATION FUNCTION RESET WRITE ACCESS 0 to 1 only when XT RG EXIF 3 Control XT RG 1 runs from crystal or external x XTUP and clock XT RG 0 runs from internal ring oscillator XTOFF 0 RGMD EXIF 2 Status RGMD 1 CPU clock ring RGMD 0 0 None CPU clock crystal Write CD1 0 10 or Control CD1 0 01 4 clocks CS1 0 10 PMMI e CDI CDO PMR7 PMR 6 CD1 0 11 2 0 1 only from CDI 0 Control SWB 1 hardware invokes switchback to 4 SWB clocks SWB 0 hardware switchback i Unrestricted XTOFF PMR3 Control Disables crystal operation after ring is 0 1 only when XT RG selected 0 PIP STATUS 7 Status 1 indicates a power fail interrupt in service 0 None HIP STATUS 6 Status 1 indicates high priority interrupt in service 0
34. be used in conjunction with this data sheet Download it 14 Total Interrupt Sources with Six External at www maxim ic com microcontrollers Note Some revisions of this device may incorporate deviations from published specifications known as errata Multiple revisions of any device may be simultaneously available through various sales channels For information about device errata click here www maxim ic com errata 1 of 47 REV 070505 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock ORDERING INFORMATION MAX CLOCK PART TEMP RANGE SPEED PIN PACKAGE MHz DS87C530 QCL 0 C to 70 C 33 52 PLCC DS87C530 QCL 0 C to 70 C 33 52 PLCC DS87C530 QNL 40 C to 85 C 33 52 PLCC DS87C530 QNL 40 C to 85 C 33 52 PLCC DS87C530 KCL 0 C to 70 C 33 52 Windowed CLCC DS87C530 ECL 0 C to 70 C 33 52 TQFP DS87C530 ECL 0 C to 70 C 33 52 TQFP DS87C530 ENL 40 C to 85 C 33 52 TQFP DS87C530 ENL 40 C to 85 C 33 52 TQFP DS83C530 QCL 0 C to 70 C 33 52 PLCC DS83C530 QCL 0 C to 70 C 33 52 PLCC DS83C530 QNL 40 C to 85 C 33 52 PLCC DS83C530 QNL 40 C to 85 C 33 52 PLCC DS83C530 ECL 0 C to 70 C 33 52 TQFP DS83C530 ECL 0 C to 70 C 33 52 TQFP DS83C530 ENL 40 C to 85 C 33 52 TQFP DS83C530 ENL 40 C to 85 C 33 52 TQFP Denotes a Pb free RoHS compliant device The windowed ceramic LCC package
35. bled the RTC maintains time for the life of the backup source even when Vcc is removed The RTC will maintain an accuracy of 2 minutes per month at 25 C Under no circumstances are negative voltages of any amplitude allowed on any pin while the device is in data retention mode Vcc lt Negative voltages will shorten battery life possibly corrupting the contents of internal SRAM and the RTC Figure 2 Real Time Clock SUB SECONDS SECONDS MINUTES DAY OF WEEK 8 BITS 6 BITS 6 BITS 3 5 SUB SECONDS DS MINUTES HOURS CALENDAR REGISTER REGISTER REGISTER REGISTER REGISTERS ko 886 3 5753170 MEJ ETLER 86 21 54151736 WE 453 H PREJ 86 755 83298787 Http www 100y com tw NONVOLATILE RAM The 1k x 8 on chip SRAM can be nonvolatile if an external backup energy source is used This allows the device to log data or to store configuration settings Internal switching circuits will detect the loss of Vcc and switch SRAM power to the backup source on the pin The 256 bytes of direct RAM are not affected by this circuit and are volatile CRYSTAL AND BACKUP SOURCES To use the unique functions of the DS87C530 DS83C530 a 32 768kHz timekeeping crystal and a backup energy source are needed The following describes guidelines for choosing these devices Timekeeping Crystal The DS87C530 DS83C530 can use a standard 32 768kHz crystal as the RTC time base There are two versions of standard crystals
36. ch instruction byte The user concerned with precise program timing should examine the timing of each instruction for familiarity with the changes Note that a machine cycle now requires just 4 clocks and provides one ALE pulse per cycle Many instructions require only one cycle but some require five In the original architecture all were one or two cycles except for MUL and DIV Refer to the High Speed Microcontroller User s Guide for details and individual instruction timing SPECIAL FUNCTION REGISTERS Special Function Registers SFRs control most special features of the DS87C530 DS83C530 This allows the device to incorporate new features but remain instruction set compatible with the 8051 EQUATE statements can be used to define the new SFR to an assembler or compiler All SFRs contained in the standard 80C52 are duplicated in this device Table 1 shows the register addresses and bit locations The High Speed Microcontroller User s Guide describes all SFRs te OZ 886 3 5753170 JJ HL 86 21 54151736 V EI 86 755 83298787 Http www 100 com tw 8 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock Table 1 Special Function Register Locations Functions not present in the 80C52 are in bold REGISTER BIT7 BIT6 BITS BIT4 BIT 3 BIT 2 BI
37. cryption Array The array has no impact while FFh Simply programming the array to a non FFh state will cause the encryption to function Other EPROM Options The DS87C530 has user selectable options that must be set before beginning software execution These options use EPROM bits rather than SFRs Program the EPROM selectable options as shown in Table 9 The Option Register sets or reads these selections The bits in the Option Control Register have the following function Bits 7 to 4 Reserved program to 1 Bit 3 Watchdog POR default Set 1 Watchdog reset function is disabled on power up Set 0 Watchdog reset function is enabled automatically Bits 2 to 0 Reserved Program to 1 DS87C530 Signature The Signature bytes identify the product and programming revision to EPROM programmers This information is at programming addresses 30h 31h and 60h This information is as follows ADDRESS VALUE MEANING 30h DAh Manufacturer 31h 30h Model 60h Olh Extension he 8 886 3 5753170 86 21 54151736 WEE 7 86 755 83298787 29 of 47 Http www 100y com tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock Table 9 EPROM Programming Modes MODE RST PSEN ALE PROG EA VPP P2 6 P2 7 P3 3 P3 6 P3 7 Program Code Data H L PL 12 75V L H H H H Verify Code Data H L
38. curs automatically needing no action from the software Refer to the Electrical Specifications section for the exact value of POWER FAIL INTERRUPT The voltage reference that sets a precise reset threshold also generates an optional early warning power fail interrupt PFI When enabled by software the processor will vector to program memory address 0033h if Vcc drops below Vprw PFI has the highest priority The PFI enable is in the Watchdog Control SFR WDCON D8h Setting WDCON 5 to logic 1 will enable the PFI Application software can also H d 886 3 5753170 WERE 86 21 54151736 25 of 47 WERE E 86 755 83298787 Http www 100y com tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock read the PFI flag at WDCON 4 A PFI condition sets this bit to a 1 The flag is independent of the interrupt enable and software must manually clear it If the PFI is enabled and the bandgap select bit BGS is set a PFI will bring the device out of Stop mode WATCHDOG TIMER To prevent software from losing control the DS87C530 DS83C530 include a programmable watchdog timer The Watchdog is a free running timer that sets a flag if allowed to reach a preselected timeout It can be re started by software A typical application is to select the flag as a reset source When the Watchdog times out it sets its flag which generates reset Software must restart the timer before it reaches its t
39. e The MOVxX instruction accesses the on chip data memory Although physically on chip software treats this area as though it was located off chip The 1 of SRAM is between address 0000h and 03FFh Access to the on chip data RAM is optional under software control When enabled by software the data SRAM is between 0000h and 03FFh Any MOVX instruction that uses this area will go to the on chip RAM while enabled MOVX addresses greater than 03FFh automatically go to external memory through Ports 0 and 2 When disabled the 1kB memory area is transparent to the system memory map Any MOVX directed to the space between 0000h and FFFFh goes to the expanded bus on Ports 0 and 2 This also is the default condition This default allows the DS87C530 DS83C530 to drop into an existing system that uses these addresses for other hardware and still have full compatibility 7 4 886 3 5753170 86 21 54151736 HER J 86 755 83298787 Http www 100 com tw 14 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock The on chip data area is software selectable using 2 bits in the Power Management Register at location C4h This selection is dynamically programmable Thus access to the on chip area becomes transparent to reach off chip devices at the same addresses The control bits are DMEI PMR 1 DMEO 0 They have the following operation Table 2 Data Memory Access Control
40. e since any external circuit that writes to the port will overcome the weak pullup When software writes a 5 50 P12 0 to any port pin the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs Writing a after the port has been at 0 will cause a strong transition driver to turn on followed by a weaker sustaining pullup 6 al Once the momentary strong driver turns off the port again becomes the output high and input state The alternate modes of Port 1 are outlined as follows 7 52 1 4 Port Alternate Function P1 0 T2 External I O for Timer Counter 2 8 4 P1 5 P1 1 T2EX Timer Counter 2 Capture Reload Trigger P1 2 RXDI Serial Port 1 Input P1 3 TXDI Serial Port 1 Output 9 2 1 6 P1 4 INT2 External Interrupt 2 Positive Edge Detect P1 5 INT3 External Interrupt 3 Negative Edge Detect P1 6 INT4 External Interrupt 4 Positive Edge Detect 10 3 P1 7 P1 7 INTS External Interrupt 5 Negative Edge Detect 44 7 4 886 3 5753170 86 21 54151736 WEE E EREI 86 755 83298787 Http www 100y com tw 5 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock PIN DESCRIPTION continued FIN NAME FUNCTION PLCC TQFP 30 23 P2 0 AD8 Port 2 8 15 I O Port 2 is a bidirectional I O port The reset condition of 31 24 P2 1 AD9 Port 2 is logic high In this
41. e internal clocks serial ports and timers running Power consumption drops because the CPU is not active Since clocks are running the Idle power consumption is a function of crystal frequency It should be approximately one half the operational power at a given frequency The CPU can exit the Idle state with any interrupt or a reset Idle is available for backward software compatibility The system can now reduce power consumption to below Idle levels by using or PMM2 and running STOP MODE ENHANCEMENTS Setting bit 1 of the Power Control register PCON 87h invokes the Stop mode Stop mode is the lowest power state since it turns off all internal clocking The Icc of a standard Stop mode is approximately 1 uA but is specified in the Electrical Specifications The CPU will exit Stop mode from an external interrupt or a reset condition Internally generated interrupts timer serial port watchdog are not useful since they require clocking activity One exception is that a RTC interrupt can cause the device to exit Stop mode This provides a very power efficient way of performing infrequent yet periodic tasks The DS87C530 DS83C530 provide two enhancements to the Stop mode As documented below the device provides a bandgap reference to determine Power fail Interrupt and Reset thresholds The default state is that the bandgap reference is off while in Stop mode This allows the extremely low power state mentioned above A user can opt
42. eature allows software to select a reduced emission mode This disables the ALE signal when it is unneeded The DS83C530 is a factory mask ROM version of the DS87C530 designed for high volume cost sensitive applications It is identical in all respects to the DS87C530 except that the 16kB of EPROM is replaced by a user supplied application program All references to features of the DS87C530 will apply to the DS83C530 with the exception of EPROM specific features where noted Please contact your local Dallas Semiconductor sales representative for ordering information Note The DS87C530 DS83C530 are monolithic devices A user must supply an external battery or super cap and a 32 768kHz timekeeping crystal to have permanently powered timekeeping or nonvolatile RAM The DS87C530 DS83C530 provide all the support and switching circuitry needed to manage these resources d H d 886 3 5753170 86 21 54151736 E EI 86 755 83298787 Http www 100 com tw 3 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock Figure 1 Block Diagram P1 0 P1 7 P3 0 P3 7 RT LATCH zi SERIAL PORT 1 PIN DESCRIPTION 2 ux REAL TIME CONTROL A CLOCK ADO AD7 DS87C530 DECODE CLOCKS AND MEMORY CONTROL WATCHDOG TIMER P2 0 P2 7 PIN NAME FUNCTION P
43. es with every instruction cycle MR OZ 886 3 5753170 WE JJ 86 21 54151736 E 86 755 83298787 24 47 Http www 100 com tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock PERIPHERAL OVERVIEW The DS87C530 DS83C530 provide several of the most commonly needed peripheral functions in microcomputer based systems These new functions include a second serial port power fail reset Power fail interrupt and a programmable watchdog timer These are described below and more details are available in the High Speed Microcontroller User s Guide SERIAL PORTS The DS87C530 DS83C530 provide a serial port UART that is identical to the 80C52 In addition it includes a second hardware serial port that is a full duplicate of the standard one This port optionally uses pins P1 2 RXDI and P1 3 TXDI It has duplicate control functions included in new SFR locations Both ports can operate simultaneously but can be at different baud rates or even in different modes The second serial port has similar control registers SCON1 COh SBUFI Clh to the original The new serial port can only use Timer 1 for timer generated baud rates TIMER RATE CONTROL There is one important difference between the DS87C530 DS83C530 and 8051 regarding timers The original 8051 used 12 clocks per cycle for timers as well as for machine cycles The DS87C530 DS83C530 architecture normally uses 4 clocks per mac
44. hine cycle However in the area of timers and serial ports the DS87C530 DS83C530 will default to 12 clocks per cycle on reset This allows existing code with real time dependencies such as baud rates to operate properly If an application needs higher speed timers or serial baud rates the user can select individual timers to run at the 4 clock rate The Clock Control register CKCON 8Eh determines these timer speeds When the relevant CKCON bit is logic 1 the DS87C530 DS83C530 use 4 clocks per cycle to generate timer speeds When the bit is a 0 the DS87C530 uses 12 clocks for timer speeds The reset condition is a 0 5 selects the speed of Timer 2 CKCON 4 selects Timer 1 and CKCON 3 selects Timer 0 Unless a user desires very fast timing it is unnecessary to alter these bits Note that the timer controls are independent POWER FAIL RESET The DS87C530 DS83C530 use a precision bandgap voltage reference to decide if Vcc is out of tolerance While powering up the internal monitor circuit maintains a reset state until Vcc rises above the level Once above this level the monitor enables the crystal oscillator and counts 65 536 clocks It then exits the reset state This power on reset POR interval allows time for the oscillator to stabilize system needs no external components to generate a power related reset Anytime Vcc drops below Vest aS in power failure or a power drop the monitor will generate and hold a reset It oc
45. imeout or the processor is reset Software can select one of four timeout values Then it restarts the timer and enables the reset function After enabling the reset function software must then restart the timer before its expiration or hardware will reset the CPU Both the Watchdog Reset Enable and the Watchdog Restart control bits are protected by a Timed Access circuit This prevents errant software from accidentally clearing the Watchdog Timeout values are precise since they are a function of the crystal frequency as shown in Table 7 For reference the time periods at 33MHz also are shown The Watchdog also provides a useful option for systems that do not require a reset circuit It will set an interrupt flag 512 clocks before setting the reset flag Software can optionally enable this interrupt source The interrupt is independent of the reset A common use of the interrupt is during debug to show developers where the Watchdog times out This indicates where the Watchdog must be restarted by software The interrupt also can serve as a convenient time base generator or can wake up the processor from power saving modes The Watchdog function is controlled by the Clock Control CKCON S8Eh Watchdog Control WDCON D8h and Extended Interrupt Enable EIE E8h SFRs CKCON 7 and CKCON 6 WD1 and WDO respectively and they select the Watchdog timeout period as shown in Table 7 Table 7 Watchdog Timeout Values
46. ion 86h No other bits in register 86h have any effect and are 0 The user switches between data pointers by toggling the Isb of register 86h The increment INC instruction is the fastest way to accomplish this DPTR related instructions use the currently selected DPTR for any activity Therefore it takes only one instruction to switch from a source to a destination address Using the Dual Data Pointer saves code from needing to save source and destination addresses when doing a block move The software simply switches between DPTR and 1 once software loads them The relevant register locations are as follows DPL 82h Low byte original DPTR DPH 83h High byte original DPTR DPLI 84h Low byte new DPTR DPHI 85h High byte new DPTR DPS 86h DPTR Select Isb MEM 7 d 886 3 5753170 WERT 86 21 54151736 86 755 83298787 Http www 100y com tw 16 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock POWER MANAGEMENT Along with the standard Idle and power down Stop modes of the standard 80C52 the DS87C530 DS83C530 provide a new Power Management Mode This mode allows the processor to continue functioning yet to save power compared with full operation The DS87C530 DS83C530 also feature several enhancements to Stop mode that make it more useful POWER MANAGEMENT MODE PMM Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU to run soft
47. ionally choose to have the bandgap enabled during Stop mode With the bandgap reference enabled PFI and Power fail Reset are functional and are a valid means for leaving Stop mode This allows software to detect and compensate for a brownout or power supply sag even when in Stop mode In Stop mode with the bandgap enabled Icc will be approximately 504A compared with 1uA with the bandgap off If a user does not require a Power fail Reset or Interrupt while in Stop mode the bandgap can remain disabled Only the most power sensitive applications should turn off the bandgap as this results in an uncontrolled power down condition The control of the bandgap reference is located in the Extended Interrupt Flag register EXIF 91h Setting BGS EXIF 0 to a 1 will keep the bandgap reference enabled during Stop mode The default or reset condition is with the bit at a logic 0 This results in the bandgap being off during Stop mode Note that this bit has no control of the reference during full power PMM or Idle modes The second feature allows an additional power saving option while also making Stop easier to use This is the ability to start instantly when exiting Stop mode It is the internal ring oscillator that provides this feature This ring can be a clock source when exiting Stop mode in response to an interrupt The benefit of the ring oscillator is as follows Using Stop mode turns off the crystal oscillator and all internal clocks to save powe
48. is intrinsically Pb free MR 7 886 3 5753170 WERE 86 21 54151736 E PREI 86 755 83298787 Http www 100 com tw 2 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock DETAILED DESCRIPTION DS87C530 DS83C530 EPROM ROM microcontrollers with a real time clock RTC are 8051 compatible microcontrollers based on the Dallas Semiconductor high speed core They use 4 clocks per instruction cycle instead of the 12 used by the standard 8051 They also provide a unique mix of peripherals not widely available on other processors They include an on chip RTC and battery backup support for an on chip 1k x 8 SRAM The new Power Management Mode allows software to select reduced power operation while still processing A combination of high performance microcontroller core RTC battery backed SRAM and power management makes the DS87C530 DS83C530 ideal for instruments and portable applications They also provide several peripherals found on other Dallas high speed microcontrollers These include two independent serial ports two data pointers on chip power monitor with brownout detection and a watchdog timer Power Management Mode PMM allows software to select a slower CPU clock While default operation uses four clocks per machine cycle the PMM runs the processor at 64 or 1024 clocks per cycle There is a corresponding drop in power consumption when the processor slows The EMI reduction f
49. le MOVX Instruction 9 es eo es eo ei ci es T LL LLG m MN Next Instr Instruction Address Data MOVX Data Address MOVX Next Address Instruction instruction Read 886 3 5753170 MEJ 86 21 54151736 86 755 83298787 Http www 100 com tw 40 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock DATA MEMORY WRITE WITH STRETCH 2 Last Cycle Second Fourth of Previous a Machine 4 Machine machine gt ja Machine ed Instruction Cycle Cycle Cycle Cycle Machine R MOVX Instruction Cree c1 c1 FERHTLFUEFLELELTUTEFTTAE UL Next Instr MOVX Instruction Address Data MOVX Data Address Nex Address Instruction instruction Read FOUR CYCLE DATA MEMORY WRITE STRETCH VALUE 2 EXTERNAL CLOCK DRIVE 7 886 3 5753170 Wd JJ H i 86 21 54151736 WE 45 86 755 83298787 Http www 100y com tw 41 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock SERIAL PORT MODE 0 TIMING SERIAL PORT
50. le software can simply check the elapsed number of minutes by reading one register Alternately it can read the complete time of day including subseconds in only four registers The calendar stores its data in binary form While this requires software translation it allows complete flexibility as to the exact value A user can start the calendar with a variety of selections since it is simply a 16 bit binary number of days This number allows a total range of 179 years beginning from 0000 The RTC features a programmable alarm condition A user selects the alarm time When the RTC reaches the selected value it sets a flag This will cause an interrupt if enabled even in Stop mode The alarm consists of a comparator that matches the user value against the RTC actual value A user can select a match for 1 or more of the sub seconds seconds minutes or hours This allows an interrupt 10 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock automatically to occur once per second once per minute once per hour or once per day Enabling interrupts with no match will generate an interrupt 256 times per second Software enables the timekeeper oscillator using the RTC enable bit in the RTC Control register F9h This starts the clock It can disable the oscillator to preserve the life of the backup energy source if unneeded Values in the RTC Control register are maintained by the backup source through power failure Once ena
51. ls are characterized with load capacitance of 80pF except Port 0 ALE PSEN RD and WR with 100pF Interfacing to memory devices with float times turn off times over 25ns may cause contention This will not damage the parts but will cause an increase in operating current Specifications assume a 5096 duty cycle for the oscillator Port 2 and ALE timing will change in relation to duty cycle variation Note 2 Address is driven strongly until ALE falls and is then held in a weak latch until overdriven externally 7 8886 3 5753170 86 21 54151736 HEJ HL VENI 86 755 83298787 Http www 100y com tw 35 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock MOVX CHARACTERISTICS USING STRETCH MEMORY CYCLES VARIABLE CLOCK PARAMETER SYMBOL UNITS STRETCH MIN MAX l 5terer 5 tucs 0 Data Access ALE Pulse Width traria m ns yO 2tcrcr 5 gt 0 0 5 2 tucs 0 Port 0 Address Valid to ALE Low tAvLL2 pe ns ate tcrcr 5 gt 0 Address Hold After ALE Low for 0 5 10 0 MOVX Writ tux a tcrcr 7 tmcs gt 0 2tcrcr 5 tucs 0 RD Pulse Width trLRH ns tmcs 10 gt 0 2tcrcr 5 tucs 0 WR Pulse Width twrLwH ns tmcs 10 870 2 22 0 RD Low Valid Data In
52. m execution because program code from 4kB to 16kB 1000h 3FFFh is no longer located on chip This could result in code misalignment and execution of an invalid instruction The recommended method is to modify the ROMSIZE register from a location in memory that will be internal or external both before and after the operation In the above example the instruction which modifies the ROMSIZE register should be located below the 4kB 1000h boundary so that it will be unaffected by the memory modification The same precaution should be applied if the internal program memory size is modified while executing from external program memory Off chip memory is accessed using the multiplexed address data bus on PO and the MSB address on P2 While serving as a memory bus these pins are not I O ports This convention follows the standard 8051 method of expanding on chip memory Off chip ROM access also occurs if the EA pin is a logic 0 EA overrides all bit settings The PSEN signal will go active low to serve as a chip enable or output enable when Ports 0 and 2 fetch from external ROM Figure 4 ROM Memory Map ROM SIZE ADJUSTABLE DEFAULT 16K BYTES ROM SIZE IGNORED FFFFh 0 OFF CHIP OFF CHIP USER SELECTABLE o000h L DATA MEMORY ACCESS Unlike many 8051 derivatives the DS87C530 DS83C530 contain on chip data memory The devices also contain the standard 256 bytes of RAM accessed by direct instructions These areas are separat
53. n the timer has completely timed out This flag is normally associated with a CPU reset and allows software to determine the reset source EWT WDCON 1 is the enable for the Watchdog Timer reset function RWT WDCON 0 is the bit that software uses to restart the Watchdog Timer Setting this bit restarts the timer for another full interval Application software must set this bit before the timeout Both of these bits are protected by Timed Access discussed below As mentioned previously WD1 and 0 CKCON 7 and 6 select the timeout The Reset Watchdog Timer bit WDCON 0 should be asserted prior to modifying the Watchdog Timer Mode Select bits WD1 WDO to avoid corruption of the watchdog count Finally the user can enable the Watchdog Interrupt using EWDI EIE 4 INTERRUPTS The DS87C530 DS83C530 provide 14 interrupt sources with three priority levels The Power Fail Interrupt PFI has the highest priority Software can assign high or low priority to other sources All interrupts that are new to the 8051 family except for the PFI have a lower natural priority than the originals Table 8 Interrupt Sources and Priorities NAME FUNCTION VECTOR N anig 8051 DALLAS PFI Power Fail Interrupt 33h 1 DALLAS INTO External Interrupt 0 03h 2 8051 TFO Timer 0 OBh 3 8051 INTI External Interrupt 1 13h 4 8051 TF1 Timer 1 1Bh 5 8051 SCONO TIO or RIO from Serial Port 0 23h 6 8051 TF2 Timer 2 2Bh
54. n Register Locations continued Functions not present in the 80C52 are in bold REGISTER BIT 7 BIT 6 BIT 5 4 3 BIT 2 BIT 1 0 ADDRESS TL2 CCh TH2 CDh PSW CY AC FO RSI RSO OV FL P WDCON SMOD 1 POR EPFI PFI WDIF WTRF EWT RWT D8h ACC EIE ERTCI EWDI EX5 4 EX3 EX2 E8h B FOh RTASS F2h RTAS 0 0 F3h RTAM 0 0 F4h RTAH 0 0 0 F5h EIP PRTCI PWDI 5 PX4 PX3 PX2 F8h RTCC SSCE SCE MCE HCE RTCRE RTCWE RTCIF RTCE F9h RTCSS RTCS 0 RTCM 0 m RTCH 13 7 886 3 5753170 86 21 54151736 WE I HL VEN 86 755 83298787 RTCD1 Http www 100y com tw NONVOLATILE FUNCTIONS The DS87C530 DS83C530 provide two functions that are permanently powered if a user supplies an external energy source These are an on chip RTC and a nonvolatile SRAM The chip contains all related functions and controls The user must supply a backup source and a 32 768kHz timekeeping crystal REAL TIME CLOCK The on chip RTC keeps time of day and calendar functions Its time base is a 32 768kHz crystal between pins RTCX1 and RTCX2 The RTC maintains time to 1 256 of a second It also allows a user to read and write seconds minutes hours day of the week and date Figure 2 shows the clock organization Timekeeping registers allow easy access to commonly needed time values For examp
55. ng oscillator to exit Stop mode quickly As mentioned above the processor will automatically switch from the ring to the crystal after a delay of 65 536 crystal clocks For a 3 57MHz crystal this is approximately 18ms The processor sets a flag called RGMD Ring Mode located at EXIF 2 that tells software that the ring is being used The bit will be a logic 1 when the ring is in use Attempt no serial communication or precision timing while this bit is set since the operating frequency is not precise Figure 6 Ring Oscillator Exit from Stop Mode STOP MODE WITHOUT RING STARTUP 4 10 ms uC OPERATING gt uC OPERATING GRYSTAL Sihon cr uC ENTERS INTERRUPT uC ENTERS HRUP CLOCK STOP MODE CLOCK STARTS STABLE STOP MODE V CANON S STOP MODE WITH RING STARTUP uC OPERATING BBS ENSIS COR hw cos uC ENTERS INTERRUPT uC ENTERS STOP MODE RING STARTS STOP MODE POWER SAVED e NOTE DIAGRAM ASSUMES THAT THE OPERATION FOLLOWING STOP REQUIRES LESS THAN 18ms TO COMPLETE EMI REDUCTION One of the major contributors to radiated noise in an 8051 based system is the toggling of ALE The DS87C530 DS83C530 allow software to disable ALE when not used by setting the ALEOFF PMR 2 bit to 1 When ALEOFF 1 ALE will still toggle during an off chip MOVX However ALE will remain in a static when performing on chip memory access The default state of ALEOFF 0 so ALE toggl
56. om RST 5 5V to RST V 5 Changed Note 10 from RST 5 5V to RST V cc 6 Changed serial port mode 0 timing diagram label from tovx to 7 Added information pertaining to 52 pin TQFP package 060895 Initial release 44 M 886 3 5753170 WEE 86 21 54151736 86 755 83298787 Http www 100y com tw 47 of 47 Maxim Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Dallas Semiconductor product No circuit patent licenses are implied Maxim Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2005 Maxim Integrated Products e Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products Inc The Dallas logo is a registered trademark of Dallas Semiconductor Corporation
57. ommonly connected to the latch enable of an external 373 family transparent latch ALE has a pulse width of 39 32 ALE 1 5 XTAL cycles and a period of four XTALI cycles ALE is forced high when the device is in a Reset condition ALE can be disabled and forced high by writing ALEOFF 1 PMR 2 ALE operates independently of ALEOFF during external memory accesses 50 43 P0 0 ADO 49 42 P0 1 Port 0 0 7 I O Port 0 is an open drain 8 bit bidirectional I O port As an 48 Al P0 2 AD2 alternate function Port 0 can function as the multiplexed address data bus to access off chip memory During the time when ALE is high the LSB of a memory address 47 40 P0 3 AD3 is presented When ALE falls to a logic 0 the port transitions to a bidirectional data 46 39 P0 4 AD4 bus This bus is used to read external ROM and read write external RAM memory or peripherals When used as a memory bus the port provides active high drivers 45 38 0 5 AD5 The reset condition of Port 0 is tri state Pullup resistors are required when using 44 37 P0 6 AD6 Port 0 as an I O port 43 36 P0 7 AD7 3 48 P1 0 IVa Port 1 I O Port 1 functions as both an 8 bit bidirectional I O port and an alternate functional interface for Timer 2 I O new External Interrupts and new Serial Port 1 4 49 The reset condition of Port 1 is with all bits at a logic 1 In this state a weak pullup holds the port high This condition also serves as an input mod
58. ort has been at 0 will cause a strong transition driver to turn 18 11 P3 3 on followed by a weaker sustaining pullup Once the momentary strong driver turns off the port again becomes both the output high and input state The alternate modes of Port 3 are outlined below 19 12 P3 4 Port Alternate Function P3 0 RXDO Serial Port 0 Input P3 2 INTO External Interrupt 0 P3 3 INTI External Interrupt 1 21 14 P3 6 P3 4 TO Timer 0 External Input P3 5 T1 Timer 1 External Input P3 6 WR External Data Memory Write Strobe 22 15 P3 7 P3 7 RD External Data Memory Read Strobe External Access Input Active Low Connect to ground to use an external ROM 42 35 EA Internal RAM is still accessible as determined by register settings Connect to Vcc to use internal ROM Input Connect to the power source that maintains SRAM and RTC when 51 44 VBAT lt Can be connected to a lithium battery or a super cap Connect to GND if battery will not be used with device Timekeeping Crystals A 32 768kHz crystal between these pins supplies the time 27 20 RTCX2 base for the RTC The devices support both 6pF and 12 5pF load capacitance crystals as selected by an SFR bit described later To prevent noise from 28 21 RTCXI affecting the RTC the RTCX2 and RTCXI pins should be guard ringed with GND2 2 11 13 4 6 7 Not Connected These pins should not be connected They are reserved for use 14 40 33 34 N C AE 41 47 with future devices in the
59. r This requires that the oscillator be restarted when exiting Stop mode Actual startup time is crystal dependent but is normally at least 4ms A common recommendation is 10ms In an application that will wake up perform a short operation then return to sleep the crystal startup can be longer than the real transaction However the ring oscillator will start instantly Running from the ring the user can perform a simple operation and return to sleep before the crystal has even started If a user selects the ring to provide the startup clock and the processor remains running hardware will automatically switch to the crystal once a power on reset interval 65 536 clocks has expired Hardware uses this value to assure proper crystal start even though power is not being cycled M dt 7 886 3 5753170 23 of 47 Ji 7 86 21 54151736 ETRE 86 755 83298787 Http www 100 com tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock The ring oscillator runs at approximately 2MHz to 4MHz but will not be a precise value Do not conduct real time precision operations including serial communication during this ring period Figure 6 shows how the operation would compare when using the ring and when starting up normally The default state is to exit Stop mode without using the ring oscillator The RGSL ring select bit at EXIF 1 EXIF 91h controls this function When RGSL 1 the CPU will use the ri
60. re a high speed 8051 compatible core Higher speed comes not just from increasing the clock frequency but also from a newer more efficient design This updated core does not have the dummy memory cycles that are present in a standard 8051 A conventional 8051 generates machine cycles using the clock frequency divided by 12 In the DS87C530 DS83C530 the same machine cycle takes 4 clocks Thus the fastest instruction one machine cycle executes three times faster for the same crystal frequency Note that these are identical instructions The majority of instructions on the DS87C530 DS83C530 will see the full 3 to 1 speed improvement Some instructions will get between 1 5 and 2 4 to 1 improvement All instructions are faster than the original 8051 The numerical average of all opcodes gives approximately a 2 5 to 1 speed improvement Improvement of individual programs will depend on the actual instructions used Speed sensitive applications would make the most use of instructions that are three times faster However the sheer number of 3 to 1 improved opcodes makes dramatic speed improvements likely for any code These architecture improvements produce a peak instruction cycle in 121ns 8 25 MIPs The Dual Data Pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory INSTRUCTION SET SUMMARY All instructions perform the same functions as their 8051 counterparts Their effect on bits flags and other stat
61. rite Enable 0 RTC Oscillator Enable EPROM PROGRAMMING The DS87C530 follows standards for a 16kB EPROM version in the 8051 family It is available in a UV erasable ceramic windowed package and in plastic packages for one time user programmable versions The part has unique signature information so programmers can support its specific EPROM options PROGRAMMING PROCEDURE The DS87C530 should run from a clock speed between 4MHz and 6MHz when programmed The programming fixture should apply address information for each byte to the address lines and the data value to the data lines The control signals must be manipulated as shown in Table 9 The diagram in Figure 5 shows the expected electrical connection for programming Note that the programmer must apply addresses in demultiplexed fashion to Ports 1 and 2 with data on Port 0 Waveforms and timing are provided in the Electrical Specifications section Program the DS87C530 as follows 1 Apply the address value 2 Apply the data value 3 Select the programming option from Table 9 using the control signals 4 Increase the voltage on from 5V to 12 75V if writing to the EPROM 5 Pulse the PROG signal five times for EPROM array and 25 times for encryption table lock bits and other EPROM bits 6 Repeatas many times as necessary MEM 7 d 886 3 5753170 86 21 54151736 86 755 83298787 28 of 47 Http www 100y com
62. rts 0 and 2 Figure 4 shows a depiction of the ROM memory map The ROMSIZE register is used to select the maximum on chip decoded address for ROM Bits RMS2 RMS1 RMSO have the following effect RMS2 RMSI RMSO0 MAXIMUM ON CHIP ROM ADDRESS 1kB 7 886 3 5753170 86 21 54151736 AkB WERE 7 HLF G3 86 755 83298787 Http www 100y com tw 8kB 16kB default Invalid treserved gt gt gt gt Invalid reserved The reset default condition is a maximum on chip ROM address of 16kB Thus no action is required if this feature is not used When accessing external program memory the first 16kB would be inaccessible To select a smaller effective ROM size software must alter bits RMS2 RMSO Altering these bits requires a timed access procedure Care should be taken so that changing the ROMSIZE register does not corrupt program execution For example assume that a device is executing instructions from internal program memory near the 12kB boundary 3000h and that the ROMSIZE register is currently configured for a 16kB internal program space If software reconfigures the ROMSIZE register to 4kB 0000h 0FFFh in the current state the 13 of 47 DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock device will immediately jump to external progra
63. ry mapped This on chip SRAM is reached by the instruction It is not used for executable memory The scratchpad area is 256 bytes of register mapped RAM and is identical to the RAM found on the 80C52 There is no conflict or overlap among the 256 bytes and the 1 as they use different addressing modes and separate instructions OPERATIONAL CONSIDERATION The erasure window of the windowed LCC should be covered without regard to the programmed unprogrammed state of the EPROM Otherwise the device may not meet the AC and DC parameters listed in the data sheet PROGRAM MEMORY ACCESS On chip ROM begins at address 0000h and is contiguous through 3FFFh 16kB Exceeding the maximum address of on chip ROM will cause the DS87C530 DS83C530 to access off chip memory However the maximum on chip decoded address is selectable by software using the ROMSIZE feature Software can cause the microcontroller to behave like a device with less on chip memory This is beneficial when overlapping external memory such as Flash is used The maximum memory size is dynamically variable Thus a portion of memory can be removed from the memory map to access off chip memory then restored to access on chip memory In fact all the on chip memory can be removed from the memory map allowing the full 64kB memory space to be addressed from off chip memory ROM addresses that are larger than the selected maximum are automatically fetched from outside the part via Po
64. state a weak pullup holds the port high This condition also serves as an input mode since any external circuit that writes to the port will 32 25 P2 2 ADIO overcome the weak pullup When software writes a 0 to any port pin the device 33 26 P2 3 AD11 will activate a strong pulldown that remains on until either a 1 is written or a reset occurs Writing a 1 after the port has been at 0 will cause a strong transition driver 34 27 P2 4 ADI2 to turn on followed by a weaker sustaining pullup Once the momentary strong 35 28 P2 5 AD13 driver turns off the port again becomes both the output high and input state As an alternate function Port 2 can function as MSB of the external address bus This 36 29 P2 6 ADI4 bus can be used to read external ROM and read write external RAM memory or 37 30 P2 7 15 Peripherals 15 8 P3 0 Port 3 I O Port 3 functions as both an 8 bit bi directional I O port and an alternate functional interface for external interrupts Serial Port 0 Timer 0 and 1 Inputs and RD and WR strobes The reset condition of Port 3 is with all bits at a 16 9 P3 1 logic 1 In this state a weak pullup holds the port high This condition also serves as an input mode since any external circuit that writes to the port will overcome 17 10 P3 2 the weak pullup When software writes a 0 to any port pin the device will activate a strong pulldown that remains on until either a 1 is written or reset occurs Writing a 1 after the p
65. t Then it will perform the switch to ring operation if desired Lastly software can disable the crystal amplifier if desired There are two ways of exiting PMM Software can remove the condition by reversing the procedure that invoked PMM or hardware can optionally remove it To resume operation at a divide by 4 rate under software control simply select 4 clocks per cycle and then crystal based operation if relevant When disabling the crystal as the time base in favor of the ring oscillator there are timing restrictions associated with restarting the crystal operation Details are described below There are three registers containing bits that are concerned with PMM functions They are Power Management Register PMR C4h Status STATUS C5h and External Interrupt Flag EXIF 91h Clock Divider Software can select the instruction cycle rate by selecting bits CD1 PMR 7 and PMR 6 as follows CDI 0 0 Reserved 0 1 4 clocks default 1 0 64 clocks 1 1 1024 clocks The selection of instruction cycle rate will take effect after a delay of one instruction cycle Note that the clock divider choice applies to all functions including timers Since baud rates are altered it will be difficult to conduct serial communication while in PMM There are minor restrictions on accessing the clock selection bits The processor must be running in a 4 clock state to select either 64
66. ty setting then Switchback will not occur on INTO if the CPU is servicing a high priority interrupt Status Information in the Status register assists decisions about switching into PMM This register contains information about the level of active interrupts and the activity on the serial ports The DS87C530 DS83C530 support three levels of interrupt priority These levels are Power fail High Low Bits STATUS 7 S indicate the service status of each level If PIP Power fail Interrupt Priority STATUS 7 is 1 then the processor is servicing this level If either HIP High Interrupt Priority STATUS 6 or LIP Low Interrupt Priority STATUS 5 is high then the corresponding level is in service Software should not rely on a lower priority level interrupt source to remove PMM Switchback when a higher level is in service Check the current priority service level before entering PMM If the current service level locks out a desired Switchback source then it would be advisable to wait until this condition clears before entering PMM Alternately software can prevent an undesired exit from PMM by entering a low priority interrupt service level before entering PMM This will prevent other low priority interrupts from causing a Switchback Status also contains information about the state of the serial ports Serial Port Zero Receive Activity 5 0 STATUS 0 indicates a serial word is being received on Serial Port 0 when this bit is set
67. us functions is identical However the timing of each instruction is different This applies both in absolute and relative number of clocks For absolute timing of real time events the timing of software loops can be calculated using a table in the High Speed Microcontroller User s Guide However counter timers default to run at the older 12 clocks per increment In this way timer based events occur at the standard intervals with software executing at higher speed Timers optionally can run at 4 clocks per increment to take advantage of faster processor operation Bod 7 5 886 3 5753170 JJ 86 21 54151736 7 of 47 Vi VE 86 755 83298787 Http www 100y com tw DS87C530 DS83C530 EPROM ROM Microcontrollers with Real Time Clock The relative time of two instructions might be different in the new architecture than it was previously For example in the original architecture the MOVX DPTR instruction and the MOV direct direct instruction used two machine cycles or 24 oscillator cycles Therefore they required the same amount of time In the DS87C530 DS83C530 the MOVX instruction takes as little as two machine cycles or eight oscillator cycles but the MOV direct direct uses three machine cycles or 12 oscillator cycles While both are faster than their original counterparts they now have different execution times This is because the DS87C530 DS83C530 usually use one instruction cycle for ea
68. ware but to use substantially less power During default operation the DS87C530 DS83C530 use four clocks per machine cycle Thus the instruction cycle rate is Clock 4 At 33MHz crystal speed the instruction cycle speed is 8 25MHz 33 4 In PMM the microcontroller continues to operate but uses an internally divided version of the clock source This creates a lower power state without external components It offers a choice of two reduced instruction cycle speeds and two clock sources discussed below The speeds are Clock 64 and Clock 1024 Software is the only mechanism to invoke the PMM Table 4 illustrates the instruction cycle rate in PMM for several common crystal frequencies Since power consumption is a direct function of operating speed PMM 1 eliminates most of the power consumption while still allowing a reasonable speed of processing PMM 2 runs very slowly and provides the lowest power consumption without stopping the CPU This is illustrated in Table 5 Note that PMM provides a lower power condition than Idle mode This is because in Idle all clocked functions such as timers run at a rate of crystal divided by 4 Since wake up from PMM is as fast as or faster than from Idle and allows the CPU to operate even if doing NOPS there is little reason to use Idle mode in new designs Table 4 Machine Cycle Rate S BED ie 64 TORS TS CLOCKS MHz kHz kHz 11 0592 2 765 172 8 10 8 16 4 00 250

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