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Intel 845 Computer Accessories User Manual

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1. Signal Name Ball Signal Name Ball SBA4 AE28 SCS9 H25 SBA5 AE27 SCS10 G6 SBA6 AE24 SCS11 H6 SBA7 AE25 SDQO F27 SB_STB AF27 SDQ1 E27 SB_STB AF26 SDQ2 B28 5 50 F17 SDQ3 C27 SBS1 G17 SDQ4 D26 SCAS J25 SDQ5 E25 SCKO F13 SDQ6 B25 SCK1 G13 SDQ7 D24 SCK2 E2 SDQ8 F23 SCK3 C2 SDQ9 B23 SCK4 G15 SDQ10 C22 SCK5 G14 50011 21 SCK6 F3 SDQ12 D20 SCK7 E3 50013 19 SCK8 G16 50014 18 SCK9 F15 SDQ15 C17 SCK10 H5 50016 B13 SCK11 G5 SDQ17 E13 SCKEO G9 SDQ18 C12 SCKE1 F4 50019 11 5 2 G10 SDQ20 E11 SCKE3 F5 50921 10 SCKE4 G11 SDQ22 F9 SCKE5 E5 SDQ23 c9 5 50 H23 SDQ24 E8 5 51 423 50025 7 5652 G7 SDQ26 C7 SCS3 G8 SDQ27 D6 SCS4 J24 50028 5 5 55 24 50029 4 5 56 H7 50030 5 57 F7 SDQ31 B2 SCS8 G25 SDQ32 G28 Inte 82845 for SDR Datasheet 131 Ballout and Package Information Signal Name Ball Signal Name Ball SDQ33 E28 SCB5 016 50034 28 6 15 50035 027 SCB7 C14 SDQ36 B27 SDREF J9 J21 SDQ37 F25 G22 SDQ38 C25 SMA1 E21 SDQ39 E24 SMA2 21 50040 C24 SMA3 921 50041 23 SMA4 E20 50042 022 5 5 G20 50043 22 SMA6 E19 50044 21 7 F19 SDQ45 C20 G19 50046 018 9 918 0047 18 SMA10 E17 50048 14 SMA11 E15 50049 SMA12 G12 SDQ50 E12 SMRCOMP J28 50051 11 SRAS G23 SDQ
2. s Loo pe 3 o e me _ me o o o wm o om me ow ow me ow os ow wm os ox wo ow o wm 138 Inte 82845 for SDR Datasheet Chain 0 Ball Signal Name Initial Logic Level ww Inte 82845 for SDR Datasheet Testability 139 Testability Table 24 XOR Chain 1 Chain 1 Ball Signal Name Initial Logic Level 2 HADSTDB1s SCK3 11 SCK7 1 SDQ30 0 1 1 1 1 1 1 m a A 140 Inte 82845 SDR Datasheet intel Table 25 XOR Chain 2 See iier wm 1 m o m9 Inte 82845 for SDR Datasheet Testability 141 Testability Table 26 XOR Chain 3 nd m s so wm s sm wm m om 3 142 Inte 82845 for SDR Datasheet Table 27 Chain 4 Chain 4 Ball Element Signal Note Initial Logic Level Inte 82845 for SDR Datasheet Testability 143 Testability _2 In
3. Multi Transaction Timer Count Value MTTC number programmed these bits represents the guaranteed time slice measured in eight 66 MHz clock granularity allotted to the current agent either AGP master or MCH after which the AGP arbiter will grant the bus to another agent Inte 82845 for SDR Datasheet 71 Register Description 3 5 32 72 intel LPTT AGP Low Priority Transaction Timer Register Device 0 Address Offset BDh Default Value 00h Access R W Size 8 bits LPTT is an 8 bit register similar in function to AMTT This register is used to control the minimum tenure on the AGP for low priority data transactions both reads and writes issued using PIPE or SB mechanisms The number of clocks programmed in the LPTT represents the guaranteed time slice measured in 66 MHz clocks allotted to the current low priority AGP transaction data transfer state This does not necessarily apply to a single transaction but it can span over multiple low priority transactions of the same type After this time expires the AGP arbiter may grant the bus to another agent if there is a pending request The LPTT does not apply in the case of high priority request where ownership is transferred directly to high priority requesting queue The default value of LPTT is 00h and disables this function The LPTT value be programmed with 8 clock granularity For example if the LPTT is programmed to 10h the selected v
4. SMM Space Open D OPEN R W L When D 1 D_LCK 0 the SMM space DRAM is made visible even when SMM decode is not active This is intended to help BIOS initialize SMM space Software should ensure that D 1 and D CLS 1 not set at the same time When D LCK is set to 1 D OPEN is reset to 0 and becomes read only SMM Space Closed D CLS R W When D CLS 1 SMM space DRAM is not accessible to data references even if SMM decode is active Code references may still access SMM space DRAM This allows SMM software to reference through SMM space to update the display even when SMM is mapped over the VGA range Software should ensure that D OPEN 1 and D CLS 1 are not set at the same time Note that the D CLS bit only applies to Compatible SMM space SMM Space Locked D LCK R W When D LCK is set to 1 D OPEN is reset to 0 and D LCK D OPEN C BASE SEG SMRAM EN TSEG SZ TSEG EN become Read Only D LCK can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset The combination of D LCK and OPEN provide convenience with security The BIOS can use the D OPEN function to initialize SMM space and then use D to lock down SMM space in the future so that no application software or BIOS itself can violate the integrity of SMM space even if the program has knowledge of the D OPEN function Global SMRAM Enable G SMRAME R W L 0 Disable 1 E
5. 0 75 X default 001 1 00 X 010 1 25 X 011 1 50 X 100 2 00 X 101 2 50 110 2 3 00 X 111 24 00 X Inte 82845 for SDR Datasheet 41 Register Description 3 4 6 42 intel RCVENSTR Strength Control Register RCVENOUT Signal Group Memory Address Offset 34h Default Value 00h Access R W Size 8 bits This register controls the drive strength of the I O buffers for the Receive Enable Out signal group RDCLKO signal 2 0 Receive Enable Out Signal Group RCVEnOut Strength Control This field selects the signal drive strength 000 0 75 X default 001 1 00 X 010 1 25 X 011 1 50 X 100 2 00 X 101 2 50 110 2 3 00 X 111 4 00 X Inte 82845 for SDR Datasheet Register Description 3 5 Host Hub Interface Bridge Device Registers Device 0 Table 8 provides the register address map for Device 0 PCI configuration space 5 in the Default Value column indicates that a strap determines the power up default value for that bit Table 8 Intel MCH Configuration Space Device 0 ar oe ee Offset x Value 00 0 Vendor Identification Identification s0861 E E Sm M ow me revon aeneon O fonon 0 Co c meme 0 m E 1 7 e ow xe wr wem ree fo oS m wm eee 7 seem m E
6. 0E0000h 0E3FFFh BIOS Extension PAMS 7 4 R 8 we 0E4000h 0E7FFFh BIOS Extension 6 3 01 we OE8000h 0EBFFFh BIOS Extension 674 R WE RE oECooon oEFFFFh BIOS Extension For details on overall system address mapping scheme see Chapter DOS Application Area 00000h 9FFFh The DOS area is 640 KB in size and it is further divided into two parts The 512 KB area at Oh to 7FFFFh is always mapped to the system memory controlled by the MCH while the 128 KB address range from 080000 to 09FFFFh can be mapped to PCIO to system memory By default this range is mapped to system memory and can be declared as a system memory hole accesses forwarded to PCIO via MCH FDHC configuration register Video Buffer Area A0000h BFFFFh Attribute bits do not control this 128 KB area The host initiated cycles in this region are always forwarded to either PCIO or AGP unless this range is accessed in SMM mode Routing of accesses is controlled by the Legacy VGA control mechanism of the virtual PCI PCI bridge device embedded within the MCH This area can be programmed as SMM area via the SMRAM register When used as a SMM space this range cannot be accessed from the hub interface or AGP Expansion Area CO000h DFFFFh This 128 KB area is divided into eight 16 KB segments which can be assigned with different attributes via PAM control register as defined by the table above Inte 82845 f
7. 1 8 V Power Input Pins These pins are connected to a 1 8 V power source SDRAM Power Input Pins These pins are connected to a 3 3 V power source for SDR VCCSM 1 0 PLL Power Input Pins These pins provide power for the PLL AGTL Bus Termination Voltage Inputs These pins provide the AGTL bus termination Ground The VSS pins are the ground pins for the MCH VTT VSS VSSA 1 0 PLL Ground The VSSA 1 0 pins are the ground pins for the PLL on the MCH Inte 82845 for SDR Datasheet 29 Signal Description intel 2 7 Reset States During Reset Z Ti state ISO Isolate inputs in inactive state Strap input sampled during assertion or on the de asserting edge of RSTIN Driven high 5 Driven low D Strong drive to normal value supplied by core logic if not otherwise stated I Input active State State State During During During Signal Name RSTIN Signal Name RSTIN Signal Name RSTIN Assertion Assertion Assertion System Bus Interface HLRCOMP AD STB 1 0 CPURST HSWNG AD_STB 1 0 HADSTB 1 0 21 SDR System Memory SBSTB zi Sox oj SR STER HDSTBP 3 0 21 HDSTBNI 3 0 21 DBI 3 0 z z Clocks BCLK 30 Inte 82845 SDR Datasheet Register Description 3 Register Description The MCH contains two sets of software accessible registers accessed via the host processor I
8. 0 Software must write a 1 to clear this status bit 1 Indicates that an AGP access occurred to an address that is outside of the graphics aperture range Inte 82845 for SDR Datasheet 75 Register Description 3 5 36 76 Note Single bit DRAM ECC Error Flag DSERR 0 Software must write a 1 to clear this bit and unlock the error logging mechanism 1 A memory read data transfer had a single bit correctable error and the corrected data was sent for the access When this bit is set the address channel number and device number that caused the error are logged in the EAP Register When this bit is set the EAP CN DN and ES fields are locked to further single bit error updates until the processor clears this bit by writing a 1 ERRCMD Error Command Register Device 0 Address Offset Default Value 0000h Access R W Size 16 bits This register enables various errors to generate a SERR message via the hub interface Since the MCH does not have an SERR signal SERR messages are passed from the MCH to the ICH2 over the hub interface When a bit in this register is set a SERR message will be generated on the hub interface when the corresponding flag is set in the ERRSTS register The actual generation of the SERR message is globally enabled for Device 0 via the PCICMD register An error can generate and only one error message via the hub interface It is software 5 responsi
9. 0 1 V a b Host AGTL Output High Voltage VTT 0 1 V lo a b Host AGTL Output Low Current VTTmax 0 75Rtt mA Rttmin 45 Q Rttyp 500 Rttmax 55 Q lLeak a c Host AGTL Input Leakage 215 Voi Vpad Current VTT Cpap a c Host AGTL Input Capacitance 1 0 pF 3 3 V Interface k m p Input Low Voltage SDREF 2 0 V k m p Input High Voltage SDREF 2 0 V VoL k l Output Low Voltage 0 4 V k l Output High Voltage 2 4 V lo k l Output Low Current 4 mA QVo s lou k l Output High Current 4 mA max lLeak k m p Input Leakage Current 100 0 lt Vin lt VCC3_3 122 Inte 82845 for SDR Datasheet Electrical Characteristics intel Symbol Signal Parameter Min Typ Max Unit Notes Group k m p Input Capacitance 4 65 5 37 pF 1 5 V Interface e f Input Low Voltage 0 4 VCC1_5 V Vin e f Input High Voltage 0 6 x VCC1_5 V VoL Output Low Voltage 0 15 x VCC1 5 V Output High Voltage 0 85 x VCC1 5 V lo e g Output Low Current 1 mA Q Vo Output High Current 0 2 mA a lLeak e f Input Leakage Current 15 0 lt Vin lt VCC1_5 Cin e f Input Capacitance 1 32 1 92 pF 1 8 V Interface Vit i o Input Low Voltage HI REF 0 15 V Vin I
10. 9 seme E sem m E eem pees mem m LE ww mem ________ s seem Inte 82845 for SDR Datasheet 43 Register Description 44 Address Register Register Name Default Offset Symbol Value 8C 8Fh Error Address Pointer 00000000h 90 96h 0 6 Programmable Attribute 7 Registers 0000000000 RO R W 0000h 00h R W SMRAM 9Dh System Management RAM Control 02h RO R W R W L ESMRAMC Extended System Mgmt RAM Control 38h NEN p 0 Inte 82845 SDR Datasheet Register Description 3 5 1 VID Vendor Identification Register Device 0 Address Offset 00 01h Default Value 8086h Attribute RO Size 16 bits The VID Register contains the vendor identification number This 16 bit register combined with the DID Register uniquely identifies any PCI device Writes to this register have no effect Vendor Identification Number This is a 16 bit value assigned to Intel Intel VID 8086h 3 5 2 DID Device Identification Register Device 0 Address Offset 02 03h Default Value 1A30h Attribute RO Size 16 bits This 16 bit register combined with the VID Register uniquely identifies any PCI device Writes to this register have no effect NK Device Identification Number This is 16 bit value assigned to the Host Hub Interface Brid
11. BIOS needs to determine the size and type of memory used for each of the rows of memory to properly configure the MCH memory interface SMBus Configuration and Access of the Serial Presence Detect Ports For more details on SMBus Configuration and Serial Present Detect Ports see the Intel 82801 Controller Hub 2 ICH2 and 82801BAM I O Controller Hub 2 Mobile ICH2 M Datasheet Memory Register Programming This section provides an overview of how the required information for programming the SDRAM registers is obtained from the Serial Presence Detect ports on the DIMMs The Serial Presence Detect ports are used to determine refresh rate MA and MD buffer strength row type on a row by row basis SDRAM Timings row sizes and row page sizes Table 13 ists a subset of the data available through the on board Serial Presence Detect ROM on each DIMM Table 13 Data Bytes on DIMM Used for Programming DRAM Registers 000 110 able 135 only a subset of the defined SPD bytes the DIMMs These bytes collectively provide enough data for programming the MCH SDRAM registers Inte 82845 for SDR Datasheet Functional Description 5 2 3 Memory Address Translation and Decoding The 845 MCH contains address decoders that translate the address received on the system bus or the hub interface Decoding and translation of these addresses vary with the four SDRAM types Also the number of pages page sizes and de
12. Device Identification Number This is a 16 bit value assigned to the Device 1 Device 1 DID 1A31h Inte 82845 for SDR Datasheet 81 Register Description 3 6 3 PCICMD1 PCI PCI Command Register Device 1 Address Offset 04 05 Default 0000h Access RO RW Size 16 bits Fast Back to Back 2 Implemented Hardwired to 0 SERR Message Enable SERRE1 R W This bit is a global enable bit for Device 1 SERR messaging The does not have an SERR signal The communicates the SERR condition by sending an SERR message to the ICH2 0 Disable SERR message is not generated by the for Device 1 1 Enable is enabled to generate SERR messages over the hub interface for specific Device 1 error conditions that are individually enabled in the BCTRL register The error status is reported in the PCISTS1 register NOTE This bit only controls SERR messaging for the Device 1 Device 0 has its own SERRE bit to control error reporting for error conditions occurring on Device 0 Parity Error Enable PERRE1 RO Not Implemented Hardwired to 0 Memory Write and Invalidate Enable MWIE RO Not Implemented Hardwired to 0 Special Cycle Enable SCE RO Not Implemented Hardwired to 0 Bus Master Enable BME1 R W This bit is not functional It is a R W bit for compatibility with compliance testing software Memory Access Enable MAE1 R W 0
13. FRAMES signals are defined below G_FRAME s t s AGP G_IRDY y o s t s AGP 5 s t s AGP FRAME During FRAME Operations G_FRAME is an output when the MCH acts as an initiator on the AGP Interface Initiator Ready This signal indicates the AGP compliant master is ready to provide all write data for the current transaction Once G_IRDY is asserted for a write operation the master is not allowed to insert wait states The master is never allowed to insert a wait state during the initial data transfer 32 bytes of a write transaction However it may insert wait states after each 32 byte block is transferred Target Ready This signal indicates the AGP compliant target is ready to provide read data for the entire transaction when the transfer size is less than or equal to 32 bytes or is ready to transfer the initial or subsequent block 32 bytes of data when the transfer size is greater than 32 bytes The target is allowed to insert wait states after each block 32 bytes is transferred on write transactions STOP G_STOP Is an input when the MCH acts as a FRAME based AGP initiator and an output when the MCH acts as a FRAME based AGP target G_STOP is used for disconnect retry and abort sequences on the AGP interface Inte 82845 for SDR Datasheet Signal Description G_DEVSEL Device Select This signal indicates that FRAME based AGP target s t s device has decoded its addre
14. Inte 82845 for SDR Datasheet Inte 82845 for SDR Datasheet 5 Register Description DRA DRAM Row Attribute Registers Device 0 Offset 70 73 Default 00h Access R W Size 8 bits The DRAM Row Attribute Register defines the page sizes to be used when accessing different pairs of rows Each nibble of information in the DRA registers describes the page size of a pair of Row 2 3 71h Row 4 5 72h Used SDRAM configuration only Row 6 7 73h RAODD and RAEVEN fields must contain default value of 008 7 6 4 3 2 0 Row attribute for Row 1 Row Attribute for Row 0 7 6 4 3 2 0 Row attribute for Row 3 Row Attribute for Row 2 7 6 4 3 2 0 Row attribute for Row 5 Row Attribute for Row 4 7 6 4 3 2 0 Row attribute for Row 7 Row Attribute for Row 6 Register Description Row Attribute for Odd Numbered Row RAODD This 3 bit field defines the page size of the corresponding row 001 2 010 4 011 8 100 16 Others Reserved 2 0 Row Attribute for Even Numbered Row RAEVEN This 3 bit field defines the page size of the corresponding row 001 2 010 4 011 8 100 16 Others Reserved 54 Inte 82845 for SDR Datasheet Register Description 3 5 17 DRT DRAM Timing Register Device 0 Offset 78 7Bh Default 00000010h Access R W Size 32 bits 18 16 DRAM Idle Timer Th
15. Rev 1 7 Note See the Intel Pentium 4 Processor in a 478 Pin Package and Intel 845 Chipset Platform Design Guide for an expanded set of related documents Inte 82845 for SDR Datasheet 13 Introduction 1 3 1 4 intel Intel 845 Chipset System Architecture The MCH provides the processor interface system memory interface AGP interface and hub interface in an 845 chipset desktop platform The processor interface supports the Pentium 4 processor subset of the Extended Mode of the Scalable Bus Protocol The MCH supports a single channel of PC133 SDRAM The MCH contains advanced power management logic The 845 chipset platform supports the I O Controller Hub 2 ICH2 to provide the features required by a desktop platform Intel 82801BA I O Controller Hub 2 ICH2 The 2 is a highly integrated multifunctional I O Controller Hub that provides the interface to the PCI Bus and integrates many of the functions needed in today s PC platforms The MCH and ICH2 communicate over a dedicated hub interface The 82801BA Functions and capabilities include PCI Rev 2 2 compliant with support for 33 MHz PCI operations e Supports up to 6 Request Grant pairs PCI slots Power management logic support e Enhanced DMA controller interrupt controller and timer functions Integrated IDE controller Ultra ATA 100 66 33 USB host interface 2 host controllers and supports 4 USB ports Integ
16. Revision 2 0 AGP Signal Levels The 4x data transfers use 1 5 V signaling levels as described by the AGP Interface Specification Revision 2 0 The MCH supports 1x 2x data transfers using 1 5 V signaling levels 4x AGP Protocol In addition to the 1x and 2x AGP protocol the MCH supports 4x AGP read and write data transfers and 4x sideband address generation The 4x operation is compliant with the AGP Interface Specification Revision 2 0 The MCH indicates that it supports 4x data transfers via bit 2 of the AGPSTAT RATE field When bit 2 of the AGPCMD DRATE field is set to 1 during system initialization the MCH performs AGP read write data transactions using 4x protocol This bit is not dynamic Once this bit is set during initialization the data transfer rate must not be changed The 4x data rate transfer provides 1 06 GB s transfer rates The control signal protocol for the 4x data transfer protocol is identical to 1x 2x protocol In 4x mode 16 bytes of data are transferred on every 66 MHz clock edge The minimum throttleable block size remains four 66 MHz clocks 64 bytes of data are transferred per block Three additional signal pins are required to implement the 4x data transfer protocol These signal pins are complimentary data transfer strobes for the AD bus 2 and the SBA bus 1 Fast Writes The MCH supports 2x and 4x Fast Writes from the MCH to the graphics controller on AGP Fast Write operation is compliant with Fast Writ
17. register and the Configuration Data CONF DATA register The Configuration Address register enables disables the configuration space and determines what portion of configuration space is visible through the configuration data window CONF ADDR Configuration Address Register I O Address OCF8h Accessed as a DWord Default Value 00000000h Access R W Size 32 bits CONF_ADDR is 32 bit register that be accessed only as a DWord A Byte or Word reference will pass through the Configuration Address register and the hub interface onto the PCI bus as an I O cycle CONF_ADDR register contains the Bus Number Device Number Function Number and Register Number for which a subsequent configuration access is intended Inte 82845 MCH for SDR Datasheet 30 24 23 16 15 11 Register Description Configuration Enable CFGE 0 Disable 1 Enable Accesses to PCI configuration space are enabled Reserved These bits are read only and have a value of 0 Bus Number When Bus Number is programmed to 00h the target of the configuration cycle is a hub interface agent 2 etc The configuration cycle is forwarded to the hub interface if Bus Number is programmed to 00h and the MCH is not the target the device number is 22 If Bus Number is non zero and matches the value programmed into the Secondary Bus Number Register of device 1 a Type 0 PCI configuration cycle will be generated
18. technologies for x8 and x16 devices By using 64 Mb technology the smallest memory capacity possible is 32 MB Configurable optional ECC operation single bit Error Correction and multiple bit Error Detection Page sizes of 2 KB 4 KB 8 KB and 16 KB individually selected for every row Thermal management Maximum 3 Double Sided DIMMs 6 rows populated with unbuffered PC133 with or without ECC Note Mixed mode populating ECC and Non ECC Memories simultaneously is not supported 3 GB Maximum using 512 Mb technology Supports up to 24 simultaneous open pages Maximum memory bandwidth of 1 067 GB s with PC133 Hub Interface to Intel 82801BA ICH2 266 MB s point to point hub interface to ICH2 66 base clock MSI interrupt messages power management state change SMI SCI and SERR error indication Inte 82845 for SDR Datasheet connector or on the motherboard Supports AGP 2 0 including 1x 2x and 4x data transfers and 2 4 Fast Write protocol Supports only 1 5 V AGP electrical characteristics 32 deep request queue Delayed transaction support for AGP to System Memory FRAMES semantic reads System Interrupt Support System bus interrupt delivery mechanism Interrupts signaled as upstream memory writes from AGP PCI Supports peer MSI between hub interface and AGP Provides redirection for IPI and upst
19. 101 2 50 110 2 3 00 X 111 24 00 X Inte 82845 for SDR Datasheet Register Description 3 4 3 CKESTR Strength Control Register SCKE Signal Group Memory Address Offset 31h Default Value 00h Access R W Size 8 bits This register controls the drive strength of the I O buffers for the CKE signal group This group has two possible loadings depending on the width of SDRAM devices used in each row of memory x8 or x16 The proper strength can be independently programmed for each configuration The actual strength used for each signal is determined by the DRAMWIDTH Register offset 2Ch 2 0 SCKE x16 Strength Control This field selects the signal drive strength 000 0 75 X default 001 1 00 X 010 1 25 X 011 1 50 X 100 2 00 X 101 2 50 X 110 3 00 X 111 4 00 X SCKE x8 Strength Control This field selects the signal drive strength 000 0 75 X default 001 1 00 X 010 1 25 X 011 1 50 X 100 2 00 X 101 2 50 110 2 3 00 X 111 24 00 X Inte 82845 for SDR Datasheet 39 Register Description 3 4 4 40 intel CSBSTR Strength Control Register SCS Signal Group Memory Address Offset 32h Default Value 00h Access R W Size 8 bits This register controls the drive strength of the I O buffers for the SCS signal group This group has two possible loadings depending on the width of SDRAM devices used in each row of memory x8 or x16 The proper strengt
20. 32 bit address The bottom 4 bits of this register are read only and return 0s when read The configuration software must initialize this register For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary ___ ____ Memory Address 1 5 1 Corresponds to 31 20 the memory address MLIMIT1 Memory Limit Address Register Device 1 Address Offset 22 23h Default Value 0000h Access R W Size 16 bits This register controls the host to AGP non prefetchable memory accesses routing based on the following formula MEMORY_BASE1 lt address lt MEMORY_LIMIT1 The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return Os when read The configuration software must initialize this register For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Memory Address Limit 1 MEM_LIMIT1 Corresponds to A 31 20 of the memory address Default 0 Memory range covered by MLIMIT1 registers are used to map non prefetchable AGP address ranges typically where control status memory mapped I O data structures of the graphics c
21. 4 DOS Compatible Area Address L 1MB pper Lower Expansion Card BIOS 4 by and Buffer Area 0 0000 768 0B8000h M h Displ 736 KB Controlled by Standard PCI ISA por ers Isp ay Enable and Video Memory MDA Enable SMM Memory 704 0A0000h 640 KB Optional AGP Optional System Memory System Memory sys addr map 2 Figure 5 Extended Memory Range Address Map 1 0000 0000 4 GB High BIOS Optional extended SMRAM 00 0000 Hub Interface always FEFO 0000 Local APIC Space FEEO 0000 Hub Interface always FEDO 0000 APIC Space FEC8 0000 APIC Space FECO 0000 AGP PCI Top of Low Memory TOM Extended SMRAM Space TEM TSEG 100C 0000 Extended SMRAM translated to 1 MB 100A 0000 0100 0000 16 MB Hole System Memory Region 00 0 0000 15 MB Optional System Memory Region 0010_0000 1 MB sys addr map 3 98 Inte 82845 for SDR Datasheet 4 1 1 System Address VGA and MDA Memory Space Video cards use these legacy address ranges to map a frame buffer or a character based video buffer The address ranges in this memory space are VGAA 0_000A_0000 to 0 000 MDA 0 0008 0000 to 0 000 7FFF 0 000B 8000 to 0 000 FFFF By default accesses to these ranges are forwarded to the hub interface Ho
22. 7 1 4 8 intel System Interrupts The MCH supports both Intel 8259 and Pentium 4 processor interrupt delivery mechanisms The serial APIC interrupt mechanism is not supported Intel 8259 support consists of flushing inbound hub interface write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the hub interface The MCH supports the Pentium 4 processor interrupt delivery mechanism IOxAPIC and PCI MSI interrupts are generated as memory writes The MCH decodes upstream memory writes to the range OFEEO_O0000h OFEEF_FFFFh from AGP and the hub interface as message based interrupts The MCH forwards the memory writes along with the associated write data to the system bus as an interrupt message transaction Note that since this address does not decode as part of system memory the write cycle and the write data are not forwarded to system memory via the write buffer The MCH provides the response and TRDY for all interrupt message cycles including the ones originating from the MCH The MCH supports interrupt re direction for inter processor interrupts IPIs as well as upstream interrupt memory writes For message based interrupts system write buffer coherency is maintained by relying on strict ordering of memory writes The MCH ensures that all memory writes received from a given interface prior to an interrupt message memory write are delivered to the system bus for snooping in the same order that they occur on
23. 82845 for SDR Datasheet 105 System Address 4 5 2 106 intel AGP Interface Decode Rules Cycles Initiated Using AGP FRAME Protocol The does not support any AGP FRAME access targeting the hub interface The claims AGP initiated memory read and write transactions decoded to the system memory range or the Graphics Aperture range All other memory read and write requests will be master aborted by the AGP initiator as a consequence of MCH not responding to a transaction Under certain conditions the MCH restricts access to the DOS Compatibility ranges governed by the PAM registers by distinguishing access type and destination bus The MCH does NOT accept AGP FRAME write transactions to the compatibility ranges if the PAM designates system memory as writeable If accesses to a range are not write enabled by the PAM the MCH does not respond and the cycle results in a master abort The accepts FRAME read transactions to the compatibility ranges if the PAM designates system memory as readable If accesses to a range are not read enabled by the PAM the MCH does not respond and the cycle results in a master abort If agent on AGP issues an I O PCI Configuration or PCI Special Cycle transaction the MCH does not respond and cycle results in a master abort Cycles Initiated Using AGP PIPE or SB Protocol All cycles must reference system memory that is system memory address range including PAM
24. AA2 HD36 AE10 HD1 AB5 HD37 AD9 HD2 5 HD38 9 HD3 AB3 HD39 AC10 HD4 AB4 HD40 AE12 HD5 5 HD41 AF10 HD6 AA3 HD42 AG11 HD7 HD43 AG10 Inte 82845 for SDR Datasheet 129 Ballout and Package Information 130 Signal Name Ball Signal Name Ball HD44 AH11 HI_8 M27 HD45 AG12 9 N28 HD46 AE13 HI_10 M24 HD47 AF12 HI_REF P26 HD48 AG13 5 N25 HD49 AH13 HI_STB N24 HD50 AC14 HIT Y5 HD51 AF14 HITM Y3 HD52 AG14 HLOCK W5 HD53 AE14 HLRCOMP P27 HD54 AG15 HRCOMPO AC2 HD55 AG16 AC13 HD56 AG17 HREQO U6 HD57 AH15 HREQ1 7 58 17 HREQ2 R7 HD59 AF16 HREQ3 U5 HD60 AE15 HREQ4 U2 HD61 AH17 HSWNGO AA7 HD62 AD17 HSWNG1 AD13 HD63 AE16 HTRDY U7 HDSTBNO AD4 HVREF M7 R8 Y8 AB11 AB17 HDSTBPO AD3 NC AD26 AD27 HDSTBN1 AE6 PIPE AF22 HDSTBP1 AE7 RBF AE22 HDSTBN2 AE11 RDCLKIN G3 HDSTBP2 AD11 RDCLKO H3 HDSTBN3 AC15 RSO w2 HDSTBP3 AC16 RS1 W7 0 25 RS2 W6 HI 1 P24 RSTIN J27 2 27 RSVD B19 C5 C8 C23 C26 D12 3 26 27 23 25 4 M26 SBAO AH28 5 M25 SBA1 AH27 HL6 128 5 2 28 HL7 35 SBA3 AG27 Inte 82845 for SDR Datasheet Ballout and Package Information
25. BIOS responsibility Both D OPEN and D CLOSE must not be set to 1 at the same time When TSEG SMM space is enabled the TSEG space must not be reported to the OS as available system memory This is a BIOS responsibility Any address translated through the AGP Aperture GTLB must not target system memory from 000A0000h to 000FFFFFh Inte 82845 SDR Datasheet 4 5 4 5 1 System Address Address Space The MCH does not support the existence of any other I O devices beside itself on the system bus The MCH generates either hub interface or AGP bus cycles for all processor I O accesses The contains two internal registers in the processor I O space Configuration Address CONF_ADDR register and Configuration Data DATA register These locations used to implement the PCI configuration space access mechanism and as described in Chapter The processor allows 64 KB 3 bytes to be addressed within the I O space The propagates the processor I O address without any translation on to the destination bus and therefore provides addressability for 64 KB 3 byte locations Note that the upper 3 locations can be accessed only during I O address wrap around when signal 16 address signal is asserted A164 is asserted on the system bus whenever an I O access is made to 4 bytes from address OFFFDh OFFFEh or OFFFFh A16 is also asserted when access is made to 2 bytes from address OFFFF
26. Disable All of Device 1 s memory space is disabled 1 Enable The Memory and Prefetchable memory address ranges defined in the MBASE1 MLIMIT1 5 1 and PMLIMIT1 registers are enabled Access Enable IOAE1 R W 0 Disable All of device 1 s I O space is disabled 1 Enable This bit must be set to1 to enable the I O address range defined in the IOBASE1 and IOLIMIT1 registers 82 Inte 82845 for SDR Datasheet 3 6 4 Register Description PCISTS1 PCI PCI Status Register Device 1 Address Offset 06 07h Default Value 00AO0h Access RO R WC Size 16 bits PCISTSI is a 16 bit status register that reports the occurrence of error conditions associated with primary side of the virtual PCI PCI bridge embedded n the MCH Since this device does not physically reside on PCI A it reports the optimum operating conditions so that it does not restrict the capability of PCI A 15 Detected Parity Error DPE1 RO Not Implemented Hardwired to 0 14 Signaled System Error SSE1 R WC 0 Software clears this bit by writing a 1 to it 1 device 1 generated an SERR message over the hub interface for any enabled Device 1 error condition Device 1 error conditions are enabled in the ERRCMD PCICMD1 and 1 registers Device 1 error flags are read reset from the ERRSTS SSTS1 register Received Master Abort Status RMAS1 RO Not Implemented Hardwired to 0 Received Target Abort
27. Enable All processor cycles to system memory result in NOP command on the system memory interface 010 All Banks Pre charge Enable All processor cycles to system memory result in an all banks precharge command on the system memory interface 011 Mode Register Set Enable All processor cycles to system memory result in a mode register set command on the system memory interface Host address lines are mapped to memory address lines to specify the command sent Host address lines 15 3 are mapped to SMA 12 0 100 Reserved 101 Reserved 110 CBR Refresh Enable In this mode all processor cycles to system memory result in a CBR cycle on the SDRAM interface 111 Normal operation 1 0 DRAM Type DT RO Used to select between supported SDRAM types 00 Single Data Rate SDR SDRAM 01 11 Reserved Inte 82845 for SDR Datasheet 57 Register Description 3 5 19 3 5 20 58 DERRSYN DRAM Error Syndrome Register Device 0 Address Offset 86h Default Value 00h Access RO Size 8 bits This register is used to report the ECC syndromes for each quadword of a 32 byte aligned data quantity read from the system memory array _________ ________ DRAM ECC Syndrome DECCSYN After a system memory ECC error hardware loads this field with a syndrome that describes the set of bits found to be in error Note This field is locked from the time that it is loaded up to the time when the err
28. GWHT is reached thermal management start stop cycles occur based on the settings in WTT WTMW and WTHM 11 Reserved START Write Thermal Management SWTM Software writes to this bit to start and stop write thermal management 0 Write thermal management stops and the counters associated with WTMW and WTHM reset 1 Write thermal management begins based on the settings in WTMW WTHM and remains in effect until this bit is reset to 0 Reserved Inte 82845 for SDR Datasheet 3 6 24 Register Description DRTC DRAM Read Thermal Management Control Register Device 1 Address Offset 58 5Fh Default Value 0000 0000 0000 0000h Access R W L Size 64 bits 40 28 27 22 21 15 Inte 82845 for SDR Datasheet 95 Global Read Hexword Threshold GRHT The thirteen bit value held in this field is multiplied by 2 5 to arrive at the number hexwords that must be written within the Global DRAM Read Sampling Window to cause the thermal management mechanism to be invoked Read Thermal Management Time RTMT This value provides a multiplier between 0 and 63 that specifies how long counter based read thermal management remains in effect as a number of Global DRAM Read Sampling Windows For example if GDRSW is programmed to 1000_0000b and RTT is set to 01_0000b then read thermal management will be performed for 8192 10 host clocks 100 MHz seconds once invoked 128 4 10
29. O address space Control registers I O mapped into the processor I O space which control access to PCI and AGP configuration space see Section p 3 nternal configuration registers residing within the MCH are partitioned into two logical device register sets logical since they reside within a single physical device The first register set is dedicated to Host HI Bridge functionality 1 e DRAM configuration other chip set operating parameters and optional features The second register block is dedicated to Host AGP Bridge functions controls AGP interface configurations and operating parameters The MCH supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism 1 in the PCI specification The MCH internal registers I O Mapped and configuration registers are accessible by the processor The registers can be accessed as Byte Word 16 bit or DWord 32 bit quantities with the exception of CONF ADDR which can only be accessed as a DWord multi byte numeric fields use little endian ordering 1 lower addresses contain the least significant parts of the field 3 1 Register Terminology reas on Ka regse reaa ony vetes to 1e regse raro rore R WC Read Write Clear A register bit with this attribute can be read and written However a write of a 1 clears sets to 0 the corresponding bit and a write of a 0 has no effect R WO Read Write Once A register bit with thi
30. O O O O O O O 39 560 NOOO OOO OO teat OOO OO 4 OOOOO OOOOOO OOOOOOOO OOOOOOOO OOOOOO 1 270 OO O O O O O O O O O OO O O O O O O 000000 y v 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 47 18 20 2122 23 24 26 2728 5g Note All dimensions are in millimeters Inte 82845 for SDR Datasheet 135 Ballout and Package Information This page is intentionally left blank 136 I
31. OBh Default Value 06h Access RO Size 8 bits This register contains the Base Class Code of the MCH device 1 ______ Base Class Code BASEC This is an 8 bit value that indicates the Base Class Code for the MCH device 1 06h Bridge device 84 Inte 82845 for SDR Datasheet Register Description 3 6 8 MLT1 Master Latency Timer Register Device 1 Address Offset Default Value 00h Access R W Size 8 bits This functionality is not applicable It is described here since these bits should be implemented as a read write to prevent standard PCI PCI bridge configuration software from getting confused eJ _________ ______ applicable but supports read write operations Reads return previously written data 3 6 9 HDR1 Header Type Register Device 1 Offset OEh Default 01h Access RO Size 8 bits This register identifies the header layout of the configuration space wj o o 5 0 0 0 5 1 This read only field always returns 01h when read Writes have no effect 3 6 10 PBUSN1 Primary Bus Number Register Device 1 Offset 18h Default 00h Access RO Size 8 bits This register identifies that virtual PCI PCI Bridge is connected to bus 0 Bus Number Hardwired to 0 Inte 82845 for SDR Datasheet 85 Register Description 3 6 11 3 6 12 86 intel SBUSN1 Secondary Bus Number Register Device 1 Offset 1
32. The following notes apply to the ballout Note No Connect Note RSVD These pins should not be connected and should be allowed to float Note 55 Connect to ground Inte 82845 for SDR Datasheet 125 Ballout and Package Information Figure 6 Intel 82845 MCH Ballout Diagram Top View Left Side VSS vss 5 5 1 No Connect 2 RSVD These pins should not be connected and should be allowed to float 3 VSS Connect to ground 126 Inte 82845 SDR Datasheet Ballout and Package Information 7 Intel 82845 Ballout Diagram Top View Right Side 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HD50 1 HD33 VSS VSS VSS om om oom m om R _ oom om ome om e 5 1 Connect 2 RSVD These pins should not be connected and should be allowed to float 3 VSS Connect to ground Inte 82845 for SDR Datasheet 127 Ballout and Package Information Table 22 Intel 82845 MCH Ballout Listed Alphabetically by Signal Name Signal Name Ball Signal Name Ball 66IN P22 G_AD14 U25 AD_STBO R24 G_AD15 V24 AD_STBO R23 G_AD16 Y27 AD_STB1 AC27 G_AD17 Y26 AD_STB1 AC28 G_AD18 AA28 ADS V3
33. are routed to AGP The AGP interface is treated as a separate PCI bus from the configuration point of view Routing of configuration AGP is controlled via the standard PCI PCI bridge mechanism using information contained within the Primary Bus Number the Secondary Bus Number and the Subordinate Bus Number registers of the corresponding PCI PCI bridge device A detailed description of the mechanism for translating processor I O bus cycles to configuration cycles on one of the buses is described below PCI Bus 0 Configuration Mechanism The MCH decodes the Bus Number bits 23 16 and the Device Number fields of the CONF register If the Bus Number field of CONF is 0 the configuration cycle is targeting a PCI Bus 0 device The Host HI Bridge entity in the MCH is hardwired as Device 0 on PCI Bus 0 The Host AGP Bridge entity in the MCH is hardwired as Device 1 on PCI Bus 0 Configuration cycles to any of the MCH s internal devices are confined to the MCH and not sent over the hub interface Accesses to disabled MCH internal devices are forwarded over the hub interface as Type 0 Configuration Cycles Inte 82845 for SDR Datasheet 33 Register Description 3 3 3 3 1 34 intel If the Bus Number in the CONF_ADDR is non zero and is less than the value in the Host AGP device s Secondary Bus Number register or greater than the value in the Host AGP device s Subordinate Bus Number register the MCH will gene
34. as 0 Thus the bottom of the defined I O address range is aligned to a 4 KB boundary ee Address Base Corresponds to A 15 12 of the I O address Default FOh IOLIMIT1 I O Limit Address Register Device 1 Address Offset 1Dh Default Value 00h Access Size 8 bits This register controls the hosts to AGP I O access routing based on the following formula BASE lt address x IO LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are assumed to be FFFh Thus the top of the defined I O address range is at the top of a 4 KB aligned address block Address Limit Corresponds to A 15 12 of the I O address Default 0 Reserved Only 16 bit addressing supported Inte 82845 for SDR Datasheet 3 6 16 Register Description SSTS1 Secondary Status Register Device 1 Address Offset 1E 1Fh Default Value 02A0h Access RO R WC Size 16 bits 55751 is a 16 bit status register that reports the occurrence of error conditions associated with secondary side i e AGP side of the virtual PCI PCI bridge embedded in _______ 15 Detected Parity Error DPE1 R WC 0 Software sets this bit to 0 by writing a 1 to it 1 MCH detected a parity error in the address or data phase of AGP bus transactions 13 Received Master Abort Status RMAS1 R WC 0 Software sets this b
35. by configuration software to locate the base address of the graphics aperture They correspond to bits 27 4 of the base address in the processor s address space that will cause a graphics aperture translation to be inserted into the path of any memory read or write These bits can behave as though they were hardwired to 0 if programmed to do so by the APSIZE bits of the APSIZE register This causes configuration software to understand that the granularity of the graphics aperture base address is either finer or more coarse depending on the bits set by MCH specific configuration software in APSIZE Lower Hardwired Address RO Hardwired to Os This forces a minimum aperture size selected by this register to be 4 MB Prefetchable RO This bit is hardwired to 1 to identify the Graphics Aperture range as prefetchable as per the PC Local Bus Specification for the base address registers There are no side effects on reads the device returns all bytes on reads regardless of the byte enables and the MCH may merge processor writes into this range without causing errors These bits determine addressing type and they are hardwired to 00 to indicate that address range defined by the upper bits of this register can be located anywhere in the 32 bit address space Memory Space Indicator RO Hardwired to 0 to identify aperture range as a memory range Inte 82845 for SDR Datasheet Register Descripti
36. disabled and all accesses are directed to the hub interface The MCH does not respond as a PCI target for any read or write access to this area Read Only Reads are forwarded to system memory and writes are forwarded to the hub interface for termination This write protects the corresponding memory segment The MCH responds as an AGP or hub interface target for read accesses but not for any write accesses Write Only Writes are forwarded to system memory and reads are forwarded to the hub interface for termination The MCH responds as an AGP or hub interface target for write accesses but not for any read accesses Read Write This is the normal operating mode of system memory Both read and write cycles from the host are claimed by the MCH and forwarded to system memory The MCH responds as an AGP or hub interface target for both read and write accesses Inte 82845 for SDR Datasheet 59 Register Description 60 intel At the time that a hub interface or AGP accesses to the PAM region may occur the targeted PAM segment must be programmed to be both readable and writeable As an example consider BIOS that is implemented on the expansion bus During the initialization process the BIOS can be shadowed in system memory to increase the system performance When BIOS is shadowed in system memory it should be copied to the same address location To shadow the BIOS the attributes for that address range should be set to w
37. or Graphics Aperture range also physically mapped within system memory but using different address range AGP accesses to SMM space are not allowed AGP initiated cycles that target system memory are not snooped on the host bus even if they fall outside of the AGP aperture range If a cycle is outside of the system memory range then it terminates as follows Reads remap to memory address Oh return data from address Oh and set the IAAF error bit in ERRSTS register in device 0 Writes are terminated internally without affecting any chip signals or system memory AGP Accesses to MCH that Cross Device Boundaries For AGP FRAME accesses when an AGP master gets disconnected it resumes at the new address which allows the cycle to be routed to or claimed by the new target Therefore the target on potential device boundaries should disconnect accesses The MCH disconnects AGP FRAME transactions on 4 KB boundaries AGP PIPE and SBA accesses are limited to 256 bytes and must hit system memory Read accesses crossing a device boundary will return invalid data when the access crosses out of system memory Write accesses crossing out of system memory will be discarded The IAAF Error bit will be set Inte 82845 for SDR Datasheet intel 5 5 1 5 1 1 Functional Description Functional Description This chapter describes the system bus that connects the MCH to the processor the system memory interface the AGP inter
38. programmable memory attributes on 13 Legacy memory segments of various sizes in the 640 Kbytes to 1 Mbytes address range Seven Programmable Attribute Map PAM Registers are used to support these features Cacheability of these areas is controlled via the MTRR registers in the processor Two bits are used to specify memory attributes for each memory segment These bits apply to host initiator only access to the PAM areas The MCH forwards to system memory for any AGP PCI or hub interface initiated accesses to the PAM areas These attributes are RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the MCH and directed to system memory Conversely when RE 0 the host read accesses are directed to PCIO WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the MCH and directed to system memory Conversely when WE 0 the host write accesses are directed to PCIO The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or disabled For example if a memory segment has 1 and WE 0 the segment is Read Only Each PAM Register controls two regions typically 16 KB in size Each of these regions has a 4 bit field The four bits that control each region have the same encoding and defined in the following table Bits 7 3 Bits 6 2 Bits 0 Description Reserved Reserved Disabled System memory is
39. upon a Reset predetermined default states Some register values at reset are determined by external strapping options The default state represents the minimum functionality feature set required to successfully bring up the system Hence it does not represent the optimal system configuration It is the responsibility of the system initialization software usually BIOS to properly determine the DRAM configurations operating parameters and optional system features that are applicable and to program the MCH registers accordingly PCI Bus Configuration Space Access The and are physically connected by the hub interface From a configuration standpoint the hub interface is PCI bus 0 As a result all devices internal to the MCH and ICH2 appear to be on PCI bus 0 The system s primary PCI expansion bus is physically attached to the 2 and from a configuration perspective appears to be a hierarchical PCI bus behind a PCI to PCI bridge and therefore has a programmable PCI Bus number Note that the primary PCI bus is referred to as PCI_A in this document and is not PCI bus 0 from a configuration standpoint The AGP appears to system software to be a real PCI bus behind PCI to PCI bridges resident as devices on PCI bus 0 The MCH contains two PCI devices within a single physical component The configuration registers for the four devices are mapped as devices residing on PCI bus 0 Device 0 Host Hub Interface Bridge DRAM
40. which results in a Master Abort reported in the MCH s virtual PCI PCI bridge registers For Bus Numbers resulting in hub interface configuration cycles the MCH propagates the device number field as A 15 11 For bus numbers resulting in AGP type 1 configuration cycles the device number is propagated as GAD 15 11 Function Number This field is mapped to GAD 10 8 during AGP configuration cycles and A 10 8 during Hub Interface configuration cycles This allows the configuration registers of a particular function in a multi function device to be accessed The MCH ignores configuration cycles to its internal devices if the function number is not equal to 0 Register Number This field selects one register within a particular bus device and function as specified by the other fields in the Configuration Address register This field is mapped to GAD 7 2 during AGP configuration cycles and A 7 2 during hub interface configuration cycles Inte 82845 for SDR Datasheet 35 Register Description 3 3 2 3 4 Note intel CONF_DATA Configuration Data Register I O Address OCFCh Default Value 00000000h Access R W Size 32 bits CONF_DATA is a 32 bit read write window into configuration space The portion of configuration space that is referenced by CONF_DATA is determined by the contents of CONF_ADDR Configuration Data Window CDW If bit 31 of the CONF ADDR register is 1 any I O access to the CONF D
41. 52 STO AG25 50053 10 511 24 50054 010 ST2 26 50055 B9 SWE G27 50056 9 TESTIN H26 SDQ57 D8 VCC1 5 R22 R29 022 U26 W22 W29 AA22 AA26 21 50058 87 29 021 AD23 AE26 50059 AF23 AG29 25 SDQ60 C6 5 N14 N16 P13 P15 P17 R14 R16 T15 U14 U16 50061 C4 VCCA1 17 50062 T13 SDQ63 D3 8 125 129 22 23 26 SCBO C16 VCCSM A9 A13 A17 A21 A25 SCB1 E16 C1 C29 D7 D11 D15 D19 D23 D25 F6 F10 F14 F18 SCB2 C15 F22 G1 G4 G29 H8 H10 SCB3 014 12 14 16 18 20 H22 H24 J5 J7 K6 K22 SCB4 17 K24 K26 123 Inte 82845 for SDR Datasheet Ballout and Package Information Signal Name Ball VSS A3 A7 A11 A15 A19 A23 A27 D5 09 013 D17 D21 1 4 E26 E29 F8 12 F16 F20 F24 G26 H9 H11 13 15 H17 H19 H21 J1 96 J22 J26 J29 K5 7 K27 L1 L4 L6 L8 L22 L24 L26 M23 N1 N4 N8 N13 N15 N17 N22 N29 P6 P8 P14 P16 R1 R4 R13 R15 R17 R26 T6 T8 T14 16 T22 01 04 015 029 V6 V8 V22 W1 W4 W8 W26 Y6 Y22 1 AAA AA8 AA29 AB6 9 10 12 13 14 15 16 19 22 1 4 18 20 21 23 26 AD6 AD8 AD10 AD12 AD14 AD16 AD19 AD22 AE1 AE4 AE18 AE20 AE29 AF5 AF7 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF25 AG1 AG1
42. 6 bit segment is analyzed If more than 8 of the 16 signals would normally be driven low on the bus the corresponding DBI signal will be asserted and the data will be inverted prior to being driven on the bus When the processor or the MCH receives data it monitors DBI 3 0 to determine if the corresponding data segment should be inverted Inte 82845 for SDR Datasheet 107 Functional Description 5 1 2 5 1 3 108 intel System Bus Interrupt Delivery The Pentium 4 processor supports the system bus interrupt delivery the APIC serial bus interrupt delivery mechanism is not supported Interrupt related messages are encoded on the system bus as Interrupt Message Transactions In an 845 chipset platform system bus interrupts can originate from the processor on the system bus or from a downstream device on the hub interface or AGP In the later case the MCH drives the Interrupt Message Transaction onto the system bus In an 845 chipset platform the ICH2 contains IOxAPICs and its interrupts are generated as upstream hub interface memory writes Furthermore PCI 2 2 defines MSIs Message Signaled Interrupts that are also in the form of memory writes A PCI 2 2 device can generate an interrupt as an MSI cycle on it s PCI bus instead of asserting a hardware signal to the IOxAPIC The MSI can be directed to the IOxAPIC which in turn generates an interrupt as an upstream hub interface memory write Alternatively the
43. 8 AG20 AG22 AH19 AH21 AH23 AJ3 AJ5 AJ7 AJ9 AJ11 AJ13 15 AJ17 AJ27 Inte 82845 for SDR Datasheet Signal Name Ball VSSA1 U17 VSSAO U13 VTT 8 08 9 8 18 20 19 AD18 AD20 19 21 18 20 AG19 AG21 AG23 19 AJ21 AJ23 WBF AE23 NOTES 1 NC No Connect 2 RSVD These pins should not be connected and should be allowed float 3 VSS Connect to ground 133 Ballout and Package Information intel 7 1 Package Mechanical Information This section provides the MCH package mechanical dimensions The package is a 593 ball FC BGA Figure 8 Intel MCH FC BGA Package Dimensions Top and Side View Top View 37 50 33 90 16 95 16 33 90 36 28 E lt 9 67 7 Side View Substrate Die 277 See Detail 0 600 0 100 1 100 0 100 OOOOOOO 4 4 Detail 4 7 0 152 0 74 0 025 Underfill Epoxy 0 10 40 025 De Solder Bumps Units Millimeters pkg_olga_593_top side 134 Inte 82845 for SDR Datasheet intel Ballout and Package Information Figure 9 Intel MCH FC BGA Package Dimensions Bottom View gt 0 205 lt lt lt 35 560 17 780 99909909999009002 0 O O
44. 9h Default 00h Access R W Size 8 bits This register identifies the bus number assigned to the second bus side of the virtual PCI PCI bridge i e to AGP This number is programmed by the PCI configuration software to allow mapping of configuration cycles to AGP _______ Bus Number Programmable Default 00h SUBUSN1 Subordinate Bus Number Register Device 1 Offset 1Ah Default 00h Access R W Size 8 bits This register identifies the subordinate bus if any that resides at the level below AGP This number is programmed by the PCI configuration software to allow mapping of configuration cycles to AGP _________ Bus Number Programmable Default 0 Inte 82845 for SDR Datasheet Register Description intel 3 6 13 1 5 Master Latency Timer Register Device 1 Address Offset 1Bh Default Value 00h Access R W Size 8 bits This register controls the bus tenure of the MCH on AGP MLT is an 8 bit register that controls the amount of time the MCH as an AGP PCI bus master can burst data on the AGP bus The count value is 8 bit quantity however MLT 2 0 are reserved and have a value 0 when determining the count value The MCH s MLT is used to guarantee to the AGP master a minimum amount of the system resources When the MCH begins the first AGP FRAME cycle after being granted the bus the counter is loaded and enabled to count from the
45. ATA register will be mapped to configuration space using the contents of CONF ADDR Memory Mapped Register Space system memory control functions have been consolidated into a new memory mapped address region within Device 0 Function 0 This space will be accessed using a new Base Address register BAR located at Device 0 Function 0 address offset 14h By default this BAR is invisible i e read only as Os accesses to these memory mapped registers must be made as a single DWord 4 bytes or less Access must be aligned on a natural boundary The high level address map for the memory mapped registers is shown in Table 7 Memory mapped Register Address Map 36 Memory Address Offset Register Group 020h 02Bh Reserved 2Ch DRAM Width Register 02Dh 02Fh Reserved 030h 034h Strength Registers 040h 0DFh Reserved 140h 1DFh Reserved Inte 82845 SDR Datasheet Register Description 3 4 1 DRAMWIDTH DRAM Width Register Address Offset 2Ch Default Value 00h Access R W Size 8 bits This register determines the width of SDRAM devices populated in each row of memory Row 5 Width Width of devices in Row 5 0 16 bit wide devices or Unpopulated default 1 8 bit wide devices Row 4 Width Width of devices in Row 4 0 16 bit wide devices or Unpopulated default 1 8 bit wide devices 3 Row 3 Width Width of devices in Row 3 0 16 bit wide devices or Unpopu
46. C Error DSERR 0 Disable For systems that do not support ECC this bit must be disabled 1 Enable Generation of the hub interface SMI message is enabled when the system memory controller detects a single bit error 1 SMI on Multiple Bit DRAM ECC Error DMERR 0 Disable For systems not supporting ECC this bit must be disabled 1 Enable Generation of the hub interface SMI message is enabled when the system memory controller detects a multiple bit error SCICMD SCI Command Register Device 0 Address Offset CE CDh Default Value 0000h Access R W Size 16 bits This register enables various errors to generate a SCI message via the hub interface An error can generate one and only one error message via the hub interface It is software 5 responsibility to make sure that when an SCI error message is enabled for an error condition SERR and SMI error messages are disabled for that same error condition Bep SCI on Single bit ECC Error DSERR 0 Disable For systems that do not support ECC this bit must be disabled 1 Enable Generation of the hub interface SCI message is enabled when the MCH system memory controller detects a single bit error 1 5 on Multiple Bit DRAM ECC Error DMERR 0 Disable For systems not supporting ECC this bit must be disabled 1 Enable Generation of the hub interface SCI message is enabled when the MCH system memory controller detects a multiple bit e
47. CLKO RDCLKIN System Memory SDRAM Interface Hub Interface HI 10 0 HI STB HI STB I 5 7 0 PIPE gt ST 2 0 RBF amp WBF AD STB 1 0 AD_STB 1 0 SBSTB SBSTB gt AGPRCOMP Interface 4 gt gt IRDYs _ gt G_STOP G DEVSEL G_REQ gt G_GNT G_ADJ31 0 8 gt G_C BE 3 0 gt G PAR SDREF AGPREF HLRCOMP GRCOMP HRCOMP 1 0 HSWNG 0 SMRCOMP VCC1 5 VCC1_8 VCCSM 1 0 VTT vss VSSA 1 0 Voltage Refernce PLL Power IK BCLK BCLK Clocks 4 66 and gt SOCK 11 0 Reset 4 1 RSTIN TESTIN block dia 845 20 Inte 82845 for SDR Datasheet Signal Description 2 1 System Bus Signals ADS y o Address Strobe The system bus owner asserts ADS to indicate the first AGTL of two cycles of a request phase BNR Block Next Request BNRi is used to block the current request bus AGTL owner from issuing a new request This signal dynamically controls the system bus pipeline depth Bus Priority Request The is the only Priority Agent on the system AGTL bus It asserts this signal to obtain the ownership of the address bus This signal has priority over symmetric bus requests and will cause the current
48. Controller Logically this appears as a PCI device residing on PCI bus 0 Physically Device 0 contains the standard PCI registers DRAM registers the Graphics Aperture controller and other MCH specific registers Device 1 Host AGP Bridge Logically this appears as a virtual PCI to PCI bridge residing on PCI bus 0 Physically Device 1 contains the standard PCI to PCI bridge registers and the standard AGP PCI configuration registers including the AGP I O and memory address mapping Table 6 shows the Device assignment for the various internal devices Table 6 Intel MCH Internal Device Assignments 32 MCH Function Bus 0 Device DRAM Controller 8 bit Controller NOTE A physical PCI bus 0 does not exist The hub interface and the internal devices in the and 2 logically constitute PCI Bus 0 to configuration software Inte 82845 for SDR Datasheet 3 2 2 Register Description Standard PCI Bus Configuration Mechanism The PCI Bus defines a slot based configuration space that allows each device to contain up to 8 functions with each function containing up to 256 8 bit configuration registers The PCI specification defines two bus cycles to access the PCI configuration space Configuration Read and Configuration Write Memory and I O spaces are supported directly by the processor Configuration space is supported by a mapping mechanism implemented within the MCH The PCI specifica
49. Flow Control Signals RBF Read Buffer Full RBF indicates if the master is ready to accept AGP previously requested low priority read data When RBF is asserted the MCH is not allowed to initiate the return low priority read data That is the MCH can finish returning the data for the request currently being serviced RBF is only sampled at the beginning of a cycle If the AGP master is always ready to accept return read data then it is not required to implement this signal During FRAME Operation Not Used WBF Write Buffer Full Indicates if the master is ready to accept fast write AGP data from the When WBF is asserted the is not allowed to drive fast write data to the AGP master WBF is only sampled at the beginning of a cycle If the AGP master is always ready to accept fast write data then it is not required to implement this signal During FRAME Operation Not Used 2 4 3 AGP Status Signals ST 2 0 Status ST 2 0 provides information from the arbiter to an AGP Master AGP on what it may do ST 2 0 only have meaning to the master when its G_GNT is asserted When G_GNT is deasserted these signals have no meaning and must be ignored Refer to the AGP Interface Specification Revision 2 0 for further explanation of the ST 2 0 values and their meanings During FRAME Operation These signals are not used during FRAME based operation except that a 111 indicates that the master may begin F
50. GP to host core interface is asynchronous Inte 82845 for SDR Datasheet 1 4 6 Introduction Hub Interface The 8 bit hub interface connects the MCH to the ICH2 All communication between the MCH and the ICH2 occurs over the hub interface The hub interface runs at 66 MHz 266 MB s In addition to the normal traffic types the following communication also occurs over the hub interface Interrupt related messages Power management events as messages e SMI SCI and SERR error indication messages It is assumed that the hub interface is always connected to 2 Intel MCH Clocking The MCH has the following clock input pins e Differential BCLK for the host interface 66 MHz clock input for the AGP and hub interface Clock synthesizer chip s generate the system host clocks AGP and hub interface clocks and PCI clocks The system bus target speed is 400 MHz The MCH does not require any relationship between the HCLKIN host clock and the 66 MHz clock generated for AGP and the hub interface they are asynchronous to each other The AGP and hub interface runs at a constant 66 MHz base frequency The hub interface runs at 4x AGP transfers can be 1x 2x or 4x Table 5 indicates the supported frequency ratios between the various interfaces Table 5 Intel MCH Clock Ratio Table Speed Processor BCLK 100 MHz SDR 133 MHz 3 4 synchronous Inte 82845 for SDR Datasheet 17 Introduction 1 4
51. G_AD19 AB25 AGPREF AA21 G_AD20 AB27 BCLK K8 G_AD21 AA27 BCLK J8 G_AD22 AB26 BNR W3 G_AD23 Y23 BPRI Y7 G_AD24 AB23 BRO V7 G_AD25 AA24 CPURST AE17 G_AD26 AA25 DBSY V5 G_AD27 AB24 DEFER Y4 G_AD28 AC25 DBIO AD5 G AD29 AC24 DBI1 AG4 G_AD30 AC22 DBI2 AH9 G_AD31 AD24 DBI3 AD15 25 DRDY V4 G_C BE1 V23 G_ADO R27 G_C BE2 Y25 G_AD1 R28 G_C BE3 AA23 G_AD2 T25 G_DEVSEL W28 G_AD3 R25 G_FRAME Y24 G_AD4 T26 G_GNT AH25 G_AD5 T27 G_IRDY W27 G_AD6 U27 G_PAR W25 07 U28 AG24 G_AD8 V26 G_STOP W23 G_AD9 V27 G_TRDY W24 AD10 T23 GRCOMP AD25 G AD11 U23 HA3 T4 G_AD12 T24 HA4 5 G_AD13 U24 HA5 T3 128 Inte 82845 for SDR Datasheet Ballout and Package Information Signal Name Ball Signal Name Ball HA6 U3 HD8 AE3 HA7 R3 HD9 AB7 HA8 P7 HD10 AD7 9 R2 HD11 AC7 HA10 P4 HD12 AC6 HA11 R6 HD13 AC3 HA12 P5 HD14 AC8 HA13 P3 HD15 AE2 HA14 N2 HD16 5 15 7 HD17 AG2 HA16 N3 HD18 AE8 HA17 K4 HD19 AF6 HA18 M4 HD20 AH2 HA19 M3 HD21 AF3 HA20 L3 HD22 AG3 HA21 L5 HD23 AE5 HA22 K3 HD24 AH7 HA23 J2 HD25 AH3 HA24 M5 HD26 AF4 HA25 J3 HD27 AG8 HA26 L2 HD28 AG7 HA27 H4 HD29 AG6 HA28 N5 HD30 AF8 HA29 G2 HD31 5 HA30 6 HD32 AC11 1 17 HD33 AC12 HADSTBO R5 HD34 9 HADSTB1 N6 HD35 AC9 HDO
52. If Bus Number is non zero greater than the value in the Secondary Bus Number register of device 1 and less than or equal to the value programmed into the Subordinate Bus Number register of device 1 a Type 1 PCI configuration cycle will be generated AGP If Bus Number is non zero and does not fall within the ranges enumerated by device 1 s Secondary Bus Number or Subordinate Bus Number register then a hub interface Type 1 configuration cycle is generated Device Number This field selects one agent on the PCI bus selected by the Bus Number field When the Bus Number field is 00 the MCH decodes the Device Number field The MCH is always Device Number 0 for the Host Hub Interface bridge entity and Device Number 1 for the Host AGP entity Therefore when Bus Number 0 and Device 0 1 the internal devices are selected If the Bus Number is non zero and matches the value programmed into the Secondary Bus Number register a Type 0 PCI configuration cycle is generated decodes the Device Number field 15 11 and assert the appropriate GAD signal as an IDSEL For PCI to PCI Bridge translation one of the 16 IDSELs is generated When bit 15 0 bits 14 11 are decoded to assert a signal AD 31 16 IDSEL GAD16 is asserted to access Device 0 GAD17 for Device 1 and so forth up to Device 15 which asserts AD31 All device numbers higher than 15 cause a type 0 configuration access with no IDSEL asserted
53. Intel 845 Chipset 82845 Memory Controller Hub for SDR Datasheet January 2002 290725 002 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel 845 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributo
54. M register and 4 GB i e TOM to 4 GB are subtractively decoded and forwarded to the hub interface if they do decode to a space that corresponds to another device AGP Memory Address Ranges The MCH can be programmed to direct memory accesses to the AGP bus interface when addresses are within either of two ranges specified via registers in MCH device 1 configuration space The first range is controlled via the Memory Base Address MBASE1 register and Memory Limit Address MLIMIT1 register The second range is controlled via the Prefetchable Memory Base Address register and Prefetchable Memory Limit Address PMLIMIT1 register The MCH positively decodes memory accesses to AGP memory address space as defined by the following equations Memory Base Address lt Address Memory Limit Address Prefetchable Memory Base Address lt Address lt Prefetchable Memory Limit Address The plug and play configuration software programs the effective size of the range and it depends on the size of memory claimed by the AGP device The MCH device 1 memory range registers described above are used to allocate memory address space for any devices sitting on AGP bus that require such a window Inte 82845 for SDR Datasheet 4 3 Note Note System Address Map AGP DRAM Graphics Aperture Memory mapped graphics data structures can reside in a Graphics Aperture to system memory This aperture is an address
55. MSI can be directed directly to the system bus The target of a MSI is dependent on the address of the interrupt memory write The forwards inbound hub interface and AGP PCI semantic only memory writes to address xxxxh to the system bus as Interrupt Message Transactions Upstream Interrupt Messages The MCH accepts message based interrupts from AGP PCI semantics only or its hub interface and forwards them to the system bus as Interrupt Message Transactions The interrupt messages presented to are in the form of memory writes to address OFEEx xxxxh At the hub interface or AGP interface the memory write interrupt message is treated like any other memory write it is either posted to the inbound data buffer if space is available or retried if data buffer space is not immediately available Once posted the memory write from AGP or the hub interface to address OFEEx xxxxh is decoded as a cycle that needs to be propagated by the to the system bus as an Interrupt Message Transaction Inte 82845 for SDR Datasheet 5 2 5 2 1 5 2 2 Functional Description System Memory Interface The 845 chipset can be configured to support PC133 SDRAM Single Data Rate SDR SDRAM Interface Overview The MCH integrates a system memory SDRAM controller with a 64 bit wide interface and twelve system memory clock signals each at 133 MHz MCH s system memory buffers support LVTTL SDRAM signaling
56. RAME transaction Inte 82845 for SDR Datasheet 25 Signal Description 2 4 4 2 4 5 26 AGP Strobes Signals AD_STBO AD_STBO AD STB1 AD STB1 SB STB SB_STB Signals Address Data Strobe 0 This signal provides timing for 2x 4x data on AD 15 0 and the C BE 1 0 signals The agent that is providing the data drives this signal Address Data Bus Strobe 0 Compliment Differential strobe pair that provides timing information for the AD 15 0 and C BE 1 0 signals The agent that is providing the data drives this signal Address Data Bus Strobe 1 This signal provides timing for 2x and 4x clocked data on AD 31 16 C BE 3 2 signals The agent that is providing the data drives this signal Address Data Bus Strobe 1 Compliment The differential compliment to the AD_STB1 signal It is used to provide timing for 4x clocked data Sideband Strobe This signal provides timing for 2x and 4x clocked data on the SBA 7 0 bus It is driven by the AGP master after the system has been configured for 2x or 4x clocked sideband address delivery Sideband Strobe Compliment SB STB is the differential compliment to the SB STB signal It is used to provide timing for 4x clocked data For transactions on the AGP interface carried using AGP FRAME protocol these signals operate similar to their semantics in the PCI 2 1 specification the exact role of all
57. SDR Datasheet 109 Functional Description 5 2 2 1 intel Configuration Mechanism For DIMMs Detection of the type of SDRAM installed on the DIMM is supported via a Serial Presence Detect mechanism as defined in the JEDEC 168 pin DIMM specification This uses the SCL SDA and SA 2 0 pins on the DIMMs to detect the type and size of the installed DIMMs No special programmable modes are provided on the MCH for detecting the size and type of memory installed Type and size detection must be done via the serial presence detection pins Memory Detection and Initialization Before any cycles to the memory interface can be supported the MCH SDRAM registers must be initialized The MCH must be configured for operation with the installed memory types Detection of memory type and size is accomplished via the System Management Bus SMBus interface on the ICH2 This two wire bus is used to extract the SDRAM type and size information from the Serial Presence Detect port on the SDRAM DIMMs SDRAM DIMMs contain a 5 pin Serial Presence Detect interface including SCL serial clock SDA serial data and SA 2 0 Devices on the SMBus bus have a seven bit address For the SDRAM DIMMs the upper four bits are fixed at 1010 The lower three bits are strapped on the SA 2 0 pins SCL and SDA are connected directly to the system management bus on the ICH2 Thus data is read from the Serial Presence Detect port on the DIMMs via a series of I O cycles to the ICH2
58. Segment HSEG and Top of Memory Segment TSEG System Management RAM SMRAM space provides a memory area that is available for the SMI handler s and code and data storage This memory resource is normally hidden from the system OS so that the processor has immediate access to this memory space upon entry to SMM The MCH provides three SMRAM options Below MB option that supports compatible SMI handlers Above 1 MB option that allows new SMI handlers to execute with write back cacheable SMRAM Optional larger write back cacheable T_SEG area from 128 KB to 1 MB in size above 1 MB that is reserved from the highest area in system memory The above MB solutions require changes to compatible SMRAM handlers code to properly execute above 1 MB Masters from the hub interface and AGP are not allowed to access the SMM space Inte 82845 for SDR Datasheet 103 System Address 4 3 1 intel SMM Space Definition Its addressed SMM space and its DRAM SMM space define SMM space The addressed SMM space is defined as the range of bus addresses used by the processor to access SMM space System memory SMM space is defined as the range of physical system memory locations containing the SMM code SMM space can be accessed at one of three transaction address ranges Compatible High and TSEG The Compatible and TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space is the same address range Si
59. Status RTAS1 RO Not Implemented Hardwired to 0 Signaled Target Abort Status STAS1 RO Not Implemented Hardwired to 0 10 9 DEVSEL Timing DEVT1 RO Hardwired to 006 Indicate that the device 1 uses the fastest possible decode Data Parity Detected DPD1 Not Implemented Hardwired to O Fast Back to Back FB2B1 RO Hardwired to 1 The AGP port always supports fast back to back transactions 26 Reserved 66 MHz Capability CAP66 RO Hardwired to 1 Indicates that the AGP port is 66 MHz capable Reserved Inte 82845 for SDR Datasheet 83 Register Description intel 3 6 5 RID1 Revision Identification Register Device 1 Address Offset 08h Default Value See RID1 table below Access RO Size 8 bits This register contains the revision number of the MCH device 1 These bits are read only and writes to this register have no effect Revision Identification Number RID This is an 8 bit value that indicates the revision identification number for the MCH device 1 03h Stepping 04h Stepping 3 6 6 SUBC1 Sub Class Code Register Device 1 Address Offset Default Value 04h Access RO Size 8 bits This register contains the Sub Class Code for the device 1 Sub Class Code SUBC1 This is an 8 bit value that indicates the category of bridge of the MCH 04h Host bridge 3 6 7 BCC1 Base Class Code Register Device 1 Address Offset
60. a 1 to this bit to clear it 1 This bit is set when host accesses the defined memory ranges in Extended gt High Memory and T segment while not in SMM space and with the D OPEN bit SMRAM_Cache SM_CACHE RO Hardwired to 1 SMRAM_L1_EN SM_L1 RO Hardwired to 1 SMRAM L2 EN SM L2 RO Hardwired to 1 TSEG SZ 1 0 T SZ R W Selects the size of the TSEG memory block if enabled This memory is taken from the top of system memory space TOM TSEG 52 which is longer claimed by the memory controller all accesses to this space are sent to the hub interface if TSEG EN is set This field decodes as follows 00 TOM 128 KB to TOM 01 256 KB to TOM 10 512 KB to TOM TOM 1 MB to TOM Once D LCK is set this bit becomes read only TSEG EN T EN R W L Enabling of SMRAM memory TSEG 128 KB 256 KB 512 KB or 1 MB of additional SMRAM memory for Extended SMRAM space only When SMRAME 1 and TSEG 1 the TSEG is enabled to appear in the appropriate physical address space Once D LCK is set this bit becomes read only Inte 82845 for SDR Datasheet 3 5 25 Register Description ACAPID AGP Capability Identifier Register Device 0 Address Offset Default Value 0020 0002h Access RO Size 32 bits This register provides standard identifier for AGP capability 23 20 19 16 Major Revision Number MAJREV These bits prov
61. a PIPE or to operations delivered via SBA if the AGP Side Band Enable bit is also set to 1 Reserved 1 uses the Fast Write protocol for memory write transactions from the MCH to the AGP master Fast Writes occur at the data transfer rate selected by the DRATE bits 2 0 in this register Reserved Data Rate DRATE The settings of these bits determine the AGP data transfer rate One and only one bit in this field must be set to indicate the desired data transfer rate 001 1x transfer mode 010 2x transfer mode 100 4x transfer mode Configuration software updates this field by setting only one bit that corresponds to the capability of AGP master after that capability has been verified by accessing the same functional register in the AGP masters configuration space 4 Fast Write Enable FWEN 0 When this bit is set to 0 or when the data rate bits are to 1x mode the memory write transactions from the MCH to the AGP master use standard PCI protocol Note This field applies to AD and SBA buses It also applies to Fast Writes if they are enabled Inte 82845 for SDR Datasheet 67 Register Description 3 5 28 68 AGPCTRL AGP Control Register Device 0 Address Offset BO B3h Default Value 0000 0000h Access R W Size 32 bits This register provides for additional control of the AGP interface ______ ____ GTLB Enable This bit provides enable an
62. ad write Inte 82845 for SDR Datasheet 5 0 Graphics Aperture Size APSIZE Each bit in APSIZE 5 0 operates on similarly ordered bits in APBASE 27 22 of the Aperture Base configuration register When a particular bit of this field is 0 it forces the similarly ordered bit in APBASE 27 22 to behave as hardwired to 0 When a particular bit of this field is set to 1 it allows corresponding bit of the APBASE 27 22 to be read write accessible Only the following combinations are allowed 5 4 3 2 1 0 0 0 0 0 0 0 0 Default for APSIZE 5 0 000000b forces default APBASE 27 22 0000006 i e all bits respond as hardwired to 0 This provides maximum aperture size of 256 MB As another example 69 Register Description 3 5 30 Note 70 intel ATTBASE Aperture Translation Table Base Register Device 0 Address Offset B8 BBh Default Value 0000 0000h Access R W Size 32 bits This register provides the starting address of the Graphics Aperture Translation Table Base located in the system memory This value is used by the MCH Graphics Aperture address translation logic including the GTLB logic to obtain the appropriate address translation entry required during the translation of the aperture address into a corresponding physical system memory address The ATTBASE register may be dynamically changed The address provided via ATTBASE is 4 KB aligned Aperture Translation Table Base TTABLE Th
63. alue corresponds to the time period of 16 AGP 66 MHz clocks Low Priority Transaction Timer Count Value LPTTC The number of clocks programmed these bits represents the guaranteed time slice measured in eight 66 MHz clock granularity allotted to the current low priority AGP transaction data transfer state Inte 82845 for SDR Datasheet Register Description 3 5 33 of Low Memory Register Device 0 Address Offset 4 5 Default Value 0100h Access R W Size 16 bits This register contains the maximum address below 4 GB that should be treated as a memory access Note that this register must be set to a value of 0100h 16 MB or greater Usually it will sit below the areas configured for the hub interface PCI memory and the graphics aperture ___ ______ ______ of Low Memory This register contains the address that corresponds to bits 31 to 20 of the maximum system memory address that lies below 4 GB Configuration software should set this value to either the maximum amount of memory in the system or to the minimum address allocated for PCI memory or the graphics aperture whichever is smaller Programming Example 400h 1 GB An access to 4000 0000h or above will be considered above the TOM and therefore not routed to system memory It may go to AGP aperture or subtractively decode to the hub interface Inte 82845 for SDR Datasheet 73 R
64. array when entering system suspend SCKE is also used to dynamically powerdown inactive SDRAM rows There is one SCKE per SDRAM row These signals can be toggled on every rising SCLK edge RDCLKO Clock Output RDCLKO is used to emulate source synch clocking for CMOS reads This signal connects to RDCLKIN RDCLKIN Clock Input RDCLKIN is used to emulate source synch clocking for CMOS reads This signal connects to RDCLKO 2 3 Hub Interface Signals HI_ 10 0 Hub Interface Signals Signals used for the hub interface CMOS HI_STB Hub Interface Strobe One two differential strobe signals used to CMOS transmit or receive packet data over the hub interface HI_STB Hub Interface Strobe Compliment One two differential strobe CMOS signals used to transmit or receive packet data over the hub interface Inte 82845 for SDR Datasheet 23 Signal Description 2 4 AGP Interface Signals 2 4 1 AGP Addressing Signals PIPE Pipelined Read This signal is asserted by the AGP master to indicate a AGP full width address is to be enqueued on by the target using the AD bus One address is placed in the AGP request queue on each rising clock edge while PIPE is asserted When PIPE is deasserted no new requests are queued across the AD bus During SBA Operation Not Used During FRAME Operation Not Used PIPE is a sustained three state signal from masters graphics controller and is an MCH input Note Ini
65. assertion of If the count expires while the MCH s grant is removed due to AGP master request will lose the use of the bus and the AGP master agent may be granted the bus If the MCH s bus grant is not removed the MCH continues to own the AGP bus regardless of the MLT expiration or idle condition Note that the MCH always properly terminates an AGP transaction with FRAME negation prior to the final data transfer The number of clocks programmed in the MLT represents the guaranteed time slice measured in 66 MHz AGP clocks allotted to the MCH after which it must complete the current data transfer phase and then surrender the bus as soon as its bus grant is removed For example if the MLT is programmed to 18h the value is 24 AGP clocks The default value of MLT is 00h and disables this function When the MLT is disabled the burst time for the MCH is unlimited i e the MCH can burst forever Secondary Counter Value Default Os i e SMLT disabled Inte 82845 for SDR Datasheet 87 Register Description 3 6 14 3 6 15 88 intel IOBASE1 1 O Base Address Register Device 1 Address Offset 1Ch Default Value FOh Access R W Size 8 bits This register controls the hosts to AGP I O access routing based on the following formula lO BASE lt address lt IO LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are treated
66. at 133 MHz The MCH includes support for Up to 3 GB of 133 MHz SDR SDRAM PC133 unbuffered 168 pin SDR SDRAM DIMMs Maximum 3 DIMMs single sided and or double sided Configurable optional ECC The two bank select lines SBS 1 0 and the thirteen address lines SMA 12 0 allow the MCH to support 64 bit wide DIMMs using 64 Mb 128 Mb 256 Mb and 512 Mb SDRAM technologies While address lines SMA 9 0 determine the starting address for a burst burst lengths are fixed at four Twelve chip selects SCS lines allow a maximum of three rows of single sided SDRAM DIMMs and six rows of double sided SDRAM DIMMs The MCH s system memory controller targets CAS latencies of 2 3 clocks for SDRAM The MCH provides refresh functionality with a programmable rate normal SDRAM rate is 1 refresh 15 6 us Memory Organization and Configuration In the following discussion the term row refers to a set of memory devices that are simultaneously selected by a SCS signal The MCH supports a maximum of 6 rows of memory For the purposes of this discussion a side of a DIMM is equivalent to a row of SDRAM devices Table 12 Supported DIMM Configurations Density Device Width Single 55 08 55 08 88 05 55 06 85 05 55 08 55 08 55 05 n 64 MB 32 MB 128 MB 64MB 256 128 512 MB 256 DIMMs 128MB 64MB 256 128MB 512MB 256MB 1024MB 512 Inte 82845 for
67. bility to make sure that when an SERR error message is enabled for an error condition SMI and SCI error messages are disabled for that same error condition ______ SERR Non DRAM Lock 0 Disable 1 Enable will generate a hub interface SERR special cycle when a processor lock cycle is detected that does not hit system memory Reserved status SERR on Detecting Hub Interface Unimplemented Special Cycle HIAUSCERR SERR messaging for Device 0 is globally enabled in the PCICMD register 0 Disable MCH does not generate an SERR message for this event 1 Enable MCH generates a SERR message over the hub interface when an unimplemented Special Cycle is received on the hub interface SERR on Target Abort on Hub Interface Exception TAHLA_SERR 0 Disable 1 Enable Generation of the hub interface SERR message is enabled when a MCH originated hub interface cycle is completed with Target Abort completion packet or special cycle Inte 82845 for SDR Datasheet Register Description SERR on AGP Access Outside of Graphics Aperture OOGF SERR 0 Disable 1 Enable Generation of the hub interface SERR message is enabled when AGP access occurs to an address outside of the graphics aperture SERR on Invalid AGP Access IAAF SERR 0 Disable 1 Generation of the hub interface SERR message is enabled when AGP access occurs to an address outside of
68. cation Initialization Complete IC R W This bit is used for communication of software state between the memory controller and the BIOS BIOS sets this bit to 1 after initialization of the DRAM memory array is complete Dynamic Powerdown Mode Enable R W When set the system memory controller will put a pair of rows into powerdown mode when all banks are pre charged closed Once a bank is accessed the relevant pair of rows is taken out of powerdown mode The entry into powerdown mode is performed by de activation of CKE The exit is performed by activation of CKE 0 Disable System memory powerdown disabled 1 Enable System memory powerdown enabled Note Dynamic powerdown is a mobile only feature and not supported on desktop applications Active SDRAM Rows R W Implementations may use this field to limit the maximum number of SDRAM rows that may be active at once 0000 All rows allowed to be in the active state Others Reserved 21 20 DRAM Data Integrity Mode DDIM R W These bits select the system memory data integrity mode 00 Non ECC mode 10 Error checking with correction Other Reserved 10 8 Refresh Mode Select RMS R W This field determines whether refresh is enabled and if 50 at what rate refreshes will be executed 000 Reserved 001 Refresh enabled Refresh interval 15 6 us 010 Refresh enabled Refresh interval 7 8 us 011 Refresh enabled Refresh interval 64 us 111 Refresh enable
69. cation number for the MCH Device 0 03h Stepping 04h Stepping 3 5 6 SUBC Sub Class Code Register Device 0 Address Offset Default Value 00h Access RO Size 8 bits This register contains the Sub Class Code for the MCH Device 0 Description Sub Class Code SUBC This is an 8 bit value that indicates the category of bridge of the MCH 00h Host bridge 3 5 7 BCC Base Class Code Register Device 0 Address Offset OBh Default Value 06h Access RO Size 8 bits This register contains the Base Class Code of the MCH Device 0 eC Base Class Code BASEC This is an 8 bit value that indicates the Base Class Code for the MCH 06h Bridge device 48 Inte 82845 SDR Datasheet Register Description 3 5 8 MLT Master Latency Timer Register Device 0 Address Offset Default Value 00h Access RO Size 8 bits The hub interface does not comprehend the concept of Master Latency Timer Therefore this register is not implemented Hardwired to 00h Writes no effect 3 5 9 HDR Header Type Register Device 0 Address Offset OEh Default 00h Access RO Size 8 bits This register identifies the header layout of the configuration space O Hardwired to 00 Writes effect Inte 82845 for SDR Datasheet 49 Register Description 3 5 10 Note 50 APBASE Aperture Base Configu
70. ce synchronous transfers for address and data and System bus interrupt delivery Hub Interface The proprietary hub interconnect that connects the MCH to the ICH2 In this document hub interface cycles originating from or destined for the primary PCI interface on the ICH2 are generally referred to as hub interface cycles Accelerated Graphics Port AGP Refers to the AGP interface that is in the MCH The MCH supports AGP 2 0 compliant components only with 1 5 V signaling level PIPE and SBA addressing cycles and their associated data phases are generally referred to as AGP transactions FRAME cycles over the AGP bus are generally referred to as AGP PCI transactions PCI A The physical PCI bus driven directly by the 2 component It supports 5 V 32 bit 33 MHz PCI 2 2 compliant components Communication between PCI A and the MCH occurs over the hub interface Note Even though this PCI bus is referred to as PCI A it is not PCI Bus 0 from a configuration standpoint Full Reset A full reset is defined this document when RSTIN is asserted Inte 82845 for SDR Datasheet 11 Introduction Term Description GART Graphics Aperture Re map Table This table contains the page re map information used during AGP aperture address translations GTLB Graphics Translation Look aside Buffer A cache used to store frequently used GART entries UP Uni P
71. d Refresh interval 64 clocks fast refresh mode Other Reserved 56 Inte 82845 for SDR Datasheet Register Description ee Mode Select SMS R W These bits select the special operational mode of the system memory interface The special modes are intended for initialization at power up 000 Post Reset state When the MCH exits reset power up or otherwise the mode select field is cleared to 000 During any reset sequence while power is applied and reset is active the MCH asserts all CKE signals After internal reset is deasserted CKE signals remain deasserted until this field is written to a value different than 000 On this event all CKE signals are asserted During suspend MCH internal signal triggers system memory controller to flush pending commands and enter all rows into Self Refresh mode As part of resume sequence the MCH will be reset which will clear this bit field to O00 and maintain CKE signals deasserted After internal reset is deasserted CKE signals remain deasserted until this field is written to a value different than 000 On this event all CKE signals are asserted During entry to other low power states C3 S1 MCH internal signal triggers DRAM controller to flush pending commands and enter all rows into Self Refresh mode During exit to normal mode MCH signal triggers DRAM controller to exit Self Refresh and resume normal operation without S W involvement 001 NOP Command
72. d flush control of the 0 Disable Default GTLB is flushed by clearing the valid bits associated with each entry 1 Enable Normal operations of the Graphics Translation Lookaside Buffer Data Rate 4x Override 1 The RATE 2 0 bit in the AGPSTS register will be read as a 001 This bit allows the BIOS to force 1x mode Note that this bit must be set by the BIOS before AGP configuration Inte 82845 for SDR Datasheet Register Description 3 5 29 APSIZE Aperture Size Device 0 Address Offset Default Value Access Size B4h 00h R W 8 bits This register determines the effective size of the Graphics Aperture used for a particular MCH configuration This register can be updated by the MCH specific BIOS configuration sequence before the PCI standard bus enumeration sequence takes place If the register is not updated the default value will select an aperture of maximum size 1 256 MB The size of the table that will correspond to a 256 MB aperture is not practical for most applications therefore these bits must be programmed to a smaller practical value that will force adequate address range to be requested via APBASE register from the PCI configuration software 000000 1 1 0 0 0 0 0 1 4 MB 8 MB 16 MB 32 MB 64 MB 128 MB 256 MB programming APSIZE 5 0 1 11000b hardwires APBASE 24 22 000b and while enabling APBASE 27 25 as re
73. e signals This pin is weakly driven to its last driven value The signal description also includes the type of buffer used for the particular signal AGTL Open Drain interface signal Refer to the AGTL I O Specification for complete details The MCH integrates AGTL termination resistors AGP AGP interface signals These signals are compatible with AGP 2 0 1 5 V Signaling Environment DC and AC Specifications The buffers are not 3 3 V tolerant CMOS CMOS buffers Ref Voltage reference signal System address and data bus signals are logically inverted signals In other words the actual values are inverted of what appears on the system bus This must be taken into account and the addresses and data bus signals must be inverted inside the MCH processor control signals follow normal convention A 0 indicates an active level low voltage if the signal is followed by symbol and 1 indicates an active level high voltage if the signal has no suffix Inte 82845 for SDR Datasheet 19 Signal Description Figure 1 Intel MCH Simplified Block Diagram 31 3 63 0 ADS BNR DBSY DEFER DRDY HIT HITM HLOCK HREQ 4 0 HTRDY RS 2 0 CPURST BRO DBI 3 0 HADSTB 1 0 HDSTBP 3 0 HDSTBN 3 Processor System Bus Interface dk dt OR SCS 11 0 SMA 12 0 SBS 1 0 SRAS SCAS SWE SDQ 63 0 SCB 7 0 SCKE 5 0 RD
74. egister Description 3 5 34 74 MCHCFG MCH Configuration Register Device 0 Offset C6 C7h Default 0000h Access R W RO Size 16 bits 7 System Memory Frequency Select This bit must be programmed prior to memory initialization 0 Reserved 1 System Memory frequency is set to 133 MHz Reserved MDA Present MDAP R W This bit works with the VGA Enable bit in the BCTRL1 register device 1 to control the routing of host initiated transactions targeting MDA compatible I O and memory address ranges This bit should not be set when the VGA Enable bit is not set in either device 1 If the VGA enable bit is set then accesses to I O address range x3BCh 3BFh are forwarded to the hub interface MDA resources are defined as the following Memory 0B0000h 0B7FFFh 3B4h 5 3B8h 3B9h 3BAh including ISA address aliases A 15 10 are not used in decode Any I O reference that includes the I O locations listed above or their aliases are forwarded to the hub interface even if the reference includes I O locations not listed above Refer to the Chapter further information In Order Queue Depth IOQD RO This bit reflects the value sampled HA7 on the deassertion of the CPURST H It indicates the depth of the host bus in order queue level of host bus pipelining 0 HA7 was sampled asserted i e 0 the depth of the host bus in order queue is set to 1 NO pipelin
75. es as currently described in the AGP Interface Specification Revision 2 0 To use the Fast Write protocol both AGPCTRL FWCE and AGPCMD FWPE must be set to 1 AGPCTRL FWCE is set to 0 by default When this bit is set to 1 the MCH indicates that it supports Fast Writes through AGPSTAT FW When both AGPCMD FWEN and AGPCTRL FWCE are set to 1 the MCH uses Fast Write protocol to transfer memory write data to the AGP master Memory writes originating from the processor or from the hub interface use the Fast Write protocol when it is both capability enabled and enabled The data rate used to perform the Fast Writes is dependent on the bits set in the AGPCMD DRATE field bits 2 0 If bit 2 of the AGPCMD DRATE field is 1 the data transfers occur using 4x strobing If bit 1 of AGPCMD DRATE field is 1 the data transfers occur using 2x strobing If bit 0 of AGPCMD DRATE field is 1 Fast Writes are disabled and data transfers occur using standard PCI protocol Note that only one of the three DRATE bits can be set by initialization software rabie 16 82845 SDR Datasheet Functional Description intel Table 16 Data Rate Control Bits AGPCNTL AGPCND AGPCMD AGPCND AGPCMD MCH gt AGP Master Write FWCE FWPE DRATE DRATE DRATE Protocol bit 2 bit 1 bit 0 5 3 6 FRAME Transactions on AGP accepts and generates AGP FRAME transactions on the AGP bus The guarantees that AGP FRAME accesses t
76. et to extend the snoop window HITM y o Hit Modified This signal indicates that a caching agent holds a modified AGTL version of the requested line and that this agent assumes responsibility for providing the line HITM is also driven in conjunction with HIT to extend the snoop window HLOCK Host Lock All system bus cycles sampled with the assertion of HLOCK AGTL and ADS until the negation of HLOCK must be atomic i e no hub interface or AGP snoopable access to system memory are allowed when HLOCK is asserted by the processor HREQ 4 0 Host Request Command These signals define the attributes of the AGTL request In Enhanced Mode HREQ 4 0 are transferred at 2x rate HREQ 4 0 are asserted by the requesting agent during both halves of Request Phase In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request In the second half the signals carry additional information to define the complete transaction type The transactions supported by the MCH host bridge are defined in the Section HTRDY Host Target Ready HTRDY indicates that the target of the processor AGTL transaction is able to enter the data transfer phase RS 2 0 Response Status RS 2 0 indicates the type of response according to AGTL the following the table RS 2 0 000 001 010 011 100 101 110 111 22 Response Type Idle state Retry response Deferred
77. evice 8 Secondar atus Register Device 89 Adress Register Device T UU ermal Management Contro Inte 82845 for SDR Datasheet 5 6 82845 SDR Datasheet Tables General Terminolog Inte 82845 for SDR Datasheet 7 Revision History Revision Description Number Initial Release September 2001 002 Changed the document name to add the term for SDR January 2002 DWTC DRAM Write Thermal Management Control Register was incorrectly placed in Device 0 It should be in Device 1 DRTC DRAM Read Thermal Management Control Register was incorrectly placed in Device 0 It should be in Device 1 Inte 82845 for SDR Datasheet intel Intel 82845 MCH Features Accelerated Graphics Port AGP Interface Supports a single AGP device either a Intel Pentium 4 Processor 478 pin package Support Enhanced Mode Scaleable Bus Protocol 2 Address 4 Data System Bus interrupt delivery 400 MHz system bus System Bus Dynamic Bus Inversion DBI 32 bit system bus addressing 12 deep In Order Queue bus driver technology with integrated termination resistors System Memory Support Directly supports one SDR SDRAM channel 64 bits wide 72 bits with ECC 133 MEZz Single Data Rate SDR SDRAM devices 64 Mb 128 Mb 256 Mb 512 Mb
78. face the MCH power and thermal management the MCH clocking and the MCH system reset and power sequencing System Bus The MCH supports the Pentium 4 processor subset of the Enhanced Mode Scaleable Bus Source synchronous transfers are used for the address and data signals The address signals are double pumped and a new address can be generated every other bus clock At 100 MHz bus frequency the address signals run at 200 MT s for a maximum address queue rate of 50 M addresses sec The data is quad pumped and an entire 64 byte cache line can be transferred in two bus clocks At 100 MHz bus frequency the data signals run at 400 MT s for a maximum bandwidth of 3 2 GB s The MCH supports a 12 deep IOQ The MCH supports two outstanding deferred transactions on the system bus The two transactions must target different I O interfaces as only one deferred transaction can be outstanding to any single I O interface at a time Dynamic Bus Inversion The MCH supports Dynamic Bus Inversion DBI when driving and receiving data from the system bus DBI limits the number of data signals that are driven to a low voltage on each quad pumped data phase This decreases the power consumption of the DBI 3 0 indicates if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase DBI 3 0 4 Data Bits DBIO HD 15 0 DBI14 HD 31 16 DBI2 HD 47 32 DBIS HD 63 48 When the processor or the MCH drives data each 1
79. ge Function 0 Inte 82845 for SDR Datasheet 45 Register Description 3 5 3 46 Command Register Device 0 Address Offset 04 05 Default 0006h Access R W RO Size 16 bits Since MCH Device 0 does not physically reside on PCIO many of the bits are not implemented e Fast Back to Back RO implemented Hardwired to 0 This bit controls whether not the master can do fast back to back write Since device 0 is strictly a target this bit is not implemented SERR Enable SERRE R W This bit is a global enable bit for Device 0 SERR messaging The MCH does not have an SERR signal The MCH communicates the SERR condition by sending a SERR message to the ICH2 0 Disable SERR message is not generated by the MCH for Device 0 1 Enable The MCH is enabled to generate SERR messages over the hub interface for specific Device 0 error conditions that are individually enabled in the ERRCMD Register The error status is reported in the ERRSTS and PCISTS registers NOTE This bit only controls SERR message for the Device 0 Device 1 has its own SERRE bits to control error reporting for error conditions occurring on their respective devices 1 Address Data Stepping RO Not implemented Hardwired to 0 Parity Error Enable PERRE RO Not implemented Hardwired to 0 The PERR signal is not implemented by the MCH VGA Palette Snoop RO Not implemented Hardwired t
80. guration are not supported by the MCH as a target and result in master abort e Exclusive Access The MCH does not support PCI locked cycles as a target Fast Back to Back Transactions The as a target supports fast back to back cycles from AGP FRAME initiator As an initiator of AGP FRAME cycle the MCH only supports the following transactions Memory Read and Memory Read Line supports reads from host to AGP does not support reads from the hub interface to AGP Memory Read Multiple This command is not supported by the as an AGP FRAME initiator Memory Write The initiates AGP cycles on behalf of the host or the hub interface As an initiator the MCH does not issue Memory Write and Invalidate cycles The MCH does not support write merging or write collapsing The MCH allows non snoopable write transactions from the hub interface to the AGP bus Read and Write read and write cycles from the host are sent to the AGP bus The I O base and limit address range for the AGP bus are programmed in the configuration registers All other accesses that do not correspond to this programmed address range are forwarded to the hub interface Exclusive Access The MCH does not issue a locked cycle on the AGP bus on behalf of either the host or the hub interface The hub interface and host locked transactions to AGP are initiated as unlocked transactions by the MCH
81. h The I O accesses other than ones used for configuration space access are forwarded normally to the hub interface unless they fall within the AGP I O address range as defined by the mechanisms explained below The MCH does not post I O write cycles to IDE The MCH never responds to I O or configuration cycles initiated on AGP or the hub interface Hub interface transactions requiring completion are terminated with master abort completion packets on the hub interface Hub interface write transactions not requiring completion are dropped AGP PCI I O reads are never acknowledged by the MCH Intel MCH Decode Rules and Cross Bridge Address Mapping The address map described above applies globally to accesses arriving on any of the three interfaces 1 processor system bus hub interface or Hub Interface Decode Rules The MCH accepts accesses from the hub interface with the following address ranges All memory read and write accesses to main DRAM except SMM space All memory write accesses from the hub interface to AGP memory range defined by MBASEI PMBASEI and PMLIMITI All memory read write accesses to the Graphics Aperture defined by APBASE and APSIZE Memory writes to VGA range on AGP if enabled memory reads from the hub interface that target gt 4 GB memory range are terminated with a master abort completion and all memory writes 24 GB from the hub interface are ignored Inte
82. h can be independently programmed for each configuration The actual strength used for each signal is determined by the DRAMWIDTH Register offset 2Ch ee SCS x16 Strength Control This field selects the signal drive strength 000 0 75 X default 001 1 00 X 010 1 25 X 011 1 50 X 100 2 00 X 101 2 50 X 110 3 00 X 111 4 00 X SCS x8 Strength Control This field selects the signal drive strength 000 0 75 X default 001 1 00 X 010 1 25 X 011 1 50 X 100 2 00 X 101 2 50 110 2 3 00 X 111 24 00 X Inte 82845 for SDR Datasheet 3 4 5 Register Description CKSTR Strength Control Register Clock Signal Group Memory Address Offset 33h Default Value 00h Access R W Size 8 bits This register controls the drive strength of the I O buffers for the Clock CK signal group including both the CK and CK signals This group has two possible loadings depending on the width of SDRAM devices used in each row of memory x8 or x16 The proper strength can be independently programmed for each configuration The actual strength used for each signal is determined by the DRAMWIDTH Register offset 2Ch 0 x16 Strength Control This field selects the signal drive strength 000 0 75 X default 001 1 00 X 010 1 25 X 011 1 50 X 100 2 00 X 101 2 50 X 110 3 00 X 111 4 00 X CK x8 Strength Control This field selects the signal drive strength 000
83. hancements over the Compatible Mode P6 bus protocol are e Source synchronous double pumped address Source synchronous quad pumped data e System bus interrupt and side band signal delivery The MCH supports a 64 byte cache line size Only one processor is supported at a system bus frequency of 400 MHz The MCH supports a 3 4 host to memory frequency ratio using the 100 MHz clock The integrates termination resistors on all of the AGTL signals The MCH supports 32 bit system bus addresses allowing the processor to access the entire 4 GB of the MCH memory address space The MCH has a 12 deep In Order Queue to support up to twelve outstanding pipelined address requests on the system bus The MCH supports two outstanding defer cycles at a time however only one to any particular I O interface Processor initiated I O cycles are positively decoded to AGP PCI or MCH configuration space and subtractively decoded to the hub interface Processor initiated memory cycles are positively decoded to AGP PCI or system memory and are again subtractively decoded to the hub interface if under 4 GB AGP semantic memory accesses initiated from to system memory are not snooped on the system bus Memory accesses initiated from AGP PCI using PCI semantics and from the hub interface to system memory will be snooped on the system bus Memory accesses whose addresses lie within the AGP aperture are translated using the AGP address
84. hat 4 GB Support 4G Hardwired to 0 to indicate that the MCH does not support addresses greater than 4 Fast Write Support FW Hardwired to 1 to indicate that the MCH supports Fast Writes from the host to the AGP master Data Rate Support RATE Hardwired to 111 After reset the MCH reports its data transfer rate capability Bit 0 identifies if AGP device supports 1x data transfer mode bit 1 identifies if AGP device supports 2x data transfer mode bit 2 identifies if AGP device supports 4x data transfer mode 111 1x 2x and 4x data transfer modes are supported by Note The selected data transfer mode applies to both AD bus and SBA bus It also applies to Fast Writes if they are enabled Inte 82845 for SDR Datasheet 3 5 27 Register Description AGPCMD AGP Command Register Device 0 Address Offset 8 Default Value 0000_0000 Access R W Size 32 bits This register provides control of the AGP operational parameters ee 7 SideBand Address Enable 5 0 Disable 1 Enable AGP Enable AGPEN 0 ignores all AGP operations including the sync cycle Any AGP operation received while this bit is 1 will be serviced even if this bit is set to 0 If this bit transitions from a 1 to a O on clock edge in the middle of an SBA command being delivered in 1X mode the command will be issued 1 The MCH will respond to AGP operations delivered vi
85. he code for reads from memory but does not correct any errors that are found Thus the read performance hit associated with ECC is not incurred AGP Interface Overview The MCH supports 1 5 V AGP 1x 2x 4x devices The AGP signal buffers are 1 5 V drive receive buffers are not 3 3 volt tolerant The MCH supports 2x 4x source synchronous clocking transfers for read and write data and sideband addressing The MCH also support 2x and 4x clocking for Fast Writes initiated from the MCH on behalf of the processor AGP PIPE or SBA 7 0 transactions to system memory do not get snooped and are therefore not coherent with the processor caches AGP FRAME transactions to system memory snooped AGP PIPE and SBA 7 0 accesses to and from the hub interface are not supported AGP access from AGP master to the hub interface are also not supported Only the AGP FRAME memory writes from the hub interface are supported AGP Target Operations AS an initiator the MCH does not initiate cycles using AGP enhanced protocols The MCH supports AGP cycles targeting the interface to system memory only The MCH supports interleaved AGP PIPE AGP FRAME SBA 7 0 and FRAME transactions Inte 82845 for SDR Datasheet Functional Description intel Table 15 AGP Commands Supported by the Intel MCH When Acting as an AGP Target Command Encoding Cycle Destination Hi Priority Read System memory 0100 Hub i
86. his segment can be assigned read and write attributes It is by default after reset read write disabled and cycles are forwarded to the hub interface By manipulating the read write attributes the MCH can shadow BIOS into system memory ISA Hole Memory Space BIOS software may optionally open a window between 15 MB and 16 MB 0 0080 0000h to 0 00FF FFFFh that relays transactions to the hub interface instead of completing them with a system memory access This window is opened by programming the FDHC HEN configuration field Inte 82845 for SDR Datasheet Note 4 1 5 4 1 6 4 1 7 System Address Map TSEG SMM Memory Space The TSEG SMM space TSEG to TOM allows system management software to partition a region of system memory just below the top of low memory TOM that is accessible only by system management software This region may be 128 KB 256 512 KB or 1 MB in size depending on the ESMRAMC TSEG SZ field SMM memory is globally enabled by SMRAM G_SMRAME Requests can access SMM system memory when either SMM space is open SMRAM D_OPEN or the receives SMM code request on its system bus To access the TSEG SMM space TSEG must be enabled by ESMRAMC T EN When all of these conditions met then a system bus access to the TSEG space between TOM TSEG and is sent to system memory If the high SMRAM is not enabled or if the TSEG is not enabled then all memory requests from al
87. host clocks 16 Read Thermal Management Monitoring Window RTMMW The value in this register is padded with four Os to specify a window 0 2047 host clocks with 16 clock granularity While the thermal management mechanism is invoked system memory reads are monitored during this window If the number of hexwords read during the window reaches the Read Thermal Management Hexword Maximum bits 14 3 then read requests are blocked for the remainder of the window Read Thermal Management Hexword Maximum This field defines the maximum number of hexwords between 0 4095 that are permitted to be read from system memory within one Read Thermal Management Monitoring Window Read Thermal Management Mode RTMMode 00 Thermal management via counters and Hardware Thermal Management_on signal mechanisms disabled 01 Hardware Thermal Management_on signal mechanism is enabled In this mode as long as the Thermal Management_on signal is asserted read thermal management is in effect based on the settings in RTMW and RTHM When the Thermal Management_on signal is deasserted read thermal management stops and the counters associated with the RTMW and RTHM are reset When the hardware Thermal Management_on signal mechanism is not enabled the Thermal Management_on signal has no effects 10 Counter mechanism controlled through GDRSW and GRHT is enabled When the threshold set in GDRSW is reached thermal management star
88. ide a major revision number of AGP specification that this version of the conforms This field is hardwired to value of 00106 implying Rev 2 x Minor AGP Revision Number MINREV These bits provide a minor revision number of AGP specification that this version of the MCH conforms This number is hardwired to value of 0000 implying Rev x 0 Together with the major revision number this field identifies MCH as an AGP Revision 2 0 compliant device Next Capability Pointer NCAPTR AGP capability is the first and the last capability described via the capability pointer mechanism therefore these bits are hardwired to Oh to indicate the end of the capability linked list AGP Capability ID CAPID This field identifies the linked list item as containing AGP registers This field has a value of 0000 00100 assigned by the PCI SIG Inte 82845 for SDR Datasheet 65 Register Description 3 5 26 66 AGPSTAT AGP Status Register Device 0 Address Offset A4 A7h Default Value 1 00 0217 Access RO Size 32 bits This register reports AGP device capability status S 2 Request Queue RQ This field contains the maximum number AGP command requests the MCH is configured to manage 1Fh Allows a maximum of 32 outstanding AGP command requests Side Band Addressing Support SBA Hardwired to 1 to indicate that the MCH supports side band addressing Reserved Greater t
89. ing support on the host bus 1 HA7 was sampled 1 i e undriven on the host bus the depth of the host bus in order queue is configured to the maximum allowed by the host bus protocol i e 12 Note that the has 12 deep Note that HA7 15 not driven by the during CPURSTH If 100 size of 1 is desired HA7 must be driven low during CPURST by an external source APIC Memory Range Disable APICDIS R W 0 The sends cycles between 0 FECO 0000 and 0 FEC7 FFFF to the hub interface 1 The forwards accesses to the IOAPIC regions to the appropriate interface as specified by the memory and PCI configuration registers Reserved a Reserved Inte 82845 for SDR Datasheet intel 3 5 35 Register Description ERRSTS Error Status Register Device 0 Address Offset C8 C9h Default Value 0000h Access R WC Size 16 bits This register is used to report various error conditions via the hub interface messages to ICH2 An SERR SMI or SCI error message may be generated via the hub interface on a zero to one transition of any of these flags when enabled in the PCICMD ERRCMD SMICMD or SCICMD registers respectively These bits are set regardless of whether or not the SERR is enabled and generated LOCK to Memory Flag 0 Software must write a 1 to clear this status bit 1 Indicates that a host initiated LOCK cycle targeting n
90. is determines the number of clocks the DRAM controller will remain in the idle state before it begins precharging all pages 000 infinite 001 0 DRAM clocks 010 8 DRAM clocks 011 16 DRAM clocks 100 64 DRAM clocks Others Reserved 10 9 Activate to Precharge delay tRAS This bit controls the number of DRAM clocks for tRAS 00 7 clocks 01 6 clocks 10 5 clocks 11 Reserved Reserved CAS Latency tCL This bit controls the number of DRAM clocks between when a read command is sampled by the SDRAMs and when the MCH samples read data from the SDRAMs 00 Reserved 01 3 clocks 10 2 clocks 11 Reserved Reserved DRAM RAS to CAS Delay tRCD This bit controls the number of clocks inserted between row activate command and a read or write command to that row 0 DRAM clocks 1 2 DRAM clocks DRAM RAS Precharge tRP This bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same row 0 DRAM clocks 1 2 DRAM clocks Inte 82845 for SDR Datasheet 55 Register Description 3 5 18 DRC DRAM Controller Mode Register Device 0 Offset 7C 7Fh Default 00000000h Access R W RO Size 32 bits Revision Number REV R W Reflects the revision number of the format used for SDRAM register definition Currently this field must be 00 since this revision rev 00 is the only existing version of the specifi
91. is field contains pointer to the base of translation table used to map memory space addresses in the aperture range to addresses in system memory Note It should be modified only when the GTLB has been disabled Inte 82845 for SDR Datasheet Register Description intel 3 5 31 Interface Multi Transaction Timer Register Device 0 Address Offset BCh Default Value 00h Access R W Size 8 bits AMTT is 8 bit register that controls the amount of time that the MCH arbiter allows AGP master to perform multiple back to back transactions The MCH AMTT mechanism is used to optimize the performance of the AGP master using PCI protocol that performs multiple back to back transactions to fragmented memory ranges and as a consequence it can not use long burst transfers The AMTT mechanism applies to the host AGP transactions as well and it guarantees to the processor a fair share of the AGP interface bandwidth The number of clocks programmed in the AMTT represents the guaranteed time slice measured in 66 MHz clocks allotted to the current agent either AGP master or host bridge after which the AGP arbiter will grant the bus to another agent The default value of AMTT 15 and disables this function The AMTT value can be programmed with 8 clock granularity For example if the AMTT is programmed to 18h then the selected value corresponds to the time period of 24 AGP 66 MHz clocks
92. it to 0 by writing a 1 to it 1 MCH terminated a Host to AGP with an unexpected master abort Received Target Abort Status RTAS1 R WC 0 Software sets this bit to 0 by writing a 1 to it 1 MCH initiated transaction on AGP is terminated with a target abort Signaled Target Abort Status STAS1 RO Hardwired to a 0 The MCH does not generate target abort on AGP DEVSEL Timing DEVT1 RO Hardwired to 01 This 2 bit field indicates the timing of the DEVSEL signal when the MCH responds as a target on AGP This field indicates the time when a valid DEVSEL can be sampled by the initiator of the PCI cycle 01 Medium timing Master Data Parity Error Detected DPD1 RO Hardwired to 0 MCH does not implement signal Fast Back to Back 2 1 Hardwired to 1 as target supports fast back to back transactions on AGP 66 MHz Capable CAP66 RO Hardwired to 1 AGP bus is capable of 66 MHz operation Inte 82845 for SDR Datasheet 89 Register Description 3 6 17 3 6 18 90 Note intel MBASE1 Memory Base Address Register Device 1 Address Offset 20 21h Default Value FFFOh Access R W Size 16 bits This register controls the host to AGP non prefetchable memory accesses routing based on the following formula MEMORY_BASE1 lt address lt MEMORY_LIMIT1 The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the
93. l interfaces are forwarded to system memory If the TSEG SMM space is enabled and an agent attempts a non SMM access to TSEG space then the transaction is specially terminated Hub interface and AGP originated accesses are not allowed to SMM space IOAPIC Memory Space The IOAPIC space 0 FECO 0000h to 0 7 FFFFh is used to communicate with IOAPIC interrupt controllers that may be populated on the hub interface Since it is difficult to relocate an interrupt controller using plug and play software fixed address decode regions have been allocated for them Processor accesses to the IOAPICO region are always sent to the hub interface System Bus Interrupt APIC Memory Space The system bus interrupt space FEEO 0000h to 0 FEEF is the address used to deliver interrupts to the system bus Any device may issue a memory write to OFEEx xxxxh The MCH forwards this memory write along with the data to the system bus as an Interrupt Message Transaction The MCH terminates the system bus transaction by providing the response and asserting TRDY This memory write cycle does go to system memory High SMM Memory Space The HIGHSMM space 0 FEDA 0000h to 0 FEDB FFFFh allows cacheable access to the compatible SMM space by re mapping valid SMM accesses between 0 FEDA 0000 and 0 to accesses between 0 000A 0000 and 0 0008 FFFF The accesses are remapped when SMRAM space is enabled an appropria
94. lated default 1 8 bit wide devices Row 2 Width Width of devices in Row 2 0 16 bit wide devices or Unpopulated default 1 8 bit wide devices Row 1 Width Width of devices in Row 1 0 16 bit wide devices or Unpopulated default 1 8 bit wide devices Row 0 Width Width of devices in Row 0 0 16 bit wide devices or Unpopulated default 1 8 bit wide devices Note Since there are multiple clock signals assigned to each row of a DIMM it is important to clarify exactly which row width field affects which clock signal Row Parameters SDR Clocks Affected 0 SCK 0 SCK 2 1 SCK 1 SCK 3 2 SCK 4 SCK 6 3 SCK 5 SCK 7 4 SCK 8 SCK 10 5 SCK 9 SCK 11 Inte 82845 for SDR Datasheet 37 Register Description 3 4 2 38 intel DQCMDSTR Strength Control Register SDQ and CMD Signal Groups Memory Address Offset 30h Default Value 00h Access R W Size 8 bits This register controls the drive strength of the I O buffers for the DQ DQS and CMD signal groups 0 CMD Strength Control SRAS SCAS SWE SMA 12 0 SBS 1 0 This field selects the signal drive strength 000 0 75 X default 001 1 00 X 010 1 25 X 011 1 50 X 100 2 00 X 101 2 50 X 110 3 00 X 111 4 00 X SDQ SDQS Strength Control This field selects the signal drive strength 000 0 75 X default 001 1 00 X 010 1 25 X 011 1 50 X 100 2 00 X
95. nable Compatible SMRAM functions are enabled providing 128 of DRAM accessible at the A0000h address while in SMM ADS with SMM decode To enable Extended SMRAM function this bit has to be set to 1 Once D LCK is set this bit becomes read only Compatible SMM Space Base Segment C BASE SEG RO This field indicates the location of SMM space SMM DRAM is remapped It is simply made visible if the conditions are right to access SMM space otherwise the access is forwarded to the hub interface 010 Hardwired to 010 to indicate that the supports the SMM space at A0000h BFFFFh Inte 82845 for SDR Datasheet 63 Register Description 3 5 24 64 intel ESMRAMC Extended System Mgmt RAM Control Register Device 0 Address Offset Default Value 38h Access RO R W R WC R W L Size 8 bits The Extended SMRAM register controls the configuration of Extended SMRAM space The Extended SMRAM E_SMRAM memory provides a write back cacheable SMRAM memory space that is above 1 MB SMRAM SMRAME R W L Controls the SMM memory space location i e above 1 MB or below 1 MB When G_SMRAME is 1 and H_SMRAME this bit is set to 1 the high SMRAM memory space is enabled SMRAM accesses from FEDA_0000h to FEDB_FFFFh are remapped to DRAM address 000A0000h to OOOBFFFFh Once D LCK is set this bit becomes read only E SMRAM ERR E SMERR R WC 0 The software must write
96. nce the High SMM space is remapped the addressed and system memory SMM space is a different address range Note that the High system memory space is the same as the Compatible Transaction Address space Therefore the table below describes three unique address ranges Compatible Transaction Address e High Transaction Address TSEG Transaction Address Table 11 SMM Space Address Ranges SMM Space Enabled Transaction Address Space System Memory Space Compatible A0000h to BFFFFh A0000h to BFFFFh 4 3 2 104 Note Note High OFEDA0000h to OFEDBFFFFh A0000h to BFFFFh TSEG TOM TSEG SZ to TOM TOM TSEG SZ to TOM High SMM This is different than in some previous chipsets where the High segment was the 384 KB region from A0000h to FFFFFh TSEG SMM Note that this is different than in previous chipsets where the TSEG address space was offset by 256 MB to allow for simpler decoding and the TSEG was remapped to just under the TOM In the MCH the 256 MB does not offset the TSEG region and it is not remapped SMM Space Restrictions If any of the following conditions are violated the results of SMM accesses are unpredictable and may cause the system to hang The Compatible SMM space must not be setup as cacheable High or TSEG SMM transaction address space must not overlap address space assigned to system memory the aperture range or to any devices including hub interface and AGP devices This is a
97. nents the 82845 Memory Controller Hub MCH for the host bridge and the Intel 82801BA I O Controller Hub 2 for the I O subsystem The provides the processor interface system memory interface AGP interface and hub interface in an 845 chipset desktop platform This document describes the 82845 Memory Controller Hub MCH for use with SDR Single Data Rate memory devices Section 1 3 provides an overview of the 845 chipset Terminology and Notations This section provides the definitions of some of the terms used in this document Notations used for data types and numbers are also included In addition Section B 1 contains register terminology definitions Table 1 General Terminology Term Description MCH The Memory Controller Hub component that contains the processor interface System Memory DRAM controller and AGP interface It communicates with the I O controller hub ICH2 and other IO controller hubs over proprietary interconnect called the hub interface ICH2 The I O Controller Hub component that contains the primary PCI interface LPC interface USB ATA 100 97 and other I O functions It communicates with the MCH over proprietary interconnect called the hub interface Host This term is used synonymously with processor Core The internal base logic in the MCH System Bus Processor to MCH interface The system bus runs at 400 MHz from a 100 MHz quad pumped clock It consists of sour
98. nes the power up default value for that bit Table 10 Intel MCH Configuration Space Device 1 Offset 00 01h Oth vb Vendor Identification Identification 8086 ie o e Ronsona RO mem 7 ow Sw secese wm fo em Soi fon fo CS em meme 7 vem meme o wm _ m mem 7 7 50 57h DWTC Write Thermal Management Control ru Oh 80 Inte 82845 for SDR Datasheet 3 6 1 3 6 2 Register Description Address Symbol Offset 58 5Fh DRTC DRAM Read Thermal Management Control 0000000 R W L E 59 ___ __ _______ Reserved VID1 Vendor Identification Register Device 1 Address Offset 00 01 Default Value 8086h Attribute RO Size 16 bits The register contains the vendor identification number This 16 bit register combined with the DID1 Register uniquely identifies any PCI device Writes to this register have no effect Vendor Identification Number This is a 16 bit value assigned to Intel Intel VID 8086h DID1 Device Identification Register Device 1 Address Offset 02 03h Default Value 1A31h Attribute RO Size 16 bits This 16 bit register combined with the VIDI register uniquely identifies any PCI device Writes to this register have no effect
99. nput High Voltage HI REF 0 15 V VoL Output Low Voltage 0 1 x VCC1_8 V lo 1 mA Von Output High Voltage 0 9x VCC1_8 V 1 mA lo Output Low Current 1 mA Q Vo Output High Current 1 mA Input Leakage Current 150 15 0 lt lt 1 8 2 58 3 17 pF Clock Signals Input Low Voltage 0 8 V Input High Voltage 2 4 V CiN v Input Capacitance 1 2 1 4 pF w Input Low Voltage 0 V Vin w Input High Voltage 0 660 0 710 0 850 V Vcnoss w Crossing Voltage 0 45 x Vn 0 5 x 10 55 x V w Input Capacitance 0 94 14 pF RSTIN Signals Input Low Voltage 0 8 V Vin p Input High Voltage 2 0 V lLeak p Input Leakage Current 100 0 lt Vin lt VCC3_3 Inte 82845 for SDR Datasheet 123 Electrical Characteristics This page is intentionally left blank 124 Inte 82845 for SDR Datasheet Ballout and Package Information intel 7 Ballout and Package Information This chapter provides the MCH ballout and package information The ballout footprint is shown in Figure lFigure ese figures represent the ballout organize number lable igure 6 and Figure 7 These fig he ballout organized by ball number Table 22 provides the MCH ballout listed alphabetically by signal name
100. nsities supported vary with the type In general the MCH supports 64 Mb 128 Mb 256 Mb and 512 Mb SDRAM devices The multiplexed row column address to the SDRAM memory array is provided by the SBS 1 0 and SMA 12 0 signals These addresses are derived from the system address bus as defined by able 14 SDRAM devices Table 14 Address Translation and Decoding Tech Configuration Row size Row 64 1 16x4bks 32 12 8 2 Row B mu 64 Mb 2Meg x 8 x 4 bks 64 12 9 2 128 Mb x 16 x 4bks 64 12 9 2 128 Mb x 8 x 4bks 128 MB 12 10 2 Ro 256 x 16 x 4 bks 128 13x9x2 Ro OO cl __ _ _ 512 x 16 x 4bks 256 13 10 2 Row 27 13 27 26 25 24 15 16 23 22 21 20 19 18 17 e lets ie o o n ep 21 Inte 82845 for SDR Datasheet 111 Functional Description 5 2 4 5 2 4 1 5 3 5 3 1 112 intel DRAM Performance Description The overall memory performance is controlled by the DRAM Timing DRT Register pipelining depth used in the MCH memory speed grade and the type of SDRAM used in the system In addition the exact performance in a system is also dependent on the total memory sup
101. nte 82845 for SDR Datasheet Testability intel 8 Testability In the MCH testability for Automated Test Equipment ATE board level testing has been implemented as an XOR chain An XOR tree is a chain of XOR gates each with one input pin connected to it see Figure 10 Figure 10 XOR Tree Chain VCC1 8 Dp Input Input Input Input Input xor vsd The algorithm used for in circuit test is as follows Drive all input pins to an initial logic level 1 Observe the output corresponding to scan chain being tested Toggle pins one at a time starting from the first pin in the chain and continuing to the last pin from its initial logic level to the opposite logic level Observe the output changes with each pin toggle 8 1 Test Mode Initialization XOR test mode can be entered by pulling three shared pins reset straps low through the rising transition of RSTIN The signals that need to be pulled are as follows e 0 Global strap enable e SBAI 0 XOR strap e ST2 0 PLL Bypass mode it is recommended to enter PLL Bypass test mode Inte 82845 for SDR Datasheet 137 Testability 8 2 XOR Chains Note RSTIN TESTIN and all Rcomp buffers are not part of any XOR chain Table 23 XOR Chain 0 Chain 0 Ball Signal Name Initial Logic Level 3 owe Lm pue 00 s ome owe
102. nterface Cycle goes to DRAM with byte enables inactive Hi Priority Write 0101 System memory High priority write 0101 Hub interface Cycle goes to DRAM with byte enables inactive does not go to the hub interface Long Read 1000 System memory Low priority read Hub interface Complete locally with random data does not go to the hub interface Hi Priority Long 1001 System memory High priority read Read Hub interface Complete with random data Complete with QW of random data request queue NOTES 1 refers to a function that is not applicable A A A A Flush 1010 MCH A CH summarized in The MCH supports both normal and high priority read and write requests The MCH does not support AGP cycles to the hub interface PIPE and SBA cycles do not require coherency management and all AGP initiator accesses to system memory using AGP PIPE or SBA protocol are treated as non snoopable cycles These accesses are directed to the AGP aperture in system memory that is programmed as either uncacheable UC memory or write combining WC in the processor s MTRRs As a target of an AGP cycle the MCH supports all the transactions targeting system memory rabie 15 15 Inte 82845 for SDR Datasheet 113 Functional Description 5 3 2 5 3 3 5 3 4 5 3 5 114 intel AGP Transaction Ordering The MCH observes transaction ordering rules as defined by the AGP Interface Specification
103. o 0 Memory Write and Invalidate Enable MWIE RO Not implemented Hardwired to 0 Special Cycle Enable SCE RO Not implemented Hardwired to 0 2 Bus Master Enable BME RO Hardwired to 1 The MCH is always enabled as a master on the hub interface Memory Access Enable MAE RO Not implemented Hardwired to 1 The MCH always allows access to system memory Access Enable IOAE RO Not implemented Hardwired to 0 7 5 4 3 1 Inte 82845 SDR Datasheet 3 5 4 Register Description PCISTS PCI Status Register Device 0 Address Offset 06 07h Default Value 0090h Access RO R WC Size 16 bits PCISTS is 16 bit status register that reports the occurrence of error events on Device 08 on the hub interface Since MCH Device 0 is the Host to hub interface bridge many of the bits are not implemented Signaled System Error SSE R WC 0 Software clears this bit by writing a 1 to it 1 MCH Device 0 generated an SERR message over the hub interface for any enabled Device 0 error condition Device 0 error conditions are enabled in the and ERRCMD Registers Device 0 error flags are read reset from the PCISTS or ERRSTS Registers Received Master Abort Status RMAS R WC 0 Software clears this bit by writing a 1 to it 1 generated a hub interface request that receives a Master Abort completion packet or Master Abort Special Cycle 12 Received Target Abort Stat
104. o system memory kept coherent with the processor caches by generating snoops to the host bus LOCK SERR and PERR signals are not supported MCH Initiator and Target Operations able 17 summarizes target operation for AGP FRAME initiators The cycles can be either destined to system memory or the hub interface Table 17 Commands a by the Intel When Acting as FRAME Target PCI Command Intel Cycle Destination Response as a FRAME Target Interrupt Interrupt Acknowledge 0 ee M Inte 82845 for SDR Datasheet 115 Functional Description 116 PCI Command 3 0 Intel Cycle Destination Response as a FRAME Target Dual Address Cycle 1101 N A Memory Read Line 1110 System Memory Memory Write and 1111 System memory Posts data Invalidate 1111 Hub interface Posts Data NOTES 1 N A refers to a function that is not applicable As a target of an AGP FRAME cycle the MCH only supports the following transactions Memory Read Memory Read Line and Memory Read Multiple These commands supported identically by the MCH The MCH does not support reads of the hub interface bus from AGP Memory Write and Memory Write Invalidate These commands are aliased and processed identically Other Commands Other commands e g I O and Confi
105. on intel 3 5 11 SVID Subsystem Vendor Identification Device 0 Offset 2C 2Dh Default 0000h Access R WO Size 16 bits This value is used to identify the vendor of the subsystem 2 Subsystem Vendor ID Default 0000h This field should be programmed during boot up After this field is written once it becomes read only 3 5 12 SID Subsystem Identification Device 0 Offset 2E 2Fh Default 0000h Access R WO Size 16 bits This value is used to identify a particular subsystem Subsystem ID Default 0000h This field should be programmed during boot up After this field is written once it becomes read only 3 5 13 CAPPTR Capabilities Pointer Device 0 Offset 34h Default E4h Access RO Size 8 bits The CAPPTR provides the offset that is the pointer to the location where the AGP standard registers are located __________ _________ AGP Standard Register Block Pointer Address This address pointer indicates to software where it can find the beginning of the AGP register block E4h AGP register block beginning address Inte 82845 for SDR Datasheet 51 Register Description 3 5 14 3 5 15 52 intel AGPM AGP Miscellaneous Configuration Register Device 0 Address Offset 51h Default Value 00h Access R W Size 8 bits e o EE Aperture Access Global Enable APEN This bit is used to prevent access to the g
106. on DRAM memory space occurred SERR on Hub Interface Target Abort TAHLA 0 Software must write a 1 to clear this status bit 1 MCH detected that a MCH originated hub interface cycle was terminated with a Target Abort completion packet or special cycle MCH Detects Unimplemented Hub Interface Special Cycle HIAUSC 0 Software must write a 1 to clear this status bit 1 MCH detected an Unimplemented Special Cycle on the hub interface Invalid AGP Access Flag IAAF 0 Software must write 1 to clear this status bit 1 Indicates that an AGP access was attempted outside of the graphics aperture and either to the 640 KB 1 MB range or above the top of memory Invalid Graphics Aperture Translation Table Entry ITTEF 0 Software must write a 1 to clear this status bit 1 Indicates that an invalid translation table entry was returned in response to an AGP access to the graphics aperture Multiple bit DRAM ECC Error Flag 0 After software completes the error processing a value of 1 is written to this bit field to set the value back to 0 and unlock the error logging mechanism 1 A memory read data transfer had an uncorrectable multiple bit error When this bit is set the address and device number that caused the error are logged in the EAP Register Software uses bits 1 0 to detect whether the logged error address is for Single or Multiple bit error 4 AGP Access Outside of Graphics Aperture Flag OOGF
107. on the AGP bus Configuration Read and Write Host configuration cycles to AGP are forwarded as Type 1 configuration cycles Fast Back to Back Transactions The as an initiator does not perform fast back to back cycles Inte 82845 for SDR Datasheet 5 4 5 4 1 Functional Description MCH Retry Disconnect Conditions The MCH generates retry disconnect according to the AGP Interface Specification Revision 2 0 rules when being accessed as a target from the AGP FRAME device Delayed Transaction When an AGP FRAME to system memory read cycle is retried by it is processed internally as a delayed transaction The MCH supports the delayed transaction mechanism on the target interface for the transactions issued using AGP FRAME protocol This mechanism is compatible with the PCI Local Bus Specification Revision 2 1 process of latching all information required to complete the transaction terminating with Retry and completing the request without holding the master in wait states is called a delayed transaction The MCH latches the address and command when establishing a delayed transaction The MCH generates a delayed transaction on the only for to system memory read accesses The MCH does not allow more than one delayed transaction access from AGP at any time Power and Thermal Management An 845 chipset platform is compliant with the following specificati
108. ons APM Revision 1 2 ACPI Revision 1 0b PCI Power Management Revision 1 0 e PC 99 Revision 1 0 e PC 99A PC 01 Revision 1 0 Processor Power State Control CO Full On This is the only state that runs software clocks are running STPCLK is deasserted and the processor core is active The processor can service snoops and maintain cache coherency in this state Stop Grant State This function can be enabled or disabled via a configuration bit When this function is enabled STPCLK is asserted to place the processor into the C2 state with a programmable duty cycle This is an ACPI defined function but BIOS or APM via BIOS can use this facility Inte 82845 for SDR Datasheet 117 Functional Description 5 4 2 5 5 5 6 118 intel Sleep State Control 50 Awake In this state all power planes are active All of the ACPI software states are embedded in this state S1 The recommended implementation of S1 state is the same as C2 state Stop Grant which is entered by the assertion of the STPCLK signal from the ICH2 to the processor A further power saving can be achieved by asserting processor SLP from the ICH2 This puts the processor into Sleep State 52 ACPI 52 state is not supported in the 845 chipset desktop platform S3 Suspend To RAM STR The next level of power reduction occurs when the clock synthesizers and main power planes ICH2 MCH and the processor are shut do
109. ontroller will reside and PMBASE land Registers are used to map prefetchable address ranges typically graphics local memory This segregation allows application of USWC space attributes to be performed in a true plug and play manner to the prefetchable address range for improved host AGP memory access performance Inte 82845 for SDR Datasheet Register Description 3 6 19 PMBASE1 Prefetchable Memory Base Address Register Device 1 Address Offset 24 25 Default Value FFFOh Access R W Size 16 bits This register controls the host to AGP prefetchable memory accesses routing based on the following formula PREFETCHABLE_MEMORY_BASE1 lt address lt PREFETCHABLE_MEMORY_LIMIT1 The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return 0s when read The configuration software must initialize this register For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary ee 15 4 Prefetchable Memory Address Base 1 PMEM_BASE1 Corresponds to A 31 20 of the memory address 3 6 20 PMLIMIT1 Prefetchable Memory Limit Address Register Device 1 Address Offset 26 27h Default Value 0000h Access R W Size 16 bits This register controls the host to AGP prefetchable memo
110. or SDR Datasheet 61 Register Description 3 5 22 62 intel This 64 KB area is divided into four 16 KB segments that can be assigned with different attributes via PAM control register as defined by the table above Extended System BIOS Area E0000h EFFFFh System BIOS Area F0000h FFFFFh This area is a single 64 KB segment which can be assigned with different attributes via PAM control register as defined by the table above FDHC Fixed DRAM Hole Control Register Device 0 Address Offset 97h Default Value 00h Access R W Size 8 bits This 8 bit register controls a fixed DRAM hole 15 16 MB Hole Enable HEN This bit enables memory hole in DRAM space Host cycles matching enabled hole are passed on to the ICH2 through the hub interface The hub interface cycles matching an enabled hole will be ignored by the MCH Note that a selected hole is not re mapped 0 Disabled No hole 1 15 16 1 hole Reserved Inte 82845 for SDR Datasheet 3 5 23 Register Description SMRAM System Management RAM Control Register Device 0 Address Offset 9Dh Default Value 02h Access R W RO R W L Size 8 bits The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated The Open Close and Lock bits function only when the G_LSMRAME bit is set to a 1 Also the OPEN bit must be reset before the LOCK bit is set KS
111. or flag is cleared by software If the first error was a single bit correctable error then a subsequent multiple bit error will overwrite this field In all other cases an error that occurs after the first error and before the error flag has been cleared by software will escape recording EAP Error Address Pointer Register Device 0 Address Offset 8C 8Fh Default Value 0000 0000h Access RO Size 32 bits This register contains the address of the 32 byte aligned data unit on which system memory ECC error s was detected Bemplm 29 1 Error Address Pointer EAP This field is used to store address bits A 33 5 of the 32 byte aligned data unit of system memory of which an error single bit or multi bit error has occurred Note The value of this bit field represents the address of the first single or the first multiple bit error occurrence after the error flag bits in the ERRSTS register have been cleared by software A multiple bit error will overwrite a single bit error Once the error flag bits are set as a result of an error this bit field is locked and does not change as a result of a new error until the error flag is cleared by software EM Reserved Inte 82845 SDR Datasheet intel 3 5 21 Register Description PAM 0 6 Programmable Attribute Map Registers Device 0 Address Offset 90 96h Default Value 00h Attribute R W RO Size 8 bits The MCH allows
112. ost clocks 16 Write Thermal Management Monitoring Window WTMMW The value in this register is padded with four Os to specify a window of 0 2047 host clocks with a 16 clock granularity While the thermal management mechanism is invoked system memory writes are monitored during this window If the number of hexwords written during the window reaches the Write Thermal Management Hexword Maximum bits 14 3 then write requests are blocked for the remainder of the window Write Thermal Management Hexword Maximum WTMHM The Write Thermal Management Hexword Maximum defines the maximum number of hexwords between 0 4095 that are permitted to be written to system memory within one Write Thermal Management Monitoring Window Write Thermal Management Mode WTMMode 00 Thermal management via Counters and Hardware Thermal Management_on signal mechanisms disabled 01 Hardware Thermal Management_on signal mechanism is enabled In this mode as long as the Thermal Management_on signal is asserted write thermal management is in effect based on the settings in WTMW WTHM When the Thermal Management_on signal is deasserted write thermal management stops and the counters associated with the WTMW WTHM are reset When the hardware Thermal Management on signal mechanism is not enabled the Thermal Management on signal has no effects 10 Counter mechanism controlled through GDWSW and GWHT is enabled When the threshold set in GDWSW and
113. p DBIO HD 15 0 DRDY Data Ready Asserted for each cycle that data is transferred AGTL HA 31 3 Host Address Bus 31 3 connect to the system address bus During AGTL processor cycles HA 31 3 are inputs The MCH drives HA 31 3 during snoop cycles on behalf of the hub interface and AGP Secondary initiators HA 31 3 are transferred at 2x rate Note that the address is inverted on the system bus HADSTB 1 0 Host Address Strobe The source synchronous strobes used to transfer AGTL HA 31 3 HREQ 4 0 at the 2x transfer rate Strobe Address Bits HADSTBO HA 16 3 HREQ 4 0 HADSTB1 HA 31 17 Inte 82845 for SDR Datasheet 21 Signal Description HD 63 0 Host Data These signals are connected to the system data bus AGTL HD 63 0 are transferred at a 4x rate Note that the data signals are inverted on the system bus HDSTBP 3 0 Differential Host Data Strobes differential source synchronous AGTL strobes used to transfer HD 63 0 and DBI 3 0 at the 4x transfer rate 0 63 0 3 0 Data Bits HDSTBP3 HDSTBN3 HD 63 48 DBI3 HDSTBP2 HDSTBN2 47 32 DBI2 HD HDSTBP1 HDSTBN1 HD 31 16 DBI1 Strobe HDSTBPO HDSTBNO 15 0 DBIO HIT y o Hit This signal indicates that a caching agent holds an unmodified version AGTL of the requested line HIT is also driven in conjunction with HITM by the targ
114. pendent of the 1 address and memory address ranges defined by the previously defined base and limit registers Forwarding of these accesses is also independent of the settings of bit 2 ISA Enable of this register if this bit is 1 Refer to Chapter further information ISA Enable ISA_EN R W Modifies the response by the MCH to an I O access issued by the host that targets ISA I O addresses This applies only to I O addresses that are enabled by the IOBASE and IOLIMIT registers 0 Disable All addresses defined by the IOBASE and IOLIMIT Registers for host I O transactions are mapped to AGP Default 1 Enable MCH does not forward to AGP any I O transactions addressing the last 768 bytes each 1 KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers Instead of going to AGP these cycles are forwarded to PCIO where they can be subtractively or positively claimed by the ISA bridge Inte 82845 for SDR Datasheet Register Description Parity Error Response Enable PER_EN R W Controls MCH s response to data phase parity errors on AGP 0 Address and data parity errors on AGP are not reported via the MCH hub interface SERR messaging mechanism Other types of error conditions can still be signaled via SERR messaging independent of this bit s state 1 The G_PERR signal is not implemented by the However when this bit is set to 1 address and data pari
115. ping el OOOO O Fast Back to Back Enable 2 Hardwired to 0 Since there is only target allowed this bit is meaningless The will not generate FB2B cycles 1x mode but will generate FB2B cycles in 2x and 4x Fast Write modes Secondary Bus Reset SRESET RO Hardwired to 0 does not support generation of reset via this bit on the AGP Note The only way to perform a hard reset of the AGP is via the system reset either initiated by software or hardware via the ICH2 Master Abort Mode MAMODE RO Hardwired to 0 This means that when acting as a master on AGP and a Master Abort occurs the MCH will discard data on writes and return all 1s during 3 VGA Enable VGA EN1 R W This bit controls the routing of host initiated transactions targeting compatible and memory address ranges 0 VGA compatible memory and I O range accesses not forwarded to AGP Default Rather they are mapped to primary PCI unless they are mapped to via and memory range registers defined above IOBASE1 IOLIMIT1 MBASE1 MLIMIT1 PMBASE1 PMLIMIT1 1 MCH forwards the following host accesses to the AGP Memory accesses in the range 0A0000h to OBFFFFh addresses where 9 0 are in the ranges 3BOh to 3BBh and 3COh to 3DFh inclusive of ISA address aliases A 15 10 are not decoded When this bit is set forwarding of these accesses issued by the host is inde
116. ported external buffering and memory array layout The most important contribution to overall performance by the system memory controller is to minimize the latency required to initiate and complete requests to memory and to support the highest possible bandwidth full streaming quick turn arounds One measure of performance is the total flight time to complete a cache line request A complete discussion of performance involves the entire chipset not just the system memory controller Data Integrity ECC The MCH supports single bit Error Correcting Code or Error Checking and Correcting and multiple bit EC Error Checking on the system memory interface The MCH generates an 8 bit code word for each 64 bit QWord of memory The MCH performs two QWord writes at a time thus two 8 bit codes are sent with each write Since the code word covers a full QWord writes of less than a QWord require a read merge write operation Consider a DWord write to memory In this case when in ECC mode the MCH reads the QWord where the addressed DWord will be written merges in the new DWord generates a code covering the new QWord and finally writes the entire QWord and code back to memory Any correctable single bit errors detected during the initial QWord read are corrected before merging the new DWord The MCH also supports EC Error Checking data integrity mode In this mode the MCH generates and stores a code for each QWord of memory It then checks t
117. put 2 4 ow m Table 28 XOR Chain 5 Chain 5 Ball Signal KACELI Initial Logic Level GOBEO _ input wm s 144 82845 SDR Datasheet GTRDY TRDY RU n NN o estore 1 Inte 82845 for SDR Datasheet Testability 145 Testability Table 29 XOR Chain 6 E ILE RE LI AD AD_STB1 ME Foe oem m 3 s wm m 3 _ oes s m os s reser m 3 146 Inte 82845 for SDR Datasheet Chain 6 Ball manum Signal Name ELI Initial Logic Level Table 30 XOR Chain 7 LCS E IL 29 input oe Lom o ome s Wm poem De 03 pase 7 me 1 ow s wm m 0 s ww 1 Inte 82845 for SDR Datasheet Testability 147 Testability 3 Input 2 a e 148 Inte 82845 SDR Datasheet
118. r to obtain the latest specifications and before placing your product order is a two wire communications bus protocol developed by Philips SMBus is a subset of the bus protocol and was developed by Intel Implementations of the bus protocol may require licenses from various entities including Philips Electronics and North American Philips Corporation Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation www intel com or call 1 800 548 4725 Intel Pentium and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2001 2002 Intel Corporation 2 Inte 82845 SDR Datasheet reng ontrol Register Inte 82845 for SDR Datasheet 3 ication Register a SSS a e de Register Device Master Latency Timer Register Device y Reg ribute Registers Device 295 De VIRAMC Extended System Mgmt R Toe Register Device 0 AUR OMMANA 82845 SDR Datasheet tmi 00 655 Register D
119. r used for the particular signal AGTL Open Drain interface signal Refer to the AGTL I O Specification for complete details The MCH integrates most AGTL termination resistors AGP AGP interface signals These signals are compatible with AGP 2 0 1 5 V Signaling Environment DC and AC Specifications The buffers are not 3 3 V tolerant HI CMOS Interface 1 8 CMOS buffers SM CMOS System memory 3 3 CMOS buffers Table 20 Signal Groups Signal Signal Type Group AGTL I O ADS BNR BRO DBSY DBI 3 0 DRDY HA 31 3 0 s 63 0 HDSTBP 3 0 HDSTBN 3 0 HIT HITM AGTL Output CPURST DEFER HTRDY RS 2 0 Input HLOCK d Host Reference HVREF HSWING 1 0 Voltages e AGP I O AD STBO AD_STBO AD STB1 AD_STB1 G FRAMEZ G_IRDY G_STOP DEVSEL G_AD 81 0 G_C BE 3 0 PIPE SBA 7 0 RBF WBF SB STB SB_STB G_REQ AGP Output ST 2 0 G_GNT h AGP Reference AGPREF Voltage i Hub Interface s HI 10 0 HI STB HI_STB CMOS I O Hub Interface Reference Voltage SDRAMCMOS SDQ 63 0 SCB 7 0 SDRAM CMOS SCS 11 0 f SMA 12 0 SBS 1 0 SRAS SCAS SWE Output SCKE 5 0 SCK 11 0 RDCLKO n SDRAM Reference SDREF Voltage CMOS Input TESTIN CMOS Input RSTIN 3 3V r AGTL Termination VTT Voltage 120 Inte 82845 SDR Da
120. rameters are listed in the DC tables Warning Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operating beyond the operating conditions is not recommended and extended exposure beyond operating conditions may affect reliability Table 18 Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes Tstorage Storage Temperature 55 150 VCC1 5 1 5 Supply Voltage with respect to VSS 0 72 2 3 V VCC1 8 1 8 V Supply Voltage with respect to 55 0 88 2 69 V VCCSM 3 3 V Supply Voltage with respect to 55 2 83 6 3 V VTT AGTL buffer DC input voltage with respect 0 55 2 3 V to VSS 6 2 Power Characteristics Table 19 Power Characteristics Symbol Parameter Min Typ Max Unit Notes lvrr MCH VTT supply current 2 4 lvcc1 5 1 5 core supply current 1 5 A 1 lvcci 5 1 5 0 37 1 lvcci 1 8 hub interface supply current 0 20 A lvccsM 3 3 V system memory supply current 2 0 A Isus 33 3 3 V standby supply current 25 mA HVREF AGPREF REF SDREF 10 mA supply current NOTES 1 These current levels can happen simultaneously and can be summed into one supply Inte 82845 for SDR Datasheet 119 Electrical Characteristics intel 6 3 Signal Groups The signal description includes the type of buffe
121. range defined by the APBASE and APSIZE registers of the MCH device 0 The APBASE register follows the standard base address register template as defined by the PCI Local Bus Specification Revision 2 1 The size of the range claimed by the APBASE is programmed via back end register APSIZE programmed by the chipset specific BIOS before plug and play session is performed APSIZE allows the BIOS software to pre configure the aperture size to be 4 MB 8 MB 16 MB 32 MB 64 MB 128 MB or 256 MB By programming APSIZE to a specific size the corresponding lower bits of APBASE are forced to 0 behave as hardwired The default value of APSIZE forces an aperture size of 256 MB The aperture address range is naturally aligned Accesses within the aperture range are forwarded to the system memory subsystem The MCH translates the originally issued addresses via a translation table maintained in system memory The aperture range should be programmed as non cacheable in the processor caches Plug and play software configuration model does not allow overlap of different address ranges Therefore the AGP Graphics Aperture and AGP memory address range are independent address ranges that may abut but cannot overlap one another System Management Mode SMM Memory Range The MCH supports the use of system memory as System Management RAM SMRAM enabling the use of System Management Mode The MCH supports three SMRAM options Compatible SMRAM C_SMRAM High
122. rant TESTIN Test Input This is used for manufacturing and board level test CMOS purposes Note This signal has an internal pull up resistor 28 Inte 82845 for SDR Datasheet Signal Description 2 6 Voltage Reference and Power Signals Ref Host Reference Voltage Reference voltage input for the data address and common clock signals of the host AGTL interface Ref Signal Name HVREF SDREF SDRAM Reference Voltage Reference voltage input for DQ DQS RDCLKIN SDR Hub Interface Reference Reference voltage input for the hub interface AGP Reference Reference voltage input for the AGP interface Compensation for Hub Interface This signal is used to calibrate the CMOS hub interface buffers It is connected to 40 2 Q pull up resistor with 1 tolerance and is pulled up to VCC1 8 REF Ref AGPREF Ref HLRCOMP GRCOMP Compensation for AGP This signal is used to calibrate buffers It is CMOS connected to a 40 2 O pull down resistor with a 196 tolerance 0 Compensation for Host These signals used to calibrate the host CMOS AGTL I O buffers Each signal is connected to 24 9 Q pull down resistor with a 1 tolerance Host Reference Voltage Reference voltage input for the compensation CMOS logic HSWNG 1 0 SMRCOMP System Memory CMOS 1 5 V Power Input These pins are connected to a 1 5 V power source VCC1 5 VCC1 8
123. raphics aperture from any port processor hub interface or AGP PCI B before the aperture range is established by the configuration software and the appropriate translation table in system memory has been initialized The default value is 0 thus this field must be set after system is fully configured to enable aperture accesses DRB 0 7 DRAM Row Boundary Registers Device 0 Offset 60 67 DRBO DRB7 Default 00h Access R W Size 8 bits The DRAM Row Boundary Register defines the upper boundary address of each pair of DRAM rows with a granularity of 32 MB Each row has its own single byte DRB register For example a value of 1 in DRBO indicates that 32 MB of DRAM has been populated in the first row Row 0 60h Row 1 61h Row 2 62h Row 3 63h Row 4 64h Row 5 65h See Note 1 Row 6 66h See Note 2 Row 7 67h See Note 2 DRBO Total memory in in 32 MB increments Total memory in in 32 MB increments Notes 1 DRB5 Total memory in row0 row2 row3 row5 in 32 MB increments 2 DRB 7 6 must be programmed with the value contained in DBR5 Each Row is represented by a byte Each byte has the following format ee DRAM Row Boundary Address This 8 bit value defines the upper and lower addresses for each DRAM row This 8 bit value is compared against a set of address lines to determine the upper address limit of a particular row
124. rate a Type 1 hub interface configuration cycle The ICH2 compares the non zero Bus Number with the Secondary Bus Number and Subordinate Bus Number registers of its P2P bridges to determine if the configuration cycle is meant for Primary PCI or a downstream PCI bus Primary PCI and Downstream Configuration Mechanism AGP Configuration Mechanism From the chip set configuration perspective AGP is seen as a PCI bus interface residing on a Secondary Bus side of the virtual PCI PCI bridges referred to as Host AGP bridge On the Primary Bus side the virtual PCI PCI bridge is attached to PCI Bus 0 Therefore the Primary Bus Number register is hardwired to 0 The virtual PCI PCI bridge entity converts Type 1 PCI bus configuration cycles on PCI Bus 0 into Type 0 or Type 1 configuration cycles on the AGP interface Type 1 configuration cycles on PCI Bus 0 that have a Bus Number that matches the Secondary Bus Number of the MCH s virtual Host to PCI B AGP bridge will be translated into Type 0 configuration cycles on the AGP interface If the Bus Number is non zero greater than the value programmed into the Secondary Bus Number Register and less than or equal to the value programmed into the Subordinate Bus Number Register the MCH will generate a Type 1 PCI configuration cycle on AGP Mapped Registers The MCH contains two registers that reside in the processor I O address space the Configuration Address CONF ADDR
125. rated LAN controller System Management Bus SMBus compatible with most devices ICH2 has both bus master and slave capability 97 2 1 compliant link for audio and telephony codecs up to 6 channels ICH2 Low Pin Count LPC interface FWH Interface FWH Flash BIOS support Alert on LAN AOL AOL2 Intel 82845 MCH Overview The MCH role in a system is to manage the flow of information between its four interfaces the system bus the memory interface the AGP port and the hub interface The MCH arbitrates between the four interfaces when each initiates an operation While doing so the MCH supports data coherency via snooping and performs address translation for access to AGP Aperture memory To increase system performance the MCH incorporates several queues and a write cache The MCH is in a 593 pin FC BGA package and contains the following functionality e Supports single Pentium 4 processor configuration at 400 MHz e AGTL system bus with integrated termination supporting 32 bit system bus addressing Up to 3 512 Mb technology of PC133 SDRAM 1 5 AGP interface with 4x SBA data transfer and 2x 4x fast write capability 8 bit 66 MHz hub interface to the ICH2 e Distributed arbitration for highly concurrent operation Inte 82845 for SDR Datasheet 1 4 2 Introduction System Bus Interface The MCH is optimized for the Pentium 4 processor The primary en
126. ration Register Device 0 Offset 10 13h Default 0000 0008h Access R W RO Size 32 bits The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics Aperture The standard PCI Configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested dependent on which bits are hardwired to 0 or behave as hardwired to 0 To allow for flexibility of the aperture an additional register called APSIZE is used as a back end register to control which bits of the APBASE will behave as hardwired to 0 This register will be programmed by the MCH specific BIOS code that runs before any of the generic configuration software is run Bit 9 of the MCHCFG register is used to prevent accesses to the aperture range before this register is initialized by the configuration software and the appropriate translation table structure has been established in the system memory ______ __ Upper Programmable Address R W These bits are part of the aperture base set by configuration software to locate the base address of the graphics aperture They correspond to bits 31 28 of the base address in the processor s address space that will cause a graphics aperture translation to be inserted into the path of any memory read or write Default 0000 Middle Hardwired Programmable Base Address R W These bits are part of the aperture base set
127. rea below 1 MB The final range is a DOS legacy space which is used for BIOS and legacy devices on the LPC interface Figure 3 Addressable Memory Space 16 GB Additional System Memory Address Range x 4 PCI Memory Address Hub Interface AGP Graphics APICs Range Aperture Aperture Top of Low Y MM M System Memory Address Range 1MB Independently Programmable DOS Legacy Address Non overlapping Windows Range sys map 1 These address ranges are always mapped to system memory regardless of the system configuration Memory may be taken out of the system memory segment for use by System Management Mode SMM hardware and software The Top of Low Memory TOM register defines the top of system memory Note that the address of the highest 16 MB quantity of valid memory in the system is placed into the GBA15 register For memory populations lt 3 GB this value will be the same as the one programmed into the TOM register For other memory configurations the two are unlikely to be the same since the PCI configuration portion of the BIOS software will program the TOM register to the maximum value that is less than the amount of memory in the system and that allows enough room for all populated PCI devices Inte 82845 for SDR Datasheet 97 System Address Figure
128. ream interrupts to the system bus Power Management SMRAM space remapping to A0000h Supports extended SMRAM space above 256 MB additional TSEG from Top of Memory SMRAM accesses from or hub interface are not supported PC 799 suspend to DRAM support ACPI Revision 1 0b compliant power management APM Revision 1 2 compliant power management Hardware Design Guide Version 1 0 compliant Package MCH 593 pin FC BGA 37 5 x 37 5 mm System Block Diagram Intel Pentium 4 Processor Intel 845 Chipset System Memory Intel 82845 SDRAM 4x AGP H Memory Interface i AGP 2 B Graphics 20 y Controller Hub 7 SDRAM Controller Hub Interface v 2 IDE Drives UltraATA 100 227 y 51015 3 eoo Bus 4 USB Ports 2 O Intel 82801 Agent 97 2 1 2 Controller Hub E ICH2 Keyboard Super I O Mouse FD PP SP IR LAN Connect GPIO FWH Flash BIOS sys_blk Inte 82845 for SDR Datasheet 1 1 1 Introduction Introduction The Intel 82845 Memory Controller Hub MCH is designed for use with the Intel Pentium 4 processor in the 478 pin package The Intel 845 chipset contains two main compo
129. response Reserved not driven by MCH Hard Failure not driven by MCH No data response Implicit Write back Normal data response Inte 82845 for SDR Datasheet Signal Description 2 2 SDR SDRAM Interface Signals SCS 11 0 4 Chip Select These signals select the particular SDRAM components CMOS during the active state Note There are two SCS signals per SDRAM row These signals can be toggled on every rising system memory clock edge SMA 12 0 Multiplexed Memory Address These signals used to provide the CMOS multiplexed row and column address to SDRAM SBS 1 0 Memory Bank Select SBS 1 0 define the banks that are selected within CMOS each SDRAM row The SMA and SBS signals combine to address every possible location ina SDRAM device SRAS SDRAM Row Address Strobe SRAS is Used with SCAS SWE CMOS along with SCS to define the DRAM commands SCAS SDRAM Column Address Strobe SCAS is used with SRAS CMOS SWE along with SCS to define the SDRAM commands SWE Write Enable SWE is used with SCAS SRAS along with SCS CMOS to define the SDRAM commands SDQ 63 0 Data Lines These signals are used to interface to the SDRAM data bus CMOS SCB 7 0 Check Data Lines These signals are used to interface to the CMOS SDRAM ECC signals SCKE 5 0 Clock Enable These pins used to signal self refresh or CMOS Powerdown command to a SDRAM
130. rite only BIOS is shadowed by first performing a read of that address This read is forwarded to the expansion bus The host then does a write of the same address which is directed to system memory After the BIOS is shadowed the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus rable 9Jand Figure 2hhow the PAM registers and the associated attribute bits Figure 2 PAM Register Attributes Offset PAM6 96h PAM5 95h PAM4 94h PAM3 93h PAM2 92h PAM1 91h PAMO 90h 7 6 5 4 3 2 1 AT Reserved Read Enable R W Reserved 1 Enable Write Enable R W 0 Disable 1 Enable Write Enable R W 0 Disable 1 Enable Read Enable R W 0 Disable 1 Enable Reserved 0 Disable Reserved pam Inte 82845 for SDR Datasheet Register Description R we RE oFoooon orFFFFh BIOS Area 9 30 we RE oCo000h 0C3FFFh ISA Add on BIOS PAMT4 R WE RE ISA Add on BIOS R WE RE 0CB000h OCBFFFh ISA Add on BIOS PAM2 7 4 a 8 we OCCOO0h OCFFFFh ISA Add on BIOS PAM3 3 0 R oR we 0D0000h 0D3FFFh ISA Add on BIOS PAM3 7 4 a 8 we 0D4000h 0D7FFFh ISA Add on BIOS 3 0 FR OD8000h ODBFFFh ISA Add on BIOS PAM474 R WE RE oDCooon oDFFFFh ISA Add on BIOS PAMS 3 0 R oR we
131. rocessor DBI Dynamic Bus inversion MSI Message Signaled Interrupts MSIs allow a device to request interrupt service via standard memory write transaction instead of through a hardware signal IPI Inter Processor Interrupt SDR Single Data Rate SDRAM memory Table 2 Data Type Notation Data Type bit b byte word DWord DW QWord QW DQWord DOW Kilobyte KB Megabit Mb Megabyte MB Gigabit Gb Gigabyte GB Quadword 8 bytes 4 words Double Quadword 16 bytes or 8 words This is sometimes referred to as a Superword SW or SWord and is also referred to as a Cache Line 1 048 576 bytes 1024 KB Table 3 Number Format Notation 12 Number Format Notation 11100 82845 SDR Datasheet Introduction 1 2 Reference Documents Document Document Number Location Inte Pentium 4 Processor in a 478 Pin Package and Intel 845 Chipset Platform for 298354 SDR Design Guide Inte 82801BA I O Controller Hub ICH2 and Intel 82801BAM I O Controller Hub 290687 ICH2 M Datasheet Inte 845 Chipset Thermal and Mechanical Design Guidelines for SDR 298586 Inte 82802AB AC Firmware Hub FWH Datasheet 290658 PCI Local Bus Specification Revision 2 1 Contact Intel Field Representative Accelerated Graphics Port Interface Specification Revision 2 0 w agpforum org Inte Pentium 4 Processor Datasheet PC SDRAM Specification
132. rror Inte 82845 for SDR Datasheet Register Description 3 5 39 SKPD Scratchpad Data Register Device 0 Address Offset DE DFh Default Value 0000h Access R W Size 16 bits Description 15 0 Scratchpad 15 0 These bits are R W storage bits that have no effect on the MCH functionality 3 5 40 CAPID Product Specific Capability Identifier Register Device 0 Address Offset E4h Default Value 0104A009h Access RO Size 32 bits EN 31 System Memory Capability 0 Component only supports SDR SDRAM memory DRAM Type field is read only default 1 Reserved Mobile Power Management Capability 0 Component is NOT capable of all mobile power management features and is limited to desktop use only default 1 Component is capable of all mobile power management features 27 24 CAPID Version 0001b First revision of the CAPID register definition default CAPID Length 04h Indicates a structure length of 4 bytes default Next Capability Pointer AOh Points to the next Capability in this device ACAPID register default 10016 Identifies the CAP ID assigned by the PCI SIG for vendor dependent capability pointers default Inte 82845 for SDR Datasheet 79 Register Description intel 3 6 Bridge Registers Device 1 rabie 10 provides the register address map for Device 0 PCI configuration space An s in the Default Value column indicates that a strap determi
133. ry accesses routing based on the following formula PREFETCHABLE_MEMORY_BASE1 lt address lt PREFETCHABLE_MEMORY_LIMIT1 The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only return 05 when read The configuration software must initialize this register For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block 15 4 Prefetchable Memory Address Limit 1 PMEM LIMIT1 Corresponds to A 31 20 of the memory address Default 00h Note Prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC prefetchable from the processor perspective Inte 82845 for SDR Datasheet 91 Register Description 3 6 21 92 BCTRL1 PCI PCI Bridge Control Register Device 1 Address Offset Default 00h Access RO RW Size 8 bits This register provides extensions to the PCICMDI register that are specific to PCI PCI bridges BCTRLI provides additional control for the secondary interface i e AGP as well as some bits that affect the overall behavior of the virtual PCI PCI bridge embedded in e g VGA compatible address ranges map
134. s attribute can be written to only once after power up After the first write the bit becomes read only Lock A register bit with this attribute becomes Read Only after a lock bit is set Reserved Bits Some of the MCH registers described in this section contain reserved bits These bits are labeled Reserved Software must deal correctly with fields that are reserved On reads software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value On writes software must ensure that the values of reserved bit positions are preserved That is the values of reserved bit positions must first be read merged with the new values for other bit positions and then written back Note that software does not need to perform a read merge write operation for the Configuration Address CONF ADDR register Inte 82845 for SDR Datasheet 31 Register Description 3 2 Reserved In addition to reserved bits within a register the MCH contains address locations in the Registers configuration space that are marked Reserved When a Reserved register location is read a random value is returned Reserved registers can be 8 16 or 32 bit in size Registers that are marked as Reserved must not be modified by system software Writes to Reserved registers may cause system failure Default Value Upon a Full Reset the MCH sets all of its internal configuration registers to
135. s phase for a read cycle PAR is driven by the MCH when it acts as a FRAME based AGP target during each data phase of a FRAME based AGP memory read cycle Even parity is generated across AD 31 0 and G_C BE 3 0 During SBA and PIPE Operation This signal is not used during SBA and PIPE operation NOTE PCIRST from the ICH2 is connected to RSTIN and is used to reset AGP interface logic within the MCH The AGP agent will also use PCIRST provided by the ICH2 as an input to reset its internal logic Inte 82845 for SDR Datasheet 27 Signal Description 2 5 Clocks Reset and Miscellaneous Signals BCLK Differential Host Clock In These pins receive a differential host clock BCLK CMOS from the external clock synthesizer This clock is used by all of the MCH logic that is in the host clock domain 66IN 66 MHz Clock In This receives 66 MHz clock from the clock CMOS synthesizer This clock is used by AGP PCI and hub interface clock domains Note That this clock input is 3 3 V tolerant SCK 11 0 System Memory Clocks SDR These signals deliver synchronized CMOS clock to the DIMMs There are two per row RSTIN Reset When asserted this signal asynchronously resets the CMOS logic RSTIN is connected to the PCIRST output of the ICH2 All AGP PCI output and bi directional signals will also three state compliant to PCI Rev 2 0 and 2 1 specifications Note This input needs to be 3 3 V tole
136. ss as the target of the current access The AGP asserts G_DEVSEL based on the DRAM address range being accessed by a PCI initiator As an input it indicates whether any device on the bus has been selected Request Indicates that FRAME PIPE based AGP master is AGP requesting use of the AGP interface This signal is an input into the MCH G_GNT Grant During SBA PIPE FRAME operation G_GNT along with AGP the information on the ST 2 0 signals status bus indicates how the AGP interface will be used next AD 31 0 Address Data Bus These signals are used to transfer both address and AGP data on the AGP interface G_C BE 3 0 Command Byte Enable AGP During FRAME Operation During the address phase of a transaction G_C BE 3 0 define the bus command During the data phase G_C BE 3 0 are used as byte enables The byte enables determine which byte lanes carry meaningful data During PIPE Operation When an address is enqueued using PIPE the G_C BE signals carry command information The command encoding used during PIPE based AGP is DIFFERENT than the command encoding used during FRAME based AGP cycles or standard PCI cycles a PCI bus G PAR m During Operations This signal is driven by the when it acts as a FRAME based AGP initiator during address and data phases for a write cycle and during the addres
137. stem Address 4 1 2 4 1 3 100 PAM Memory Spaces The address ranges in this memory space are 0_000C_0000 to 0_000C_3FFF 0_000C_4000 to 0_000C_7FFF PAMC8 0_000C_8000 to _000C_BFFF PAMCC 0_000C_C000 to 0_000C_FFFF PAMDO 0_000D_0000 to 0 000 3FFF PAMD4 0 000 4000 to 0 0000 7FFF PAMD8 0 000 8000 to 0 000 BFFF PAMDC 0 0000 C000 to 0 0000 FFFF 0 000 0000 to 0 000 3FFF PAMEA 0 000 4000 to 0 000 7FFF PAME8 0 000 8000 to 0 000 BFFF 0 000 C000 to 0 000 FFFF 0 000 0000 to 0 000 FFFF 256 KB region is divided into three parts SA expansion region 128 KB area between 0 000C 0000h 0 000D FFFFh Extended BIOS region 64 KB area between 0 000E 0000h 0 000E FFFFh System BIOS region 64 KB area between 0 000F 0000h 0 000F FFFFh The ISA expansion region is divided into eight 16 KB segments Each segment can be assigned one of four read write states read only write only read write or disabled Typically these blocks are mapped through MCH and are subtractively decoded to ISA space The extended system BIOS region is divided into four 16 KB segments Each segment can be assigned independent read and write attributes so it can be mapped either to main system memory or to the hub interface Typically this area is used for RAM or ROM The system BIOS region is a single 64 KB segment T
138. symmetric owner to stop issuing new transactions unless the HLOCK signal was asserted BRO y o Bus Request 0 The MCH pulls the processor bus BRO signal low AGTL during CPURST The signal is sampled by the processor on the active to inactive transition of CPURST The minimum setup time for this signal is 4 BCLKs The minimum hold time is 2 BCLKs and the maximum hold time is 20 BCLKs BRO should be three stated after the hold time requirement has been satisfied CPURST Processor Reset The CPURST pin is an output from the AGTL MCH asserts CPURST while RSTIN PCIRST from the ICH2 is asserted and for approximately 1 ms after RSTIN is deasserted The CPURST allows the processor to begin execution in a known state DBSY y o Data Bus Busy DBSY is used by the data bus owner to hold the data AGTL bus for transfers requiring more than one cycle DEFER Defer Response This signal when asserted indicates that the MCH will terminate the transaction currently being snooped with either a deferred response or with a retry response DBI 3 0 Dynamic Bus Inversion DBI 3 0 are driven along with the HD 63 0 AGTL signals DBI 3 0 Indicate if the associated data signals are inverted DBI 3 0 are asserted such that the number of data bits driven electrically low low voltage within the corresponding 16 bit group never exceeds 8 DBI x Data Bits DBI3 HD 63 48 DBI2 HD 47 32 DBI14 HD 31 16 am
139. t stop cycles occur based on the settings in RTT RTMW and RTHM 11 Reserved START Read Thermal Management SRTM Software writes to this bit to start and stop read thermal management 0 Read thermal management stops and the counters associated with RTMW and RTHM reset 1 Read thermal management begins based on the settings in RTMW and RTHM and remains to be in effect until this bit is reset to 0 Register Description 96 This page is intentionally left blank Inte 82845 for SDR Datasheet 4 4 1 tel System Address Map System Address Map A system based on the 845 chipset supports 4 GB of addressable memory space and 64 KB 3 of addressable I O space The I O and memory spaces are divided by system configuration software into regions The memory ranges are useful either as system memory or as specialized memory while the I O regions are used solely to control the operation of devices in the system When the MCH receives a write request whose address targets an invalid space the data is ignored For reads the MCH responds by returning all zeros on the requesting interface Memory Address Ranges The system memory map is broken into two categories e Extended Memory Range 1 MB to 4 GB The second is extended memory existing between 4GB It contains a 32 bit memory space which is used for mapping PCI AGP APIC SMRAM and BIOS memory spaces DOS Compatible A
140. tasheet Electrical Characteristics Signal Signal Type Group s 1 5 V Core and AGP VCC1 5 Voltage t 1 8 V Hub Interface VCC1 8 Voltage u 3 3 V PC133 VCCSM SDRAM Voltage CMOS Clock Input 66IN w CMOS Clock Input BCLK BCLK Inte 82845 for SDR Datasheet 121 Electrical Characteristics 6 4 DC Characteristics Table 21 DC Characteristics Symbol Signal Parameter Min Typ Max Unit Notes Group Buffer Supply Voltage VCCSM u PC133 SDRAM I O Voltage 3 135 3 3 3 465 VCC1 8 t 1 8V Supply Voltage 1 71 1 8 1 89 V VCC1 5 s Core and AGP Voltage 1 425 1 5 1 575 V VTT r Host AGTL Termination Voltage N A N A 1 75 V Reference Voltages HVREF d Host Address and Data Reference 2 3x 29 2 3xVTT 2 8XVTT 296 Voltage HSWING d Host Compensation Reference 1 8 x VTT 2 1 3x VTT 1 3XVTT 256 Voltage HI REF Hub Interface Reference Voltage 0 48 x VCC1 8 1 2x VCC1 8 0 52x VCC1 8 V SDREF n SDRAM Reference Voltage 0 49 x 5 1 2x VCCSM 0 51 x VCCSM V AGPREF h AGP Reference Voltage 0 48 x VCC1 5 1 2x VCC1 5 0 52x VCC1 5 V System Bus Interface Host AGTL Input Low Voltage 2 3 x VTT 0 1 V Host AGTL Input High Voltage 2 3 x VTT 0 1 V VoL a b Host AGTL Output Low Voltage 1 3 x VTT
141. te access is detected on the system bus and when ESMRAMC H_SMRAME allows access to high SMRAM space SMM memory accesses from any hub interface or AGP are specially terminated reads are provided with the value from address 0 while writes are ignored entirely Inte 82845 for SDR Datasheet 101 System Address 4 1 10 4 2 102 Note intel AGP Aperture Space Device 0 BAR Processors and AGP devices communicate through a special buffer called the graphics aperture APBASE to APBASE APSIZE This aperture acts as a window into main system memory and is defined by the APBASE and APSIZE configuration registers of the MCH Note that the AGP aperture must be above the top of memory and must not intersect with any other address space AGP Memory and Prefetchable Memory Plug and play software configures the AGP memory window to provide enough memory space for the devices behind this PCI to PCI bridge Accesses whose addresses fall within this window are decoded and forwarded to AGP for completion The address ranges are e MBASEI to MLIMIT1 PMI to PMLIMIT1 Note that these registers must be programmed with values that place the AGP memory space window between the value in the TOM register and 4 GB In addition neither region should overlap with any other fixed or relocatable area of memory Hub Interface Subtractive Decode accesses that fall between the value programmed into the TO
142. the given interface Powerdown Flow Since the MCH is powered down during STR the MCH cannot maintain any state information when exiting STR Thus the entire initialization process when exiting STR must be performed by the BIOS via accesses to the DRC2 register Entry into STR ACPI S3 is initiated by the Operating System OS based on detecting a lack of system activity The OS unloads all system device drivers as part of the process of entering STR The OS then writes to the PM1_CNT I O register in the ICH2 to trigger the transition into STR Inte 82845 for SDR Datasheet Signal Description Signal Description This chapter provides a detailed description of the MCH signals The signal descriptions are arranged in functional groups according to their associated interface see Figure 1 The states of all of the signals during reset are provided in the System Reset section The symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage level When is not present after the signal name the signal is asserted when at the high voltage level The following notations are used to describe the signal type I Input pin Output pin Bi directional Input Output pin s t s Sustained Three state This pin is driven to its inactive state prior to three stating as t s Active Sustained Three state This applies to some of the hub interfac
143. the graphics aperture and either to the 640 KB 1 MB range or above the top of memory SERR on Invalid Translation Table Entry ITTEF SERR 0 Disable 1 Enable Generation of the hub interface SERR message is enabled when an invalid translation table entry was returned in response to an AGP access to the graphics aperture SERR Multiple Bit DRAM ECC Error DMERR SERR 0 Disable For systems not supporting ECC this bit must be disabled 1 Enable Generation of the hub interface SERR message is enabled when the system memory controller detects a multiple bit error SERR on Single bit ECC Error DSERR 0 Disable For systems that do not support this bit must be disabled 1 Enable Generation of the hub interface SERR message is enabled when the system memory controller detects a single bit error Inte 82845 for SDR Datasheet 77 Register Description 3 5 37 Note 3 5 38 78 Note SMICMD SMI Command Register Device 0 Address Offset CC CDh Default Value 0000h Access R W Size 16 bits This register enables various errors to generate a SMI message via the hub interface An error can generate and only one error message via the hub interface It is software 5 responsibility to make sure that when an SMI error message is enabled for an error condition SERR and SCI error messages are disabled for that same error condition Deep SMI on Single bit EC
144. tial AGP designs may not use PIPE i e PCI only 66 MHz Therefore an 8 kQ pull up resistor connected to this pin is required on the motherboard SBA 7 0 Sideband Address These signals are used by the AGP master AGP graphics controller to place addresses into the AGP request queue The SBA bus and AD bus operate independently That is a transaction can proceed on the SBA bus and the AD bus simultaneously During PIPE Operation Not Used During FRAME Operation Not Used Note When sideband addressing is disabled these signals are isolated no external internal pull up resistors are required NOTE The above table contains two mechanisms to queue requests by the AGP master Note that the master can only use one mechanism The master may not switch methods without a full reset of the system When PIPE is used to queue addresses the master is not allowed to queue addresses using the SBA bus For example during configuration time if the master indicates that it can use either mechanism the configuration software will indicate which mechanism the master will use Once this choice has been made the master will continue to use the mechanism selected until the master is reset and reprogrammed to use the other mode This change of modes is not a dynamic mechanism but rather a static decision when the device is first being configured after reset 24 Inte 82845 for SDR Datasheet Signal Description 2 4 2
145. tion defines two mechanisms to access configuration space Mechanism 1 and Mechanism 12 The supports only Mechanism 1 The configuration access mechanism makes use of the CONF ADDR Register at I O address OCF8h though OCFBh and DATA register at I O address OCFCh though OCFFh To reference a configuration register a DWord I O write cycle is used to place a value into CONF that specifies the PCI bus the device on that bus the function within the device and a specific configuration register of the device function being accessed CONF ADDR 31 must be 1 to enable a configuration cycle CONF DATA then becomes a window into the four bytes of configuration space specified by the contents of CONF ADDR Any read or write to CONF DATA results in the MCH translating the CONF ADDR into the appropriate configuration cycle The MCH is responsible for translating and routing the processor s I O accesses to the CONF ADDR and CONF DATA registers to internal MCH configuration registers hub interface or AGP Routing Configuration Accesses The MCH supports two bus interfaces the hub interface and AGP PCI configuration cycles are selectively routed to one of these interfaces The MCH is responsible for routing PCI configuration cycles to the proper interface PCI configuration cycles to the ICH2 internal devices and Primary PCI including downstream devices are routed to the ICH2 via the hub interface AGP configuration cycles
146. translation table regardless of the originating interface System Bus Error Checking The MCH does not generate parity nor check parity for data address request and response signals on the processor bus Inte 82845 for SDR Datasheet 15 Introduction 1 4 3 intel System Memory Interface The MCH directly supports one channel of PC133 SDRAM The memory interface supports Single Data Rate SDR devices with densities of 64 Mb 128 Mb 256 Mb and 512 Mb technology The memory interface also supports variable page sizes of 2 KB 4 KB 8 KB and 16 KB Page size is individually selected for every row and a maximum of 8 pages per DIMM may be opened simultaneously The MCH supports a maximum of 3 double sided DIMMs 6 rows populated with unbuffered PC133 with or without ECC Note that in mixed mode populating ECC and Non ECC memories simultaneously is not supported Table 4 Memory Capacity 1 4 4 Technology 133 64 Mb 384 128 Mb 768 256 1 5 GB 512 Mb 3 GB The memory interface provides optional ECC error checking for system memory data integrity During system memory writes ECC is generated on a QWord 64 bit basis Because the MCH stores only entire cache lines in its internal buffers partial QWord writes initially cause a read of the underlying data and their write back into memory is no different from that of a complete cache line During system memor
147. ty errors detected on AGP are reported via hub interface SERR messaging mechanism if further enabled by SERRE1 3 6 22 ERRCMD1 Error Command Register Device 1 Address Offset 40h Default Value 00h Access R W Size 8 bits pee O 1 generates an SERR message over the hub interface when a target abort is received SERR on Receiving Target Abort SERTA 0 MCH does not assert an SERR message upon receipt of a target abort on AGP SERR messaging for Device 1 is globally enabled in the PCICMD1 register AGP Inte 82845 for SDR Datasheet 93 Register Description 3 6 23 94 DWTC DRAM Write Thermal Management Control Register Device 1 Address Offset 50 57h Default Value 00h Access R W L Size 64 bits 40 28 27 22 21 15 Global Write Hexword Threshold GWHT The 13 bit value this field is multiplied by 21540 arrive at the number of hexwords that must be written within the Global DRAM Write Sampling Window to cause the thermal management mechanism to be invoked Write Thermal Management Time WTMT This value provides a multiplier between 0 and 63 that specifies how long thermal management remains in effect as a number of Global DRAM Write Sampling Windows For example if GDWSW is programmed to 1000_0000b and WTT is set to 01_0000b then thermal management will be performed for 8192 10 host clocks 100 MHz seconds once invoked 128 4 10 h
148. us RTAS R WC 0 Software clears this bit by writing a 1 to it 1 generated a hub interface request that receives a Target Abort completion packet Target Abort Special Cycle Signaled Target Abort Status STAS RO Not Implemented Hardwired to 0 The MCH will not generate a Target Abort hub interface completion packet or special cycle DEVSEL Timing DEVT RO Hardwired to 00 Hub interface does not comprehend DEVSEL protocol Master Data Parity Error Detected DPD RO Not Implemented Hardwired to 0 PERR signaling and messaging are not implemented by the MCH Fast Back to Back FB2B RO Hardwired to 1 Capability List CLIST RO 1 Indicates to the configuration software that this device function implements a list of new capabilities A list of new capabilities is accessed via the CAPPTR Register offset 34h CAPPTR contains an offset pointing to the start address within configuration space of this device where the AGP Capability standard register resides Reserved Inte 82845 for SDR Datasheet 47 Register Description intel 3 5 5 RID Revision Identification Register Device 0 Address Offset 08h Default Value See table below Access RO Size 8 bits This register contains the revision number of the MCH Device 0 These bits are read only and writes to this register have no effect Revision Identification Number This is an 8 bit value that indicates the revision identifi
149. wever if the ENI bit is set in the BCTRL configuration register transactions within the VGA and MDA spaces are sent to AGP If the MCHCFG MDAP configuration bit is set accesses that fall within the MDA range are sent to the hub interface independent of the setting of the ENI bit If the MCHCFG MDAP configuration bit is set accesses in the MDA range are sent to the hub interface independent of the setting of the bit Legacy support requires the ability to have a second graphics controller monochrome in the system In an 845 chipset system accesses in the standard VGA range are forwarded to AGP Since the monochrome adapter may be on the hub interface or or ISA bus the MCH must decode cycles in the MDA range and forward them to the hub interface This capability is controlled by a configuration bit MCHCFG MDAP In addition to the memory range B0000h to B7FFFh the decodes I O cycles at 3B4h 3B5h 3B8h 3B9h and and forwards them to the hub interface An optimization allows the system to reclaim the memory displaced by these regions If SMM memory space is enabled by SMRAM G SMRARE and either the SMRAM D OPEN bit is set or the system bus receives an SMM encoded request for code not data then the transaction is steered to system memory rather than the hub interface Under these conditions bit and the MDAP bit are ignored Inte 82845 for SDR Datasheet 99 Sy
150. wn but the system memory plane and the ICH2 resume well remain active This is the Suspend to RAM STR state All clocks from synthesizers are shut down during the S3 state S4 and S5 Suspend To Disk STD Soft Off The next level of power reduction occurs when the memory power and MCH are shut down in addition to the clock synthesizers ICH2 and the processor power planes The 2 resume well is still powered G3 Mechanical Off In this state only the RTC well is powered The system can only reactivate when the power switch is returned to the position Intel MCH Clocking The 845 chipset is supported by the CK_408 compliant clock synthesizer For details on clocking refer to the Intel Pentium 4 Processor in a 478 Pin Package and Intel 845 Chipset Platform Design Guide Intel MCH System Reset and Power Sequencing For details on MCH system reset and power sequencing refer to the Intel Pentium 4 Processor in a 478 Pin Package and Intel 845 Chipset Platform Design Guide Inte 82845 for SDR Datasheet Electrical Characteristics 6 Electrical Characteristics This chapter contains the absolute maximum operating ratings power characteristics and DC characteristics for the 82845 MCH 6 1 Absolute Maximum Ratings able 18 1515 the MCH s maximum environmental stress ratings Functional operation at the absolute maximum and minimum is neither implied nor guaranteed Functional operating pa
151. y reads and the read of the data that underlies partial writes the MCH supports detection of single bit and multiple bit errors and will correct single bit errors when correction is enabled The MCH supports a thermal management scheme to selectively manage reads and or writes Thermal management can be triggered by preset read write bandwidth limits AGP Interface A single AGP component or connector not both is supported by the MCH AGP interface The AGP buffers operate only in 1 5 V mode They are not 3 3 V safe The AGP interface supports 1x 2x 4x AGP signaling and 2x 4x fast writes AGP semantic cycles to system memory are not snooped on the system bus PCI semantic cycles to system memory are snooped on the system bus The MCH supports PIPE or SBA 7 0 AGP address mechanisms but not both simultaneously Either the PIPE or the SBA 7 0 mechanism must be selected during system initialization Both upstream and downstream addressing is limited to 32 bits for AGP and AGP PCI transactions The MCH contains a 32 deep AGP request queue High priority accesses are supported All accesses from the interface that fall within the Graphics Aperture address range pass through an address translation mechanism with a fully associative 20 entry TLB Accesses between AGP and hub interface are limited to memory writes originating from the hub interface destined for AGP The AGP interface is clocked from a dedicated 66 MHz clock 66IN The A

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