Emerson MVME6100 Film Camera User Manual
Contents
1. Documents For additional information refer to the following table for manufacturers data sheets or user s manuals As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table A 2 Manufacturers Documents Document Title and Source Publication Number MPC7457 RISC Microprocessor Hardware Specification MPC7457EC D Literature Distribution Center for Motorola Rev 1 3 3 2003 Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 Web Site http e www motorola com webapp sps library prod_lib jsp E mail ldcformotorola hibbertco com Tsil48 PCI X to VME Bus Bridge User Manual 80A3020_MA001_02 Tundra Semiconductor Corporation 603 March Road Ottawa Ontario Canada K2K 2M5 Web Site www tundra com PowerPC Apollo Microprocessor Implementation Definition Book Addendum to SC Vger IV Book IV Version 1 0 Literature Distribution Center for Motorola 04 21 00 Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 Web Site http e www motorola com webapp sps library prod_lib jsp E mail ldcformotorola hibbertco com MV64360 System Controller for PowerPC Processors Data Sheet MV S100414 00C Contact your local Motorola Computer Group Field Area Engineer for Programmable Register documentation A 2 Computer Group Literature Center Web Site Manufactu2. F112 2000 F112 OFFF Reserved undefined F112 3000 F11F FFFF Reserved undefined Computer Group Literature Center Web Site System Status Register 1 System Status Register 1 The MVME6100 board System Status Register 1 is a read only register used to provide board status information Table 1 7 System Status Register 1 REG System Status Register 1 0xF1100000 BIT 7 6 5 4 3 2 1 0 FIELD E S g 2 E E SS S e fA S Z J l Se 5 z Se 9 ea os E o A a 2 3 2 e z Ed n lt z D n D OPER R RESET X X X X 1 1 X 0 REF_CLK Reference clock This bit reflects the current state of the 28 8 KHz reference clock derived from the 1 8432 MHz UART oscillator divided by 64 This clock may be used as a fixed timing reference BANK_SEL Boot Flash bank select This bit reflects the current state of the boot Flash bank select jumper A cleared condition indicates that Flash bank A is the boot bank A set condition indicates that Flash B is the boot bank SAFE_START ENV safe start This bit reflects the current state of the ENV safe start select jumper A set condition indicates that MOTLoad should provide the user the capability to select which Boot Image is used to boot the board cleared MOTLoad should proceed with the first boot image found http www motorola com computer literature 1 11 Board Description and Memory Maps ABORT_L
3. Abort This bit reflects the current state of the onboard abort signal This is a debounced version of the abort switch and may be used to determine the state of the abort switch A set condition indicates that the abort switch is not depressed while a cleared condition would indicate that the abort switch is asserted FLASH_BSY_L FLASH Busy This bit provides the current state of the Flash Bank A StrataFlash device Status pins These two open drain output pins are wire ORed Refer to the appropriate Intel StrataFlash data sheet for a description on the function of the Status pin FUSE_STAT Fuse Status This bit indicates the status of the onboard fuses A cleared condition indicates that one of the fuses is open A set condition indicates that all fuses are functional SROM_INIT SROM Init This bit indicates the status of the SROM Init A cleared condition indicates that the SROM Init is disabled A set condition indicates that the SROM Init is enabled and the MV64360 was initialized using the MV64360 User Defined Initialization SROM at A6 1 12 Computer Group Literature Center Web Site System Status Register 2 System Status Register 2 The MVME6100 board system status register 2 provides board control and status bits Table 1 8 System Status Register 2 REG System Status Register 2 0xF1100001 BIT 7 6 5 4 3 2 1 0 FIELD E g D l a Ia S a A a a 9 E S e T P Sn lt m
4. OU 0 MII GMII GMII PCS 1 PCS Select TxD1 0 Resistor 0 Gigabit port 1 0 MII GMII GMII PCS 1 PCS Select WE 3 0 Resistor X DRAM PLLN TBD Refer to MV64360 DP 3 0 Divider 7 4 Specification MV S100614 3 0 00 Rev B 1 13 2003 page 144 for detail MVME6100 is not using this mode BADR 0 Resistor 1 DRAM PLL 1 Pull up NP NP BADR 1 Resistor 1 DRAM PLL 1 Pull down HIKVCO HIKVCO BADR 2 Resistor 1 DRAM PLL 0 PLL power down NP normal operation 1 PLL power up TxDO 6 1 Resistor X DRAMPLLM TBD Refer to MV64360 Divider Specification MV S100614 00 Rev B 1 13 2003 page 144 for detail MVME6100 is not using this mode http www motorola com computer literature Programming Details Table 2 2 MV64360 Power Up Configuration Settings continued Device Default AD Bus Select Power Up Signal Option Setting Description State of Bit vs Function TxDO 7 Resistor 0 JTAG Pad 0 Normal Operation ca Byes 1 Bypass pad calibration TxD1 1 Resistor 0 Core PLL 0 Normal Operation Bypass 1 Bypass the core s PLL TxD1 4 2 Resistors 000 Core PLL 000 Tuning of the core PLL Control clock tree Flash Memory The MVME6100 contains two banks of flash memory accessed via the Device Controller bus contained within MV64360 Each bank contains from 8MB to 64MB of 32 bit wide Boot Block flash memory provided by two 16 bit wide Intel StrataFlash devices The Boot Bank i
5. VME 2Esst ASIC provides Eight programmable VMEbus map decoders A16 A24 A32 and A64 address 8 bit 16 bit and 32 bit single cycle data transfers 8 bit 16 bit 32 bit and 64 bit block transfers Supports SCT BLT MBLT 2eV ME and 2eSST protocols 8 entry command and 4KB data write post buffer 4KB read ahead buffer Uouovovuvovou PMCspan Support One PMCspan slot Supports 33 66 MHz 32 64 bit PCI bus Access through PCI6520 bridge to PMCspan Form Factor Standard 6U VME Miscellaneous Combined reset and abort switch Status LEDs 8 bit software readable switch VME geographical address switch http www motorola com computer literature 1 3 Board Description and Memory Maps bel V 2 S g gt zZ zZ Q P1 S ve V 2 z N gt z zZz 2 CH gt D l S e 8 S P2 S IS 8 o g S vi D L o F O o 4248 0504 Figure 1 1 MVME6100 Board Layout Diagram 1 4 Computer Group Literature Center Web Site Memory Maps Memory M
6. by the MVME6100 as follows 2 14 Computer Group Literature Center Web Site PCI Bus 0 Local Bus Devices PMC Slot 0 PMC Slot 1 INTA INTB INTC INTD INTA INTB INTC INTD GPP 16 GPP 17 GPP 18 GPP 19 MV64360 Figure 2 1 PCI Bus 1 Local Bus PMC Expansion Slots PCI Bus 0 Local Bus Devices The MV64360 PCI Bus 0 local bus contains the Tsil48 ASIC and PCI6520 PMCSpan bridge Tsi148 ASIC The VMEbus interface is provided by the Tsil48 ASIC Tempe is a PCI X bus to VMEbus interface chip While Tsi148 has many of the same features as the VMEchip2 and Universe it includes new features and enhancements Therefore Tsil48 is not register compatible with the VMEchip 2 or Universe chips See the Tsi 48 User s Manual from Tundra Semiconductor listed in Appendix A Related Documentation for further details PCI6520 PMCSpan Bridge The PMCSpan interface is provided by the PCI6520 PCI6520 is a PCI X to PCI X transparent bridge to interface between PMCspan bus and the local PCIO bus This part operates asynchronously between primary local http www motorola com computer literature 2 15 Programming Details PCIO bus at 133MHz and the secondary PMCspan bus at 33 or 66 MHz See the PLX PCI6520 Specification for further programming information MV64360 Interrupt Controller The MVME6100 uses the MV64360 interrupt controller to route inter
7. for service and repair to ensure that all safety features are maintained Observe Warnings in Manual Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment caution when handling testing and adjusting this equipment and its To prevent serious injury or death from dangerous voltages use extreme components Warning Flammability All Motorola PWBs printed wiring boards are manufactured with a flammability rating of 94V 0 by UL recognized manufacturers EMI Caution This equipment generates uses and can radiate electromagnetic energy It d may cause or be susceptible to electromagnetic interference EMI if not Eeer installed and used with adequate EMI protection Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry Danger of explosion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment Caution anufacturer Dispose of used batteries according to the manufacturer s instructions Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du m me type ou d un type Attention quivalent recommand p
8. initialization via the I2C bus for user defined initialization http www motorola com computer literature 2 3 Programming Details The MVME6100 board supports both options An onboard switch setting will be used to select the option If the pin sample only method is selected then states of the various pins on the device AD bus are sampled when reset is deasserted to determine the desired operating modes The following table describes the configuration options Combinations of pullups pulldowns and switches are used to set the options Some options are fixed and some are selectable at build time by installing the proper pullup pulldown resistor Finally some options may be selected using an onboard switch Each option is described in the Table 6 Using the SROM initialization method any of the MV64360 internal registers or other system components i e devices on the PCI bus can be initialized Initialization takes place by sequentially reading 8 byte address data pairs from the SROM and writing the 32 bit data to the decoded 32 bit address until the a data pattern matching the last serial data item register is read from the SROM default value Oxffffffff An 8 Kbyte EEPROM is provided onboard for this user defined initialization of the MV64360 Table 2 2 MV64360 Power Up Configuration Settings Device Default AD Bus Select Power Up Signal Option Setting Description Stat
9. pressing the Ctrl key and the letter simultaneously for example Ctrl d XV Board Description and Memory Maps Introduction This chapter briefly describes the board level hardware features of the MVMEG6100 single board computer including a table of features and a block diagram The remainder of the chapter provides memory map information including a default memory map MOTLoad s processor memory map a default PCI memory map MOTLoad s PCI memory map a PCI I O memory map and system I O memory maps Note Programmable registers in the MV64360 system controller are documented in a separate publication and obtainable from Motorola Computer Group by contacting your Field Area Engineer Refer to Appendix A Related Documentation for more information on obtaining this documentation Overview The MVME6100 is a single board computer based on the PowerPC MPC7457 processor the Marvell MV64360 system controller up to 2 GB of ECC protected DDR DRAM up to 128MB of Flash memory a dual Gigabit Ethernet interface two asynchronous serial ports and two TEEE1386 1 PCI PCI X capable mezzanine card slots PMCs 1 1 Board Description and Memory Maps The following table lists the features of the MVME6100 Table 1 1 MVME6100 Features Summary Feature Description Processor Single 1 3 GHz MPC7457 processor Bus clock frequency at 133 MHz 36 bit address 64 bit data buses Integrated L1 and L2 cach
10. reset and must be reset by the system software to enable writing of the Flash Bank B boot block FBA_WP_HDR Hardware Flash Bank A write protect header status Read ONLY Hardware jumper configuration can not be overridden by the software control bit 6 in this register FBOOTB_WP_HDR Hardware Flash Bank B Boot Block write protect header status Read ONLY Hardware jumper configuration can not be overridden by the software control bit 3 in this register 1 14 Computer Group Literature Center Web Site System Status Register 3 System Status Register 3 The MVME6100 board system status register 3 provides the board software controlled reset functions Table 1 9 System Status Register 3 REG System Status Register 3 0xF1100002 BIT 7 6 5 4 3 2 1 0 FIELD amp DO Loi D z Q AQ D D Q Q Q lt gt gt gt gt gt gt gt O n N n n Co n n D Ei Ei Ei Ei Ei Ei Ei OPER R W R R R R R R R RESET Io 0 0 0 0 0 0 0 BOARD_RESET Board Reset Setting this bit will force a hard reset of the MVME6100 board This bit will clear automatically when the board reset is complete This bit will always be cleared during a read http www motorola com computer literature 1 15 Board Description and Memory Maps Presence Detect Register The MVME5500 board contains a presence detect register that may be read by the system software to determine the presence of optional devic
11. 1 0a at the rising edge of RST The MVME6100 dynamically determines the mode and frequency of the PCI Bus 1 defined by the PCI X Addendum to the PCI Local Bus 2 12 Computer Group Literature Center Web Site PCI Configuration Space Specification Revision 1 0b at the rising edge of RST Onboard logic will sense the states of PCIXCAP and M66EN for all devices on the bus and select the appropriate mode and clock frequency Software can access the MV 64360 Configuration Registers to determine the PCI mode and clock frequency of PCI Bus 1 and PCI Bus 0 Refer to the MV64360 Data Sheet listed in Appendix A Related Documentation for details Voltage Input Output VIO is selected on PCI Bus 1 by the position of the PMC keying pins Both sites should be set for the same VIO that is keyed identically If 5V VIO is selected PCI Bus 1 reverts to PCI mode at 33 MHz PCI Configuration Space The MV64360 controls all PCI configuration space access from either the CPU or PCI busses The IDSEL assignments for MVME6100 are shown on the following table Table 2 6 IDSEL Mapping for PCI Devices Device PCI Address PCI Bus Number Field Line IDSEL Connection PCI Bus 0 PCI 0b1_0000 AD16 MV64360 ASIC Bus 1 PCI Bus 0 0 0b1_0100 AD22 PCI6520 PCI Bus 0 0b1_0101 AD21 Tempe VME Bridge ASIC PCI Bus 1 0b1_0100 AD20 PMC Slot 0 SCSI controller also uses IDSEL AD20 PCI Bus 1 0b1_0101 AD21 PMC Slot 0 Secondary
12. 1 Arbitration Request Grant Pairs 16 I PCI Bus 1 Interrupts PCI PMCO INTA PMC1 INTC 17 I PCI Bus 1 Interrupts PCI PMCO INTB PMC1 INTD 18 I PCI Bus 1 Interrupts PCI PMCO INTC PMC1 INTA 19 I PCI Bus 1 Interrupts PCI PMCO INTD PMC1 INTB 2 2 Computer Group Literature Center Web Site MV64360 Reset Configuration Table 2 1 MV64360 MPP Pin Function Assignments continued MPP Pin Input Number Output Function 20 I PCI Bus 0 Interrupt PCI VME INT 0 Tempe LINTO PMCspan INT 2 21 I PCI Bus 0 Interrupt PCI VME INT 1 Tempe LINT1 PMCspan INT 3 22 I PCI Bus 0 Interrupt PCI VME INT 2 Tempe LINT2 PMCspan INT 0 23 I PCI Bus 0 Interrupt PCI VME INT 3 Tempe LINT3 PMCspan INT 1 MPP 19 16 PCI_1 Interrupts MPP 23 20 PCI_O Interrupts 24 O MV64360 SROM initialization active InitAct 25 O Watchdog Timer Expired output WDE 26 O Watchdog Timer NMI output WDNMI 27 I Reserved for future device interrupt 28 O Tempe ASIC VMEbus grant 29 I Tempe ASIC VMEbus request 30 O PC16520 PMCspan bridge grant 31 I PC16520 PMCspan bridge request MPP 31 28 PCI_O Arbitration Request Grant Pairs MV64360 Reset Configuration The MV64360 supports two methods of device initialization following reset _ Pins sampled on the deassertion of reset Partial pin sample on deassertion of reset plus Serial ROM
13. 21 Dallas Semiconductor Web Site http www dalsemi com TSOP Type I Shielded Metal Cover SMT Yamaichi Electronics USA Web Site http www yeu com A 4 Computer Group Literature Center Web Site Related Specifications Related Specifications For additional information refer to the following table for related specifications For your convenience a source for the listed document is also provided It is important to note that in many cases the information is preliminary and the revision levels of the documents are subject to change without notice Table A 3 Related Specifications Document Title and Source Publication Number VITA _http www vita com VME64 Specification ANSI VITA 1 1994 VME64 Extensions ANSI VITA 1 1 1997 2eSST Source Synchronous Transfer VITA 1 5 199x PCI Special Interest Group PCI SIG http www pcisig com Peripheral Component Interconnect PCI Local Bus Specification PCI Local Bus Revision 2 0 2 1 2 2 Specification PCI X Addendum to the PCI Local Bus Specification Rev 1 0b IEEE http standards ieee org catalog IEEE Common Mezzanine Card Specification CMC Institute of P1386 Draft 2 0 Electrical and Electronics Engineers Inc IEEE PCI Mezzanine Card Specification PMC P1386 1 Draft 2 0 Institute of Electrical and Electronics Engineers Inc http www motorola com computer literature A 5 Index B block diagra
14. DR DRAM Serial Presence Detect There are two onboard SPD serial EEPROMs on the MVME6100 accessible via the UC serial interface The first 128 bytes of each SPD contains module type SDRAM organization and timing parameters 2 10 Computer Group Literature Center Web Site MV64360 Initialization MV64360 Initialization Serial EEPROM devices are provided to support optional initialization of the MV64360 enabled by the SA A switch Using the SROM initialization method any of the MV64360 internal registers or other system components that is devices on the PCI bus can be initialized Initialization takes place by sequentially reading 8 byte address data pairs from the SROM and writing the 32 bit data to the decoded 32 bit address until the a data pattern matching the last serial data item register is read for the SROM default value Oxffffffff The onboard reset logic keeps the processor reset asserted until this initialization process is completed An SROM is provided for user MV64360 initialization VPD and User Configuration EEPROMs The MVME6100 board contains an Atmel AT24C64 or compatible Vital Product Data VPD EEPROM containing configuration information specific to the board Typical information that may be present in the VPD is manufacturer board revision build version date of assembly memory present options present and L3 cache information A second AT24C64 device is available for user data storage Temperatu
15. Flash Bank B Note The internal registers only occupy the first 64KB but minimum http www motorola com computer literature Board Description and Memory Maps Default PCI Memory Map The MV64360 presents the following default PCI memory map after RESET negation Note it is the same as the GT 64260A with the addition of integrated SRAM Table 1 4 Default PCI Address Map PCI Address Start End Size Definition 0000 0000 007F FFFF 8M DRAM Bank 0 0080 0000 OOFF FFFF 8M DRAM Bank 1 0100 0000 017F FFFF 8M DRAM Bank 2 0180 0000 O1FF FFFF 8M DRAM Bank 3 0200 0000 OFFF FFFF 224M Unassigned 1000 0000 11FF FFFF 32M PCI Bus P2P I O Space 1200 0000 13FF FFFF 32M PCI Bus P2P Memory Space 0 1400 0000 1400 FFFF 64K Internal Registers 1401 0000 1BFF FFFF 128M 64K Unassigned 1C00 0000 1C7F FFFF 8M Device CSO 1C80 0000 1CFF FFFF 8M Device CS1 1D00 0000 1DFF FFFF 16M Device CS2 1E00 0000 1 FFF FFFF 32M Unassigned 2000 0000 21FF FFFF 32M PCI Bus 0 P2P I O Space 2200 0000 23FF FFFF 32M PCI Bus 0 P2P Memory Space 0 2400 0000 25FF FFFF 32M PCI Bus 0 P2P Memory Space 1 2600 0000 41 FF FFFF 448M Unassigned 4200 0000 4303 FFFF 256K MV64360 Integrated SRAM 4304 0000 F1FF FFFF 2800M Unassigned 1 8 Computer Group Literature Center Web Site MOTLoad s PCI Memory Maps Table 1 4 Default PCI Address Map continued PCI Ad
16. MVME6100 Single Board Computer Programmer e Reference Guide V6100A PG1 July 2004 Edition Copyright 2004 Motorola Inc All rights reserved Printed in the United States of America Motorola and the stylized M logo are trademarks of Motorola Inc registered in the U S Patent and Trademark Office All other product or service names mentioned in this document are the property of their respective owners Safety Summary The following general safety precautions must be observed during all phases of operation service and repair of this equipment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment The safety precautions listed below represent warnings of certain dangers of which Motorola is aware You as the user of the product should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment Ground the Instrument To minimize shock hazard the equipment chassis and enclosure must be connected to an electrical ground If the equipment is supplied with a three conductor AC power cable the power cable must be plugged into an approved three contact electrical outlet with the grounding wire green yellow reliably connected to an electrical ground safety ground at the power outlet The power jack and mating plug of the power cable meet International El
17. PCI Agent IPMC slot PCI Bus 1 0b1_0110 AD22 PMC Slot 1 PCI Bus 1 Ob1_0111 AD23 PMC Slot 1 Secondary PCI Agent http www motorola com computer literature 2 13 Programming Details PCI Arbitration Assignments for MV64360 ASIC PCI arbitration is performed by the MV64360 ASIC The MV64360 integrates two PCI arbiters one for each PCI interface PCI Bus 0 1 Each arbiter can handle up to six external agents plus one internal agent PCI Bus 0 1 master The internal PCI arbiter REQ GNT signals are multiplexed on the MV64360 MPP pins The internal PCI arbiter is disabled by default the MPP pins function as general purpose inputs Software will configure the MPP pins to function as request grant pairs for the internal PCI arbiter The arbitration assignments on MVME6100 are as follows Table 2 7 PCI Arbitration Assignments for MV64360 ASIC MPP Pin Assignment PCI Master s 30 31 1 PCI6520 PMCspan bridge GNT MPP30 REQ MPP 31 28 29 Tsil48 ASIC VMEbus GNT MPP 28 REQ MPP 29 12 13 PMC Slot 0 GNT REQ 14 15 PMC Slot 1 GNT REQ 8 9 PMC Slot 0 Secondary PCI Agent IPMC761 GNT REQ 10 11 PMC Slot 1 Secondary PCI Agent GNT REQ PCI Bus 1 Local Bus PMC Expansion Slots Two PMC slots reside on the PCI Bus 1 local bus The presence of PMCs can be positively determined by reading System Status Register 3 The INTA INTB INTC and INTD from the PMC slots are routed
18. RJ45 connector on the front panel COM2 is also an RS232 port which is routed to an onboard planar header for rear I O access via option inductors resistors Unused control inputs on COM1 and COM2 are wired active The reference clock frequency for the QUART is 1 8432 MHz All UART ports are capable of signaling at up to 115 Kbaud Real Time Clock and NVRAM The Real Time Clock NVRAM Watchdog Timer is implemented using a SGS Thompson M48T37V Timekeeper SRAM and M4T28 BR12SHI1 SnapHat battery Refer to the M48T37V data sheets for additional programming information Table 1 13 M48T37V Access Address Offset Function 0xF 1110000 0x0000 OxSFFF Available for users 0x0100 0x0200 VxWorks bootline 0x6000 OX6FFF Reserved MOTLoad expansion 0x7000 Ox7FEF MOTLoad use GEVs 0x7FF0 0 Ox7FFF Real Time Block 1 20 Computer Group Literature Center Web Site Programming Details Introduction This chapter includes additional programming information for the MVMEG6100 single board computer Items discussed include m LU UUUUUUUUUU UU MV64360 Multi Purpose Port Configuration on page 2 1 MV64360 Reset Configuration on page 2 3 Flash Memory on page 2 8 Real Time Clock and NVRAM on page 2 8 Two Wire Serial Interface on page 2 9 DDR DRAM Serial Presence Detect on page 2 10 MV64360 Initialization on page 2 11 VPD and User Configuration EEPROMs on page 2 11 Temperature Sensor on pag
19. a m lt OP m H D e n E Q D a gl e 8 a IS IS ca GIE T T ca oe OPER R W R R W R W R W R R R RESET 1 1 1 1 X X X BD_FAIL Board Fail This bit is used to control the Board Fail LED located on the front panel A set condition illuminates the front panel LED and a cleared condition extinguishes the front panel LED EEPROM_WP Not used on the MVME6100 FLASHA_WP Software Flash Bank A Write Protect This bit is to provide software controlled protection against inadvertent writes to the expansion FLASH memory devices Clearing this bit and disabling the HW write protect will enable writes to the Bank A Flash devices This bit is set during reset and must be reset by the system software to enable writing of the flash devices http www motorola com computer literature 1 13 Board Description and Memory Maps TSTAT_MASK Thermostat Mask This bit is used to mask the DS1621 temperature sensor thermostat output If this bit is cleared the thermostat output will be enabled to generate an interrupt on GPP3 If the bit is set the thermostat output is disabled from generating an interrupt FBOOTB_WP Software Flash Bank B Boot Block Write Protect This bit is to provide software controlled protection against inadvertent writes to the Flash Bank B Top 1 MB OxFFF00000 space Clearing this bit and disabling HW write protect will enable writes to the Bank B Flash Top IMB boot block devices This bit is set during
20. antnaseasssaseasanacsas 1 9 Table 1 6 Device Bank 1 VO Memory Map vsiccencissiscn csiovsctvensarisrtscevneiviiesvisees 1 10 Table 1 7 System Stats Register siscsisusscisncasersscussshcsacandbaastaschsecastasinsopabsesoieavians 1 11 Table 1 8 System Status Resister Z sisrreciviroprrr cingvinrcrneaansteneeremnnvnarnsneene 1 13 Table 1 9 System Status Register F soicscsssice cannseuets capisvactoeensntiniooms atgeasmnastaenanaaaaea 1 15 Table kat Presence Detect Register AER 1 16 Table 1 11 Configuration Header Switch Register csssssssessesseenseenesens 1 17 Tape t 12 TEEN E 1 19 Fable 1 13 MASTA 7V AGGESS sornione nann REAREA 1 20 Table 2 1 MV64360 MPP Pin Function Assignments sseseeeseeesereeerererrrrerrereeres 2 2 Table 2 2 MV64360 Power Up Configuration Settings eeesereseeeeeerererrrrerrereeres 2 4 Table 2 3 MASTI E 2 9 Table 2 4 ZC Bus Device Addressi g scsscacticwresieps vienewnmsci nen avinavectiiaeen 2 10 Table RE 2 12 Table 2 6 IDSEL Mapping tor PCI Devices sriereumoireiemisinna t 2 13 Table 2 7 PCI Arbitration Assignments for MV64360 ASIC oo eee 2 14 Table 2 8 MV64300 Interrupt ASSIEME ciccimeacrunocasmonin a 2 16 Table A 1 Motorola Computer Group Documents ssssssesseeseesseererseeerrereresrereseses A 1 Table A 2 Manmutacturers Documents 4 ssiseoresecitesimesnsveccanseiaaleiariis eeineseeaheremnses A 2 Table A d ONG SPECII E A 5 xi About This Guide The MVME6100 Single Boar
21. aps Default Processor Memory Map The MV64360 presents a default CPU memory map following RESET negation The following table shows the default memory map from the point of view of the processor Address bits 35 32 are only relevant for the MPC7457 extended address mode and are not shown in the following Table 1 2 Default Processor Address Map tables Note that it is the same as the GT 64260A with the addition of integrated SRAM Processor Address Notes Start End Size Definition 0000 0000 007F FFFF 8M DRAM Bank 0 0080 0000 OOFF FFFF 8M DRAM Bank 1 0100 0000 017F FFFF 8M DRAM Bank 2 0180 0000 O1FF FFFF 8M DRAM Bank 3 0200 0000 OFFF FFFF 224M Unassigned 1000 0000 11FF FFFF 32M PCI Bus 0 I O Space 1200 0000 13FF FFFF 32M PCI Bus 0 Memory Space 0 1400 0000 1BFF FFFF 128M Unassigned 1C00 0000 1C7F FFFF 8M Device CS0 1C80 0000 1CFF FFFF 8M Device CS1 1D00 0000 1DFF FFFF 16M Device CS2 1E00 0000 1 FFF FFFF 32M Unassigned 2000 0000 21FF FFFF 32M PCI Bus 1 I O 2200 0000 23FF FFFF 32M PCI Bus Memory Space 0 2400 0000 25FF FFFF 32M PCI Bus 1 Memory Space 1 2600 0000 27FF FFFF 32M PCI Bus 1 Memory Space 2 http www motorola com computer literature 1 5 Board Description and Memory Maps Table 1 2 Default Processor Address Map continued Processor Address Notes Start End Size Defin
22. ar le constructeur Mettre au rebut les batteries usag es conform ment aux instructions du fabricant Explosionsgefahr bei unsachgem em Austausch der Batterie Ersatz nur durch denselben oder einen vom Hersteller empfohlenen Typ Entsorgung Vorsicht gebrauchter Batterien nach Angaben des Herstellers CE Notice European Community This is a Class A product In a domestic environment this product may cause radio interference in which case the user may be required to take Warning adequate measures Motorola Computer Group products with the CE marking comply with the EMC Directive 89 336 EEC Compliance with this directive implies conformity to the following European Norms EN55022 Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment this product tested to Equipment Class A EN55024 Information technology equipment Immunity characteristics Limits and methods of measurement Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will maintain the required EMC performance In accordance with European Community directives a Declaration of Conformity has been made and is available on request Please contact your sales representative Notice While reasonable efforts have been made to assure the accuracy of this document Motorola Inc assumes no liabil
23. d Computer Programmer s Reference Guide provides general programming information including memory maps interrupts and register data for the MVME6100 family of boards This document should be used by anyone who wants general as well as technical information about the MVME6100 products As of the printing date of this manual the MV ME6100 supports the models listed below Model Number MVME6100 0161 Description 1 267 GHz MPC7457 processor 512MB DDR memory 128MB Flash Scanbe handles MVME6100 0163 1 267 GHz MPC7457 processor 512MB DDR memory 128MB Flash IEEE handles MVME6100 0171 1 267 GHz MPC7457 processor 1GB DDR memory 128MB Flash Scanbe handles MVME6100 0173 1 267 GHz MPC7457 processor 1GB DDR memory 128MB Flash IEEE handles xiii Overview of Contents This manual is divided into the following chapters and appendices Chapter 1 Board Description and Memory Maps provides a brief product description and a block diagram The remainder of the chapter provides information on memory maps and system and configuration registers Chapter 2 Programming Details provides additional programming information including IDSEL mapping interrupt assignments for the MV64360 interrupt controller flash memory two wire serial interface addressing and other device and system considerations Appendix A Related Documentation provides a listing of related Motorola manuals ve
24. dress Start End Size Definition F200 0000 F3FF FFFF 32M PCI Bus 1 P2P Memory Space 1 F400 0000 FEFF FFFF 176M Unassigned FF00 0000 FF7F FFFF 8M Device CS3 FC00 0000 FFFF FFFF 64M Boot Flash Bank B MOTLoad s PCI Memory Maps MOTLoad s PCI memory map for each PCI domain is shown in the following tables Table 1 5 MOTLoad s PCI Memory Maps PCI Address Start End Size Definition 0000 0000 top_dram dram_size System Memory onboard DRAM VME Memory Map The MVME6100 is fully capable of supporting both the PReP and the CHRP VME Memory Map examples with RAM size limited to 2 GB System I O Memory Map System resources including system control and status registers NVRAMIRTC and the 16550 UART are mapped into a 1 MB address http www motorola com computer literature 1 9 Board Description and Memory Maps range assigned to Device Bank 1 The memory map is defined in the following table Table 1 6 Device Bank 1 I O Memory Map Address Definition F110 0000 System Status Register 1 F110 0001 System Status Register 2 F110 0002 System Status Register 3 F110 0003 Reserved F110 0004 Presence Detect Register F110 0005 Software Readable Header Switch F110 0006 Timebase Enable Register F110 0008 F110 FFFF Reserved for onboard registers F111 0000 F111 7FFF M48T37V NVRAM RTC F112 0000 F112 OFFF COM 1 UART F112 1000 F112 OFFF COM 2 UART
25. dule installed in slot 1 If cleared the PMC module is installed Configuration Header Switch Register S1 The MVME6100 board has an 8 bit header or switch that may be read by the software Table 1 11 Configuration Header Switch Register REG Configuration Header Switch Register 0xF1100005 BIT 7 6 5 4 3 2 1 0 FIELD bel Q i a S a Ser Oo Oo Oo Oo Oo Oo Oo Oo ea ea ea ea ea ea ea ea oO Oo oO Oo oO oO oO oO OPER R RESET X X X X X X X X CFG 7 0 Configuration Bits 7 0 These bits reflect the position of the switch installed in the configuration header location A cleared condition http www motorola com computer literature Board Description and Memory Maps indicates that the switch is ON for the header position associated with that bit and a set condition indicates that the switch is OFF L 8 9 G A ON 16 CFG_0 0 CFG_1 0 CFG_2 0 CFG_3 0 CFG_4 0 CFG_5 0 CFG_6 0 CFG_7 0 1 16 ON M CFG_0 1 M CFG 1 1 M CFG 2 1 a M CFG_3 1 a M CFG_4 1 gt M CFG_5 1 Oo CFG _6 1 o M CFG_7 1 Computer Group Literature Center Web Site Time Base Enable Register Time Base Enable Register The time base enable TBEN register provides the means to control the process
26. e L3 Cache 2MB using DDR SRAM Bus clock frequency at 211 MHz Flash Two banks A amp B of soldered Intel StrataFlash devices 8 to 64MB supported on each bank Boot bank is switch selectable between banks Bank A has combination of software and hardware write protect scheme Bank B top 1MB block can be write protected through software hardware write protect control System Memory Two banks on board for up to 2GB using 256Mb or 512Mb devices Bus clock frequency at 133 MHz Memory Controller PCI Host Bridge Dual 10 100 1000 Ethernet Interrupt Controller PCI Interface UC Interface Provided by Marvell MV64360 system controller NVRAM Real Time Clock Watchdog Timer 32KB provided by MK48T37 On board Peripheral Support Dual 10 100 1000 Ethernet ports routed to front panel RJ 45 connectors one optionally routed to P2 backplane Two asynchronous serial ports provided by an ST16C554D one serial port is routed to a front panel RJ 45 connector and the second serial port is optionally routed to the P2 connector for rear I O or on board header Computer Group Literature Center Web Site Overview Table 1 1 MVME6100 Features Summary continued Feature Description PCI PMC Two 32 64 bit PMC slots with front panel I O plus P2 rear I O as specified by IEEE P1386 64 bit slots 33 66 MHz PCI or 66 100 MHz PCI X VME Interface Tsil48
27. e 2 11 MV64360 Device Controller Bank Assignments on page 2 11 MPC Bus and PCI Bus Arbitration on page 2 12 PCI Bus 0 and PCI Bus 1 Local Buses on page 2 12 MV64360 Interrupt Controller on page 2 16 MV64360 Endian Issues on page 2 18 MV64360 Multi Purpose Port Configuration The MV64360 contains a 32 bit multi purpose port MPP The MPP pins can be configured as general purpose I O pins as external interrupt inputs or as a specific control status pin for one of the MV64360 internal devices After reset all MPP pins default to GPP pins general purpose inputs Software must then configure each of the pins for the desired function The 2 1 Programming Details following table defines the function assigned to each MPP pin on the MVME6100 board Table 2 1 MV64360 MPP Pin Function Assignments MPP Pin Input Number Output Function 0 I COM 1 COM2 interrupts ORed 1 I Unused 2 I Abort interrupt 3 I RTC and thermostat interrupts ORed 4 I Unused 5 I IPMC761 interrupt 6 I MV64360 WDNMI interrupt 7 I BCM5421S PHY interrupts ORed MPP 7 0 Interrupts 8 O PCI Bus 1 PMC slot 0 agent grant 9 I PCI Bus 1 PMC slot 0 agent request 10 O PCI Bus 1 PMC slot 1 agent grant 11 I PCI Bus 1 PMC slot 1 agent request 12 O PCI Bus 1 PMC slot 0 grant 13 I PCI Bus 1 PMC slot 0 request 14 O PCI Bus 1 PMC slot 1 grant 15 I PCI Bus 1 PMC slot 1 request MPP 15 8 PCI_
28. e of Bit vs Function AD 0 switch X SROM 0 No SROM initialization EE Ti SROM initialization enabled AD 1 Resistor 1 DRAM Pads 0 Calibration Disabled CARDED ifa Calibration Enabled AD 3 2 Resistors 11 SROM Device 00 1010000 A0 SE 01 1010001 A2 10 1010010 A4 11 1010011 A6 AD 4 Fixed 1 Internal 60x 0 Internal arbiter disabled Base 1 Internal arbiter enabled 2 4 Computer Group Literature Center Web Site MV64360 Reset Configuration Table 2 2 MV64360 Power Up Configuration Settings continued Device Default AD Bus Select Power Up Signal Option Setting Description State of Bit vs Function AD 5 Resistor 1 Internal Space 0 0x 1400 0000 ee 1 Oxf100 0000 AD 7 6 Resistor 01 CPU Bus 00 60x bus mode Configuration To MPX bus mode 10 Reserved 11 Reserved AD 8 Resistor 1 CPU Pads 0 Calibration Disabled A Calibration Enabled AD 9 Fixed 0 Multiple 0 Not supported Nive eo 1 Supported Support AD 12 Resistor 1 PCI_O Pads 0 Calibration Disabled E la Calibration Enabled AD 13 Resistor 1 PCI_1 Pads 0 Calibration Disabled nee ss Calibration Enabled AD 15 14 Resistors 10 BootCS 00 8 bits Device Width 01 16 bits 10 32 bits 11 Reserved AD 16 Resistor 1 PCI Retry 0 Disable 1 Enable AD 17 Fixed 1 1 Must pull high http www motorola com computer literature Programming Details Table 2 2 MV64360 Power Up Configuration Se
29. ectrotechnical Commission IEC safety standards and local electrical regulatory codes Do Not Operate in an Explosive Atmosphere Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage Keep Away From Live Circuits Inside the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries such personnel should always disconnect power and discharge circuits before touching components Use Caution When Exposing or Handling a CRT Breakage of a Cathode Ray Tube CRT causes a high velocity scattering of glass fragments implosion To prevent CRT implosion do not handle the CRT and avoid rough handling or jarring of the equipment Handling of a CRT should be done only by qualified service personnel using approved safety mask and gloves Do Not Substitute Parts or Modify Equipment Do not install substitute parts or perform any unauthorized modification of the equipment Contact your local Motorola representative
30. eg srein en r r NE E heli 2 11 MV64360 Device Controller Bank Assignments esseieissnirisissssisrsruresemmisssi 2 11 MPC Bus and PCI Bus Agbittation i c ccsivivesiesivenrvensvecnienscnreniagecsone au mienpeai neers 2 12 PCI Bus O and PCT Bus 1 Local BUSES 2 si ccsscssussenasceiieiesgecnsbaunsnxtecasgacesbieenaoem sees 2 12 PCI Made Frequency melee titi sanere r an AR 2 12 PCI Com onrat S PICE gea Seege eege S 2 13 PCI Arbitration Assignments for MV64360 ASIC oo eee eee eeseeteeeeeees 2 14 PCI Bus 1 Local Bus PMC Expansion Slots s c csscscsisocsecsssaccsseapiecescesastseness 2 14 Pol Bust Local E 2 15 RK RE 2 15 PEIO PMCS pan Se errimea aaea esas 2 15 WEY Ga SGD Webern ra E 2 16 LE 2 18 APPENDIX A Related Documentation Motorola Computer Group Documents iesse CES A 1 Ktauu geruegg DOCENS paariraa Kees Aste eebe PRENERA aR ERA AERA A 2 LE A 5 viii List of Figures Figure 1 1 MVMEG6100 Board Layout Diagram eu iesgtetegeabtak ege wcorentweeoswers 1 4 Figure 2 1 PCI Bus 1 Local Bus PMC Expansion Slots A 2 15 List of Tables Table lol MVMEGIOO Features Zen ged 1 2 Table 1 2 Default Processor Address Map vissscisa cisisisasvesssascervssnrias Eege 1 5 Table 1 3 MOTLaad s Processor Address Map casissivssessnesesssvevmsanecernobantiaceestakcays 1 7 Table 1 4 Default PCI Address Map sccicpcitisinneascsinncnrnva vers cvawinnneinnaninns 1 8 Table 1 5 MOTLoad s PCI Memory Maps sciisicccssscsascssatoiastrmcen
31. es Table 1 10 Presence Detect Register REG Presence Detect Register 0xF1100004 BIT 7 6 3 4 3 2 1 0 FIELD e 4 a la z 2 S g z S S IS Z z E S R Is Ei GG Si D D E ES ES OPER R RESET X X X X X X X X IPMC_PRSNT IPMC Module Present If set HIGH true there is PMCspan module installed If cleared the PMCspan module is not installed EREADY1 EREADY 1 Indicates that the PrPMC module installed in PMC slot 2 is ready for enumeration when set If cleared the PrPMC module is not ready for enumeration The PrPMC software must assert EREADY for this bit to be set The purpose of EREADY is to provide a signaling method indicating that a non monarch vassal PrPMC is ready to be enumerated EREADY0 EREADYO Indicates that the PrPMC module installed in PMC slot 1 is ready for enumeration when set If cleared the PrPMC module is not ready for enumeration The purpose of EREADY is to provide a signaling method indicating that a non monarch vassal PrPMC is ready to be enumerated Computer Group Literature Center Web Site Configuration Header Switch Register S1 PCIE_PRSNT_L PMCspan Module Present If set there is no PMCspan module installed If cleared the PMCspan module is installed PMCOP_L PMC Module 0 Present If set there is no PMC module installed in slot 0 If cleared the PMC module is installed PMC1P_L PMC Module 1 Present If set there is no PMC mo
32. ition 2800 0000 29FF FFFF 32M PCI Bus 1 Memory Space 3 2A00 0000 41 FF FFFF 384M Unassigned 4200 0000 4303 FFFF 256K MV64360 Integrated SRAM 4304 0000 FOFF FFFF 2783M Unassigned F100 0000 F100 FFFF 64K Internal Registers See Note F101 0000 HIER FFFF 16M 64K Unassigned F200 0000 F3FF FFFF 32M PCI Bus 0 Memory Space 1 F400 0000 FSFF FFFF 32M PCI Bus 0 Memory Space 2 F600 0000 F7FF FFFF 32M PCI Bus 0 Memory Space 3 F800 0000 FEFF FFFF 112M Unassigned FF00 0000 FF7F FFFF 8M Device CS3 FCO 0000 FFFF FFFF 64M Boot Flash Bank A or B depending on S4 3 switch setting Note Set by configuration resistors 1 6 Computer Group Literature Center Web Site MOTLoad s Processor Memory Map MOTLoad s Processor Memory Map MOTLoad s processor memory map is given in the following table Table 1 3 MOTLoad s Processor Address Map address decoding resolution is 1MB Processor Address Start End Size Definition Notes 0000 0000 top_dram 1 dram_size System Memory onboard DRAM 8000 0000 DFFF FFFF 1536M PCI Bus 0 and or VME Memory Space E000 0000 EFFF FFFF 256M PCI Bus 1 Memory Space F000 0000 FO7F FFFF 8M PCI Bus 1 I O Space F080 0000 FOFF FFFF 8M PCI Bus 0 I O Space F100 0000 F10F FFFF 1M MV64360 Internal Registers See Note F110 0000 F11F FFFF 1M Device CS1 I O System Regs NVRAM RTC UARTs F400 0000 F7FF FFFF 64M Device CSO Flash Bank A F800 0000 FBFF FFFF 64M Device Boot
33. ity resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to the Motorola Computer Group Web site The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause a
34. m 1 4 C comments sending xiv config switch register 1 17 conventions used in the manual xv D default PCI memory map 1 8 default processor memory map 1 5 documentation related A 1 manual conventions xv manufacturers documents A 2 memory maps default PCI 1 8 default processor 1 5 MOTLoad s PCI 1 9 MOTLoad s processor 1 7 system I O 1 9 MOTLoad s PCI memory map 1 9 MOTLoad s processor memory map 1 7 N NVRAM 2 8 P presence detect register 1 16 R real time clock 2 8 registers config switch register 1 17 presence detect register 1 16 system status register 1 1 11 system status register 2 1 13 system status register 3 1 15 time base enable register 1 19 related documentation A 1 S suggestions submitting Xiv system I O memory map 1 9 system status register 1 1 11 system status register 2 1 13 system status register 3 1 15 T time base enable register 1 19 typeface meaning of xv
35. memory is never swapped The internal registers of the MV64360 are always programed in little endian On a CPU access to the internal registers data is byte swapped Data swapping on a CPU access to the PCI is controlled via PCI Swap bits of each PCI Low Address register This configurable setting allows a CPU access to PCI agents with a different endianess convention Refer to the MV64360 Data Sheet listed in Appendix A Related Documentation for additional information and programming details Computer Group Literature Center Web Site Related Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual You can obtain electronic copies of Motorola Computer Group publications by LI Contacting your local Motorola sales office LI Visiting Motorola Computer Group s World Wide Web literature site http www motorola com computer literature Table A 1 Motorola Computer Group Documents Document Title Motorola Publication Number and Use MVME6100 Single Board Computer Installation V6100A IH and Use MOTLoad Firmware Package User s Manual MOTLODA UM IPMC712 761 I O Module Installation and Use VIPMCA IH PMCspan PMC Adapter Carrier Board Installation PMCSPANA IH To obtain the most up to date product information in PDF or HTML format visit http www motorola com computer literature A Related Documentation Manufacturers
36. nal and external interrupt requests to the CPU and the PCI bus The MV64360 interrupt controller registers are implemented as part of the CPU interface unit in order to have minimum read latency from CPU interrupt handler This is not backward compatible with the Discovery I implementation since the registers are placed at different offsets The external interrupt sources will use the GPP interface to register external interrupts The following table shows the MVME6100 interrupt assignment to MV64360 GPP pins Table 2 8 MV64360 Interrupt Assignments GPP Group MV64360 Edge Level Polarity Interrupt Source Notes 0 GPP 0 Level High COM1 I COM2 3 GPP 1 Level N A Unused pulled high 7 onboard GPP 2 Level Low ABORT GPP 3 Level Low RTC Thermostat output 6 GPP 5 Level High IPMC761 interrupt 2 GPP 6 Level Low MV64360 WDNMI interrupt GPP 7 Level Low BCMS5421S PHY 1 INTR l BCMS5421S PHY 2 INTR 2 GPP 16 Level Low PCI PMC 0 INTA PMC 1 2 INTC GPP 17 Level Low PCI PMC 0 INTB PMC 1 2 INTD 2 16 Computer Group Literature Center Web Site MV64360 Interrupt Controller Table 2 8 MV64360 Interrupt Assignments continued Bus 0 GPP Group MV64360 Edge Level Polarity Interrupt Source Notes GPP 18 Level Low PCI PMC 0 INTC PMC 1 2 INTA GPP 19 Level Low PCI PMC 0 INTD PMC 1 2 INTB GPP 20 Level Lo
37. ndor documentation and industry specifications Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation We want to know what you think about our manuals and how we can make them better Mail comments to Motorola Computer Group Reader Comments DW164 2900 S Diablo Way Tempe Arizona 85282 You can also submit comments to the following e mail address reader comments mcg mot com In all your correspondence please list your name position and company Be sure to include the title and part number of the manual and tell how you used it Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements Conventions Used in This Manual The following typographical conventions are used in this document bold is used for user input that you type just as it appears it is also used for commands options and arguments to commands and names of programs directories and files italic is used for names of variables to which you assign values for function parameters and for structure names and fields Italic is also used for comments in screen displays and examples and to introduce new terms courier is used for system output for example screen displays reports examples and system prompts lt Enter gt lt Return gt or lt CR gt represents the carriage return or Enter key Ctrl represents the Control key Execute control characters by
38. or s TBEN input Table 1 12 TBEN Register REG TBEN Register 0xF 1100006 FIELD e D Lei o o o o o A SC IS gt if e e e e 88 IS ai ai oi oi oi oi Be Ie OPER R W RESET 1 1 1 1 1 X X 1 TBENO Processor 0 time base enable When this bit is cleared the TBEN pin of processor 0 is driven low When this bit is set the TBEN pin is driven high TBENI Not used on the MVME6100 Quad Universal Asynchronous Receiver Transmitter UART The MVME6100 board contains one EXAR ST16C554D Quad UART device connected to the MV64360 device controller bus to provide asynchronous debug ports The Quad UART supports up to four asynchronous serial ports of which two are used on the MVME6100 The ST16C554D is a universal asynchronous receiver and transmitter and is an enhanced UART with 16 byte FIFOs receive trigger levels and data rates up to 1 5 Mbps Onboard status registers provide the user with error indications operational status and modem interface control System http www motorola com computer literature 1 19 Board Description and Memory Maps interrupts may be tailored to meet user requirements The ST16C554DCQ64 provides constant active interrupt outputs but do not offer TXRDY RXRDY outputs Refer to the EXAR ST16C554D data sheet for additional information COM 1 is an RS232 port and the TTL level signals are routed through appropriate EIA 232 drivers and receivers to an
39. re Sensor The MVME6100 board provides a Maxim DS1621 digital temperature sensor with an DC Serial Bus interface This device may be used to provide a measure of the ambient temperature of the board MV64360 Device Controller Bank Assignments The MVME6100 board uses three of the MV64360 Device Controller banks for interfacing to various devices The following tables define the device bank assignments and the programmable device bank timing parameters required for each of the banks used http www motorola com computer literature 2 11 Programming Details Table 2 5 Device Bank Assignments Device Data Bank Width Function Notes 0 32 bit Bank A or Bank B Soldered FLASH 1 1 8 bit T O Devices 2 NA Not Used 3 NA Not Used Boot 32 bit Bank A or Bank B Soldered FLASH 1 Note 1 Determined by boot bank select jumper MPC Bus and PCI Bus Arbitration The MV64360 ASIC supplies these functions Refer to the MV64360 Data Sheet listed in Appendix A Related Documentation for details PCI Bus 0 and PCI Bus 1 Local Buses The PCI devices on the MVME6100 are the MV64360 ASIC the PMCspan bridge PCI6520 the Tsil48 ASIC PMCspan slot and the PMC Slots PCI Mode Frequency Selection The MVME6100 PCI Bus 0 bus is be set to PCI X and 133 MHz for maximum performance Onboard logic drives the PCI X initialization pattern as defined by the PCI X Addendum to the PCI Local Bus Specification Revision
40. rers Documents Table A 2 Manufacturers Documents continued Document Title and Source Interface Broadcom Corporation Web Site http www broadcom com BCM5421S 10 100 1000BASE T Gigabit Transceiver with SERDES Publication Number 5421S DS05 D2 10 25 02 3 Volt Intel StrataFlash Memory 28F256K3 Intel Corporation Literature Center 19521 E 32nd Parkway Aurora CO 80011 8141 Web Site http developer intel com design flcomp datashts 290737 htm 290737 PCI6520 HB7 Transparent PCIx PCIx Bridge Preliminary Data Book PLX Technology Inc 870 Maude Avenue Sunnyvale California 94085 Web Site http www hintcorp com products hint default asp PCI6520 Ver 0 992 EXAR ST16C554 554D ST68C554 Quad UART with 16 Byte FIFOs EXAR Corporation 48720 Kato Road Fremont CA 94538 Web Site http www exar com ST16C554 554D Rev 3 10 http www motorola com computer literature A A Related Documentation Table A 2 Manufacturers Documents continued Document Title and Source Publication Number 3 3V 5V 256Kbit 32Kx8 Timekeeper SRAM M48T37V ST Microelectronics 1000 East Bell Road Phoenix AZ 85022 Web Site http www st com stonline books toc index htm 2 Wire Serial CMOS EEPROM AT24C02N Atmel Corporation AT24C64A San Jose CA Web Site http www atmel com atmel support Dallas Semiconductor DS 1621Digital Thermometer and Thermostat DS16
41. s jumper selectable to select either flash bank as the boot bank The jumper effectively swaps the chip selects to the two flash banks so that either bank can be used as the boot bank The state of the jumper is readable in the BANK_SELECT bit of System Status Register 1 to properly set up the MV64360 Device Controller Bus memory maps The boot device bank is the same as any of the other device banks except that its default address map matches the PowerPC CPU boot address Oxfff0 0100 and that its default width is sampled at reset Real Time Clock and NVRAM The Real Time Clock NVRAM Watchdog Timer is implemented using a SGS Thompson M48T37V Timekeeper SRAM and M4T28 BR12SH1 SnapHat battery Refer to the M48T37V data sheets for additional programming information Refer to Appendix A Related Documentation 2 8 Computer Group Literature Center Web Site Two Wire Serial Interface Table 2 3 M48T37V Access Address Offset Function 0xF1110000 0x0000 OxSFFF Available for users 0x0100 0x0200 VxWorks bootline 0x6000 OX6FFF Reserved MOTLoad expansion 0x7000 Ox7FEF MOTLoad use GEVs Ox7FFO 0 Ox7FFF Real Time Block Two Wire Serial Interface A two wire serial interface for the MVME6100 is provided by an PC compatible serial controller integrated into the MV64360 system controller The DC serial controller provides two basic functions The first function is to provide MV64360 regis
42. t DFARS 252 227 7014 Jun 1995 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 Contents About This Guide EE xiv Commens and SUCHSREIIIS sopsie5 cctecssystanuies sancasueshsapignaccs sbeuiedbeniabeddediipemncaeieeneunanges xiv Conventions Used int This Mannal EE XV CHAPTER 1 Board Description and Memory Maps Tntroductioi E 1 1 ENEE Ee 1 1 LE E 1 5 Detault Processor Memory Map isesisccstcsscntscsssscsncssabissectesaies ape tats ese pomaasanes 1 5 NMOTLodd s Processor Memory Map E 1 7 Werle PEI Memory Nap E 1 8 MOTLoad s PEI Memory Maps dicoriierere iinei ea RRO ERE 1 9 Ka 1 9 Seege LO Memory Mop Edel 1 9 OSU BE EE 1 11 SEENEN Ee 1 13 E Ee 1 15 Presence Detect Register ee EE 1 16 Configuration HeadenS witch Register S1 s cscissecancssscsstansscasssLasessssesscocesasess 1 17 Time Base Emable es tet cusses th cerca AA 1 19 Quad Universal Asynchronous Receiver Transmitter UART 00 eee 1 19 Real Tine Clock mad NVRAM WE 1 20 CHAPTER 2 Programming Details engen reniri EA 2 1 MV64360 Multi Purpose Port Configuration essesseseessseeesessreersreerrrrererreseeresere 2 1 MOTIGO Reset COnN OR aare E E RE 2 3 BESSA RT senideren R N Ea 2 8 Real Time Coik and NY RAM EE 2 8 RK EE 2 9 DDE DRAM Semel Presence Delect EE 2 10 NEV 64360 Tatahzatweng srera r R 2 11 VPD and User Configuration EEPROMS cisscescesssnsessassasnsssonsensnebarasonnenbantactrsctantne 2 11 Vil Temperaire een
43. ter initialization following a reset The MV64360 can be configured by switch setting to automatically read data out of a serial EEPROM following a reset and initialize any number of internal registers In the second function the controller is used by the system software to read the contents of the VPD and SPD EEPROMs contained on the MVME6100 to initialize the memory controller and other interfaces For additional details regarding the MV64360 two wire serial controller operation refer to the MV64360 System Controller Data Sheet See Appendix A Related Documentation http www motorola com computer literature 2 9 Programming Details The following table shows the UC devices on the MVME6100 and their assigned device IDs Table 2 4 DC Bus Device Addressing Device Address DC BUS Device Function Size A2A1A0 Address Notes Memory SPD Bank 0 and 1 256 x 8 000b A0 1 Memory SPD Bank 2 and 3 256 x 8 001b A2 1 Reserved PMCSpan SROM NA 010b A4 MV64360 User Defined Initialization 8K x 8 011b A6 2 Configuration VPD 8Kx8 100b A8 2 User VPD 8K x8 101b AA 2 Not Used NA 110b AC Not Used NA 111b AE DS1621 Temperature Sensor NA 011b 90 Notes 1 The SPD defines the physical attributes of each bank or group of banks i e if both banks of a group are populated they will be the same speed and memory size 2 This is a dual address serial EEPROM AT24C64A or equivalent D
44. ttings continued Device Default AD Bus Select Power Up Signal Option Setting Description State of Bit vs Function AD 18 Resistor 1 DRAM Clock 0 DRAM is running at a Select higher frequency than the core clock 1 DRAM is running at a same frequency as the core clock AD 19 Resistor 1 DRAM 0 DRAM address and control Address Contr signals toggle on falling ol Delay edge of DRAM clock 1 DRAM address and control signals toggle on rising edge of DRAM clock AD 21 20 Resistors Ol DRAM control 00 Reserved path pipeline 01 Two Pipe stages select 10 Reserved 11 Three pipe stages AD 24 22 Resistors 000 DRAM read 000 DRAM running in sync path control 100 mode 001 DRAM running in async 111 mode AD 25 Fixed 0 Gigabit port3 0 Disable Pehle l Enable AD 28 26 Resistors 101 PCI_1 DLL 000 DLL disable cone 001 Conventional PCI mode at 66MHz 101 PCI X mode at 133 MHz 110 PCI X mode at 66 MHz 2 6 Computer Group Literature Center Web Site MV64360 Reset Configuration Table 2 2 MV64360 Power Up Configuration Settings continued Device Default AD Bus Select Power Up Signal Option Setting Description State of Bit vs Function AD 31 29 Resistors 101 PCI_O DLL 000 DLL disable oe 001 Conventional PCI mode at 66MHz 101 PCI X mode at 133 MHz 110 PCI X mode at 66 MHz TxDO 0 Resistor 0 Gigabit oort
45. w PCI VME INT 0 Tsil48 1 5 LINTO PMCspan INT 2 GPP 21 Level Low PCI VME INT 1 Tsil48 1 5 LINT1 PMCspan INT 3 GPP 22 Level Low PCI VME INT 2 Tsil48 1 5 LINT2 PMCspan INT 0 GPP 23 Level Low PCI VME INT 3 Tsil48 1 5 LINT3 PMCspan INT 1 3 GPP 24 Reserved for SROM initialization active InitAct output GPP 25 Reserved for Watchdog Timer WDE output GPP 26 Reserved for Watchdog Timer WDNMI output GPP 27 Reserved for future device interrupt Notes 1 The interrupting device is addressed from the MV64360 PCI 2 The interrupting device is addressed from the MV64360 PCI Bus 1 3 The interrupting device is addressed from the MV64360 Device Bus http www motorola com computer literature Programming Details The interrupting device is addressed from the MV64360 I2C Bus The mapping of VMEbus interrupt sources and Tsil48 internal interrupt sources are programmable via the Interrupt Map Registers 1 and 2 in the Tsil48 ASIC The DS1621 Digital Thermometer and Thermostat provides 9 bit temperature readings which indicate the temperature of the device The thermal alarm output TOUT is active when the temperature of the device exceeds a user defined temperature TH GPP 1 4 30 31 are unused They are resistively pulled high onboard MV64360 Endian Issues The MV64360 supports only a big endian CPU bus The endianess of the local memory DDR and SRAM is also big endian Data transferred to from the local
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