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Digi NS9215 Computer Hardware User Manual

1. map Offset 31 24 23 16 15 8 7 0 090 0000 General Arbiter Control A090 0004 BRCO A090 0008 BRCI A090 000C BRC2 A090 0010 BRC3 A090 0014 Reserved A090 0018 AHB Error Detect Status 1 A090 001C AHB Error Detect Status 2 A090 0020 AHB Error Monitoring Configuration A090 0024 Timer Master Control A090 0028 Timer 0 Reload Count and Compare register A090 002C Timer Reload Count and Compare register A090 0030 Timer 2 Reload Count and Compare register A090 0034 Timer 3 Reload Count and Compare register A090 0038 Timer 4 Reload Count and Compare register A090 003C Timer 5 Reload Count and Compare register A090 0040 Timer 6 Reload Count and Compare register A090 0044 Timer 7 Reload Count and Compare register A090 0048 Timer 8 Reload Count and Compare register A090 004C Timer 9 Reload Count and Compare register A090 0050 Timer 0 Read and Capture register A090 0054 Timer Read and Capture register A090 0058 Timer 2 Read and Capture register A090 005C Timer 3 Read and Capture register A090 0060 Timer 4 Read and Capture register A090 0064 Timer 5 Read and Capture register A090 0068 Timer 6 Read and Capture register A090 006C Timer 7 Read and Capture register A090 0070 Timer 8 Read and Capture register 154 Hardware Reference NS9215 www digiembedded com SYSTEM CONTROL MODULE System configuration registers 31 24 23 16
2. 090 0074 Timer 9 Read and Capture register A090 0078 Timer 6 High register A090 007C Timer 7 High register A090 0080 Timer 8 High register A090 0084 Timer 9 High register A090 0088 Timer 6 Low register A090 008C Timer 7 Low register A090 0090 Timer 8 Low register A090 0094 Timer 9 Low register A090 0098 Timer 6 High and Low Step register A090 009C Timer 7 High and Low Step register A090 00A0 Timer 8 High and Low Step register A090 00A4 Timer 9 High and Low Step register A090 00A8 Timer 6 Reload Step register A090 00AC Timer 7 Reload Step register A090 00 0 Timer 8 Reload Step register A090 00 4 Timer 9 Reload Step register A090 00B8 Reserved A090 00BC Reserved A090 00 0 Reserved A090 00C4 Interrupt Vector Address Register Level 0 A090 00C8 Interrupt Vector Address Register Level 1 A090 00CC Interrupt Vector Address Register Level 2 A090 0000 Interrupt Vector Address Register Level 3 A090 00D4 Interrupt Vector Address Register Level 4 A090 00D8 Interrupt Vector Address Register Level 5 A090 00DC Interrupt Vector Address Register Level 6 A090 00 0 Interrupt Vector Address Register Level 7 A090 00 4 Interrupt Vector Address Register Level 8 A090 00 8 Interrupt Vector Address Register Level 9 A090 00EC Interrupt Vector Address Register Level 10 A090 00F0 Interrupt Vector Address Register Level 11 A090 00 4 Interrupt Vector Address Register Level 12 155 156 SYS
3. PLL div by Ref Clk 2 4 8 16 32 64 986 CPU clock 149 9136 128 clock z max programmable 1 set by BP mux select default is strapping NR 4 0 AHB clock CCSel 0 main clocks or software OD 1 0 1 to modules E setby 4 8 16 32 64 128 AHB clocks 74 9569MHz software 8 0 256 only programmable PLL Vco RefCIk NR 1 NF 1 ClkOut PLL Vco OD 1 defaults NR 1 8 OD 1 1 NF 1 61 Sample Clock Frequency Settings With 29 4912 2 Crystal NF 1 61 and OD 1 1 NR 1 Out CPU clock CPU clock AHB clock CCSel 1 CCSel 0 6 299 8272 149 9136 74 9568 74 9568 7 256 9947 128 4975 64 2487 64 2487 8 224 8704 112 4352 56 2176 56 2176 9 199 8848 99 9424 49 9712 49 9712 10 179 8962 89 9482 44 9741 44 9741 11 163 5421 81 7711 40 8855 40 8855 12 149 9136 74 9568 37 4784 37 4784 Restrictions RefCIk NR 1 range 275KHz 550MHz PLL Vco range 110 2 550MHz Bootstrap initialization Configuring the powerup settings The PLL and other system configuration settings can be configured at powerup before the CPU boots External pins configure the necessary control register bits at powerup There are internal pullup resistors on these pins to provide a default configuration External pulldown resistors can configure the PLL and system configuration registers depending on the applic
4. 331 TX Buffer Descriptor 21 2 4 0 2 0 1 ens 332 Off Set E M 332 egre HU 333 Occ 333 Offset deeem hoe ie RE TR d e C 333 RX FIFO 333 Sample hash table 0 50050 334 Chapter 7 External 339 E 339 Initiating DMA transfers iiie teet een lee 339 Processor initiated 339 External 339 buffer 2 2 0 0 4 42 41010 enn 340 DMA buffer descriptor diagram 340 Source address 4 0 0 00 2202002020 22 22 340 www digiembedded com 17 18 Buffer length m 340 Destination address 0 0 04 2 4 340 rM T 341 Wrap W bib ERR AR RIA 341 Em 341 341 Dit 341 Descriptor list processing inae 3
5. 329 Multicast Low Address Mask Register 0 329 Multicast Low Address Mask Register 1 329 Multicast Low Address Mask Register 2 329 Multicast Low Address Mask Register 3 329 Multicast Low Address Mask Register 4 330 Multicast Low Address Mask Register 5 330 Multicast Low Address Mask Register 6 330 Multicast Low Address Mask Register 7 330 Multicast High Address Mask Register 0 330 Multicast High Address Mask Register 4 330 Multicast High Address Mask Register 2 330 Multicast High Address Mask Register 3 330 Multicast High Address Mask Register 4 330 Multicast High Address Mask Register 5 331 Multicast High Address Mask Register 6 331 Multicast High Address Mask Register 7 331 Multicast Address Filter Enable
6. 379 Module TX 20 00 20 2 2 0 0 0 202 22222 380 Module DMA TX Buffer Descriptor 381 Module TX Interrupt Configuration register 381 Module Direct Mode TX Data FIFO 382 Module Direct Mode TX Data Last 383 Chapter 10 Serial Control Module UART 385 e 385 UART module 5 menm 386 TELA RR TE GU Fara 386 Example corfig tat loh eiecit ipea esie e e ete o 386 Baud rate 1 eere a etu d e ERR Ce a a a Pd eui 387 LECT 387 Hardware based flow 000 1 388 Character based flow control XON 388 Example esee ei erae REPE REMINDER ERRARE 388 Forced character transmission 2 388 Force character transmission 389 Collecting feedback cere ban RR RETRO 389 ARM wakeup
7. 1 CRm Figure 1 5 and bit pattern The mnemonics for these instructions are MCR cond p15 opcode_1 Rd CRn CRm opcode_2 MRC cond p15 opcode_1 Rd CRn CRm opcode_2 If you try to read from a write only register or write to a read only register you will have UNPREDICTABLE results In all instructions that access CP15 m opcode 1 field SHOULD BE ZERO except when the values specified are used to select the operations you want Using other values results in unpredictable behavior m opcode 2 and CRm fields SHOULD BE ZERO except when the values specified are used to select the behavior you want Using other values results in unpredictable behavior Terms and This table lists the terms and abbreviations used in the CP15 registers and abbreviations explanations Abbreviation Description UNPREDICTABLE UNP For reads The data returned when reading from this location is unpredictable and can have any value For writes Writing to this location causes unpredictable behavior or an unpredictable change in device configuration UNDEFINED UND An instruction that accesses CP15 in the manner indicated takes the UNDEFINED instruction exception SHOULD BE ZERO SBZ When writing to this field all bits of the field SHOULD BE ZERO SHOULD BE ONE SBO When writing to this location all bits in this field SHOULD BE ONE SHOULD BE ZE
8. 58 GPIO Configuration Register 36 59 GPIO Configuration Register 7 59 GPIO Configuration Register 8 60 GPIO Configuration Register 39 60 GPIO Configuration Register 480 61 GPIO Configuration Register 481 61 GPIO Configuration Register 12 62 GPIO Configuration Register 13 62 GPIO Configuration Register 14 63 GPIO Configuration Register 15 63 GPIO Configuration Register 16 64 GPIO Configuration Register 17 64 GPIO Configuration Register 18 65 GPIO Configuration Register 19 65 GPIO Configuration Register 20 66 GPIO Configuration Register 21 66
9. 97 operation instructions 2 2 2 97 Modified virtual address format MVA 98 R9 Cache Lockdown register 00 98 eS LUCES 98 Instruction or data lockdown register 99 ACCESS INSEFUCTIONS RET 99 Modifying the Cache Lockdown 5 99 Register format iecore ate rte ah achiev 99 Cache Lockdown register 99 Lockdown cache Specific loading of addresses into a cache way 100 Cache unlock procedure eoe user tud 101 R10 TLB Lockdown register 101 101 101 invalidate 2 2 2 101 Programming mmn 102 Sample code SEQUENCE 102 Ril R12 registers eue er oet tob du HE 102 R13 Process ID register 102 FCSE PID register cia reru TA 103 www digiembedded c
10. 256 13 Static Memory Write Delay 0 3 2 257 StaticMemory Turn Round Delay 0 3 registers 258 Chapter 6 Ethernet Communication Module 261 TT 261 COMMON 5 2 gt 24 52 261 Ethernet communications module 262 Ethernet cmm 262 MAC module block diagram 263 module features 263 PHY interface 1 5 mens 264 Station address logie 5 ei n Ce 264 receive RR 265 Statistics mod le 265 Ethernet front end module 266 Ethernet front end module EFE 266 Receive packet processor 266 Transmit packet 267 Receive packet processor 4 1 eee 267 Power dowr mode eot ete id p tuae d 267 Transferring a frame to system 268 Receive buf
11. Signal U D OD Description 10 data mask 3 4 byte enable data 31 24 B11 data_mask 2 4 Byte enable data 23 16 10 data mask 1 4 Byte enable data 15 08 data mask 0 4 Byte enable data 07 00 A9 ns ta strb I Slow peripheral transfer acknowledge A6 n 4 Transfer direction B7 clk en 3 4 SDRAM clock enable D7 en 2 4 SDRAM clock enable 7 clk en 1 4 SDRAM clock enable B8 clk en 0 4 SDRAM clock enable B4 cs 7 4 Chip select 7 cs3 A3 cs 6 4 Chip select 6 st cs3 A4 cs 5 4 Chip select 5 dy cs2 C5 cs 4 4 Chip select 4 st cs2 B5 cs 3 4 Chip select 3 dy csl B6 cs 2 4 Chip select 2 st cs1 Flash boot D6 ces 1 4 Chip select 1 dy cs0 Boot sdram C6 cs 0 4 Chip select 0 st 0 C4 ras n 4 SDRAM RAS A2 cas n 4 SDRAM CAS C7 wen 4 SDRAM write enable B3 10 4 SDRAM A10 AP 8 st oe n 4 Static output enable a addr 27 24 reset to gpio mode These address lines cannot be used for boot b gpio 31 16 reset to memory data bus data 15 0 Ethernet interface MAC Description A12 mdc gpio 32 U IO 2 MII clock D11 mdio gpio 35 U 2 data B12 gpio 33 U VO 2 TX clock 16 txd 3 gpio 47 U 2 TX data 3 30 Hardware Reference NS9215 265 General purpose I O GPIO U D 1 0 Description
12. Code Master slave Description 0x0 NO_IRQ N A No interrupt active 0 1 ARBIT LOST Master Arbitration lost the transfer has to be repeated 0 2 M No acknowledge by slave 0x3 M TX DATA Master TX data required in register TX DATA 0 4 Master RX data available in register RX DATA 0 5 M CMD ACK Master Command acknowledge interrupt 0x6 N A N A Reserved 0 7 N A Reserved 0x8 S RX ABORT Slave The transaction is aborted by the master before the slave performs a NO ACK 0 9 S REQ Slave Command request 5 Slave No acknowledge by master TX DATA REG is reset 455 2 MASTER SLAVE INTERFACE Code Master slave Description OxB S TX DATA IST Slave TX data required in register TX DATA first byte of transaction 0 S RX DATA IST Slave RX data available in register RX DATA first byte of transaction 0XD S TX DATA Slave TX data required in register TX DATA OxE S RX DATA Slave RX data available in register RX DATA 0 5 Slave General call address Software driver 2 master software driver slave high level driver The 12C master software driver uses three commands only M READ to start a read sequence M WRITE to start a write sequence M STOP to give up the IC bus If during a read or write sequence another M READ M WRITE is requested by the ARM CPU a
13. 360 Processing flow diagram ient derer enn e ERE RP A 360 ee Buc M 360 Jerez 361 Processing 361 Chapter 9 Hub Module 363 Block diagrami snimate 364 AHB slave 2 2 meme 364 cen 364 Servicing and FIEOS cree rick c d pete 364 Buffer descripEOrs eec tu exti 365 Source address pointer isses mmn 365 Buffer lengthy iii ida cies EAS 365 Control 15 W eee rer e rrr ie etr ede ee 365 Controll TA E eta states 365 Control etre nd aea e ete a rot ud et t 365 C ntroll Pls T 365 Controll RET 366 Status 15 0 366 Transmit 367 diet 367 Vista example nirien EE 368 Control and status register address 368 UART A register address 369 UART B register address 369 UART C register address map
14. 140 Address decoding c t t d ERE EE ANE E EET ERO AREA DES 141 Programmable 142 Software watchdog timer 1 142 General purpose timers counters isses meme 143 Source clock frequency coser cen 143 GPTC characteristics ear e ute irs 143 enin Bm 143 l6 bit mode esee db e LU ERE ME 144 Basic PWM function eene ee eene 144 Functional block 2 2 2 144 Enhanced PWM RR DII ei Diui ted 145 Sample enhanced PWM waveform 145 Quadrature decoder tetas 145 How the quadrature decoder counter 146 Provides input signals eene i dae eR 146 Monitors how far the encoder has 147 seti 147 Testing EXEC 147 5 ITER EE PIE PR 147 Interrupt controller 148 FIQ interr Upi 148 IRO intel
15. P4 agnd ref adc tie to ground P5 VREF adc tie to ground T2 vss adc tie to ground N6 vdd adc tie to 3 3V R4 vinO adc tie to ground T3 vinl adc tie to ground R5 vin2 adc tie to ground U2 vin3 adc tie to ground T4 vin4 adc tie to ground U3 vin5 adc tie to ground T5 vin6 adc tie to ground 04 vin7 adc tie to ground www digiembedded com 49 265 POR and battery backed logic POR and battery backed logic 50 Description M3 por_gnd reg POR reference ground N2 por_vss POR VSS por vdd POR VDD 3 3V L3 por reference POR reference trip voltage 2 74V min 2 97V max por early reference POR early power loss voltage 1 19V min 1 28V max bat vdd Battery VDD 3 0V aux comp Auxiliary analog comparator input trip point 2 4V min 2 5V max N3 M4 bat vdd reg Battery regulated core VDD 1 8V P3 por bypass U I POR bypass pull low to disable POR 14 por test POR analog test pin leave unconnected The POR will generate keep reset out n low between 75ms and 300ms after 3 3V reaches the POR reference trip voltage threshold The POR reference trip voltage is between 2 74V and 2 97V with hysteresis between 50mV and 80mV If the POR feature is not used and the RTC is used the inputs must be terminated as shown below M3 por gnd reg tie to ground N2 por vss tie to ground por vdd tie to 3 3V L3 por referen
16. 148 32 vector interrupt 22 1 2 27 2 148 IRQ characteristics tette tre tede RENE PAD 149 500 65 149 Vectored interrupt controller VIC 22222 2 2 1 151 Configurable system 1 151 PLE a 151 PLL configuration and control system block diagram 152 Bootstrap initializatlOn 152 Configuring the powerup 152 System configuration 0 0 0 0 0 0 2 154 Register address map nd ee ad 154 General Arbiter Control register 158 BRCO BRC1 BRC2 and BRC3 registers 158 Channel allocations 159 AHB Error Detect Status 1 eerie tee HI adieu lees 159 Hardware Reference NS9215 www digiembedded com AHB Error Detect Stats 2 eite esee dra ek cud uid ee 160 AHB Error Monitoring Configuration register 161 Timer Master Control register sss menn 162 T
17. RENE Rr PARAT AE 82 Thumb instruction set 82 instr ctiori Set b 83 System control processor 15 2 83 ARMO926EJ S system 83 Address manipulation 83 Accessing CP15 83 Terms and abbreviations 2 84 Register ien ER PUER 85 RO ID code and cache type status registers 86 ID COG Dm 86 Cache eset etit ened eed vu e Y LR eta 86 Cache type register and field description 87 Dsize and Isize fields petet ete ELEME 87 Control register socie ore EENE D P ERG 88 Control register 89 Bit functionality TRE 89 Hardware Reference NS9215 ICache and DCache 90 R2 Translation Table Base 5 91 Register T
18. 0 0 A wakeup 0 Do not wake on character match 1 Wake character match R W Enet 0x0 Ethernet wakeup 0 Do not wake on Ethernet packet Wake on Ethernet packet AHB Bus Activity Status Address A090 022C The AHB Bus Activity Status register is a read only register that determines the activity on the AHB bus Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Act stat Register bit assignment Bits Access Mnemonic Reset Description D31 00 R Act stat 0 0 Bus activity status Provides the CPU with the status of activity on the system bus excluding the CPU This register can be used to help determine when to enter sleep mode or to reduce the system clock frequencies The counter is reset each time a master accesses the AHB bus The counter will saturate at all 1s System Memory Chip Select 0 Dynamic Memory Base and Mask registers Addresses A090 0100 0104 190 Hardware Reference NS9215 Registers Register bit assignment SYSTEM CONTROL MODULE System Memory Chip Select 1 Dynamic Memory Base and Mask registers These control registers set the base and mask for system memory chip select 0 with a minimum size of 4K The powerup default settings produce a memory range of 0 0000 0000 OxOFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select O base CSOB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip select
19. 305 Receive multicast packet counter A060 0 8 305 Receive broadcast packet counter A060 06AC 305 Receive control frame packet counter A060 0680 305 Receive PAUSE frame packet counter A060 0684 305 Receive unknown OPCODE packet counter A060 06 8 305 Receive alignment error counter A060 O6BC 306 Receive code error counter A060 06 4 306 Receive carrier sense error counter A060 06 8 306 Receive undersize packet counter A060 306 Receive oversize packet counter A060 0600 306 Receive fragments counter A060 06D4 306 Receive jabber counter A060 0608 307 15 16 Transmit statistics counters address 307 Transmit byte counter A060 06 0 307 Transmit packet counter A060 06 4 308 Transmit multicast packet counter A060 06 8 308 Transmit broadcast packet counter A060 308
20. 110 First level 110 Page table nn 110 First level descriptor bit assignments Priority encoding of fault status 111 First level descriptor bit assignments Interpreting first level descriptor bits 111 Section 1 111 Section descriptor 0 0 00 4 4 1 111 Section descriptor bit 2 0 00 44 1 2 112 Coarse page table descriptor 112 Coarse page table descriptor 112 Coarse page table descriptor bit 112 Fine page table descriptor 112 Fine page table descriptor 113 Fine page table descriptor bit 113 Translating section references 113 Second level 2 4 114 Second level descriptor format 11
21. 315 B Buffer Descriptor Pointer register 315 C Buffer Descriptor Pointer register 316 D Buffer Descriptor Pointer register 316 Ethernet Interrupt Status register 317 Ethernet Interrupt Enable register sss 319 TX Buffer Descriptor Pointer register 320 Transmit Recover Buffer Descriptor Pointer register 321 TX Error Buffer Descriptor Pointer register 321 TX Stall Buffer Descriptor Pointer register 322 A Buffer Descriptor Pointer Offset 323 B Buffer Descriptor Pointer Offset 324 C Buffer Descriptor Pointer Offset 324 D Buffer Descriptor Pointer Offset 2 2 2 325 Transmit Buffer Descriptor Pointer Offset register 325 RX Free Buffer register ise XR ERA NER NERA EPIRI teens 326 Multicast Address Filter 4 4
22. ELE LE LI LILI LIL addr data Y pia 9 cs n st oe n DN VJ 212 Hardware Reference NS9215 Burst of zero wait states with fixed length Burst of two wait states with fixed length www digiembedded com MEMORY CONTROLLER Static memory read Timing and parameters WAITRD 0 WAITOEN 0 WAITPAGE N A WAITWR N A WAITWEN N A WAITTURN N A This diagram shows a burst of zero wait state reads with the length specified Because the length of the burst is known the chip select can be held asserted during the whole burst and generate the external transfers before the current AHB transfer has completed The first read requires five arbitration cycles the three subsequent sequential reads have zero AHB cycles added because the external transfers are automatically generated out addr Y Au Y e A C data D A 4 D A 8 D A C 4 st oe n Timing parameter WAITRD 0 WAITOEN 0 WAITPAGE N A WAITWR N A WAITWEN N A WAITTURN N A This diagram shows a burst of two wait state reads with the length specified The WAITRD value is used for all transfers in the burst 213 MEMORY CONTROLLER irs addr Y 4 8 data D A D A 4 st_oe_n Timing parameter WAITRD
23. 436 Available strapping 00 0 0 0 0 40 4 4 437 EEPROM FLASH header 437 Header 437 Time to completion esee e hee 438 SPI Control and Status 4 21 0 22 439 Register address map 439 SP Configuration register Dd 439 Clock Generation register sss meme ees 440 Register programming steps 441 Interrupt Enable register sss memes 441 Interrupt Status 2 2 2 2 442 SPI timing characteristics tert alas 443 SPI master timing diagram 444 SPI slave timing parameters 444 SPI slave timing diagram issssssssssssse mm nnn 445 Chapter 13 2 Master Slave 447 T D 447 Physical 2 bus ciet og t eh pak DR EE 447 Multi miaSter treten Cera SR I leu 448 I2C external additesses
24. R17 gpio 80 U 2 17 gpio 81 U IO 2 N16 gpio 82 U 2 7 gpio 83 U 2 M17 gpio 84 U 2 U N e L15 gpio 85 U 10 2 N 40 Hardware Reference NS9215 265 General purpose I O GPIO Description gpio 86 IO N 0 BUS 0 6 PIC 1 BUS 0 6 Ext Timer Event Out Ch 2 gpio 86 K16 gpio 87 PIC 0 BUS 0 7 0 PIC 1 BUS O 7 I O Ext Timer Event Out Ch 3 gpio 87 K14 gpio 88 IO PIC 0 BUS 0 8 I O PIC 1 BUS 0 8 I O Ext Timer Event Out Ch 4 gpio 88 4 gpio 89 VO PIC 0 BUS 0 9 PIC 1 BUS 0 9 Ext Timer Event Out Ch 5 gpio 89 16 gpio 90 0 BUS O 10 I O PIC 1 BUS O 10 I O Ext Timer Event Out Ch 6 gpio 90 15 gpio 91 PIC 0 BUS O 11 I O PIC 1 BUS O 11 I O Ext Timer Event Out Ch 7 gpio 91 F14 gpio 92 PIC 0 BUS 0 12 10 PIC 1 BUS 0 12 1 Ext Timer Event Out Ch 8 gpio 92 F16 gpio 93 IO PIC 0 BUS 0 13 I O PIC 1 BUS 0 13 I O Ext Timer Event Out Ch 9 gpio 92 E15 gpi0 94 0 BUS 0 14 I O PIC 1 BUS O 14 I O dup gpio 94 E16 gplo 95
25. addr 18 2 addr 18 2 addr 18 2 addr 18 2 20 0 131201 CE_n OE_n 2Mx32 ROM A 15 0 10 15 0 CE_n OE_n WE_n UB_n LB n A 15 0 10 15 0 CE_n OE_n WE_n UB_n LB n 64Kx16 SRAM A 16 0 IO 7 0 n OE n WE n A 16 0 IO 7 0 OE WE n A 16 0 IO 7 0 OE WE n A 16 0 IO 7 0 n OE n WE n 128Kx8 SRAM datat 31 0 data 31 16 data 15 0 data 31 24 data 23 16 data 15 8 data 7 0 data 31 0 MEMORY CONTROLLER Dynamic memory controller Dynamic memory controller Write protection Access sequencing and memory width Each dynamic memory chip select can be configured for write protection by setting the appropriate bit in the write protect P field on the Dynamic Memory Configuration register If a write access is performed to a write protected memory bank a bus error is generated The data width of each chip select must be configured by programming the appropriate Dynamic Memory Configuration register When the chip select data bus width is narrower than the transfer initiated from the current bus master the internal bus transfer takes several external bus transfers to complete If chip select 4 is configured as 16 bit wide memory for example and a 32 bit read is initiated the AHB bus stalls while the memory controller reads two consecutive words from memor
26. 203 RJ 203 Low power DL IUe SERVER CERA AERA LT TR 204 Low power SDRAM deep sleep 204 11 12 Low power SDRAM partial array refresh 204 Memory map PRI 205 Power on reset memory 205 Chip select 1 memory configuration sisse 205 Example Boot from flash SRAM mapped after boot 205 Example Boot from flash SDRAM remapped after boot 206 Static memory 207 Write 0 1 208 Extended wait transfers 208 Memory mapped 5 209 Static memory initializatlon cte a 209 Access sequencing and memory width 209 Wait state 1 00 000224 4 21 209 Programmable i attrita 210 Static memory read 1 210 Output enable programmable 210 ROM SRAM and 2 1 1
27. 217 External memory write transfer with two write enable delay states 217 Two external memory write transfers with zero wait states 218 Flash memory 218 Bus turnaround E 219 Bus turnaround Timing and 219 Read followed by write with turnaround csse 219 Write followed by a read with no 220 Read followed by a write with two turnaround 220 Byte lane COntFOl Reed Iota taa lal Cub ta TOP DRE E Dua 221 Address 2 212 222 Memory banks constructed from 8 bit or non byte partitioned memory devices Hardware Reference NS9215 www digiembedded com 222 Memory banks constructed from 16 or 32 bit memory devices 223 Dynamic memory controller esses eene 225 Write protection Tia 225 Access sequencing and memory 225 SDRAM Initialization oe aE prx E 225 Left shift value table 32 bit wide data bus SDRAM 226 Left shift value table 32 bit wide data bus SDRAM
28. 370 UART D register address map 370 SPI register address 371 AD register address map 371 371 2 register address 371 RESERVE Oi 371 RTC register address 372 Hardware Assist register address map 0 372 IO Hardware Assist register address map 1 372 register address map 0 20 4 0 4 07 7 2 372 IO register address map 1 2 22 202200 00202222 372 Module Interrupt and FIFO Status 5 372 www digiembedded com 19 20 Module 375 Module DMA RX Buffer Descriptor 376 Module Interrupt Configuration register 371 Module Direct Mode RX Status 378 Module Direct Mode RX Data FIFO
29. eneon tion Multicast address filtering example 2 Notes To accept multicast packets with destination addresses in the range of 0x01_00_5E_00_00_00 to 0x01 00 5E 00 00 Of using entry 4 the registers set as shown Register Function MFILTEN 0 10 Enable entry 4 MFILTL4 0 5 00 00 00 Lower 32 bits of multicast address MFILTH4 0x01_00 Upper 16 bits of multicast address MCMSKL4 OxFFFF 0 Include only bits 31 04 of the lower 32 bits of the multicast address in the comparison MCMSKH4 OxFFFF Include all of the upper 16 bits of the multicast address in the comparison m of the address filter entries are enabled the SAL must be set to accept all multicast packets by setting the PRM bit in the Station Address Filter register m Runt packets that are less than 6 bytes and therefore do not have a valid destination address are automatically discarded by the multicast address filtering logic Clock synchronization Writing to other registers The multicast filtering logic resides in the RX CLK domain but all of the registers are controlled in the AHB clock domain To provide traditional dual rank clock synchronization flops for each bit of the five Multicast Address Filter registers consumes a large amount of gates Therefore the logic is designed such that only the MFILTEN register bits are synchronized and when these bits are cleared changes in the other
30. write 5 Writing ADDR REQ is not required if the device address is not changed Read on a non existing slave Do not wait for the slave to perform a No ACK STATUS REG and RX DATA REG are read simultaneously 457 Slave module normal mode 16 bit 458 2 MASTER SLAVE INTERFACE Flow charts S RX DATA 1ST irq wait irq read rx status N S ABO S RX DATA irq write cmd S NOP write cmd S STOP wait irq read rx status S TX DATA 1ST irq 2 write cmd S NOP lt 4 write TX DATA REG wait irq read status 5 5 N Note STATUS REG and RX DATA REG are read simultaneously Hardware Reference NS9215 Real Time Clock Module T E 1 4 functionality Real Time Clock module tracks the time of the day to accuracy of 10 milliseconds and provides calendar functionality that tracks day month and year RTC monitors these time periods Year from 1900 2999 Month from 1 12 Date from 1 28 29 30 or 31 as a function of year and month Day of week from 1 7 Hour from 0 23 or from 1 12 with the AM PM flag set Minute from 0 59 Second from 0 00 59 99 RTC functionality also provides an alarm register that allows compa
31. 293 Maximum Frame register 2 1 1 1 een 294 MII Management Configuration register 295 Clocks field 5 0 00 mni 296 MII Management Command 5 296 MII Management Address register 297 MII Management Write Data 5 298 MII Management Read Data register 298 MII Management Indicators 2 0 44 299 Station Address registers sss mmm enn 300 Station Address Filter register 301 RegisterHash Tables reete heit riae ern aate 302 ig 302 303 Statistics registers die 303 Combined transmit and receive statistics counters address map 303 Receive statistics counters address 304 Receive byte counter A060 069 304 Receive packet counter A060 06A0 304 Receive FCS error counter A060
32. Launch Edge SIN SOUT SPI Model and Mode2 functional timing CS Modet Mode aK bd Mode 1 Mode Launch Edge 7 Capture Edge SIN SOUT 435 SERIAL CONTROL MODULE SPI SPI clock generation Clock generation samples In SPI master mode In SPI slave mode The reference clock for the SPI module is the system PLL output This clock is a nominal 300 MHz m SPI master mode the clock is divided down to produce the required data rate m SPI slave mode the divided down clock recovers the input SPI clock SPI clock generation is specified using the Clock Generation register These are some examples of clock generation Interface Type Data rate DIVISOR Master 33 Mbps 0x009 Master 20 Mbps 0 00 Master 5 Mbps 0x03C Master 500 Kbps 0x258 Slave all 0x006 In SPI master mode the value programmed in the DIVISOR field must always be rounded up to the next whole integer For example if the required data rate is 14 Mbps the calculation is 300 14 or 21 43 m The value programmed in the DIVISOR field would be 0x016 m The actual data rate would be 13 64 Mbps m general equation is DIVISOR round Up PLL output interface data rate In SPI slave mode the value programmed in the DIVISOR field should always be 0x006 The SPI slave mode data rate is determined by the frequency of the input clock provided by the external SPI
33. RDL A070 0048 DynamictRC Dynamic Memory Active to Active Command Period tgo A070 004C DynamictRFC Dynamic Memory Auto Refresh Period and Auto Refresh to Active Command Period A070 0050 DynamictXSR Dynamic Memory Exit Self Refresh to Active Command tsp A070 0054 DynamictRRD Dynamic Memory Active Bank A to Active B Time 070 0058 Dynamic Memory Load Mode register to Active Command Time A070 0080 StaticExtendedWait Static Memory Extended Wait A070 0100 DynamicConfig0 Dynamic Memory Configuration Register 0 A070 0104 DynamicRasCas0 Dynamic Memory RAS and CAS Delay 0 A070 0120 DynamicConfigl Dynamic Memory Configuration Register 1 A070 0124 DynamicRasCas1 Dynamic Memory RAS and CAS Delay 1 A070 0140 DynamicConfig2 Dynamic Memory Configuration Register 2 A070 0144 DynamicRasCas2 Dynamic Memory RAS and CAS Delay 2 A070 0160 DynamicConfig3 Dynamic Memory Configuration Register 3 A070 0164 DynamicRasCas3 Dynamic Memory RAS and CAS Delay 3 A070 0200 StaticConfig0 Static Memory Configuration Register 0 A070 0204 StaticWaitWen0 Static Memory Write Enable Delay 0 A070 0208 StaticWaitOen0 Static Memory Output Enable Delay 0 A070 020C Static WaitRdO Static Memory Read Delay 0 A070 0210 Static WaitPage0 Static Memory Page Mode Read Delay 0 A070 0214 StaticWaitWr0 Static Memory Write Delay 0 A070 0218 StaticWaitTurn0 Static Memory Turn Round Delay 0 A070 0220 StaticConfigl Stat
34. 000022 1 4 41 406 UART Baud Rate Divisor 6 000 0702 2 2 0 20 teens 406 UART Interrupt Enable 407 UART Interrupt Identification register 408 Hardware Reference NS9215 www digiembedded com UART FIFO Control 0 00 0 409 UART Line Control geo Lures eot ae dd 409 UART Modem Control register 7 1 4 4 4 2 411 UART Line Status register ecce reed 411 UART Modem Status register sess meme 412 Chapter 11 Serial Control Module HDLC 415 HDEC module strU CEUre eoec oe ederet nte ere Pot t ed 415 Receive and transmit 2 22 415 Receive operatori a ad 416 Transmit operation bak ar es 416 Transmitter undertow 111 eei e d Pr 416 ee n O 416 p 416 Last byte bit pattern table 417 Data 417 Encoding
35. 469 Interrupt Enable Status 222222222 470 General Status register 1 21 2 2 471 Chapter 15 Analog to Digital Converter ADC Module 473 dlc P 473 ADC module struck re iue oreet tete restent taret ta rb e o 473 control block oorr 474 ADC DMA xu tres 474 ADC control and status lt 475 Register address 475 23 ADC Configuration 1 0 00 475 ADC Clock Configuration register 477 ADC Output Registers 0 7 0 00 477 Chapter 16 Timing rir or I err he ra a 479 Electrical 22 2 479 Absolute maximum 6 nen 479 Recommended operating 480 Power diSsipatlOn deutet us cxli tremenda pepe beue sena 480 DC electrical characteristics esses 481 yep i a 481 cR 482 Reset and edge sen
36. WAITRD N A WAITOEN N A WAITPAGE N A WAITWR 2 WAITWEN 0 WAITTURN N A This diagram shows a single external memory write transfer with two write enable delay states WAITWEN 2 One wait state is added 1 ux Y X data D A y en X Fc st we n ANE 217 MEMORY CONTROLLER Static memory Write Timing and parameters Two external memory write transfers with zero wait states Flash memory WAITRD N A WAITOEN N A WAITPAGE N A WAITWR 2 WAITWEN 2 WAITTURN N A This diagram shows two external memory write transfers with zero wait states WAITWR 0 Four AHB wait states are added to the second write because this write can be started only when the first write has completed This is the timing of any sequence of write transfers nonsequential to nonsequential or nonsequential to sequential with any value of HBURST The maximum speed of write transfers is controlled by the external timing of the write enable relative to the chip select so all external writes must take two cycles to complete the cycle in which write enable is asserted and the cycle in which write enable is deasserted out addr A 0 4 data DA cs n st 521 NE WAITRD N A WAITOEN N A WAITPAGE N A WAITWR 0 WAITWEN
37. D07 R W1TC R W1TC MATCHO DSR Character match0 Indicates that a receive character match has occurred against the Receive Match register 0 Data set ready Indicates that a state change has occurred on input signal DSR D06 R W1TC DCD Data carrier detect Indicates that a state change has occurred in input signal DCD D05 R W1TC CTS Clear to send Indicates that a state change has occurred on input signal CTS D04 R W1TC RI Ring indicator Indicates that a state change has occurred on input signal RI D03 R W1TC TBC Transmit buffer close Indicates that transmission of the last byte in a transmit buffer has completed D02 www digiembedded com R W1TC Receive buffer close Indicates that a UART receive buffer close condition has occurred These are UART receive buffer close events Receive character match Receive character gap timeout Receive line break Receive framing error d UN Receive parity error 397 SERIAL CONTROL MODULE UART Receive Character GAP Control register Reset 0 Description Transmit idle Indicates that the transmitter has moved from the active state to the idle state The transmitter moves from the active state to the idle state when the transmit FIFO is empty and the transmitter is not actively shifting out data Bits Access Mnemonic D01 TX IDLE D00 R WITC IDLE 0 R
38. 0 0 1 Writing to register RO is UNPREDICTABLE R0 ID code is a read only register that returns the 32 bit device ID code You can access the ID code register by reading CP15 register RO with the opcode 2 field set to any value other than 1 or 2 Note this example 0 Rd c0 0 3 7 returns ID This is the contents of the ID code register Bits Function Value 31 24 ASCII code of implementer trademark 0x41 23 20 Specification revision 0x0 19 16 Architecture ARMv5TEJ 0x6 15 4 Part number 0x926 3 0 Layout revision 0x0 R0 Cache type is a read only register that contains information about the size and architecture of the instruction cache ICache and data cache DCache enabling operating systems to establish how to perform operations such as cache cleaning and lockdown See Cache features on page 127 for more information about cache 86 Hardware Reference NS9215 WORKING WITH THE CPU ID code and cache type status registers You can access the cache type register by reading CP15 register RO with the opcode 2 field set to 1 Note this example 15 0 Rd 1 returns cache details Cache type register and field i 38 description Field Description Ctype Determines the cache type and specifies whether the cache supports lockdown and how it is cleaned Ctype encoding is shown below all unused values are reserved Value 0b111
39. 258 Hardware Reference NS9215 Register bit assignment www digiembedded com MEMORY CONTROLLER StaticMemory Turn Round Delay 0 3 registers Bits Access Mnemonic Description D31 04 N A Reserved N A do not modify D03 00 R W WTTN Bus turnaround cycles WAITTURN 00000 11110 n 1 clk out turnaround cycles where bus turnaround time is WAITTURN 1 telk out 1111 16 out turnaround cycles reset value on reset n To prevent bus contention on the external memory databus the WAITTURN field controls the number of bus turnaround cycles added between static memory read and write accesses The WAITTURN field also controls the number of turnaround cycles between static memory and dynamic memory accesses 259 MEMORY CONTROLLER StaticMemory Turn Round Delay 0 3 registers 260 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Ethernet Communication Module E R Ethernet Communication module consists of an Ethernet Media Access Controller MAC and Ethernet front end module The Ethernet MAC interfaces to an external PHY through the industry standard interface Media Independent Interface MII The Ethernet front end module provides all of the control functions to the MAC Features The Ethernet MAC module provides the following m Station address logic SAL Statistics module mw Interface to MII Media Independent Interface PHY The Ethernet front end module doe
40. D03 R W Int Sel 0x0 Interrupt select 0 Interrupt disable Generate IRQ D02 R W Up Down 0 0 Up Down select 0 Up counter 1 Down counter Dol R W Bit timer 0x0 32 or 16 bit timer 0 16 bit timer 1 32 bit timer R W Rel Enbl 0x0 Reload enable 0 Halt at terminal count The timer must be disabled then enabled to reload the timer when the terminal count is reached Reload and resume count at terminal count Timer 6 9 High registers Addresses A090 0078 007 0080 0084 The Timer 6 9 High registers contains the high registers for the enhanced PWM features available in timers 6 through 9 170 Hardware Reference NS9215 SYSTEM CONTROL MODULE Timer 6 9 Low registers Register 31 30 29 2 2 26 25 24 23 22 21 20 19 18 17 16 High 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 High Register bit assignment Bits Access Mnemonic Reset Description D31 00 R W High 0x0 The PWM output toggles high when the timer counter reaches this value Timer 6 9 Low registers Addresses A090 0088 008C 0090 0094 The Timer 6 9 Low registers contain the low registers for the enhanced PWM features available in timers 6 through 9 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Low 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Low Register bit assignment Bits Access Mnemonic Reset Description D31 00 R W Low 0x0 The PWM output toggles low when the timer counter reaches this value
41. Way SBZ Set index Word SBZ wm Sare the base two logarithms of the associativity and the number of sets m set way and word files define the format For all of the cache operations word SHOULD BE ZERO For example a 16 KB cache 4 way set associative 8 word line results in the following m log associativity 2log54 2 m S log NSETS where NSETS cache size in bytes associativity line length in bytes NSETS 16384 4 32 128 Result S 100 128 27 The test and clean DCache instruction provides an efficient way to clean the entire DCache using a simple loop The test and clean DCache instruction tests a number of lines in the DCache to determine whether any of them are dirty If any dirty lines are found one of those lines is cleaned The test and clean DCache instruction also returns the status of the entire DCache in bit 30 96 Hardware Reference NS9215 Test clean and invalidate DCache instruction WORKING WITH THE CPU R6 TLB Operations register Note The test and clean DCache instruction p15 0 r15 c7 10 3 is a special encoding that uses r15 as a destination operand The PC is not changed by using this instruction however This instruction also sets the condition code flags If the cache contains any dirty lines bit 30 is set to 0 If the cache contains no dirty lines bit 30 is set to 1 Use the following loop to clean the entire cache tc lo
42. Module Interrupt and FIFO Status register Addresses 9000 0000 9000 8000 9001 0000 9001 8000 9002 0000 9002 8000 9003 0000 9003 8000 The Interrupt and FIFO Status register allows software to determine the cause of the current low speed peripheral interrupts and to clear the interrupt bit Note An access type of R W means that the processor must write 1 to clear the value if the read value is 1 If the read value is 0 the write value must be 0 372 Hardware Reference NS9215 3 March 2008 Register 31 3 2 27 HUB MODULE Module Interrupt and FIFO Status register 2 20 20 19 18 17 16 RXC AP RXPS DN RAS RFS RAS 5 RP RP IP 15 Register bit assignment Bit s D31 4 13 AFO ful 55 R W 12 11 AFO ful Mnemonic RXNCIP Reset 0x0 Description Normal completion interrupt pending RX Set when a buffer is closed under normal conditions An interruptis generated when the I bit is set in the current buffer descriptor A normal DMA completion occurs when the buffer length field expires D30 R W RXECIP 0x0 Error completion interrupt pending RX Set when the DMA channel finds either a bad buffer descriptor or a bad data buffer pointer The DMA channe
43. Register bit assignment Bits Access Mnemonic Reset Description D31 R W ENABLE 0 Enable character match Write 1 to enable the receive character match control logic D30 24 R Not used 0x0 Write this field to 0 D23 16 R W MASK 0 0 Mask Allows you to not include specific bits in the receive character match operation Writing 1 masks off the bit in the specified position Bit positions that are not used should always be masked For example bit positions 9 through 12 should always be masked for 8 bit characters D15 08 R Not used 0x0 Write this field to 0 D07 00 R W DATA 0x0 Data Allows you to specify the receive characters to match against Receive Character Based Flow Control register Address 9001 1028 9001 9028 9002 1028 9002 9028 The Receive Character Based Flow Control register lets you define the UART module s receive character based flow control operation Use this register in conjunction with the Receive Character Match Control registers to define the flow control characters If enabled this function s output is wired to the UART module instead of the CTS signal 400 Hardware Reference NS9215 SERIAL CONTROL MODULE UART Receive Character Based Flow Control register Caution Be aware that if multiple matches occur an XOFF assertion will supersede an XON assertion Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN ABLE Not used MASK 15 14 13 12 11 10 9
44. 417 Digital phase locked loop DPLL operation Encoding 418 I up MEUM 418 DPLL tracked bit cell 0 2 2 419 NRZ data 74 0 0 122 419 Biphase data encoding ole ded tu re e Foren ee ted 419 DPLL operation Adjustment ranges and output 5 419 NRZ encoding 4 0 4 0700700 0111111 420 Biphase Level 0 420 Biphase Mark Biphase Space encoding 421 IRDA compliant encode 421 Normal mode 421 Example 22222 2 2 menm 421 Wrapper HDLC Control and Status 422 Register address 422 Wrapper Configuration 1 lt 422 Interrupt Enable register nenne 424 Interrupt Status register iius ect be atrio 425 HDLC Data Register 1 2 00 0000 0 44 471 14 1 4
45. ARM926E S processor is targeted at multi tasking applications in which full memory management high performance low die size and low power are important The ARM926E S processor supports the 32 bit ARM and 16 bit Thumb instructions sets allowing you to trade off between high performance and high code density The processor includes features for efficient execution of J ava byte codes providing ava performance similar to J IT but without the associated overhead The ARM926EJ S supports the ARM debug architecture and includes logic to assist in both hardware and software debug The processor has a Harvard cached architecture and provides a complete high performance processor subsystem including m 926 S integer core m Memory Management Unit MMU see MemoryManagement Unit MMU beginning on page 105 for information m Separate instruction and data AMBA AHB bus interfaces 81 WORKING WITH THE CPU Arm926EJ S This drawing shows the main blocks in the ARM926E S processor process block diagram DEXT Write buffer DCACHE Cache writeback PA write TAGRAM buffer AHB interface WDATA LDA Bus interface unit ARM926EJ S Instruction AHB interface IROUTE Instruction sets The processor executes three instruction sets m 32 bit ARM instruction set m 16 bit Thumb instruction set m 8 0 J ava instruction set ARM instruct
46. Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1127 1255 1511 WAX Reserved Abe 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bi ES RMC GIRAF uU Reve RCD m RUN a a UB Reve Register bit assignment Bits Access Mnemonic Reset Description D31 R C C164 0 Carry register 1 TR64 counter carry bit D30 R C C1127 0 Carry register 1 TR127 counter carry bit D29 R C C1255 0 Carry register 1 TR255 counter carry bit D28 R C C1511 0 Carry register TR511 counter carry bit D27 R C CIIK 0 Carry register 1 TR1K counter carry bit D26 R C CIMAX 0 Carry register 1 TRMAX counter carry bit D25 R C 0 Carry register 1 TRMGV counter carry bit D24 17 N A Reserved N A N A D16 R C CIRBY 0 Carry register 1 RBYT counter carry bit D15 R C 0 Carry register 1 RPKT counter carry bit D14 R C 0 Carry register 1 RFCS counter carry bit D13 R C CIRMC 0 Carry register RMCA counter carry bit D12 R C CIRBC 0 Carry register RBCA counter carry bit D11 R C 0 Carry register 1 RXCF counter carry bit D10 R C CIRXP 0 Carry register 1 RXPF counter carry bit D09 R C CIRXU 0 Carry register 1 RXUO counter carry bit D08 R C CIRAL 0 Carry register 1 RALN counter carry bit D07 N A Reserved N A N A D06 R C CIRCD 0 Carry register 1 RCDE counter carry bit D05 R C CIRCS 0 Carry register 1 RCSE counter carry bit D04 R C CIRUN 0 Carry register 1 RUND counter carry register D03 R C CIROV 0 Carry register
47. www digiembedded com WN PIC 0 BUS O 15 I O PIC 1 BUS O 15 I O QDC Q dup gpio 95 41 265 Description C16 gpio 96 U LO 2 PIC 0 BUS 01 0 PIC 1 BUS 0 CAN RXD I dup gpio 96 PIC 0 BUS PIC 1 BUS PIC 0 CAN TXD O dup gpio97 16 gplo 97 U 2 N D15 gpio 98 U 2 PIC 0 BUS I 2 I O PIC 1 BUS 1 2 1 O 1 CAN RXD I dup gpio 98 PIC 0 BUS I 3 I O PIC 1 BUS 1 3 I O PIC 1 CAN TXD O dup gpio 99 PIC 0 BUS 1 41 0 0 PIC 1 BUS I 4 I O PWM Ch4 gpio 100 E8 gpio 99 U 2 D8 gpio 100 U IO 2 C8 gpio 101 U 2 PIC 0 BUS 1 51 1 0 PIC 1 BUS 1 5 I O Ext Int Ch 3 dup gpio 101 PIC 0 BUS 1 6 I O PIC 1 BUS 1 6 I O PC SCL dup gpio 102 E6 gpio 102 U IO 4 5 gpio 103 U UO 4 PIC 0 BUS 1 7 I O 1 BUS 1 SDA dup gpio 103 R12 gpio a 0 U IO 4 addr 24 SCL dup Ext Int Ch 0 dup gpio a 0 Boot width 1 015 gpio a 1 U IO 4 addr 25 SDA dup Ext Int Ch 1 dup Ext Int Ch 0 WN N 42 Hardware Reference NS9215 265 System clock Pin Signal U D OD Description 14 gpio a 2 U IO 4 0 addr 26 Reserved 1 cs0 we n 2 ExtInt Ch 2 dup 3 gpio a 2 SPI boot
48. www digiembedded com 171 SYSTEM CONTROL MODULE Timer 6 9 High and Low Step registers Timer 6 9 High and Low Step registers Addresses A090 0098 009C 00A0 00A4 The Timer 6 9 High and Low Step registers contain the high and low step registers for the enhanced PWM features available in timers 6 through 9 Register 31 30 2 7 26 25 24 23 22 21 20 19 18 17 16 Hi Step Hi Step Dir 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register bit assignment Bits Access Mnemonic Reset Description D31 R W Hi Step Dir 0x0 High step direction 0 Subtract the high step value from the original high register value to increase the high time 1 Add the high step value to the original high register value to decrease the high time D30 16 R W Hi Step 0x0 High step This value is either added or subtracted from the original high register value once each cycle D15 R W Lo Step Dir 0x0 Low step direction 0 Subtract the low step value from the original low register value to increase low time 2 1 Add the low step value to the original low register value to decrease low time 2 D14 00 R W Lo Step 0x0 Low step This value is either added or subtracted from the original low register value once each cycle Timer 6 9 Reload Step registers Addresses A090 00A8 00AC 0080 0084 The Timer 6 9 reload Step registers contain the reload step registers for the enhanced PWM features available in timers 6 through 9
49. 01 165 10 32bit 11 Reserved The value of the chip select 1 memory width field on power on reset reset n is determined by the gpio a 0 addr 23 signal This value can be overridden by software Note For chip select 1 the value ofthe gpio a 0 addr 23 signal is reflected in this field When programmed this register reflects the last value written into it Note Synchronous burst mode memory devices are not supported StaticMemory Write Enable Delay 0 3 registers Address A070 0204 0224 0244 0264 The Static Memory Write Enable Delay 0 3 registers allow you to program the delay from the chip select to the write enable assertion The Static Memory Write Enable Delay register is used in conjunction with the Static Memory Write Delay registers to control the width of the write enable signals It is recommended that these registers be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WWEN 254 Hardware Reference NS9215 MEMORY CONTROLLER Static Memory Output Enable Delay 0 3 registers Register bit assignment Bits Access Mnemonic Description D31 04 N A Reserved N A do not modify D03 00 R W WWEN Wait write enable WAITWEN 0000 One outcycle delay be
50. D31 16 R Default 0x0000 0000 D15 00 R W Default 0x0000 0000 Address A060 D31 16 R Default 0x0000 0000 D15 00 R W Default 0x0000 0000 Address A060 D31 16 R Default 0x0000 0000 330 Hardware Reference NS9215 MFMSKLA MFMSKLS5 MFMSKL6 MFMSKL7 Reserved read as 0 5 Reserved read as 0 MFMSKHI Reserved read as 0 MFMSKH2 Reserved read as 0 MFMSKH3 Reserved read as 0 Multicast High Address Mask Register 5 Multicast High Address Mask Register 6 Multicast High Address Mask Register 7 ETHERNET COMMUNICATION MODULE Multicast Address Filter Enable register D15 00 R W Default 0x0000 0000 MFMSKH4 Address A060 4 D31 16 R Default 0x0000 0000 Reserved read as 0 D15 00 R W Default 0x0000 0000 MFMSKH5 Address A060 0AB8 D31 16 R Default 0x0000 0000 Reserved read as 0 D15 00 R W Default 0x0000 0000 MFMSKH6 Address A060 OABC D31 16 R Default 0x0000 0000 Reserved read as 0 D15 00 R W Default 0x0000 0000 MFMSKH7 Multicast Address Filter Enable register Register www digiembedded com Address A060 The Multicast Address Filter Enable register individually enables each of the eight entries in the multicast address filter logic For an explanation of the synchronization scheme used for this register see Clock synchronization on page 276 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1
51. Date event has occurred D03 Hour Evnt 0x0 Hour event 0 Hour event has not occurred 1 Hour event has occurred D02 Min Evnt 0x0 Minute event 0 Minute event has not occurred Minute event has occurred Evnt 0 0 Second event 0 Second event has not occurred Second event has occurred D00 R R Hsec Evnt 0x0 Hundredth of a second event 0 Hundredth second event has not occurred Hundredth second event has occurred 467 REAL TIME CLOCK MODULE Interrupt Enable register Address 9006 0020 The Interrupt Enable register sets which events can generate and interrupt The interrupt that is generated remains set until it is cleared by disabling the event or by reading clearing the Event Flags register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Alrm Mnth Date Hour Min Sec Hsec Reserved Int Int Int Int Int Int Int Register bit assignment Access Mnemonic Description D31 07 N A Reserved N A N A D06 W Alrm Int 0x0 Alarm interrupt 0 Disable alarm interrupt Enable alarm interrupt D05 W Mnth Int 0x0 Month interrupt 0 Disable month interrupt Enable month interrupt D04 Date Int 0x0 Date interrupt 0 Disable date interrupt Enable date interrupt D03 W Hour Int 0x0 Hour interrupt 0 Disable hour interrupt Enable hour interrupt D02
52. ERXINT Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FT Not RXSH used GN HST 279 ETHERNET COMMUNICATION MODULE Ethernet General Control Register 1 Register bit assignment Bits Access Reset Description D31 R W ERX 0 Enable RX packet processing 0 Reset RX 1 Enable RX Used as a soft reset for the RX When cleared resets all logic in the RX and flushes the FIFO The ERX bit must be set active high to allow data to be received from the MAC receiver D30 R W ERXDMA 0 Enable receive DMA 0 Disable receive DMA data request use to stall receiver 1 Enable receive DMA data request Must be set active high to allow the RX_RD logic to request the AHB bus to DMA receive frames into system memory Set this bit to zero to temporarily stall the receive side Ethernet DMA The RX_RD logic stalls on frame boundaries D29 N A Reserved N A N A D28 R W ERXSHT 0 Accept short lt 64 receive frames 0 Do not accept short frames 1 Accept short frames When set allows frames that are smaller than 64 bytes to be accepted by the WR logic ERXSHT is typically set for debugging only D27 24 R W Not used 0 Always write as 0 D23 R W ETX 0 Enable TX packet processing 0 Reset TX Enable TX Used as a soft reset for the TX When cleared resets all logic in the TX and flushes the FIFOs ETX must be set active high to allow da
53. SERIAL CONTROL MODULE UART Serial Control Module UART Features www digiembedded com E 1 0 processor ASIC supports four independent universal asynchronous receiver transmitter UART channels A through D Each channel supports several modes conditions and formats DMA transfers to from system memory Independent receive and transmit programmable bit rate generators High speed data transfer up to 1 8432 Mbps Programmable data format 5 to 8 data bits Odd even or no parity 1 or 2 stop bits MSB or LSB first Programmable channel modes Normal Local loopback Remote loopback Modem control signal support RTS CTS DSR DCD RI Maskable interrupt conditions Receiver idle Transmitter idle Receive error conditions Character gap timeout Character match events CTS DSR DCD RI state change detection m 5485 transceiver control signal Transmit FIFO bypass to force out a character 385 SERIAL CONTROL MODULE UART UART module structure status 6 0 Normal mode operation The UART achieves normal mode operation by programming the UART and Wrapper configuration registers Example This example shows a normal mode operation configuration for a hyperterminal configuration application Any field not specified in this table can be left at reset value Control register Field VELOT Comment UART
54. These registers allow you to control which cache ways of the four way cache are used for the allocation on a linefill When the registers are defined subsequent linefills are placed only in the specified target cache way This gives you some control over the cache pollution cause by particular applications and provides a traditional lockdown operation for locking critical code into the cache A locking bit for each cache way determines whether the normal cache allocation is allowed to access that cache way see Cache Lockdown register L bits on page 99 A maximum of three cache ways of the four way associative cache can be locked ensuring that normal cache line replacement is performed Note f no cache ways have the L bit set to 0 cache way 3 is used for all linefills 98 Hardware Reference NS9215 Instruction or data lockdown register Access instructions Modifying the Cache Lockdown register Register format Cache Lockdown register L bits www digiembedded com WORKING WITH THE CPU R9 Cache Lockdown register The first four bits of this register determine the L bit for the associated cache way The opcode 2 field of the MRC or MCR instruction determines whether the instruction or data lockdown register is accessed opcode 2 0 Selects the DCache Lockdown register or the Unified Cache Lockdown register if a unified cache is implemented The ARM926EJ S processor has separate DCache and ICache opcode 2 1 Select
55. Y b NS9215 Hardware Reference 90000847_C Release date 10 April 2008 2008 Digi International Inc Printed the United States of America rights reserved Digi Digi International the Digi logo a Digi International Company ConnectCore NET NET4OS and NET Works are trademarks or registered trademarks of Digi International Inc the United States and other countries worldwide All other trademarks are the property of their respective owners Information in this document is subject to change without notice and does not represent a commitment on the part of Digi International Digi provides this document as is without warranty of any kind either expressed or implied including but not limited to the implied warranties of fitness or merchantability for a particular purpose Digi may make improvements and or changes in this manual or in the product s and the program s described in this manual at any time This product could include technical inaccuracies or typographical errors Changes are made periodically to the information herein these changes may be incorporated in new editions of the publication Contents Chapter 1 Pinout 265 s snos ase i sse a 27 The Legend ene eth gt o Ue UR 27 Memory ta etu anne nl S tret ed LO Cede e 28 Ethernet interface oae reete rte rea e tee Ra E dot nate 30 Ge
56. 011 Divide by 8 18 7393 9 3693 100 Divide by 16 9 3693 4 6848 Determines the frequency of the system clock rates The full speed rate is 150MHz for the CPU clock and 75MHz for the AHB clock If CCSEL 0 then the CPU clock will be the same frequency as the AHB clock 74 9568 maximum This register can be written on the fly D28 26 R W Max CSC 0x000 Max clock scale control 000 Full speed 149 9136 74 9568 001 Divide by 2 74 9568 37 4784 010 Divide by 4 37 4784 18 7392 011 Divide by 8 18 7393 9 3693 100 Divide by 16 9 3693 4 6848 Software can write to the CSC bits to reduce the clock frequency of the CPU and AHB clocks This register determines the maximum system CPU and AHB clock frequencies when returning low speed operation This register is only valid if the hardware clock scale control bit is set in the Power Management register If CCSEL 0 then the CPU clock will be the same frequency as the AHB clock 74 9568 maximum D25 CCSel 0 0 CPU clock select 0 clock is equal to AHB clock 1 CPU clock is 2 x AHB clock D24 18 N A Reserved N A N A D17 MCOut 1 0x1 Memory clock out 1 0 Clock disabled 1 Clock enabled D16 R W MCOut 0 0x1 Memory clock out 0 0 Clock disabled 1 Clock enabled D15 N A Reserved N A N A D14 EXT DMA 0x1 External DMA 0 Clock disabled 1 Clock enabled 181 SYSTEM CONTROL MODULE
57. 1 Timer enabled 03 R W T3E 0x0 Timer 3 enable 0 Timer reset 1 Timer enabled D02 R W 2 0 0 Timer 2 enable 0 Timer reset Timer enabled Dol R W TIE 0x0 Timer 1 enable 0 Timer reset 1 Timer enabled R W TOE 0x0 Timer 0 enable 0 Timer reset 1 Timer enabled Timer 0 4 Control registers Addresses A090 0190 0194 0198 019 01A0 164 Hardware Reference NS9215 Register 31 30 29 28 27 26 25 SYSTEM CONTROL MODULE Timer 0 4 Control registers 24 23 22 21 20 19 Reserved 15 Register bit assignment Bits D31 16 14 13 12 11 10 9 8 7 6 5 4 3 2 Timer Up di Access Mnemonic N A Reserved N A Reset Description N A D15 R W TE 0x0 Timer enable 0 Timer is disabled 1 Timer is enabled D14 12 R W Cap Comp 0x0 Capture and compare mode functions Applicable only when in 16 bit timer mode 000 001 010 011 100 101 110 111 Normal operation Compare mode toggle output on match Compare mode pulse output on match Capture mode on input falling edge Capture mode on input rising edge Capture mode on every 290 rising edge Capture mode on every 4 rising edge Capture mode on every gth rising edge D11 R W Debug 0x0 Debug mode 0 Timer enabled in CPU debug mode Timer disabled in CPU debug mode D10 R W Int Clr 0x0 Interrupt clear Clears the timer interrupt Software must write a 1 then a 0 to this location t
58. 9002 0004 www digiembedded com 9002 8004 9003 0004 9003 8004 The DMA RX Control register contains control register settings for each receive DMA channel 375 MODULE Module DMA Buffer Descriptor Pointer Register Register bit assignment 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 INDEX Bit s Access Mnemonic Reset Description D31 R W CE 0x0 Channel enable 0 Disable DMA operation Enable DMA operation D30 R W CA 0x0 Channel abort When set causes the current DMA operation to complete and closes the buffer The DMA channel remains idle until this bit is cleared D29 R W FLEX I O 0x0 0 DMA controlled by CPU 1 DMA controlled by flexible I O This bit is valid only for channels 0 and 1 which are assigned to flexible I O module 0 and flexible I O module 1 D28 R W DIRECT 0x0 0 DMA mode 1 Direct access mode D27 16 N A Reserved N A N A D15 10 R STATE 0x0 DMA state machine status field D09 00 R INDEX 0 0 This field can be read at any time to determine the current index Module DMA RX Buffer Descriptor Pointer Addresses 9000 0008 9000 8008 9001 0008 9001 8008 9002 0008 9002 8008 9003 0008 9003 8008 The RX Buffer Descriptor Pointer register is the address of the first buffer descriptor for each DMA channel 376 Hardware Reference NS9215 3 March 2008 I O MODULE Module RX Interrupt Confi
59. PC SDA reset done gpio 12 SPI CLK dup RXC RTS RS485 Control UART C QDC Q Ext Timer Event Out Ch 9 gpio 13 SPI CLK boot E14 gpio 14 IO TXC DTR UART C DMA Ch 1 0 RXD I gpio 14 SPI TXD boot 14 gpio 15 www digiembedded com IO c c gt TXD UART C Ext Timer Event In Ch 9 PIC 0 CAN TXD O gpio 15 SPI EN boot 33 D3 PINOUT 265 Signal gpio 16 U General purpose I O GPIO 4 Description data 0 DCD UART B Ext Int Ch 0 dup gpio 16 B2 gpio 17 data 1 CTS UART B Ext Int Ch 1 dup gpio 17 C2 gpio 18 IO data 2 DSR UART B Ext Int Ch 2 dup gpio 18 D4 gpio 19 IO data 3 RXD UART B EXT INT CH 3 dup gpio 19 Bl gpio 20 IO data 4 RI UART B Ext DMA Done Ch 0 dup gpio 20 E3 gpio 21 IO data 5 RTS RS485 Control UART B Ext DMA Pden Ch 0 dup gpio 21 D2 gpio 22 IO data 6 TXC DTR UART B Ext DMA Done Ch 1 dup gpio 22 4 gpio 23 IO data 7 TXD UART B PIC 1 CAN gpio 23 gp
60. S processor running code from a noncachable region of memory If code is run from a cachable region of memory or a different device is used a different IMB implementation is required IMBs are discussed in Instruction Memory Barrier beginning on page 134 133 WORKING WITH THE CPU AHB behavior Instruction Memory Barrier IMB operation If instruction prefetching is disabled all instruction fetches appear on the AHB interface as single nonsequential fetches If prefetching is enabled instruction fetches appear either as bursts of four instructions or as single nonsequential fetches No speculative instruction fetching is done across a 1 KB boundary instruction fetches including those made in Thumb state are word transfers 32 bits In Thumb state a single word instruction fetch reads two Thumb instructions and a four word burst reads eight instructions Whenever code is treated as data for example self modifying code or loading code into memory a sequence of instructions called an instruction memory barrier IMB operation must be used to ensure consistency between the data and instruction streams processed by the 926 S processor Usually the instruction and data streams are considered to be completely independent by the ARM926E S processor memory system and any changes in the data side are not automatically reflected in the instruction side For example if code is modified in main memory I
61. base CSOB Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select O mask 5 15 14 13 12 11 10 9 8 7 6 4 3 2 1 Chip select mask 5 Reserved CSDO Bits Access Mnemonic Reset Description D31 12 R W CSOB 0x00000 Chip select 0 base Base address for chip select 0 D11 00 N A Reserved N A N A D31 12 R W CSOM 0 0000 Chip select 0 mask Mask or size for chip select 0 D11 01 N A Reserved N A N A D00 R W CSDO 0 1 Chip select 0 disable 0 Disable chip select Enable chip select System Memory Chip Select 1 Dynamic Memory Base and Mask registers Addresses A090 01D8 01DC These control registers set the base and mask for system memory chip select 1 with a minimum size of 4K The powerup default settings produce a memory range of www digiembedded com 0x1000 0000 Ox1FFF 191 SYSTEM CONTROL MODULE System Memory Chip Select 2 Dynamic Memory Base and Mask registers Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select 1 base CS1B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip select 1 base 51 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select 1 mask CS1M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip select 1 mask 51 Reserved CSD1 Register bit assignment Bits Access Mnemonic Reset Description D31 12 R W CS1B 0x 10000 Chip select 1 base Base address for chip
62. www digiembedded com 453 MASTER SLAVE INTERFACE Configuration register Timing parameter for fast mode Register Register bit assignment Address 9005 000C The Configuration register controls the timing on the 12C bus This register also controls the external interrupt indication which can be disabled The 12 bus clock timing is programmable by the scl ref value 08 00 The timing parameter for standard mode is as follows 2 bus clock clk CLREF 2 4 4 scl delay clk PLL Clk Out 4 Notes To determine the PLL Clk Out frequency see the PLL configuration and control system block diagram on page 152 and the PLL Configuration register on page 186 In noisy environments and fast mode transmission spike filtering can be applied to the received data and clock signal The spike filter evaluates the incoming signal and suppresses spikes The maximum length of the suppressed spikes can be specified in the spike filter width field of the Configuration register This is the timing parameter for fast mode 2 bus clock 4 3 CLREF 2 4 scl_delay scl_delay is influenced by the SCL rise time 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IROD TMDE VSCD SFW CLREF Bits Access Mnemonic Reset Description D31 16 N A Reserved N A N A D15 R W IRQD 0 Mask the interrupt to the A
63. 06B8 www digiembedded com ETHERNET COMMUNICATION MODULE Statistics registers D17 00 R W Reset 0x00000 RPKT Incremented for each frame received with a length of 64 to 1518 bytes and containing a frame check sequence FCS error FCS errors are not counted for VLAN frames that exceed 1518 bytes or for any frames with dribble bits D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 RFCS Incremented for each good multicast frame with a length no greater than 1518 bytes non VLAN or 1522 bytes VLAN excluding broadcast frames This counter does not look at range length errors D31 18 R Reset Read as 0 Reserved D17 00 R W Reset 0x00000 RMCA Incremented for each good broadcast frame with a length no greater than 1518 bytes non VLAN or 1522 bytes VLAN excluding multicast frames This counter does not look at range length errors D31 18 R Reset Read as 0 Reserved D17 00 R W Reset 0x00000 RBCA Incremented for each MAC control frame received PAUSE and unsupported D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 RXCF Incremented each time a valid PAUSE control frame is received D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 RXPF Incremented each time a MAC control frame is received with an OPCODE other than PAUSE D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 RBUO 305 Receive alignment error counter A060 06BC Receive code
64. 2 0 Lw clk_enable td www digiembedded com 493 TIMING Values in SRAM The next table describes the values shown in the SRAM timing diagrams timing diagrams Parm Description Min Unit Notes 15 clock high to data out valid 2 42 ns M16 data out hold time from clock high 2 2 ns M17 clock high to address valid 2 2 ns M18 address hold time from clock high 2 2 ns M19 clock high to st_cs_n low 2 2 ns 2 M20 clock high to st_cs_n high 2 2 ns 2 M21 clock high to we_n low 2 2 ns M22 clock high to we_n high 2 2 ns M23 clock high to byte_lanes low 2 2 ns M24 clock high to byte_lanes high 2 2 ns M25 data input setup time to rising clk 10 ns M26 data input hold time to rising clk 0 ns M27 clock high to oe_n low 2 2 ns M28 clock high to oe_n high 2 2 ns Notes 1 The CPU clock out 2 signal is for reference only 2 Only one of the four dy cs n signals is used The diagrams show the active low configuration which can be reversed active high with the PC field 3 Use this formula to calculate the length of the st cs n signal Tacc board delay optional buffer delays both address out and data in 10ns 494 Hardware Reference NS9215 Memory Timing Static RAM read cycles with 0 wait states out p s addr lt 27 0 gt 9 M20 St cs n 3 0 E oe n 23 24 byte la
65. 227 Left shift value table 16 bit wide data bus SDRAM 227 Left shift value table 16 bit wide data bus SDRAM BRC 228 SDRAM address and data bus interconnect 228 32 bit wide 2 228 32 bit wide 00 40 4 4 4404 4 2 229 REQISLENS E 230 gun dE 230 Reset Valles CU hrec d e I DOCE ENTRE 232 Control register 232 SEACUS FEQISE Ol aig fs ER 234 Configuration register aden li 234 Dynamic Memory Control 235 Dynamic Memory Refresh Timer 5 236 REGISTE anaes tetas 237 Dynamic Memory Read Configuration register 237 Dynamic Memory Precharge Command Period 238 Dynamic Memory Active to Precharge Command Period register 239 Dynamic Memory Self refresh Exit Time 240 Dynamic Memory Last Data Out to Active Time register 240 Dynamic Memory Data in to Active Command Time register 241 Dynamic Memory
66. 327 Multicast Low Address Filter Register 0 327 Multicast Low Address Filter Register 1 327 Multicast Low Address Filter Register 2 327 Multicast Low Address Filter Register 3 327 Multicast Low Address Filter Register 4 327 Multicast Low Address Filter Register 5 327 Hardware Reference NS9215 Multicast Low Address Filter Register 6 328 Multicast Low Address Filter Register 7 328 Multicast High Address Filter Register 0 328 Multicast High Address Filter Register 21 328 Multicast High Address Filter Register 32 328 Multicast High Address Filter Register 3 328 Multicast High Address Filter Register 4 328 Multicast High Address Filter Register 45 328 Multicast High Address Filter Register 6 329 Multicast High Address Filter Register 7 329 Multicast Address Mask registers
67. ARM926E S cache format isses ene 132 ARMO926EJ S cache associativity 132 Set way word format for ARM926E S caches 132 Noncachable instruction 2 2 2 2 2 133 Self moditylng 133 AHB 134 Instruction Memory 134 134 Sample IMB sequences 2 135 Chapter 4 System Control Module 137 gre 137 SAU 137 YE CIBO Ex 138 www digiembedded com 9 10 High speed bus 10 0 rnestr 138 High speed bus n 138 How the bus arbiter 22 2 2 1 138 Ownership 139 Locked bus 139 Relinquishing the 139 SPLIT 140 Arbiter configuration
68. Addresses A090 01 8 01 These control registers set the base and mask for system memory chip select 3 with a minimum size of 4K The powerup default settings produce a memory range of 0x3000 0000 Ox3FFF FFFF 193 SYSTEM CONTROL MODULE System Memory Chip Select 0 Static Memory Base and Mask registers Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select 3 base CS3B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Chip select 3 base CS3B Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select 3 mask CS3M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip select 3 mask CS3M Reserved CSD3 Register bit assignment Bits Access Mnemonic Reset Description D31 12 R W CS3B 0x30000 Chip select 3 base Base address for chip select 3 D11 00 N A Reserved N A N A D31 12 R W CS3M 0 0000 Chip select 3 mask Mask or size for chip select 3 D11 01 N A Reserved N A N A D00 R W CSD3 0 1 Chip select 3 disable 0 Disable chip select Enable chip select System Memory Chip Select 0 Static Memory Base and Mask registers Addresses A090 01 0 01 4 These control registers set the base and mask for system memory chip select 0 with a minimum size of 4K The powerup default settings produce a memory range of 0 4000 0000 Ox4FFF FFFF 194 Hardware Reference NS9215 Registers Register bit assignment SYSTEM CONTROL MODULE System Memory Chip Selec
69. Because the collision window starts at the beginning of transmissions the preamble and SFD start of frame delimiter are included The default value 0x37 55d corresponds to the frame byte count at the end of the window D07 04 N A Reserved N A N A D03 00 R W RETX OxF Retransmission maximum Programmable field specifying the number of retransmission attempts following a collision before aborting the frame due to excessive collisions The 802 3u standard specifies the attemptLimit to be OxF 15d Maximum Frame register Address A060 0414 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 294 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE MII Management Configuration register Register bit assignment Bits Access Mnemonic Reset Description D31 16 N A Reserved N A N A D15 00 R W MAXF 0x0600 Maximum frame length Default value of 0x600 represents a maximum receive frame of 1536 octets An untagged maximum size Ethernet frame is 1518 octets A tagged frame adds four octets for a total of 1522 octets To use a shorter maximum length restriction program this field accordingly Note If a proprietary header is allowed this field should be adjusted accordingly For exam ple if 4 byte proprietary headers are prepended to the frames the MAXF value should be set to 1526 octets This allows the maximum VLAN tagged frame pl
70. P12 gpio a 3 U IO 4 0 addr 27 Reserved 1 cs0 oe 2 UARTrefclock 3 gpio a 3 Endian a There is a possible conflict when 12 is used as the I2C SDA signal this case the 2 SDA signal is driven low while in reset then driven active high after end of reset until software configures this pin for the I2C function System clock U D OD Description 116 sys osc I System oscillator circuit in L17 X2 sys osc System oscillator circuit out 15 sys pll dvdd P PLL clean power M16 sys pll dvss P PLL clean ground P2 xl rtc osc I oscillator circuit in 32 768 KHz R2 X2 rtc osc oscillator circuit out www digiembedded com 43 265 System clock drawing ADDR MUST not be pulled down to a logic during boot This will result in the NS9210 being in 59215 PLL bypass mode CPU clock 2 X1 SYS OSC 2 frequency ADDR PLL bypass BootStrap SM Oscillator 100 OHM Optional 20 40MHz Oscillator 29 4912MHz Crystal or Oscillator allows full speed operation SYS OSC 20 40MHz x2 SYS OSC 20 40MHz 330 OHM SYS_PLL_DVDD SYS_PLL_DVSS 44 Hardware Reference NS9215 265 System mode RTC clock and battery backup drawing NS9215 x1 rtc osc XCB5208 18 2 osc bat vdd reg bat vdd reg bat vdd 170 Battery b AUX COMP Pin R1 A
71. Reading from returns the value of the Domain Access Control register m Writing to writes the value of the Domain Access Control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1312 1110 9 8 7 6 5 4 3 2 1 0 Each two bit field defines the access permissions for one of the 16 domains D15 D0 00 No access Any access generates a domain fault 01 Client Accesses are checked against the access permission bits in the section or page descriptor 10 Reserved Currently behaves like no access mode 00 11 Manager Accesses not checked against the access permission bits so a permission fault cannot be generated Use these instructions to access the Domain Access Control register 5 0 Rd c3 0 read domain access permissions pl5 0 Rd c3 0 write domain access permissions 91 WORKING WITH THE CPU R4 register Accessing reading or writing this register causes UNPREDICTABLE behavior R5 Fault Status registers Register R5 accesses the Fault Status registers FSRs The Fault Status registers contain the source of the last instruction or data fault The instruction side FSR is intended for debug purposes only The FSR is updated for alignment faults and for external aborts that occur while the MMU is disabled The FSR accessed is determined by the opcode 2 value opcode 2 0 Data Fault Status register DFSR opcode 2 1 Instruction Fault Status register IFSR
72. See MemoryManagement Unit MMU beginning on page 105 for the fault type encoding Access Access the FSRs using these instructions instructions 15 0 Rd c5 c0 0 read DFSR MCR p15 0 Rd c5 c0 0 write DFSR p15 0 Rd c5 c0 1 read IFSR MCR 15 0 Rd c5 c0 1 write IFSR Register format 31 9 8 7 4 3 0 UNP SBZ 0 Domain Status Register bits Bits Description 31 9 UNPREDICTABLE SHOULD BE ZERO 8 Always reads as zero Writes are ignored 7 4 Specifies which of the 16 domains D15 D0 was being accessed when a data fault occurred 3 0 Type of fault generated See MemoryManagement Unit MMU beginning on page 105 92 Hardware Reference NS9215 Status and domain fields WORKING WITH THE CPU Fault Address register This table shows the encodings used for the status field in the Fault Status register and indicates whether the domain field contains valid information See MMU faults and CPU aborts on page 119 for information about MMU aborts in Fault Address and Fault Status registers Priority Source Size Status Domain Highest Alignment N A 0b00x1 Invalid External abort on translation First level 0b1100 Invalid Second level 0b1110 Valid Translation Section page 0b0101 Invalid 060111 Valid Domain Section page 0b1001 Valid 061011 Valid Permission Section page 0b1101 Valid 051111 Valid Lowest External abort Section page 0b1000
73. Transmit deferral packet counter A060 06F4 308 Transmit excessive deferral packet counter A060 06 8 308 Transmit single collision packet counter A060 06 308 Transmit multiple collision packet counter A060 0700 309 Transmit late collision packet counter A060 0704 309 Transmit excessive collision packet counter A060 0708 309 Transmit total collision packet counter A060 0700 309 Transmit jabber frame counter A060 0718 309 Transmit FCS error counter A060 071 309 Transmit oversize frame counter A060 0724 310 Transmit undersize frame counter A060 0728 310 Transmit fragment counter A060 072 310 General Statistics registers address map 310 Carry Register T 310 Carry Register 2 rp 311 Carry Register 1 Mask 0 0020 0002 22 2 2 2 312 Carry Register 2 Mask 27 00 000022 2 314 A Buffer Descriptor Pointer register
74. descriptor in the ring In this situation the next buffer descriptor 1s found using the appropriate Buffer Descriptor Pointer register When the WRAP bit is not set the next buffer descriptor is found using an offset of 0x10 from the current buffer descriptor pointer I When set tells the RX RD logic to set RXBUFC in the Ethernet Interrupt Status register after the frame has been transferred to system memory E ENABLE bit which when set tells the RX RD logic that this buffer descriptor is enabled When a new frame is received pools that do not have the ENABLE bit set in their next buffer descriptor are skipped when deciding in which pool to put the frame The receive processor can use up to four different sized receive buffers in system memory Note To enable a pool that is currently disabled change the ENABLE bit from 0 to 1 and reinitialize the buffer descriptors pointed to by the Buffer Descriptor Pointer register 1 Set the ERXINIT bit in the Ethernet General Control Register 1 7 for RXINIT to be set in the Ethernet General Status register Change the ENABLE bit only while the receive packet processor is idle Buffer pointer 32 bit pointer to the start of the buffer in system memory This pointer must be aligned on a 32 bit boundary Status Lower 16 bits ofthe Ethernet Receive Status register The status is taken from the receive status FIFO and added to the buffer descriptor after the last word of the frame i
75. gpio 72 R13 gpio 73 IO 0 GEN 510 PIC 1 GEN IO S I O PWM Ch3 gpio 73 P13 gpio 74 0 GEN IO 6 I O 0 GEN IO 6 I O Ext Timer Event In Ch 0 gpio 74 016 gpio 75 www digiembedded com 0 GEN IO 7 I O PIC 1 GEN IO 7 I O Ext Timer Event in Ch 1 gpio 75 39 265 Description T15 gpio 76 U IO 2 PIC 0 CTL IO 0 I O PIC 1 IO 0 I O Ext Timer Event in Ch 2 gpio 76 0 IO 1 I O 1 IO 1 I O Ext Timer Event Ch 3 gpio 77 0 IO 2I I O 1 IO 2 I O Ext Timer Event Ch 4 gpio 78 0 IO 3 I O 1 IO 3 I O Ext Timer Event Ch 5 gpio 79 PIC 0 BUS 0 0 I O PIC 1 BUS 0 0 1 Ext Timer Event in Ch 6 dup gpio 80 PIC 0 BUS 0 1 I O PIC 1 BUS O 1 I O Ext Timer Event in Ch 7 dup gpio 81 PIC 0 BUS 0 2 I O PIC 1 BUS 0 2 I O Ext Timer Event in Ch 8 dup gpio 82 PIC 0 BUS 0 3 I O PIC 1 BUS 0 3 I O Ext Timer Event in Ch 9 dup gpio 83 PIC 0 BUS 0 4 I O PIC 1 BUS 0 4 I O Ext Timer Event Out Ch 0 gpio 84 PIC 0 BUS 0 5 I O PIC 1 BUS 0 5 I O Ext Timer Event Out Ch 1 gpio 85 T16 gpio 77 U 10 2 R14 gpio 78 U IO 2 14 gpio 79 U IO 2
76. information for the relevant dynamic memory chip select These registers are usually modified only during system initialization Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved Protect BDMC Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rsvd AM Rsvd AM1 Reserved MD Reserved Register bit assignment Bits Access Mnemonic Description D31 21 N A Reserved N A do not modify D20 R W Protect Write protect 0 Writes not protected reset value on reset_n 1 Write protected D19 R W BDMC Buffer enable 0 Buffer disabled for accesses to this chip select reset value on reset_n 1 Buffer enabled for accesses to this chip select The buffers must be disabled during SDRAM initialization The buffers must be enabled during normal operation D18 15 N A Reserved N A do not modify D14 R W AM Address mapping 0 Reset value on reset n See Table Register map on page 230 for more information D13 N A Reserved N A do not modify D12 07 R W AMI Address mapping 00000000 Reset value on reset n The SDRAM column and row width and number of banks are computed automatically from the address mapping See Register map beginning on page 230 for more information D06 05 N A Reserved N A do not modify D04 03 R W MD Memory device 00 SDRAM reset value on reset n 01 Low power SDRAM 10 Reserved 11 Reserved 02 00 N A Reserved N A do not modify 248 Hardware Reference NS9215 MEMORY C
77. lines low during a read access as memory devices during a read all device bytes must be selected to avoid undriven byte lanes on the read data value With 16 and 32 bit wide memory devices byte select signals exist and must be appropriately controlled see the next two figures Memory banks constructed from 16 bit memory addr 22 2 cs n St n 51 we n 20 0 addr 21 1 20 0 cs n CEn OE n oe n OE n WEn st we n WE A 20 0 CE n WE n data mask 3 UB n data mask 1 UB n data mask 3 UB n data mask 2 LB n data mask 0 LB n data mask 2 LB n data 31 16 1O 15 0 data 15 0 IO 15 0 data 15 0 IO 15 0 32 bit bank consisting of two 16 bit devices 16 bit bank consisting of one 16 bit device Memory bank constructed from 32 bit memory addr 22 2 20 0 cs n CE n st oe n n st we n WE n data mask 3 B 3 n data mask 2 B 2 n data mask 1 B 1 n data mask 0 B 0 n data 31 0 IO 31 0 32 bit bank consisting of one 32 bit device The next figure shows connections for a typical memory system with different data width memory devices www digiembedded com 223 224 MEMORY CONTROLLER Address connectivity addr 22 0 cs 0 st oe n cs 1 st we n cs 2 data mask 3 data mask 2 data mask 1 data mask 0 Hardware Reference NS9215 addr 22 2 addr 11 2 addr 17 2
78. the bit cell boundaries are late with respect to the DPLL tracked bit cell boundaries and the count is lengthened by either one or two counts How far off the DPLL tracked bit cell boundaries are determines whether the count is adjusted by one or two Thistracking allows for minor differences in the transmit and receive clock frequencies NRZ and NRZI With NRZ and NRZI data encoding the DPLL counter runs continuously and adjusts data encoding after every receive data transition Because NRZ encoding does not guarantee a minimum density of transitions the difference between the sending data rate and the DPLL output clock rate must be very small and depends on the longest possible run of zeros in the received frame NRZI encoding guarantees at least one transition every six bits with the inserted zeroes Because the DPLL can adjust by two counts every bit cell the maximum difference between the sending data rate and the DPLL output clock rate is 1 48 2 Biphase data With biphase data encoding the DPLL works in multiple access conditions where encoding there may not be flags on the idle line The DPLL properly generates an output clock based on the first transition in the leading zero of an opening flag Similarly the DPLL requires only the completion of the closing flag to provide the extra two clocks to the receiver to properly assemble the data biphase level mode this means the transition that defines the last zero of
79. 0114 0118 011C 0120 0124 0128 012C 0130 0134 0138 013 0140 level 31 The Interrupt Vector Address register configures the Interrupt vector address for each interrupt level source Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Interrupt vector address register value IVARV 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt vector address register value IVARV Register bit assignment Bits Access Mnemonic Reset Description D31 00 R W Int Vec Adr 0x0 Interrupt Vector Address register Interrupt vector address register bits Int Interrupt Config Configuration 31 0 registers Addresses A090 0144 0148 014C 0150 0154 0158 015C 0160 Each Interrupt Configuration register is 8 bits in length and programs each interrupt configuration for each priority level Individual This table shows how the 32 individual 8 byte registers are mapped in the eight 32 register mapping bit registers Register 31 24 23 16 15 08 07 00 A090 0144 Int Config 0 Int Config 1 Int Config 2 Int Config 3 A090 0148 Int Config 4 Int Config 5 Int Config 6 Int Config 7 A090 014C Int Config 8 Int Config 9 Int Config 10 Int Config 11 A090 0150 Int Config 12 Int Config 13 Int Config14 Int Config 15 A090 0154 Int Config 16 Int Config 17 Int Config 18 Int Config 19 A090 0158 Int Config 20 Int Config 21 Int Config 22 Int Config 23 www digiembedded com 175 SYSTEM CONTROL MOD
80. 1 0 Reserved Cal Time 460 Hardware Reference NS9215 REAL TIME CLOCK MODULE 12 24 Hour register Register bit assignment Description D31 02 N A Reserved N A N A D01 R W Cal 0 1 Calendar operation 0 Calendar operation enabled Calendar operation disabled D00 R W Time 0 Time date hour minute second operation 0 Time operation enabled 1 Time operation disabled 12 24 Hour register Address 9006 0004 The 12 24 Hour register controls 12 or 24 hour clock mode operation Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ide Register bit assignment Bits Access Mnemonic Reset Description D31 01 N A Reserved N A N A DOO R W 12 24 0x0 12 24 clock mode operation 0 24 hour mode operation 1 12 hour mode operation www digiembedded com 461 REAL TIME CLOCK MODULE Time register Address 9006 0008 The TIme register sets the time values to the correct values and reads the time registers BCD is binary coded decimal Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Rsvd PM HR T HR U Rsvd MT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Rsvd ST SU HT HU Register bit assignment Bits Access Reset Description D31 N A Reserved N A N A D30 R W PM 0x0 PM Used in 12 hour mode only 0 AM 1 PM
81. 1 Pad to 64 bytes append Any 1 0 1 If untagged pad to 60 bytes append If VLAN tagged pad to 64 bytes append CRC Back to Back Inter Packet Gap register Address A060 0408 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IPGT 291 www digiembedded com ETHERNET COMMUNICATION MODULE Non Back to Back Inter Packet Gap register Register bit assignment Bits Access Mnemonic Reset Description D31 07 N A Reserved N A N A D06 00 R W IPGT 0x00 Back to back inter packet gap Programmable field that indicates the nibble time offset of the minimum period between the end of any transmitted frame to the beginning of the next frame Full duplex mode m Register value should be the appropriate period in nibble times minus 3 m Recommended setting is 0x15 21d which represents the minimum IPG of 0 96 uS in 100 Mbps or 9 6uS in 10 Mbps Half duplex mode m Register value should be the appropriate period in nibble times minus 6 m Recommended setting is 0x12 18d which represents the minimum IPG of 0 96 uS in 100 Mbps or 9 6 uS in 10 Mbps Non Back to Back Inter Packet Gap register Address A060 040C Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rsvd IPGR1 Rsvd IPGR2 292 Hardware Reference NS9215 ETHERNET COMMUNICATIO
82. 13 62 31 30 29 28 27 26 25 24 23 21 20 19 18 17 16 5 4 15 14 13 12 11 10 9 8 7 5 4 3 2 1 0 2 Bit s Access Mnemonic Reset Description D31 24 R W 55 0 18 GPIO 55 configuration D23 16 R W GPIO54 0x18 GPIO 54 configuration D15 08 R W GPIOS53 0x18 GPIO 53 configuration D07 00 R W 52 0x18 GPIO 52 configuration Hardware Reference NS9215 CONTROL MODULE GPIO Configuration registers GPIO Address A090 2038 Configuration Register 14 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO59 GPIO58 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO57 GPIO56 Bit s Access Mnemonic Reset Description D31 24 R W 59 0 18 GPIO 59 configuration D23 16 R W 8 0 18 GPIO 58 configuration D15 08 R W 57 0 18 GPIO 57 configuration D07 00 R W 56 0 18 GPIO 56 configuration GPIO Address A090 203C Configuration Register 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO61 GPIO60 Bit s Access Mnemonic Reset Description D31 24 R W GPIO63 0x18 GPIO 63 configuration D23 16 R W GPIO62 0x18 GPIO 62 configuration D15 08 R W GPIO61 0x18 GPIO 61 configuration D07 00 R W GPIO60 0x18 GPIO 60 configuration www digiembedded com 63 GPIO I O CONTROL MODULE 222777717 71 GPIO Configuration registers Address A090 2040 Configuration Register 16 31 30 29
83. 20 19 18 17 16 RXBPTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXBPTR Register bit assignment Bits Access Mnemonic Reset Description D31 00 R W RXBPTR 0x00000000 RX_B Buffer Descriptor Pointer Contains a pointer to the initial receive buffer descriptor for the B pool of buffers www digiembedded com 315 ETHERNET COMMUNICATION MODULE RX C Buffer Descriptor Pointer register RX C Buffer Descriptor Pointer register Address A060 0A08 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXCPTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXCPTR Register bit assignment Bits Access Mnemonic Reset Description D31 00 R W RXCPTR 0x00000000 RX_C Buffer Descriptor Pointer Contains a pointer to the initial receive buffer descriptor for the C pool of buffers RX_D Buffer Descriptor Pointer register ee 000000 0 0 0 0006 6 660 060 6 6 0666000 660505000 6 0 0 0 0 0 0 50060060 Address A060 0 0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXDPTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register bit assignment Bits Access Mnemonic Reset Description D31 00 R W RXDPTR 0x00000000 RX_D Buffer Descriptor Pointer Contains a pointer to the initial receive buffer descriptor for the D pool of buffers 316 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Ethernet Interrupt Status register Ethernet Interrupt Status register Register R
84. 28 27 26 24 23 21 20 19 18 17 16 GPIO67 GPIO66 15 14 13 12 11 10 8 7 5 4 3 2 1 0 GPIO65 Bit s Access Mnemonic Reset Description D31 24 R W GPIO67 0x18 GPIO 67 configuration D23 16 R W GPIO66 0x18 GPIO 66 configuration D15 08 R W GPIO65 0x18 GPIO 65 configuration D07 00 R W GPIO64 0x18 GPIO 64 configuration GPIO Address A090_2044 Configuration Register 17 31 30 2 28 27 26 24 23 21 20 19 18 17 16 GPIO 1 15 14 13 12 11 10 8 7 5 4 3 2 1 0 GPIO69 GPIO68 5 55 Reset Description D31 24 R W GPIO71 0x18 GPIO 71 configuration D23 16 R W GPIO70 0x18 GPIO 70 configuration D15 08 R W GPIO69 0x18 GPIO 69 configuration D07 00 R W GPIO68 0x18 GPIO 68 configuration 64 Hardware Reference NS9215 CONTROL MODULE GPIO Configuration registers GPIO Address A090 2048 Configuration Register 18 31 30 29 28 27 26 24 23 21 20 19 18 17 16 5 15 14 13 12 11 10 8 7 5 4 3 2 1 0 GPIO 3 2 Bit s Access Mnemonic Reset Description D31 24 R W GPIO75 0x18 GPIO 75 configuration D23 16 R W GPIO74 0x18 GPIO 74 configuration D15 08 R W GPIO73 0x18 GPIO 73 configuration D07 00 R W GPIO72 0x18 GPIO 72 configuration GPIO Address A090 204C Configuration Register 19 31 30 29 28 27 26 24 23 21 20 19 18 17 16 9 8 15 14 13 12 11 10 8 7 5 4 3 2 1 0 7 GPIO76 Bit s Access Mnemonic Reset Des
85. 6 5 4 3 2 1 0 Reserved Pap Register bit assignment Bits Access Reset Description D31 01 N A Reserved N A N A D00 R ArbControl 0 0 Arbiter control 0 connected directly to memory controller 1 connected to main arbiter BRCO BRC2 and BRC3 registers Addresses A090 0004 0008 000C 0010 The BRC 0 3 registers control the AHB arbiter bandwidth allocation scheme 158 Hardware Reference NS9215 Channel allocation Register Register bit assignment SYSTEM CONTROL MODULE AHB Error Detect Status 1 This is how the channels are assigned in the four registers Register name 31 24 23 16 15 08 07 00 BRCO Channel 0 Channel 1 Channel 2 Channel 3 BRCI Channel 4 Channel 5 Channel 6 Channel 7 BRC2 Channel 8 Channel 9 Channel 10 Channel 11 BRC3 Channel 12 Channel 13 Channel 14 Channel 15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Channel O 4 8 or 12 Channel 1 5 9 or 13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 6 10 14 Channel 3 7 11 15 CEB Rsvd BRF HMSTR This table shows the bit definition for each channel using data bits 07 00 as the example Bits Access Mnemonic Reset Description D07 R W CEB 0x0 Channel enable bit 0 Disabled Enabled D06 N A Reserved N A N A D05 04 R W BRF 0x0 Bandwidth reduction field Program the weight for each AHB bus master Used to limit access to the ro
86. 8 7 6 5 4 3 2 1 0 Not used DATA Register bit assignment Bits 55 Reset Description D31 11 R Not used 0 Write this field to 0 D10 R FLOW_STATE 0 0 Flow control state 0 Hardware initiated Hardware initiated XOFF 09 08 R W FLOW4 0 Flow control enable Allows you to define flow characteristics using the DATA and MASK fields on the Receive Character Match Control Register 4 Note The ENABLE field has no effect on the flow control logic The flow control is defined as shown 0x Disabled 10 Change the FLOW STATE field to XON upon match 11 ChangetheFLOW STATE field to XOFF upon match D07 06 R W FLOW3 0 Flow control enable www digiembedded com Allows you to define flow characteristics using the DATA and MASK fields on the Receive Character Match Control Register 3 Note The ENABLE field has no effect on the flow control logic The flow control is defined as shown Ox Disabled 10 Change the FLOW STATE field to upon match 11 ChangetheFLOW STATE field to XOFF upon match 401 SERIAL CONTROL MODULE UART Force Transmit Character Control register Bits Access Mnemonic Reset Description D05 04 R W FLOW2 0 Flow control enable Allows you to define flow characteristics using the DATA and MASK fields on the Receive Character Match Control Register 2 Note The ENABLE field has no effect on the flow control logic The flow control is defined as shown Ox Disabled 10 Change t
87. 9001 1020 Receive Character Match Control 3 9001 1024 Receive Character Match Control 4 9001 1028 Receive Character Based Flow Control 9001 102C Force Transit Character Control 9001 1030 ARM Wakeup Control 9001 1034 Transmit Byte Count 9001 1038 9001 109C 9001 1100 UART Receive Buffer read DLAB 0 UART Transmit Holding write 9001_ 1100 UART Baud Rate Divisor LSB DLAB 1 9001_ 1104 UART Baud Interrupt Enable DLAB 0 9001_ 1104 UART Baud Rate Divisor MSB DLAB 1 9001_ 1108 UART Identification read UART FIFO Control write 9001_110C UART Line Control 9001 1110 UART Modem Control 390 Hardware Reference NS9215 SERIAL CONTROL MODULE UART Wrapper Configuration register 9001 1114 UART Line Status 9001 1118 UART Modem Status 9001 111C UART Scratch Wrapper Configuration register Address 9001 1000 9001 9000 9002 1000 9002 9000 This is the primary Wrapper Configuration register Register 31 30 9 28 7 26 25 4 22 21 20 19 18 17 16 Reserv TXFL eg REN TXEN Feserved ps USH UH RXCL Reserv Register bit assignment Bits Access Mnemonic Reset Description D31 N A Reserved N A N A D30 R W RXEN 0 0 Disable wrapper function 1 Enable wrapper to process receive characters D29 R W TXEN 0 0 Disable transmitter function 1 Enable wrapper to process transmit characters D28 R W MODE 0 Selects either UART or HDLC mode This
88. 9001 9104 9002 1104 9002 9104 DLAB 1 UART Baud Rate Divisor sets bits 15 08 of the baud rate generator divisor 406 Hardware Reference NS9215 SERIAL CONTROL MODULE UART UART Interrupt Enable register Register 15 14 13 12 m 10 9 8 7 6 5 4 3 2 1 0 Reserved BRDM Register bit assignment Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 00 R W BRDM 0 Bits 15 08 of the baud rate generator divisor UART Interrupt Enable register Address 9001 1104 9001 9104 9002 1104 9002 9104 DLAB 0 The UART Interrupt Enable register selects the source of the interrupt from the UART Note that only bit ETBEI bit 01 must be set for normal operation All other bits are for diagnostic purposes only Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register bit assignment Bits Access Mnemonic Reset Description D31 04 N A Reserved N A N A D03 R W EDSSI N A Enables modem status interrupt 0 Disabled Enabled www digiembedded com 407 SERIAL CONTROL MODULE UART BEEN UART Interrupt Identification register Bits Access Mnemonic Reset Description D02 R W ELSI 0 Enables receive line status interrupt 0 Disabled Enabled D01 R W ETBEI 0 Enables transmit holding register empty interrupt 0 Disabled 1 Enabled D00 R W ERBFI 0 Enables receive data available interrupt 0 Disabled 1 Enabled UART Interrupt Identification registe
89. A D03 TBC Enable transmit buffer close Enables interrupt generation when the HDLC transmit FIFO indicates to the HDLC transmitter that a byte corresponds to a buffer close event D02 RBC Enable receive buffer close Enables interrupt generation whenever a buffer close event is passed from the HDLC receiver to the receive FIFO These are the HDLC receive buffer close events 1 Receive overrun detected 2 Receive abort detected 3 Buffer closed due to invalid CRC 4 Buffer closed due to valid CRC 01 R W TX_IDLE Enable transmit idle Enables interrupt generation whenever the transmitter moves from the active state to the idle state This indicates that the transmit FIFO is empty and the transmitter is not actively shifting out data D00 R W RX IDLE Enable receive idle Enables interrupt generation whenever the receiver moves from the active state to the idle state If a start bit is not received after a stop bit the receiver enters the idle state Interrupt Status register Address 9002 9008 The Interrupt Status register provides status about HDLC events All events are indicated by reading a 1 and are cleared by writing a 1 www digiembedded com 425 SERIAL CONTROL MODULE HDLC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Not used HNT di OFLOW ICRC VCRC RABORT 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TBC RBC TX IDLE
90. A o YX cs n st oe n NE Timing parameter WAITRD 2 WAITOEN 0 WAITPAGE 1 WAITWR N A WAITWEN N A WAITTURN N A This diagram shows a 32 bit read from an 8 bit page mode ROM device causing four burst reads to be performed A total of eight AHB wait states are added during this transfer five AHB arbitration cycles and then one for each of the subsequent reads WAITRD and WAITPAGE are 0 out addr y A y 1 Y A 2 A 3 data CYA X XY X Xy cs n D A 1 D A 2 D A 3 st_oe_n WAITRD 0 WAITOEN 0 WAITPAGE 0 WAITWR N A WAITWEN N A WAITTURN N A 215 MEMORY CONTROLLER Static memory write control Write enable The delay between the assertion of the chip select and the write enable is programming programmable from 1 to 16 cycles using the WAITWEN bits of the Static Memory delay Write Enable Delay StaticWaitWen 3 0 registers The delay reduces the power consumption for memories The write enable is asserted on the rising edge of HCLK after the assertion of the chip select for zero wait states The write enable is always deasserted a cycle before the chip select at the end of the transfer datamask n byte lane signal has the same timing as st we n write enable signal for writes to 8 bit devices that use the byte lane selects instead of the write enables SRAM Write timing for SRAM starts with assertion o
91. AUX Boot Boot End resp acc 184 Hardware Reference NS9215 Register bit assignment Bits D31 24 Access Mnemonic R REV Miscellaneous System Configuration and Status register Reset 0 0 SYSTEM CONTROL MODULE Description Revision Indicates the hardware identification and revision of the processor chip D23 16 0 3 Identification Identifies the chip as 0 NS9750B AI 1 NS9360 2 NS9210 3 NS9215 D15 07 N A Reserved N A N A D06 R AUX COMP N A Auxiliary analog comparator status 0 Levelis below 2 4V 1 Level 15 above 2 4V D05 D04 03 R Boot mode R Boot width HW strap gpio a 2 HW strap gpio a 0 addr 23 Boot mode 0 Boot from SPI 1 Boot from flash If boot mode is set to boot from flash 00 8 bit 01 32 bit 10 32 bit 11 16 bit If boot mode is set to boot from SPI 00 Reserved 01 Boot using 8 bit address SPI device 10 Boot using 24 bit address SPI device 11 Bootusing 16 bit address SPI device D02 R W End mode HW strap gpio a 3 Endian mode 0 Little endian mode 1 Big endian mode D01 R W Mis bus resp 0x0 Misaligned bus address response mode 0 Allow misaligned bus addresses 1 Generate an error response when a misaligned bus address is found that is when haddr bits 1 or 0 are not level 0 D00 R W Int reg acc 0x1 Internal register access mode bit 0 0 Allow access to internal registers using P
92. Address A060 0A3C So the nx RD logic knows when the software is freeing a buffer for reuse the software writes to the RXFREE register each time it frees a buffer in one of the pools RXFREE has an individual bit for each pool this bit is set to 1 when the register is written Reads to RXFREE always return all 05 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RX RX RX RX Reserved FREED FREEC FREEB FREEA Register bit assignment Bits Access Mnemonic Reset Description D31 04 N A Reserved N A N A D03 W RXFREED 0 Pool D free bit D02 W RXFREEC 0 Pool C free bit 326 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Multicast Address Filter registers Bits Access Mnemonic Reset Description D01 W RXFREEB 0 Pool B free bit D00 W RXFREEA 0 Pool A free bit Multicast Address Filter registers Multicast Low Address Filter Register 0 Multicast Low Address Filter Register 1 Multicast Low Address Filter Register 2 Multicast Low Address Filter Register 3 Multicast Low Address Filter Register 4 Multicast Low Address Filter Register 5 www digiembedded com Each of the eight entries in the multicast address filter logic has individual registers to hold its 48 bit multicast address The multicast address for each entry is split between two registers Each entry has a register that contains the lower 32 bit
93. Bits Access Mnemonic Reset Description D13 R W IO hub 0 IO hub 0 Clock disabled Clock enabled D12 R W RTC 0 1 RTC 0 Clock disabled Clock enabled D11 R W PC 0 1 0 Clock disabled Clock enabled D10 N A Reserved N A N A D09 R W AES 0x0 AES 0 Clock disabled Clock enabled D08 R W ADC 0 1 ADC 0 Clock disabled Clock enabled D07 06 N A Reserved N A Always write to 00 D05 R W SPI 0 SPI 0 Clock disabled Clock enabled D04 R W UARTD 0 1 UARTD 0 Clock disabled Clock enabled D03 R W UART 0 1 UART C 0 Clock disabled Clock enabled D02 R W UART B 0 1 0 Clock disabled Clock enabled D01 R W UARTA 0 UARTA 0 Clock disabled Clock enabled D00 R W Eth MAC 0 Ethernet 0 Clock disabled Clock enabled Module Reset register Address A090 0180 182 Hardware Reference NS9215 Register Register bit assignment www digiembedded com SYSTEM CONTROL MODULE Module Reset register The Module Reset register resets each module on the AHB bus 31 30 29 28 27 26 2 24 23 22 21 20 19 18 17 16 RST STAT Bits D31 29 D28 15 D14 Access R N A Mnemonic RST STAT Reserved EXT DMA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reser IO Reser R UART UART UART UART Eth Reset Description Not reset Reset status N A 0x1 001 External reset using reset_n 010 Extern
94. Config 18 Int Config 19 A090 0158 Int Config 20 Int Config 21 Int Config 22 Int Config 23 A090 015C Int Config 24 Int Config 25 Int Config 26 Int Config 27 A090 0160 Int Config 28 Int Config 29 Int Config 30 Int Config 31 A090 0164 ISADDR A090 0168 Interrupt Status Active A090 016C Interrupt Status Raw A090 0170 Reserved A090 0174 Software Watchdog Configuration A090 0178 Software Watchdog Timer Hardware Reference NS9215 www digiembedded com SYSTEM CONTROL MODULE System configuration registers Offset 31 24 23 16 15 8 7 0 A090 017C Clock Configuration register A090 0180 Module Reset register A090 0184 Miscellaneous System Configuration register A090 0188 PLL Configuration register A090 018C Active Interrupt ID register A090 0190 Timer 0 Control register A090 0194 Timer 1 Control register A090 0198 Timer 2 Control register A090 019C Timer 3 Control register A090 01A0 Timer 4 Control register A090 01A4 Timer 5 Control register A090 01A8 Timer 6 Control register A090 01AC Timer 7 Control register A090 01 0 TImer 8 Control register A090 01B4 Timer 9 Control register A090 01B8 A090 01CC Reserved A090 01D0 System Memory Chip Select 0 Dynamic Memory Base A090 01D4 System Memory Chip Select 0 Dynamic Memory Mask A090 01D8 System Memory Chip Select 1 Dynamic Memory Base A090 01DC System Memory Chip
95. D29 28 R W HR_T 0x0 Hours tens BCD digit 0 2 D27 24 R W HR U 0x0 Hours units BCD digit 0 9 D23 N A Reserved N A N A D22 20 R W MT 0 0 Minutes tens BCD digit 0 5 D19 16 R W MU 0x0 Minutes units BCD digit 0 9 D15 N A Reserved N A N A D14 12 R W ST 0x0 Seconds tens BCD digit 0 5 D11 08 R W SU 0 0 Seconds units BCD digit 0 9 D07 04 R W HT 0x0 Hundredths of a second tens BCD digit 0 9 D03 00 R W HU 0x0 Hundredths of a second units BCD digit 0 9 462 Hardware Reference NS9215 REAL TIME CLOCK MODULE Calendar register Calendar register Address 9006 000C The Calendar register sets the calendar values to the correct values and reads the calendar registers BCD is binary coded decimal Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved CT CU YT YU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DT DU MT MU Day Register bit assignment Access Mnemonic Description D31 30 N A Reserved N A N A D29 28 R W 0 0 Century tens BCD digit 1 2 D27 24 R W CU 0x0 Century units BCD digit 0 9 D23 20 R W YT 0x0 Years tens BCD digit 0 9 D19 16 R W YU 0x0 Years units BCD digit 0 9 D15 14 N A Reserved N A N A D13 12 R W DT 0x0 Date tens BCD digit 0 3 D11 08 R W DU 0x0 Date units BCD digit 0 9 D07 R W MT 0x0 Months tens BCD digit 0 1 D06 03 R W MU 0x0 Months units BCD digit 0 9 D02 00 R W Day 0x0 Day of
96. DMA TX Interrupt Configuration register 0x9003 0024 Reserved 0x9003 0028 SPI Direct Mode TX Data FIFO 0x9003 002C SPI Direct Mode TX Data Last FIFO 0 9003 0030 0 9003 OFFF Reserved 0x9003 1000 0 9003 7FFF SPI CSR Space Register Offset Description 31 00 0 9003 8000 0 9003 8FFF Reserved 0x9003_ 9000 0x9003_FFFF AD CSR Space Registers 9004 0000 9004 7FFF and 9004 8000 9004 FFFF are reserved Register Offset Description 31 00 0x9005 0000 0x9005_7FFF PC CSR Space Registers 9005 8000 9005 FFFF are reserved 371 I O MODULE Module Interrupt FIFO Status register RTC register address map Register Offset Description 31 00 0x9006_0000 0 9006 00 RTC CSR Space 0x9006_0000 0x9006_00FC 64 byte Battery Backed RAM IO Hardware Assist register Register Offset Description 31 00 address map 0 0 0x9006 8000 0 9006 FFFF IO Hardware Assist CSR Space for Flexible I O Module 0 IO Hardware Assist register Register Offset Description 31 00 address map 1 0x9007 0000 0x9007 7FFF IO Hardware Assist CSR Space for Flexible I O Module 1 IO register address map 0 Register Offset Description 31 00 0x9008 0000 0x9008 FFFF IO Space for Flexible I O Module 0 IO register address map 1 Register Offset Description 31 00 0x9009 0000 0 9009 FFFF IO Space for Flexible I O Module 1
97. Enable register to enable interrupt generation on specific events Enable the interrupt by writing a 1 to the appropriate bit field s Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ica RXCLS Reserved TBC RBC ced RX_IDLE Register bit assignment Bits Access Mnemonic Reset Description D31 22 R W Not used 0 Write this field to 0 D21 R W HINT 0 Enable HDLC interrupt Enables interrupt generation directly from the HDLC module This is normally handled by hardware D20 N A Reserved N A N A D19 R W OFLOW 0 Enable overflow error Enables interrupt generation if the 4 character FIFO in the HDLC overflows Note This should not happen in a properly configured system D18 R W ICRC 0 Enable invalid CRC Enables interrupt generation when a frame is received with an invalid CRC D17 R W 0 Enable valid Enables interrupt generation when a frame is received with a valid CRC 424 Hardware Reference NS9215 Bits D16 Access R W Mnemonic RABORT Reset 0 SERIAL CONTROL MODULE HDLC Interrupt Status register Description Enable receive abort error Enables interrupt generation when a frame is received with an abort D15 N A Reserved N A N A D14 R W RXCLS Software receive close Enables interrupt generation when software forces a buffer close D13 04 N A Reserved N A N
98. Fairchild NC7SP17 Single Schmitt trigger buffer available in 5 lead SC70 and 6 lead MicroPak packages Philips Single Schmitt trigger buffer available in 5 lead SC70 and SOT 353 packages TI SN7ALVCIGI7DC Single Schmitt trigger buffer available in 5 lead SC70 and SOT 353 packages ON Semi NL17SZ17DFT2 Single Schmitt trigger buffer available in 5 lead SC70 and SOT 353 packages 483 TIMING Memory Timing 484 All AC characteristics are measured with 35pF unless otherwise noted Memory timing contains parameters and diagrams for both SDRAM and SRAM timing The table below describes the values shown in the SDRAM timing diagrams Parm Description Min Unit Notes MI data input setup time to rising 1 0 ns M2 data input hold time to rising 0 0 ns out high to address valid 9 5 ns address hold time 4 0 M5 clk out high to data mask 9 5 ns 1 2 M6 clk out high to dy cs nlow 9 5 ns 3 4 M7 clk out high to ras nlow 9 5 ns M8 clk out high to cas nlow 9 5 ns M9 clk out high to we nlow 9 5 ns M10 clk_out high to data out 9 5 ns M12 data out hold time 4 0 M3 clk_out high to clk_en high 9 5 ns M13 clk_en high to sdram access 2 2 clock M14 end sdram access to clk_en low 2 2 clocks Notes 1 four data mask signals are used for all transfers 2 four data mask signals will go low during read cycle for both 16 bit and 32 bit transfers 3 Onl
99. GPIO Configuration Register 22 67 GPIO Configuration Register 23 67 GPIO Configuration Register 24 68 GPIO Configuration Register 25 68 GPIO Configuration Register 26 69 GPIO Control reQisters RERUM EEG 70 GPIO Control Register Foe deve Ra 70 GPIO Control Register 71 GPIO Control Register 2 cs cos tete ned 72 GPIO Control Register 3 11 73 5 5 dmg dee ter 74 GPIO Status Register teer d 74 GPIO Status Register erp ERR exe 75 GPIO Status Register etie er e E EN 76 Memory Bus Configuration register 76 Chapter 3 Working with the 81 About the enn 81 926 S process block diagram 82 SOUS pM 82 5
100. GPIO Configuration YES NO NO NO Other ASIC Registers YES YES YES YEs NS9215 POR trips when voltage on L3 drops below 2 74V 2 97V Definitions reset n hardware reset input buffer with pull up resistor sreset n soft reset input buffer with pull up resistor does not reset the PLL reset_out_n hardware reset to NS9215 core and output buffer resets all logic NS9215 core including PLL reset done reflects the state of the ARM926 reset for any type of reset event 47 265 JTAG Test JTAG Test Signal U D OD Description N14 tdi U I Test data in N15 tdo 2 Test data out T17 tms U I Test mode select R16 trst n U I Test mode reset For normal operation this pin is tied to ground or pulled down P15 tck I Test mode clock P16 rtck 2 Test mode return clock Note 1 SYS MODE 2 SYS MODE 1 SYS MODE 0 0 1 1 boundary scan POR disabled 100 boundary scan POR enabled 10 1 board test mode outputs tristated 110 ARM debug enabled POR disabled 1 1 1 debug enabled POR enabled production boundary scan mode should be selected for lower power Note 2 With the internal POR enabled the RESET N pin can be left unconnected The signal RESET OUT N can be us
101. GPIO46 0 GPIO 46 control bit D15 R W GPIO47 0 GPIO 47 control bit D16 GPIO48 0 GPIO 48 control bit D17 R W GPIO49 0 GPIO 49 control bit D18 R W GPIO50 0 GPIO 50 control bit D19 R W GPIO51 0 GPIO 51 control bit D20 R W GPIO52 0 GPIO 52 control bit D21 R W 53 0 GPIO 53 control bit www digiembedded com CONTROL MODULE Bit s Access Mnemonic Reset Description D22 R W 54 0 GPIO 54 control bit D23 R W 55 0 GPIO 55 control bit D24 R W 56 0 GPIO 56 control bit D25 R W 57 0 GPIO 57 control bit D26 R W 58 0 GPIO 58 control bit D27 R W GPIOS9 0 GPIO 59 control bit D28 R W 60 0 GPIO 60 control bit D29 R W GPIO61 0 GPIO 61 control bit D30 R W 62 0 GPIO 62 control bit D31 R W GPIO63 0 GPIO 63 control bit GPIO Control Address A090 2074 Register 2 Bit s Access Mnemonic Reset Description DOO R W GPIO64 0 GPIO 64 control bit D01 R W GPIO65 0 GPIO 65 control bit D02 R W GPIO66 0 GPIO 66 control bit D03 R W GPIO67 0 GPIO 67 control bit D04 R W GPIO68 0 GPIO 68 control bit D05 R W GPIO69 0 GPIO 69 control bit D06 R W GPIO70 0 GPIO 70 control bit D07 R W GPIO71 0 GPIO 71 control bit D08 R W GPIO72 0 GPIO 72 control bit D09 R W GPIO73 0 GPIO 73 control bit D10 R W GPIO74 0 GPIO 74 control bit R W GPIO75 0 GPIO 75 control bit D12 R W GPIO76 0 GPIO 76 control
102. Hardware Reference NS9215 bp rotate bp RIGHT 1 calculation done The 6 bit result resides in bit locations 28 23 result crc gt gt 23 amp Ox3f return result EXTERNAL DMA transfers External DMA E R external interface provides two external channels for external peripheral support Each DMA channel moves data from the source address to the destination address These addresses can specify any peripheral on the AHB bus but ideally they specify an external peripheral and external memory DMA transfers Initiating DMA transfers Processor initiated External peripheral initiated www digiembedded com DMA transfers can be specified as burst oriented to maximize AHB bus efficiency transfers are performed in two steps 1 Data is moved from the source address to a 32 byte buffer in the DMA control logic 2 data is moved from the 32 byte buffer to the destination address These two steps are repeated until the DMA transfer is complete Note Optimal performance is achieved when both the source address and destination address are aligned DMA transfers can be initiated in one of two ways processor initiated and external peripheral initiated The processor must do these steps in the order shown 1 Setupthe required buffer descriptors 2 Configure the DMA Control register for each channel 3 Writealto both the CE field and the CG fie
103. J5 tdo output to tck falling 2 5 10 ns tk A out tms trst n Notes Maximum tck rate is 10 MHz 2 out is an asynchronous output driven off of the CPU clock 3 trt is an asynchronous input 510 Hardware Reference NS9215 Clock timing System PLL reference clock timing TIMING Clock timing 00000000000 0 0 0 0 0 0 0 0 0 000000000000000000000000 All AC characteristics measured with 10pF unless otherwise noted Parm Description Min Max Unit Notes SCI xl sys osc cycle time 25 50 ns SC2 xl sys osc high time SC1 2 x 0 45 SC1 2 x 0 55 ns SC3 sys osc low time SC1 2 x 0 45 SC1 2 x 0 55 ns The diagram below pertains to clock timing 2 50 X1 sys osc www digiembedded com 511 512 Hardware Reference NS9215 Packaging CHAPTER 1 7 Bax is the processor package 265 LF XBGA Diagrams that follow show the processor dimensions top bottom and side views Package 513 PACKAGING Processor Dimensions A1 BALL PAD CORNER 514 Hardware Reference NS9215 www digiembedded com 20 40 0 05 o 32 1201 418 SEATING PLANE 1 54 0 10 ES 0 70 0 05 __ I 0 32 0 05 PACKAGING Processor Dimensions 515
104. Line Control register 0x10c DLAB 0x1 Enables access to baud rate registers UART Baud Rate Divisor LSB DLR 0 0 Set baud rate to 9600 bps 0x100 MSB defaults to 0 0 UART Line Control register 0x10c DLAB 0x0 Disables access to baud rate registers WLS 0x3 8 bits per character UART FIFO Control register 0x108 FIFOEN 0x01 Enable RX and TX FIFOs 386 Hardware Reference NS9215 Control register SERIAL CONTROL MODULE UART Baud rate generator Comment UART Interrupt Enable register ETBEI 0 Enable the Transmitter Holding 0x104 Register Empty Interrupt enables the Wrapper to write a transmit character to the UART Wrapper Configuration register TX FLOW 1 TX Enabled Software RXEN 1 Enable Wrapper receive function TXEN 1 Enable Wrapper transmit function Baud rate generator The baud rate clock is generated by dividing the system reference clock by a Baud rates www digiembedded com programmable divisor use this formula BR BRD x 16 The default reference clock for the UARTs is the system reference clock input on 1 sys osc The UART reference clock optionally can be input on GPIO A 3 This table shows the baud rates achieved with CLK set to 29 4912 1 1 843 299 2 921 600 4 460 800 8 230 400 16 115 200 32 57 600 48 38 400 64 28 800 96 19 200 128 14 400 192 9 600 384 4 800 768 2 400 387 SERIAL CONTROL MODULE UART Hard
105. N A D00 R W CSD2 0 1 Chip select 2 disable 0 Disable chip select Enable chip select System Memory Chip Select 3 Static Memory Base and Mask registers Addresses A090 0208 020C These control registers set the base and mask for system memory chip select 3 with a minimum size of 4K The powerup default settings produce a memory range of www digiembedded com 0 7000 0000 Ox7FFF 197 SYSTEM CONTROL MODULE Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select 3 base CS3B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip select 3 base CS3B Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select 3 mask 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip select 3 mask CS3M Reserved CSD3 Register bit assignment Bits Access Mnemonic Reset Description D31 12 R W CS3B 0x70000 Chip select 3 base Base address for chip select 3 D11 00 N A Reserved N A N A D31 12 R W CS3M 0 0000 Chip select 3 mask Mask or size for chip select 3 D11 01 N A Reserved N A N A D00 R W CSD3 0 1 Chip select 3 disable 0 Disable chip select Enable chip select Gen ID register Address A090 0210 This register is read only and indicates the state of addr 19 09 pins at powerup 198 Hardware Reference NS9215 Register Register bit assignment SYSTEM CONTROL MODULE External Interrupt 0 3 Control register Bits Access Mnemo
106. N A do not modify D08 R W EW Extended wait 252 Hardware Reference NS9215 0 Extended wait disabled reset value on reset_n 1 Extended wait enabled Extended wait uses the Static Extended Wait register to time both the read and write transfers rather than the Static Memory Read Delay 0 3 registers and Static Memory Write Delay 0 3 registers This allows much longer transactions Extended wait also can be used with the ns ta strb signal to allow a slow peripheral to terminate the access In this case the Static Memory Extended Wait register can be programmed with the maximum timeout limit A high value on ns ta strb 15 then used to terminate the access before the maximum timeout occurs Note Extended wait and page mode cannot be selected simulta neously www digiembedded com MEMORY CONTROLLER StaticMemory Configuration 0 3 registers Bits Access Mnemonic Description D07 R W PB Byte lane state 0 For reads all bits in byte lane 3 0 are high For writes the respective active bits in byte lane 3 0 are low reset value for chip select 0 2 and 3 on reset n 1 For reads the respective active bits in byte lane 3 0 are low For writes the respective active bits in byte lane 3 0 are low Note Setting this bit to 0 disables the write enable signal WE n will always be set to 1 that is you must use byte lane select signals The byte lane state bit PB enables different types of memory to be connected For byte wide st
107. R W POL 0 Control signal polarity Defines the active polarity of the dma_req dma_done and PDEN signals 0 Active high signals 1 Active low signals D17 R W MODE 0 Fly by mode Defines the direction of data movement for fly by transfers 0 Peripheral to memory fly by write DMA transfer 1 Memory to peripheral fly by read DMA transfer Note This field is not used for DMA transfers initiated by writing a 1 to the CG field in this register 029 www digiembedded com 349 EXTERNAL DMA Status and Interrupt Enable register 5 Access Reset Description D16 R W RST 0 Reset Forces a reset of the DMA channel Writing a 1 to this field forces all fields in this register except the index field to the reset state The reset field is written with the value specified on signals HWDATA 9 0 This field always reads back a 0 Note Writing 1 to this field while the DMA channel is operational will have unpre dictable results D15 10 R STATE 0 State 0 Idle 1 3 Buffer descriptor read 4 7 Data transfer 8 12 Buffer descriptor update 13 Error 009 00 INDEX 0 Index Identifies the current 16 byte offset pointer relative to the buffer descriptor pointer Note This field can be written to only when the RST field D16 is being written to a 1 Status and Interrupt Enable register Address A080 0008 A080 0018 The DMA Status and Interrupt Enable register con
108. R WITC OFLOW Enable overflow error Indicates that an overflow occurred in the UART s 4 character FIFO Note This should not happen in a properly configured system D18 PARITY Parity error Indicates that at least one character has been received with a parity error D17 R WITC FRAME Frame error Indicates that at least one character has been received with a framing error D16 BREAK Line break Indicates that a line break condition has occurred D15 BGAP Buffer gap Indicates that a buffer gap timeout event has occurred 14 R WITC RXCLS Software receive close Indicates a software initiated buffer close has completed D13 R WITC CGAP Character gap Indicates that a character gap timeout event has occurred D12 R WITC MATCH4 Character match4 Indicates that a receive character match has occurred against the Receive Match Register 4 396 Hardware Reference NS9215 Bits D11 55 R W1TC Mnemonic MATCH3 Reset 0 SERIAL CONTROL MODULE UART Interrupt Status register Description Character match3 Indicates that a receive character match has occurred against the Receive Match Register 3 D10 R W1TC MATCH2 Character match2 Indicates that a receive character match has occurred against the Receive Match Register 2 D09 R W1TC Character match1 Indicates that a receive character match has occurred against the Receive Match Register 1
109. ROVR counter carry bit D02 R C CIRFR 0 Carry register 1 RFRG counter carry bit D01 R C 0 Carry register 1 RJBR counter carry bit D00 N A Reserved N A N A Carry Register 2 www digiembedded com Address A060 0734 311 ETHERNET COMMUNICATION MODULE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 e e2 C2 reva C2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TeK xc TNC Reserved Register bit assignment Bits Access Mnemonic Reset Description D31 20 N A Reserved N A N A D19 R C C2TJB 0 Carry register 2 TJBR counter carry bit D18 R C C2TFC 0 Carry register 2 TFCS counter carry bit D17 N A Reserved N A N A D16 R C C2TOV 0 Carry register 2 TOVR counter carry bit D15 R C C2TUN 0 Carry register 2 TUND counter carry bit D14 R C 2 0 Carry register 2 counter carry bit D13 R C C2TBY 0 Carry register 2 TBYT counter carry bit D12 R C C2TPK 0 Carry register 2 TPKT counter carry bit D11 R C C2TMC 0 Carry register 2 TMCA counter carry bit D10 R C C2TBC 0 Carry register 2 TBCA counter carry bit D09 N A Reserved N A N A D08 R C C2TDF 0 Carry register 2TDFR counter carry bit D07 R C C2TED 0 Carry register 2 TEDF counter carry bit D06 R C C2TSC 0 Carry register 2 TSCL counter carry bit D05 R C C2TMA 0 Carry register 2 TMCL counter carry bit D04 R C C2TLC 0 Carry register 2
110. RX IDLE Register bit assignment Bits Access Mnemonic Reset Description D31 22 R W Not used 0 Write this field to 0 D21 R WITC HINT 0 HDLC interrupt Indicates that the HDLC has generated an interrupt D20 N A Reserved N A N A D19 R WITC OFLOW 0 Enable overflow error Indicates that an overflow occurred in the HDLC s 4 byte FIFO Note This should not happen in a properly configured system D18 ICRC 0 Invalid CRC Indicates that a frame has been received with a CRC error D17 R WITC 0 Valid CRC Indicates that a frame has been received with a valid CRC D16 RABORT 0 Receive abort error Indicates that a frame has been received with an abort D15 N A Reserved N A N A D14 R WITC RXCLS 0 Software receive close Indicates a software initiated buffer close has completed D13 04 N A Reserved N A N A D03 R WITC TBC 0 Transmit buffer close Indicates that transmission of the last byte in a transmit buffer has completed D02 R WITC RBC 0 Receive buffer close Indicates that a HDLC receive buffer close condition has occurred These are HDLC receive buffer close events Receive overrun detected 2 Receive abort detected 3 Buffer closed due to invalid CRC 4 Bufferclosed due to valid CRC 426 Hardware Reference NS9215 SERIAL CONTROL MODULE HDLC HDLC Data Register Bits Access Mnemonic Reset Description D01 R WITC TX IDLE 0 Transmit idle Indicates that the transmitter has
111. Read as 0 Reserved D17 00 R W Reset 0x00000 TMCA Incremented for each broadcast frame transmitted excluding multicast frames D31 18 R Reset Read as 0 Reserved D17 00 R W Reset 0x00000 TBCA Incremented for each frame that was deferred on its first transmission attempt This counter does not include frames involved in collisions Reserved D31 12 R Reset Read as 0 D11 00 R W Reset 0x000 TDFR Incremented for frames aborted because they were deferred for an excessive period of time 3036 byte times Reserved D31 12 R Reset Read as 0 D11 00 R W Reset 0x000 TEDF Incremented for each frame transmitted that experienced exactly one collision during transmission D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 TSCL 308 Hardware Reference NS9215 Transmit multiple collision packet counter A060 0700 Transmit late collision packet counter A060 0704 Transmit excessive collision packet counter A060 0708 Transmit total collision packet counter A060 070C Transmit jabber frame counter A060 0718 Transmit FCS error counter A060 071C www digiembedded com ETHERNET COMMUNICATION MODULE Statistics registers Incremented for each frame transmitted that experienced 2 15 collisions including any late collisions during transmission D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 TMCL Incremented for each frame transmitted that experienced a late
112. Register 31 30 29 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 11 10 9 8 7 6 5 4 3 2 1 0 MRDD Register bit assignment Bits Access Mnemonic Reset Description D31 16 N A Reserved N A N A D15 00 R MRDD 0x0000 MII read data Read data is obtained by reading from this register after an Management read cycle An MII Management read cycle is executed by loading the MII Management Address register then setting the READ bit to 1 in the Management Command register Read data is available after the BUSY bit in the MII Management Indicators register returns to 0 MII Management Indicators register Address A060 0434 Register 31 30 29 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MIILF VALE SCAN BUSY Register bit assignment Bits Access Mnemonic Reset Description D31 04 N A Reserved N A N A D03 R MIILF 0 MII link failure www digiembedded com When set to 1 indicates that the PHY currently has a link fail condition 299 ETHERNET COMMUNICATION MODULE Bits Access Mnemonic Reset D02 R NVALID 0 Description Read data not valid When set to 1 indicates that the MII Management read cycle has not completed and the read data is not yet valid Also indicates that SCAN READ is not valid for automatic scan reads 01 R SCAN 0 Automatically scan for read data in progress When set to 1 indicates that continuous MII Manageme
113. Reserved Register bit assignment Bits Access Reset Description D31 24 N A Reserved N A N A D23 R W EIC 0x0 AHB Error Interrupt Clear Write a 1 then a 0 to this register to clear the AHB error interrupt and to clear the AHB Error Detect Status 1 and AHB Error Detect Status 2 registers D22 05 N A Reserved N A N A D04 R W SERDC 0 0 AHB Slave Error Response Detect Config 0 Record error only 1 Generate IRQ D03 00 N A Reserved N A N A Timer Master Control register Address A090 0024 The Timer Master Control register resets and enables the timer in groups which is useful when using the timers in PW applications Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved T9RSE TOLSE T HSE T8RSE T8LSE T8HSE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T RSE 715 T7HSE T6RSE TGLSE TSE 7 T6E TIE TOE 162 Hardware Reference NS9215 Register bit assignment www digiembedded com SYSTEM CONTROL MODULE Timer Master Control register Bits Access Mnemonic Reset Description D31 22 N A Reserved N A N A D21 R W TORSE 0x0 Timer 9 reload step enable 0 Reload Step register disabled 1 Reload Step register enabled D20 R W TOLSE 0x0 Timer 9 low step enable 0 Low Step register disabled 1 Low Step register enabled D19 R W 5 0 0 Timer 9 high step enable 0 Step regist
114. Reserved DADR Reserved RADR www digiembedded com 297 ETHERNET COMMUNICATION MODULE Management Write Data register Register bit assignment Bits Access Mnemonic Reset Description D31 13 N A Reserved N A N A D12 08 R W DADR 0x00 MII PHY device address Represents the 5 bit PHY device address field for management cycles Up to 32 different PHY devices can be addressed D07 05 N A Reserved N A N A D04 00 R W RADR 0x00 MII PHY register address Represents the 5 bit PHY register address field for management cycles Up to 32 registers within a single PHY device can be addressed MII Management Write Data register Address A060 042C Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MWTD Register bit assignment Bits Access Reset Description D31 16 N A Reserved N A N A D15 00 R W MWTD 0x0000 MII write data When this register is written an MII Management write cycle is performed using this 16 bit data along with the preconfigured PHY device and PHY register addresses defined in the Management Address register The write operation completes when the BUSY bit in the MII Management Indicators register returns to 0 MII Management Read Data register Address A060 0430 298 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE MII Management Indicators register
115. SWTCS 0x0 Software watchdog timer clock select 000 System memory clock 2 001 System memory clock 4 010 System memory clock 8 011 System memory clock 16 100 System memory clock 32 101 System memory clock 64 110 Reserved 111 Reserved Software Watchdog Timer Address A090 0178 The Software Watchdog Timer register services the watchdog timer www digiembedded com 179 SYSTEM CONTROL MODULE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Watchdog Timer 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Watchdog Timer Register bit assignment Access Reset Description D31 00 R W Watchdog timer 0 0 Watchdog timer m A read to this register gives the current value of the watchdog timer but will not change the contents m write to the register changes the contents based on the write data value Clock Configuration register Address A090 017C The Clock Configuration register enables and disables clocks to each module on the AHB bus Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 180 Hardware Reference NS9215 Register bit assignment www digiembedded com Bits D31 29 Access R W Mnemonic CSC Reset 0x000 SYSTEM CONTROL MODULE Clock Configuration register Description Clock scale control 000 Full speed 149 9136 74 9568 001 Divide by 2 74 9568 37 4784 010 Divide by 4 37 4784 18 7392
116. Station Address registers beginning on page 300 m Accept all frames m Accept all multicast frames Accept all multicast frames using and HT2 registers See Sample hash table code on page 334 m Accept all broadcast frames The filtering conditions are independent of each other for example the Station Address Logic register can be configured to accept all broadcast frames and frames to the programmed destination address receiver provides the station address logic with a 6 bit value that is the upper 6 bits of a 32 bit CRC calculation performed on the 48 bit multicast destination address This 6 bit value addresses the 64 bit multicast hash table created in the HT1 and HT2 registers See Sample hash table code on page 334 m f the current receive frame is a multicast frame and the 6 bit CRC addresses a bit in the hash table that is set to 1 the receive frame is accepted otherwise the frame is rejected See Sample hash table code on page 334 for sample C code to calculate hash table entries Statistics module www digiembedded com The Statistics module counts and saves Ethernet statistics in several counters see Statistics registers on page 303 The Ethernet General Control Register 2 contains three statistics module configuration bits m AUTOZ Enable statistics counter clear on read m CLRCNT Clear statistics counters m STEN Enable statistics counters If any of the c
117. TLCL counter carry bit D03 R C C2TXC 0 Carry register 2 TXCL counter carry bit D02 R C C2TNC 0 Carry register 2 TNCL counter carry bit D01 00 N A Reserved N A N A Carry Register 1 Address A060 0738 Mask register 312 Hardware Reference NS9215 Register Register bit assignment www digiembedded com ETHERNET COMMUNICATION MODULE Statistics registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EEUU e Tn Hes MES 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rek nec mxc pxu MIRAL usea mco mcs RUN n Aus used Bits Access Mnemonic Reset Description D31 R W M164 Mask register 1 TR64 counter carry bit mask D30 R W M1127 Mask register TR127 counter carry bit mask D29 R W M1255 Mask register TR255 counter carry bit mask D28 R W M1511 Mask register TR511 counter carry bit mask D27 R W MIIK Mask register 1 counter carry bit mask D26 R W MIMAX Mask register 1 TRMAX counter carry bit mask D25 R W MIMGV Mask register 1 TRMGV counter carry bit mask D24 17 N A Reserved N A N A D16 R W MIRBY Mask register 1 RBYT counter carry bit mask D15 R W MIRPK Mask register 1 RPKT counter carry bit mask D14 R W Mask register 1 RFCS counter carry bit mask D13 R W Mask register 1 RMCA counter carry bit mask
118. Use the BITORDER bit in Serial Channel B A C D Control Register A SPI slave mode 2 and 3 2 byte transfer POs SAI CLK Out Mock 2 SA CLK Out Mock 3 ED XEBA AXA XLA SP6 k SPI taln moO OE CX AEX XXX Note SPI data can be reversed such that LSB is first Use the BITORDER bit in Serial Channel B A C D Control Register A 508 Hardware Reference NS9215 Reset hardware strapping timing Reset and hardware strapping timing AC characteristics are measured with 10pF unless otherwise noted The next table describes the values shown in the IEEE 1284 timing diagram Parm Description Unit Notes reset n minimum time 10 xl sys osc 1 clock cycles R2 reset n to reset done NOR flash 4 5 ms SPI flash 15 Note The hardware strapping pins are latched 5 clock cycles after reset n is deasserted goes high VAP V VUV VUV UV V AA AAA Ri reset_n C reset done www digiembedded com 509 TIMING JTAG timing All AC characteristics are measured with 10pF unless otherwise noted The next table describes the values shown in the J TAG timing diagram Description Min Max Unit tms input setup to tck rising 5 ns J2 tms input hold to tck rising 2 ns J3 tdi input setup to tck rising 5 ns tdi input hold to tck rising 2 ns
119. Valid 0b1010 Valid R6 Fault Address register Access instructions www digiembedded com Register R6 accesses the Fault Address register FAR The Fault Address register contains the modified virtual address of the access attempted when a data abort occurred This register is updated only for data aborts not for prefetch aborts it is updated also for alignment faults and external aborts that occur while the MMU is disabled Writing R6 sets the Fault Address register to the value of the data written This is useful for debugging to restore the value of a Fault Address register to a previous state The CRm and opcode 2 fields SHOULD BE ZERO when reading or writing R6 Use these instructions to access the Fault Address register 0 Rd c0 0 read FAR MCR pl5 0 Rd 0 write FAR 93 WORKING WITH THE CPU R7 Cache Operations register Write instruction Cache functions Register R7 controls the caches and write buffer The function of each cache operation is selected by the opcode 2 and CRm fields in the MCR instruction that writes to CP15 R7 Writing other opcode 2 Or CRm values is UNPREDICTABLE Reading from R7 is UNPREDICTABLE With the exception of the two test and clean operations see Cache operation functions on page 95 and Test and clean DCache instructions on page 96 Use this instruction to write to the Cache Operations register 5 opcode 1 Rd CRn CRm op
120. W ECLK 0 External clock mode 0 The HDLC module will use separate external receive and transmit clocks 1 HDLC receiver and transmitter will both use the external transmit clock D00 R Not used 0 Always write 0 to this bit HDLC Clock Divider Low Address 9002 9118 430 Hardware Reference NS9215 SERIAL CONTROL MODULE HDLC HDLC Clock Divider High Use the HDLC CLock Divider Low register to set bits 07 00 of the clock divider This is the equation for the HDLC clock rate 29 4912 MHz HDLC rate bps 16 x DIV 1 Register 31 30 29 7 5 25 24 23 22 21 20 19 18 17 16 Not used Not used DM Register bit assignment Bits Access Mnemonic Reset Description D31 08 R Not used 0 Write this field to 0 D07 00 R W DIVL 0 Eight LSBs ofthe divider that generates the HDLC transmit and receive clock HDLC Clock Divider High Address 9002 911C Use the HDLC CLock Divider High register to set bits 14 08 of the clock divider Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 www digiembedded com 431 assignment 432 SERIAL CONTROL MODULE HDLC Register bit Bits Access Mnemonic Reset Description D31 08 R Not used 0 Write this field to 0 D07 R W EN 0 Clock enable Must be set when the internal clock is used D06 00 R W DIVH 0 Seven MSBs of the divider that generates the HDLC transmit and receive clock Hardware Reference NS9215 SERIAL CONTROL MODU
121. Window Retry register If this bit is set the TX_WR logic stops processing frames and sets the TXERR bit in the Ethernet Interrupt Status register D11 D10 TXAED TXAEC 0x0 0x0 TX abort excessive deferral When set indicates that the frame was deferred in excess of 6071 nibble times in 100 Mbps or 24 287 times in 0 Mbps mode This causes the frame to be aborted if the excessive deferral bit is set to 0 in MAC Configuration Register 2 If TXAED is set the TX_WR logic stops processing frames and sets the TXERR bit in the Ethernet Interrupt Status register TX abort excessive collisions When set indicates that the frame was aborted because the number of collisions exceeded the value set in the Collision Window Retry register If this bit is set the TX_WR logic stops processing frames and sets the TXERR bit in the Ethernet Interrupt Status register D09 www digiembedded com TXAUR 0x0 TX abort underrun When set indicates that the frame was aborted because the TX FIFO had an underrun If this bit is set the TX WR logic stops processing frames and sets the TXERR bit in the Ethernet Interrupt Status register 285 ETHERNET COMMUNICATION MODULE Bits Access Mnemonic Reset D08 R TXAJ 0x0 Description TX abort jumbo When set indicates that the frame s length exceeded the value set in the Maximum Frame register TXAJ is set only if the HUGE bit in MAC Configuration R
122. a two bit Bandwidth Reduction Field BRF to determine how often each channel can arbitrate for the system bus 100 75 50 or 25 A BRF value of 25 for example causes a channel to be skipped every 3 or 4 cycles The BRC gates the bus requesting signals going into a 16 entry Bus Request register BRR As a default unassigned channels in the BRC block the corresponding BRR entries from being set by any bus request signals On powerup only the CPU is assigned to one of the channels with 100 bandwidth strength as the default setting 1 Thearbiter evaluates the BRR at every bus clock until one or more bus requests are registered 138 Hardware Reference NS9215 SYSTEM CONTROL MODULE System bus arbiter 2 Thearbiter stops evaluating the BRR until a bus grant is issued for the previous evaluation cycle 3 Thearbiter grants the bus to requesting channels in a round robin manner at the rising clock edge of the last address issued for the current transaction note that each transaction may have multiple transfers when a SPLIT response is sampled by the arbiter or when the bus is idling 4 Each master samples the bus grant signal hgrant x at the end of the current transfer as indicated by the nready signal The bus master takes ownership of the bus at this time 5 Thearbiter updates the hmaster 3 0 Signals at the same time to indicate the current bus master and to enable the new master s address and control signals to the syst
123. and slave module commands beginning on page 449 D07 00 W TXDATA 0x0 Transmit data to PC bus Status Receive Data register Address 9005 0000 The Status Receive Data register STATUS RX DATA REG is the primary interface register for receipt of data between the I O hub and 2 bus This register is read only Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 5 RDE SCMDL IROCD RXDATA Register bit assignment Access Mnemonic Description D31 16 N A Reserved N A N A D15 R BSTS N A Bus status master only OBus is free Bus is occupied 14 R RDE N A Receive data enable rx data en Received data is available www digiembedded com 451 2 MASTER SLAVE INTERFACE Bits Access Mnemonic Reset Description D13 R SCMDL N A Slave command lock The Slave Command register is locked D12 R MCMDL N A Master command lock The Master Command register is locked D11 08 R IRQCD N A Interrupt codes irq_code The interrupt is cleared if this register is read See Interrupt Codes on page 455 for more information 07 00 R RXDATA N A Received data from C bus Together with a DATA interrupt this register provides a received byte see Master slave interrupt codes on page 455 Master Address register Address 9005 0004 If using 7 bit addressing the master device address field uses only bi
124. and error handling Overview The I2C module is designed to be a master and slave The slave is active only when the module is being addressed during an I2C bus transfer the master can arbitrate for and access the I2C bus only when the bus is free idle therefore the master and slave are mutually exclusive Physical I C bus The physical 12 bus consists of two open drain signal lines serial data SDA and serial clock SCL Pullup resistors are required see the standard 12 bus specification for the correct value for the application Each device connected to the bus is software addressable by a unique 7 or 10 bit address and a simple master slave relationship exists at all times A master can operate as a master transmitter writes or a master receiver reads The slaves respond to the received commands accordingly e In transmit mode slave is read the host interface receives character based parallel data from the ARM The module converts the parallel data to serial format and transmits the serial data to the 12 bus In receive mode slave is written to the 2 bus interface receives 8 bit based serial data from the IC bus The module converts the serial data to parallel format and interrupts the host The host s interrupt service routine reads the parallel data from the data register inside the 2 module The serial data stream synchronization and throttling are done by modulating the www digiembedded com 4
125. as part of the RX initialization process RXINIT is set in the Ethernet General Status register when the initialization process is complete and ERXINIT must be cleared before enabling frame reception from the MAC The delay from ERXINIT set to RXINIT set is less than five microseconds D18 13 N A Reserved N A N A D12 R W Not used 0 Always write as 0 DII R W RXSHFT 0 Shift RX data 0 Standard receive format No padding bytes added before receive frame data 1 Thereceiver inserts 2 bytes of padding before the first byte of the receive data to create longword alignment of the payload www digiembedded com 281 ETHERNET COMMUNICATION MODULE Ethernet General Control Register 2 Bits Access Reset Description D10 R W RXALIGN 0 Align RX data 0 Standard receive format The data block immediately follows the 14 byte header block 1 receiver inserts 2 byte padding between the 14 byte header and the data block causing longword alignment for both the header and data blocks D09 R W MAC HRST 1 MAC host interface soft reset 0 Restore MAC STAT SAL RX WR and TX RD to normal operation 1 Reset MAC STAT programmable registers in SAL RX WR and TX RD Keep high for minimum of 5usec to guarantee that all functions get reset D08 R W ITXA 0 Insert transmit source address 0 Source address for Ethernet transmit frame taken from data in TX FIFO Insert the MAC Ethernet source a
126. buffer The NS9215 uses one of two drivers 2mA 4mA 27 265 Memory bus interface Pin Signal U D OD Description B9 out 0 4 SDRAM bus clock A15 out 1 4 SDRAM bus clock P12 addr 27 a 3 U UO 4 Address bus Endian 14 addr 26 a 2 U IO 4 Address bus SPI boot 015 addr 25 gpio a 1 U 4 Address bus R12 addr 24 a 0 U 4 Address bus Boot width 1 T13 addr 23 U UO 4 Address bus Boot width 0 014 addr 22 4 Address bus T12 addr 21 4 Address bus 013 addr 20 4 Address bus R11 addr 19 U UO 4 Address bus GENID 10 T11 addr 18 U UO 4 Address bus GENID 9 U12 addr 17 U VO 4 Address bus GENID 8 T10 addr 16 U UO 4 Address bus GENID 7 R9 addr 15 U 4 Address bus GENID 6 Ull addr 14 U UO 4 Address bus GENID 5 U10 addr 13 U 4 Address bus GENID 4 T9 addr 12 U IO 4 Address bus GENID 3 U9 addr 11 U 4 Address bus GENID 2 U8 addr 10 U 4 Address bus GENID 1 T8 addr 9 U 4 Address bus GENID 0 07 addr 8 U 4 Address bus T7 addi 7 U IO 4 Address bus PLL bypass U6 addr 6 U 4 Address bus PLL OD 1 T6 addr 5 U IO 4 Address bus PLL OD 0 05 addr 4 U UO 4 Address bus PLL NR 4 M2 addr 3 U 4 Address bus PLL NR 3 addr 2 U IO 4 Address bus PLL NR 2 L2 addi 1 U 4 Add
127. can be configured to provide a basic PWM function Each PWM function requires concatenating two timer counters resulting in four PWM outputs One of the timer counters controls the pulse width and the other controls the period The basic PWM function is output through GPIO through functions labeled PWM Ch N This diagram illustrates the basic PWM function pwm out 0 Timer Counter 0 pulse wien contio pwm out 0 PWM 0 eriod control gt Timer Counter 1 B 144 Hardware Reference NS9215 SYSTEM CONTROL MODULE Enhanced PWM function Enhanced PWM function Sample enhanced PWM waveform Timer counters 6 9 have additional features to add enhanced PWM functionality High register Compared to the timer counter to toggle PWM output high Low register Compared to the timer counter to toggle PWM output back low m Three 15 bit Step registers associated with four enhanced timer counters The values of Step registers are added when the high low and reload values are reached which allows a steadily variable motor control PWM wave to be generated The enhanced PWM function is output through GPIO through the functions labeled Ext Timer Event Out Ch N for channels 6 to 9 Reload Value High Value High Value Terminal Count FFFF_0000 FFFF 7000 FFFF 000 FFFF FFFF Timer Counter clock frequency
128. clock the maximum data rate is one sixth of the 29 4912 MHz reference clock rate or 4 9152 Mbps The transmitter cannot send an arbitrary number of bits but only a multiple of bytes The receiver however can receive frames of any bit length If the last byte in the frame is not eight bits the receiver sets a status flag that is buffered along with this last byte Software then uses the table shown next to determine the number of valid data bits in this last byte Note that the receiver transfers all bits 416 Hardware Reference NS9215 SERIAL CONTROL MODULE HDLC Data encoding between the opening and closing flags except for the inserted zeroes to the receiver data buffer Last byte bit pattern table Last byte bit pattern bbbbbbb0 7 bbbbbb01 6 bbbbb011 5 bbbb0111 4 bbb01111 3 bb011111 2 b0111111 Data encoding The HDLC module provides several types of data encoding w Normal NRZ m NRZI Biphase Level Manchester m Biphase Space 0 Biphase Mark FM1 Encoding This figure shows examples of the data encoding types examples Biphase Space and Biphase Mark the signal level does not convey information The placement of the transitions determine the data w I nBiphase Level the polarity of the transmission determines the data www digiembedded com 417 SERIAL CONTROL MODULE HDLC Digital phase locked loop DPLL operati
129. cycle delay filter rejects large and short duration noise spikes that typically occur in motor system applications Each signal is sampled on rising clock edges A time history of the signals is stored in a four bit shift register Any signal is tested for a stable level that is present for three consecutive rising clock edges With this method pulses shorter than a two clock period are rejected Timer counter 5 supports the sampling clock and the counters 147 SYSTEM CONTROL MODULE Interrupt controller FIQ interrupts IRQ interrupts 32 vector interrupt controller The interrupt system is a simple two tier priority scheme Two lines access the CPU core and can interrupt the processor IRQ normal interrupt and FIQ fast interrupt FIQ has a higher priority than IRQ Most sources of interrupts on the processor are from the IRQ line There is only one FIQ source for timing critical applications The FIQ interrupt generally is reserved for timing critical applications for these reasons m Theinterrupt service routine is executed directly without determining the source of the interrupt m Interrupt latency is reduced The banked registers available for FIQ interrupts are more efficient because a context save is not required Note The interrupt source assigned to the FIQ must be assigned to the highest priority which is 0 IRQ interrupts come from several different sources in the processor and are managed using the Inte
130. data bus width is the sum of the memory device databus widths For chip select connected to Select this mapping 32 bit wide memory device 32 bit wide address mapping 16 bit wide memory device 16 bit wide address mapping 4 x 8 bit wide memory devices 32 bit wide address mapping 2 x 8 bit memory devices 16 bit wide address mapping Dynamic Memory RAS and CAS Delay 0 3 registers Address A070 0104 0124 0144 0164 250 Hardware Reference NS9215 Register Register bit assignment MEMORY CONTROLLER StaticMemory Configuration 0 3 registers The Dynamic Memory RAS and CAS Delay 0 3 registers allow you to program the RAS and CAS latencies for the relevant dynamic memory It is recommended that these registers be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode Note The values programmed into these registers must be consistent with the values used to initialize the SDRAM memory device 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CAS Reserved RAS Bits Access Mnemonic Description D31 10 N A Reserved N A do not modify D09 08 R W CAS CAS latency 00 Reserved 01 One clock cycle where the RAS to CAS latency RAS and CAS latency CAS are defined in clk out cycles 10 Two clock cycles 11 Thr
131. delay for asynchronous page mode sequential accesses These registers control the overall period for the read cycle It is recommended that these registers be 256 Hardware Reference NS9215 Register Register bit assignment MEMORY CONTROLLER Static Memory Write Delay 0 3 registers modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Reserved WTPG Bits Access Mnemonic Description D31 05 N A Reserved N A do not modify D04 00 R W WTPG Asynchronous page mode read after the first wait state WAITPAGE 00000 11110 1 out cycle for read access time For asynchronous page mode read for sequential reads the wait state time for page mode accesses after the first read is WAITPAGE x tjj out 11111 32 out cycles read access time reset value on reset n Number of wait states for asynchronous page mode read accesses after the first read Static Memory Write Delay 0 3 registers www digiembedded com Address A070 0214 0234 0254 0274 The Static Memory Write Delay 0 3 registers allow you to program the delay from the chip select to the write access These registers control the overall period for the write cycle It is recommended that these registers be modified during sys
132. descriptors operates in an unpredictable fashion 31 30 29 28 16 15 0 OFFSET 0 Source address OFFSET 4 Reserved Buffer length OFFSET 8 Destination address OFFSET W Reserved Status Field descriptions follow The source address pointer field identifies the starting location of the source data The source address can be aligned to any byte boundary Note Optimal performance is achieved when the source address is aligned on a word boundary Buffer length indicates the number of bytes to move between the source and the destination After completing the transfer the DMA controller updates this field with the actual number of bytes moved This is useful for debugging error conditions or determining the number of bytes transferred before the DONE signal was asserted The description address pointer field identifies the starting location of the source data s destination that is to where the source data needs to be moved The destination address can be aligned to any byte boundary 340 Hardware Reference NS9215 Status Wrap W bit Interrupt I bit Last L bit Full F bit EXTERNAL DMA Descriptor list processing Note Optimal performance is achieved when the destination address is aligned on a word boundary This field is not used Read back 0x0000 The Wrap W bit when set tells the DMA controller that this is the last buffer descrip
133. enter low power or disabled mode These bits can however be changed during normal operation if necessary Note The Dynamic Memory Refresh Timer register is used for all four dynamic memory chip selects The worst case value for all chip selects must be programmed Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved REFRESH Register bit assignment Bits Access Mnemonic Description D31 11 N A Reserved N A do not modify D10 00 R W REFRESH Refresh timer 0x0 Refresh disabled reset value on reset_n 0 1 0 77 n x16 16n clk_out ticks between SDRAM refresh cycles Note The refresh cycles are evenly distributed There might be slight variations however when the auto refresh command is issued depending on the status of the memory controller Dynamic Memory Read Configuration register Address A070 0028 The Dynamic Memory Read Configuration register allows you to configure the dynamic memory read strategy Modify this register only during system initialization Note The Dynamic Memory Read Configuration register is used for all four dynamic memory chip selects The worst case value for all chip selects must be programmed www digiembedded com 237 MEMORY CONTROLLER Dynamic Memory Precharge Command Period register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4
134. error counter A060 06 4 Receive carrier sense error counter A060 06 8 Receive undersize packet counter A060 06CC Receive oversize packet counter A060 06D0 Receive fragments counter A060 06D4 ETHERNET COMMUNICATION MODULE Incremented for each received frame from 64 to 1518 bytes that contains an invalid FCS and has dribble bits that is is not an integral number of bytes D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 RALN Incremented each time a valid carrier was present and at least one invalid data symbol was found D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0 000 RCDE Incremented each time a false carrier is found during idle as defined by a 1 on ER and an on RXD The event is reported with the statistics generated on the next received frame Only one false carrier condition can be detected and logged between frames D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 RCSE Incremented each time a frame is received that is less than 64 bytes in length contains a valid FCS and is otherwise well formed This counter does not look at range length errors D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 RUND Incremented each time a frame is received that exceeds 1518 bytes non VLAN or 1522 bytes VLAN contains a valid FCS and is otherwise well formed This counter does not look at range length errors This counter is no
135. interrupt RX data FIFO overflowed For proper operation reset the receive packet processor using the ERX bit in the Ethernet General Control Register 1 when an overflow condition occurs D24 R C RXOVFL STAT 0 Assigned to RX interrupt RX status FIFO overflowed D23 R C RXBUFC 0 Assigned to RX interrupt I bit set in receive Buffer Descriptor and buffer closed D22 R C RXDONEA 0 Assigned to RX interrupt Complete receive frame stored in pool A of system memory 317 ETHERNET COMMUNICATION MODULE Ethernet Interrupt Status register 318 Bits Access Mnemonic Reset Description D21 R C RXDONEB 0 Assigned to RX interrupt Complete receive frame stored in pool B of system memory D20 R C RXDONEC 0 Assigned to RX interrupt Complete receive frame stored in pool C of system memory D19 R C RXDONED 0 Assigned to RX interrupt Complete receive frame stored in pool D of system memory D18 R C RXNOBUF 0 Assigned to RX interrupt No buffer is available for this frame due to one of these conditions m four buffer rings being disabled m four buffer rings being full m No available buffer big enough for the frame 017 RXBUFFUL 0 Assigned to RX interrupt No buffer is available for this frame because all four buffer rings are disabled or full D16 R C RXBR 0 Assigned to RX interrupt New frame available in the FIFO This bit is used for diagnostics D15 07 N A Reserved N A N A D0
136. is set in the current buffer descriptor D15 00 R BLENSTAT 0 0 Debug field indicating the current byte count Module Direct Mode TX Data FIFO Addresses 9000 0028 9000 8028 9001 0028 9001 8028 9002 0028 9002 8028 9003 0028 The Direct Mode TX Data register is used when in direct mode of operation to write the TX data FIFO The write can be 8 16 or 32 bit Register 31 30 29 28 7 26 25 24 22 21 20 19 18 17 16 TO 15 4 13 12 10 9 8 6 5 4 3 2 1 0 TO 382 Hardware Reference NS9215 31 March 2008 I O MODULE Module Direct Mode TX Data Last FIFO Register bit assignment Bit s Access Mnemonic Reset Description D31 00 W TXD 0x0 TX Data FIFO Write register Module Direct Mode TX Data Last FIFO Addresses 9000 002 9000 802 9001 002 9001 802 9002 002 9000 802 9003 002 The Direct Mode TX Data LAst FIFO register is used when in direct mode of operation to write to the TX data FIFO and to cause a last status flag to be set for use by the peripheral The write can be 8 16 or 32 bit Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TXDL Register bit assignment 5 55 Reset Description D31 00 W TXDL 0x0 TX Data with Last Status FIFO Write register www digiembedded com 383 I O MODULE Module Direct Mode TX Data Last 384 Hardware Reference NS9215 3 March 2008
137. master System boot over SPI operation NET4SPI ASIC boots from an external non volatile serial memory device The device can be either a serial EEPROM or a serial Flash In either case the device must support a four wire mode0 compatible SPI interface The boot over SPI hardware interfaces to devices requiring 8 bit address 16 bit address or 24 bit address The address width is indicated by strapping pins boot mode 1 0 436 Hardware Reference NS9215 Available strapping options EEPROM FLASH header Header format www digiembedded com SERIAL CONTROL MODULE SPI System boot over SPI operation boot_mode 1 0 Address width 00 Disabled 01 8 bit address 10 16 bit address 11 24 bit address The boot over SPI hardware requires several pieces of user supplied information to complete the boot operation This information must be located in a 128 byte header starting at address zero in the external memory device Each entry in the header is four bytes long This is the format of the 128 byte header Entry Description 0x0 Size 19 0 Total number of words to fetch from the SPI EEPROM 31 20 reserved The total must include the 32 word header Code image size in bytes 128 4 0 4 Mode 27 0 All SDRAM components contain a Mode register This 31 28 reserved register contains control information required to successfully access the component The fields available in any SDRAM speci
138. nennen 347 DMA Status and Interrupt Enable register 350 DMA Peripheral Chip Select 352 Chapter 8 AES Data Encryption Decryption Module 355 FETUS 355 356 Data 356 AES DMA buffer 4 4 356 AES buffer descriptor 357 Source address pointer Hn 357 Source buffer length RARE MEER UK 357 Destination buffer nn 357 Destination address 22 0202002 2 0 4 357 pisse 357 0 358 WRAP W Ee cea 358 interrupt 358 Hardware Reference NS9215 Last DIES 358 Full E 358 T 359 ECB eet 359 Processing flow 2 0 359 CBC CFB OFB CTR processing
139. on character 389 Example confg rat lol atra xri e cd ehe 389 Wrapper Control and Status 390 Register address map 390 Wrapper Configuration register 391 Interrupt Enable 4 mens 393 Interrupt Status register inset et ibt exin en UNE EAE Ee i gees 395 Receive Character GAP Control 5 398 Receive Buffer GAP Control register 399 Receive Character Match Control 399 Receive Character Based Flow Control register 400 Force Transmit Character Control 5 402 ARM Wakeup Control register esses 403 Transmit Byte REESE NEU 404 VART Recelve Poo ret ed arca it Ea 405 VART Transmit ap 405 UART Baud Rate Divisor LSB
140. onus erroe ane EE ie ner ert nd at 448 I2C command iint rface dur hd pre pr 449 Locked interrupt driven Mode 449 Master module and slave module 5 449 scere LEE 449 pene rcm UTRUM 450 Register address map incer eet eed Yn ei 450 Command Transmit Data 450 ac ipM 450 Register bit 451 Status Receive Data 451 EET 451 22 Hardware Reference NS9215 www digiembedded com Register bit assignment sss meme 451 Master Address register ioco Bet LEO e aeta 452 RTT 452 Register bit 2 2 453 Slave Address 2 7 7 4 4 4 2 4 453 453 Register bit assignment ed 453 Configuration 454 Timing parameter for fast mode 454 UU 454 Register bit assignment esses emen 454 Interrupt CodeS 1 E 455 Master slave interrupt codes 455 Software d
141. or through the DMA controller which is integrated into the 1 0 hub The 12 does not have DMA support 363 I O MODULE Block diagram to SCM Interrupt ANBA Bus Controller AHB Master AHB Slave DMA Controller v Revd Rsd UARTA UARTB UARTC UARTD ND SPI 2 AHB slave The CPU has access to the control and status registers in the DMA controller the interface peripheral devices and the GPIO configuration DMA controller The processor provides an eight channel DMA controller to service the low speed peripherals Each channel has a transmit channel and a receive channel Servicing RX and The DMA controller services the RX and FIFOs in a round robin manner When one of FIFOs the FIFOs needs servicing that is it can accept a burst of four 32 bit words the DMA controller requests the AHB bus through the AHB master After the request has been granted the peripheral buffer data is transferred to or from system memory 364 Hardware Reference NS9215 3 March 2008 Buffer descriptors Source address pointer Buffer length Control 15 W Control 14 I Control 13 L Control 12 F www digiembedded com I O HUB MODULE DMA controller The peripheral buffer data is held in buffers in external memory linked together using buffer descriptors The buf
142. output hold from CLK rising 67 ns 2 S18 CLK falling to CS rising 50 ns S19 CS deassertion time 266 ns 2 Notes 1 SPI slave interface clock duty cycle should be no worse than 60 40 Hardware Reference NS9215 SPI slave timing diagram www digiembedded com SERIAL CONTROL MODULE SPI SPI timing characteristics The numbers shown here are for a 7 5 Mhz SPI slave interface clock rate The numbers shown here are for a 300 Mhz PLL output frequency This value must be proportionally increased with a PLL output frequency decrease This parameter does not depend on any clock frequency SDO ee o 2 17 22513 445 SERIAL CONTROL MODULE SPI SPI timing characteristics 446 Hardware Reference NS9215 2 MASTER SLAVE INTERFACE Physical I2C bus 2 Master Slave Interface 1 3 2 master slave interface provides an interface between the ARM CPU and the 2 bus The 2 master slave interface basically is a parallel to serial and serial to parallel converter The parallel data received from the ARM CPU has to be converted to an appropriate serial form to be transmitted to an external component using the 12C bus Similarly the serial data received from the I2C bus has to be converted to an appropriate parallel form for the ARM CPU The 2 master interface also manages the interface timing data structure
143. procedure to lock down code and data into way i of cache with N ways using format C makes it impossible to allocate to any cache way other than the target cache way Ensure that no processor exceptions can occur during the execution of this procedure for example disable interrupts If this is not possible all code and data used by any exception handlers must be treated as code and data as in Steps 2 and 3 If an ICache way is being locked down be sure that all the code executed by the lockdown procedure is in an uncachable area of memory or in an already locked cache way If a DCache way is being locked down be sure that all data used by the lockdown procedure is in an uncachable area of memory or is in an already locked cache way Ensure that the data instructions that are to be locked down are in a cachable area of memory Be sure that the data instructionsthat are to be locked down are not already in the cache Use the Cache Operations register R7 clean and or invalidate functions to ensure this Write these settings to the Cache Lockdown register R9 to enable allocation to the target cache way CRm 0 Set L 0 for bit i Set L 1 for all other bits For each of the cache lines to be locked down in cache way i If a DCache is being locked down use an LDR instruction to load a word from the memory cache line to ensure that the memory cache line is loaded into the cache ICache is being locked
144. register is the primary Wrapper Configuration register www digiembedded com 475 ANALOG TO DIGITAL CONVERTER ADC MODULE ADC Configuration register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADCEN Reserved INSTAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INTCLR SEL Register bit assignment 5 55 Reset Description D31 R W ADCEN 0 0 The ADC module is disabled and held in reset 1 The ADC module is enabled D30 19 N A Reserved N A N A D18 16 R INSTAT 0 Interrupt status Indicates the channel processed at the time of the interrupt D15 5 N A Reserved N A N A D04 R W INTCLR 0 Interrupt clear The ADC module generates an interrupt each time the ADC generates a new value This bit clears the interrupt The CPU must write a 1 then a 0 to this bit to clear the interrupt D03 R W DMAEN 0 DMA enable If set ADC output data is written to memory using UART D s receive DMA 0 DMA disabled 1 DMA enabled D02 00 R W SEL 000 ADC channel select 476 Controls how many channels are active 000 Channel 0 001 Channels 0 1 010 Channels 0 2 011 Channels 0 3 100 Channels 0 4 101 Channels 0 5 110 Channels 0 6 111 Channels 0 7 Hardware Reference NS9215 ANALOG TO DIGITAL CONVERTER ADC MODULE ADC Clock Configuration register ADC Clock Configuration register Register Register bit assignment Address 9003 9004 The ADC Clock Configuration
145. that only one bus master has access to the system bus at any time If you are using a system in which bus bandwidth allocation is critical you must be sure that your worst case bus bandwidth allocation goals can be met See Arbiter configuration example on page 140 for information about configuring the AHB arbiter The high speed bus system is split into two subsystems High speed peripheral subsystem Connects all high speed peripheral devices to a port on the external memory controller m subsystem Connects the CPU directly to a second port on the external memory controller The high speed bus contains two arbiters one for the ARM926 CPU and one for the main bus m CPU arbiter Splits the bandwidth 50 50 between the data and instruction interfaces If the CPU access is to external memory no further arbitration is necessary the CPU has immediate access to external memory through slave port 0 on the memory controller If CPU access is to one of the peripherals on the main bus however the main arbiter will arbitrate the access Main arbiter Contains a 16 entry Bus Request Configuration BRC register Each BRC entry represents a bus request and grant channel Each request grant channel can be assigned to only one bus master at a time Each bus master can be connected to multiple request grant channels simultaneously however depending on the bus bandwidth requirement of that master Each request grant channel has
146. the acknowledgement can be any interrupt associated with that module When a module is locked another command must not be sent to that module The command lock status can be checked in the STATUS RX DATA REG The 12 master recognizes four high level commands which are used in the CMD field of the Command register the IC slave recognizes two high level commands Description 0x0 No operation 0 4 M READ Start reading bytes from slave 0x5 WRITE Start writing bytes to slave 0x6 M_STOP Stop this transaction give up the bus 0x10 S_NOP No operation This command is necessary for 16 bit mode providing data in TX_DATA_REG without a command 0x16 S_STOP Stop transaction by not acknowledging the byte received Any M READ or WRITE command causes the 2 module to participate in the bus arbitration process when the 2 bus is free idle If the module becomes the new 449 2 MASTER SLAVE INTERFACE bus owner the transaction goes through If the module loses bus arbitration an M ARBIT LOST interrupt is generated to the host processor and the command must be reissued I C registers 000060000000 60 0 0 0000 6000 00 00 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0000 0 0 All registers have 8 bit definitions but must be accessed in pairs For example TX DATA REG and CMD REG ar
147. the AHB arbiter to guarantee bandwidth to a given master These are the conditions in this example m 5 AHB masters CPU Ethernet Rx Ethernet Tx hub and external a AHB clock frequency 75 MHz m X Average access time per 16 byte memory access 4 clock cycles ARM926E S is guaranteed one half the total memory bandwidth In this example the bandwidth for each master can be calculated using this formula Bandwidth per master 75 2 4 clock cycles per access x 5 masters x 16 bytes 60MB master Note The worst case scenario is that there are 90 Mbps total to be split by all 5 masters if this meets the requirements of all the masters the AHB arbiter is programmed like this BRCO 31 24 8 1 0 00 0000 channel enabled 100 ARM7EJ S BRCO 23 16 8 1 0 00 0001 channel enabled 100 Ethernet Rx BRCO 15 8 8 1 0 00 0000 channel enabled 100 Ethernet TX BRCO 7 0 8 b1_0 00 0101 channel enabled 100 IO hub BRC1 31 24 8 bl 0 00 0011 channel enabled 100 Ext DMA 140 Hardware Reference NS9215 SYSTEM CONTROL MODULE BRC1 23 16 8 bl 0 00 0000 channel disabled 15 8 8 1 0 00 0000 channel disabled 7 0 8 1 0 00 0000 channel disabled BRC2 31 24 8 0 0 00 0000 channel disabled BRC2 23 16 8 0 0 00 0000 channel disabled BRC2 15 8 87 0 0 00 0000 channel disabled BRC2 7 0 8 0 0 00 0000 channel disabled BRC3 31 24 8 0 0 00 0000 channel disabled B
148. the CRC and closing flag are transmitted HDLC Data register 3 Address 9002 9108 HDLC Data Register 3 writes the last byte of data of a frame after which the closing flag is transmitted This register is for debug purposes only Register 31 30 29 28 27 26 25 22 2 20 19 18 17 16 Reserved HDATA Register bit assignment Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 00 R W HDATA 0 Read Returns the contents of the receive buffer Write Used for the last data byte in a frame after which the closing flag is transmitted 428 Hardware Reference NS9215 SERIAL CONTROL MODULE HDLC HDLC Control Register 1 HDLC Control Register 1 000000000000 0 0 00 00 0000 0600 0 00 0 00 00 0 00 00 0 0 0000000000000000000000000000000000000 Address 9002 9110 HDLC Control Register 1 configures the HDLC transmitter and receiver Register 31 30 29 28 27 26 2b 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not Reserved HDATA HDATA CLK used HINT Register bit assignment Bits Access Mnemonic Reset Description D31 08 R Not used 0 Write this field to 0 D07 06 R HMODE 0 00 Normal operation 01 Force receiver to flag search mode 10 Normal operation 11 Force transmitter to send abort D05 04 N A Reserved N A N A D03 02 R W CLK 0 Clock source Note This field should be programmed last 00 Reserved 01 Reserved 10 Use external clock 11 Use internal cloc
149. the Ethernet Receive Status register is loaded at the same time Bits 15 0 are also loaded into the status field of the receive buffer descriptor used for the frame Hardware Reference NS9215 Register 31 30 29 28 27 26 25 ETHERNET COMMUNICATION MODULE Ethernet Receive Status register 24 23 22 21 20 19 18 17 16 Reserved RXSIZE 8 7 6 5 4 3 2 1 0 RXDV RXOK RXBR RXMC Rsvd RXDR Reserved RXSHT Reserved Register bit assignment Bits D31 27 Access N A Mnemonic Reserved Reset N A Description N A D26 16 R RXSIZE 0x000 Receive frame size in bytes Length of the received frame in bytes D15 D14 RXCE RXDV 0x0 0x0 Receive carrier event previously seen When set indicates that a carrier event activity an activity on the receive channel that does not result in a frame receive attempt being made was found at some point since the last receive statistics A carrier event results when the interface signals to the PHY have the following values MRXER 1 MRXDV 0 RXD 0xE The event is being reported with this frame although it is not associated with the frame Receive data violation event previously seen Set when the last receive event was not long enough to be a valid frame D13 RXOK 0x0 Receive frame OK Set when the frame has a valid CRC and no symb
150. the closing flag biphase mark and biphase space modes this means the transition that defines the end of the last zero of the closing flag DPLL operation Adjustment ranges and output clocks This figure shows the adjustment ranges and output clock for the different DPLL modes of operation www digiembedded com 419 SERIAL CONTROL MODULE HDLC DPLL operation Adjustment ranges and output clocks Bit cell adj NRZI Clock Bi L ad Bi L Clock Bi S adj 5 Clock B Madi Bi M Clock NRZ and NRZI encoding Biphase Level encoding 420 ipte cese add one addtwo subtract two subtract none ignore transitions subtract one addone ignore transitions none add one ignore transitions subtract one none none add one ignore transitions subtract one none With NRZ and NRZI encoding all transitions occur on bit cell boundaries and the data should be sampled in the middle of the bit cell If a transition occurs after the expected bit cell boundary but before the midpoint the DPLL needs to lengthen the count to line up the bit cell boundaries this corresponds to the add one and add two regions of the figure If a transition occurs before the bit cell boundary but after the midpoint the DPLL needs to shorten the count to line up the bit cell boundaries this corresponds to the subtract o
151. the next buffer descriptor that will be used RXCOFF can be used to determine where the RX_RD logic will put the next packet RX_D Buffer Descriptor Pointer Offset register Address A060 0A34 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RXDOFF Register bit assignment Bits Access Mnemonic Reset Description D31 11 N A Reserved N A N A D10 00 R RXDOFF 0x000 Contains an 11 bit byte offset from the start of the pool D ring The offset is updated at the end of the RX packet and will have the offset to the next buffer descriptor that will be used RXDOFF can be used to determine where the RX_RD logic will put the next packet Transmit Buffer Descriptor Pointer Offset register Address A060 0A38 www digiembedded com 325 ETHERNET COMMUNICATION MODULE Register 31 29 28 27 26 2 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TXOFF Register bit assignment Bits Access Mnemonic Reset Description D31 10 N A Reserved N A N A D09 00 R TXOFF 0x000 Contains a 10 bit byte offset from the start ofthe transmit ring in the TX buffer descriptor RAM The offset is updated at the end of the TX packet and will have the offset to the next buffer descriptor that will be used TXOFF can be used to determine from where the TX WR logic will grab the next packet RX Free Buffer register
152. used to perform the actual decryption Additional data optional Data used to compute the authentication code Note The data must be DMA ed through the AES module twice in CCM mode for both encryption and decryption modes This is the format of the Nonce buffer Bits 127 120 119 8 L par 8 L par 1 0 Contents reserved Nonce Message length This is the CCM buffer descriptor processing flow CCM Mode Encryption CCM Mode Decryption Source DMA Destination DMA Source DMA Destination DMA Operations Operations Operations Operations Key Buffer Key Buffer Nonce Nonce Additional Authentication Data optional Data Buffer Pass 1 Decrypted Data decryption Additional Data Buffer Pass Authentication Authentication 1 Code Data authentication Optional Data Buffer Pass Authentication 2 Encrypted Data 2 Code encryption amp uthentication 361 AES DATA ENCRYPTION DECRYPTION MODULE 362 Hardware Reference NS9215 I O Hub Module E 9 I O hub provides access to the low speed ports the processor through one master port on the AHB bus The low speed ports include four UART ports one SPI port one 12 port 2 multi function controlled ports and one analog to digital A D port UART channel C can be configured for HDLC operation The SPI UART and A D ports can be controlled either directly by the CPU
153. week units BCD digit 0 7 www digiembedded com 463 REAL TIME CLOCK MODULE Time Alarm register Address 9006 0010 The Time Alarm register sets the time alarm BCD is binary coded decimal Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Rsvd PM HR T HR U Rsvd MT M U 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Rsvd ST SU HT HU Register bit assignment Bits 55 Reset Description D31 N A Reserved N A N A D30 R W PM 0x0 PM Used in 12 hour mode only 0 AM 1 PM D29 28 R W HR_T 0x0 Hours tens BCD digit 0 2 D27 24 R W HR_U 0x0 Hours units BCD digit 0 9 D23 N A Reserved N A N A D22 20 R W MT 0x0 Minutes tens BCD digit 0 5 D19 16 R W MU 0x0 Minutes units BCD digit 0 9 D15 N A Reserved N A N A D14 12 R W ST 0x0 Seconds tens BCD digit 0 5 D11 08 R W SU 0x0 Seconds units BCD digit 0 9 D07 04 R W HT 0x0 Hundredths of a second tens BCD digit 0 9 D03 00 R W HU 0x0 Hundredths of a second units BCD digit 0 9 464 Hardware Reference NS9215 REAL TIME CLOCK MODULE Calendar Alarm register Calendar Alarm register Address 9006 0014 The Calendar Alarm register sets the calendar alarm This register programs a specific date and month when an alarm should cause an event You cannot set an alarm that is more than one year in the future BCD is binary coded decimal
154. write transfers which are longer than can be supported by the Static Memory Read Delay registers or the Static Memory Write Delay registers when the EW extended wait bit in the related Static Memory Configuration register is enabled There is only one Static Memory Extended Wait register which is used by the relevant static memory chip select if the appropriate EW bit is set in the Static Memory Configuration register It is recommended that this register be modified during system initialization or when there are no current or outstanding transactions If necessary however these control bits can be changed during normal operation Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Reserved EXTW Register bit assignment Bits Access Mnemonic Description D31 10 N A Reserved N A do not modify D09 00 R W EXTW External wait timeout 0x0 16 clock cycles where the delay is in clk_out cycles 0x1 0x3FF n 1 x 16 clock cycles Example Static memory read write time 16 us CLK frequency 50 MHz This value must be programmed into the Static Memory Extended Wait register 16 x 106 x 50 x 10 16 1 49 Dynamic Memory Configuration 0 3 registers Address A070 0100 0120 0140 0160 www digiembedded com 247 MEMORY CONTROLLER m Dynamic Memory Configuration 0 3 registers Use the Dynamic Memory Configuration 0 3 registers to program the configuration
155. www digiembedded com 409 SERIAL CONTROL MODULE UART UART Line Control register Register 31 30 29 28 27 25 2 a 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SB SP EPS SIB WS Register bit assignment Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 R W DLAB 0 Divisor latch access bit 0 Disabled Enabled Enables the Baud Rate Divisor MSB and LSB registers to be configured D06 R W SB 0 Set break if set TX data is set to 0 0 Disabled Enabled D05 R W SP 0 Stick parity operates as follows m When set bits 04 03 11 parity bit always set to 0 m When set bits 04 03 00 parity bit always set to 1 0 Disabled 1 Enabled D04 R W EPS 0 Parity select 0 Odd parity Even parity D03 R W PEN 0 Parity enable 0 Parity disabled Parity enabled D02 R W STB 0 Number of stop bits 0 1 5 stop bits WLS 00 2 stop bits all other WLS settings D01 00 R W WLS 0 Word length select 00 Sbits 01 6bits 10 7bits 11 8 bits 410 Hardware Reference NS9215 SERIAL CONTROL MODULE UART UART Modem Control register UART Modem Control register Address 9001 1110 9001 9110 9002 1110 9002 9110 The UART Modem Control register controls the modem signals Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved AFE LLB Reserved RTS DTR Register bit assignment Bits Access
156. 0 WAITTURN 0 Write timing for flash memory is the same as for SRAM devices 218 Hardware Reference NS9215 MEMORY CONTROLLER Bus turnaround Bus turnaround The memory controller can be configured for each memory bank to use external bus turnaround cycles between read and write memory accesses The WAITTURN field can be programmed for 1 to 16 turnaround wait states to avoid bus contention on the external memory databus Bus turnaround cycles are generated between external bus transfers as follows Read to read different memory banks Read to write same memory bank Read to write different memory banks Bus turnaround Timing and parameters Read followed by write with no turnaround www digiembedded com This section shows bus turnaround timing diagrams and parameters This diagram shows a zero wait read followed by a zero wait write with default turnaround between the transfers of two cycles because of the timing of the AHB transfers Standard AHB wait states are added to the transfers five for the read and three for the write ee ET E 1 adi Y 2 s data D A D B sen 7 csin Iu l st wen 7 WAITRD 0 WAITOEN 0 WAITPAGE N A WAITWR 0 WAITWEN 0 WAITTURN 0 219 MEMORY CONTROLLER Bus turnaround Timing and parameters Write followed by This diagram shows
157. 0 Method Writeback Cache cleaning Register 7 operations see R7 Cache Operations register on page 94 Cache lockdown Format see R9 Cache Lockdown register on page 98 S bit Specifies whether the cache is a unified cache S 0 or separate ICache and DCache S 1 Will always report separate and DCache for this processor Dsize Specifies the size line length and associativity of the DCache Isize Species the size length and associativity of the ICache Dsize and Isize The Dsize and Isize fields in the cache type register have the same format as fields shown 11 10 9 65 321 0 The field contains these bits www digiembedded com 87 WORKING WITH THE CPU Field Description Size Determines the cache size in conjunction with the M bit m The M bit is 0 for DCache and ICache m The size field is bits 21 18 for the DCache and bits 9 6 for the ICache m The minimum size of each cache is 4 KB the maximum size is 128 KB m Cache size encoding with M 0 Size field Cache size 0b0011 4KB 0b0100 8 Note The processor always reports 4KB for DCache and 8KB for Assoc Determines the cache associativity in conjunction with the M bit m The M bit is 0 for both DCache and ICache m The assoc field is bits 17 15 for the DCache and bits 5 3 for the ICache m Cache associativity with encoding Assoc field Associativity 0010 4 Other values Reserved M bit Multiplier bi
158. 0 Applies only to UART channel C 0 UART mode 1 HDLC mode D27 18 N A Reserved N A N A D17 R W RXFLUSH 0 Resets the contents of the 64 byte RXFIFO Write a 1 then a 0 to reset the FIFO D16 R W TXFLUSH 0 Resets the contents of the 64 byte TX FIFO Write a 1 then a 0 to reset the FIFO D15 14 R RXBYTES 00 Indicates how many bytes are pending in the wrapper The wrapper writes to the RX FIFO only when 4 bytes are received or a buffer close event occurs such as end of frame D13 R W RXCLOSE 0 Allows software to close a receive buffer Hardware clears this bit when the buffer has been closed 0 Idle or buffer already closed 1 Software initiated buffer close D12 R W CRC 0 Controls whether the HDLC transmitter hardware sends CRC bytes before the closing flag 0 Send CRC bytes before the closing flag 1 Do not send CRC bytes before the closing flag handled by software D11 06 N A Reserved 0 N A D05 R W RL 0 Remote loopback Provides an internal remote loopback feature When the RL field is set to 1 the receive HDLC data signal is connected to the transmit HDLC data signal 423 SERIAL CONTROL MODULE HDLC Bits Access Mnemonic Reset Description D04 R W LL 0 Local loopback Provides an internal local loopback feature When the LL field is set to 1 the transmit HDLC data signal is connected to the receive HDLC data signal D03 00 N A Reserved N A N A Interrupt Enable register Address 9002 9004 Use the Interrupt
159. 00 AHB clock 8 0101 AHB clock 16 0110 AHB clock 32 0111 AHB clock 64 1000 AHB clock 128 1111 External event D05 04 R W Timer mode 1 0 0 Timer mode 1 00 Internal timer or external event 01 External low level gated timer 10 External high level gated timer 11 Concatenate the lower timer Note When either external gated option is selected the time clock select bits deter mine the frequency D03 R W Int Sel 0x0 Interrupt select 0 Interrupt disable Generate IRQ D02 R W Up Down 0x0 Up Down select 0 Upcounter Down counter D01 R W Bit timer 0x0 32 or 16 bit timer 0 16 bit timer 1 32 bit timer D00 R W Rel Enbl 0x0 Reload enable 0 Halt at terminal count The timer must be disabled then enabled to reload the timer when the terminal count is reached 1 Reload and resume count at terminal count Timer 6 9 Control registers 168 Addresses A090 01 8 01AC 0180 0184 Hardware Reference NS9215 SYSTEM CONTROL MODULE Timer 6 9 Control registers Register Reserved TM2 1 0 5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Timer Int Up Bit Rel isi db m dd Register bit assignment Bits Access Reset Description D31 18 N A Reserved N A N A D17 16 R W TM2 0x0 Timer mode 2 00 Mode as set by timer mode 1 01 PWM mode using High Low and Step registers 10 Clock mode toggle the timer output at the
160. 060 040C IPGR Non Back to Back Inter Packet Gap register A060 0410 CLRT Collision Window Retry register A060 0414 MAXF Maximum Frame register A060 0418 060 041C Reserved A060 0420 MCFG MII Management Configuration register A060 0424 MCMD MII Management Command register A060 0428 MADR MII Management Address register A060 042C MWTD MII Management Write Data register A060 0430 MRDD MII Management Read Data register A060 0434 MIND MII Management Indicators register A060 0440 SA1 Station Address Register 1 A060 0444 SA2 Station Address Register 2 A060 0448 SA3 Station Address register 3 A060 0500 SAFR Station Address Filter register A060 0504 HT1 Hash Table Register 1 A060 0508 HT2 Hash Table Register 2 A060 0680 STAT Statistics Register Base 45 registers A060 0A00 RXAPTR RX_A Buffer Descriptor Pointer register A060 0A04 RXBPTR RX B Buffer Descriptor Pointer register A060 0A08 RXCPTR RX C Buffer Descriptor Pointer register 277 ETHERNET COMMUNICATION MODULE Ethernet Control and Status registers Address Register Description A060 0A0C RXDPTR RX_D Buffer Descriptor Pointer register A060 0A10 EINTR Ethernet Interrupt Status register A060 0A14 EINTREN Ethernet Interrupt Enable register A060 0A18 TXPTR TX Buffer Descriptor Pointer register A060 0 1 TXRPTR TX Recover Buffer Descriptor Pointer register A060 0A20 TXERBD TX Error Bu
161. 1 Priority Level 31 lowest nterrupt Source 31 Invert LT v Interrupt Source ID Reg 311 Enable IRQ characteristics The IRQ interrupts are enabled by the respective enabling bits Once enabled the interrupt source programmed in the Interrupt Configuration register for each priority level connectsthe interrupt to one of 32 priority lines going into the priority encoder block The priority encoder block has a fixed order with line 0 as the highest priority The interrupt with the highest priority level has its encoded priority level displayed to select the appropriate vector for the ISADDR register see ISADDR register on page 176 The CPU once interrupted can read the ISADDR register to get the address of the Interrupt Service Routine A read to the ISADDR register updates the priority encoder block which masks the current and any lower priority interrupt requests Writing to this address indicates to the priority hardware that the current interrupt is serviced allowing lower priority interrupts to become active The write value to the ISADDR register must be the level of the interrupt being serviced Valid values are 0 31 The priority encoder block enables 32 prioritized interrupts to be serviced in nested fashion A software interrupt can be implemented by writing to a software interrupt register The software interrupt typically is assigned level 1 or level 2 priority Interrupt sources An
162. 1 the mask to enable or include that bit in the address filter m Bits are set 0 the mask if they are not included or are disabled in the address filter These bits become don t cares For an explanation of the synchronization scheme used for these registers see Clock synchronization on page 276 Address A060 0A80 D31 00 R W Default 0x0000 0000 MFMSKLO Address A060 0484 D31 00 R W Default 0x0000 0000 MFMSKLI Address A060 0A88 D31 00 R W Default 0x0000 0000 MFMSKI2 Address A060 0A8C D31 00 R W Default 0x0000 0000 MFMSKL3 329 ETHERNET COMMUNICATION MODULE 01 Multicast Address Mask registers Multicast Low Address Mask Register 4 Multicast Low Address Mask Register 5 Multicast Low Address Mask Register 6 Multicast Low Address Mask Register 7 Multicast High Address Mask Register 0 Multicast High Address Mask Register 1 Multicast High Address Mask Register 2 Multicast High Address Mask Register 3 Multicast High Address Mask Register 4 Address A060 0A90 D31 00 R W Default 0x0000 0000 Address A060 0A94 D31 00 R W Default 0x0000 0000 Address A060 0A98 D31 00 R W Default 0x0000 0000 Address A060 0A9C D31 00 R W Default 0x0000 0000 Address A060 0 0 D31 16 R Default 0x0000 0000 D15 00 R W Default 0x0000 0000 Address A060 4 D31 16 R Default 0x0000 0000 D15 00 R W Default 0x0000 0000 Address A060 0AA8
163. 1 04 N A Reserved N A do not modify D03 00 R W DAL Data in to active command or tapw 0 0 0 1 clock cycles where the delay is in cycles OxF 15 clock cycles reset value on reset_n Dynamic Memory Write Recovery Time register Address A070 0044 The Dynamic Memory Write Recovery Time register allows you to program the write recovery time It is recommended that this register be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode This value normally is found in SDRAM datasheets as Or trp Note The Dynamic Memory Write Recovery Time register is used for all four dynamic memory chip selects The worst case value for all chip selects must be programmed Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Reserved WR Register bit assignment Bits Access Mnemonic Description D31 04 N A Reserved N A do not modify D03 00 R W WR Write recovery time twn tppL gt 0 0 0 1 clock cycles where the delay is in cycles OxF 16 clock cycles reset value on reset_n 242 Hardware Reference NS9215 MEMORY CONTROLLER Dynamic Memory Active to Active Command Period register Dynamic Memory Active to Active Command Period register Register Re
164. 1 Valid Lowest External abort Section page 0b1000 Valid 0b1010 Valid Notes m Alignment faults can write either 050001 050011 into Fault Status register 3 0 m Invalid values can occur in the status bit encoding for domain faults This happens when the fault is raised before a valid domain field has been read from a page table description m X Aborts masked by a higher priority abort can be regenerated by fixing the cause of the higher priority abort and repeating the access m Alignment faults are not possible for instruction fetches m The Instruction Fault Status register can be updated for instruction prefetch operations MCR p15 0 Rd c7 c13 1 For load and store instructions that can involve the transfer of more than one word LDM STM STRD and STC LDC the value written into the Fault Address register depends on the type of access and for external aborts on whether the access crosses a 1 KB boundary Domain Fault Address register Alignment MVA of first aborted address in transfer External abort on translation MVA of first aborted address in transfer Translation MVA of first aborted address in transfer 120 Hardware Reference NS9215 Compatibility issues WORKING WITH THE CPU Domain access control Domain Fault Address register Domain MVA of first aborted address in transfer Permission MVA of first aborted address in transfer External about for noncached reads of last address before 1K
165. 10 TLB Lockdown 28 26 and0 Enables specific page table entries to be locked into the register Locking entries in the TLB guarantees that accesses to the locked page or section can proceed without incurring the time penalty of a TLB miss This enables the execution latency for time critical pieces of code such as interrupt handlers to be minimized CP15 MMU registers except R8 TLB Operations contain state that can be read using MRC instructions and can be written using MCR instructions Registers R5 Fault Status and R6 Fault Address are also written by the MMU during an abort Writing to R8 TLB Operations causes the MMU to perform a TLB operation to manipulate TLB entries This register is write only The virtual address VA generated by the CPU core is converted to a modified virtual address MVA by the FCSE fast context switch extension using the value held in CP15 R13 Process ID register The MMU translates MVAs into physical addresses to access external memory and also performs access permission checking 107 WORKING WITH THE CPU BEES MemoryManagement Unit MMU Translation table base TTB register format The MMU table walking hardware adds entries to the TLB The translation information that comprises both the address translation data and the access permission data resides in a translation table located in physical memory The MMU provides the logic for automatically traversing this translati
166. 14 13 I O CONTROL MODULE GPIO Configuration registers 1 GPIO 0 Bit s Access Mnemonic Reset Description D31 24 R W GPIO A3 0x18 GPIO A 3 configuration D23 16 R W GPIO A2 0x18 GPIO A 2 configuration D15 08 R W GPIO 1 0x18 GPIO 1 configuration D07 00 R W GPIO A0 Ox18 0 configuration 69 I O CONTROL MODULE GPIO Control registers GPIO Control Registers 0 through 38 contain the control information for each of the 108 GPIO pins When a GPIO pin is configured as a GPIO output the corresponding bit in GPIO Control Registers 0 through 38 is driven out the GPIO pin In all configurations the CPU has read write access to these registers GPIO Control Address A090 206C Register 0 Bit s Access Mnemonic Reset Description R W GPIOO 0 GPIO 0 control bit 01 GPIOI 0 GPIO 1 control bit D02 R W GPIO2 0 GPIO 2 control bit D03 R W GPIO3 0 GPIO 3 control bit D04 R W 4 0 GPIO 4 control bit D05 R W GPIO5 0 GPIO 5 control bit D06 R W GPIO6 0 GPIO 6 control bit D07 R W GPIO7 0 GPIO 7 control bit D08 R W GPIO8 0 GPIO 8 control bit D09 R W GPIO9 0 GPIO 9 control bit D10 R W GPIO10 0 GPIO 10 control bit Dil R W GPIO11 0 GPIO 11 control bit D12 R W GPIO12 0 GPIO 12 control bit D13 R W GPIO13 0 GPIO 13 control bit 14 R W GPIO14 0 GPIO 14 control bit D15 R W GPIO15 0 GPIO 15 cont
167. 15 WORKING WITH THE CPU External aborts interpreted in the same way as for a section see Interpreting access permission bits on page 121 The only difference is that the fault generated is a page permission fault Tiny page If the level one descriptor defines page mapped access and the level two descriptor is for a tiny page the AP bits of the level one descriptor define whether the access is allowed in the same way as for a section The fault generated is a page permission fault External aborts In addition to MMU generated aborts external aborts cam be generated for certain types of accessthat involve transfers over the AHB bus These aborts can be used to flag errors on external memory accesses Not all accesses can be aborted in this way however These accesses can be aborted externally m Page walks m reads Nonbuffered writes w read lock write SWP sequence For a read lock write SWP sequence the write is always attempted if the read externally aborts A swap to an NCB region is forced to have precisely the same behavior as a swap to an NCNB region This means that the write part of a swap to an NCB region can be aborted externally Enabling and disabling the MMU Enabling the MMU www digiembedded com Before enabling the MMU using the R1 Control register you must perform these steps 1 Program the R2 Translation Table Base register and the R3 Domain Ac
168. 172 Hardware Reference NS9215 SYSTEM CONTROL MODULE Timer 0 9 Reload Count and Compare register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rel Rel Step Dir Register bit assignment Access Mnemonic Reset Description D31 16 N A Reserved N A N A D15 R W Rel Dir 0x0 Reload step direction 0 Subtract the reload step value from the original reload register value to increase the overall period 1 Add the reload step value to the original reload register value to decrease the overall period D14 00 R W Rel Step 0x0 Reload step This value is either added or subtracted from the original low register value once each cycle Timer 0 9 Reload Count and Compare register Addresses A090 0028 002 0030 0034 0038 003 0040 0044 0048 004C The Timer 0 to 9 Reload Count and Compare register holds the up down reload and compare values for timers 0 to 9 Register 31 30 29 28 27 26 25 3 22 2 20 19 18 17 16 Cnt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 0 www digiembedded com 173 SYSTEM CONTROL MODULE Timer 0 9 Read Capture register Register bit assignment Bits Access Mnemonic Reset Description D31 16 R W Comp Rel Cnt 0x0 Timer Compare register or Timer Reload Bits 31 16 Count register An external toggle or pulse is generated each time the timer value matches this value An
169. 19 18 17 16 15 14 13 12 11 10 9 8 7 6 32 1 SBZ S B s s sez z o 5 5 Bit functionality Bits Name 31 19 N A Function Reserved m When read returns an UNPREDICTABLE value m When written SHOULD BE ZERO or a value read from bits 31 19 on the same processor m Use aread modify write sequence when modifying this register to provide the greatest future compatibility 18 N A Reserved SBO Read 1 write 1 17 N A Reserved SBZ read 0 write 0 16 N A Reserved SBO Read 1 write 1 15 14 Determines whether the T is set when load instructions change the PC 0 Loads to PC set the T bit Loads to PC do not set the T bit 14 RR bit Replacement strategy for ICache and DCache 0 Random replacement Round robin replacement 13 V bit 12 I bit Location of exception vectors 0 Normal exception vectors selected address range 0x0000 0000 to 0x0000 001C 1 High exception vectors selected address range 0xFFFF 0000 to OxFFFF 001C Set to the value of VINITHI on reset ICache enable disable 0 ICache disabled Cache enabled 11 10 N A SHOULD BE ZERO 9 R bit ROM protection Modifies the ROM protection system 8 S bit System protection Modifies the MMU protection system See MemoryManagement Unit MMU begi
170. 2 period 873 000 Lowtime 1 382 293 usec High time 218 453 usec Lowtime 2 272 254 usec Quadrature decoder function www digiembedded com The processor provides a quadrature decoder function to allow the CPU to determine the external device rate of rotation and the direction of rotation Example applications are robotic axles for feedback control mechanical knobs to determine user input and in computer mice to determine direction of movement One timer counter will include a quadrature decoder function which takes some computational load off the CPU When a CPU reads the output signals of a quadrature encoder every state must be decoded and a counter needs to be updated based on the interpretation of the states For example for an encoder of 256 pulses per revolution turning at a modest 6000 rpm the CPU needs to find and decoded 102 400 state changes per second and update the counter accordingly With an x8 sampling rate the CPU needs to sample the input about 8 x 102 400 timer per second This consumes a significant portion of the CPU bandwidth 145 SYSTEM CONTROL MODULE How the quadrature decoder counter works A quadrature decoder counter module performs these tasks at real time speed and interrupts the CPU at the predetermined conditions How the quadrature decoder counter works Provides input A quadrature encoder provides a pair of signals in phase and quad phase with signals opposite polari
171. 2 Bits C and B indicate whether the area of memory mapped by this page is treated as write back cachable write through cachable noncached buffered or noncached nonbuffered 3 2 3 2 SHOULD BE ZERO 1 0 1 0 1 0 These bits indicate the page size and validity and are interpreted as shown in First level descriptor bit assignments Priority encoding of fault status on page 111 VELOT Description 00 Invalid Generates a section translation fault 01 Coarse page table Indicates that this is a coarse page table descriptor 10 Section Indicates that this is a section descriptor 11 Fine page table Indicates that this is a fine page table descriptor A section descriptor provides the base address of a 1 MB block of memory 31 12 11 109 8 5 4 3 2 1 0 Section base address S SBZ AP Domain 1 1 0 2 11 WORKING WITH THE CPU MemoryManagement Unit MMU Section descriptor bit description Coarse page table descriptor Coarse page table descriptor format Coarse page table descriptor bit description Fine page table descriptor Bits Description 31 20 Forms the corresponding bits of the physical address for section 19 12 Always written as 0 11 10 Specify the access permissions for this section 09 Always written as 0 8 5 Specifies one of the 16 possible domains held in the Domain and Access Control register that con
172. 2 WAITOEN 0 WAITPAGE N A WAITWR N A WAITWEN N A WAITTURN N A Asynchronous page mode read The memory controller supports asynchronous page mode read of up to four memory transfers by updating address bits addr 1 and addr 0 This feature increases the bandwidth by using a reduced access time for the read accesses that are in page mode The first read access takes static wait read and WAITRD cycles Subsequent read accesses that are in page mode take static wait page and WAITPAGE cycles The chip select and output enable lines are held during the burst and only the lower two address bits change between subsequent accesses At the end of the burst the chip select and output enable lines are deasserted together Asynchronous page mode read Timing and parameters External memory page mode read transfer This section shows asynchronous page mode read timing diagrams and parameters This diagram shows an external memory page mode read transfer with two initial wait states and one sequential wait state The first read requires five AHB arbitration cycles plus three wait states the following up to 3 sequential transfers have only one AHB wait state This gives increased performance over the equivalent nonpage mode ROM timing 214 Hardware Reference NS9215 External memory 32 bit burst read from 8 bit memory www digiembedded com MEMORY CONTROLLER Asynchronous page mode read Timing and parameters PL addr Y
173. 2 2 2 210 Static memory read Timing and 211 External memory read transfer with zero wait 211 External memory read transfer with two wait 211 External memory read transfer with two output enable delay states 212 External memory read transfers with zero wait 5 212 Burst of zero wait states with fixed 213 Burst of two wait states with fixed length 213 Asynchronous page mode read 214 Asynchronous page mode read Timing and 214 External memory page mode read transfer 214 External memory 32 bit burst read from 8 bit 215 Static memory write 1 memes 216 Write enable programming delay 216 SRAM 216 Static memory Write Timing and 216 External memory write transfer with zero wait 5 216 External memory write transfer with two wait
174. 25 GPIO24 16 0 Bit s Access Mnemonic Reset Description D31 24 R W GPIO27 0x00 GPIO 27 configuration D23 16 R W GPIO26 0x00 GPIO 26 configuration D15 08 R W GPIO25 0x00 GPIO 25 configuration D07 00 R W GPIO24 0x00 GPIO 24 configuration GPIO Address A090 201C Configuration Register 7 31 30 29 28 27 26 24 23 21 20 19 18 17 16 GPICG9 8 15 14 13 12 1 10 8 5 4 3 2 1 0 7 6 5 Access Reset Description D31 24 R W GPIO31 0x00 GPIO 31 configuration D23 16 R W GPIO30 0x00 GPIO 30 configuration D15 08 R W GPIO29 0x00 GPIO 29 configuration D07 00 R W GPIO28 0x00 GPIO 28 configuration www digiembedded com 59 I O CONTROL MODULE 222777717 71 GPIO Configuration registers GPIO Address A090 2020 Configuration Register 8 Bit s Access Mnemonic Reset Description D31 24 R W GPIO35 0x18 GPIO 35 configuration D23 16 R W GPIO34 0x18 GPIO 34 configuration D15 08 R W GPIO33 0x18 GPIO 33 configuration D07 00 R W GPIO32 0x18 GPIO 32 configuration GPIO Address A090_ 2024 Configuration Register 9 31 30 2 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO89 GPIO88 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 Bit s Access Mnemonic Reset D31 24 R W GPIO39 0x18 D23 16 R W GPIO38 0x18 D15 08 R W GPIO37 0x18 D07 00 R W GPIO36 0x18 Description GPIO 39 configuration GPIO 38 configuration GPIO 37 configur
175. 27 HDLC Data Register 2 i 427 HDLC Data register 3 2 428 HDEC Corntrol Reglster T expe ep epi arena era REA ARR KR PERPE 429 HDLC Control R glster 2 etr uiuit eerte e un cute eot eed es 429 HDLC ClOCK Divider LOW 2 rece rette e Y eoe Ye iat xt 430 HDLC Clock Divider High iet eir xr cua eR nri Vot abito Reveal 431 Chapter 12 Serial Control Module 5 433 FeatUrES tama 433 21 SPI modu le Str ct fe bd ner Y 434 SP 434 Simple parallel serial data 434 Full duplex operation 2 iere et eer REIR SERRE RR 434 SPI clocking 7 2 400 1 een 435 TIMING ee 435 Clocking mode rtt tete tee 435 SPI clock generatlori ed le a 436 Clock generation samples 436 In SPI master 436 In slave mode een etr EXE ERE pA 436 System boot over SPl
176. 27 26 2b 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Stand Standby Reserved status Rady int Int stat mode Register bit assignment Bits Access Mnemonic Reset Description D31 05 N A Reserved N A N A D04 R Standby status 0x0 RTC standby mode status 0 RTC module is in standby mode and cannot be accessed by the CPU 1 RTC module is not in standby mode and can be accessed by the CPU 200 Hardware Reference NS9215 SYSTEM CONTROL MODULE RTC Module Control register Bits Access Mnemonic Reset Description D03 R Rdy int 0x0 RTC clock ready interrupt status 0 RTC clock ready interrupt not asserted 1 RTC clock ready interrupt asserted Note The RTC clock ready and RTC module interrupts are ORed together to the inter rupt controller Read this bit to determine the actual source D02 R Int stat 0x0 RTC module interrupt status 0 RTC module interrupt not asserted 1 module interrupt asserted Note The RTC clock ready and RTC module interrupts are ORed together to the inter rupt controller Read this bit to determine the actual source D01 R W Standby mode 0x0 RTC standby mode Allows the RTC module to be placed in low power mode 0 The RTC module is placed in standby mode and cannot be accessed by the CPU The RTC clock must be enabled when in standby mode bit 10 Normal operation The CPU must wait for the interrupt and read the status to determine that th
177. 3 TIMING timing All AC characteristics are measured with 10pF unless otherwise noted The table below describes the values shown in the 12 timing diagram Standard Mode Fast Mode Parm Description Min Max Min Max lic sda to iic scl START hold time 4 0 0 6 C2 lic scl low period 4 7 1 3 C3 lic scl high period 4 7 1 3 scltoiic sda DATA hold time 0 0 C5 iic_sda to iic_scl DATA setup tim 250 100 u C6 lic scltoiic sda STA 4 7 0 6 u C7 lic scl to iic STOP setup time 4 0 0 6 8 scl 504 Hardware Reference NS9215 SPI Timing www digiembedded com Memory Timing All AC characteristics are measured with 10pF unless otherwise noted The next table describes the values shown in the LCD timing diagrams TIMING Parm Description Min Max Unit 5 es SPI master parameters SPO SPI enable low setup to first SPI CLK out 10 ns 0 3 1 3 rising SP1 SPI enable low setup to first SPI CLK 3 10 ns 1 2 1 3 falling SP3 SPI data in setup to SPI CLK out rising 30 ns 0 3 SP4 SPI data in hold from SPI CLK out rising 0 ns 0 3 SP5 SPI data in setup to SPI CLK out falling 30 ns 1 2 SP6 SPI data in hold from SPI CLK out falling 0 ns 1 2 SP7 SPI CLK out falling to SPI data out valid 10 ns 0 3 6 SP8 SPI CLK out rising to SPI data out valid 10 ns 1 2 6 5 9 SPI enable low
178. 3 0 GPIO A 3 control bit D31 12 N A Reserved N A N A www digiembedded com CONTROL MODULE GPIO Status registers GPIO Status Registers 40 through 3 contain the status information for each of the 108 GPIO pins In all configurations the value on the GPIO input pin is brought to the status register and the CPU has read only access to the register GPIO Status Address A090 2080 Register 1 Bit s Access Mnemonic Reset Description DOO R GPIO32 Undefined GPIO 32 status bit R GPIO33 Undefined GPIO 33 status bit D02 R GPIO34 Undefined GPIO 34 status bit D03 R GPIO35 Undefined GPIO 35 status bit D04 R GPIO36 Undefined GPIO 36 status bit D05 R GPIO37 Undefined GPIO 37 status bit D06 R GPIO38 Undefined GPIO 38 status bit D07 R GPIO39 Undefined GPIO 39 status bit D08 R GPIO40 Undefined GPIO 40 status bit D09 R GPIO41 Undefined GPIO 41 status bit D10 R GPIO42 Undefined GPIO 42 status bit D11 R GPIO43 Undefined GPIO 43 status bit D12 R GPIO44 Undefined GPIO 44 status bit R GPIO45 Undefined GPIO 45 status bit 14 R GPIO46 Undefined GPIO 46 status bit D15 R GPIO47 Undefined GPIO 47 status bit 016 R 48 Undefined GPIO 48 status bit D17 R GPIO49 Undefined GPIO 49 status bit D18 R 50 Undefined GPIO 50 status bit 019 R Undefined GPIO 51 status bit D20 R GPIO52 Undefined GPIO 52 status bit D21 R 5
179. 3 2 1 0 Reserved RD Register bit assignment Bits Access Mnemonic Description D31 02 N A Reserved N A do not modify D01 00 R W RD Read data strategy 00 Reserved 01 Command delayed strategy using CLKDELAY command delayed clock out not delayed 10 Command delayed strategy plus one clock cycle using CLKDELAY command delayed clock out not delayed 11 Command delayed strategy plus two clock cycles using CLKDELAY command delayed clock out not delayed Dynamic Memory Precharge Command Period register Address A070 0030 The Dynamic Memory Precharge Command Period register allows you to program the precharge command period tgp Modify this register only during system initialization This value normally is found in SDRAM datasheets as tgp Note The Dynamic Memory Precharge Command Period register is used for all four dynamic memory chip selects The worst case value for all chip selects must be programmed Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RP 238 Hardware Reference NS9215 MEMORY CONTROLLER Dynamic Memory Active to Precharge Command Period register Register bit assignment Bits Access Mnemonic Description D31 04 N A Reserved N A do not modify D03 00 R W RP Precharge command period tgp 0 0 0 n 1 clock cycles where the delay is in cycles OxF 16 clock cycles reset value on reset_n Dynamic M
180. 3 Undefined GPIO 3 status bit D22 R GPIO54 Undefined GPIO 54 status bit D23 R 55 Undefined GPIO 55 status bit D24 R 56 Undefined GPIO 56 status bit D25 R 57 Undefined GPIO 57 status bit 74 Hardware Reference NS9215 CONTROL MODULE GPIO Status registers Bit s Access Mnemonic Reset Description D26 R GPIO58 Undefined GPIO 58 status bit D27 R 59 Undefined GPIO 59 status bit D28 R GPIO60 Undefined GPIO 60 status bit D29 R GPIO61 Undefined GPIO 61 status bit D30 R GPIO62 Undefined GPIO 62 status bit D31 R GPIO63 Undefined GPIO 63 status bit GPIO Status Address A090 2084 Register 2 Bit s Access Mnemonic Reset Description GPIO64 Undefined GPIO 64 status bit D01 R GPIO65 Undefined GPIO 65 status bit D02 R GPIO66 Undefined GPIO 66 status bit D03 R GPIO67 Undefined GPIO 67 status bit D04 R GPIO68 Undefined GPIO 68 status bit D05 R GPIO69 Undefined GPIO 69 status bit D06 R GPIO70 Undefined GPIO 70 status bit D07 R GPIO71 Undefined GPIO 71 status bit D08 R GPIO72 Undefined GPIO 72 status bit D09 R GPIO73 Undefined GPIO 73 status bit D10 R GPIO74 Undefined GPIO 74 status bit D11 R 75 Undefined GPIO 75 status bit D12 R GPIO76 Undefined GPIO 76 status bit D13 R 77 Undefined GPIO 77 status bit 14 R GPIO78 Undefined GPIO 78 status bit D15 R GPIO79 Undefined GPIO 79 stat
181. 4 Second level descriptor 114 Second level descriptor bit 115 Second level descriptor least significant 115 Translation sequence for large page 116 Translating sequence for small page references 117 Translation sequence for tiny page references 118 SUBPAGES 118 Hardware Reference NS9215 MMU faults and CPU 119 Alignment fault 0 He 119 Fault Address and Fault Status registers 119 Priority encoding 2 2 2 eem 120 Fault Address register 42 70202 2 2 4 120 FAR values for multi word transfers 120 Compatibility 1550 ertet ex PR e 121 DOMAIN access 121 Specifying access 0 5 121 Interpreting access permission 45 2 2 2 121 Fault che
182. 41 Peripheral DMA read 5 342 Determining the width of 0 342 Equation variables cci aa ceins 342 Peripheral DMA single read 55 343 Peripheral DMA burst read 55 343 Peripheral DMA write 343 Determining the width of 2 2 20 0 344 Peripheral single write 5 344 Peripheral DMA burst write 5 344 Peripheral REQ and DONE signaling sss 344 LT 344 DONE SIGN all 345 Special circumstances ciis et e 345 Static chip select 2 2 40 0 7201 345 Static ram chip select 2 00 2 345 Control and Status registers ste i ede ead a P rd bd 346 Register address map oem mr eme 346 DMA Buffer Descriptor 346 DMA Control
183. 47 2 MASTER SLAVE INTERFACE serial clock Serial clock modulation can be controlled by both the transmitter and receiver based in their hosts service speed Multi master bus The 12 is a true multi master bus with collision detection and arbitration to prevent data corruption when two or more masters initiate transfer simultaneously If a master loses arbitration during the addressing stage it is possible that the winning master is trying to address the transfer The losing master must therefore immediately switch over to its slave mode The on chip filtering rejects spikes on the bus data line to preserve data integrity The number of ICs that can be connected to the same bus is limited only by a maximum bus capacity of 400 pf 12 external addresses 2 external bus addresses are allocated as two groups of eight addresses 0000XXX and 1111XXX KENG R W Description addres bit 0000 000 0 General call address 0000 000 1 START byte not supported in the processor 0000 001 X CBUS address not supported in the processor 0000 010 X Reserved for different bus format 0000 011 X Reserved 0000 1xx X hs mode master code not supported in the processor 1111 1xx X Reserved 1111 Oxx X 10 bit slave address The general call address is for addressing all devices connected to the 12 bus A device can ignore this address by not issuing an acknowledgement The meaning of the general call add
184. 514 Chapter 18 Change log 517 REVISION MK 517 REVISION 517 25 26 Hardware Reference NS9215 Pinout 265 The Legend ER T NS9215 offers a connection to a 10 100 Ethernet network as well asa glueless connection to SDRAM PC100 DIMM flash EEPROM and SRAM memories and an external bus expansion module It includes four multi function serial ports one I2C channel 12 bit Analog to Digital converter battery backed real time clock and an AES data encryption decryption module The NS215 provides up to 108 general purpose 1 GPIO pins and configurable power management with sleep mode Heading Description Pin Pin number assigned for a specific I O signal Signal Pin name for each I O signal Some signals have multiple function modes and are identified accordingly The mode is configured through firmware using one or more configuration registers nis the signal name indicates that this signal is active is active low U D U or D indicates whether the pin has an internal pullup resistor or a pulldown resistor U Pullup input current source D Pulldown input current sink If no value is listed that pin has neither an internal pullup nor pulldown resistor IO The type of signal input I output O input output I O or power P OD mA The output drive of an output
185. 56 Mb 8Mx32 4 banks row length 13 column length 8 1 0 100 00 512 Mb 64 8 4 banks row length 13 column length 11 1 0 100 01 512 Mb 32 16 4 banks row length 13 column length 10 32 bit extended bus low power SDRAM address mapping bank row column 1 1 000 00 16 Mb 2 8 2 banks row length 11 column length 9 1 1 000 01 16 Mb 1Mx16 2 banks row length 11 column length 8 1 1 001 00 64 Mb 8 8 4 banks row length 12 column length 9 1 1 001 01 64 MB 4 16 4 banks row length 12 column length 8 1 1 001 10 64 Mb 2Mx32 4 banks row length 11 column length 8 1 1 010 00 128 Mb 16 8 4 banks row length 12 column length 10 1 1 010 01 128 Mb 8 16 4 banks row length 12 column length 9 1 1 010 10 128 Mb 4Mx32 4 banks row length 12 column length 8 1 1 011 00 256 Mb 32 8 4 banks row length 13 column length 10 1 1 011 01 256 16 16 4 banks row length 13 column length 9 1 1 011 10 256 Mb 8Mx32 4 banks row length 13 column length 8 1 1 100 00 512 Mb 64 8 4 banks row length 13 column length 11 1 1 100 01 512 Mb 32 16 4 banks row length 13 column length 10 A chip select can be connected to a single memory device in this situation the chip select data bus width is the same asthe device width As an alternative the chip select can be connected to a number of external devices In this situation the chip select
186. 6 R C STOVFL 0 Assigned to TX interrupt Statistics counter overflow Individual counters can be masked using the Carry Register 1 and 2 Mask registers The source of this interrupt is cleared by clearing the counter that overflowed and by clearing the associated carry bit in either Carry Register 1 or Carry Register 2 by writing a 1 to the bit D05 R Not used 0 Always write as 0 D04 R C TXBUFC 0 Assigned to TX interrupt I bit set in the Transmit Buffer Descriptor and buffer closed D03 R C TXBUFNR 0 Assigned to TX interrupt F bit not set in the Transmit Buffer Descriptor when read from the TX Buffer descriptor RAM D02 R C TXDONE 0 Assigned to TX interrupt Hardware Reference NS9215 Frame transmission complete Ethernet Interrupt Enable register ETHERNET COMMUNICATION MODULE Ethernet Interrupt Enable register Bits Access Mnemonic Reset Description D01 R C TXERR 0 Last frame not transmitted successfully Assigned to TX interrupt See Ethernet Interrupt Status register on page 317 for information about restarting the transmitter when this bit is set D00 R C TXIDLE 0 TX WR logic has no frame to transmit Assigned to TX interrupt See Ethernet Interrupt Status register on page 317 for information about restarting the transmitter when this bit is set Address A060 0A14 The Ethernet Interrupt Enable register contains individual enable bits for each of the bits in the Ethernet Interrupt Status register When t
187. 7 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reserved EN7 EN6 MFILT MFILT MFILT MFILT MFILT MFILT MFILT MFILT EN5 EN4 EN2 ENO 331 ETHERNET COMMUNICATION MODULE Register bit assignment Bits D31 08 Access R Mnemonic Reserved Reset N A Description Read as 0 D07 R W MFILTEN7 0x0000 0000 Enable entry 7 of multicast address filter 0 Disable entry 1 Enable entry D06 R W MFILTEN6 0x0000 0000 Enable entry 6 of multicast address filter 0 Disable entry Enable entry D05 R W MFILTENS 0x0000 0000 Enable entry 5 of multicast address filter 0 Disable entry Enable entry D04 R W MFILTENA 0x0000 0000 Enable entry 4 of multicast address filter 0 Disable entry 1 Enable entry D03 D02 R W R W MFILTEN3 MFILTEN2 0x0000 0000 0x0000 0000 Enable entry 3 of multicast address filter 0 Disable entry 1 Enable entry Enable entry 2 of multicast address filter 0 Disable entry Enable entry 01 D00 R W R W MFILTENI MFILTENO 0x0000 0000 0x0000 0000 Enable entry 1 of multicast address filter 0 Disable entry Enable entry Enable entry 0 of multicast address filter 0 Disable entry 1 Enable entry TX Buffer Descriptor RAM Offset 0 332 Address A060 1000 The TX buffer descriptor RAM holds 64 transmit buffer descriptors on chip Each buffer des
188. 75 Multicast address filtering example 2 276 276 Clock synchronization s erre Etre Dead dus 276 Hardware Reference NS9215 www digiembedded com Writing to other 276 Ethernet Control and Status registers 277 Register address 22 22 emn 271 Ethernet General Control Register 279 Ethernet General Control Register 32 7 0 0 2 282 Ethernet General Status 2 4 283 Ethernet Transmit Status 284 Ethernet Receive Status 286 MAC Configuration Register 1 27 0 0 02020002 2 288 MAC Configuration Register 2 2 2 0 40 2 2000 4 289 PAD operation table for transmit 291 Back to Back Inter Packet Gap 5 291 Non Back to Back Inter Packet Gap register 292 Collision Window Retry
189. 89 0x18 GPIO 89 configuration D07 00 R W GPIO88 0x18 GPIO 88 configuration Address A090 205C 31 30 29 28 27 26 24 23 21 20 19 18 17 16 95 GPIO 15 14 13 12 11 10 8 7 5 4 3 2 1 0 92 Bit s Access Mnemonic Reset Description D31 24 R W GPIO95 0x18 GPIO 95 configuration D23 16 R W GPIO94 0x18 GPIO 94 configuration D15 08 R W GPIO93 0x18 GPIO 93 configuration D07 00 R W GPIO92 0x18 GPIO 92 configuration 67 I O CONTROL MODULE GPIO Configuration registers GPIO Address A090 2060 Configuration Register 24 31 30 29 28 27 26 25 4 B 21 20 19 18 17 16 GPIO99 GPIO98 15 14 13 12 11 10 9 8 7 5 4 3 2 1 0 GPIO97 GPIO96 Bit s Access Mnemonic Reset Description D31 24 R W GPIO99 0x18 GPIO 99 configuration D23 16 R W 98 0 18 GPIO 98 configuration D15 08 R W GPIO97 0x18 GPIO 97 configuration D07 00 R W GPIO96 0x18 GPIO 96 configuration GPIO Address A090_2064 Configuration Register 25 31 30 29 28 27 26 25 24 23 21 20 19 18 17 16 GPIO103 GPIO102 15 14 13 12 11 10 9 8 7 5 4 3 2 1 0 GPIO101 GPIO100 Bit s Access Mnemonic Reset Description D31 24 R W GPIO103 0x18 GPIO 103 configuration D23 16 R W GPIO102 0x18 GPIO 102 configuration D15 08 R W GPIO101 0x18 GPIO 101 configuration D07 00 R W GPIO100 0x18 GPIO 100 configuration 68 Hardware Reference NS9215 GPIO Configuration Register 26 www digiembedded com Address A090_2068 15
190. 9 8 7 6 5 4 3 2 1 0 Chip select 1 mask 51 Reserved CSD1 Register bit assignment Bits Access Mnemonic Reset Description D31 12 R W CS1B 0x50000 Chip select 1 base Base address for chip select 1 D11 00 N A Reserved N A N A D31 12 R W CSIM OxF0000 Chip select 1 mask Mask or size for the chip select 1 D11 01 N A Reserved N A N A D00 R W CSDI 0 1 Chip select 1 disable 0 Disable chip select Enable chip select System Memory Chip Select 2 Static Memory Base and Mask registers Addresses A090 0200 0204 These control registers set the base and mask for system memory chip select 2 with a minimum size of 4K The powerup default settings produce a memory range of 0 6000 0000 Ox6FFF FFFF 196 Hardware Reference NS9215 Registers Register bit assignment SYSTEM CONTROL MODULE System Memory Chip Select 3 Static Memory Base and Mask registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select 2 base CS2B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip select 2 base CS2B Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select 2 mask CS2M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Chip select 2 mask 52 Reserved CSD2 Bits Access Mnemonic Reset Description D31 12 R W CS2B 0x60000 Chip select 2 base Base address for chip select 2 D11 00 N A Reserved N A N A D31 12 R W CS2M 0 0000 Chip select 2 mask Mask or size for chip select 2 D11 01 N A Reserved N A
191. A D18 D17 16 R W Rel mode TM2 0 0 0 0 Reload mode Initializes the timer and the reload value at terminal count Reload mode is useful in quadrature decoder applications as it allows the reload value to be half of he terminal count 0 Use the value in the Reload register 1 Use half the value in the Reload register Timer mode 2 00 Mode as set by timer mode 1 01 Reserved 10 Reserved 11 Quadrature decoder counter mode D15 TE 0x0 Timer enable 0 Timer disabled 1 Timer enabled D14 12 R W Cap Comp 0x0 Capture and compare mode functions Applicable only when in 16 bit timer mode 000 Normal operation 001 Compare mode toggle output on match 010 Compare mode pulse output on match 011 Capture mode on input falling edge 100 Capture mode on input rising edge 219 rising edge 101 Capture mode on every 110 Capture mode on every 4 rising edge 111 Capture mode on every gth rising edge D11 R W Debug 0 0 Debug mode 0 Timer enabled in CPU debug mode Timer disabled in CPU debug mode D10 www digiembedded com R W Int Clr 0x0 Interrupt clear Clears the timer interrupt Software must write a 1 then a 0 to this location to clear the interrupt 167 SYSTEM CONTROL MODULE Bits Access Mnemonic 09 06 R W TCS Reset 0x0 Description Timer clock select 0000 AHB clock x 2 0001 AHB clock 0010 AHB clock 2 0011 AHB clock 4 01
192. A depending on the MMU page table entry that is the VA is translated to MVA and the MVA is remapped to a PA This table gives the page table C and B bit settings for the DCache R1 Control register C bit 2M bit 2 1 and the associated behavior WORKING WITH THE CPU Cache MVA Set Way formats 926 5 behavior DCache disabled Read from external memory Write as a nonbuffered store s to external memory DCache is not updated DCache disabled Read from external memory Write as a buffered store s to external memory DCache is not updated DCache enabled Read hit Read from DCache Read miss Linefill Write hit Write to the DCache and buffered store to external memory Write miss Buffered store to external memory Page Description tableC table bit bit 0 0 Noncachable nonbufferable 0 1 Noncachable bufferable 1 0 Write through 1 1 Write back DCache enabled Read hit Read from DCache Read miss Linefill Write hit Write to the DCache only Write miss Buffered store to external memory Cache and Set Way formats This section shows how the and set way formats ARM926E S caches map to a generic virtually indexed virtually addressed cache shown next The next figure shows a generic virtually indexed virtually addressed cache 130 Hardware Reference NS9215 Generic virtually indexed virtually addressed cache ww
193. A070 020C 022C 024C 026C The Static Memory Read Delay 0 3 registers allow you to program the delay from the chip select to the read access It is recommended that these registers be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode These registers are not used if the extended wait bit is set in the related Static Memory Configuration register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WTRD Register bit assignment Bits Access Mnemonic Description D31 05 N A Reserved N A do not modify D04 00 R W WTRD Nonpage mode read wait states or asynchronous page mode read first access wait state WAITRD 00000 11110 n 1 out cycle for read accesses For nonsequential reads the wait state time is WAITRD 1 x out 11111 32 out cycles for read accesses reset value on reset n Use this equation to compute this field WTRD T T 10 0 T 1 Ty Total board propagation delay including any buffers T Peripheral access time out clock period Any decimal portion must be rounded up values are in nanoseconds StaticMemory Page Mode Read Delay 0 3 registers Address A070 0210 0230 0250 0270 The Static Memory Page Mode Read Delay 0 3 registers allow you to program the
194. AMInit value the Dynamic Control register to 01 Issue SDRAM Mode command Program the SDRAM memory 10 bit mode register The mode register enables these parameters to be programmed Parameter Parameter description 02 00 Burst length m 4 for a 32 bit wide external bus m 8 fora 16 bit wide external bus 03 Burst type Sequential 06 04 CAS latency Dependent on the SDRAM device and operating frequency 08 07 Operating mode Standard operation 09 Write burst mode Programmed burst length read transaction from the SDRAM memory programs the mode register The transfer address contains the value to be programmed Address bits 31 28 determine the chip select of the specific SDRAM that is being programmed The 10 bit mode value must be shifted left per the specific device being programmed see the tables following this procedure to determine the left shift value All other address bits must be set to 0 Set the SDRAMInit value in the Dynamic Control register to 00 Issue SDRAM nor mal operation command Enable the buffers by writing 1 to the buffer enable bit in the Dynamic Config uration N register The SDRAM is now ready for normal operation Device size Configuration Load Mode register left shift 16M 2x1Mx 16 11 4 2 8 12 64 1 2 32 12 2 4 16 12 4 8Mx8 13 128 1 4 32 12 2x8Mx 16 13 4x16Mx8 14 226 Hardware Reference NS9215 Left shift value table 32 bit wide
195. Always write as 0 D13 12 N A Reserved N A N A D11 R W Not used 0 Always write as 0 D10 R W RPERFUN 0 Reset PERFUN Set this bit to 1 to put the MAC receive logic into reset D09 R W RPEMCST 0 Reset PEMCS TX Set this bit to 1 to put the MAC control sublayer transmit domain logic into reset D08 R W RPETFUN 0 Reset PETFUN Set this bit to 1 to put the MAC transmit logic into reset D07 05 N A Reserved N A N A Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE MAC Configuration Register 2 Bits Access Mnemonic Reset Description D04 R W LOOPBK 0 Internal loopback Set this bit to 1 to cause the MAC transmit interface to be internally looped back to the MAC receive interface Clearing this bit results in normal operation D03 01 R W Not used 0 Always write as 0 D00 R W RXEN 0 Receive enable Set this bit to 1 to allow the MAC receiver to receive frames MAC Configuration Register 2 Register Register bit assignment www digiembedded com Address A060 0404 MAC Configuration Register 2 provides additional bits that control functionality within the Ethernet MAC block 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rsvd EDE Not NOBO Reserved LONGP AUTOP VLANP PADEN CRCEN Not HUGE bid FULLD FER used used used Access Mnemonic Reset Definition D31 15 N A Reserved N A N A 14 R W EDEFER 0 Excess deferral 0 MAC ab
196. B Time register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Reserved XSR Register bit assignment Bits Access Mnemonic Description D31 05 N A Reserved N A do not modify D04 00 R W XSR Exit self refresh to active time command 0x0 0x1E n 1 clock cycles where the delay is cycles Ox1F 32 clock cycles reset value on reset n Dynamic Memory Active Bank A to Active Bank B Time register Address A070 0054 The Dynamic Memory Active Bank A to Active Bank B Time register allows you to program the active bank A to active bank B latency It is recommended that this register be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode This value normally is found in SDRAM datasheets as Note Register 31 The Dynamic Memory Active Bank A to Active Bank B Time register is used for all four dynamic memory chip selects The worst case value for all chip selects must be programmed 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved Reserved RRD www digiembedded com 245 MEMORY CONTROLLER Dynamic Memory Load Mode register to Active Command Time register Register bit assignment Bits Access Mnemonic Description D31 04 N A Reserved N A do not modify D03 00 R W RRD Ac
197. B boundary if any word of or nonbuffered writes the transfer before 1 KB boundary is externally aborted MVA of last address in transfer if the first externally aborted word is after the 1 KB boundary enable code to be ported easily to future architectures it is recommended that no reliance is made on external abort behavior m Instruction Fault Status register is intended for debugging purposes only Domain access control Specifying access permissions Interpreting access permission bits www digiembedded com MMU accesses are controlled primarily through the use of domains There are 16 domains and each has a two bit field to define access to it Client users and Manager users are supported The domains are defined in the R3 Domain Access Control register the register format R3 Domain Access Control register on page 91 shows how the 32 bits of the register are allocated to define the 16 two bit domains This table shows how the bits within each domain are defined to specify access permissions Description 00 No access Any access generates a domain fault 01 Client Accesses are checked against the access permission bits in the section or page descriptor 10 Reserved Reserved Currently behaves like no access mode 11 Manager Accesses are not checked against the access permission bits so a permission fault cannot be generated This table shows how to inter
198. Cache may contain stale entries To remove these stale entries part of all of the ICache must be invalidated Use this procedure to ensure consistency between data and instruction sides 1 Cleanthe DCache If the cache contains cache lines corresponding to write back regions of memory it might contain dirty entries These entries must be cleaned to make external memory consistent with the DCache If only a small part of the cache has to be cleaned it can be done by using a sequence of clean DCache single entry instructions If the entire cache has to be cleaned you can use the test and clean operation see R7 Cache Operations register beginning on page 94 2 Drain the write buffer Executing a drain write buffer causes the ARM926EJ S core to wait until outstanding buffered writes have completed on the AHB interface This includes writes that occur as a result of data being written back to main memory because of clean operations and data for store instructions 3 Synchronize data and instruction streams in level two AHB systems The level two AHB subsystem might require synchronization between data and instruction sides It is possible for the data and instruction AHB masters to be attached to different AHB subsystems Even if both masters are present on the same bus some form of separate ICache might exist for performance reasons this must be invalidated to ensure consistency The process of synchronizing instructions and data in leve
199. D03 R W EN TXBUFNR 0 Enable the TXBUFNR interrupt bit D02 R W EN TXDONE 0 Enable the TXDONE interrupt bit 01 R W EN TXERR 0 Enable the TXERR interrupt bit D00 R W EN TXIDLE 0 Enable the TXIDLE interrupt bit TX Buffer Descriptor Pointer register Address A060 0A18 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reserved TXPTR Register bit assignment Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 00 R W TXPTR 0x00 Contains a pointer to the initial transmit buffer descriptor in the TX buffer descriptor RAM Note This pointer is the 8 bit physical address of the TX buffer descriptor RAM and points to the first location of the four location buffer descriptor The byte offset of this buffer descriptor can be calculated by multiplying this value by 4 320 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Transmit Recover Buffer Descriptor Pointer register Transmit Recover Buffer Descriptor Pointer register Address A060 0A1C Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reserved TXRPTR Register bit assignment Bits Access Mnemonic Reset Description D3 1 08 N A Reserved N A N A D07 00 R W TXRPTR 0x00 Contains a pointer to a buffer descriptor in the TX buffer descriptor RAM Note This pointer is the 8 bit physical address of t
200. D12 R W MIRBC Mask register 1 RBCA counter carry bit mask D11 R W MIRXC Mask register RXCF counter carry bit mask D10 R W Mask register 1 RXPF counter carry bit mask D09 R W MIRXU Mask register 1 RXUO counter carry bit mask D08 R W MIRAL Mask register 1 RALN counter carry bit mask D07 R W Not used Always write as 1 D06 R W MIRCD Mask register 1 RCDE counter carry bit mask D05 R W MIRCS Mask register 1 RCSE counter carry bit mask D04 R W MIRUN Mask register 1 RUND counter carry bit mask D03 R W MIROV Mask register 1 ROVR counter carry bit mask D02 R W MIRFR Mask register 1 RFRG counter carry bit mask D01 R W MIRJB Mask register 1 RJBR counter carry bit mask D00 R W Not used Always write as 1 313 ETHERNET COMMUNICATION MODULE Carry Register 2 Address A060 073C Mask register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 M2 M2 Not M2 Reserved JTB TFC used TOV 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TUN tro 2 usea Txe two Not used Register bit assignment Bits Access Mnemonic Reset Description D31 20 N A Reserved N A N A D19 R W M2TJB 1 Mask register 2 TJBR counter carry bit mask D18 R W M2TFC 1 Mask register 2 TFCS counter carry bit mask D17 R W Not used 1 Always write as 1 D16 R W M2TOV 1 Mask register 2 TOVR counter carry bit mask D15 R W M2TUN 1 Mask register 2 TUND counter carry bi
201. D12 txd 2 gpio 46 U 2 TX data 2 C12 txd 1 gpio 45 U IO 2 TX data 1 B13 txd 0 gpio 44 U 2 TX data 0 B15 tx er gpio 43 U IO 2 TX code err B14 tx_en gpio 42 U IO 2 TX enable 14 col gpio 48 U IO 2 Collision C13 crs gpio 49 U IO 2 Carrier sense 14 clk gpio 34 U IO 2 RX clock E17 rxd 3 gpio 41 U 2 RX data 3 D16 rxd 2 gpio 40 U 2 2 7 rxd 1 gpio 39 U 2 RX data 1 D13 rxd 0 gpio 38 U 2 RX data 0 C17 er gpio 37 U IO 2 RX error D17 dv gpio 36 U UO 2 RX data valid General purpose 1 0 GPIO Some signals are multiplexed to two or more GPIOs to maximize the number of possible applications These duplicate signals are marked as dup in the Descriptions column in the table Selecting the primary GPIO pin and the duplicate GPIO pin for the same function is not recommended If both the primary GPIO pin and duplicate GPIO pin are programmed for the same function however the primary GPIO pin has precedence and will be used 2C module must be held in reset until the GPIO assigned to 12 has been configured www digiembedded com 31 265 Note GPIOs except 12 and 16 to 31 are reset to mode 3 input GPIO 12 is reset to mode 2 reset done GPIO 16 to 31 are reset to mode 0 external memory data 15 0 Description K15 gpio 0 U 2 DCD UART Ext Done Ch 0 0 GEN IO 0j I O gpi
202. ERBD to identify frames that were not transmitted successfully TX Stall Buffer Descriptor Pointer register Address A060 0424 Register 322 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE A Buffer Descriptor Pointer Offset register Register bit assignment Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 00 R TXSPTR 0x00 Ifthe TX runs out of frames to send it sets TXIDLE in the Ethernet Interrupt Status register and stores the pointer in the TX buffer descriptor RAM to the buffer descriptor that did not have its F bit set in the TX Stall Buffer Descriptor Pointer register Note This pointer is the 8 bit physical address of the TX buffer descriptor RAM and points to the first location of the four location buffer descriptor The byte offset of this buffer descriptor can be calculated by multiplying this value by 4 Software uses TXSPTR to identify the entry in the TX buffer descriptor RAM at which the TX stalled Note RX A Buffer Descriptor Pointer Offset register Address A060 0 28 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RXAOFF Register bit assignment Bits Access Mnemonic Reset Description D31 11 N A Reserved N A N A D10 00 R RXAOFF 0x000 Contains an 11 bit byte offset from the start of the pool A ring The offset is updated at the end of the RX pac
203. Ethernet underrun can only occur due to the following programming errors Insufficient bandwidth is assigned to the Ethernet transmitter 272 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Ethernet slave interface A packet consisting of multiple linked buffer descriptors does not have the F bit set in any of the non first buffer descriptors When an underrun occurs it is also possible for the Ethernet transmitter to send out a corrupted packet with a good Ethernet CRC if the MAC is configured to add the CRC to the frame that is CRCEN in MAC Configuration Register 32 is set to 1 Ethernet slave interface The AHB slave interface supports only single 32 bit transfers The slave interface also supports limiting CSR and RAM accesses to CPU privileged mode accesses Use the internal register access mode bit 0 in the Miscellaneous System Configuration register to set access accordingly see Miscellaneous System Configuration and Status register beginning on page 184 The slave also generates an AHB ERROR if the address is not aligned on a 32 bit boundary and the misaligned bus address response mode is set in the Miscellaneous System Configuration register In addition accesses to non existent addresses result in an AHB ERROR response Interrupts Separate RX and TX interrupts are provided back to the system Interrupt sources This table shows all interrupt sources and the interrupts to which they are assigned In
204. F when matched Forced character transmission UART provides a mechanism in which you can bypass data in the transmit FIFO with a specific character The specified character is transmitted after the current 388 Hardware Reference NS9215 SERIAL CONTROL MODULE UART ARM wakeup on character recognition character completes regardless of any flow control mechanism that might stall normal data transmission Use the Force Transmit Character Control register to program this operation Force character These steps outline a single force character transmission operation transmission 1 Read the Force Transmit Character Control register and verify that the ENABLE d poem field is 0 The Force Transmit Character Control register must not be written while the ENABLE field is 1 2 Writealtothe ENABLE field and the required character to the CHAR field This operation can be a single step Collecting Force character transmission completion status is available It is up to you asto feedback whether you want to collect feedback If you do want to collect feedback these are your options Poll the ENABLE field the Force Transmit Character Control register until it reads 0 Poll the FORCE field in the Interrupt Status register until it reads 1 w Enable the FORCE interrupt by writing a 1 to the FORCE field in the Interrupt Enable register and servicing the interrupt when it occurs ARM wakeup on character recognition The UART mo
205. FACK bit in the Status register Note Static memory can be accessed as normal when the SDRAM memory is in self refresh mode The memory controller supports J EDEC low power SDRAM deep sleep mode Deep sleep mode can be entered by setting the deep sleep DP bit in the Dynamic Memory Control register The device is put into a low power mode where it is powered down and no longer refreshed data in the memory is lost The memory controller supports J EDEC low power SDRAM partial array refresh Partial array refresh can be programmed by initializing the SDRAM memory device appropriately When the memory device is put into self refresh mode only the memory banks specified are refreshed The memory banks that are not refreshed lose their data contents 204 Hardware Reference NS9215 MEMORY CONTROLLER Memory map Power on reset memory map Chip select 1 memory configuration Example Boot from flash SRAM mapped after boot www digiembedded com The memory controller provides hardware support for booting from external nonvolatile memory During booting the nonvolatile memory must be located at address 0x00000000 in memory When the system is booted the SRAM or SDRAM memory can be remapped to address 0x00000000 by modifying the address map in the AHB decoder On power on reset memory chip select 1 is mirrored onto memory chip select 0 and chip select 4 Any transactions to memory chip select 0 or chip s
206. FFF Reserved 0 9002 1000 0x9002_7FFF UART C CSR Space UART D register 0x9002 8000 UART D Interrupt and FIFO Status 0x9002 8004 UART D DMA RX Control 0x9002 8008 UART D DMA RX Buffer Descriptor Pointer 0x9002 800C UART D DMA RX Interrupt Configuration register 0x9002 8010 UART D Mode RX Status FIFO 0x9002 8014 UART D Direct Mode RX Data FIFO 0x9002 8018 UART D DMA TX Control 0x9002 801C UART D DMA TX Buffer Descriptor Pointer 0x9002 8020 UART D DMA TX Interrupt Configuration register 0x9002 8024 Reserved 0x9002 8028 UART D Direct Mode TX Data FIFO 0x9002 802C UART D Direct Mode TX Data Last FIFO 370 Hardware Reference NS9215 3 March 2008 SPI register address map AD register address map Reserved Pc register address map Reserved www digiembedded com Register Offset HUB MODULE Control and status register address maps Description 31 00 0 9002 8030 0x9002_8FFF Reserved 0 9002 9000 0x9002_FFFF UART D CSR Space Register Offset Description 31 00 0 9003 0000 SPI Interrupt and FIFO Status 0x9003 0004 SPI DMA RX Control 0x9003 0008 SPI DMA RX Buffer Descriptor Pointer 0x9003 000C SPI DMA RX Interrupt Configuration register 0x9003 0010 SPI Direct Mode RX Status FIFO 0x9003 0014 SPI Direct Mode RX Data FIFO 0x9003 0018 SPI DMA TX Control 0x9003 001C SPI DMA TX Buffer Descriptor Pointer 0x9003 0020 SPI
207. GPIO Configuration registers GPIO Configuration registers 0 through 26 contain the configuration information for each of the 108 GPIO pins Each GPIO pin can have up to four functions Configure each pin for the function and direction needed using the configuration options shown below GPIO Each GPIO configuration section is set up the same way This table shows the settings configuration using bits D07 00 the same settings apply to the corresponding bits in D15 08 options D23 D16 and D31 24 Bit s Mnemonic Description D07 06 Reserved N A D05 03 FUNC Use these bits to select the function you want to use For a definition of each function see General purpose I O GPIO on page 31 000 Function 0 001 Function 1 010 Function 2 011 Function 3 100 Function 4 applicable only for GPIO 0 15 D02 DIR Controls the pin direction when the FUNC field is configured for GPIO mode function 3 0 Input Output GPIO pins reset to the input state Note The pin direction is controlled by the selected function in modes 0 through 2 01 Controls the inversion function of the GPIO pin 0 Disables the inversion function 1 Enables the inversion function This bit applies to all functional modes D00 PUDIS Controls the GPIO pin pullup resistor operation 0 Enables the pullup 1 Disables the pullup Note The pullup cannot be disabled on GPIO 9 GPIO 12 and on GPIO A 0 and GPIO A I www digiembedd
208. HB maximum burst size allowed when reading from the source Note that the source must have enough data as defined by this register setting before asserting REQ 00 1 unitas set by the source width field D28 27 01 4bytes Recommended for 8 bit devices 10 16 bytes Recommended for 16 bit devices 11 32bytes Recommended for 32 bit devices EXTERNAL DMA Control register Bit s Access Mnemonic Reset Description D22 21 R W DB 0 Destination burst Defines the AHB maximum burst size allowed when writing to the destination Note that the destination must have enough space as defined by this register setting before asserting REQ 00 1 unitas set by the destination width field D26 25 01 4 bytes Recommended for 8 bit devices 10 16 bytes Recommended for 16 bit devices 11 32 bytes Recommended for 32 bit devices D20 R W SINC_N 0 Source address increment Controls whether the source address pointers are incremented after each DMA transfer The DMA controller uses these bits in all modes whenever referring to a memory address 0 Increment source address pointer Do not increment source address pointer D19 R W DINC N 0 Destination address increment Controls whether the destination address pointers are incremented after each DMA transfer The DMA controller uses these bits whenever referring to a memory address 0 Increment destination address pointer Do not increment destination address pointer D18
209. IC 1 BUS 1 18 O gpio 61 R7 gpio 62 I O UART D dup PIC 0 BUS_1 19 1 O PIC 1 BUS_1 19 1 O gpio 62 P7 gp1o 63 IO RI UART D dup PIC 0 BUS 1 20 I O PIC 1 BUS 1 20 I O gpio 63 R8 gpio 64 I O RTS R5485 Control D dup PIC 0 BUS 1 21 I O PIC 1 BUS I 21 I 0 gpio 64 P8 38 gpio 65 Hardware Reference NS9215 IO TXC DTR UART D dup PIC 0 BUS 1 22 I O PIC 1 BUS 1 22 0 O gpio 65 265 General purpose I O GPIO Description N8 gpio 66 IO l2 c TXD UART D dup PIC 0 BUS 1 23 I O PIC 1 BUS 1 23 I O gpio 66 P9 gpio 67 0 CLK I 0 CLK O Ext Int Ch 3 dup gpio 67 R10 gplo 68 0 GEN IO 0 I O dup PIC 1 GEN IO 0 I O PIC 1 CAN RXD I dup gpio 68 P10 gpio 69 VO 0 IO 1 I O dup PIC 1 GEN IO 1 I O PIC 1 CAN TXD O dup gpio 69 N10 gpio 70 0 GEN IO 2 I O dup 1 GEN IO 2 I O PWM Ch0 gpio 70 gpio 71 0 GEN 3 1 PIC 1 GEN IO 3J I O PWM gpio 71 N12 gpio 72 0 GEN IO 4 I O 1 GEN IO 4 I O PWM 2
210. ISRA Register bit assignment Bits Access Mnemonic Reset Description D31 00 IS addr 0x0 Interrupt service routine address m A read to this register updates the priority logic block and masks the current and any lower priority interrupt requests m Write the value of the interrupt level 0 31 to clear the current priority level Interrupt Status Active Address A090 0168 The Interrupt Status Active register shows the current active interrupt request Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Interrupt status active ISA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt status active ISA Register bit assignment Bits Access Mnemonic Reset Description D31 00 R ISA 0x0 Interrupt status active Provides the status of all active enabled interrupt request levels where bit 0 is for the interrupt assigned to level 0 bit 1 is for the interrupt assigned to level 1 and so on through bit 31 for the interrupt assigned to level 31 www digiembedded com 177 SYSTEM CONTROL MODULE Interrupt Status Raw Address A090 016C The Interrupt Status Raw register shows all current interrupt requests Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Interrupt status raw ISRAW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt status raw ISRAW Register bit assignment Bits Access Mnemonic Reset Description D31 00 R ISRAW 0x0 Interrupt status raw
211. Interrupt Status register shows the current active interrupt requests The Raw Inter www digiembedded com rupts register shows the status of the unmasked interrupt requests 149 SYSTEM CONTROL MODULE The interrupt sources are assigned as shown 0 Watchdog Timer 1 Bus Error 2 Ext DMA 3 CPU Wake Interrupt 4 Ethernet Module Receive Interrupt 5 Ethernet Module Transmit Interrupt 6 Ethernet Phy Interrupt 7 UART A Interrupt 8 UART B Interrupt 9 UART C Interrupt 10 UART D Interrupt 11 SPI Interrupt 12 Reserved 13 Reserved 14 ADC Interrupt 15 Early Power Loss Interrupt 16 Interrupt 17 Interrupt 18 Timer Interrupt 0 19 Timer Interrupt 1 20 Timer Interrupt 2 21 Timer Interrupt 3 22 Timer Interrupt 4 23 Timer Interrupt 5 24 Timer Interrupt 6 25 Timer Interrupt 7 26 Timer Interrupt 8 27 Timer Interrupt 9 28 External Interrupt 0 29 External Interrupt 1 30 External Interrupt 2 31 External Interrupt 3 150 Hardware Reference NS9215 SYSTEM CONTROL MODULE Vectored interrupt controller VIC flow Vectored interrupt controller VIC flow This is how the VIC flow works 1 2 3 0 A 10 An interrupt occurs The CPU branches to either the IRQ or FIQ interrupt vector If the CPU goes to the IRQ vector the CPU reads the service routine address from the VIC s ISADDR register The READ updates the VIC s priority hardware to
212. LE SPI Serial Control Module SPI Features www digiembedded com 1 2 processor ASIC contains a single high speed four wire serial peripheral interface SPI module DMA transfers to and from system memory m Four wire interface CLK CS m supported through GPIO programming Master or slave operation High speed data transfer Master 33 33 Mbps Slave 7 50 Mbps m Programmable MSB LSB formatting Programmable SPI mode 0 1 2 or 3 m Master mode internal diagnostic loopback w A Maskable interrupt conditions Receiver idle Transmitter idle 433 SERIAL CONTROL MODULE SPI SPI module structure c c 5 o a a o Transmit Receive State kot State Machine Machine sys pag spi dk Generation v Transmit Receive MHBB gt gt Ffo Interface Interface 2 555 5 3 gt SPI controller Ce 000000000000 0000 0 00 00000 0 000000 0 0000600 0 0 000060000000 60000000 60000 0 00 00 The SPI controller provides full duplex synchronous character oriented data channel between master and slave devices using a four wire interface RXD TXD CLK CS The master interface operates in a broadcast mode The slave interface is activa
213. MA operation Enable DMA operation D30 R W CA 0 0 Channel abort When set causes the current DMA operation to complete and closes the buffer The DMA channel remains idle until this bit is cleared D29 R W FLEX I O 0x0 0 DMA controlled by CPU 1 controlled by flexible I O module This bit is valid only for channels 0 and 1 which are assigned to flexible I O module 0 and flexible I O module 1 D28 R W DIRECT 0 0 0 DMA mode 1 Direct access mode D27 R W INDEXEN 0 0 0 Hardware will not use the INDEX field when in the idle state 1 Hardware will use the INDEX field when in the idle state D26 16 N A Reserved N A N A D15 10 R STATE 0 0 DMA state machine status field D09 00 R W INDEX 0x0 When the state machine is in the idle state this register can be used to change the index This field can be read at any time to determine the current index 380 Hardware Reference NS9215 3 March 2008 I O MODULE Module DMA TX Buffer Descriptor Pointer Module DMA TX Buffer Descriptor Pointer Addresses 9000 001 9000 801 9001 001C 9001 801 9002 001 9002 801 9003 001 TX Buffer Descriptor Pointer isthe address of the first buffer descriptor for each DMA channel Register Register bit assignment Bit s Access Mnemonic Reset Description D31 00 R W TXBDP 0x0 The first buffer descriptor in the ring Used when the W bit is found which indicates the last buffer descriptor
214. Mnemonic Reset Description D31 06 N A Reserved N A N A D05 R W AFE 0 Automatic flow control 0 RTS controlled by bit 1 RTS 1 RTS controlled by 4 byte RX FIFO status D04 R W LLB 0 Local loopback enable bit TX data looped back to RX data 0 Disabled Enabled D03 02 N A Reserved N A N A D01 R W RTS 0 Controls the Request to Send RTS output 0 RTS 1 RTS 0 D00 R W DTR 0 Controls the Data Terminal Ready DTR output 0 DTR 1 1 DTR 0 UART Line Status register Address 9001 1114 9001 9114 9002 1114 9002 9114 The UART Line Status register reads the line status register This register is used for diagnostic purposes only www digiembedded com 41 SERIAL CONTROL MODULE UART UART Modem Status register Register Reserved HER THRE Bl FE PE OE DR Register bit assignment Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 R FIER N A RX FIFO error Indicates at least one parity framing or break error in the RX FIFO D06 R TEMT N A Transmit holding and shift registers empty D05 R THRE N A Transmit holding register empty D04 R BI N A Break indicator The receiver found a line break D03 R FE N A Framing error The receiver found a framing error D02 R PE N A Parity error The receiver found a parity error D01 R OE N A Overrun error The RX FIFO experienced an overrun D00 R DR N A Data ready Indicates a data byte is re
215. N MODULE Collision Window Retry register Register bit assignment Bits Access Mnemonic Reset Description D31 15 N A Reserved N A N A D14 08 R W 0 00 Non back to back inter packet gap part 1 Programmable field indicating optional carrierSense window referenced in IEEE 8 2 3 4 2 3 2 1 m is detected during the timing of IPGR1 the MAC defers to carrier m comes after IPGRI the MAC continues timing IPGR2 and transmits knowingly causing a collision This ensures fair access to the medium 5 range of values is 0x0 to IPGR2 The recommended value is 0xC D07 N A Reserved N A N A D06 00 R W IPGR2 0x00 Non back to back inter packet gap part 2 Programmable field indicating the non back to back inter packet gap The recommended value for this field 18 0x12 18d which represents the minimum IPG of 0 96 uS in 100 Mbps or 9 6 uS in 10 Mbps Collision Window Retry register Address A060 0410 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CWIN Reserved RETX www digiembedded com 293 ETHERNET COMMUNICATION MODULE Register bit assignment Bits Access Mnemonic Reset Description D31 14 N A Reserved N A N A D13 08 R W CWIN 0x37 Collision window Programmable field indicating the slot time or collision window during which collisions occur in properly configured networks
216. Normal frame filtering is still performed When a qualified frame is inserted into the receive FIFO the receive packet processor notifies the system power controller which performs the wake up sequence The frame remains in the receive FIFO until the system wakes up 267 ETHERNET COMMUNICATION MODULE Transferring a frame to system memory Receive buffer descriptor format Receive buffer descriptor format description The RD logic manages the transfer of a frame the RX FIFO to system memory The transfer is enabled by setting the ERXDMA enable receive DMA bit in Ethernet General Control Register 1 Transferring a frame in the receive FIFO to system memory begins when the RX WR logic notifies the RX RD logic that a good frame is in the receive FIFO Frames are transferred to system memory using up to four rings that is 1 2 or 3rings can also be used of buffer descriptors that point to buffers in system memory The maximum frame size that each ring can accept is programmable The first thing the RX RD logic does then is analyze the frame length in the receive status FIFO to determine which buffer descriptor to use The RD logic goes through the four buffer descriptors looking for the optimum buffer size It searches the enabled descriptors starting with A then B C and finally D any poolsthat are full that is the F bit is set in the buffer descriptor are skipped The search stops as soon asthe logic encou
217. O15 GPIO14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 il 0 GPIO13 GPIO12 Bit s Access Mnemonic Reset Description D31 24 R W 15 0 18 1 5 configuration D23 16 R W GPIO14 0x18 GPIO 14 configuration D15 08 R W GPIO13 0x18 GPIO 13 configuration D07 00 R W GPIO12 0x10 GPIO 12 configuration www digiembedded com 57 I O CONTROL MODULE 22227777771 71 GPIO Configuration registers GPIO Address A090 2010 Configuration Register 4 019 15 14 13 12 11 10 GPIO17 24 21 20 19 18 17 GPIO18 Access Mnemonic Description D31 24 R W GPIO19 0x00 GPIO 19 configuration D23 16 R W GPIO18 0x00 GPIO 18 configuration D15 08 R W GPIO17 0x00 GPIO 17 configuration D07 00 R W GPIO16 0x00 GPIO 16 configuration GPIO Address A090_2014 Configuration Register 5 31 30 29 28 27 26 24 23 21 20 19 18 17 16 2 22 15 14 13 12 11 10 8 7 5 4 3 2 1 0 21 20 Bit s Access Mnemonic Reset Description D31 24 R W GPIO23 0x00 GPIO 23 configuration D23 16 R W GPIO22 0x00 GPIO 22 configuration D15 08 R W GPIO21 0x00 GPIO 21 configuration D07 00 R W GPIO20 0x00 GPIO 20 configuration 58 Hardware Reference NS9215 Configuration Register 6 31 30 29 15 14 13 28 12 Address A090 2018 27 26 11 10 24 8 23 7 I O CONTROL MODULE GPIO Configuration registers 21 20 19 18 17 27 26 5 4 3 2 1
218. ODULE SPI SPI Control and Status registers SPI Control and Status registers Register address map The configuration registers for the SPI module are located at 0x9003 1000 9003 1000 SPI Configuration register 9003 1010 Clock Generation register 9003 1020 Interrupt Enable register 9003 1024 Interrupt Status register SPI Configuration register Register Register bit assignment www digiembedded com Address 9003 1000 This is the primary SPI Configuration register 1 2 7 20 A 2 2 20 19 18 17 16 Bits Access Mnemonic Reset Description D31 13 R W Not used 0 Write this field to 0 D12 R W MLB 0 Enable master loopback mode Write a to enable the master mode transmitter to receiver loopback function 439 SERIAL CONTROL MODULE SPI Bits Access Mnemonic Reset Description D11 08 R W DISCARD 0 Discard bytes Defines the number of bytes the receiver should drop when the transmitter has initiated a new operation new operation is defined by the chip select signal being asserted low m The programmed value defines the number of bytes to discard m maximum number of receive bytes that can be discarded is 14 D07 06 R W Not used 0 Write this field to 0 D05 04 R W MODE 0 SPI mode Defines the required interface timing as specified in Timing modes on page 435 D03 R W RXBYTE 0 Controls how the SPI receiver handles receive data m RXBYTE set to 0 The rec
219. ONTROLLER Dynamic Memory Configuration 0 3 registers Address mapping The next table shows address mapping for the Dynamic Memory Configuration 0 3 for the Dynamic registers Address mappings that are not shown in the table are reserved Memory Configuration 14 12 11 9 8 7 Description registers s 16 bit external bus high performance address mapping row bank column 0 000 00 16 Mb 2 8 2 banks row length 11 column length 9 0 000 01 16 Mb 1Mx16 2 banks row length 11 column length 8 0 0 001 00 64 Mb 8Mx80 4 banks row length 12 column length 9 0 0 001 01 64 Mb 4 16 4 banks row length 12 column length 8 0 0 010 00 128 Mb 16 8 4 banks row length 12 column length 10 0 0 010 01 128 Mb 8 16 4 banks row length 12 column length 9 0 0 011 00 256 Mb 32 8 4 banks row length 13 column length 10 0 0 011 01 256 Mb 16 16 4 banks row length 13 column length 9 0 0 100 00 512 Mb 64 8 4 banks row length 13 column length 11 0 100 01 512 Mb 32Mx16 4 banks row length 13 column length 10 16 bit external bus low power SDRAM address mapping bank row column 1 000 00 16 Mb 2 8 2 banks row length 11 column length 9 0 1 000 01 16 Mb 1 16 2 banks row length 11 column length 8 0 1 001 00 64 Mb 8 8 4 banks row length 12 column length 9 0 1 001 01 64 Mb 4 16 4 banks row length 12 column le
220. PACKAGING A1 BALL PAD CORNER 516 0 80 1 10 Hardware Reference NS9215 40000000000000000 40000000000000000 1 10 Change log 1 8 following changes were made since the last revision of this document Revision B EE Modified ADC data in the POR table Added RTC clock and battery back up connection information Updated POR and battery backup logic information for situations when the POR feature is not used Added power dissipation data for 75MHz Deleted IDDS because it does not apply to this type of IC Revision C Added Flexible Interface Module signals to include PIC signals within GPIO pin out signals table 517
221. Provides the status of all active enabled and disabled interrupt request levels where bit 0 is for the interrupt assigned to level 0 bit 1 is for the interrupt assigned to level 1 and so on through bit 31 for the interrupt assigned to level 31 Software Watchdog Configuration Address A090 0174 The Software Watchdog Configuration register configures the software watchdog timer operation Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R De SW SW SW Reserved bug WE WI WIC serv SWTCS 178 Hardware Reference NS9215 Register bit SYSTEM CONTROL MODULE Software Watchdog Timer assignment Bits Access Mnemonic Reset Description D31 09 NA Reserved N A N A D08 R W Debug 0x0 Debug mode 0 Timer enabled in CPU debug mode Timer disabled in CPU debug mode D07 R W SWWE 0x0 Software watchdog enable 0 Software watchdog disabled 1 Software watchdog enabled once set cannot be cleared D06 N A Reserved N A N A D05 R W SWWI 0x0 Software watchdog interrupt clear Write 1 then a 0 to this register to clear the software watchdog interrupt D04 R W SWWIC 0x0 Software watchdog interrupt response 0 Generate interrupt 1 Generate reset Note If the interrupt option is selected and a software watchdog timeout occurs and the interrupt has not been cleared from a pre vious timeout the reset is asserted D03 N A Reserved N A N A D02 00 R W
222. R7 Cache Operations register Function Description Drain write buffer Acts as an explicit memory barrier This instruction drains the contents of the write buffers of all memory stores occurring in program order before the instruction is completed No instructions occurring in program order after this instruction are executed until the instruction completes Use this instruction when timing of specific stores to the level two memory system has to be controlled for example when a store to an interrupt acknowledge location has to complete before interrupts are enabled Wait for interrupt Drains the contents of the write buffers puts the processor into low power state and stops the processor from executing further instructions until an interrupt or debug request occurs When an interrupt does occur the MCR instruction completes and the IRQ or FIRQ handler is entered as normal The return link in R14 irq or R14 contains the address of the MCR instruction plus eight so the typical instruction used for interrupt return SUBS PC R14 4 returns to the instruction following the MCR This table lists the cache operation functions and associated data and instruction formats for R7 Function operation Data format Instruction Invalidate and DCache SBZ MCR p15 0 Rd c7 c7 0 Invalidate Cache SBZ MCR p15 0 Rd c7 c5 0 Invalidate ICache sin
223. RC3 23 16 8 0 0 00 0000 channel disabled BRC3 15 8 87 0 0 00 0000 channel disabled BRC 7 0 870 0 00 0000 channel disabled Address decoding Address decoding www digiembedded com A central address decoder provides a select signal nsel x for each slave on the bus This table shows how the system memory address is set up to allow access to the internal and external resources on the system bus Note that the external memory chip select ranges can be reset after powerup The table shows the default powerup values you can change the ranges by writing to the BASE and MASK registers see System Memory Chip Select 0 Dynamic Memory Base and Mask registers on page 190 through System Memory Chip Select 3 Dynamic Memory Base and Mask registers on page 193 for more information Address range System functions 0x0000 0000 OxOFFF FFFF 256 MB System memory chip select 0 Dynamic memory default 0x1000 0000 Ox1FFF FFFF 256 MB System memory chip select 1 Dynamic memory default 0x2000 0000 Ox2FFF FFFF 256 MB System memory chip select 2 Dynamic memory default 0x3000 0000 Ox3FFF FFFF 256 MB System memory chip select 3 Dynamic memory default 0x4000 0000 OxAFFF FFFF 256 MB System memory chip select 0 Static memory default 0 5000 0000 0 5 FFFF 256 MB System memory chip select 1 Static memory default 0x6000 0000 Ox6FFF FFFF 256 MB System memory chip select 2 Sta
224. RFCS Receive FCS error counter R W A060 06A8 RMCA Receive multicast packet counter R W A060 06AC RBCA Receive broadcast packet counter R W A060 06 0 RXCF Receive control frame packet counter R W A060 06 4 RXPF Receive PAUSE frame packet counter R W A060 06 8 RXUO Receive unknown OPCODE counter R W A060 06BC RALN Receive alignment error counter R W A060 06 0 Reserved N A N A A060 06 4 RCDE Receive code error counter R W A060 06C8 RCSE Receive carrier sense error counter R W A060 06CC RUND Receive undersize packet counter R W A060 0600 ROVR Receive oversize packet counter R W A060 06D4 RFRG Receive fragments counter R W A060 06D8 RJBR Receive jabber counter R W A060 06DC Reserved N A N A Receive byte Incremented by the byte count of frames received with 0 to 1518 bytes including counter A060 those in bad packets excluding framing bits but including FCS bytes 069C D31 24 R Reset Read as 0 Reserved D23 00 R W Reset 0x000000 RBYT Receive packet Incremented for each received frame including bad packets and all unicast counter A060 broadcast and multicast packets 06A0 D31 18 R Reset Read as 0 Reserved 304 Hardware Reference NS9215 Receive FCS error counter A060 06 4 Receive multicast packet counter A060 06A8 Receive broadcast packet counter A060 06AC Receive control frame packet counter A060 06B0 Receive PAUSE frame packet counter A060 06B4 Receive unknown OPCODE packet counter A060
225. RIVILEGED mode only 1 Allow access to internal registers using PRIVILEGED or USER mode www digiembedded com 185 SYSTEM CONTROL MODULE PLL Configuration register Address A090 0188 The PLL Configuration register configures the PLL A write to this register reconfigures and resets the PLL PLL frequency This is the formula for PLL frequency formula PLL Veo RefCIk NR 1 NF 1 ClkOut PLL Vco OD 1 Restrictions m NR 1 range 275 2 550 2 m range 110MHz 550MHz Register Register bit assignment 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved NF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BP OD NR Bits Access Mnemonic Reset Description D31 17 N A Reserved N A N A D16 08 R W NF 0 3 PLL feedback divider D07 R W BP HW strap PLL bypass addr 7 0 PLL enabled 1 PLL bypassed D06 05 R W OD HW strap PLL output divider addr 6 5 D04 00 R W NR HW strap PLL reference clock divider addr 4 3 addr 2 0 186 Hardware Reference NS9215 SYSTEM CONTROL MODULE Active Interrupt Level ID Status register Active Interrupt Level ID Status register Address A090 018C The Active Interrupt Level ID Status register is six bits in length and shows the current active interrupt level ID Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INTID Re
226. RM CPU irq dis Must be set to 0 14 R W TMDE 1 Timing characteristics of serial data and serial clock OStandard mode Fast mode D13 R W VSCD 1 Virtual system clock divider for master and slave Must be set to 0 454 Hardware Reference NS9215 2 MASTER SLAVE INTERFACE Interrupt Codes Bits Access Mnemonic Reset Description D12 09 R W SFW OxF Spike filter width A default value of 1 is recommended Available values are 0 15 D08 00 R W CLREF 0x0 ref 9 1 The I2C clock on port iic scl out is generated by the system clock divided by the 10 bit value of ref The LSB of clk ref cannot be programmed and 18 set to 0 internally The programmed value of ref 9 1 must be greater than 3 Interrupt Codes Master slave interrupt codes www digiembedded com Interrupts are signaled in the irq code field in the STATUS REG by providing the appropriate interrupt code see Master slave interrupt codes on page 455 The ARM CPU waits for an interrupt by polling the STATUS REG or checking the irq signal An interrupt is cleared by reading the STATUS REG Which also forces the irq signal down minimum one cycle if another interrupt is stored Note RX DATA REG contains only a received byte if it is accessed after a RX DATA master or slave interrupt is signaled At all other times the internal master or slave shift register is accessed with RX DATA REG see Status Receive Data register on page 451
227. RO or SBZP When writing to this location all bits of this field PRESERVED SHOULD BE ZERO or PRESERVED by writing the same value that has been read previously from the same field 84 Hardware Reference NS9215 Note WORKING WITH THE CPU System control processor CP15 registers In all cases reading from or writing any data values to any CP15 registers including those fields specified as UNPREDICTABLE SHOULD BE ONE SHOULD BE ZERO does not cause any physical damage to the chip Register summary CP15 uses 16 registers Register locations 0 5 13 each provide access to more than one register The register accessed depends on the value of the opcode 2 field in the CP15 MRC MCR instructions see Accessing CP15 registers on page 83 m Register location 9 provides access to more than one register The register accessed depends on the value of the CRm field see Accessing CP15 registers on page 83 Register Reads Writes 0 ID code based on opcode 2 value Unpredictable 0 Cache type based on opcode 2 value Unpredictable 1 1 Control 2 Translation table base Translation table base 3 Domain access control Domain access control 4 Reserved Reserved 5 Data fault status based on opcode 2 value Data fault status based on opcode 2 value 6 Instruction fault status based on opcode 2 Instruction fault status based on opcode 2 value value 7 Cach
228. Register 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DT MT Reserved Register bit assignment Bits Access Mnemonic Reset Description D31 14 N A Reserved N A N A D13 12 R W D_T 0x0 Date tens BCD digit 0 3 D11 08 R W DU 0x0 Date units BCD digit 0 9 D07 R W MT 0x0 Months tens CD digit 0 1 D06 03 R W MU 0x0 Months units BCD digit 0 9 D02 00 N A Reserved N A N A Alarm Enable register Address 9006 0018 The Alarm Enable register sets the fields that can trigger an alarm Setting a bit enables the corresponding time unit trigger event Triggering the alarm causes an event to be generated as set in the Events Flag register If all fields are enabled an alarm is generated at the time set the specific month date hour minute second and hundredth second If only the minute field is set the alarm triggers when that particular minute is reached and every hour thereafter www digiembedded com 465 Register REAL TIME CLOCK MODULE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reserved Mnth Date Hour Min Sec Hsec Register bit assignment Bits Access Mnemonic Reset Description D31 06 N A Reserved N A N A D05 R W Mnth 0x0 Month 0 Disable the month event Enable the month event D04 R W Date 0x0 Date 0 Disable the date event Enable the date ev
229. Register bit assignment MEMORY CONTROLLER Dynamic Memory Data in to Active Command Time register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved APR Bits Access Mnemonic Description D31 04 N A Reserved N A do not modify D03 00 R W APR Last data out to active command time 0 0 0 n 1 clock cycles where the delay is in cycles OxF 16 clock cycles reset value on reset_n Dynamic Memory Data in to Active Command Time register Register www digiembedded com Address A070 0040 The Dynamic Memory Data in to Active Command Time register allows you to program the data in to active command time It is recommended that this register be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode This value normally is found in SDRAM data sheets as or Note Dynamic Memory Data in Active Command Time register is used for all four dynamic memory chip selects The worst case value for all chip selects must be programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Jh 6 5 4 3 2 1 0 Reserved DAL 241 MEMORY CONTROLLER Dynamic Memory Write Recovery Time register Register bit assignment Bits Access Mnemonic Description D3
230. Select 1 Dynamic Memory Mask A090 01 0 System Memory Chip Select 2 Dynamic Memory Base A090 01 4 System Memory Chip Select 2 Dynamic Memory Mask A090 01 8 System Memory Chip Select 3 Dynamic Memory Base A090 01EC System Memory Chip Select 3 Dynamic Memory Mask A090 01 0 System Memory Chip Select 0 Static Memory Base A090 01 4 System Memory Chip Select 0 Static Memory Mask A090 01 8 System Memory Chip Select 1 Static Memory Base A090 01FC System Memory Chip Select 1 Static Memory Mask A090 0200 System Memory Chip Select 2 Static Memory Base A090 0204 System Memory Chip Select 2 Static Memory Mask A090 0208 System Memory Chip Select 3 Static Memory Base A090 020C System Memory Chip Select 3 Static Memory Mask A090 0210 Gen ID 157 SYSTEM CONTROL MODULE General Arbiter Control register 31 24 23 16 090 0214 External Interrupt 0 Control register A090 0218 External Interrupt 1 Control register A090 021C External Interrupt 2 Control register A090 0220 External Interrupt 3 Control register A090 0224 RTC Module Control A090 0228 Power Management A090 022C AHB Bus Activity Status General Arbiter Control register Address A090 0000 The General Arbiter Control register controls whether the CPU access is routed through the main arbiter or is connected directly to the memory controller Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7
231. T COMMUNICATION MODULE Sample hash table code MERCURY EFE ht2 bits data SWAP32 hash table 1 MERCURY EFE htl bits data SWAP32 hash table 0 Function void eth make hash table WORD32 hash table Description This routine creates hash table based on the values of the MAC addresses setup by set hash bit The CRC value of each MAC address is calculated and the lower six bits are used to generate a value between 0 and 64 The corresponding bit in the 64 bit hash table is then set Parameters hash table pointer to buffer to store hash table in Return Values none static void eth make hash table WORD32 hash table 1 int index memset hash table 0 8 clear hash table for index 0 index lt mca count index for each mca address 1 set hash bit BYTE hash table calculate hash bit mca address index j 335 336 ETHERNET COMMUNICATION MODULE Sample hash table code Function void set hash bit BYTE table int bit Description This routine sets the appropriate bit in the hash table Parameters table pointer to hash table bit position of bit to set Return Values static void set hash bit BYTE table int bit int byte index bit index byte index bit gt gt 3 bit ind
232. TEM CONTROL MODULE Offset 31 24 23 16 15 8 7 0 A090 00F8 Interrupt Vector Address Register Level 13 A090 00FC Interrupt Vector Address Register Level 14 A090 0100 Interrupt Vector Address Register Level 15 A090 0104 Interrupt Vector Address Register Level 16 A090 0108 Interrupt Vector Address Register Level 17 A090 010C Interrupt Vector Address Register Level 18 A090 0110 Interrupt Vector Address Register Level 19 A090 0114 Interrupt Vector Address Register Level 20 A090 0118 Interrupt Vector Address Register Level 21 A090 011C Interrupt Vector Address Register Level 22 A090 0120 Interrupt Vector Address Register Level 23 A090 0124 Interrupt Vector Address Register Level 24 A090 0128 Interrupt Vector Address Register Level 25 A090 012C Interrupt Vector Address Register Level 26 A090 0130 Interrupt Vector Address Register Level 27 A090 0134 Interrupt Vector Address Register Level 28 A090 0138 Interrupt Vector Address Register Level 29 A090 013C Interrupt Vector Address Register Level 30 A090 0140 Interrupt Vector Address Register Level 31 A090 0144 Int Config 0 Int Config 1 Int Config 2 Int Config 3 A090 0148 Int Config 4 Int Config 5 Int Config 6 Int Config 7 A090 014C Int Config 8 Int Config 9 Int Config 10 Int Config 11 A090 0150 Int Config 12 Int Config 13 Int Config 14 Int Config 15 A090 0154 Int Config 16 Int Config 17 Int
233. The output enable is always deasserted at the same time as the chip select at the end of the transfer ROM SRAM and The memory controller uses the same read timing control for ROM SRAM and flash Flash devices Each read starts with the assertion of the appropriate memory bank chip select signals cs n and memory address addr 27 0 The read access time is determined by the number of wait states programmed for the WAITRD field in the Static Memory Read Delay register The WAITTURN field in the Static Memory Turn Round Delay register determines the number of bus turnaround wait states added between external read and write transfers 210 Hardware Reference NS9215 MEMORY CONTROLLER Static memory read Timing and parameters Static memory read Timing and parameters External memory read transfer with zero wait states External memory read transfer with two wait states www digiembedded com This section shows static memory read timing diagrams and parameters This diagram shows an external memory read transfer with the minimum zero wait states WAITRD 0 Maximum performance is achieved when accessing the external device with load multiple LDM or store multiple STM CPU instructions addr data Y cs n aum NEUF uuum st oe n WAITRD 0 WAITOEN 0 WAITPAGE N A WAITWR N A WAITWEN N A WAITTURN N A This diagram shows an external memory read transf
234. U into wait for interrupt mode In wait for interrupt mode the clock is stopped to the CPU but reset is not asserted The CPU resumes and executes a CPU Wake Interrupt when activity is detected by one of the wakeup modules selected by the other bits in this register The PC will be restored to the address after the coprocessor instruction that stopped the CPU s clock when the CPU Wake Interrupt ISR completes The processor can not wake up on a timer interrupt because the system timers are stopped when the processor enters wake for interrupt mode D30 R W HW clk scale 0x0 Hardware clock scale control 0 Disable hardware clock scale control 1 Enable hardware clock scale control Used by hardware to increase the clock rate when activity is found on one ofthe modules enabled as a wakeup module Hardware automatically increases the system clock frequencies to the value set by the max clock scale control bit in the Clock Control register D29 22 N A Reserved N A N A D21 Hardware Reference NS9215 R W MemSRFEn 0x0 SDRAM self refresh control 0 Memory self refresh control disabled 1 Memory self refresh control enabled When enabled the memory controller is automatically placed in self refresh mode when the CPU is in sleep mode and taken out of self refresh upon wakeup Bits D20 Access R W Mnemonic WakelntClr Reset 0 0 SYSTEM CONTROL MODULE Power Management Descrip
235. ULE Register 15 08 07 00 090 015 Int Config 24 Int Config 25 Int Config 26 Int Config 27 A090 0160 Int Config 28 Int Config 29 Int Config 30 Int Config 31 Register bit This is how the bits are assigned in each register using data bits 07 00 as the assignment example Bits Access Mnemonic Reset Description D07 R W IE 0 0 Interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled D06 R INV 0x0 Invert 0 Do not invert the level of the interrupt source 1 Invert the level of the interrupt source D05 R W IT 0x0 Interrupt type 0 IRQ 1 FIQ If FIQ is programmed nterrupt must be the highest priority D04 00 R W ISD 0 0 Interrupt source ID Ox1F Assign an interrupt ID to each priority level See Interrupt sources beginning on page 149 for the list of interrupt ID numbers ISADDR register Address A090 0164 The ISADDR register provides the current ISADDR value Read and write to this register for IRQ interrupts only Immediately before the read to the ISADDR register always perform an extra write or read to any other internal register to consume an extra clock cycle Make sure that the extra access is not optimized away 176 Hardware Reference NS9215 SYSTEM CONTROL MODULE Interrupt Status Active Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Interrupt service routine address ISRA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt service routine address
236. VA m Cache and MMU domain Modified virtual address AMBA domain Physical address This is an example of the address manipulation that occurs when the ARM926EJ S core requests an instruction 1 926 S core issues the virtual address of the instruction 2 The virtual address is translated using the FCSE PID fast context switch extension process ID value to the modified virtual address The instruction cache ICache and memory management unit MMU find the modified virtual address see R13 Process ID register on page 102 3 Ifthe protection check carried out by the MMU on the modified virtual address does not abort and the modified virtual address tag is in the ICache the instruction data is returned to the ARM926E S core If the protection check carried out by the MMU on the modified virtual address does not abort but the cache misses the MVA tag is not in the cache the MMU translates the modified virtual address to produce the physical address This address is given to the AMBA bus interface to perform an external access Use only MRC and MCR instructions only in privileged mode to access CP15 registers Figure 1 shows the MRC and MCR instruction bit pattern 83 WORKING WITH THE CPU System control processor CP15 registers 31 28 27 26 25 2423 21 20 19 16 15 12 1110 9 8 7 5 4 3 1 2 1111110 L CRn Rd 1 11 111
237. W FORCE 0 Enable force complete Enables interrupt generation when a force character transmission operation has completed www digiembedded com 393 394 SERIAL CONTROL MODULE UART Bits Access Mnemonic Reset Description D19 R W OFLOW 0 Enable overflow error Enables interrupt generation if the 4 character FIFO in the UART overflows Note This should not happen in a properly configured system D18 R W PARITY 0 Enable parity error Enables interrupt generation when a character is received with a parity error D17 R W FRAME 0 Enable frame error Enables interrupt generation when a character is received with a framing error D16 R W BREAK 0 Enable line break Enables interrupt generation when a line break condition occurs 15 R W BGAP 0 Enable buffer gap Enables interrupt generation when a buffer gap timeout event occurs 14 R W RXCLS 0 Software receive close Enables interrupt generation when software forces a buffer close D13 R W CGAP 0 Enable character gap Enables interrupt generation when a character gap timeout event occurs D12 R W 0 Enable character match4 Enables interrupt generation when a receive character match occurs against the Receive Match Register 4 D11 R W MATCH3 0 Enable character match3 Enables interrupt generation when a receive character match occurs against the Receive Match Register 3 D10 R W MATCH2 0 Enable character match2 Enables interrupt generati
238. W Min Int 0x0 Minute interrupt 0 Disable minute interrupt Enable minute interrupt W Sec Int 0x0 Second interrupt 0 Disable second interrupt Enable second interrupt D00 W Hsec Int 0x0 Hundredth of a second interrupt 0 Disable hundredth second interrupt 1 Enable hundredth second interrupt 468 Hardware Reference NS9215 Interrupt Disable register REAL TIME CLOCK MODULE Interrupt Disable register Address 9006 0024 The Interrupt Disable register resets interrupts that are currently enables An interrupt is disabled by writing a 1 then a 0 to the appropriate disable register bit Register 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Reserved Alrm Mnth Date Hour Min Sec Hsec Dis Dis Dis Dis Dis Dis Dis Register bit assignment Bits Access Mnemonic Reset Description D31 07 N A Reserved N A N A D06 W Alrm Dis 0x0 Alarm interrupt disable 0 Enable alarm interrupt Disable alarm interrupt D05 W Mnth Dis 0 0 Month interrupt disable 0 Enable month interrupt 1 Disable month interrupt D04 Date Dis 0 0 Date interrupt disable 0 Enable date interrupt Disable date interrupt D03 W Hour Dis 0x0 Hour interrupt disable 0 Enable hour interrupt Disable hour interrupt D02 W Min Dis 0 0 Minute interrupt disable 0 Enable minute interrupt Disable minute interrupt D01 W Sec Dis 0x0 Second interrupt disable 0 Enable sec
239. Write Recovery Time register 242 Dynamic Memory Active to Active Command Period 243 Dynamic Memory Auto Refresh Period register 243 Dynamic Memory Exit Self refresh register 244 Dynamic Memory Active Bank to Active Bank B Time register 245 Dynamic Memory Load Mode register to Active Command Time register 246 Static Memory Extended Wait register 247 EXAM Pl 247 Dynamic Memory Configuration 0 3 registers 247 Address mapping for the Dynamic Memory Configuration registers 249 Chip select and memory 250 Dynamic Memory RAS and CAS Delay 0 3 registers 250 StaticMemory Configuration 0 3 5 251 StaticMemory Write Enable Delay 0 3 2 20 254 Static Memory Output Enable Delay 0 3 255 Static Memory Read Delay 0 3 5 5 256 StaticMemory Page Mode Read Delay 0 3
240. XCL Transmit excessive collision packet counter R W A060 070C TNCL Transmit total collision counter R W A060 0710 Reserved N A N A A060 0714 Reserved N A N A A060 0718 TJBR Transmit jabber frame counter R W A060 071C TFCS Transmit FCS error counter R W A060 0720 Reserved N A N A A060 0724 TOVR Transmit oversize frame counter R W A060 0728 TUND Transmit undersize frame counter R W A060 072C TFRG Transmit fragments frame counter R W Transmit byte Incremented by the number of bytesthat were put on the wire including fragments counter A060 of frames that were involved with collisions This count does not include 06 0 preamble SFD or jam bytes D31 24 R Reset Read as 0 Reserved D23 00 R W Reset 0x000000 TBYT www digiembedded com 307 Transmit packet counter A060 06 4 Transmit multicast packet counter A060 06 8 Transmit broadcast packet counter A060 06EC Transmit deferral packet counter A060 06F4 Transmit excessive deferral packet counter A060 06F8 Transmit single collision packet counter A060 06FC ETHERNET COMMUNICATION MODULE Incremented for each transmitted packet including bad packets excessive deferred packets excessive collision packets late collision packets and all unicast broadcast and multicast packets Reserved D31 18 R Reset Read as 0 D17 00 R W Reset 0x00000 TPKT Incremented for each multicast valid frame transmitted excluding broadcast frames D31 18 R Reset
241. a buffer associated with this descriptor 000 Non AES memory to memory or external DMA mode 001 Key buffer 010 IV buffer 011 Nonce buffer CCM mode only 16 bytes fixed length 100 Additional authentication data CCM mode only 101 Data to be encrypted or decrypted The Wrap W bit when set tells the DMA controller that this is the last buffer descriptor within the continuous list of descriptors The next buffer descriptor is found using the initial DMA channel buffer descriptor pointer When the W bit is not set the next buffer descriptor is found using an offset of 0x10 from the current buffer descriptor The Interrupt bit when set tells the DMA controller to issue an interrupt to the CPU when the buffer is closed due to a normal channel completion The interrupt occurs regardless of the normal completion interrupt enable configuration for the DMA channel The Last bit when set tells the DMA controller that this buffer descriptor is the last descriptor that completes an entire message frame The DMA controller uses this bit to assert the normal channel completion status when the byte count reaches zero The Full bit when set indicates that the buffer descriptor is valid and can be processed by the DMA channel The DMA channel clears this bit after completing the transfer s 358 Hardware Reference NS9215 AES DATA ENCRYPTION DECRYPTION MODULE Decryption The DMA channel does not try a transfer when the F bit is clear The DMA
242. a zero wait write followed by a zero wait read with default a read with no turnaround between the transfers of one cycle Three wait states are added to the turnaround write transfer five wait states are added to the read transfer The five AHB arbitration cycles for the read transfer include two wait states to allow the previous write access to complete and the three standard wait states for the read transfer dk out addr A 0 B cata DA DB 5 oen _ st wen WAITRD 0 WAITOEN 0 WAITPAGE N A WAITWR 0 WAITWEN 0 WAITTURN 0 Read followed by 5 diagram shows a zero wait read followed by a zero wait write with two a write with two turnaround cycles added The standard minimum of three AHB arbitration cycles is turnaround cycles adgeg to the read transfer and two wait states are added to the write transfer as for any read write transfer sequence Ta 220 Hardware Reference NS9215 MEMORY CONTROLLER Byte lane control Timing parameters WAITRD 0 WAITOEN 0 WAITPAGE N A WAITWR 0 WAITWEN 0 WAITTURN 2 Byte lane control The memory controller generates the byte lane control signals data mask 3 0 according to these attributes m Little or big endian operation Transfer width wm External memory bank databus width defined within each control register m decoded ad
243. ady in the FIFO UART Modem Status register Address 9001_1118 9001_9118 9002_1118 9002_9118 The UART Modem Status register reads the modem status register This register is used for diagnostic purposes only 412 Hardware Reference NS9215 Register Register bit assignment www digiembedded com SERIAL CONTROL MODULE UART UART Modem Status register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DCD RI DSR CTS DDCD TERI DDSR DCTS Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 R DCD N A Reflects the status of the data carrier detect input D06 R RI N A Reflects the status of the ring indicator D05 R DSR N A Reflects the status of the data set ready input D04 R CTS N A Reflects the status of the clear to send input D03 R DDCD N A Delta DCD indicator Indicates that an edge was found on DCD since the last time the register was read D02 R TERI N A Trailing edge of RI indicator Indicates that RI has changed from a 0 to a 1 D01 R DDSR N A Delta DSR indicator Indicates that an edge was found on DSR since the last time the register was read D00 R DCTS N A Delta CTS indicator Indicates that an edge was found on CTS since the last time the register was read 413 SERIAL CONTROL MODULE UART 414 Hardware Reference NS9215 SERIAL CONTROL MODULE HDLC Re
244. age table descriptors stored in memory to determine MMU operation Register Bits Description Control register A S R Contains bits to enable the MMU M bit enable data address alignment checks A bit and to control the access protection scheme S bit and R bit Translation Table Base 31 14 Holds the physical address of the base of the translation table register maintained in main memory This base address must be ona 16 KB boundary R3 Domain Access Control 31 0 Comprises 16 two bit fields Each field defines the access register control attributes for one of 16 domains D15 to D00 R5 Fault Status registers 7 0 Indicates the cause of a data or prefetch abort and the domain IFSR and DFSR number of the aborted access when an abort occurs Bits 7 4 specify which of the 16 domains D15 to D00 was being accessed when a fault occurred Bits 3 0 indicate the type of access being attempted The value of all other bits is UNPREDICTABLE The encoding of these bits is shown in Priority encoding table on page 120 R6 Fault Address register 31 0 Holds the MVA associated with the access that caused the data abort See Priority encoding table on page 120 for details of the address stored for each type of fault R8 TLB Operations 31 0 Performs TLB maintenance operations These are either register invalidating all the unpreserved entries in the TLB or invalidating a specific entry R
245. al reset using sreset_n 011 PLL change reset 100 Software watchdog reset 101 AHB bus monitor reset Status to determine the cause of the last chip level reset N A External DMA 0 Module reset 1 Module enabled D13 D12 D11 R W N A IO hub Reserved 0x1 N A 0x1 IO hub 0 Module reset 1 Module enabled N A re 0 Module reset 1 Module enabled D10 N A Reserved N A N A D09 R W AES ADC 0 0 0x1 AES 0 Module reset 1 Module enabled ADC 0 Module reset 1 Module enabled 183 SYSTEM CONTROL MODULE Miscellaneous System Configuration and Status register Bits Access Mnemonic Reset Description D07 06 N A Reserved N A Always write to 00 D05 R W SPI 0 1 SPI 0 Module reset 1 Module enabled D04 R W UARTD 0x1 UART 0 Module reset 1 Module enabled D03 R W UART 0 1 UART C 0 Module reset 1 Module enabled D02 R W UART B 0 UART B 0 Module reset 1 Module enabled D01 R W UARTA 0 UARTA 0 Module reset 1 Module enabled D00 R W Eth MAC 0 1 Ethernet MAC 0 Module reset 1 Module enabled Miscellaneous System Configuration and Status register Address A090 0184 The Miscellaneous System Configuration and Status register configures miscellaneous system configuration bits Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mis Int
246. and a 64 KB entry is put in the TLB if the subpage permissions are identical Hardware Reference NS9215 WORKING WITH THE CPU MMU faults and CPU aborts When you use subpage permissions and the page entry has to be invalidated you must invalidate all four subpages separately MMU faults and CPU aborts Alignment fault checking Fault Address and Fault Status registers www digiembedded com The MMU generates an abort on these types of faults m Alignment faults data accesses only mw Translation faults Domain faults Permission faults In addition an external abort can be raised by the external system This can happen only for access types that have the core synchronized to the external system m Page walks m reads Nonbuffered writes wm read lock write sequence SWP Alignment fault checking is enabled by the A bit in the R1 Control register Alignment fault checking is not affected by whether the MMU is enabled Translation domain and permission faults are generated only when the MMU is enabled The access control mechanisms of the MMU detect the conditions that produce these faults If a fault is detected as a result of a memory access the MMU aborts the access and signals the fault condition to the CPU core The MMU retains status and address information about faults generated by the data accesses in the Data Fault Status register and Fault Address register see Fau
247. anged 2 Set the DIVISOR field to the value you want 3 Setthe ENABLE field to 1 The DIVISOR field must not be changed 3 d 2 7 20 2 2 20 19 18 17 16 Not used 15 12 1 10 9 8 7 6 5 4 3 2 1 0 No used Dvisor Bit s Access Mnemonic Reset Divisor D31 17 R W Not used 0 Write this field to 0 D16 R W ENABLE 0 Enable clock generation Write a 1 to this field to enable the SPI module clock generation logic D15 10 R W Not used 0 Write this field to 0 D09 00 R W DIVISOR 0 Divisor Allows you to specify the required data rate of the interface The reference clock used is the system PLL output This frequency is a nominal 300 MHz m For SPI master operation Set this field to a value no smaller than 0x009 This produces the maximum supported data rate of 33 Mbps m For SPI slave operation Always set this field to 0x006 Interrupt Enable register www digiembedded com Address 9003_ 1020 441 SERIAL CONTROL MODULE SPI Use the Interrupt Enable register to enable interrupt generation on specific events Enable the interrupt by writing 1 to the appropriate bit field s Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Not used 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not used RX IDLE Register bit assignment Bits Access Mnemonic Reset Description D31 02 R W Not used 0 Write this field to 0 D01 R W TX IDLE 0 Enable transmit idle Enables interr
248. are at the bit cell boundary and the data transitions are at the center of the bit cell the DPLL operation is adjusted accordingly Decoding biphase mark or biphase space encoding requires that the data be sampled by both edges of the recovered receive clock There is an optional IRDA compliant encode and decode function available The encoder sends an active high pulse for a zero and no pulse for a one The pulse is 1 4th of a bit cell wide The decoder watches for active low pulses which are stretched to one bit time wide to recreate the normal asynchronous waveform for the receiver enabling the IRDA compliant encode decode modifies the transmitter so there are always two opening flags transmitted Normal mode operation Example configuration www digiembedded com The HDLC achieves normal mode operation by programming the HDLC and Wrapper configuration registers This example shows a normal mode operation configuration for a typical application Any field not specified in this table can be left at reset value Control register Field HDLC Control register CLK 0x3 Enable internal clock generation HDLC Clock Divider High EN 0 1 Enable the internal clock divider the clock rate will be 1 8432 Mbps 421 SERIAL CONTROL MODULE HDLC Wrapper and HDLC Control and Status registers Control register Wrapper Configuration register RXEN 1 Enable Wrapper receiv
249. atic memories the byte lane 3 0 signal from the memory controller is usually connected to WE n write enable In this case for reads all byte lane 3 0 bits must be high which means that the byte lane state bit must be low 16 bit wide static memory devices usually have the byte lane 3 0 signals connected to the nUB and nLB upper byte and lower byte signals in the static memory In this case a write to a particular byte must assert the appropriate nUB or nLB signal low For reads all nUB and nLB signals must be asserted low so the bus is driven In this case the byte lane state must be high D06 R W PC Chip select polarity 0 Active low chip select 1 Active high chip select D05 04 N A Reserved N A do not modify D03 R W PM Page mode 0 Disabled reset on reset 1 Async page mode enabled page length four In page mode the memory controller can burst up to four external accesses Devices with asynchronous page mode burst four or higher are supported Asynchronous page mode burst two devices are not supported and must be accessed normally 253 MEMORY CONTROLLER StaticMemory Write Enable Delay 0 3 registers Bits Access Mnemonic Description D02 R W BMODE Burst mode Allows the static output enable signal to toggle during bursts 0 Do not toggle output enable during bursts 1 Toggle output enable during bursts D01 00 R W MW Memory width 00 8Sbit reset value for chip select 0 2 and on reset
250. ation This table shows how each bit configures the powerup settings 0 Use an external pulldown a l Usethe internal pullup 152 Hardware Reference NS9215 www digiembedded com Configuration bits SYSTEM CONTROL MODULE Bootstrap initialization gpio a 3 Endian configuration 0 Little endian 1 Big endian gpio a 2 Boot mode 0 Boot from SDRAM using serial SPI 1 Boot from Flash ROM gpio a 0 addr 23 Flash SPI configuration If booting from Flash 00 8bit 01 32bit 10 32bit 11 16bit If booting from SPI 00 Reserved 01 8 bit addressing 10 11 24 bit addressing 16 bit addressing addr 19 9 Gen ID addi 7 PLL bypass setting 0 Bypass 1 Normal operation addr 6 5 PLL output divider setting OD 00 01 10 11 3 2 1 0 addr 4 0 PLL reference clock divider setting NR 00111 00110 00101 00100 00011 00010 00001 00000 01111 01110 01101 31 30 29 28 27 26 25 24 23 22 21 01100 01011 01010 01001 01000 10111 10110 10101 10100 10011 10010 20 19 18 17 16 15 14 13 12 11 10 10001 10000 11111 11110 11101 11100 11011 11010 11001 11000 N UU 153 SYSTEM CONTROL MODULE System configuration registers configuration registers must be accessed as 32 bit words and as single accesses only Bursting is not allowed Register address
251. ation GPIO 36 configuration 60 Hardware Reference NS9215 CONTROL MODULE GPIO Configuration registers GPIO Address A090 2028 Configuration Register 10 31 30 29 7 26 2 20 19 18 17 4 GPIO43 GPIO42 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO4 GPIO40 Bit s Access Mnemonic Reset Description D31 24 R W GPIO43 0x18 GPIO 43 configuration D23 16 R W GPIO42 0x18 GPIO 42 configuration D15 08 R W GPIO41 0x18 GPIO 41 configuration D07 00 R W GPIO40 0x18 GPIO 40 configuration GPIO Address A090 202C Configuration Register 11 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 GPIO47 GPIO46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GPIO45 GPIO44 Bit s Access Mnemonic Reset Description D31 24 R W GPIO47 0x18 GPIO 47 configuration D23 16 R W GPIO46 0x18 GPIO 46 configuration D15 08 R W GPIO45 0x18 GPIO 45 configuration D07 00 R W GPIO44 0x18 GPIO 44 configuration www digiembedded com I O CONTROL MODULE 222777717 71 GPIO Configuration registers GPIO Address A090 2030 Configuration Register 12 GPIO GPIO51 GPIO49 GPIO50 GPIO48 Description GPIO 51 configuration GPIO 50 configuration GPIO 49 configuration Bit s Access Mnemonic Reset D31 24 R W 0 18 23 16 R W 50 0 18 D15 08 R W GPIO49 0x18 D07 00 R W GPIO48 0x18 GPIO 48 configuration Address A090 2034 Configuration Register
252. ation register 374 Hardware Reference NS9215 31 March 2008 Bit s Access Mnemonic D18 R MODIP Reset 0x0 HUB MODULE Module DMA RX Control Description Module interrupt pending The hardware module has asserted an interrupt Software must read the appropriate Interrupt Status register to determine the cause D17 16 N A Reserved N A N A D15 R RXPBUSY 0x0 0 Peripheral idle 1 Peripheral busy Note Applicable only for channels connected to the flexible I O module processors The CPU must not access the Module Direct Mode RX Data FIFO Read register when this bit is set If this bit is set the read generates a bus error D14 R RX FIFO full 0x0 Receive status and data FIFO full status 0 Not full Full D13 R RX FIFO empty Ox1 Receive status and data FIFO empty status 0 Not empty Empty D12 R TXPBUSY 0x0 0 Peripheral idle 1 Peripheral busy Note Applicable only for channels connected to the flexible I O module processors The CPU must not access the Module Direct Mode TX Data FIFO register when this bit is set If this bit is set the read generates bus error D11 R TX FIFO full 0x0 Transmit data FIFO full status 0 Not full Full D10 R TX FIFO empty 0x1 Transmit data FIFO empty status 0 Not empty Empty D09 00 N A Reserved N A N A Module DMA RX Control Addresses 9000 0004 9000 8004 9001 0004 9001 8004
253. bit D13 R W GPIO77 0 GPIO 77 control bit 14 R W GPIO78 0 GPIO 78 control bit D15 R W GPIO79 0 GPIO 79 control bit D16 R W GPIO80 0 GPIO 80 control bit D17 R W GPIO81 0 GPIO 81 control bit D18 R W GPIO82 0 GPIO 82 control bit 72 Hardware Reference NS9215 CONTROL MODULE GPIO Control registers Bit s Access Mnemonic Reset Description D19 R W GPIO83 0 GPIO 83 control bit D20 R W GPIO84 0 GPIO 84 control bit D21 R W GPIO85 0 GPIO 85 control bit D22 R W GPIO86 0 GPIO 86 control bit D23 R W GPIO87 0 GPIO 87 control bit D24 R W GPIO88 0 GPIO 88 control bit D25 R W GPIO89 0 GPIO 89 control bit D26 R W GPIO90 0 GPIO 90 control bit D27 R W GPIO91 0 GPIO 91 control bit D28 R W GPIO92 0 GPIO 92 control bit D29 R W GPIO93 0 GPIO 93 control bit D30 R W GPIO94 0 GPIO 94 control bit D31 R W GPIO95 0 GPIO 95 control bit GPIO Control Address A090_ 2078 Register 3 Bit s Access Mnemonic Reset Description R W GPIO96 0 GPIO 96 control bit D01 R W GPIO97 0 GPIO 97 control bit D02 R W GPIO98 0 GPIO 98 control bit D03 R W GPIO99 0 GPIO 99 control bit D04 R W GPIO100 0 GPIO 100 control bit D05 R W GPIO101 0 GPIO 101 control bit D06 R W GPIO102 0 GPIO 102 control bit D07 R W GPIO103 0 GPIO 103 control bit 08 R W GPIO 0 0 GPIO A 0 control bit D09 R W GPIO 1 0 GPIO A 1 control bit 10 R W GPIO A2 0 GPIO A 2 control bit D11 R W GPIO A
254. bit applies only to UART3 0 UART mode 1 HDLC mode D27 20 N A Reserved N A N A D19 R W RTSEN 0 Indicates which signal is output RTS or RS485 transceiver control 0 RTS 1 RS485 transceiver control D18 R W DTREN 0 Indicates which signal is output or TX baud clock www digiembedded com 0 DTR 1 TX baud clock 391 SERIAL CONTROL MODULE UART Bits Access Mnemonic Reset Description D17 R W RXFLUSH 0 Resets the contents of the 64 byte RXFIFO Write a 1 then a 0 to reset the FIFO D16 R W TXFLUSH N A Resets the contents of the 64 byte TX FIFO Write a 1 then a 0 to reset the FIFO D15 14 R RXBYTES 00 Indicates how many bytes are pending in the wrapper The wrapper writes to the RX FIFO only when 4 bytes are received or a buffer close event occurs such as a character gap timeout character match or error D13 R W RXCLOSE 0 Allows software to close a receive buffer Hardware clears this bit when the buffer has been closed 0 Idle or buffer already closed 1 Software initiated buffer close D12 N A Reserved N A N A D11 06 R W TXFLOW 010000 Selects which signals are routed to the for hardware flow control Transmit data is halted when the selected signal is deasserted 0 CTS 0 CTS disabled CTS enabled 1 DCD 0 DCD disabled 1 DCD enabled 2 DSR 0 DSR disabled DSR enabled 3 RI 0 RI disabled 1 RI enabled 4 Software 0 TX disabled 1 enabled 5 Receive character bas
255. ble Setto 1 to have the MAC pad all short transmit frames to 64 bytes and to append a valid CRC This bit is used in conjunction with auto detect pad enable AUTOP and pad CRC enable PADEN See PAD operation table for transmit frames below This bit is ignored if PADEN is set to 0 D05 R W PADEN Pad CRC enable 0 Short transmit frames not padded 1 The MAC pads all short transmit frames This bit is used in conjunction with auto detect pad enable AUTOP and VLAN pad enable VLANP See PAD operation table for transmit frames below D04 CRCEN CRC enable 0 Transmit frames presented to the MAC contain a CRC 1 Append a CRC to every transmit frame whether padding is required or not CRCEN must be set if PADEN is set to 1 D03 Not used Always write as 0 D02 290 Hardware Reference NS9215 HUGE Huge frame enable 0 Transmit and receive frames are limited to the MAXF value in the Maximum Frame register 1 Frames of any length are transmitted and received ETHERNET COMMUNICATION MODULE Back to Back Inter Packet Gap register Bits Access Mnemonic Reset Definition D01 R W Not used 0 Always write as 0 D00 R W FULLD 0 Full duplex 0 The MAC operates in half duplex mode 1 operates in full duplex mode PAD operation table for transmit Type AUTOP VLANP PADEN Action frames Any X X 0 No pad check CRC Any 0 0 1 Pad to 60 bytes append Any X 1
256. bytes in the current 32 bit location D08 N A Reserved N A N A D07 R FFLAG N A Full flag Indicates that the FIFO went full when the current location was written D06 00 R PSTAT N A General peripheral status unique to the peripheral attached to the channel Module Direct Mode RX Data FIFO Addresses 9000 0014 9000 8014 9001 0014 9001 8014 9002_0014 9002_8014 9003_0014 9003_8014 The Direct Mode RX Data FIFO register is used when in direct mode of operation to read the RX Data FIFO Note The Module Direct Mode RX FIFO Status register must be read before this register is read to determine the valid number of bytes in the 32 bit access The data is packed in little endian format Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Register bit assignment 5 55 Reset Description D31 00 R RXD N A RX Data FIFO Read register www digiembedded com 379 I O MODULE Module DMA TX Control Addresses 9000 0018 9000 8018 9001 0018 9001 8018 9002 0018 9002 8018 9003 0018 The DMA TX Control register contains control register settings for each transmit DMA channel Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CE CA ae DIRECT INDEXEN Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register bit assignment Bit s Access Mnemonic Reset Description D31 R W CE 0x0 Channel enable 0 Disable D
257. ce tieto 3 3V por early reference tie to ground P3 por bypass tie to 1 8V E12 reset n tie to system reset remains active low 40 ms Min after 3 3V amp 1 8V are valid 5 reset out n leave open M13 sys mode 2 0 POR disabled See System mode table amp JTAG drawing following JTAG Test 14 table L14 Hardware Reference NS9215 PINOUT 265 Power and ground If the RTC feature is not used the inputs must be terminated as shown below N4 Bat vdd tie to 3 3V aux comp tie to ground N3 M4 bat vdd reg tie to ground P2 xl rtc osc tie to ground R2 X2 rtc osc leave open If the RTC feature is used see RTC clock and battery backup drawing on page 45 Power and ground E7 E11 G7 G11 G13 L5 L7 L11 L13 N7 N11 Core VCC 1 8V Al A17 C3 C15 E5 E9 E13 75 J13 J15 N5 N13 R3 RIS U1 017 VCC 3 3V G8 G9 G10 H7 H8 H9 H10 H11 77 18 J9 710 J11 K7 K8 9 10 GND K11 L8 L9 L10 M5 www digiembedded com 51 265 52 Hardware Reference NS9215 I O Control Module ER 2 T NS9215 ASIC contains 108 pins that are designated as general purpose 1 0 GPIO m first 16 GPIO can be configured to serve one of five functions m The remaining GPIO can be configured to serve one of four functions All signals set to a disabled peripheral are held in the inactive state The I O control module contains the control
258. ceive and transmit operations Serial Control Module HDLC E 1 HDLC module allows full duplex synchronous communication Both the receiver and transmitter can select either an internal or external clock The HDLC module encapsulates data within opening and closing flags and sixteen bits of CRC precedes the closing flag information between the opening and closing flag is zero stuffed that is if five consecutive ones occur independent of byte boundaries a zero is automatically inserted by the transmitter and automatically deleted by the receiver This allows a flag byte 07Eh to be unique within a serial stream The standard CRC CCITT polynomial x16 x12 5 1 is implemented with the generator and checker preset to all ones HDLC module structure AHB Bus ref int Receive and transmit operations Both receive and transmit operations are essentially automatic www digiembedded com 415 SERIAL CONTROL MODULE HDLC Receive operation Transmit operation Transmitter underflow Clocking In the receiver each byte is marked with status to indicate end of frame short frame and CRC error The receiver automatically synchronizes on flag bytes and presets the CRC checker accordingly If the current receive frame is not needed for example because it is addressed to a different station a flag search command is available The flag search
259. cess Control register 2 Program first level and second level page tables as required ensuring that a valid translation table is placed in memory at the location specified by the Translation Table Base register When these steps have been performed you can enable the MMU by setting R1 Control register bit 0 the M bit to high 125 WORKING WITH THE CPU Disabling the MMU Care must be taken if the translated address differs from the untranslated address because several instructions following the enabling of the MMU might have been prefetched with MMU off VA MVA PA If this happens enabling the MMU can be considered as a branch with delayed execution A similar situation occurs when the MMU is disabled Consider this code sequence MRC p15 0 cl C0 0 Read control register ORR 0x1 Set M bit MCR p15 0 R1 C1 0 0 Write control register and enable MMU Fetch Flat Fetch Flat Fetch Translated Note Because the same register R1 Control register controls the enabling of ICache DCache and the MMU all three can be enabled using a single MCR instruction Clear bit 0 the M bit in the R1 Control register to disable the MMU Note f the MMU is enabled then disabled then subsequently re enabled the contents of the TLB are preserved If these are now invalid the TLB must be invalidated before re enabling the MMU see R8 TLB Operations register on page 97 TLB structure The MMU runs a si
260. channel enters an idle state upon fetching a buffer descriptor with the F bit cleared When the F bit is modified by the device driver the device driver must also write an to the CE bit in the DMA Control register to activate the idle channel Decryption 000 000000000000000000 06000000 00000 0 0 0 0000 000000 0000 00000000 9 99 9 9 94 94 94 During decryption the expanded key must be fed to the AES core backwards The hardware key expander can handle this but the input key is different than for encryption The key must be expanded and the last words must be written to the key buffer as shown m A128 bit key KO K2 is expanded to the following 32 bit word sequence 40 K41 K42 To expand the key backwards the hardware key expander needs K40 K43 m A192 bit key KO K2 K5 is expanded to the following 32 bit word sequence K46 K47 K48 49 K50 51 To expand the key backwards the hardware key expander core needs K48 51 followed by K46 47 m A256 bit key KO K2 K5 K7 is expanded to the following 32 bit word sequence K52 K53 K54 55 K56 K57 K58 K59 To expand the key backwards the hardware key expander core needs K56 59 followed by K52 55 The hardware key expander recreates all the remaining words in backwards order ECB processing ECB mode does not requir
261. cking sequence 2 icc tet i EE RR E REA ERR HR RSEN EE NR EA 122 Alignment uper erae tul e vu 123 Translation euo istae n maces 124 DOMAIN faults ctr e aee wa 124 Permissior 124 External ADO sacs sears RENTUR 125 Enabling and disabling the 0 2 00202 4 41411 3 125 Enabling the MMU iscritte Pedes cde clie tendere sia senda 125 Disabling the MMU etre tete eet Red 126 LEES 126 Caches and write 22 mem mee e enn 127 er Tei SETTE 127 Write DUP te iiss e toii pects 128 Enabling the retener traer dicet nt 128 ICache and M bit 05 2 4 2 4 2 129 ICache page table C bit 129 register C and M bits for DCache 129 DCache page table C and B settings 129 Cache MVA and Set Way formats 130 Generic virtually indexed virtually addressed 131
262. clock max MII management clock 000 4 001 4 37 5 MHz 010 6 74 9 MHz 011 8 100 10 101 20 37 5 MHz 110 30 74 9 MHz 111 40 Address A060 0424 296 Hardware Reference NS9215 Register ETHERNET COMMUNICATION MODULE MII Management Address register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SCAN READ Register bit Note f both SCAN and READ are set SCAN takes precedence assignment Bits Access Mnemonic Reset Description D31 02 N A Reserved N A N A D01 R W SCAN Automatically scan for read data Setto 1 to have the MII Management module perform read cycles continuously This is useful for monitoring link fail for example Note SCAN must transition from a 0 to a 1 to initiate the continuous read cycles D00 R W READ Single scan for read data Setto 1 to have the MII Management module perform a single read cycle The read data is returned in the MII Management Read Data register after the BUSY bit in the MII Management Indicators register has returned to a value of 0 Note READ must transition from a 0 to a 1 to initiate a single read cycle MII Management Address register 90600090600092000090000920000920000920000909009292000099200009900099000990009900090900009000091 Address A060 0428 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
263. code 2 This table describes the cache functions provided by register R7 Function Description Invalidate cache Invalidates all cache data including any dirty data Invalidate single entry using either index or Invalidates a single cache line discarding any dirty data modified virtual address Clean single data entry using either index or Writes the specified DCache line to main memory if the modified virtual address line is marked valid and dirty The line is marked as not dirty and the valid bit is unchanged Clean and invalidate single data entry using Writes the specified DCache line to main memory if the wither index or modified virtual address line is marked valid and dirty The line is marked not valid Test and clean DCache Tests a number of cache lines and cleans one of them if any are dirty Returns the overall dirty state of the cache in bit 30 See Test and clean DCache instructions on page 96 Test clean and invalidate DCache Tests a number of cache lines and cleans one of them if any are dirty When the entire cache has been tested and cleaned it is invalidated See Test and clean DCache instructions on page 96 Prefetch ICache line Performs an ICache lookup of the specified modified virtual address If the cache misses and the region is cachable a linefill is performed 94 Hardware Reference NS9215 Cache operation functions www digiembedded com WORKING WITH THE CPU
264. collision during a transmission attempt Late collisions are defined using the CWIN 13 08 field of the Collision Window Retry register D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 TLCL Incremented for each frame transmitted that experienced excessive collisions during transmission as defined by the RETX 03 00 field of the Collision Window Retry register and was aborted D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 TXCL Incremented by the number of collisions experienced during the transmission of a frame Note This register does not include collisions that result in an excessive collision count or late collisions D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0 000 TNCL Incremented for each oversized transmitted frame with an incorrect FCS value D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 TJBR Incremented for every valid sized packet with an incorrect FCS value D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 TFCS 309 ETHERNET COMMUNICATION MODULE Transmit oversize Incremented for each transmitted frame that exceeds 1518 bytes NON VLAN frame counter 1532 bytes VLAN and contains a valid FCS A060 0724 D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 TOVR Transmit Incremented for every frame less than 64 bytes with a correct FCS value This undersize frame counter also is incremented when a jumbo packet is abor
265. command forces the receiver to ignore the incoming data stream until another flag is received In the transmitter the CRC generator is preset and the opening flag transmitted automatically after the first byte is written to the transmitter buffer The CRC an the closing flag are transmitted after the byte that is written to the buffer through the Address register If no CRC is required writing the last byte of the frame to the Long Stop register automatically appends a closing flag after the last byte If the transmitter underflows either an abort or a flag istransmitted under software control There is a command available to send the abort pattern seven consecutive ones if a transmit frame needs to be aborted prematurely The abort command takes effect on the next byte boundary and causes an FEh a zero followed by seven ones transmission after which the transmitter sends the idle line condition The abort command also purges the transmit FIFO The idle line condition can be either flags or all ones Bits A 15 bit divider circuit provides the clocking for the HDLC module This clock is sixteen times the data rate The receiver uses a digital phase locked loop DPLL to generate a synchronized receive clock for the incoming data stream The HDLC module also allows for an external 1x same speed as the data rate clock for both the receiver and the transmitter HDLC receive and transmit clocks can be input or output When using an external
266. cription 31 00 0 9001 8000 B Interrupt and FIFO Status 0x9001 8804 UART B DMA RX Control 0x9001 8008 UART B DMA RX Buffer Descriptor Pointer 0x9001 800C UART B DMA RX Interrupt Configuration register 0x9001 8010 UART B Direct Mode RX Status FIFO 0x9001 8014 UART B Direct Mode RX Data FIFO 0x9001 8018 UART B DMA TX Control 0x9001 801C UART B DMA TX Buffer Descriptor Pointer 0x9001 8020 UART B DMA TX Interrupt Configuration register 0x9001 8024 Reserved 0x9001 8028 UART B Direct Mode TX Data FIFO 0x9001 802C UART B Direct Mode TX Data Last FIFO 369 MODULE Control and status register address maps Register Offset Description 31 00 0x9001 8030 0x9001_8FFF Reserved 0x9001 9000 0x9001 9FFF UART B CSR Space UART C register 0x9002 0000 UART C Interrupt and FIFO Status 0x9002 0004 UART C DMA RX Control 0x9002 0008 UART C DMA RX Buffer Descriptor Pointer 0x9002 000C UART C DMA RX Interrupt Configuration register 0x9002 0010 UART C Direct Mode RX Status FIFO 0x9002 0014 UART C Direct Mode RX Data FIFO 0x9002 0018 UART C DMA TX Control 0x9002 001C UART C DMA TX Buffer Descriptor Pointer 0x9002 0020 UART C DMA TX Interrupt Configuration register 0x9002 0024 Reserved 0x9002 0028 UART C Direct Mode TX Data FIFO 0x9002 002C UAT C Direct Mode TX Data Last FIFO 0x9002 0030 0x9002 O
267. cription D31 24 R W GPIO79 0x18 GPIO 79 configuration D23 16 78 0 18 GPIO 78 configuration D15 08 R W 77 0 18 GPIO 77 configuration D07 00 R W GPIO76 0x18 GPIO 76 configuration www digiembedded com 65 I O CONTROL MODULE 222777717 71 GPIO Configuration registers GPIO Address A090 2050 Configuration Register 20 Bit s Access Mnemonic Reset Description D31 24 R W GPIO83 0x18 GPIO 83 configuration D23 16 R W GPIO82 0x18 GPIO 82 configuration D15 08 R W GPIO81 0x18 GPIO 81 configuration D07 00 R W GPIO80 0x18 GPIO 80 configuration GPIO Address A090_2054 Configuration Register 21 31 30 29 28 27 26 23 20 19 18 Bit s Access Mnemonic Reset Description D31 24 R W GPIO87 0x18 GPIO 87 configuration D23 16 R W GPIO86 0x18 GPIO 86 configuration D15 08 R W GPIO85 0x18 GPIO 85 configuration D07 00 R W GPIO84 0x18 GPIO 84 configuration 66 Hardware Reference NS9215 Configuration Register 22 GPIO Configuration Register 23 www digiembedded com Address A090 2058 I O CONTROL MODULE GPIO Configuration registers 31 30 29 28 27 26 24 23 21 20 19 18 17 16 GPICet 15 14 13 12 11 10 8 7 5 4 3 2 1 0 9 8 5 55 Reset Description D31 24 R W GPIO91 0x18 GPIO 91 configuration D23 16 R W GPIO90 0x18 GPIO 90 configuration D15 08 R W GPIO
268. criptor occupies four locations in the RAM and the RAM is implemented as a 256x32 device This is the format of the TX buffer descriptor RAM D31 00 Hardware Reference NS9215 R W Source address ETHERNET COMMUNICATION MODULE RX FIFO RAM Offset 4 D31 11 R W Not used D10 00 R W Buffer length Offset 8 D31 00 R W Destination address not used Offset C D31 R W W Wrap D30 R W I Interrupt on buffer completion D29 R W L Last buffer on transmit frame D28 R W F Buffer full D27 16 R W Reserved N A D15 00 R W Status Transmit status from MAC See Transmit buffer descriptor format on page 270 for more information about the fields in Offset4C RX FIFO RAM EEE Address A060 2000 512 locations The 2k Byte RX FIFO RAM can be used by the CPU as a scratch pad memory during boot up CPU access is enabled by setting the RXRAM bit in the Ethernet General Control Register 1 This bit must be cleared before enabling the Ethernet receiver Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Scr Mem 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Scr Register bit assignment Bits Access Mnemonic Reset Descript
269. current buffer is closed by status bits received from the peripheral device Status bits can include conditions such as a character gap timeout character match or error condition This is the Full F bit 365 MODULE m For transmit channels CPU sets the F bit after the data is written to a buffer The DMA controller clears this bit as each buffer is read from external memory If the DMA controller ever finds that this bit is not set when the buffer descriptor is read the NRIP bit is set in the Interrupt Status register and the DMA controller stops immediately and goes to the ERROR state The CPU must clear the CE bit to restore the DMA m For receive channels hardware sets the bit after data is written to a buffer The CPU must clear the F bit after all data has been read from the buffer If the DMA controller ever finds that this bit is not clear when the buffer descriptor is read the NRIP bit is set in the Interrupt Status register and the DMA controller stops immediately The DMA controller must be soft reset after the buffer descriptor problem has been solved Control 11 0 These bits are not used Status 15 0 The status depends on the module as defined in the next tables 366 Note In direct mode the status can be read from the Direct Mode RX Status FIFO UART 15 7 Reserved 6 5 01 Error bits 3 0 indicate the error type bit 4 Reserved bit 3 Receiver overflow should never occur in a properl
270. d for all writes to a noncachable bufferable region write through region and write misses to a write back region A separate buffer is incorporated in the DCache for holding write back data for cache line evictions or cleaning of dirty cache lines m Themain write buffer has a 16 word data buffer and a four address buffer m The DCache write back buffer has eight data word entries and a single address entry The drain write buffer instruction enables both write buffers to be drained under software control The MCR wait for interrupt causes both write buffers to be drained and the ARM926EJ S processor to be put into low power state until an interrupt occurs On reset the ICache and DCache entries all are invalidated and the caches disabled The caches are not accessed for reads or writes The caches are enabled using the 1 C and M bits from the R1 Control register and can be enabled independently of one another 128 Hardware Reference NS9215 bit settings ICache page table bit settings R1 register C and M bits for DCache DCache page table C and B settings www digiembedded com WORKING WITH THE CPU Caches and write buffer This table gives the and M bit settings for the ICache and the associated behavior R1 I bit R1 M bit 926 S behavior ICache disabled instruction fetches are fetched from external memory AHB 1 0 ICache enabled MMU disabl
271. d in the page tables but do not correspond to address values that have been accessed since the TLB was invalidated m set associative part of the must be considered as a cache of the underlying page table where memory coherency must be maintained at all times To guarantee coherency if a level one descriptor is modified in main memory either an invalidate TLB or Invalidate TLB by entry operation must be used to remove any cached copies of the level one descriptor This is required regardless of the type of level one descriptor section level two page reference or fault wm f any of the subpage permissions for a given page are different each of the subpages are treated separately To invalidate all entries associated with a page with subpage permissions four MVA based invalidate operations are required one for each subpage Caches and write buffer Cache features www digiembedded com The ARM926E S processor includes an instruction cache ICache data cache DCache and write buffer The instruction cache is 8 KB in length and the data cache is 4 KB in length m The caches are virtual index virtual tag addressed using the modified virtual address MVA This avoids cache cleaning and or invalidating on context switch wm caches are four way set associative with a cache line length of eight words per line 32 bytes per line and with two dirty bits in the DCache wm DCache supports write
272. d one of the static ram chip select signals st cs n N This table shows how to program the static ram chip select control registers for access using the AHB DMA controller Fields not explicitly listed must be left in the reset state Fields listed but not defined must be defined by you Register name Comment Configuration PB 1 System requirement PM User defined Set to 1 if it is not necessary for the chip select signal to toggle for each access MW User defined Read Delay WTRD User defined To determine the read delay 1 Use this equation to compute the total delay Ta Ty T 10 0 7 Divide the total delay by the AHB clock period 8 Round up any fractional value Page Read Delay WTPG user defined For most applications this is the same value as the WTRD value 345 EXTERNAL Control and Status registers Register name Field VELU Comment Output Enable Delay WOEN User defined For most applications this field can be set to 0 Write Enable Delay WWEN User defined For most applications this field can be left in the default state Write Delay WTWR User defined For most applications this field can be left in the default state Turn Delay WTTN User defined For most applications this field can be left in the default state Control and Status registers The external DMA configuration registers are located at base address 0 080 0000 the configuration register
273. data bus SDRAM BRC Left shift value table 16 bit wide data bus SDRAM RBC www digiembedded com MEMORY CONTROLLER SDRAM Initialization Device size Configuration Load Mode register left shift 256M 1 x 8M x 32 12 2x 16M x 16 13 4x32Mx8 14 512M 2x 32M x 16 14 4x 64M x 8 15 Device size Configuration Load Mode register left shift 16M 2x 16 10 4x2Mx8 11 64 1 2 32 10 2 4 16 10 4x8Mx8 11 128M 1 x 4M x 32 10 2x 8M x 16 11 4 16Mx8 12 256M 1 x 8M x 32 11 2x 16M x 16 11 4x32Mx8 12 512M 2x 32M x 16 12 4 64M x 8 13 Device size Configuration Load Mode register left shift 16M Ix IMx16 10 2x2Mx8 12 64M 1 4 16 1 2x8Mx8 12 128 1x8Mx16 12 2 16 8 13 256 1 x 16M x 16 12 2x32M x 8 13 512 1 32 16 13 2 64 8 14 227 MEMORY CONTROLLER SDRAM address data bus interconnect Left shift value table 16 bit wide Device size Configuration Load Mode register left shift SDRAM 16M 1 1 16 9 2 2 8 10 64 1 4 16 9 2 8 8 10 128 1 8 16 10 2 16 8 11 256 1x16M x 16 10 2x32M x 8 11 512M 1 x 33M x 16 11 2x 64M x 8 12 SDRAM address and data bus interconnect The processor ASIC can connect to standard 16M and larger SDRAM components in either 16 or 32 bit wide configurations The next tables show address and data bus connec
274. ddress A070 0000 The Control register controls the memory controller operation The control bits can be changed during normal operation Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LPM ADDM MCEN 232 Hardware Reference NS9215 MEMORY CONTROLLER Control register Register bit assignment Bits Access Mnemonic Description D31 03 N A Reserved N A do not modify D02 R W LPM Low power mode 0 Normal mode reset value on reset n 1 Low power mode Indicates normal or low power mode Entering low power mode reduces memory controller power consumption Dynamic memory Is refreshed as necessary The memory controller returns to normal functional mode by clearing the low power mode bit or by power on reset If you modify this bit be sure the memory controller is in idle state If you modify the L bit be aware of these conditions m The external memory cannot be accessed in low power or disabled state If a memory access is performed in either of these states an error response is generated m The memory controller AHB programming port be accessed normally m The memory controller registers can be programmed in low power and or disabled state D01 R W ADDM Address mirror 0 Normal memory map 1 Reset memory map Static memory chip select 1 is mirrored onto chip select 0 and chip select 4 reset value on reset n Indicates nor
275. ddress into the Ethernet transmit frame source address field Set to force the MAC to automatically insert the Ethernet MAC source address into the Ethernet transmit frame source address The SA1 SA2 and SA3 registers provide the address information When the ITXA bit is cleared the Ethernet MAC source address is taken from the data in the TX FIFO D07 R W RXRAM 1 FIFO RAM access 0 CPU access to the RX FIFO RAM is disabled CPU access to the RX FIFO RAM is enabled D06 00 N A Reserved N A N A Ethernet General Control Register 2 Address A060 0004 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Not used 282 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Ethernet General Status register Register bit assignment Bits Access Mnemonic Reset Description D31 08 R W Not used 0 Always write as 0 D07 R W TCLER 0 Clear transmit error 0 1 transition Clear transmit error Clears out conditions in the transmit packet processor that have caused the processor to stop and require assistance from software before the processor can be restarted for example an AHB bus error or the TXBUFNR bit set in the Ethernet Interrupt Status register Toggle this bit from low to high to restart the transmit packet processor D06 04 R W Not used 0 Always write as 0 D03 R W TKICK 0 Transmit DMA state machine enable 01 transition used by software to start a DMA transfer after a bu
276. der AES PIFO Engine FIFO Data In Data blocks The AES module works on 128 bit blocks of data This table shows the performance per each 128 bit block depending on the key size Key size 192 Characteristic Number of cycles 44 52 60 Latency cycles 44 52 60 Throughput bits cycles 2 90 2 46 2 13 Throughput 2 75 MHz bytes sec 27 19 23 06 19 97 AES DMA buffer descriptor The AES DMA buffer descriptor is the same as the external DMA buffer descriptor with the exception of the control bits AES op and AES control 356 Hardware Reference NS9215 AES buffer descriptor diagram Source address pointer Source buffer length Destination buffer length Destination address pointer AES control www digiembedded com AES DATA ENCRYPTION DECRYPTION MODULE AES DMA buffer descriptor 31 30 29 28 16 15 0 OFFSET 0 Source address OFFSET 4 Destination buffer length Source buffer length OFFSET 48 Destination address OFFSET Reserved AES Op AES control Field definitions follow The source address pointer identifies the starting location of the source data The source address can be aligned to any byte boundary Note Optimal performance is achieved when the source address is aligned on a word boundary The source buffer length indicates the number of bytes to be read from the source After complet
277. dge sensitive input timing requirements Ouputs All electrical outputs 3 3V interface DC electrical outputs are provided below Sym Parameter Unit High level output voltage LVTTL level Min 0 6 Vit Low level input voltage Max 0 4 V LVTTL level Reset and edge sensitive input timing requirements 482 The critical timing requirement is the rise and fall time of the input If the rise time is too slow for the reset input the hardware strapping options may be registered incorrectly If the rise time of a positive edge triggered external interrupt is too slow then an interrupt may be detected on both the rising and falling edge of the input signal A maximum rise and fall time must be met to ensure that reset and edge sensitive inputs are handled correctly With Digi processors the maximum is 500 nanoseconds as shown reset n or positive edge input max 500 0 8V to 2 0V negative edge input tp max 500nsec 2 0V to 0 8V Hardware Reference NS9215 www digiembedded com TIMING Reset and edge sensitive input timing requirements If an external device driving the reset or edge sensitive input on a Digi processor cannot meet the 500ns maximum rise and fall time requirement the signal must be buffered with a Schmitt trigger device Here are sample Schmitt trigger device part numbers Manufacturer Part Number Description
278. down use the Cache Operations register 7 MCR prefetch ICache line CRm c13 lt opcode2 gt 1 to fetch the memory cache line into the cache Hardware Reference NS9215 Cache unlock procedure WORKING WITH THE CPU R10 TLB Lockdown register 8 Write lt gt 0 to Cache Lockdown register R9 setting L 1 for bit i and restoring all other bits to the values they had before the lockdown routine was started To unlock the locked down portion of the cache write to Cache Lockdown register R9 setting L 0 for the appropriate bit The following sequence for example sets the L bit to 0 for way 0 of the ICache unlocking way 0 MRC p15 0 Rn c9 1 BIC Rn Rn 0x01 MCR p15 0 Rn c9 1 R10 TLB Lockdown register Register format P bit Invalidate operation www digiembedded com The TLB Lockdown register controls where hardware page table walks place the TLB entry in the set associative region or the lockdown region of the TLB If the TLB entry is put in the lockdown region the register indicates which entry is written The TLB lockdown region contains eight entries see the discussion of the TLB structure in TLB structure beginning on page 126 for more information 31 29 28 26 25 0 SBZ Victim SBZ UNP When writing the TLB Lockdown register the value in the P bit DO determines in which region the TLB entry is placed P 0 Subsequent hardware page table walk
279. dress 31 2019 0 Section base address Section index Second level The base address of the page table to be used is determined by the descriptor descriptor returned if any from a first level fetch either a coarse page table descriptor or a fine page table descriptor The page table is then accessed and a second level descriptor returned Second level descriptor format 31 16 15 1211109 8 7 6 5 4 Fault Large page base address AP2 AP1 APO Large page Small page base address 2 AP1 APO Small page Tiny page base address AP Tiny page Second level A second level descriptor defines a tiny small or large page descriptor or is descriptor pages invalid a large page descriptor provides the base address of a 64 KB block of memory A small page descriptor provides the base address of a 4 KB block of memory 114 Hardware Reference NS9215 WORKING WITH THE CPU MemoryManagement Unit MMU m Atiny page descriptor provides the base address of 1 KB block of memory Coarse page tables provide base addresses for either small or large pages Large page descriptors must be repeated in 16 consecutive entries Small page descriptors must be repeated in each consecutive entry Fine page tables provide base addresses for large small or tiny pages Large page descriptors must be repeated in 64 consecutive entries Small page descriptors must be repeated in four consecut
280. dress value for write accesses only Word transfers are the largest size transfers supported by the memory controller Any access tried with a size greater that a word causes an error response Each memory chip select can be 8 16 or 32 bits wide The memory type used determines how the st we n and data mask signals are connected to provide byte halfword and word access For read accesses you must control the data mask signals by driving them all high or all low Do this by programming the byte lane state PB bit in the Static Configuration 3 0 register See Address connectivity on page 222 for additional information with respect to st we n and data mask for different memory configurations www digiembedded com 221 MEMORY CONTROLLER Address connectivity Memory banks For memory banks constructed from 8 bit or non byte partitioned memory devices constructed from it is important that the byte lane state PB bit is cleared to 0 within the respective 8 bit or non byte memory bank control register This forces all data mask lines high during a read partitioned access as the byte lane selects are connected to the device write enables memory devices The next figure shows 8 bit memory configuring memory banks that are 8 16 and 32 bits wide In each of these configurations the data mask 3 0 Signals are connected to write enable WE n inputs of each 8 bit memory The st we n signal from the memory controller is not used
281. dule provides a signal to the SCM module that can wake up the ARM processor This signal is asserted when a specified character is received Use the Receive Character Match Control registers and the ARM Wakeup Control register to implement the logic Example This table shows a sample configuration where the wakeup signal is asserted on configuration reception of any character Control register Field Comment Receive Character Match Control ENABLE 1 Enable character match Register Q MASK Oxff Mask all bits DATA 0x00 Don t care ARM Wakeup Control register ENABLE 1 Enable the function www digiembedded com 389 SERIAL CONTROL MODULE UART Wrapper Control and Status registers Wrapper Control and Status registers The configuration registers for UART module A start at 0 9001 1000 UART module B start at 0x9001 9000 UART module C start at 0x9002 1000 and UART module D start at 9002 9000 Register address These are the configuration registers for UART module A The configuration registers map for other UART modules are the same except they have different starting addresses 9001 1000 Wrapper Configuration 9001 1004 Interrupt Enable 9001 1008 Interrupt Status 9001 100C Receive Character GAP Control 9001 1010 Receive Buffer GAP Control 9001 1014 Receive Character Match Control 0 9001 1018 Receive Character Match Control 1 9001 101C Receive Character Match Control 2
282. dware Reference NS9215 Register bit SYSTEM CONTROL MODULE AHB Error Monitoring Configuration register assignment Bits Access Mnemonic Reset Description D31 20 N A Reserved N A N A D19 t IE Not reset CPU instruction error An error was found on CPU instruction access to external memory The other fields in this register and the AHB Error Status 1 register are not valid if this bit is set D18 DE Notreset data error An error was found on the CPU data access to external memory The other fields in this register and the AHB Error Status 1 register are not valid if this field is set D17 Not reset AHB error response Set if an AHB slave ERROR response is found D16 15 N A Reserved N A N A 14 HWR Not reset hwrite Transaction type write or read D13 10 HMSTR Not reset hmaster 3 0 Initiating master identifier D09 06 HPR Notreset hprot 3 0 Transaction protection code D05 03 HSZ Not reset hsize 2 0 Transaction size D02 00 HBRST Not reset hburst 2 0 Transaction burst type AHB Error Monitoring Configuration register Address A090 0020 The AHB Error Monitoring Configuration register configures the AHB arbiter error monitoring settings www digiembedded com 161 SYSTEM CONTROL MODULE Register 31 30 29 28 27 26 2b 24 23 22 21 20 19 18 17 16 Reserved EC Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SERDC
283. e an initialization vector Software just needs to set up key buffer descriptor followed by a data buffer descriptor Processing flow This is the ECB buffer descriptor processing flow diagram www digiembedded com 359 AES DATA ENCRYPTION DECRYPTION MODULE CBC processing Encryption Decryption Source DMA Operations Key Buffer Destination DMA Operations Data Buffer Encrypted or Decrypted Data CBC CFB OFB and CTR processing CBC CFB OFB and CTR modes need an initialization vector Software must set up this buffer descriptor sequence Key IV Data Processing flow This is the buffer descriptor processing flow for CBC CFB OFB and CTR diagram CBC OFB Mode Encryption Decryption Source DMA Operations Key Buffer i Destination DMA Operations Data Buffer Encrypted or Decrypted Data CCM mode CCM mode does not require an initialization vector 360 Hardware Reference NS9215 Nonce buffer Processing flow www digiembedded com AES DATA ENCRYPTION DECRYPTION MODULE CCM mode For encryption software must set up this buffer descriptor sequence Key Nonce additional data optional data used to compute the authentication code data used to perform the actual encryption For decryption software must set up this buffer descriptor sequence Key Nonce Data
284. e clock change is complete RTC clock ready interrupt status bit is set The clock change may take up to 30 microseconds after this bit is set Note This bit must be set to 0 when not access ing the RTC registers or battery back RAM When early power loss interrupt is detected set this bit to 0 D00 R W rdy int 0x0 RTC clock ready interrupt clear 0 RTC clock ready interrupt enabled 1 RTC clock ready interrupt cleared Note This register must be set then cleared to service the RTC clock ready interrupt www digiembedded com 201 SYSTEM CONTROL MODULE 202 Hardware Reference NS9215 Memory Controller Features 5 Multiport Memory Controller is AMBA compliant system on chip SoC peripheral that connects to the Advanced High performance Bus AHB The remainder of this chapter refers to this controller as the memory controller The memory controller provides these features m AMBA 32 bit AHB compliancy Dynamic memory interface support including SDRAM and J EDEC low power SDRAM m Asynchronous static memory device support including RAM ROM and Flash with and without asynchronous page mode m Can operate with cached processors with copyback caches operate with uncached processors m Low transaction latency m Read and write buffers to reduce latency and improve performance particularly for uncached processors m 8 bit 16 bit and 32 bit wide static memory suppo
285. e for large page references Modified virtual address 31 2019 1615 1211 0 table index Translation table base 31 14 13 0 Translation base 81 M 1413 210 eme Re First level descriptor 81 y 109 8 543210 eee Hf 31 109 210 Second level descriptor 31 1615 1211109876543210 Physical address 31 1615 0 Page base address Page index Because the upper four bits of the page index and low order four bits of the coarse page table index overlap each coarse page table entry for a large page must be duplicated 16 times in consecutive memory locations in the coarse page table If the large page descriptor is included in a fine page table the high order six bits of the page index and low order six bits of the fine page table overlap Each fine page table entry for a large page must be duplicated 64 times 116 Hardware Reference NS9215 Translating sequence for small page references www digiembedded com WORKING WITH THE CPU MemoryManagement Unit MMU Modified virtual address 31 2019 1211 0 Level two Translation table base 31 14 13 0 31 i 1413 210 Translation base Table index ol First level descriptor 109 8 543210 Coarse page table base address oman lohi 31 109 21 Coarse page table base address L2 table index ol Second level descriptor 31 1211109876543210 Page base address Physical address 1211 ole Page base address Page index If a
286. e function TXEN 1 Enable Wrapper transmit function Wrapper and HDLC Control and Status registers The configuration registers for the HDLC module are located at 0x9002 9000 Register address These are the configuration registers located within a single HDLC module map 9002 9000 Wrapper Configuration 9002 9004 Interrupt Enable 9002 9008 Interrupt Status 9002 9100 HDLC Data Register 1 9002 9104 HDLC Data Register 2 9002 9108 HDLC Data Register 3 9002 910C Reserved 9002 9110 HDLC Control Register 1 9002 9114 HDLC Control Register 2 9002 9118 HDLC Clock Divider Low 9002 911C HDLC Clock Divider High Wrapper Configuration register Address 9002 9000 This is the primary Wrapper Configuration register 422 Hardware Reference NS9215 Register Register bit assignment www digiembedded com SERIAL CONTROL MODULE HDLC Wrapper Configuration register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserv RX TX ed RXEN TXEN MODE Reserved FLUSH FLUSH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXBYTES dus CRC Reserved RL LL Reserved CLOSE Bits Access Mnemonic Reset Description D31 N A Reserved N A N A D30 R W RXEN 0 0 Disable wrapper function Enable wrapper to process receive characters D29 R W TXEN 0 0 Disable wrapper transmitter function 1 Enable wrapper to process transmit characters D28 R W MODE
287. e operations Cache operations 8 Unpredictable TLB 9 Cache lockdown based on CRm value Cache lockdown 10 TLB lockdown TLB lockdown 11 and 12 Reserved Reserved 13 FCSE PID based on opcode 2 value FCSE PID based on opcode 2 value FCSE Fast context switch extension FCSE Fast context switch extension PID Process identifier PID Process identifier 13 Context ID based on opcode 2 value Context ID based on opcode 2 value 14 Reserved Reserved 15 Test configuration Test configuration All CP15 register bits that are defined and contain state are set to 0 by reset with these exceptions m The V bit is set to 0 at reset if the VINITHI signal is low and set to 1 if the VINITHI signal is high www digiembedded com 85 WORKING WITH THE CPU ID code and cache type status registers m TheBbit is set to 0 at reset if the BIGENDINIT signal is low and set to 1 if the BIGENDINIT signal is high RO ID code and cache type status registers R0 ID code R0 Cache type register Register RO access the ID register and cache type register Reading from RO returns the device ID and the cache type depending on the opcode 2 value opcode 2 0 ID value opcode 2 1 instruction and data cache type CRm field SHOULD BE ZERO when reading from these registers This table shows the instructions you can use to read register RO Read ID code MRC p15 0 Rd c0 c0 0 3 7 Read cache type 15 0
288. e single entry SBZ MCR p15 0 Rd c8 c7 1 Invalidate set associative TLB SBZ MCR p15 0 Rd c8 c5 0 Invalidate single entry MVA MCR p15 0 Rd c8 c5 1 97 WORKING WITH THE CPU R9 Cache Lockdown register Modified virtual address format MVA Operation Instruction Invalidate set associative TLB SBZ MCR 5 0 Rd c8 0 Invalidate single entry MVA MCR p15 0 Rd c8 c6 1 m The invalidate operations invalidate all the unpreserved entries in the TLB m The invalidate single entry operations invalidate any entry corresponding to the modified virtual address given in regardless of its preserved state See R10 TLB Lockdown register beginning on page 101 for an explanation of how to preserve TLB entries This is the modified virtual address format used for invalid TLB single entry operations 31 10 9 0 Modified virtual address SBZ Note f either small or large pages are used and these pages contain subpage access permissions that are different you must use four invalidate TLB single entry operations with the MVA set to each subpage to invalidate all information related to that page held in a TLB R9 Cache Lockdown register Cache ways Register R9 access the cache lockdown registers Access this register using CRm 0 The Cache Lockdown register uses a cache way based locking scheme format C that allows you to control each cache way independently
289. e written simultaneously and RX DATA REG and STATUS REG are read simultaneously Register address This table shows the register addresses configuration registers must be accessed map as 32 bit words and as single accesses only Bursting is not allowed Register Description 9005 0000 Command Transmit Data register CMD TX DATA REG Status Receive Data register STATUS RX DATA REG 9005 0004 Master Address register 9005 0008 Slave Address register 9005 000C Configuration register After a reset all registers are set to the initial value If an unspecified register or bit is read a zero is returned Command Transmit Data register Address 9005 0000 The Command Transmit Data CMD TX DATA REG register is the primary interface register for transmission of data between the 1 hub and 12 bus This register is write only Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 170 9 8 7 6 5 4 3 2 1 0 PIPE DLEN TXVAL CMD TXDATA 450 Hardware Reference NS9215 2 MASTER SLAVE INTERFACE Status Receive Data register Register bit assignment Bits Access Mnemonic Reset Description D31 16 N A Reserved N A N A D15 W PIPE 0x0 Pipeline mode Must be set to 0 D14 W DLEN 0x0 DLEN port ic Must be set to 0 D13 W TXVAL 0x0 Provide new transmit data in CMD TX DATA REG tx data val D12 08 W CMD 0x0 Command to be sent see Master module
290. eceive idle Indicates that the receiver has moved from the active state to the idle state The receiver moves from the active state to the idle state when a start bit has not been received after the previous stop bit Receive Character GAP Control register Address 9001 100C 9001 900 9002 100 9002 900C The Receive Character GAP Control register configures the receive character gap control logic Register REGISTER Register bit assignment Bits Access Mnemonic Reset Description D31 R W ENABLE 0 Enable receive character gap timer Write a 1 to this field to enable the receive character gap timer D30 25 R W Not used 0x0 Write this field to 0 D24 00 R W VALUE 0 Value Defines the period between receiving the stop bit and asserting the character gap timeout event Use this equation to compute the required divisor value N FCLK gap period 1 Nominal 29 4912 MHz gap period Desired character gap period A reasonable setting is 10 bit periods one character plus the start and stop bits Given a data rate of 115 200bps the desired period is 86 805 and the timeout value is 25594 398 Hardware Reference NS9215 SERIAL CONTROL MODULE UART Receive Buffer GAP Control register Receive Buffer GAP Control register Register Register bit assignment Address 9001 1010 9001 9010 9002 1010 9002 9010 The Receive Buffer GAP Control register configures the receive buffer gap control logic The bu
291. ed All instruction fetches are cachable with no protection checks addresses are flat mapped that is VA MVA PA 1 1 ICache enabled MMU enabled Instruction fetches are cachable or noncachable depending on the page descriptor C bit see ICache page table C bit settings on page 129 and protection checks are performed AII addresses are remapped from VA to PA depending on the page entry that 15 the VA is translated to MVA and the MVA is remapped to a PA This table shows the page table C bit settings for the ICache R11 bit 2M bit 1 Page table Description 926 5 behavior bit 0 Noncachable ICache disabled instruction fetches are fetched from external memory 1 Cachable Cache hit Read from the ICache Cache miss Linefill from external memory This table gives the R1 Control register C and M bit settings for DCache and the associated behavior R1 C bit R1 M bit 926 5 behavior 0 0 DCache disabled data accesses are to the external memory 1 0 DCache enabled MMU disabled data accesses are noncachable nonbufferable with no protection checks addresses are flat mapped that is VA MVA PA 1 1 DCache enabled MMU enabled data accesses are cachable or noncachable depending on the page descriptor C bit and B bit see DCache page table C and B settings on page 129 and protection checks are performed addresses are remapped from VA to P
292. ed to an active low chip select SPI data order 15 reversed that is LSB last and MSB first if the BITORDR bit in Serial Channel Control Register 15 set to a 0 15 period of AHB clock 5 duty cycle skew 10 duty cycle skew Cioad for all outputs SPI data order can be reversed such that LSB is first Use the BITORDR bit in Serial Channel B A C D Control Register A 559215 Memory Timing SPI master mode 0 and 1 2 byte transfer SPO 5 k pse SPI CLK Ou Mode 1 dps SA Data ss Xs XX FX SB SPI Se Data In VES Note SPI data be reversed such that LSB is first Use the BITORDER bit in Serial Channel B A C D Control Register A SPI master mode2 and 3 2 byte transfer POs SAI CLK Out 2 A CLK Out 3 SH Endle oe SE oe boom ceo SP5 f 6655 X X A XS Note SPI data be reversed such that LSB is first Use the BITORDER bit in Serial Channel B A C D Control Register A SPI taln www digiembedded com 507 SPI slave mode 0 and 1 2 byte transfer soy p _ SA Mode 1 MM PE MSP MAE YE EES he je SH Data Out VU M8 Y X X X TSX X Spe CK XA X58 A Data In MB CS SB Note SPI data can be reversed such that LSB is first
293. ed as a reset for other components on the board RESET Can be used for a de bounced push button input A rise time of 500 5 or less is required As an alternative an external power monitor can be used to drive RESET N Leave RESET OUT N unconnected and use test mode 110 for debug and 011 for boundary scan Note 3 POR early power loss voltage trip point 1 19V min 1 28V max Preferably use a voltage divider from the main voltage used to generate the 3 3V and 1 8V If this voltage starts to drop the CPU can be interrupted ahead of time that the power is going down Also this function can be used as a general purpose analog comparator if early power loss detection is not needed Note 1 gt O JTAG 20 PIN HEADER Should be positioned on PCB with pin 1 facing toward board edge D Full Debug P Production R11 24K 48 Hardware Reference NS9215 Test Modes sys mode 2 PINOUT 265 ADC Description 4 ref adc Analog reference ground P5 VREF adc Analog reference voltage 3 3max T2 vss adc ADC VSS N6 vdd adc ADC VDD 3 3V R4 vin0_adc I ADC input 0 T3 vinl_adc I ADC input 1 R5 vin2_adc I ADC input 2 U2 vin3_adc I ADC input 3 T4 vin4_adc I ADC input 4 03 vin5 adc I ADC input 5 T5 vin6 adc I ADC input 6 vin7 adc I ADC input 7 If the ADC feature is not used the inputs must be terminated as shown below
294. ed com 55 I O CONTROL MODULE 222777717 71 GPIO Configuration registers GPIO Address A090 2000 Configuration Register 0 31 30 9 28 27 26 25 24 23 22 21 20 19 18 GPICG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 GPIOI 5 Access Mnemonic Reset Description D31 24 R W GPIO3 0x18 GPIO 3 configuration D23 16 R W GPIO2 0x18 GPIO 2 configuration D15 08 R W 0 18 GPIO 1 configuration D07 00 R W GPIOO 0x18 GPIO 0 configuration GPIO Address A090 2004 Configuration Register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 GPIO7 GPIO6 GPIO5 GPIO4 Bit s Access Mnemonic Reset Description D31 24 GPIO7 0x18 GPIO 7 configuration D23 16 R W GPIO6 0x18 GPIO 6 configuration D15 08 R W GPIOS5 0x18 GPIO 5 configuration D07 00 R W GPIO4 0x18 GPIO 4 configuration 56 Hardware Reference NS9215 CONTROL MODULE GPIO Configuration registers GPIO Address A090 2008 Configuration Register 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO11 GPIO10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO9 GPIO8 Bit s Access Mnemonic Reset Description D31 24 R W GPIO11 0x18 GPIO 11 configuration D23 16 R W GPIO10 0x18 GPIO 10 configuration D15 08 R W GPIO9 0x18 GPIO 9 configuration D07 00 R W GPIO8 0x18 GPIO 8 configuration GPIO Address A090 200 Configuration Register 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPI
295. ed flow control 0 Disabled 1 Enabled D05 R W RL 0 Remote loopback Provides an internal remote loopback feature When the RL field is set to 1 the receive serial data signal is connected to the transmit serial data signal A local loopback is provided in the UART D04 R W RTS 0 RTS control 0 Controlled directly by UART 1 Deasserted when RX FIFO is half full 392 Hardware Reference NS9215 SERIAL CONTROL MODULE UART Interrupt Enable register Bits Access Mnemonic Reset Description D03 02 R W 5485 00 RS485 transceiver deassertion control In bit times after the stop bit period 00 0 01 1 10 15 2 D01 00 R W RS4850N 00 RS485 transceiver assertion control In bit times before the falling edge of the start bit 00 0 01 1 10 15 11 2 Interrupt Enable register Address 9001 1004 9001 9004 9002 1004 9002 9004 Use the Interrupt Enable register to enable interrupt generation on specific events Enable the interrupt by writing a 1 to the appropriate bit field s Register 31 30 29 23 27 26 25 24 23 22 2 20 19 18 17 16 Not used joe FORCE OFLOW PARITY jin n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RXCLS CGAP en eH 2 DSR CTS RBC tz DE Register bit assignment Bits Access Mnemonic Reset Description D31 22 R W Not used 0 Write this field to 0 D21 R W Reserved 0 Always write to 0 D20 R
296. ee clock cycles reset value on reset D07 02 N A Reserved N A do not modify D01 00 R W RAS RAS latency active to read write delay 00 Reserved 01 One clock cycle where the RAS to CAS latency RAS and CAS latency CAS are defined in clk out cycles 10 Two clock cycles 11 Three clock cycles reset value on reset StaticMemory Configuration 0 3 registers www digiembedded com Address A070 0200 0220 0240 0260 The Static Memory Configuration 0 3 registers configure the static memory configuration It is recommended that these registers be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode 251 MEMORY CONTROLLER StaticMemory Configuration 0 3 registers Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PSMC BSMC Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EW PB PC Reserved PM BMOD MW Register bit assignment Bits Access Description D31 21 N A Reserved N A do not modify D20 R W PSMC Write protect Writes not protected reset value on reset n Write protected 19 R W BSMC Buffer enable 0 Write buffer disabled reset value on reset n Write buffer enabled Note This field must always be set to 0 when a peripheral other than SRAM is attached to the static ram chip select D18 09 N A Reserved
297. efined GPIO_A 3 status bit D31 12 N A Reserved N A N A Memory Bus Configuration register The Memory Bus Configuration register controls chip select and upper address options Address A090 208C 76 Hardware Reference NS9215 www digiembedded com I O CONTROL MODULE Memory Bus Configuration register Bit s Access Mnemonic Reset Description 02 00 R W CSO 0 4 Controls which system memory chip select is routed to 50 000 dy cs 0 001 dy cs 1 010 dy cs 2 011 dy cs 3 100 st cs 0 default 101 st cs 1 110 st cs 2 111 st cs 3 D05 03 R W CSI 0x0 Controls which system memory chip select is routed to CS1 000 dy cs 0 default 001 dy cs 1 010 dy cs 2 011 dy 3 100 st cs 0 101 st cs 1 110 st cs 2 111 st cs 3 D08 00 R W CS2 0 5 Controls which system memory chip select is routed to CS2 000 dy 0 001 dy 1 010 dy cs 2 011 dy 3 100 st cs 0 101 st cs 1 default 110 st cs 2 111 st cs 3 01 09 R W CS3 0 1 Controls which system memory chip select is routed to CS3 000 dy 0 001 dy cs 1 default 010 dy cs 2 011 dy cs 3 100 st cs 0 101 st cs 1 110 st cs 2 111 st cs 3 77 I O CONTROL MODULE 5 Access Mnemonic Reset Description D14 12 R W CS4 0x6 Controls which system memory chip select is routed to CS4 000 dy_cs 0 001 dy es 1 010 dy 2 011 dy cs 3 100 st cs 0 101 st cs 1 110 st cs 2 default 111 st cs 3 D17 15 R W 55 0 2 Controls which system mem
298. egister 2 is set to 0 Jumbo frames result in the TX buffer descriptor buffer length field being set to 0x000 If the HUGE bit is set to 0 the frame is truncated If TXAJ is set the TX_WR logic stops processing frames and sets the TXERR bit in the Ethernet Interrupt Status register D07 R Not used 0x0 Always set to 0 D06 R TXDEF 0x0 Transmit frame deferred When set indicates that the frame was deferred for at least one attempt but less than the maximum number for an excessive deferral TXDEF is also set when a frame was deferred due to a collision This bit is not set for late collisions D05 R TXCRC 0x0 Transmit CRC error When set indicates that the attached CRC in the frame did not match the internally generated CRC This bit is not set if the MAC is inserting the CRC in the frame that is the CRCEN bit 15 set in MAC Configuration Register 2 If TXCRC is set the TX WR logic stops processing frames and sets the TXERR bit in the Ethernet Interrupt Status register D04 R Not used 0x0 Always set to 0 D03 00 R TXCOLC 0x0 Transmit collision count Number of collisions the frame incurred during transmission attempts Ethernet Receive Status register 286 Address A060 001C The Ethernet Receive Status register contains the status for the last completed receive frame The RXBR bit in the Ethernet Interrupt Status register see page 317 is set whenever a receive frame is completed and
299. egister bit assignment www digiembedded com Address A060 0A10 The Ethernet Interrupt Status register contains status bits for all of the Ethernet interrupt sources Each interrupt status bit is assigned to either the RX or TX Ethernet interrupt bits D25 16 are assigned to the RX interrupt and D06 00 are assigned to the TX interrupt The bits are set to indicate an interrupt condition and are cleared by writing 1 the appropriate bit interrupts bits are enabled using the Ethernet Interrupt Enable register EINTREN If any enabled bit in the Ethernet Interrupt Status register is set its associated Ethernet interrupt to the system is set The interrupt to the system is negated when all active interrupt sources have been cleared If an interrupt source is active at the same time the interrupt bit is being cleared the interrupt status bit remains set and the interrupt signal remains set Note For diagnostics software can cause any of these interrupt status bitsto be set by writing a 1 to a bit that is 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RX RX RX RX RX RX Reserved OVFL OVFL EEG DONE DONE DONE DONE 2 BU RXBR DATA STAT B FFUL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o TX ST N TX TX TX TX Reserved OVFL used BUFC prd DONE ERR IDLE Bits Access Mnemonic Reset Description D31 26 N A Reserved N A N A D25 R C RXOVFL DATA 0 Assigned to RX
300. eiver buffers 4 bytes before writing to the RX FIFO m Writealto RXBYTE The receiver writes to the RX FIFO each time a new byte is received This allows low latency handling of SPI receive data D02 R W BITORDR 0x0 Bit ordering Controls the order in which bits are transmitted and received in the serial shift register m BITORDR set to 0 Bits are processed LSB first MSB last m BITORDR set to 1 Bits are processed MSB first LSB last Dol R W SLAVE 0 Slave enable Set this field to 1 to enable the SPI module for slave operation The SLAVE field must not be set until all SPI configuration fields have been defined You can set either the MASTER field 000 or the SLAVE field but not both D00 R W MASTER 0 Slave enable Set this field to 1 to enable the SPI module for master operation The MASTER field must not be set until all SPI configuration fields have been defined Youcan set either the MASTER field or the SLAVE field 001 but not both Clock Generation register Address 9003 1010 440 Hardware Reference NS9215 Register programming steps Register Register bit assignment SERIAL CONTROL MODULE SPI Interrupt Enable register Use this register to define the data rate of the interface This register must be programmed in three steps Failure to follow these steps can result in unpredictable behavior of the SPI module 1 Setthe ENABLE field to 0 The DIVISOR field must not be ch
301. elect 4 or chip select 1 then access memory chip select 1 Clearing the address mirror bit M in the Control register disables address mirroring and memory chip select 0 chip select 4 and memory chip select 1 can be accessed as normal You can configure the memory width and chip select polarity of static memory chip select 1 by using selected input signals This allows you to boot from chip select 1 These are the bootstrap signals m a 0 addr 23 Memory width select m gpio a 2 Boot mode The system is set up as m Chip select 1 is connected to the boot flash device Chip select 0 is connected to the SRAM to be remapped to 0x00000000 after boot This is the boot sequence 1 At power on the reset chip select 1 is mirrored into chip select 0 and chip select 4 205 Example Boot from flash SDRAM remapped after boot MEMORY CONTROLLER When the power on reset reset n goes inactive the processor starts booting from 0x00000000 in memory The software programs the optimum delay values in the flash memory so the boot code can run at full speed The code branches to chip select 1 so the code can continue executing from the non remapped memory location The appropriate values are programmed into the memory controller to configure chip select 0 The address mirroring is disabled by clearing the address mirror M field in the Control register The ARM reset and interrupt vectors are copied from flash me
302. em bus See your AMBA standards documentation for detailed information and illustrations of AMBA AHB transactions Ownership Ownership of the data bus is delayed from ownership of the address control bus When hready indicates that a transfer is complete the master that owns the address control bus can use the data bus and continues to own that data bus until the transaction completes Note f a master is assigned more than one request grant channel these channels need to be set and reset simultaneously to guarantee that a non requesting master will not occupy the system bus Locked bus The arbiter observes the hlock x signal from each master to allow guaranteed back sequence to back cycles such as read modified write cycles The arbiter ensures that no other bus masters are granted the bus until the locked sequence has completed To support SPLIT or RETRY transfers in a locked sequence the arbiter retains the bus master as granted for an additional transfer to ensure that the last transfer in the locked sequence completed successfully If the master is performing a locked transfer and the slave issues a split response the master continues to be granted the bus until the slave finishes the SPLIT response This situation degrades AHB performance Relinquishing the When the current bus master relinquishes the bus ownership is granted to the next bus requester m there are no new requesters ownership is granted to the
303. emory Active to Precharge Command Period register Address A070 0034 The Dynamic Memory Active to Precharge Command Period register allows you to program the active to precharge command period It recommended that this register be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode This value normally is found in SDRAM datasheets as tras Note The Dynamic Memory Active to Precharge Command Period register is used for all four dynamic memory chip selects The worst case value for all chip selects must be programmed Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Reserved RAS Register bit assignment Bits Access Mnemonic Description D31 04 N A Reserved N A do not modify D03 00 R W RAS Active to precharge command period tras 0 0 0 n 1 clock cycles where the delay is in cycles OxF 16 clock cycles reset value on reset_n www digiembedded com 239 MEMORY CONTROLLER Dynamic Memory Self refresh Exit Time register Dynamic Memory Self refresh Exit Time register Register Register bit assignment Address A070 0038 The Dynamic Memory Self refresh Exit Time register allows you to program the self refresh exit time It is recommended that this register be modified during sy
304. ent D03 R W Hour 0x0 Hour 0 Disable the hour event Enable the hour event D02 R W Min 0x0 Minute 0 Disable the minute event Enable the minute event 0 0 Second 0 Disable the second event 1 Enable the second event D00 R W Hsec 0x0 Hundredth of a second 0 Disable the hundredth second event 1 Enable the hundredth second event Event Flags register 466 Address 9006 001C The Event Flags register indicates that an event has occurred since the last reset Read the register to determine the cause of the current active interrupt This register is cleared when read R R in Access column Note that the Event Flags register can change even if the corresponding alarm enable bit is not set Hardware Reference NS9215 Register Register bit assignment www digiembedded com REAL TIME CLOCK MODULE Event Flags register 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 Reserved Alarm Mnth Date Hour Min Sec Hsec Evnt Evnt Evnt Evnt Evnt Evnt D31 07 Access N A Reserved Description N A N A D06 Alarm 0x0 Alarm event One of the events programmed in the Alarm Events register has triggered D05 R R Mnth Evnt 0x0 Month event 0 Month event has not occurred 1 Month event has occurred D04 R R Date Evnt 0x0 Date event 0 Date event has not occurred
305. er Oxlc DynamictRP See the Memory Controller chapter Ox20 DynamictRAS See the Memory Controller chapter Ox24 DynamictSREX See the Memory Controller chapter Ox28 DynamictAPR See the Memory Controller chapter Ox2c DynamictDAL See the Memory Controller chapter Ox30 DynamictWR See the Memory Controller chapter Ox34 DynamictRC See the Memory Controller chapter Ox38 DynamictRFC See the Memory Controller chapter Ox3c DynamictXSRt See the Memory Controller chapter Ox40 DynamictRRD See the Memory Controller chapter Ox44 DynamictMRD See the Memory Controller chapter Ox48 DynamictConfig0 See the Memory Controller chapter Field B buffer enable in the DynamicConfig0 register should be set to 0 buffers disabled The buffers will be enabled by hardware as part of the boot process Ox4c DynamictRasCas0 See the Memory Controller Chapter Ox50 Reserved Ox7c Ox80 Boot Code First 4 bytes of boot code The boot over SP operation is performed two steps a first step the hardware fetches the 16 byte header The data rate for this step is about 375 Kbps and completes in less than 0 5ms m Inthe second step the hardware fetches the image at the user specified data rate Calculate time to completion for this step as shown Time s 1 data rate For example with a 20 Mbps data rate and a 256 KB 2Mb image the time to completion is approximately 105ms 438 Hardware Reference NS9215 SERIAL CONTROL M
306. er 13 R W 0x18181818 A090 2038 GPIO Configuration Register 14 R W 0x18181818 A090 203C GPIO Configuration Register 15 R W 0x18181818 A090 2040 GPIO Configuration Register 16 R W 0x18181818 A090 2044 GPIO Configuration Register 17 R W 0x18181818 A090 2048 GPIO Configuration Register 18 R W 0x18181818 A090 204C GPIO Configuration Register 19 R W 0x18181818 A090 2050 GPIO Configuration Register 20 R W 0x18181818 A090 2054 GPIO Configuration Register 21 R W 0x18181818 A090 2058 GPIO Configuration Register 22 R W 0x18181818 A090 205C GPIO Configuration Register 23 R W 0x18181818 A090 2060 GPIO Configuration Register 24 R W 0x18181818 A090 2064 GPIO Configuration Register 25 R W 0x18181818 A090 2068 GPIO Configuration Register 26 R W 0x18181818 A090 206C GPIO Control Register 0 R W 0x00000000 A090 2070 GPIO Control Register 1 R W 0x00000000 A090 2074 GPIO Control Register 2 R W 0x00000000 A090 2078 GPIO Control Register 3 R W 0x00000000 A090 207C Status Register 0 R Undefined A090 2080 GPIO Status Register 71 R Undefined A090 2084 GPIO Status Register 2 R Undefined A090 2088 Status Register 3 R Undefined 54 Hardware Reference NS9215 CONTROL MODULE GPIO Configuration registers Address Description Access Reset value 090 208 Memory Bus Configuration register R W 007D6344 The reset values for all the status bits are undefined because they depend on the state of the GPIO pins to NS9215
307. er disabled 1 High Step register enabled D18 R W T8RSE 0x0 Timer 8 reload step enable 0 Reload Step register disabled 1 Reload Step register enabled D17 R W T8LSE 0x0 Timer 8 low step enable 0 Low Step register disabled 1 Low Step register enabled D16 R W T8HSE 0x0 Timer 8 high step enable 0 High Step register disabled 1 High Step register enabled D15 R W T7RSE 0x0 Timer 7 reload step enable 0 Reload Step register disabled 1 Reload Step register enabled 14 T7LSE 0x0 Timer 7 low step enable 0 Low Step register disabled 1 Low Step register enabled D13 R W T7HSE 0x0 Timer 7 high step enable 0 High Step register disabled 1 High Step register enabled D12 R W T6RSE 0x0 Timer 6 reload step enable 0 Reload Step register disabled 1 Reload Step register enabled D11 R W T6LSE 0x0 Timer 6 low step enable 0 Low Step register disabled 1 Low Step register enabled D10 R W T6HSE 0x0 Timer 6 high step enable 0 High Step register disabled 1 High Step register enabled 163 SYSTEM CONTROL MODULE Bits Access Mnemonic Reset Description D09 R W 9 0 0 Timer 9 enable 0 Timer reset 1 Timer enabled D08 R W T8E 0x0 Timer 8 enable 0 Timer reset 1 Timer enabled D07 R W T7E 0x0 Timer 7 enable 0 Timer reset 1 Timer enabled D06 R W T6E 0x0 Timer 6 enable 0 Timer reset 1 Timer enabled D05 R W T5E 0x0 Timer 5 enable 0 Timer reset 1 Timer enabled D04 R W T4E 0x0 Timer 4 enable 0 Timer reset
308. er with two wait states WAITRD 2 Seven AHB cycles are required for the transfer five for the standard read access and an additional two because of the programmed wait states added WAITRD addr csi 4 st oe n Timing parameter MELLT WAITRD 2 WAITOEN 0 WAITPAGE N A WAITWR N A 211 MEMORY CONTROLLER Static memory read Timing and parameters External memory read transfer with two output enable delay states External memory read transfers with zero wait states Timing parameter VELU WAITEN N A WAITTURN N A This diagram shows an external memory read transfer with two output enable delay states WAITOEN 2 Seven AHB cycles are required for the transfer five for the standard read and an additional two because of the output delay states added addr data esi st_oe_n of WAITRD 2 WAITOEN 2 WAITPAGE N A WAITWR N A WAITWEN N A WAITTURN N A This diagram shows external memory read transfers with zero wait states WAITRD 0 These transfers can be non sequential transfers or sequential transfers of a specified burst length Bursts of unspecified length are interpreted as INCR4 transfers All transfers are treated as separate reads so have the minimum of five AHB cycles added
309. eripheral The CLK signal shown is for reference and its frequency is equal to the speed grade of the part For peripheral writes the PDEN signal is an AND function of the active status of st cs n n and we n Write data into the peripheral on the falling edge of the PDEN signal Data and control signals are always held after the falling edge of PDEN for one reference CLK cycle www digiembedded com 343 EXTERNAL Peripheral REQ and DONE signaling Determining the Use the memory controller s Static Memory Write Delay register and Static Memory width of PDEN Write Enable Delay register to determine the width of the PDEN assertion Peripheral DMA single write access CLK st cs n n PDEN ADDR amp 7 Addr Data Valid Peripheral DMA burst write access CLK st cs n n wen PDEN 5 ADDRO DATAO ADDR1 DATA1 ADDR2 DATA2 Peripheral REQ and DONE signaling The processor treats the REQ and DONE signals as asynchronous level signals REQ signal m external peripheral can initiate DMA transfer at any time by asserting the REQ signal m external peripheral can pause t
310. erved N A do not modify D02 R W SR Self refresh request SREFREQ 0 Normal mode Enter self refresh mode reset value on reset n By writing 1 to this bit self refresh can be entered under software control Writing 0 to this bit returns the memory controller to normal mode The self refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the memory controller Note The memory controller exits from power on reset with the self refresh bit on high To enter normal functional mode set the self refresh bit low Writing to this register with the bit set to high places the register into self refresh mode This functionality allows data to be stored over SDRAM self refresh of the ASIC is powered down DOI R W Not used Must write 1 R W CE Dynamic memory clock enable 0 Clock enable if idle devices are deasserted to save power reset value on reset_n 1 clock enables are driven high continuously Note Clock enable must be high during SDRAM initialization Dynamic Memory Refresh Timer register Address A070 0024 236 Hardware Reference NS9215 MEMORY CONTROLLER Dynamic Memory Read Configuration register The Dynamic Memory Refresh Timer register configures dynamic memory operation It is recommended that this register be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then
311. ess OFFSET 4 Buffer Length 11 bits used OFFSET 8 Destination Address not used OFFSET C W Reserved Status Transmit buffer descriptor field Field Description W WRAP bit which when set tells the TX WR logic that this is the last buffer descriptor within the continuous list of descriptors in the TX buffer descriptor RAM The next buffer descriptor is found using the initial buffer descriptor pointer in the TX Buffer Descriptor Pointer register When the WRAP bit is not set the next buffer descriptor is located at the next entry in the TX buffer descriptor RAM I When set tells the TX WR logic to set TXBUFC in the Ethernet Interrupt Status register when the buffer is closed due to a normal channel completion Buffer pointer 32 bit pointer to the start ofthe buffer in system memory This pointer can be aligned on any byte of a 32 bit word Status Lower 16 bits of the Ethernet Transmit Status register The status 15 returned from the Ethernet MAC at the end of the frame and written into the last buffer descriptor of the frame L When set tells the TX WR logic that this buffer descriptor is the last descriptor that completes an entire frame This bit allows multiple descriptors to be chained together to make up a frame 270 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Transmit packet processor Field Description F When set indicates the buffe
312. ex bit amp 7 table byte index 1 lt lt bit index Function int calculate hash bit BYTE mca Description This routine calculates which bit in the CRC hash table needs to be set for the MERCURY to recognize incoming packets with the MCA passed to us Parameters mca pointer to multi cast address Hardware Reference NS9215 www digiembedded com Return Values bit position to set in hash table define POLYNOMIAL 0x4c11db6L static int calculate_hash_bit BYTE mca WORD32 crc WORD 16 bp bx int result index mca word bit index BYTE 156 WORD 16 copy mca 3 ETHERNET COMMUNICATION MODULE Sample hash table code memcpy copy mca mca sizeof copy mca for index 0 index lt 3 index 1 copy mca index SWAP16 copy mca index mcap copy mca crc OxffffffffL for mca word 0 mca word lt 3 mca_word 1 bp mcap for bit index 0 bit index lt 16 bit_index 1 bx WORD16 crc gt gt 16 bx rotate bx LEFT 1 bx bp cre lt lt 1 bx amp 1 if bx crc POLYNOMIAL cre bx get high word of crc bit 31 to Isb combine with incoming shift crc left 1 bit get control bit if bit set xero crc with polynomial or in control bit 337 338 ETHERNET COMMUNICATION MODULE
313. example shows the code sequence that locks down an entry to the current sequence victim ADR rl LockAddr set R1 to the value of the address to be locked down MCR 15 0 1 8 7 1 invalidate single entry to ensure that LockAddr is not already in the TLB MRC 15 0 0 10 0 0 read the lockdown register ORR r0 r0 71 set the preserve bit MCR 15 0 0 10 0 0 write to the lockdown register LDR TLB will miss and entry will be loaded MRC p15 0 10 c10 c0 0 read the lockdown register victim will have incremented BIC 1040 71 clear preserve bit MCR 15 0 0 10 0 0 write to the lockdown register R11 and R12 registers Accessing reading or writing these registers causes UNPREDICTABLE behavior R13 Process ID register The Process ID register accesses the process identifier registers The register accessed depends on the value on the opcode 2 field opcode 2 0 Selects the Fast Context Switch Extension FCSE Process Identifier PID register 102 Hardware Reference NS9215 FCSE PID register Access instructions Register format Performing a fast context switch www digiembedded com WORKING WITH THE CPU R13 Process ID register opcode_2 1 Selects the context ID register Use the Process ID register to determine the process that is currently running The process identifier is set to 0 at reset Addresses issued by the ARM926E S core in the range 0 to 32 MB a
314. f the appropriate memory bank chip selects cs n n and address signals addr 27 0 n The write access time is determined by the number of wait states programmed for the wAITWR field in the Static Memory Write Delay register see Static Memory Write Delay 0 3 registers on page 257 The WAITTURN field in the bank control register see StaticMemory Turn Round Delay 0 3 registers on page 258 determines the number of bus turnaround wait states added between external read and write transfers Static memory Write Timing and parameters This section shows static memory write timing diagrams and parameters External memory This diagram shows a single external memory write transfer with minimum zero write transfer wait states WAITWR 0 One wait state is added with zero wait states addr i i data cs n st we n 216 Hardware Reference NS9215 External memory write transfer with two wait states External memory write transfer with two write enable delay states www digiembedded com MEMORY CONTROLLER Static memory Write Timing and parameters WAITRD N A WAITOEN N A WAITPAGE N A WAITWR 0 WAITWEN 0 WAITTURN N A This diagram shows a single external memory write transfer with two wait states WAITWR 2 One AHB wait state is added exe deed de Ede qo Ip addr data D A cs n EC st wen D S Timing parameter
315. fer descriptor 268 Receive buffer descriptor format 268 Receive buffer descriptor field 5 22 269 Transmit packet 2 nnn 269 Transmit buffer descriptor 270 Transmit buffer descriptor field definitions 270 Transmitting a fr tfie e RETE RR 271 Frame transmitted 5 3 272 Frame transmitted 4 0 0 0 22 272 Transmitting a frame to the Ethernet 272 bare ra Ege 272 Ethernet slave 273 aon 273 Interr pt 50 0 273 Status DIES 12 274 aL TULIT 274 Multicast address filtering 275 Filter 2d Fontis 275 Multicast address filter 2 0 2 2 2 2 2 22 215 Multicast address filtering example 1 2
316. fer descriptors are 16 bytes in length and are located contiguously in external memory This is the format of the buffer descriptor Address Description offset 0 Source address offset 4 Reserved Buffer length offset 8 Reserved offset C Control Status The source address pointer points to the start of the buffer in system memory transmit channels the address can start on any byte boundary mw receive channels the address must be a 32 bit word aligned The buffer length is the length of the buffer in bytes and allows a buffer size of up to 64k 1 bytes to be in a single buffer Bits 31 16 are not used For receive channels the buffer length field is updated with the actual number of bytes written to memory as the peripheral has the ability to close the buffer early The Wrap W bit when set tells the DMA controller that this is the last buffer descriptor within the continuous list of descriptors The next descriptor is found using the initial DMA channel buffer descriptor pointer When the W bit is not set the next buffer descriptor is found using the 16 byte offset The Interrupt 1 bit when set tells the DMA controller to issue an interrupt when the buffer is closed due to normal channel completion This is the Last L bit For transmit channels firmware sets the L bit when the current buffer is the last in the packet For receive channels hardware sets the L bit when the
317. ffer Descriptor Pointer register A060 0A24 TXSPTR TX Stall Buffer Descriptor Pointer register A060 0A28 RXAOFF RX_A Buffer Descriptor Pointer Offset register A060 0A2C RXBOFF RX_B Buffer Descriptor Pointer Offset register A060 0A30 RXCOFF RX_C Buffer Descriptor Pointer Offset register A060 0A34 RXDOFF RX_D Buffer Descriptor Pointer Offset register A060 0A38 TXOFF Transmit Buffer Descriptor Pointer Offset register A060 RXFREE RX Free Buffer register A060 0A40 MFILTLO Multicast Low Address Filter Register 0 A060 0A44 MFILTL1 Multicast Low Address Filter Register 1 A060 0A48 MFILTL2 Multicast Low Address Filter Register 2 A060 0A4C MFILTL3 Multicast Low Address Filter Register 3 A060 0 50 MFILTL4 Multicast Low Address Filter Register 4 A060 0 54 MFILTLS Multicast Low Address Filter Register 5 A060 0 58 MFILTL6 Multicast Low Address Filter Register 6 A060 0A5C MFILTL7 Multicast Low Address Filter Register 7 A060 0A60 MFILTHO Multicast High Address Filter Register 0 A060 0A64 MFILTHI Multicast High Address Filter Register 1 A060 0A68 MFILTH2 Multicast High Address Filter Register 2 A060 0A6C MFILTH3 Multicast High Address Filter Register 3 A060 0 70 MFILTH4 Multicast High Address Filter Register 4 A060 0A74 MFILTH5 Multicast High Address Filter Register 5 A060 0 78 MFILTH6 Multicast High Address Filter Register 6 A060 MFILTH7 Multicast High Address Filter Register 7 A060 0A80 MFMSKLO Multicast Low Address Mask Registe
318. ffer descriptor has been updated D02 R W AUTOZ 0 Enable statistics counter clear on read 0 Nochange in counter value after read 1 Counter cleared after read When set configures all counters in the Statistics module to clear on read If AUTOZ is not set the counters retain their value after a read The counters can be cleared by writing all zeros DOI R W CLRCNT 1 Clear statistics counters 0 Do not clear all counters 1 Clear all counters When set synchronously clears all counters in the Statistics module D00 R W STEN 0 Enable statistics counters 0 Counters disabled Counters enabled When set enables all counters in the Statistics module If this bit is cleared the counters will not update Ethernet General Status register Address A060 0008 www digiembedded com 283 ETHERNET COMMUNICATION MODULE Ethernet Transmit Status register Register Register bit assignment 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved bos Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits Access Mnemonic Reset Description D31 21 N A Reserved N A N A D20 R C RXINIT 0x0 RX initialization complete Set when the RX_RD logic has completed the initialization of the local buffer descriptor registers requested when ERXINIT in Ethernet General Control Register 1 is set The delay from ERXINIT set to RXINIT set is less than five microseconds D19 00 N A Reserved N A N A Et
319. ffer gap timer starts when the first character in a new buffer is received Reserved SB SP EPS FEN STB WS Bits Access Mnemonic Reset Description D31 R W ENABLE 0 Enable transmit bit rate generation Write a 1 to enable the transmit bit rate generator D30 25 R W Not used 0x0 Write this field to 0 D24 00 R W VALUE 0 Value Defines the period between receiving the stop bit and asserting the buffer gap timeout event Use this equation to compute the required divisor value N FCLK gap period 1 Nominal 29 4912 Mhz gap period Desired buffer gap period A reasonable setting is 64 character or 640 bit periods Glven a data rate of 115 200 bps the desired period is 5 55ms and the timeout value is 163 839 Receive Character Match Control register www digiembedded com Addresses 9001 1014 9001 1018 9001 901 9001 9020 9001 1024 9001 9014 9001 9018 9001 901C 9001 9020 9001 9024 9002 1014 9002 1018 9002 101C 9002 1020 9002 1024 9002 9014 9002 9018 9002 901 9002 9020 9002 9024 399 SERIAL CONTROL MODULE UART Receive Character Based Flow Control register The Receive Character Match Control registers configure the receive character match control logic Each UART module has five Receive Character Match Control registers Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN ABLE Not used VALUE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
320. fication are defined as follows Burst length 4 for 32 bit data bus 8 for 16 bit data bus Burst type Sequential CAS latency Component specific 2 or 3 OpMode Standard Write burst mode Programmed burst length This value must be left shifted such that it 1s aligned to the row address bits as specified in Address mapping beginning on page 229 For example 4Mx16 components can be combined to create a 32 bit bus These parts require 12 row address bits With a CAS2 access the Mode register contents would be 0x22 This value is shifted 12 places to the left 0x00022000 to form the value in the SDRAM config field 0x8 Divisor 9 0 Defines the interface data rate for the boot over SPI 31 10 reserved operation after the initial 16 bytes A data rate of about 375 Kbps fetches the 16 byte header See the Clock Generation register for more details HS Read 0 A lindicates the external device supports high speed read 31 1 reserved operation Serial FLASH devices operating above 20MHz generally support this feature 0x10 Config register See the Memory Controller chapter 437 SERIAL CONTROL MODULE SPI Time to completion Entry Description 0x14 DynamicRefresh See the Memory Controller chapter For example the value of this entry is 0x00000025 given a 74 9 MHz AHB clock and a 7 8125ys refresh period 18 DynamicReadConfig See the Memory Controller chapt
321. fields The byte lane signals will always go low one clock before we n goes low and will go one clock high after we n goes high 4 Ifthe PB field is set to 0 the byte lane signals will function as the write enable signals and the we n signal will always be high 5 If the PB field is set to 0 the timing for the byte lane signals is set with the WTWR and WWEN fields 500 Hardware Reference NS9215 Slow peripheral acknowledge timing www digiembedded com TIMING Memory Timing The table below describes the values shown in the slow peripheral acknowledge timing diagrams Parm Description Min Unit Notes 15 clock high to data out valid 2 2 ns M16 data out hold time from clock high 2 2 ns 17 clock high to address valid 2 42 ns 18 address hold time from clock high 2 42 ns M19 clock high to st_cs_n low 2 2 ns 2 M20 clock high to st_cs_n high 2 2 ns 2 M21 clock high to we_n low 2 2 ns M22 clock high to we n high 2 2 ns M23 clock high to byte lanes low 2 2 ns M24 lock high to byte lanes high 2 2 ns M26 data input hold time to rising clk 0 ns M27 clock high to oe n low 2 2 ns M28 clock high to oe n high 2 2 ns M29 address chip select valid to ta strb high 2 CPU cycles M30 ta strb pulse width 4 8 CPU cycles M31 ta strb rising to chip select address change 4 10 CPU cycles M32 data setup to strb rising 0 ns 501 TIMING Slow perip
322. gister bit assignment Address A070 0048 The Dynamic Memory Active to Active Command Period register allows you to program the active to active command period It is recommended that this register be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode This value normally is found in SDRAM datasheets as tpc Note The Dynamic Memory Active to Active Command period register is used for all four dynamic memory chip selects The worst case value for all chip selects must be programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RC Bits Access Mnemonic Description D31 05 N A Reserved N A do not modify D04 00 R W RC Active to active command period tgc 0 0 0 1 n 1 clock cycles where the delay is in cycles Ox1F 32 clock cycles reset value on reset_n Dynamic Memory Auto Refresh Period register www digiembedded com Address A070 004C The Dynamic Memory Auto Refresh Period register allows you to program the auto refresh period and the auto refresh to active command period It is recommended that this register be modified during initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode This value norma
323. gister bit assignment Bits Access Mnemonic Reset Description D31 06 N A Reserved N A N A D05 00 R INTID 0x0 Interrupt ID The level ID of the current active interrupt Power Management Address A090 0228 The power management register controls the processor power management features Register 31 30 29 28 27 26 2b 24 23 22 21 20 19 18 17 16 HW dk en MemSRWakelnt Ext Int stale Fen Ext Int Ext Int Ext Int 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UART UART UART B A Reserved Reserved gp VART www digiembedded com 187 assignment 188 SYSTEM CONTROL MODULE Register bit D31 Access R W Mnemonic en Reset 0x0 Description Deprecated Chip sleep enable This control bit is provided for backwards compatibility with software written for the NS9750 and NS9360 processors and should not be used by new software System software writes a 1 to this bit to stop the clock to the CPU Note that software is responsible for stopping the clocks to all other modules except the wakeup module s before setting this bit When this bit is set the clock to the CPU is stopped and the CPU is held in reset New designs should not use this bit They should stop the clock by executing the following coprocessor instruction MCR p15 0 lt Rd gt c7 c0 4 This instruction places the ARM9 CP
324. gle entry MVA MCR p15 0 r0 c7 c10 4 drain write buffer MCR p15 0 ry c7 c5 invalidate icache single entry MVA 135 WORKING WITH THE CPU Noncachable instruction fetches 136 Hardware Reference NS9215 System Control Module Features E R 4 System Control Module configures and oversees system operations for the processor and defines both the AMBA High speed Bus AHB arbiter system and system memory address space The System Control Module uses the following to configure and maintain system operations m AHB arbiter system m System level address decoding m 11 programmable timers Watchdog timer 10 general purpose timers counters m Interrupt controller a Multiple configuration and status registers m System Sleep Wake up processor Bus interconnection The AMBA AHB bus protocol uses a central multiplexor interconnection scheme All bus masters generate the address and control signals that indicate the transfer that the bus masters want to perform The arbiter determines which master has its address and control signals routed to all slaves A central decoder is required to control the read data and response multiplexor which selects the appropriate signals from the slave that is involved in the transfer 137 SYSTEM CONTROL MODULE System bus arbiter High speed bus system High speed bus arbiters How the bus arbiter works The bus arbitration mechanism ensures
325. gle entry MVA MVA MCR 15 0 Rd c7 c5 1 Invalidate ICache single entry set way Set Way MCR 5 0 Rd c7 5 2 Prefetch ICache line MVA MVA MCR p15 0 Rd c7 c13 1 Invalidate DCache SBZ MCR 15 0 Rd c7 c6 0 Invalidate DCache single entry MVA MVA 5 0 Rd c7 Invalidate DCache single entry set way Set Way MCR 5 0 Rd c7 2 Clean DCache single entry MVA MVA 5 0 Rd c7 c10 1 Clean DCache single entry set way Set Way 5 0 Rd c7 C10 2 Test and clean DCache N A 5 0 Rd c7 c10 3 Clean and invalidate DCache entry MVA MVA MCR p15 0 Rd c7 14 1 Clean and invalidate DCache entry set way Set Way 15 0 Rd c7 c14 2 Test clean and invalidate DCache N A MRC 5 0 Rd c7 c14 3 95 WORKING WITH THE CPU Modified virtual address format MVA Set Way format Set Way example Test and clean DCache instructions Function operation Data format Instruction Drain write buffer SBZ MCR p15 0 Rd c7 c10 4 Wait for interrupt SBZ MCR p15 0 Rd c7 c0 4 This is the modified virtual address format for Rd for the CP15 R7 MCR operations 31 5 5 5 4 5 4 21 0 Set index Word SBZ m tag set and word fields define the For all cache operations the word field SHOULD BE ZERO This is the Set Way format for Ra for the CP15 R7 MCR operations 31 32 31 A 5 5 5 4 5 4 21 0
326. guration register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register bit assignment Bit s Access Mnemonic Reset Description D31 00 R W RXBDP 0x0 The first buffer descriptor in the ring Used when the W bit is found which indicates the last buffer descriptor in the list Module RX Interrupt Configuration register Addresses 9000 000 9000 800C 9001 000 9001 800 9002 000 9002 800 9003 000 9000 800 RX Interrupt Configuration register allows system software to configure the interrupt for the I O hub module receive channel Register 31 30 29 28 27 26 2b 24 23 22 21 20 19 18 17 16 Reser RXTHRS ved RXECIE RXNRIE RXCAIE LSTAT FSTAT ve ISTAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BLENSTAT Register bit assignment 5 Access Mnemonic Reset Description D31 28 RXTHRS OxF RX FIFO threshold An interrupt is generated when the FIFO level rises above this level D27 N A Reserved N A N A www digiembedded com 377 MODULE Module Direct Mode RX Status 5 55 Reset Description D26 R W RXFOFIE 0x0 Enable the RXFOFIP interrupt D25 R W RXFSRIE 0x0 Enable the RXFSRIP interrupt D24 R W RXNCIE 0 0 Enable the inter
327. hat is the last buffer descriptor for the frame in the TX buffer descriptor RAM when the signal is received www digiembedded com 271 ETHERNET COMMUNICATION MODULE Frame transmitted successfully Frame transmitted unsuccessfully Transmitting a frame to the Ethernet MAC Ethernet underrun The TX WR logic examines the status received from the MAC after it hastransmitted the frame If the frame was transmitted successfully the TX wR logic sets TXDONE frame transmission complete in the Ethernet Interrupt Status register and reads the next buffer descriptor If a new frame is available that is the F bit is set the TX WR starts transferring the frame If a new frame is not available the TX WR logic sets the TXIDLE TX WR logic has no frame to transmit bit in the Ethernet Interrupt Status register and waits for the software to toggle TCLER clear transmit logic in Ethernet General Control Register 2 from low to high to resume processing When TCLER is toggled transmission starts again with the buffer descriptor pointed to by the Transmit Recover Buffer Descriptor Pointer register Software should update this register before toggling TCLER If the TX WR logic detects that the frame was aborted or had an error the logic updates the current buffer descriptor as described in the previous paragraph If the frame was aborted before the last buffer descriptor of the frame was accessed the result is a situation in which the sta
328. he TX buffer descriptor RAM and points to the first location of the four location buffer descriptor The byte offset of this buffer descriptor can be calculated by multiplying this value by 4 This is the buffer descriptor at which the TX WR logic resumes processing when TCLER is toggled from low to high in Ethernet General Control Register 2 TX Error Buffer Descriptor Pointer register Address A060 0 20 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TXERBD www digiembedded com 321 ETHERNET COMMUNICATION MODULE UTE TX Stall Buffer Descriptor Pointer register Register bit assignment Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 00 R TXERBD 0x00 Contains the pointer in the TX buffer descriptor RAM to the last buffer descriptor of a frame that was not successfully transmitted TXERBD 15 loaded by the TX WR logic when a transmit frame is aborted by the MAC or when the MAC finds a CRC error in a frame TXERBD also is loaded if a buffer descriptor that is not the first buffer descriptor in a frame does not have its F bit set Note This pointer is the 8 bit physical address of the TX buffer descriptor RAM and points to the first location of the four location buffer descriptor The byte offset of this buffer descriptor can be calculated by multiplying this value by 4 Note Software uses TX
329. he DMA transfer at any time by deasserting the REQ signal m REQ signal be deasserted during a transfer but if the peripheral is configured for burst access the burst completes The DMA transfer control logic remains paused until the REQ signal is reasserted 344 Hardware Reference NS9215 DONE signal Special circumstances EXTERNAL DMA Static RAM chip select configuration The external peripheral can terminate the DMA transfer at any time by asserting the DONE signal The peripheral must also deassert the REQ signal when it asserts the DONE signal The DONE signal can be asserted during a transfer but if the peripheral is configured for burst access the burst completes When the DMA control logic finds a DONE assertion it closes the current buffer descriptor asserts a premature buffer completion status and pauses until the REQ signal is reasserted The DONE cycle must be deasserted no later that four AHB clock cycles before reasserting the REQ signal For memory to memory DMA transfers that are initiated by software writing a 1 to the channel go CG field in the DMA Control register the DMA control logic ignores the REQ and DONE signals For memory to peripheral transfers the DMA control logic ignores the DONE signal Static RAM chip select configuration Static ram chip select configuration www digiembedded com The AHB controller accesses an external peripheral using the external memory bus an
330. he EFE module includes a set of control and status registers a receive packet processor and a transmit packet processor On one side the Ethernet front end interfaces to the MAC and provides all control and status signals required by the MAC On the other side the Ethernet front end interfaces to the system Receive packet The receive packet processor accepts good Ethernet frames for example valid processor checksum and size from the Ethernet MAC and commits them to external system memory Bad frames for example invalid checksum or code violation and frames with unacceptable destination addresses are discarded 266 Hardware Reference NS9215 Transmit packet processor ETHERNET COMMUNICATION MODULE Receive packet processor The 2K byte RX FIFO allows the entire Ethernet frame to be buffered while the receive byte count is analyzed The receive byte count is analyzed by the receive packet processor to select the optimum sized buffer for transferring the received frame to system memory The processor can use one of four different sized receive buffers in system memory The transmit packet processor transfers frames constructed in system memory to the Ethernet MAC The software initializes a buffer descriptor table in a local RAM that points the transmit packet processor to the various frame segments in system memory The 256 byte TX FIFO decouples the data transfer to the Ethernet MAC from the AHB bus fill rate Receive packet proces
331. he FLOW STATE field to XON upon match 11 ChangetheFLOW STATE field to XOFF upon match D03 02 R W FLOWI 0 Flow control enable Allows you to define flow characteristics using the DATA and MASK fields on the Receive Character Match Control Register 1 Note The ENABLE field has no effect on the flow control logic The flow control is defined as shown Ox Disabled 10 Change the FLOW STATE field to upon match 11 Change the FLOW_STATE field to XOFF upon match D01 00 R W FLOWO 0 Flow control enable Allows you to define flow characteristics using the DATA and MASK fields on the Receive Character Match Control Register 0 Note The ENABLE field has no effect on the flow control logic The flow control is defined as shown Ox Disabled 10 Change the FLOW STATE field to upon match 11 Change the FLOW_STATE field to XOFF upon match Force Transmit Character Control register Address 9001 102C 9001 902C 9002 102C 9002 902C Use the Force Transmit Character Control register to override the normal flow of transmit data 402 Hardware Reference NS9215 SERIAL CONTROL MODULE UART ARM Wakeup Control register Register 31 3 29 7 260 25 A 22 21 20 19 18 17 16 EN BE BUSY Not used 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not used CHAR Register bit assignment Bits Access Mnemonic Reset Description D31 R W ENABLE 0 Force transmit enable Use this field to force the t
332. heral acknowledge read Ons 50ns 100ns 150ns I ot tod I lI f I I ot tot data lt 31 0 gt addr 27 0 cs lt 3 0 gt _ byte lane 3 0 ta strb Slow peripheral acknowledge write 100ns ps clk_out data lt 31 0 gt addr 27 0 st cs lt 3 0 gt we n byte lt 3 0 gt ta strb 502 Hardware Reference NS9215 Ethernet timing Ethernet MII timing www digiembedded com TIMING Memory Timing All AC characteristics are measured with 10pF unless otherwise noted The table below describes the values shown in the Ethernet timing diagrams Parm Description Min Unit Notes El MII tx_clk to txd tx_en tx_er 3 11 ns 2 E2 rxd en rx er setup to rx rising 3 ns E3 MII rxd en rx er hold from rx rising 1 ns E4 mdio input setup to mdc rising 10 ns 5 input hold from mdc rising 0 ns 2 E6 mdc to mdio output 18 34 ns 1 2 E7 period 80 ns 3 Notes 1 Minimum specification is for fastest AHB bus clock of 88 5 MHz Maximum specification is for slowest AHB bus clock of 51 6 MHz 2 load 10pf for all outputs and bidirects 3 Minimum specification is for fastest AHB clock at 88 5 MHz M vasoj en x er E 2 rxd 3 0 rx en rx er N N E5 t E4 mdio input 2 E6 mdio output Xd 50
333. hernet Transmit Status register Register Address A060 0018 The Ethernet Status register contains the status for the last transmit frame The TXDONE bit in the Ethernet Interrupt Status register see page 317 is set upon completion of a transmit frame and the Ethernet Transmit Status register is loaded at the same time Bits 15 0 are also loaded into the Status field of the last transmit buffer descriptor for the frame 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not TX TX Not TXCOLC OK BR MC AL AED AEC AUR AJ used DEF CRC used 284 Hardware Reference NS9215 Register bit assignment D31 16 Access N A Mnemonic Reserved N A ETHERNET COMMUNICATION MODULE Ethernet Transmit Status register Description N A D15 TXOK 0x0 Frame transmitted OK When set indicates that the frame has been delivered to and emptied from the transmit FIFO without problems D14 D13 TXBR TXMC 0x0 0x0 Broadcast frame transmitted When set indicates the frame s destination address was a broadcast address Multicast frame transmitted When set indicates the frame s destination address was a multicast address D12 TXAL 0x0 TX abort late collision When set indicates that the frame was aborted due to a collision that occurred beyond the collision window set in the Collision
334. hese bits are cleared the corresponding bit in the Ethernet Interrupt Status register cannot cause the interrupt signal to the system to be asserted when it is set Register Register bit assignment www digiembedded com EN EN EN EN RX EN RX EN RX EN RX gu Reserved 28 JE PONE DONE PONE BONE RXBR 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 reser Sa See wr ome mx x Bits Access Mnemonic Reset Description D3 1 26 N A Reserved N A N A D25 R W EN RXOVFL DATA 0 Enable the RXOVFL DATA interrupt bit D24 R W EN RXOVFL STAT 0 Enable the RXOVFL STATUS interrupt bit D23 R W EN RXBUFC 0 Enable the RXBUFC interrupt bit D22 R W EN RXDONEA 0 Enable the RXDONEA interrupt bit D21 R W EN RXDONEB 0 Enable the RXDONEB interrupt bit D20 R W EN RXDONEC 0 Enable the RXDONEC interrupt bit D19 R W EN RXDONED 0 Enable the RXDONED interrupt bit D18 R W EN RXNOBUF 0 Enable the RXNOBUF interrupt bit D17 R W EN RXBUFFUL 0 Enable the RXBUFFUL interrupt bit 319 ETHERNET COMMUNICATION MODULE TX Buffer Descriptor Pointer register Bits Access Mnemonic Reset Description D16 R W EN RXBR 0 Enable the RXBR interrupt bit D15 07 N A Reserved N A N A D06 R W EN STOVFL 0 Enable the STOVFL interrupt bit D05 R W Not used 0 Always write as 0 D04 R W EN TXBUFC 0 Enable the TXBUFC interrupt bit
335. hold from last 3 10 2 ns 0 3 1 3 falling SPI enable low hold from last SPICLK out 10 ns 1 2 1 3 rising SP11 SPI CLK out high time SP13 45 SPI3 55 ns 0 1 2 4 3 SP12 SPI CLK out low time SP13 45 5 55 ns 0 1 2 4 3 SP13 SPI CLK out period Tpcrk 6 ns 0 1 2 3 3 SPI slave parameters SP14 SPI enable low setup to first SPI CLK in 30 ns 0 3 1 rising SP15 SPI enable low setup to first SPI CLK in 30 ns 1 2 1 falling SP16 SPI data in setup to SPI CLK in rising 0 ns 0 3 SP17 SPI data in hold from SPI CLK in rising 60 ns 0 3 SP18 SPI data in setup to SPI CLK in falling 0 ns 1 2 SP19 SPI data in hold from SPI CLK in falling 60 ns 1 2 SP20 SPI CLK in falling to SPI data out valid 20 70 ns 0 3 6 SP21 SPI CLK in rising to SPI data out valid 20 70 ns 1 2 6 505 ING 506 Parm Description Min Unit Mod es es SP22 SPI enable low hold from last SPICLK in 15 ns 0 3 1 falling SP23 SPI enable low hold from last SPI CLK in 15 ns 12 1 rising SP24 SPI CLK in high time 5 26 40 5 26 60 ns 01 22 5 3 SP25 SPI CLK in low time SP26 40 SP26 60 ns 0 1 2 5 3 SP26 SPI CLK in period Tpcrk 8 ns 0 1 2 3 Notes 1 d t oU Hardware Reference Active level of SPI enable is inverted that is 1 if the CSPOL bit in Serial Channel Control Register 15 set to a 1 Note that in SPI slave mode only a value of 0 low enable is valid the SPI slave is fix
336. ic Memory Configuration Register 1 A070 0224 StaticWaitWenl Static Memory Write Enable Delay 1 A070 0228 StaticWaitOenl Static Memory Output Enable Delay 1 A070 022C StaticWaitRdl Static Memory Read Delay 1 A070 0230 StaticWaitPagel Static Memory Page Mode Read Delay 1 A070 0234 Static WaitWrl Static Memory Write Delay 1 A070 0238 StaticWaitTurnl Static Memory Turn Round Delay 1 231 MEMORY CONTROLLER Address Register Description A070 0240 StaticConfig2 Static Memory Configuration Register 2 A070 0244 StaticWaitWen2 Static Memory Write Enable Delay 2 A070 0248 StaticWaitOen2 Static Memory Output Enable Delay 2 A070 024C StaticWaitRd2 Static Memory Read Delay 2 A070 0250 StaticWaitPage2 Static Memory Page Mode Read Delay 2 A070 0254 StaticWaitWr2 Static Memory Write Delay 2 A070 0258 StaticWaitTurn2 Static Memory Turn Round Delay 2 A070 0260 StaticConfig3 Static Memory Configuration Register 3 A070 0264 StaticWaitWen3 Static Memory Write Enable Delay 3 A070 0268 StaticWaitOen3 Static Memory Output Enable Delay 3 A070 026C StaticWaitRd3 Static memory Read Delay 3 A070 0270 StaticWaitPage3 Static Memory Page Mode Read Delay 3 A070 0274 StaticWaitWr3 Static Memory Write Delay 3 A070 0278 StaticWaitTurn3 Static Memory Turn Round Delay 3 Reset values Reset values will be noted in the description column of each register table rather than as a separate column Control register A
337. iguration bits AUTOZ CLRCNT and STEN The counters support a clear on read capability that is enabled when AUTOZ is set to 1 The combined transmit and receive statistics counters are incremented for each good or bad frame transmitted and received that falls within the specified frame length limits of the counter for example TR127 counts 65 127 byte frames The frame length excludes framing bits and includes the FCS checksum bytes All counters are 18 bits with this bit configuration D31 18 R Reserved D17 00 R W Reset 0x00000 Count R W Address Register Transmit and receive counters 060 0680 TR64 Transmit amp receive 64 Byte frame counter R W A060_0684 TR127 Transmit amp receive 65 to 127 Byte frame counter R W A060 0688 TR255 Transmit amp receive 128 to 255 Byte frame counter R W A060 068C TRS11 Transmit amp receive 256 to 511 Byte frame counter R W A060 0690 TRIK Transmit amp receive 512 to 1023 Byte frame counter R W 303 ETHERNET COMMUNICATION MODULE Address Register Transmit and receive counters R W 060 0694 TRMAX Transmit amp receive 1024 to 1518 Byte frame counter R W A060 0698 TRMGV Transmit amp receive 1519 to 1522 Byte good VLAN frame R W count Receive statistics counters address Address Register Receive counters R W 060 069 RBYT Receive byte counter R W A060 06A0 RPKT Receive packet counter R W A060 06A4
338. imer 0 4 Control 2 1 0 0 0 nns 164 Timer 5 Control register 2 22 mene 166 Timer 6 9 Control registers sess memes 168 Timer 6 9 High register Sereen ertt td ere 170 Timer 6 9 LOW redglsters ssecun stes rere atr cxt ae ien eaten bere 171 Timer 6 9 High and Low Step registers csse 172 Timer 6 9 Reload Step 2 4 172 Timer 0 9 Reload Count and Compare register 173 Timer 0 9 Read and Capture 5 174 Interrupt Vector Address Register Level 31 0 175 Int Interrupt Config Configuration 31 0 175 Individual register mapping 2 2 mn 175 ISADDR register ri E T Ven Ax AR VI 176 Interrupt Status 2 2 2 meme enn 177 Interrupt Status encre ter ed c daten P oda 178 Software Watchdog Configuration 178 Software Watchdog Timber concen esto RR RR TR ERR TU UR 179 Clock Configuration register sess 180 Module Reset register sss eme
339. in the list Module TX Interrupt Configuration register Addresses 9000 0020 9000 8020 9001 0020 9001 8020 9002 0020 9002 8020 9003 0020 The TX Interrupt Configuration register allows system software to configure the interrupt from the I O hub module transmit channel Register 3 D 272 A 2 A 20 9 17 1 TXIHFS reo TX RE vote ISTAT LSTA PSTAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 www digiembedded com 381 I O MODULE Module Direct Mode TX Data FIFO Register bit assignment Bit s Access Mnemonic Reset Description 31 28 TXTHRS OxF TX FIFO threshold An interrupt is generated when the FIFO level drops below this level D27 N A Reserved N A N A D26 R W TXFUFIE 0x0 Enable the TXFUFIP interrupt D25 R W TXFSRIE 0x0 Enable the TXFSRIP interrupt D24 R W TXNCIE 0x0 Enable the NCIP interrupt D23 R W TXECIE 0x0 Enable the ECIP interrupt D22 R W TXNRIE 0x0 Enable the NRIP interrupt D21 R W TXCAIE 0x0 Enable the CAIP interrupt D20 N A Reserved N A N A D19 R WSTAT 0 0 Debug field indicating the W bit is set in the current buffer descriptor D18 R ISTAT 0x0 Debug field indicating the I bit is set in the current buffer descriptor 017 R LSTAT 0x0 Debug field indicating the L bit is set in the current buffer descriptor D16 R FSTAT 0 0 Debug field indicating the F bit
340. ing the transfer the DMA controller updates this field with the actual number of bytes that were moved This is useful for debugging error conditions or determining the number of bytes transferred before the DONE signal was asserted The destination buffer length indicates the number of bytes to be written to the destination This field should be identical to the source buffer length for all modes with the exception of CCM when the authentication code is being generated or a key is being expanded The description address pointer field identifies the starting location of the source data s destination that is to where the source data needs to be moved The destination address must be word aligned Bits Used for Values 2 0 Encryption mode select 000 CBC 001 CFB 010 OFB 011 CTR 100 ECB 101 CCM 111 Key expand mode which allows a key to be expanded by the hardware key expander and written back to system memory 3 Encryption decryption select 0 Encryption Decryption 357 AES DATA ENCRYPTION DECRYPTION MODULE AES op code WRAP W bit Interrupt I bit Last L bit Full F bit Bits Used for Values 5 41 Key size 00 128 bits 01 192bits 10 256 bits 6 Additional authentication data 0 No additional data mode only 1 Additional data used 9 7 L par CCM mode only N A 10 Reserved N A 13 11 M par CCM mode only N A 15 14 Reserved N A Indicates the contents of the dat
341. interrupt is generated if enabled If configured for a 32 bit timer bits 31 16 timer reload D15 00 R W Rel 15 0 0x0 Timer Reload Bits 15 00 Count register This value is loaded into the Timer register after the timer 15 enable and after the terminal count has been reached if the reload enable bit is set Timer 0 9 Read and Capture register Addresses A090 0050 0054 0058 005C 0060 0064 0068 006C 0070 0074 The Timer 0 to 9 Read and Capture register reads the current state of each timer and capture register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Cap Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 15 0 Register bit assignment Bits Access Mnemonic Reset Description D31 16 Cap Read 0 0 Timer Capture register or Timer Read Bits 31 16 register Reads the capture value of each timer An interrupt 18 generated a capture event if enabled If configured as a 32 bit timer then bits 31 16 ofthe current state of each timer D15 00 R W Read 15 0 0x0 Timer Read Bits 15 00 register Reads bits 15 00 of the current state of each timer 174 Hardware Reference NS9215 SYSTEM CONTROL MODULE Interrupt Vector Address Register Level 31 0 Interrupt Vector Address Register Level 31 0 Addresses A090 00 4 level 0 00C8 00 0000 0004 0008 00 00 0 00 4 00 8 00 00 0 00F4 8 00 0100 0104 0108 010 0110
342. ion D31 00 R W Scr Mem 0 CPU scratch pad memory www digiembedded com 333 ETHERNET COMMUNICATION MODULE Sample hash table code 000000000000 000000000000 0 00 0 00 0 0 00 0 0 00 00 0 00 00 0 0 60 00 00000000000000000 This sample C code describes how to calculate hash table entries based on 6 byte Ethernet destination addresses and a hash table consisting of two 32 bit registers HT1 and HT2 contains locations 31 0 of the hash table HT2 contains locations 63 32 of the hash table The pointer to the hash table is bits 28 23 of the Ethernet destination address CRC The polynomial is the same as that used for the Ethernet FCS G x 32 26 23 22 16 12 11 10 8 7 5 4 2 1 static ETH ADDRESS _ _ list of MCA addresses static INT16 mca count of MCA addresses Function void eth load mca table void Description This routine loads the MCA table It generates a hash table for the MCA addresses currently registered and then loads this table into the registers HT1 and HT2 Parameters Return Values m none static vold eth load mca table void WORD322 has table 2 create hash table for MAC address eth make hash table hash table 334 Hardware Reference NS9215 www digiembedded com ETHERNE
343. ion The ARM instruction set allows a program to achieve maximum performance with set the minimum number of instructions The majority of instructions are executed in a single cycle Thumb The Thumb instruction set is simpler than the ARM instruction set and offers instruction set increased code density for code that does not require maximum performance Code can switch between ARM and Thumb instruction sets on any procedure call 82 Hardware Reference NS9215 Java instruction set WORKING WITH THE CPU System control processor CP15 registers In J ava state the processor core executes a majority of J ava bytecodes naturally Bytecodes are decoded in two states compared to a single decode stage when in ARM Thumb mode See azelle J ava on page 104 for more information about J ava System control processor CP15 registers ARM926EJ S system addresses Address manipulation example Accessing CP15 registers www digiembedded com The system control processor CP15 registers configure and control most of the options in the ARM926E S processor Access the CP15 registers using only the MRC and MCR instructions in a privileged mode the instructions are provided in the explanation of each applicable register Using other instructions or MRC and MCR in unprivileged mode results in an UNDEFINED instruction exception The ARM926E S has three distinct types of addresses m the ARM926EJ S domain Virtual address
344. isters for the low speed peripheral modules it supports The DMA direct mode and interrupt control register formats are the same for these modules The base address for the registers is 0x9000 0000 Write buffering in the MMU must be disabled for all registers in the 1 Hub address space from address 0x9000 0000 to Ox9FFF Register address maps are shown for each low speed peripheral module 368 Hardware Reference NS9215 3 March 2008 A register address map UART B register address map www digiembedded com I O HUB MODULE Control and status register address maps Note Registers 9000 0000 9000 7FFF and registers 9000 8000 9000 FFFF are reserved Register Offset Description 31 00 0 9001 0000 A Interrupt and FIFO Status 0x9001 0004 UART A DMA RX Control 0x9001 0008 UART A DMA RX Buffer Descriptor Pointer 0x9001 000C UART A DMA RX Interrupt Configuration register 0x9001 0010 UART A Direct Mode RX Status FIFO 0x9001 0014 UART A Direct Mode RX Data DIDO 0x9001 0018 UART A DMA TX Control 0x9001 001C UART A DMA TX Buffer Descriptor Pointer 0x9001 0020 UART A DMA TX Interrupt Configuration register 0 9001 0024 Reserved 0x9001 0028 UART A Direct Mode TX Data FIFO 0x9001 002C UART A Direct Mode TX Data Last FIFO 0x9001 0030 0x9001 OFFF Reserved 0x9001 1000 0x9001 7FFF UART A CSR Space Register Offset Des
345. ive entries Tiny page descriptors must be repeated in each consecutive entry Second level descriptor bit assignments Description 31 16 31 12 31 10 Form the corresponding bits of the physical address 15 12 eis 9 6 SHOULD BE ZERO 11 4 11 4 5 4 Access permission bits See Domain access control on page 121 and Fault checking sequence on page 122 for information about interpreting the access permission bits 3 2 3 2 3 2 Indicate whether the area of memory mapped by this page 15 treated as write back cachable write through cachable noncached buffered and noncached nonbuffered 1 0 1 0 1 0 Indicate the page size and validity and are interpreted as shown in First level descriptor bit assignments Interpreting first level descriptor bits 1 0 on page 111 Second level The two least significant bits of the second level descriptor indicate the descriptor descriptor least type as shown in this table significant bits Description 00 Invalid Generates a page translation fault 01 Indicates that this is 64 KB page 10 Small page Indicates that this is a 4 KB page 11 Indicates that this is a 1 KB page Note Tiny pages do not support subpage permissions and therefore have only one set of access permission bits www digiembedded com 115 WORKING WITH THE CPU MemoryManagement Unit MMU Translation sequenc
346. k D01 R W Not used 0 Always write 0 to this bit D00 R W HINT 0 0 Disable the HDLC interrupt Enable the HDLC interrupt HDLC Control Register 2 000000000000 00000000000 000000000000 0 0 00000 00 0 Address 9002 9114 HDLC Control Register 2 configures the HDLC transmitter and receiver www digiembedded com 429 SERIAL CONTROL MODULE HDLC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CMODE Not used MODE MODE MODE Register bit assignment Bits Access Mnemonic Reset Description D31 08 R Not used 0 Write this field to 0 D07 05 R W CMODE 0 Coding mode 000 NRZ data encoding for receiver and transmitter 010 RZI data encoding for receiver and transmitter 100 Biphase Level Manchester data encoding for receiver and transmitter 110 Biphase Space data encoding for receiver and transmitter 111 Biphase Mark data encoding for receiver and transmitter D04 R W HMODE 0 HDLC mode 0 Normal HDLC data encoding Enable coding 1 4 bit cell IRDA compliant This mode can be used only with internal clock and NRZ data encoding D03 R W IMODE 0 Transmit idle mode 0 Transmit flags while in idle mode 1 Transmit all 1s while in idle mode D02 R W UMODE 0 Underrun mode 0 Transmit flag on underrun 1 Transmit abort on underrun D01 R
347. ket and will have the offset to the next buffer descriptor that will be used RXAOFF can be used to determine where the RX_RD logic will put the next packet www digiembedded com 323 ETHERNET COMMUNICATION MODULE RX B Buffer Descriptor Pointer Offset register RX B Buffer Descriptor Pointer Offset register Address A060 0A2C Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reserved RXBOFF Register bit assignment Bits Access Mnemonic Reset Description D31 11 N A Reserved N A N A D10 00 R RXBOFF 0x000 Contains an 11 bit byte offset from the start of the pool ring The offset is updated at the end of the RX packet and will have the offset to the next buffer descriptor that will be used RXBOFF can be used to determine where the RX RD logic will put the next packet RX C Buffer Descriptor Pointer Offset register Address A060 0A30 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RXCOFF 324 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE RX D Buffer Descriptor Pointer Offset register Register bit assignment Bits Access Mnemonic Reset Description D31 11 N A Reserved N A N A D10 00 R RXCOFF 0x000 Contains an 11 bit byte offset from the start of the pool C ring The offset is updated at the end of the RX packet and will have the offset to
348. l remains in the ERROR state until the CE bit in the DMA Control register is cleared and then set again The DMA channel then uses the buffer descriptor as set in the index control field D29 D28 R W R W RXNRIP RXCAIP 0x0 0x0 Buffer not ready interrupt pending RX Set when he DMA channel finds a buffer descriptor with the F bit not set The DMA channel remains in the ERROR state until the CE bit is set in the DMA Control register is cleared and then set again Channel abort interrupt pending RX Set when the DMA channel finds the channel abort CA bit set The DMA controller closes the current buffer descriptor and remains in the IDLS state until the CA bit is cleared and the CE bit is set D27 www digiembedded com R W RXPCIP 0 0 Premature completion interrupt pending Set when a buffer descriptor 15 closed by the peripheral instead of by reaching the buffer length The DMA channel continues processing buffer descriptors 373 I O MODULE Module Interrupt FIFO Status register Bit s Access Mnemonic Reset Description D26 R W RXFOFIP 0x0 RX FIFO overflow interrupt pending Set when the RX FIFO finds an overflow condition D25 R W RXFSRIP 0x0 RX FIFO service request interrupt pending RX Set when the RX FIFO level rises above the receive FIFO threshold in the RX Interrupt Configuration register D24 R W TXNCIP 0x0 Normal completion inte
349. l signal SDRAM SDRAM SDRAM signal signal signal addr 21 BAO BAO BAO BAO addr 22 BAI BAI BAI BAI 10 10 A10 AP A10 AP A10 AP data 31 16 D 15 0 D 15 0 D 15 0 D 15 0 A12 used only in 2 x 16M x 8 configurations Registers Register map configuration registers must be accessed as 32 bit words and as single accesses only Bursting is not allowed Address Register Description A070 0000 Control register Control register A070 0004 Status register Status register A070 0008 Config register Configuration register A070 0020 DynamicControl Dynamic Memory Control register A070 0024 DynamicRefresh Dynamic Memory Refresh Timer A070 0028 DynamicReadConfig Dynamic Memory Read Configuration register A070 0030 DynamictRP Dynamic Memory Precharge Command Period tgp A070 0034 DynamictRAS Dynamic Memory Active to Precharge Command Period 070 0038 DynamictSREX Dynamic Memory Self Refresh Exit Time A070 003C DynamictAPR Dynamic Memory Last Data Out to Active Time 070 0040 DynamictDAL Dynamic Memory Data in to Active Command Time or TApw 230 Hardware Reference NS9215 www digiembedded com MEMORY CONTROLLER Registers Address Register Description A070 0044 DynamictWR Dynamic Memory Write Recovery Time
350. l two memory must be invoked using some form of fully blocking operation to ensure that the end of the operation can be determined using software It is 134 Hardware Reference NS9215 Sample sequences www digiembedded com WORKING WITH THE CPU Noncachable instruction fetches recommended that either a nonbuffered store STR or a noncached load LDR be used to trigger external synchronization 4 Invalidate the cache The ICache must be invalidated to remove any stale copies of instructions that are no longer valid If the ICache is not being used or the modified regions are not in cachable areas of memory this step might not be required 5 Flush the prefetch buffer To ensure consistency the prefetch buffer should be flushed before self modifying code is executed see Self modifying code on page 133 These sequences correspond to steps 1 4 in IMB operation clean loop MRC p15 0 r15 c7 c10 3 clean entire dcache using test and clean BNE clean loop MRC p15 0 r0 c7 c10 4 drain write buffer STR nonbuffered store to signal L2 world to synchronize MCR p15 0 r0 c7 0 invalidate icache This next sequence illustrates an IMB sequence used after modifying a single instruction for example setting a software breakpoint with no external synchronization required STR store that modifies instruction at address p15 0 ry c7 c10 1 clean dcache sin
351. last master Bus parking must be maintained if other masters are waiting for SPLIT transfers to complete www digiembedded com 139 SYSTEM CONTROL MODULE SPLIT transfers Arbiter configuration example m the bus is granted to a default master and continues to be in the IDLE state longer than a specified period of time an AHB bus arbiter timeout is generated An AHB bus arbiter timeout can be configured to interrupt the CPU or to reset the chip A SPLIT transfer occurs when a slave is not ready to perform the transfer The slave splits or masks its master taking away the master s bus ownership and allowing other masters to perform transactions until the slave has the appropriate resources to perform its master s transaction The bus arbiter supports SPLIT transfers When a SPLIT response is issued by a slave the current master is masked for further bus requesting until a corresponding hsplit 15 0 Signal is issued by the slave indicating that the slave is ready to complete the transfer The arbiter uses the x 15 0 signals to unmask the corresponding master and treats the master as the highest priority requester for the immediate next round of arbitration The master eventually is granted access to the bus to try the transfer again Note The arbiter automatically blocks bus requests with addresses directed at a SPLITting slave until that SPLIT transaction is completed This example shows how to configure
352. ld in the DMA Control register for each channel An external peripheral initiates a DMA transfer by asserting the appropriate REQ signal Software must have set up the required buffer descriptors as well as the DMA Control register for each channel including setting the CE field to 1 before the REQ signal can be asserted 339 EXTERNAL buffer descriptor DMA buffer descriptor diagram Source address pointer Buffer length Destination address pointer All DMA channels use a buffer descriptor When a DMA channel is activated it reads the DMA buffer descriptor that the Buffer Descriptor Pointer register points to A buffer descriptor is always fetched using AHB transaction to maximize AHB bus bandwidth When the current descriptor is retired the next descriptor is accessed from a circular buffer Each DMA buffer requires four 32 bit words to describe a transfer Multiple buffer descriptors are located in circular buffers of 4096 bytes The DMA channel s buffer descriptor pointer provides the first buffer descriptor address Subsequent buffer descriptors are found adjacent to the first descriptor The final buffer descriptor is defined with its W bit set When the DMA channel finds the W bit the channel wraps around to the first descriptor Each DMA channel can address a maximum of 256 buffer descriptors Important channel configured for more than the maximum number of buffer
353. lignment faults If alignment fault checking is enabled the A bit in the R1 Control register is set see R1 Control register beginning on page 88 the MMU generates an alignment fault on any data word access if the address is not word aligned or on any halfword access if the address is not halfword aligned irrespective of whether the MMU is enabled An alignment fault is not generated on any instruction fetch or byte access www digiembedded com 123 Translation faults Domain faults Permission faults WORKING WITH THE CPU Note f an access generates an alignment fault the access sequence aborts without reference to other permission checks There are two types of translation fault section and page A section translation fault is generated if the level one descriptor is marked as invalid This happens if bits 1 0 of the descriptor are both O A page translation fault is generated if the level one descriptor is marked as invalid This happens if bits 1 0 of the descriptor are both O There are two types of domain faults section and page Section The level one descriptor holdsthe four bit domain field which selects one of the 16 two bit domains in the Domain Access Control register The two bits of the specified domain are then checked for access permissions as described in Interpreting access permission bits on page 121 The domain is checked when the level one descriptor is returned Page The level one de
354. lly is found in SDRAM datasheets as tgrc or tge 243 MEMORY CONTROLLER Dynamic Memory Exit Self refresh register Note The Dynamic Memory Auto Refresh Period register is used for all four dynamic memory chip selects The worst case value for all chip selects must be programmed Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Reserved RFC Register bit assignment Bits Access Mnemonic Description D31 05 N A Reserved N A do not modify D04 00 R W RFC Auto refresh period and auto refresh to active command period 0x0 0x1E n clock cycles where the delay is in out cycles Ox1F 32 clock cycles reset value on reset n Dynamic Memory Exit Self refresh register Address A070 0050 The Dynamic Memory Exit Self refresh register allows you to program the exit self refresh to active command time tysn It is recommended that this register be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode This value normally is found in SDRAM datasheets as tycp Note The Dynamic Memory Exit Self refresh register is used for all four dynamic memory chip selects The worst case value for all the chip selects must be programmed 244 Hardware Reference NS9215 Register MEMORY CONTROLLER Dynamic Memory Active Bank A to Active Bank
355. lo 24 IO data 8 DCD UART D 1 CAN TXD O gpio 24 5 34 gpio 25 Hardware Reference NS9215 IO data 9 CTS UARTD reset done dup gpio 25 5 F4 gpio 26 T O 4 PINOUT 265 General purpose I O GPIO Description data 10 DSR UART D PIC 1 GEN IO 0J I O gpio 26 F3 gpio 27 IO data 11 RXD UART D PIC 1 GEN IO 1 I O gpio 27 G5 gpio 28 IO N data 12 RIUARTD PIC 1 GEN IO 2 I O gpio 28 G4 gpio 29 T O N data 13 RTS RS485 Control UART D PIC 1 GEN IO 3 I O gpio 29 G3 gpio 30 T O N data 14 TXC DTR UART D Reserved gpio 30 H4 gpio 31 IO data 15 TXDUARTD Reserved gpio 31 A12 gpio 32 IO Ethernet MII MDC 0 GEN IO 0j I O dup Reserved gpio 32 12 gpio 33 IO Ethernet MII TXC PIC 0 GEN IO 1 I O dup Reserved gpio 33 14 gpio 34 IO Ethernet RXC 0 GEN IO 2 I O dup Reserved gpio 34 D11 gpio 35 www digiembedded com Ethernet MDIO 0 GEN IO 3 I O dup Reserved gpio 35 35 265 Description D17 gpio 36 U 2 Ethernet RX DV 0 GEN IO 4 I O dup Re
356. lt 0x0000 0000 Address A060 0A70 D31 16 R Default 0x0000 0000 D15 00 R W Default 0x0000 0000 Address A060 0474 D31 16 R Default 0x0000 0000 D15 00 R W Default 0x0000 0000 328 Hardware Reference NS9215 MFILTL6 MFILTL7 Reserved read as 0 MFILTHO Reserved read as 0 MFILTHI Reserved read as 0 MFILTH2 Reserved read as 0 MFILTH3 Reserved read as 0 MFILTH4 Reserved read as 0 MFILTHS Multicast High Address Filter Register 6 Multicast High Address Filter Register 7 ETHERNET COMMUNICATION MODULE Multicast Address Mask registers Address A060 0478 D31 16 R Default 0x0000 0000 Reserved read as 0 D15 00 R W Default 0x0000 0000 MFILTH6 Address A060 0 7 D31 16 R Default 0x0000 0000 Reserved read as 0 D15 00 R W Default 0x0000 0000 MFILTH7 Multicast Address Mask registers Multicast Low Address Mask Register 0 Multicast Low Address Mask Register 1 Multicast Low Address Mask Register 2 Multicast Low Address Mask Register 3 www digiembedded com Each of the eight entries in the multicast address filter logic has individual mask registers that extend the filtering range of each entry The multicast address mask for each entry is split between two registers Each entry has a register that contains the lower 32 bits of the multicast mask and a separate register that contains the upper 16 bits of the mask Bits are set to
357. lt Address and Fault Status registers on page 119 The MMU also retains status about faults generated by instruction fetches in the Instruction Fault Status register An access violation for a given memory access inhibits any corresponding external access to the AHB interface with an abort returned to the CPU core On a data abort the MMU places an encoded four bit value the fault status along with the four bit encoded domain number in the Data Fault Status register Similarly on a prefetch abort the MMU places an encoded four bit value along with the four bit encoded domain number in the Instruction Fault Status register In addition the MVA associated with the data abort is latched into the Fault Address 119 WORKING WITH THE CPU MMU faults and CPU aborts Priority encoding table Fault Address register FAR FAR values for multi word transfers register If an access violation simultaneously generates more than one source of abort the aborts are encoded in the priority shown in the priority encoding table The Fault Address register is not updated by faults caused by instruction prefetches Priority Source Size Status Domain Highest Alignment 0b00x1 Invalid External abort on transmission First level 0b1100 Invalid Second level 0b1110 Valid Translation Section page 0b0101 Invalid 0b0111 Valid Domain Section page 0b1001 Valid 0b1011 Valid Permission Section page 0b1101 Valid 0b111
358. m Forwrite transfers the appropriate data mask 3 0 byte lane signals are asserted low and direct the data to the addressed bytes m For read transfers all data mask 3 0 signals are deasserted high enabling the external bus to be defined for at least the width of the accessed memory addr 22 2 cs n st oe n A 20 0 A 20 0 A 20 0 A 20 0 CE n CE n OE data 3 WE data mask 2 n data mask 1 WE n data mask 0 WE n data 31 24 10 7 0 data 23 16 10 7 0 data 15 8 10 7 0 data 7 0 10 7 0 32 bit bank consisting of four 8 bit devices addr 21 1 cs n st oe A 20 0 A 20 0 addr 20 0 A 20 0 CE n 5 _ _ _ st oe n OE n data mask 3 4 WE data mask 2 4 WE n data mask 3 WEn data 31 24 10 7 0 data 23 16 4 10 7 0 data 31 24 10 7 0 16 bit bank consisting of two 8 bit devices 8 bit bank consisting of one 8 bit device 222 Hardware Reference NS9215 MEMORY CONTROLLER Address connectivity Memory banks For memory banks constructed from 16 or 32 bit memory devices it is important constructed from that the byte lane select PB bit is set to 1 within the respective memory bank 16 32 bit control register This asserts all data mask 3 0
359. mal or reset memory map On power on reset chip select 1 is mirrored to both chip select 0 and chip select 1 chip select 4 memory areas Clearing the M bit allows chip select 0 and chip select 4 memory to be accessed D00 R W MCEN Memory controller enable 0 Disabled Enabled reset value on reset n Disabling the memory controller reduces power consumption When the memory controller is disabled the memory is not refreshed The memory controller is enabled by setting the enable bit or by power on reset If you modify this bit be sure the memory controller is in idle state If you modify the E bit be aware of these conditions m Theexternal memory cannot be accessed in low power or disabled state If a memory access is performed in either of these states an error response is generated m The memory controller AHB programming port be accessed normally m The memory controller registers can be programmed in low power and or disabled state www digiembedded com 233 MEMORY CONTROLLER Status register Address A070 0004 The Status register provides memory controller status information Register Register bit assignment 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SA WBS BUSY Bits Access Mnemonic Description D31 03 N A Reserved N A do not modify D02 R SA Self refresh acknowledge SREFACK 0 Normal mode 1 Selfrefresh m
360. mally completes an access when it finds a rising edge on ns ta strb For a burst access the peripheral must toggle ns ta strb for each access it wants to complete early The peripheral is not required to assert ns ta strb for each access in the burst for example the peripheral requires the programmed access for the start of a four access burst followed by three early completion accesses each signalled by the assertion ns ta strb Using the ns ta strb signal is valid only when the EW bit is enabled Be aware m Using extremely long transfer times might mean that SDRAM devices are not refreshed correctly m Very slow transfers can degrade system performance as the external memory interface is tied up for long periods of time This has detrimental effects on 208 Hardware Reference NS9215 Memory mapped peripherals MEMORY CONTROLLER Static memory initialization time critical services such as interrupt latency and low latency devices for example video controllers Some systems use external peripherals that can be accessed using the static memory interface Because of the way many of these peripherals function the read and write transfers to them must not be buffered The buffer must therefore be disabled Static memory initialization Access sequencing and memory width Wait state generation www digiembedded com Static memory must be initialized as required after poweron reset reset n by programming the rele
361. mory to SRAM that can then be accessed at address 0x00000000 More boot initialization or application code is executed The system is set up as Chip select 1 is connected to the boot flash device Chip select 4 is connected to the SDRAM to be remapped to 0x00000000 after boot This is the boot sequence 1 At power on the reset chip select 1 is mirrored into chip select 4 and chip select 0 206 Hardware Reference NS9215 MEMORY CONTROLLER Static memory controller When the power on reset reset n goes inactive the processor starts booting from 0x00000000 in memory The software programs the optimum delay values in flash memory so the boot code can run at full speed The code branches to chip select 1 so the code can continue executing from the non remapped memory location The appropriate values are programmed into the memory controller to configure chip select 4 and the memory device is initialized The address mirroring is disabled by clearing the address mirror M field in the Control register The ARM reset and interrupt vectors are copied from flash memory to SDRAM that can then be accessed at address 0x00000000 More boot initialization or application code is executed Static memory controller www digiembedded com This table shows configurations for the static memory controller with different types of memory devices See StaticMemory Configuration 0 3 registers on page 251 for more informa
362. moved from the active state to the idle state The transmitter moves from the active state to the idle state when the transmit FIFO is empty and the transmitter is not actively shifting out data D00 R WITC RX IDLE 0 Receive idle Indicates that the receiver has moved from the active state to the idle state The receiver moves from the active state to the idle state when a start bit has not been received after the previous stop bit HDLC Data Register 1 Address 9002_9100 HDLC Data Register 1 reads data from the receive buffer and load data in the transmit buffer This register is for debug purposes only Register 15 14 13 1 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HDATA Register bit assignment Bits Access Mnemonic Reset Description D31 08 N A Reserved 0 N A D07 00 R W HDATA 0 Read Returns the contents of the receive buffer Write Loads the transmit buffer with a byte of data HDLC Data Register 2 Address 9002 9104 HDLC Data Register 2 writes the last byte of data of a frame after which the CRC and closing flag are transmitted This register is for debug purposes only www digiembedded com 427 SERIAL CONTROL MODULE HDLC Register 31 30 29 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register bit assignment Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 00 R W HDATA 0 Read Returns the contents of the receive buffer Write Used for the last data byte in a frame after which
363. n D31 R W ENABLE 0 Enables and resets the transmit byte counter 0 Transmit byte count disabled and reset 1 Transmit byte enabled D30 24 N A Reserved N A N A D23 00 R TXCOUNT 0 This counter is incremented after bytes are transmitted 404 Hardware Reference NS9215 SERIAL CONTROL MODULE UART UART Receive Buffer UART Receive Buffer Address 9001 1100 9001 9100 9002 1100 9002 9100 DLAB 0 Read UART Receive Buffer is used for diagnostic purposes only Register 15 14 13 2 1 10 9 8 7 6 5 4 3 2 1 0 Reserved RBUFF Register bit assignment Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 00 R RBUFF 0 Receiver data bits UART Transmit Buffer Address 9001 1100 9001 9100 9002 1100 9002 9100 DLAB 0 Write UART Transmit Buffer is used for diagnostic purposes only Register www digiembedded com 405 Register bit SERIAL CONTROL MODULE UART assignment Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 00 0 Transmitter data bits UART Baud Rate Divisor LSB Register Register bit assignment Address 9001 1100 9001 9100 9002 1100 9002 9100 DLAB 1 UART Baud Rate Divisor sets bits 07 00 of the baud rate generator divisor Bits Access Mnemonic Reset Description D31 08 N A Reserved N A N A D07 00 R W BRDL 0 1 Bits 07 00 of the baud rate generator divisor UART Baud Rate Divisor MSB Address 9001 1104
364. n Round Delay 0 3 registers on page 258 StaticWaitTurn n 209 MEMORY CONTROLLER m Static Memory Extended Wait register on page 247 StaticExtendedWait The number of cycles in which an AMBA transfer completes is controlled by two additional factors m X Access width m External memory width Programmable Each bank of the memory controller has a programmable enable for the extended enable wait EW The WAITRD wait state field in the Static Memory Read Delay register can be programmed to select from 1 32 wait states for read memory accesses to SRAM and ROM or the initial read access to page mode devices The WAITWR wait state field in the Static Memory Write Delay register can be programmed to select from 1 32 wait states for access to SRAM The Static Memory Page Mode Read Delay register can be programmed to select from 1 32 wait states for page mode accesses Static memory read control n There are three types of static memory read controls m Output enable programmable delay ROM SRAM and flash m Asynchronous page mode read Output enable The delay between the assertion of the chip select and the output enable is programmable programmable from 0 to 15 cycles using the wait output enable bits WAITOEN in delay the Static Memory Output Enable Delay registers The delay is used to reduce power consumption for memories that cannot provide valid output data immediately after the chip select has been asserted
365. n by software Note The value of the gpio a 3 signal is reflected in this field When programmed this register reflects the last value written into the register You must flush all data in the memory controller before switching between little endian and big endian modes Dynamic Memory Control register Address A070 0020 The Dynamic Memory Control register controls dynamic memory operation The control bits can be changed during normal operation Register 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reva Reserved SDRAMinit Rsva Reserved used used used www digiembedded com 235 MEMORY CONTROLLER Dynamic Memory Refresh Timer register Register bit assignment Bits Access Mnemonic Description D31 15 N A Reserved N A do not modify 14 R W nRP Sync Flash reset power down signal dy_pwr_n 0 dy_pwr_n signal low reset value on reset 1 Setdy pwr nsignal high D13 R W Not used Always write to 0 D12 09 N A Reserved N A do not modify D08 07 R W SDRAMInit SDRAM initialization 00 Issue SDRAM NORMAL operation command reset value on reset_n 01 Issue SDRAM MODE command 10 Issue SDRAM PALL precharge all command 11 Issue SDRAM NOP no operation command D06 N A Reserved N A do not modify D05 R W Not used Must write 0 D04 03 N A Res
366. n neni 182 Miscellaneous System Configuration and Status register 184 PEE Configuration register isi durer eei rte 186 PEL frequency 186 Active Interrupt Level ID Status 187 Power 2 nnn 187 AHB Bus Activity 5 21 meme emen nns 190 System Memory Chip Select 0 Dynamic Memory Base and Mask registers 190 System Memory Chip Select 1 Dynamic Memory Base and Mask registers 191 System Memory Chip Select 2 Dynamic Memory Base and Mask registers 192 System Memory Chip Select 3 Dynamic Memory Base and Mask registers 193 System Memory Chip Select 0 Static Memory Base and Mask registers 194 System Memory Chip Select 1 Static Memory Base and Mask registers 195 System Memory Chip Select 2 Static Memory Base and Mask registers 196 System Memory Chip Select 3 Static Memory Base and Mask registers 197 Gen ID register UEM 198 External Interrupt 0 3 Control 2 2 2 22 2 4122 2 199 RTC Module Control lt 4444 200 Chapter 5 Memory Controller
367. nditionally aborted In the latter two cases the access permission attributes are ignored There are 16 domains which are configured using R3 Domain Access Control register see R3 Domain Access Control register on page 91 The TLB caches translated entries During CPU memory accesses the TLB provides the protection information to the access control logic When the TLB contains a translated entry for the modified virtual address MVA the access control logic determines whether m Access is permitted and an off chip access is required the MMU outputs the appropriate physical address corresponding to the MVA m Access is permitted and an off chip access is not required the cache services the access m Access is not permitted the MMU signals the CPU core to abort If the TLB misses it does not contain an entry for the MVA the translation table walk hardware is invoked to retrieve the translation information from a translation table in physical memory When retrieved the translation information is written into the TLB possible overwriting an existing value At reset the MMU is turned off no address mapping occurs and all regions are marked as noncachable and nonbufferable 106 Hardware Reference NS9215 MMU program accessible registers Address translation www digiembedded com WORKING WITH THE CPU MemoryManagement Unit MMU This table shows the CP15 registers that are used in conjunction with p
368. ne 3 0 N WTRD 1 WOEN 0 m Ifthe PB field is set to 1 all four byte lane signals will go low for 32 bit 16 bit and 8 bit read cycles m PB field is set to 0 the byte lane signal will always be high www digiembedded com 495 data lt 31 0 gt addr lt 27 0 gt st_cs_n lt 3 0 gt byte lane 3 0 496 TIMING Static RAM asynchronous page mode read WTPGz1 out Note 1 Note 2 Note 2 Note 2 oe a WTPG 1 m WTRD 2 m f the PB field is set to 1 all four byte lane signals will go low for 32 bit m 16 bit and 8 bit read cycles asynchronous page mode will read 16 bytes a page cycle A 32 bit bus will do four 32 bit reads as shown 3 2 2 2 A 16 bit bus will do eight 16 bit reads 3 2 2 2 3 2 2 2 per page cycle and an 8 bit bus will do sixteen 8 bit reads 3 2 2 2 3 2 2 2 3 2 2 2 3 2 2 2 per page cycle 3 2 2 2 is the example used here but the WTRD and WTPG fields can set them differently Notes 1 The length of the first cycle in the page is determined by the WTRD field 2 The length of the 2nd 3rd and 4th cycles is determined by the WTPG field This is the starting address The least significant two bits will always be 00 4 The least significant two bits in the second cycle will always be 01 5 The least significant two bits in the third cycle will always be 10 6 The least significant two bits in the fo
369. ne and subtract two regions shown in the figure The DPLL makes no adjustment if the bit cell boundaries are lined up within one count of the divide by sixteen counter The regions that adjust the count by two allow the DPLL to synchronize faster to the data stream when starting up With biphase level encoding there is a guaranteed clock transition at the center of every bit cell and optional data transitions at the bit cell boundaries The DPLL Hardware Reference NS9215 Biphase Mark and Biphase Space encoding IRDA compliant encode SERIAL CONTROL MODULE HDLC Normal mode operation only uses the clock transitions to track the bit cell boundaries by ignoring all transitions occurring outside a window around the center of the bit cell The window is half a bit cell wide Because the clock transitions are guaranteed the DPLL requires that they always be present If no transition is found in the window around the center of the bit cell for two successive bit cells the DPLL is not in lock and immediately enters search mode Search mode presumes that the next transition seen is a clock transition and immediately synchronizes to this transition No clock output is provided to the receiver during the search operation Biphase mark and biphase space encoding are identical per the DPLL and are similar to biphase level The primary difference is the clock placement and data transitions With these encodings the clock transitions
370. neral purpose 1 70 2 2 0 402000 2 24 4 22 31 System CLOCK 43 System clock drawing 44 RTC clock and battery backup drawing 45 SE CIN EET 45 SECUN Pm 47 TAG TSC T 48 R A 49 POR battery backed tas 50 Power and aad ETUR RE RUNE dua RR UAR E ERE NER de 51 Chapter 2 I O Control 53 System memory bus I O control sss 53 Control and 5 2 9494 el di 53 Register address REEE 53 GPIO Configuration registers sss mene 55 GPIO configuration 2 2 4 teed 55 GPIO Configuration Register 30 56 GPIO Configuration Register 1 8 56 GPIO Configuration Register 32 57 GPIO Configuration Register 33 57 GPIO Configuration Register 4 58 GPIO Configuration Register 35
371. next buffer descriptor A DMA channel asserts the NRIP field buffer not ready interrupt pending in the DMA Status register and returns to the idle state upon fetching a buffer descriptor with the F bit in the incorrect state A DMA channel always closes the current descriptor and moves on to the next descriptor when a DMA transfer is terminated by the assertion of the DONE signal 341 EXTERNAL Peripheral read access Peripheral DMA read access Determining the width of PDEN Equation variables The diagrams in this section describe how the DMA engine performs read accesses of an external peripheral m The CLK signal shown is for reference and its frequency is equal to the speed grade of the part m The peripheral data enable signal PDEN is an AND function of the active states of the st cs n n and st oe n signals timing can be adjusted by the memory controller s Static Memory Configuration 0 3 registers which control st cs n n and st oe n Note The PDEN signal is asserted for all accesses on the selected peripheral chip select If configuration registers or memory also need to be accessed you can use high level address bits and an external gate to disable the PDEN signal You can also place the peripheral and configuration registers on separate chip selects to avoid the need for the external gate DMA read accesses from an external peripheral are treated as asynchronous operatio
372. ngle unified TLB used for both data accesses and instruction fetches The TLB is divided into two parts a eight entry fully associative part used exclusively for holding locked down TLB entries m set associative part for all other entries Whether an entry is placed in the set associative part or lockdown part of the TLB depends on the state of the TLB Lockdown register when the entry is written into the TLB see R10 TLB Lockdown register on page 101 When an entry has been written into the lockdown part of the TLB it can be removed only by being overwritten explicitly or when the MVA matches the locked down entry by an MVA based TLB invalidate operation The structure of the set associative part of the TLB does not form part of the programmer s model for the ARM926E S processor No assumptions must be made 126 Hardware Reference NS9215 WORKING WITH THE CPU Caches and write buffer about the structure replacement algorithm or persistence of entries in the set associative part specifically wm Any entry written into the set associative part of the can be removed at any time The set associative part of the TLB must be considered as a temporary cache of translation page table information No reliance must be placed on an entry residing or not residing in the set associative TLB unless that entry already exists in the lockdown TLB The set associative part of the TLB can contain entries that are define
373. ngth 8 0 1 010 00 128 Mb 16 8 4 banks row length 12 column length 10 0 1 010 01 128 Mb 8 16 4 banks row length 12 column length 9 0 1 011 00 256 Mb 32 8 4 banks row length 13 column 1 10 0 1 011 01 256 Mb 16 16 4 banks row length 13 column length 9 0 1 100 00 512 Mb 64 8 4 banks row length 13 column 1 11 1 100 01 512 Mb 32 16 4 banks row length 13 column length 10 32 bit extended bus high performance address mapping row bank column 1 0 000 00 16 Mb 2 8 2 banks row length 11 column length 9 1 0 000 01 16 Mb 1Mx16 2 banks row length 11 column length 8 1 0 001 00 64 Mb 8 8 4 banks row length 12 column length 9 1 0 001 01 64 Mb 4 16 4 banks row length 12 column length 8 1 0 001 10 64 Mb 2Mx32 4 banks row length 11 column length 8 1 0 010 00 128 Mb 16 8 4 banks row length 12 column length 10 1 0 010 01 128 Mb 8Mx16 4 banks row length 12 column length 9 1 0 010 10 128 Mb 4 32 4 banks row length 12 column length 8 1 0 011 00 256 Mb 32 8 4 banks row length 13 column length 10 www digiembedded com 249 MEMORY CONTROLLER Dynamic Memory RAS and CAS Delay 0 3 registers Chip select and memory devices Chip select and memory devices Examples 14 12 11 9 8 7 Description 1 0 011 01 256 Mb 16Mx16 4 banks row length 13 column length 9 1 0 011 10 2
374. nic Reset Description D31 11 N A Reserved N A N A D10 00 R GENID HW strap General Purpose ID register addr 19 09 External Interrupt 0 3 Control register Register Register bit assignment www digiembedded com Addresses A090 0214 0218 021 0220 The External Interrupt Control registers control the behavior of external interrupts 0 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved STS CLR PLTY LVEDG Bits Access Mnemonic Reset Description D31 04 N A Reserved N A N A D03 R STS N A Status Status of the external signal before edge detect or level conversion D02 R W CLR 0x0 Clear Write a 1 then a 0 to this bit to clear the interrupt generated by the edge detect circuit 199 SYSTEM CONTROL MODULE Bits Access Mnemonic Reset Description D01 R W PLTY 0x0 Polarity 0 Iflevel sensitive the input source is active high If edge sensitive generate an interrupt on the rising edge of the external interrupt 1 Iflevel sensitive the input source is active low The level is inverted before sending to the interrupt controller If edge sensitive generate an interrupt on the falling edge of the external interrupt D00 R W LVEDG 0x0 Level edge 0 Level sensitive interrupt 1 Edge sensitive interrupt RTC Module Control register Address A090 0224 The RTC Module Control register controls the RTC module Register 31 30 29 28
375. nning on page 105 7 B bit www digiembedded com Endianness 0 Little endian operation 1 Bigendian operation Set to the value of BIGENDINIT on reset 89 WORKING WITH THE CPU Bits Name Function 6 3 N A Reserved SHOULD BE ONE 2 C bit DCache enable disable 0 Cache disabled Cache enabled 1 A bit Alignment fault enable disable 0 Data address alignment fault checking disabled 1 Data address alignment fault checking enabled 0 M bit MMU enable disable 0 Disabled Enabled ICache and The M C I and RR bits directly affect ICache and DCache behavior as shown DCache behavior Cache MMU Behavior ICache disabled Enabled or disabled All instruction fetches are from external memory AHB ICache enabled Disabled All instruction fetches are cachable with no protection checking All addresses are flat mapped that is VA MVA PA ICache enabled Enabled Instruction fetches are cachable or noncachable and protection checks are performed All addresses are remapped from VA to PA depending on the MMU page table entry that is VA translated to MVA MVA remapped to PA DCache disabled Enabled or disabled All data accesses are to external memory AHB DCache enabled Disabled All data accesses are noncachable nonbufferable All addresses are flat mapped that is VA MVA PA DCache enabled Enabled All data accesses are cachable or noncachable and protection checks are performed All addres
376. ns by the chip It is critical that the necessary width of the PDEN assertion be computed correctly and programmed in the static memory controllers Use this equation to compute total access time Total access time T Ty T 10 0 Variable Definition Ta Peripheral read access time Tp Total board propagation delay including buffers Te One AHB CLK cycle period 342 Hardware Reference NS9215 EXTERNAL Peripheral write access Peripheral DMA single read access CLK st cs n n st oe n ADDR Address Valid PDEN DQ lt DATA VALID gt Peripheral burst read access CLK st cs n n st oe n ADDR ADDRO ADDR1 PDEN DQ lt DATAO gt DATA1 gt Peripheral write access EEEE The diagrams in this section describe how the engine performs write accesses of an external p
377. nsmit buffer not ready F bit not set in transmit buffer descriptor when read from TX TX buffer descriptor RAM for a frame in progress Transmit complete Frame transmission complete TX TXERR Frame not transmitted successfully TX TXIDLE TX_WR logic in idle mode because there are no frames to send TX Status bits The status bits for all interrupts are available in the Ethernet Interrupt Status register and the associated enables are available in the Ethernet Interrupt Enable register Each interrupt status bit is cleared by writing a 1 to it Resets This table provides a summary of all resets used for the Ethernet front end and MAC as well as the modules the resets control Bit field Register Active Default Modules reset state state ERX Ethernet General Control 0 0 RX_RD RX WR Register 1 ETX Ethernet General Control 0 0 TX RD TX WR Register 1 MAC HRST Ethernet General Control 1 0 MAC STAT RX WR TX RD Register 1 programmable registers in Station Address Logic SRST MACI 1 1 except programmable registers Station Address Logic except programmable registers RX WR TX RD RPERFUN MACI 1 0 1 RPEMCST MACI 1 0 MAC PEMCS TX side 274 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Multicast address filtering Bit field Register Active Default Modules reset state state RPETFUN 1 0 MAC TX logic MIIM MII Management 1 0 MIIM logic Config
378. nt scanning read operations are in progress D00 R BUSY 0 interface BUSY with read write operation When set to 1 indicates that the MII Management module currently is performing an MII Management read or write cycle This bit returns to 0 when the operation is complete Station Address registers Registers 300 Addresses A060 0440 0444 0448 The 48 bit station address is loaded into Station Address Register 1 Station Address Register 2 and Station Address Register 3 for use by the station address logic see Station address logic SAL on page 264 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OCTET1 OCTET2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Station Address Filter register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 6 Register bit assignments for Bits Access Mnemonic Reset Description all three registers Station Address Register 1 D31 16 N A Reserved N A N A D15 08 R W OCTETI 0 Station address octet 1 stad 7 0 D07 00 R W OCTET2 0 Station address octet 2 stad 15 8 Station Address Register 2 D31 16 N A Reserved N A N A D15 08 R W OCTET3 0 Sta
379. nters an available buffer that is large enough to hold the entire receive frame The pointers to the first buffer descriptor in each of the four pools are found in the related Buffer Descriptor Pointer register RXAPTR RXBPTR RXCPTR RXDPTR Pointers to subsequent buffer descriptors are generated by adding an offset of 0 10 from this pointer for each additional buffer used 31 30 29 28 16 15 0 OFFSET 0 Source Address OFFSET 4 Buffer Length 11 lower bits used OFFSET 8 Destination Address not used OFFSET C 1 Reserved Status The current buffer descriptor for each pool is kept in local registers The current buffer descriptor registers are initialized to the buffer descriptors pointed to by the Buffer Descriptor Pointer registers by setting the ERXINIT enable initialization of buffer descriptor registers bit in Ethernet General Control Register 1 The initialization process is complete when RXINIT RX initialization complete is set in the Ethernet General Status register At the end of a frame the next buffer descriptor for the ring just used is read from system memory and stored in the registers internal to the RX RD logic 268 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Transmit packet processor Receive buffer descriptor field Field Description W WRAP bit which when set tells the RX RD logic that this is the last buffer
380. ntrol information The external DMA module has two of these registers Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CE CA Sw DW SB DB SINCN SNCN POL RST 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 www digiembedded com 347 EXTERNAL Register bit assignment Bit s D31 Access R W Mnemonic CE Reset 0 Description Channel enable Enables and disables DMA operations as required After a DMA channel has entered the IDLE state for any reason this field must be written to a 1 to initiate further DMA transfers D30 D29 CA CG Channel abort When set causes the current DMA operation to complete and closes the buffer Channel go When set causes the DMA channel to exit the IDLE state and begin a DMA transfer The CE field 31 must also be set which allows software to initiate a memory to memory transfers The dma_req and dma_done signals are not used during memory to memory transfers D28 27 D26 25 D24 23 348 Hardware Reference NS9215 R W SW DW SB Source width Defines the data bus width of the device attached to the source address specified in the buffer descriptor 00 8bit 01 16 10 32bit 11 Reserved Destination width Defines the data bus width of the device attached to the destination address specified in the buffer descriptor 00 8bit 01 16bit 10 32bit 11 Reserved Source burst Defines the A
381. o 0 SPI EN dup K17 gpio 1 U IO 2 CTSUART A Ext Int 0 0 GEN IO 1 I O gpio 1 Reserved 7 gpio 2 U IO 2 DSRUARTA Ext Int 1 0 GEN IO 2 I O gpio 2 Reserved 6 gpio 3 U IO 2 RXDUARTA Ext DMA Pden Ch 0 0 GEN IO 3 I O gpio 3 SPI RXD dup H17 gpio 4 U VO 2 RIUART A Ext Int Ch 2 Ext Timer Event In Ch 6 gpio 4 SPI CLK dup RTS RS485 Control UART A Ext Int Ch 3 Ext Timer Event Out Ch 6 gpio 5 SPI CLK dup gplo 5 U 2 H14 gpio 6 U VO 2 TXC DTR UART A Ext DMA Req Ch 0 Ext Timer Event In Ch 7 gpio 6 PIC DBG DATA OUT O G14 gpio 7 U yo 2 TXD UART A Ext Timer Event In Ch 8 Ext Timer Event Out Ch 7 gpio 7 SPI TXD dup _ 32 Hardware Reference NS9215 265 General purpose I O GPIO Description G17 gpio 8 T O DCD UART Ext DMA Done Ch 1 Ext Timer Event Out Ch 8 gpio 8 SPI EN dup G15 G16 gpio 9 gpio 10 T O CTS UART C SCL Ext Int Ch 0 dup gpio 9 PIC DBG DATA IN I DSRUART C QDC 1 Ext Int Ch 1 dup gpio 10 PIC DBG CLK O F13 gpio 11 T O RXD UART C Ext DMA Pden Ch 1 Ext Int Ch 2 dup gpio 11 SPI RXD boot F17 F15 gpio 12 gpio 13 T O IO RXC RIUARTC
382. o clear the interrupt D09 06 www digiembedded com R W TCS 0x0 Timer clock select 0000 AHB clock x 2 0001 AHB clock 0010 AHB clock 2 0011 AHB clock 4 0100 AHB clock 8 0101 AHB clock 16 0110 AHB clock 32 0111 AHB clock 64 1000 AHB clock 128 1111 External event 165 SYSTEM CONTROL MODULE Bits Access Mnemonic Reset Description D05 04 R W Timer mode 0x0 Timer mode 00 Internal timer or external event 01 External low level gated timer 10 External high level gated timer 11 Concatenate the lower timer Note When either external gated option is selected the time clock select bits deter mine the frequency D03 R W Int Sel 0 0 Interrupt select 0 Interrupt disable 1 Generate IRQ D02 R W Up Down 0 0 Up Down select 0 Up counter 1 Down counter R W Bit timer 0x0 32 or 16 bit timer 0 16 bit timer 32 bit timer D00 R W Rel Enbl 0x0 Reload enable 0 Halt at terminal count The timer must be disabled then enabled to reload the timer when the terminal count is reached Reload and resume count at terminal count Timer 5 Control register Address A090 01A4 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 2 166 Hardware Reference NS9215 Register bit assignment Bits D31 19 Access N A Mnemonic Reserved Reset N A SYSTEM CONTROL MODULE Timer 5 Control register Description N
383. ode reset value on reset Indicates the memory controller operating mode Write buffer status 0 Write buffers empty reset value on reset n Write buffers contain data D01 R WBS Enables the memory controller to enter low power mode or disabled mode clearly D00 R BUSY Busy 0 Memory controller is idle 1 Memory controller is busy performing memory transactions commands or auto refresh cycles or is in self refresh mode reset value on reset n Ensures that the memory controller enters the low power or disabled state cleanly by determining whether the memory controller is busy Configuration register Address A070 0008 The Configuration register configures memory controller operation It is recommended that this register be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode 234 Hardware Reference NS9215 MEMORY CONTROLLER Dynamic Memory Control register Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved END Register bit assignment Bits Access Mnemonic Description D31 01 N A Reserved N A do not modify DOO R W END Endian mode 0 Little endian mode 1 Big endian mode The value of the endian bit on power on reset reset_n is determined by the gpio a 3 signal This value can be overridde
384. ol errors D12 D11 RXBR RXMC 0 0 0 0 Receive broadcast frame Set when the frame has a valid broadcast address Receive multicast frame Set when the frame has a valid multicast address D10 N A Reserved N A N A D09 RXDR 0x0 Receive frame has dribble bits Set when an additional 1 7 bits are received after the end of the frame D08 07 www digiembedded com N A Reserved N A N A 287 MAC Configuration Register 1 ETHERNET COMMUNICATION MODULE MAC Configuration Register 1 Bits Access Mnemonic Reset Description D06 R RXSHT 0x0 Receive frame is too short Set when the frame s length is less than 64 bytes Short frames are accepted only when the ERXSHT bit is set to 1 in Ethernet General Control Register 1 D05 00 N A Reserved N A N A Register Register bit assignment 288 Address A060 0400 MAC Configuration Register 1 provides bits that control functionality within the Ethernet MAC block 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SRST bes Reserved ba EN CE Reserved rd Not used RXEN Bits Access Mnemonic Reset Description D31 16 N A Reserved N A N A D15 R W SRST 1 Soft reset Set this bit to 1 to reset the RX_WR TX_RD MAC except host interface SAL except host interface D14 R W Not used 0
385. om 7 Access Instr ctlofs ssec sese ra dun 103 Register Tormat ete e ru etat buat ia 103 Performing a fast context switch 103 Context ID isis ite ERES Re RR 104 c 104 Register TORMAL 104 104 R15 Test and debug register 104 azellle AVA te oa eraat eto EH IRI ERA 104 a S E E E A A 105 MemoryManagement Unit 020200 02 105 MMU Features reos proram v PRO 105 Access permissions and 5 106 ICE DEJES 106 MMU program accessible registers 107 Address translation esci ice e Pe ENTRE tenes 107 Translation table base 108 TIB register format iret ette 108 Table Walk 109 First level 109 First level fetch concatenation and address
386. on Encoding HDLC Clock NFZ Data NRZI Digital phase locked loop DPLL operation Encoding In the HDLC module the internal clock comes from the output of the dedicated divider The divider output is divided by 16 to form the transmit clock and is fed to the DPLL to form the receive clock The DPLL basically is a divide by 16 counter that uses the transition timings on the receive data stream to adjust its count The DPLL adjusts the count so the DPLL output is placed properly in the bit cells to sample the receive data Transitions To work properly the receive data stream requires transitions NRZ data encoding does not guarantee transitions in all cases for example a long string of zeroes but the other data encodings do NRZI guarantees transitions because of inserted zeroes The Biphase encodings all have at least one transition per bit cell 418 Hardware Reference NS9215 SERIAL CONTROL MODULE HDLC DPLL operation Adjustment ranges and output clocks DPLL tracked bit The DPLL counter normally counts by 16 but if a transition occurs earlier or later than cell boundaries expected the count is modified during the next count cycle m f the transition occurs earlier than expected the bit cell boundaries are early with respect to the DPLL tracked cell boundaries and the count is shortened by either one or two counts m the transition occurs later than expected
387. on This interrupt should always be enabled during normal operation D22 R W NRIE 0 Enable NRIP interrupt generation D21 R W CAIE 0 Enable CAIP interrupt generation This interrupt should always be enabled during normal operation D20 R W PCIE 0 Enable PCIP interrupt generation D19 R WRAP 0 Read only debug field that indicates the last descriptor in the descriptor list D18 R DONE 0 Read only debug field that indicates the status of the DONE signal 017 R LAST 0 Read only debug field that indicates the last buffer descriptor in the current data frame D16 R FULL 0 Read only debug field that indicates the status of the F bit from the current DMA buffer descriptor D15 00 R BLEN 0 Read only debug field that indicates the current byte transfer count DMA Peripheral Chip Select register Address A080_000C A080_001C The DMA Peripheral Chip Select register contains the DMA channel peripheral chip select definition The external DMA module has two of these registers Register 31 15 30 9 2 260 2 14 13 12 11 10 Not used 23 22 21 20 19 18 17 16 352 Hardware Reference NS9215 EXTERNAL DMA Peripheral Chip Select register Register bit assignment Bit s Access Mnemonic Definition D31 02 R W Not used 0 This field must always be set to 0 D01 00 R W SEL 0 Chip select Defines which of the four memory interface chip select signals nmpmcstcsout n is connected to the external peri
388. on fetching is enabled at reset Note t is recommended that you use ICache rather than noncachable code when possible Noncachable code previously has been used for operating system boot loaders and for preventing cache pollution ICache however can be enabled without the MMU being enabled and cache pollution can be controlled using the cache lockdown register A four word buffer holds speculatively fetched instructions Only sequential instructions are fetched speculatively if the 926 S issues nonsequential instruction fetch the contents of the buffer are discarded flushed In situations on which the contents of the prefetch buffer might become invalid during a sequence of sequential instruction fetches by the processor core for example turning the MMU on or off or turning on the ICache the prefetch buffer also is flushed This avoids the necessity of performing an explicit Instruction Memory Barrier IMB operation except when self modifying code is used Because the prefetch buffer is flushed when the ARM926E S core issues a nonsequential instruction fetch branch instruction or equivalent can be used to implement the required IMB behavior as shown in this code sequence LDMIA RO R1 R5 load code sequence into R1 R5 ADR RO self_mod_code STMIA RO R1 R5 store code sequence nonbuffered region B self mod code branch to modified code self mod code This IMB application applies only to the ARM926E
389. on table and loading entries into the TLB The number of stages in the hardware table walking and permission checking process is one or two depending on whether the address is marked as a section mapped access or a page mapped access There are three sizes of page mapped accesses and one size of section mapped access Page mapped accesses are for large pages small pages and tiny pages The translation process always begins in the same way with a level one fetch A section mapped access requires only a level one fetch but a page mapped access requires an additional level two fetch The hardware translation process is initiated when the TLB does not contain a translation for the requested MVA R2 Translation Table Base TTB register points to the base address of a table in physical memory that contains section or page descriptors or both The 14 low order bits 13 0 of the TTB register are UNPREDICTABLE a read and the table must reside on 16 KB boundary 31 14 13 0 Translation table base The translation table has up to 4096 x 32 bit entries each describing 1 MB of virtual memory This allows up to 4 GB of virtual memory to be addressed 108 Hardware Reference NS9215 Table walk process First level fetch www digiembedded com TTB base Indexed by modified virtual address bits 31 20 Translation table 4096 entries Section base Section Indexed by modified vi
390. on when a receive character match occurs against the Receive Match Register 2 D09 R W MATCHI 0 Enable character match1 Enables interrupt generation when a receive character match occurs against the Receive Match Register 1 D08 R W MATCHO 0 Enable character match Enables interrupt generation when a receive character match occurs against the Receive Match Register 0 D07 R W DSR 0 Enable data set ready Hardware Reference NS9215 Enables interrupt generation whenever a state change occurs on input signal DSR Bits Access Mnemonic Reset D06 R W DCD 0 SERIAL CONTROL MODULE UART Interrupt Status register Description Enable data carrier Enables interrupt generation whenever a stat change occurs on input signal DCD D05 R W CTS 0 Enable clear to send Enables interrupt generation whenever a state change occurs on input signal CTS D04 R W RI 0 Enable ring indicator Enables interrupt generation whenever a state change occurs on input signal RI D03 R W TBC 0 D02 R W RBC 0 Enable transmit buffer close Enables interrupt generation when the UART transmit FIFO indicates to the UART transmitter that a byte corresponds to a buffer close event Enable receive buffer close Enables interrupt generation whenever a buffer close event 15 passed from the UART receiver to the receive FIFO These are the UART receive buffer close events Receive character match Receive character gap timeout Receive line b
391. ond interrupt Disable second interrupt D00 W Hsec Dis 0x0 Hundredth of a second interrupt disable 0 Enable hundredth second interrupt Disable hundredth second interrupt www digiembedded com 469 REAL TIME CLOCK MODULE Interrupt Enable Status register Interrupt Enable Status register Address 9006 0028 The Interrupt Enable Status register determines which interrupt sources are enabled and which interrupt sources are disabled Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R d Alrm Mnth Date Hour Min Sec Hsec Stat Stat Stat Stat Stat Stat Stat Register bit assignment Access Mnemonic Description D31 07 N A Reserved N A N A D06 R Alrm Stat Alarm interrupt status 0 Interrupt enabled 1 Interrupt disabled D05 R Mnth Stat Month interrupt status 0 Interrupt enabled 1 Interrupt disabled D04 R Date Stat Date interrupt status 0 Interrupt enabled 1 Interrupt disabled D03 R Hour Stat Hour interrupt status 0 Interrupt enabled 1 Interrupt disabled D02 R Min Stat Minute interrupt status 0 Interrupt enabled 1 Interrupt disabled 01 R Sec Stat Second interrupt status 0 Interrupt enabled 1 Interrupt disabled D00 R Hsec Stat Hundredth of a second interrupt status 0 Interrupt enabled 1 Interrupt disabled 470 Hardware Reference NS9215 REAL TIME CLOCK MODULE General Status regis
392. onfigurable wait states 500 Slow peripheral acknowledge 501 Slow peripheral acknowledge read 502 Slow peripheral acknowledge write 502 Ethernet timilig 503 Ethernet MII timing iiic nra 503 CEU 504 SIMA 505 SPI master mode 0 and 1 2 byte 4 507 SPI master mode2 and 3 2 byte 507 SPI slave mode 0 and 1 2 byte transfer 508 SPI slave mode 2 and 3 2 byte transfer 508 Reset and hardware strapping 509 TIMING 510 Hardware Reference NS9215 www digiembedded com xa 511 System PLL reference 0 511 Chapter 17 513 PACKAQ 513 Processor Dimensions 1 42 2 2 2 2 nnn nnn
393. op p15 0 r15 c7 c10 3 test and clean BNE tc loop The test clean and invalidate DCache instruction is the same asthe test and clean DCache instruction except that when the entire cache has been cleaned it is invalidated Use the following loop to test clean and invalidate the entire DCache tci loop 5 0 r15 c7 c14 3 test clean and invalidate BNE tci loop R8 TLB Operations register TLB operations TLB operation instructions www digiembedded com Register R8 is a write only register that controls the translation lookaside buffer TLB There is a single TLB used to hold entries for both data and instructions The TLB is divided into two parts m Set associative m Fully associative The fully associative part also referred to as the lockdown part of the TLB stores entries to be locked down Entries held in the lockdown part of the register are preserved during an invalidate TLB operation Entries can be removed from the lockdown TLB using an invalidate TLB single entry operation There are six TLB operations the function to be performed is selected by the opcode 2 CRm fields in the MCR instruction used to write register R8 Writing other opcode 2 CRm values is UNPREDICTABLE Reading from this register is UNPREDICTABLE Use these instruction to perform TLB operations Operation Instruction Invalidate set associative TLB SBZ MCR 5 0 Rd c8 c7 0 Invalidat
394. orta sess cese o et eren eni ad a ac EX cea 91 R3 Domain Access Control register sss nn 91 Register 2 Rr 91 Access permissions and instructions 91 Pusat ted dul 92 R5 Fa lt Status regiSter S 92 ACCESS 92 Register nenne eme enn nnns 92 Register DIES PEUT 92 Status and domain 1 05 00080 93 R6 Fault Address registers cnet ur EORR 93 ba den er 93 R7 Cache Operations 4 94 Write 94 Cache FUNCTIONS D 94 Cache operation mmm 95 Modified virtual address format MVA 96 Set Way format eur 96 Set Way example wi 224414 china eg E RENE ERE 96 Test and clean DCache 96 Test clean and invalidate DCache 97 Re TLB Operations register entere a Ea 97 Operations
395. orts when the excessive deferral limit is reached that is 6071 nibble times in 100 Mbps mode or 24 287 bit times in 10 Mbps mode 1 Enables the MAC to defer to carrier indefinitely as per the 802 3u standard D13 R W Not used 0 Always write to 0 D12 R W NOBO 0 No backoff When this bit is set to 1 the MAC immediately retransmits following a collision rather than using the binary exponential backoff algorithm as specified in the 802 3u standard D11 10 N A Reserved N A N A 289 ETHERNET COMMUNICATION MODULE MAC Configuration Register 2 Bits D09 Access R W Mnemonic LONGP Reset 0 Definition Long preamble enforcement 0 Allows any length preamble as defined in the 802 30 standard 1 The MAC allows only receive frames that contain preamble fields less than 12 bytes in length R W PUREP Pure preamble enforcement 0 No preamble checking is performed 1 certifies the content of the preamble to ensure that it contains 0x55 and is error free D07 AUTOP Auto detect pad enable When set to 1 this bit causes the MAC to detect automatically the type of transmit frame either tagged or untagged by comparing the two octets following the source address with the 0x8100 VLAN protect ID and pad accordingly Note This bit is ignored if PADEN is set to 0 See PAD operation table for transmit frames below D06 VLANP VLAN pad ena
396. ory chip select 15 routed to 55 000 dy 0 001 dy es 1 010 dy cs 2 default 011 dy cs 3 100 st cs 0 101 st cs 1 110 st cs 2 111 st cs 3 D20 18 R W CS6 0 7 Controls which system memory chip select is routed to CS6 000 dy cs 0 001 dy es 1 010 dy 2 011 dy 3 100 st cs 0 101 st cs 1 110 st cs 2 111 st cs 3 default D23 21 R W CS7 0x3 Controls which system memory chip select is routed to CS7 000 dy_cs 0 001 dy_cs 1 010 dy_cs 2 011 dy cs 3 default 100 st cs 0 101 st cs 1 110 st cs 2 111 st cs 3 D24 R W DHPUDIS 0 0 High data bus pullup control 0 Enable pullup resistors data 31 16 1 Disable pullup resistors on data 31 16 Note Bits 15 00 are output and controlled through GPIO 78 Hardware Reference NS9215 www digiembedded com Bit s D25 Access R W Mnemonic APUDIS Reset 0 0 CONTROL MODULE Memory Bus Configuration register Description Address bus pullup control Applicable only to address associated with hardware strapping 0 Enable pullup resistors 1 Disable pullup resistors Note Bits 27 24 are output and controlled through GPIO D3 1 26 N A Reserved N A N A 79 I O CONTROL MODULE 80 Hardware Reference NS9215 Working with the CPU About the processor E R 3 processor is based the ARM926E S processor The ARM926EJ S processor belongs to the ARM9 family of general purpose microprocessors
397. ounters roll over an associated carry bit is set the Carry 1 CARI or Carry 2 CAR2 registers see General Statistics registers address map beginning on page 310 Any statistics counter overflow can cause the STOVFL bit in the Ethernet Interrupt Status register see page 317 to be set if its associated mask bit is not set in Carry Mask Register 1 or Carry Mask Register 2 265 ETHERNET COMMUNICATION MODULE The counters support a clear on read capability that is enabled when AUTOZ 15 set to 1 the Ethernet General Control Register 2 Ethernet front end module Ethernet front end module EFE Host I F Stat Host I F SAL Host I F System Cfg To Receive Transmit AHB Slave Interface Status Registers From Receive Transmit Packet Processors RX Interrupt TX Interrupt Rx frame Control Registers Receive Packet Processor SAL Accept Reject RX RD RX WR Src Addr Filter Rx FIFO WR et FIFO RD Ctl a gt v E Data FIFO RX RX Status FIFO Master RD Data 8 32 32 entr Interface Transmit Packet Processor Tx Status TX WR TX Buffer Tx Ctl TX Ctl pole WR FIFO RD Ctl 3 am RAM Ctl 64 entries SA and CTL 2 5 TX TX FIFO Tx Data 32 8 256 Bytes 32 T
398. ows the maximum power dissipation for 1 and core CPU Memory clock Power 150MHz 75MHz Total 1 019W Core 0 880W IO 0 139W 75 MHz 75MHz Total 0 828W Core 0 696 IO 0 132W 112MHz 56MHz Total 0 638W Core 0 536W 0 102W 56MHz 56MHz Total 0 499W Core 0 403 0 096W Sleep Mode wake on Ethernet Total 0 073W Core 0 027W 0 046W Sleep Mode wake on External IRQ Total 0 055W Core 0 022W IO 0 033W Main Power Down Battery Draw 3 0V 32uA 1 8V 6uA 480 Hardware Reference NS9215 DC electrical characteristics DC electrical characteristics DC characteristics specify the worst case DC electrical performance of the I O buffers that are guaranteed over the specified temperature range Inputs All electrical inputs are 3 3V interface The processor 1 O are 5 volt tolerant DC electrical inputs are provided below Parameter Condition Vin High level input voltage Min 2 0 LVTTL level Vir Low level input voltage Max 0 8 V LVTTL level High level input current no pulldown Vna Vppa Min Max 10 10 pA Input buffer with pulldown Min Max 10 200 pA Tis Low level input current no pullup Vss 10 10 Input buffer with pullup Min Max 10 200 uA loz High impedance leakage current Vouta 9r Vss Min Max 10 10 pA a SS 0V GND www digiembedded com 481 TIMING Reset e
399. ows this process 1 Readsthe first buffer descriptor as pointed to by the TX buffer descriptor pointer and INDEX www digiembedded com 367 1 MODULE Control and status register address maps 2 Verifies that the data buffer is valid by making sure the F bit is set to 1 3 Reads the first data buffer 16 byte bursts 4 Continues to process the buffer descriptors and data buffers until all data has been transmitted from the buffer descriptor with the L bit set to 1 The DMA controller interrupts the CPU if the I bit is set to a 1 5 Remains in the IDLE state until the channel enable bit is set to a 0 then set to a 1 again Visual example System Memory Buffer Pointer null Buffer Length null 0 1 0 1 0 0 Hub Controller i 18 byte data buffer first buffer in packet Buffer Pointer 0x200 ffer Length 0x012 TXBDP INDEX i i fer Pointer 0x 400 Length 0x064 24 byte data buffer fer 0x300 Lengthz 0x 018 W 0 1 0 L 0 F 1 Pointer 0x500 100 byte data buffer Length 0x 064 W 0 l 1 L 1 F 1 Buffer Pointer null Buffer Length null W 0 l 0 L 0 F 0 100 byte data buffer last buffer in packet Buffer Pointer nu Buffer Length null 1 0 1 0 0 Control and status register address maps The I O Hub provides a series of reg
400. pheral 00 nmpmcstcsout 0 01 nmpmcstcsout 1 10 nmpmcestcsout 2 11 nmpmcestcsout 3 www digiembedded com 353 EXTERNAL DMA Peripheral Chip Select register 354 Hardware Reference NS9215 AES DATA ENCRYPTION DECRYPTION MODULE AES Data Encryption Decryption Module E R 6 The AES data encryption decryption module provides IPSec compatible network security to processor based systems The AES core module implements Rij ndael encoding decoding in compliance with the NIST Advanced Encryption Standard AES Features Processes 32 bits at a time programmable for 128 192 256 bit key lengths Supports ECB CBC OFB CTR and CCM cipher modes Implements hardware key expander to minimize software intervention during the encryption decryption process During encryption and decryption the key expander can produce the expanded key on the fly m Exists behind external DMA channel 1 see Chapter External DMA for information about DMA control registers and programming m Uses the buffer descriptor control field to indicate a memory to memory AES operation www digiembedded com 355 AES DATA ENCRYPTION DECRYPTION MODULE Block diagram From System Memory To System Memory Ch 1 Ext DMA Ch 1 Ext DMA Source Destination Mode and Control IV gt Key Expanded Key Data Out gt Expan
401. pio 48 C13 gpio 49 Ethernet CRS Reserved Reserved gpio 49 gpio 50 U IO Ethernet PHY Int PIC 1 CLK I PIC 1 CLK O gpio 50 E10 gpio 51 DCD UART B dup PIC 0 BUS 1 8 I O PIC 1 BUS 1 8 I O gpio 51 D10 gpio 52 CTS UART B dup PIC 0 BUS I 9 I O PIC 1 BUS I 9 I O gpio 52 C10 gplo 53 DSR UART B dup PIC 0 BUS 1101 0 PIC 1 BUS 1101 0 gpio 53 C9 gplo 54 N RXD UART B dup PIC 0 BUS I 11 I O 1 BUS I 11 I O gpio 54 H5 gpio 55 www digiembedded com WN RI UART B dup PIC 0 BUS 112 0 PIC 1 BUS 1 12 0 gpio 55 37 General purpose I O GPIO J4 gplo 56 IO Description RTS RS485 Control B dup PIC 0 BUS 1 13 I O PIC 1 BUS 1 13 I O gpio 56 gplo 57 IO TXC DTR UART B dup PIC 0 BUS 1 14 O PIC 1 BUS 1 14 O gpio 57 K4 gpio 58 TXD UART B dup PIC 0 BUS 1 15 0 0 PIC 1 BUS gpio 58 gplo 59 IO DCD UART D dup PIC 0 BUS 1 16 I O PIC 1 BUS 1 16 I O gpio 59 R6 gpio 60 I O CTS UART D dup PIC 0 BUS 1 17 I O PIC 1 BUS 1I 17 I O gpio 60 P6 gplo 61 IO DSR UART D dup PIC 0 BUS 1 18 O P
402. plished by the following a Hardware which directly executes 80 of simple ava byte codes 104 Hardware Reference NS9215 DSP WORKING WITH THE CPU DSP m Software emulation within the ARM optimized J VM which addresses the remaining 20 of the ava byte codes The ARM926E S processor core provides enhanced DSP capability Multiply instructions are processed using a single cycle 32x16 implementation There are 32x32 32x16 and 16x16 multiply instructions or Multiply Accumulate MAC and the pipeline allows one multiply to start each cycle Saturating arithmetic improves efficiency by automatically selecting saturating behavior during execution and is used to set limits on signal processing calculations to minimize the effect of noise or signal errors All of these instructions are beneficial for algorithms that implement the following m GSM protocols m FFT m State space servo control MemoryManagement Unit MMU MMU Features www digiembedded com The MMU provides virtual memory features required by systems operating on platforms such as WindowsCE or Linux A single set of two level page tables stored in main memory control the address translation permission checks and memory region attributes for both data and instruction accesses The MMU uses a single unified Translation Lookaside Buffer TLB to cache the information held in the page tables TLB entries can be locked down to ensure that a memory access to a given
403. pret the access permission AP bits and how the interpretation depends on the R and S bits in the R1 Control register see R1 Control register beginning on page 88 121 WORKING WITH THE CPU AP S R Privileged permissions User permissions 00 0 0 No access No access 00 1 0 Read only Read only 00 0 1 Read only Read only 00 1 1 UNPREDICTABLE UNPREDICTABLE 01 x x Read write No access 10 Read write Read only 11 x x Read write Read write Fault checking sequence The sequence the MMU uses to check for access faults is different for sections and pages The next figure shows the sequence for both types of access 122 Hardware Reference NS9215 Section translation fault WORKING WITH THE CPU Fault checking sequence Modified virtual address rae Check address alignment Misaligned au Get first level descriptor Invalid Section Page Get page UN Section No access 00 No access 00 Page ud 19 4864 2 Check domain status Reserved 10 7 ee Section Page Manager 11 v Section permission C Violation b access access Violation p permission fault NA permissions permissions NEUEN fault v Physical address The conditions that generate each of the faults are discussed in the following sections A
404. prevent current or any lower priority interrupts from interrupting again The CPU must not read the ISADDR register for FIQ interrupts The CPU branches to the Interrupt Service Routine ISR and stacks the workspace so the IRQ can be enabled The CPU enables the IRQ interrupts so higher priority interrupts can be serviced The CPU executes the interrupt service routine The CPU clears the source of the current interrupt The CPU disables the IRQ and restores the workspace If IRQ the CPU writes the level value of the interrupt being serviced to the ISADDR register to clear the current interrupt path in the VIC s priority hardware The CPU returns from the interrupt Configurable system attributes System software can configure these system attributes Little endian big endian mode Watchdog timer enable Watchdog timeout generates IRQ FIQ RESET Watchdog timeout interval Enable disable ERROR response for misaligned data access System module clock enables Enable access to internal registers in USER mode PLL configuration Hardware strapping determines the initial powerup PLL see Bootstrap initialization on page 152 After powerup software can change the PLL settings by writing to the PLL Configuration register www digiembedded com 151 SYSTEM CONTROL MODULE BEEN Hund lizanon PLL configuration and control system block diagram X1 SYS_OSC 59 4912 MHz X2 Sys OsC
405. provides the station address logic with a 6 bit CRC value that is the upper six bits of a 32 bit CRC calculation performed on the 48 bit multicast destination address This 6 bit value addresses the 64 bit multicast hash table created in HT1 hash table 1 and HT2 hash table 2 If the current receive frame is a multicast frame and the 6 bit CRC addresses a bit in the hash table that is set to 1 the receive frame will be accepted otherwise the receive frame is rejected HT1 stores enables for the lower 32 CRC addresses HT2 stores enables for the upper 32 CRC addresses Address A060 0504 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HT1 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 HT1 Register bit assignment Bits Access Mnemonic Reset Description D31 00 R W 0 00000000 CRC 31 00 302 Hardware Reference NS9215 HT2 ETHERNET COMMUNICATION MODULE Statistics registers Address A060 0508 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HT2 HT2 Register bit assignment Bits Access Mnemonic Reset Description D31 00 R W HT2 0x00000000 CRC 63 32 Statistics registers Combined transmit and receive statistics counters address map www digiembedded com Address A060 0680 base register The Statistics module has 39 counters and 4 support registers that count and save Ethernet statistics The Ethernet General Control Register 2 contains three Statistics module conf
406. r Address 9001_1108 9001_9108 9002_1108 9002_9108 Read The UART Interrupt Identification register reads the source of the interrupt from the UART This register is for diagnostic purposes only Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Reserved IIR Register bit assignment Bits Access Mnemonic Reset Description D31 04 N A Reserved N A N A D03 00 R Interrupt identification 0110 Receiver line status error 0100 Receive data available 0010 Transmit holding register empty 0000 Modem status 408 Hardware Reference NS9215 SERIAL CONTROL MODULE UART UART FIFO Control register UART FIFO Control register Address 9001 1108 9001 9108 9002 1108 9002 9108 Write The UART FIFO Control register controls the RX and TX 4 byte FIFOs Note that only the FIFOEN bit bit 01 should be set all other bits are for diagnostic purposes only Register Reserved TXCLR A Register bit assignment Bits Access Mnemonic Reset Description D31 03 N A Reserved N A N A D02 TXCLR 0 Clear all bytes in the TX FIFO 0 Normal operation 1 TX FIFO cleared D01 RXCLR 0 Clear all bytes in the RX FIFO 0 Normal operation 1 RX FIFO cleared D00 FIFOEN 0 Enable the TX and RX FIFO 0 RX and TX FIFO disabled 1 RX and TX FIFO enabled UART Line Control register Address 9001 110 9001 910 9002 110 9002 910 The UART Line Control register controls the UART settings
407. r 31 20 19 12 11 10 9 8 Fault Coarse page table base address Domain Coarse page table Section base address AP Domain Section Fine page table base address Domain Fine page table A section descriptor provides the base address of a 1 MB block of memory Page table The page table descriptors provide the base address of a page table that contains descriptors second level descriptors There are two page table sizes m Coarse page tables which 256 entries and split the 1 MB that the table describes into 4 KB blocks m Fine page tables which have 1024 entries and split the 1 MB that the table describes into 1 KB blocks 110 Hardware Reference NS9215 First level descriptor bit assignments Priority encoding of fault status First level descriptor bit assignments Interpreting first level descriptor bits 1 0 Section descriptor Section descriptor format www digiembedded com Bits Section Coarse WORKING WITH THE CPU MemoryManagement Unit MMU Description 31 20 31 10 31 12 Forms the corresponding bits of the physical address 19 12 SHOULD ZERO 11 10 Access permission bits See Access permissions and domains on page 106 and Fault Address and Fault Status registers on page 119 for information about interpreting the access permission bits 9 9 11 9 SHOULD BE ZERO 8 5 8 5 8 5 Domain control bits 4 4 4 Must be 1 3
408. r 0 A060 0A84 MFMSKLI Multicast Low Address Mask Register 1 A060 0A88 MFMSKL2 Multicast Low Address Mask Register 2 A060 0A8C MFMSKL3 Multicast Low Address Mask Register 3 278 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Ethernet General Control Register 1 Address Register Description A060 0A90 MFMSKL4 Multicast Low Address Mask Register 4 A060 0A94 MFMSKLS5 Multicast Low Address Mask Register 5 A060 0A98 MFMSKL6 Multicast Low Address Mask Register 6 A060 0A9C MFMSKL7 Multicast Low Address Mask Register 7 A060 0AA0 5 Multicast High Address Mask Register 0 A060 0AA4 MFMSKHI Multicast High Address Mask Register 1 A060 0AA8 MFMSKH2 Multicast High Address Mask Register 2 A060 0 MFMSKH3 Multicast High Address Mask Register 3 A060 0ABO 5 Multicast High Address Mask Register 4 A060 0 4 MFMSKH5 Multicast High Address Mask Register 5 A060 0AB8 MFMSKH6 Multicast High Address Mask Register 6 A060 0ABC MFMSKH7 Multicast High Address Mask Register 7 A060 0ACO MFILTEN Multicast Address Filter Enable Register A060 1000 TXBD TX Buffer Descriptor RAM 256 locations A060 2000 RXRAM RX FIFO RAM 512 locations Ethernet General Control Register 1 Address A060 0000 Register www digiembedded com 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reser Not Not ERX wed Not used ETX
409. r is full The TX_WR logic clears this bit after emptying a buffer The system software sets this bit as required to signal that the buffer is ready for transmission If the TX_WR logic detects that this bit is not set when the buffer descriptor is read it does one of two things m Ifa frame is not in progress the TX WR logic sets the TXIDLE bit in the Ethernet Interrupt Status register m Ifa frame is in progress the TXBUFNR bit in the Ethernet Interrupt Status register is set In either case the TX_WR logic stops processing frames until TCLER clear transmit logic in Ethernet General Control Register 2 is toggled from low to high TXBUENR is set only for frames that consist of multiple buffer descriptors and contain a descriptor not the first descriptor that does not have the F bit set after frame transmission has begun Buffer length This is a dual use field m When buffer descriptor is read from the TX buffer descriptor RAM buffer length indicates the length of the buffer in bytes The TX WR logic uses this information to identify the end of the buffer For proper operation of the TX WR logic all transmit frames must be at least 34 bytes in length m Whenthe TX WR logic updates the buffer descriptor at the end of the frame it writes the length of the frame in bytes into this field for the last buffer descriptor of the frame If the MAC is configured to add CRC to the frame that is CRCEN in MAC Configu
410. ransmitter to send the character specified in the CHAR field D07 00 All user specified tules such as bit order parity or number of stop bits are enforced Write a 1 to enable this field Hardware clears the field once the character has been transmitted Writing a 1 to this field when it is already a has unpredictable results Note Writing a 1 to this field also clears the FORCE field in the Interrupt Status register D30 R BUSY 0 Read only busy Reading a indicates that the force operation you initiated is in progress D29 08 R Not used 0 Write this field to 0 D07 00 R W CHAR 0 Force character Defines the character that is forced out of the transmitter ARM Wakeup Control register Address 9001 1030 9001 9030 9002 1030 9002 9030 Use the ARM Wakeup Control register to enable the ARM wakeup control logic www digiembedded com 403 Register SERIAL CONTROL MODULE UART 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not used ABLE Register bit assignment Bits Access Mnemonic Reset Description D31 01 R Not used 0 Write this field to 0 0 Enable Write a 1 to this field to enable ARM wakeup control logic Transmit Byte Count Address 9001 1034 9001 9034 9002 1034 9002 9034 Register 3 28 7 20 BH 2 20 19 18 17 16 EN ABE Reseved TXOANT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXOOUNT Register bit assignment Bits Access Mnemonic Reset Descriptio
411. ration Register 2 is set to 1 this field will include the four bytes of CRC This field is set to 0x000 for jumbo frames that are aborted Only the lower 11 bits of this field are valid since the maximum legal frame size for Ethernet is 1522 bytes Transmitting a Setting the EXTDMA enable transmit DMA bit in Ethernet General Control Register frame 1 starts the transfer of transmit frames from the system memory to the TX FIFO The TX WR logic reads the first buffer descriptor in the TX buffer descriptor RAM m Ifthe F bit isset it transfers data from system memory to the TX FIFO using the buffer pointer asthe starting point This process continues until the end of the buffer is reached The address for each subsequent read of the buffer is incremented by 32 bytes that is 0x20 The buffer length field in the buffer descriptor is decremented by this same value each transfer to identify when the end of the buffer is reached m Ifthe L field in the buffer descriptor is 0 the next buffer descriptor in the RAM continues the frame transfer until the L field in the current buffer descriptor is 1 This identifies the current buffer as the last buffer of a transmit frame After the entire frame has been written to the TX FIFO the TX WR logic waits for a signal from the logic indicating that frame transmission has completed at the MAC The TX WR logic updates the buffer length status and F fields of the current buffer descriptor t
412. re 473 ANALOG TO DIGITAL CONVERTER ADC MODULE ADC Control ADC control The ADC control block provides access between the CPU and the ADC module The block ADC clock and control signals are generated in this block The ADC module output can be either DMA d to memory or read directly by the CPU f DMA is enabled ADC output data is written to memory using UART D s receive DMA controller m f more than one channel is enabled word 0 in the DMA buffer will always be from channel 0 followed by the data from the other selected channels m data buffer length must be a word multiple of the number of selected channels For example if three channels are selected the buffer length must be a multiple of three words or 12 bytes ADC DMA procedure EE If using the channel must set up first and enabled before enabling the ADC The procedure below must be followed each time a new DMA is started or if a DMA FIFO overflow is detected The RX FIFO overflow interrupt should be enabled to detect an overflow 1 Configure the ADC Configuration register at address 9003 9000 for DMA opera
413. re translated according to the value contained in the FCSE PID register Address A becomes A FCSE PID x 32 MB it is this modified address that the MMU and caches see Addresses above 32 MB are not modified The FCSE PID is a 7 bit field which allows 128 x 32 MB processes to be mapped If the FCSE PID is 0 there is a flat mapping between the virtual addresses output by the ARM926E S core and the modified virtual addresses used by the caches and MMU The FCSE PID is set to 0 at system reset If the MMU is disabled there is no FCSE address translation FCSE translation is not applied for addresses used for entry based cache or TLB maintenance operations For these operations VA MVA Use these instructions to access the FCSE PID register Function Data ARM instruction Read FCSE PID FCSE PID p15 0 Rd c13 c0 0 Write FCSE PID FCSE PID MCR p15 0 Rd c13 c0 0 This is the format of the FCSE PID register 31 25 24 0 FCSE PID SBZ You can perform a fast context switch by writing to the Process ID register R13 with opcode 2 set to 0 The contents of the caches and the do not have to be flushed after a fast context switch because they still hold address tags The two instructions after the FCSE PID has been written have been fetched with the old FCSE PID as shown in this code example FCSE PID 0 MOV 10 1 SHL 25 Fetched with FCSE PID 0 MCR 15 0 0 13 0 0 Fetched with FCSE PID 0 Al Fetched
414. reak Receive framing error nA Receive parity error D01 R W TX_IDLE 0 Enable transmit idle Enables interrupt generation whenever the transmitter moves from the active state to the idle state This indicates that the transmit FIFO is empty and the transmitter is not actively shifting out data D00 R W RX IDLE 0 Enable receive idle Enables interrupt generation whenever the receiver moves from the active state to the idle state If a start bit is not received after a stop bit the receiver enters the idle state Interrupt Status register Address 9001 1008 9001 9008 9002 1008 9002 9008 The Interrupt Status register provides status about UART events All events are indicated by reading a 1 and are cleared by writing a 1 www digiembedded com 395 SERIAL CONTROL MODULE UART Register 31 29 28 27 24 23 22 21 20 19 18 17 16 Reser FRA BREA wed FORCE OFLOWIPARITY we 15 13 12 11 8 7 6 5 4 3 2 1 0 TX RX BGAP RX CGAP 4 3 0 DSR DCD CIS TBC RBC IDE IDLE Register bit assignment Bits Access Description D31 22 R W Not used Write this field to 0 D21 R WITC Reserved UART interrupt Indicates that the UART has generated an interrupt D20 R WITC FORCE Force complete Indicates that a force character transmission operation has completed D19
415. region never incurs the penalty of a page table walk wm Standard ARM926E S architecture MMU mapping sizes domains and access protection scheme Mapping sizes as follows 1MB for sections 64 for large pages 4KB for small pages 1KB for tiny pages Access permissions for large pages and small pages can be specified separately for each quarter of the page subpage permissions Hardware page table walks 105 WORKING WITH THE CPU MemoryManagement Unit MMU Access permissions and domains Translated entries m Invalidate entire using R8 Operations register see R8 TLB Operations register on page 97 m Invalidate entry selected by using R8 Operations register see R8 TLB Operations register on page 97 m Lockdown of entries using R10 Lockdown register see R10 TLB Lockdown register on page 101 For large and small pages access permissions are defined for each subpage 1 for small pages 16 KB for large pages Sections and tiny pages have a single set of access permissions All regions of memory have an associated domain A domain is the primary access control mechanism for a region of memory It defines the conditions necessary for an access to proceed The domain determines whether m X Access permissions are used to qualify the access m access is unconditionally allowed to proceed m access is unco
416. register and multiplexing logic required to accomplish this task System memory The registers in this section control these system memory 1 configuration options Dus FO conttol System chip select options used to select which chip select is output m Upper address option Control and Status registers The I O control module configuration registers are located at base address 0xA090 2000 Register address map Address Description Access Reset value A090_ 2000 GPIO Configuration Register 0 R W 0x18181818 A090 2004 GPIO Configuration Register 1 R W 0x18181818 A090 2008 GPIO Configuration Register 2 R W 0x18181818 53 CONTROL MODULE BEES Control and Status registers Address Description Access Reset value 090 200 GPIO Configuration Register 3 0 18181810 090 2010 Configuration Register 4 0 00000000 090 2014 Configuration Register 5 0 00000000 090 2018 Configuration Register 6 R W 0x00000000 A090 201C GPIO Configuration Register 7 R W 0x00000000 A090 2020 Configuration Register 8 R W 0x18181818 A090 2024 Configuration Register 9 R W 0x18181818 A090 2028 GPIO Configuration Register 10 R W 0x18181818 A090 202C GPIO Configuration Register 11 R W 0x18181818 A090 2030 GPIO Configuration Register 12 R W 0x18181818 A090 2034 GPIO Configuration Regist
417. register controls the ADC clock generator The source clock is the output of the PLL The maximum ADC clock frequency is 14 MHz and the conversion time is 14 clock cycles This is the formula for the ADC clock ADC clock PLL clock 2 x N 1 Example m PLL clock frequency 299 8272 MHz m Nvalue 10 ADC clock frequency ADC clock 299 8272 MHz 2 10 1 13 6285 MHz Wait states can be added to increase conversion time beyond 14 clock cycles Not used N 5 Access Reset Description D31 16 R W WAIT N A Number of additional clock cycles per conversion cycle D15 10 R W Not used 0 This field must be written to 0 D09 00 R W N 0 ADC clock converter ADC Output Registers 0 7 www digiembedded com Addresses 9003 9008 9003 900 9003_9010 9003 9014 9003 9018 9003 901 9003 9020 9003 9024 The ADC Output registers provide CPU access for the ADC output for each channel 477 ANALOG TO DIGITAL CONVERTER ADC MODULE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Not used 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 i Register bit assignment 5 55 Reset Description D31 12 R W Not used 0 This field must be written to 0 D11 00 R DOUT 0 Provides the output of the ADC for each channel 478 Hardware Reference NS9215 Timing TIMING Electrical characteristics 1 6 chapter provides
418. register values are not seen at the input of any internal flops in the RX CLK domain Use these steps to dynamically write to any of the other Multicast Address Filter registers 1 Clear the enable bit in the MFILTEN register for the address filter you want to change 2 Update the address filter registers for the disable filter 3 Setthe enable bit for the address filter that was just changed If the address filters are changed only when the Rx WR logic is reset or not processing frames as recommended the address filter registers can be updated without using this procedure 276 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Ethernet Control and Status registers Ethernet Control and Status registers Register address filter www digiembedded com configuration registers must be accessed as 32 bit words and as single accesses only Bursting is not allowed Address Register Description A060 0000 Ethernet General Control Register 1 A060 0004 EGCR2 Ethernet General Control Register 2 A060 0008 EGSR Ethernet General Status register A060 000 060 0014 Reserved A060 0018 ETSR Ethernet Transmit Status register A060 001C ERSR Ethernet Receive Status register A060 0400 MAC Configuration Register 1 A060 0404 MAC2 MAC Configuration Register 2 A060 0408 IPGT Back to Back Inter Packet Gap register A
419. ress bus PLL NR 1 28 Hardware Reference NS9215 PINOUT 265 Memory bus interface Pin Signal U D OD Description addr 0 U IO 4 Address bus PLL NR 0 L1 data 31 U 4 Data bus K2 data 30 U IO 4 Data bus data 29 U 4 Data bus data 28 U IO 4 Data bus J2 data 27 U 4 Data bus data 26 U IO 4 Data bus Gl data 25 U IO 4 Data bus J3 data 24 U IO 4 Data bus H2 data 23 U IO 4 Data bus data 22 U 4 Data bus G2 data 21 U 4 Data bus H3 data 20 U IO 4 Data bus 1 data 19 U 4 Data bus F2 data 18 U IO 4 Data bus DI data 17 U IO 4 Data bus E2 data 16 U IO 4 Data bus H4 data 15 gpio 31 U UO 4 Data bus G3 data 14 gpio 30 U 4 Data bus G4 data 13 gpio 29 U 4 Data bus G5 data 12 gpio 28 U 4 Data bus F3 data 11 gpio 27 U IO 4 Data bus F4 data 10 gpio 26 U IO 4 Data bus F5 data 9 gpio 25 U 4 Data bus data 8 gpio 24 U IO 4 Data bus 4 data 7 gpio 23 U 4 Data bus D2 data 6 gp1o 22 U 4 Data bus E3 data 5 gpio 21 U 4 Data bus Bl data 4 gpio 20 U IO 4 Data bus D4 data 3 gpio 19 U 4 Data bus C2 data 2 gpio 18 U IO 4 Data bus B2 data 1 gpio 17 U 4 Data bus D3 data 0 gpio 16 U IO 4 Data bus www digiembedded com 29 265
420. ress is always specified in the second byte 448 Hardware Reference NS9215 2 MASTER SLAVE INTERFACE 2 command interface 2 command interface Locked interrupt driven mode Master module and slave module commands Bus arbitration www digiembedded com The 12 module converts parallel 8 bit data to serial data and serial data to parallel data between the processor and the IC bus using a set of interface registers The primary interface register for transmitting data is the CMD TX DATA REG write only The primary interface register for receiving data is the STATUS RX DATA REG read only 2 operates a locked interrupt driven mode which means that each command issued must wait for an interrupt response before the next command can be issued illustrated in Flow charts beginning on page 457 The first bit of the command 0 or 1 indicates to which module master or slave respectively the command in the CMD field of the CMD TX DATA REG is sent The master module can be sent a master command only the slave module can be sent a slave command only see Master module and slave module commands beginning on page 449 for a list of commands If a command is sent to the master module that module is locked until a command acknowledgement is given Similarly if a command is sent to the slave module the slave module is locked until it receives a command acknowledgement With either module
421. restart is performed on the 2 bus This opens the opportunity to provide a new slave device address in the MAster Address register before the command request The 12 slave high level driver identifies one command s STOP to discontinue a transaction After this command the slave remains inactive until the next start condition on the 12 bus If a slave is accessed by a master it generates 5 RX DATA and S TX DATA interrupts see Master slave interrupt codes on page 455 To distinguish the transactions from each other special S RX DATA IST and S TX DATA IST interrupts are generated for the transmitted byte 456 Hardware Reference NS9215 Flow charts 2 MASTER SLAVE INTERFACE Flow charts Master module normal mode 16 bit www digiembedded com write cmd M READ wait irq read rx status wait irq read rx status write cmd M NOP write optional M ADDR REG host idle write optional M ADDR REG write cmd M WRITE write irq ae b M ARBIT LOST 20 TX DATA REG write cmd M NOP write TX DATA REG wait irq read status write cmd M STOP M TX DATA 3 irq wait irq read status i M_CMD_ACK irq S write cmd M_READ write cmd M_WRITE Notes 9 N m
422. rison of month date hour minute second and hundredth second Each item can be masked allowing an alarm to be generated at a particular time and date on a monthly basis An interrupt can be generated on the alarm event Event detection finds and generates interrupts on rollover conditions including rollovers into a new month date hour minute second or hundredth second 459 REAL TIME CLOCK MODULE configuration and status registers RTC configuration and status registers Register address map configuration registers must be accessed as 32 bit words and as single accesses only Bursting is not allowed 9006 0000 RTC General Control register 9006 0004 12 24 Hour register 9006 0008 Time register 90060 000C Calendar register 9006 0010 Time Alarm register 9006 0014 Calendar Alarm register 9006 0018 Alarm Enable register 9006 001C Event Flags register 9006 0020 Interrupt Enable register 9006 0024 Interrupt Disable register 9006 0028 Interrupt Status register 9006 002C General Status register The reset values listed in the register descriptions are set when the regulated battery voltage on pins N3 and MA drops below 1 56V RTC General Control register Register Address 9006 0000 The RTC General Control register contains miscellaneous settings for the RTC module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2
423. river ceti 456 2 master software meme 456 2 slave high level 2 20222 22 456 CHAPS cc ETT 457 Master module normal mode 16 457 Slave module normal mode 16 458 Chapter 14 Real Time Clock Module 459 RTCfunctioriality tite tta tein toda ee Feds Fett b d d 459 RTC configuration and status 00 020 0 22 2 460 Register address 460 RTC General Control register nnn 460 12 24 dase lads 461 Time registerz ted edt 462 Calendar register x a east 463 Time Alarm register 464 Calendar Alarm register 465 Alarm Enable register icc eee eet ERR Re ERR A RR EL Rud 465 Event Flags TeglSter iss rotor trt seat na Cad 466 Interrupt Enable register 20222 468 Interrupt Disable register s ote e ont edi reote teil
424. rol bit D16 R W GPIO16 0 GPIO 16 control bit D17 R W GPIO17 0 GPIO 17 control bit D18 R W GPIO18 0 GPIO 18 control bit D19 R W GPIO19 0 GPIO 19 control bit D20 R W GPIO20 0 GPIO 20 control bit 21 GPIO21 0 GPIO 21 control bit D22 R W GPIO22 0 GPIO 22 control bit D23 R W GPIO23 0 GPIO 23 control bit D24 R W GPIO24 0 GPIO 24 control bit 70 Hardware Reference NS9215 CONTROL MODULE GPIO Control registers Bit s Access Mnemonic Reset Description D25 R W GPIO25 0 GPIO 25 control bit D26 R W GPIO26 0 GPIO 26 control bit D27 R W GPIO27 0 GPIO 27 control bit D28 R W GPIO28 0 GPIO 28 control bit D29 R W GPIO29 0 GPIO 29 control bit D30 R W GPIO30 0 GPIO 30 control bit D31 R W GPIO31 0 GPIO 31 control bit GPIO Control Address A090_ 2070 Register 1 Bit s Access Mnemonic Reset Description GPIO32 0 GPIO 32 control bit D01 R W GPIO33 0 GPIO 33 control bit D02 R W GPIO34 0 GPIO 34 control bit D03 R W GPIO35 0 GPIO 35 control bit D04 R W GPIO36 0 GPIO 36 control bit D05 R W GPIO37 0 GPIO 37 control bit D06 R W GPIO38 0 GPIO 38 control bit D07 R W GPIO39 0 GPIO 39 control bit D08 R W GPIO40 0 GPIO 40 control bit D09 R W GPIO41 0 GPIO 41 control bit D10 R W GPIO42 0 GPIO 42 control bit D11 R W GPIO43 0 GPIO 43 control bit D12 R W GPIO44 0 GPIO 44 control bit D13 R W GPIO45 0 GPIO 45 control bit 14
425. rovides a central location for clock trees and reset logic MIIM MII management Provides control status path to MII PHYs STAT www digiembedded com Statistics module Counts and saves Ethernet statistics 263 ETHERNET COMMUNICATION MODULE Station address logic SAL Feature Description SAL Station address logic Performs destination address filtering MII Media Independent Interface Provides the interface from the MAC core to a PHY that supports the MII as described in the IEEE 802 3 standard PHY interface This table shows how the different PHY interfaces are mapped to the external IO mappings External IO MII RXD 3 RXD 3 RXD 2 RXD 2 RXD 1 RXD 1 RXD 0 RXD 0 RX DV RX DV RX ER RX ER RX CLK CLE TXD 3 TXD 3 TXD 2 TXD 2 TXD 1 TXD 1 TXD 0 TXD 0 TX EN TX EN TX ER TX ER TX CLK TX CLK CRS CRS COL COL MDC MDC MDIO MDIO Station address logic SAL The station address logic module examines the destination address field of incoming frames and filters the frames before they are stored in the Ethernet front end 264 Hardware Reference NS9215 receiver ETHERNET COMMUNICATION MODULE Statistics module module The filtering options listed next are programmed in the Station Address Filter register see page 301 m X Accept frames to destination address programmed the SA1 SA2 and SA3 registers
426. rrupt Config registers see Int Interrupt Config Configuration 31 0 registers on page 175 IRQ interrupts can be enabled or disabled on a per level basis using the Interrupt Enable registers These registers serve as masks for the different interrupt levels Each interrupt level hastwo registers a Interrupt Configuration register Use this register to assign the source for each interrupt level invert the source polarity select IRQ or FIQ and enable the level Interrupt Vector Address register Contains the address of the interrupt service routine The next figure shows a 32 vector interrupt controller 148 Hardware Reference NS9215 SYSTEM CONTROL MODULE Interrupt controller nterrupt Source 0 nterrupt Source 1 Priority Level 0 highest nterrupt Source 31 Invet EE gt Interrupt Source ID Reg 0 Enable d Winning Priority Level Active Interrupt Level Reg nterrupt Source 0 nterrupt Source 1 b Interrupt Vector Address Reg Level 0 Priority Level 1 2 Priority Interrupt Vector Address Reg Level 1 nterrupt Source 31 gt ISADDR Reg P Invert v Encoder Interrupt Source ID Reg 1 Enable Interrupt Vector Address Reg Level 31 nterrupt Source 0 nterrupt Source
427. rrupt pending TX Set when a buffer is closed under normal conditions An interrupt is generated when the I bit is set in the current buffer descriptor A normal DMA completion occurs when the buffer length field expires D23 R W TXECIP 0x0 Error completion interrupt pending TX Set when the DMA channel finds either a bad buffer descriptor or a bad data buffer pointer The DMA channel remains in the ERROR state until the CE bit in the DMA Control register is cleared and then set again The DMA channel then uses the buffer descriptor as set in the index control field D22 R w TXNRIP 0x0 Buffer not ready interrupt pending TX Set when the DMA channel finds a buffer descriptor with the F bit not set The DMA channel remains in the ERROR state until the CE bit in the DMA Control register is cleared and then set again The DMA channel then uses the buffer descriptor as set in the index control field D21 R W TXCAIP 0x0 Channel abort interrupt pending TX Set when the DMA channel finds the channel abort CA control bit set The DMA controller closes the current buffer descriptor and remains in the IDLE state until the CA bit is cleared and the CE bit is set D20 R W TXFUFIP 0x0 TX FIFO underflow interrupt pending Set when the TX FIFO finds an underflow D19 R W TXFSRIP 0x0 TX FIFO service request interrupt pending TX Set when the TX FIFO level drops below the transmit FIFO threshold in the TX Interrupt Configur
428. rt m 16 bit and 32 bit wide chip select SDRAM memory support m Static memory features such as Asynchronous page mode read Programmable wait states Bus turnaround delay Output enable and write enable delays Extended wait 203 MEMORY CONTROLLER m 5 modes that dynamically control SDRAM en Dynamic memory self refresh mode supported by a power management unit PMU interface or by software Controller supports 2K 4K and 8K row address synchronous memory parts that is typical 512 MB 256 MB and 16 Mb parts with 8 16 or 32 DQ bits per device m Aseparate AHB interface to program the memory controller This enables the memory controller registers to be situated in memory with other system peripheral registers m Locked AHB transaction support m Support for all AHB burst types m Little and big endian support Note Synchronous static memory devices synchronous burst mode are not supported Low power operation Low power SDRAM deep sleep mode Low power SDRAM partial array refresh In many systems the contents of the memory system have to be maintained during low power sleep modes The processor provides two features to enable this Dynamic memory refresh over soft reset mechanism to place the dynamic memories into self refresh mode Self refresh mode can be entered as follows 1 Setthe SREFREQ bit in the Dynamic Memory Control register 2 Poll the SRE
429. rtual address bits 19 0 Coarse page table base Indexed by modified virtual address bits 19 10 Fine page table base Indexed by modified virtual address bits 19 12 1 MB Coarse page table WORKING WITH THE CPU MemoryManagement Unit MMU Large page base Large page Indexed by modified virtual address bits 15 0 256 entries Fine page table 1024 entries 64 KB Small page _ gt Indexed by modified virtual address bits 11 0 4 KB Tiny page gt Indexed by modified virtual address bits 9 0 1 KB Bits 31 14 of the TTB register are concatenated with bits 31 20 of the MVA to produce a 30 bit address 109 WORKING WITH THE CPU MemoryManagement Unit MMU First level fetch concatenation and Modified virtual address address 31 20 19 0 Table index Translation table base 31 14 13 0 Translation base 31 14 13 210 Translation base Table index 010 31 0 This address selects a 4 byte translation table entry This is a first level descriptor for either a section or a page First level The first level descriptor returned is a section description a coarse page table descriptor descriptor a fine page table descriptor or is invalid This is the format of a first level descripto
430. rupt D23 R W RXECIE 0 0 Enable the RXECIP interrupt D22 R W RXNRIE 0x0 Enable the RXNRIP interrupt 21 R W RXCAIE 0x0 Enable the RXCAIP interrupt D20 R W RXPCIE 0x0 Enable the RXPCIP interrupt D19 R WSTAT 0x0 Debug field indicating the W bit is set in the current buffer descriptor D18 R ISTAT 0x0 Debug field indicating the I bit is set in the current buffer descriptor D17 R LSTAT 0x0 Debug field indicating the L bit is set in the current buffer descriptor D16 R FSTAT 0x0 Debug field indicating the F bit is set in the current buffer descriptor D15 00 R BLENSTAT 0x0 Debug field indicating the current byte count Module Direct Mode RX Status FIFO Addresses 9000_0010 9000_8010 9001_0010 9001_8010 9002_0010 9002_8010 9003_0010 9003_8010 The Direct Mode RX Status FIFO register is used when in direct mode of operation to determine the status of the receive FIFO m This register must be read before each read to the RX Data FIFO register m RX Data FIFO register must be read after each read to this register even if the BYTE field is O Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Feserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 378 Hardware Reference NS9215 3 March 2008 Register bit I O HUB MODULE Module Direct Mode RX Data FIFO assignment Access Description D31 12 N A Reserved N A N A D11 09 R BYTE N A Number of
431. ryManagement Unit MMU page tables have 1024 entries splitting the 1 MB that the table describes into 1 KB blocks The next two sections show the format of a fine page table descriptor and define the fine page table descriptor bit assignments Note f a fine page table descriptor is returned from the first level fetch second level fetch is initiated Fine page table descriptor format 31 12 11 9 5 4 3 2 1 0 Fine page table base address SBZ Domain 1 9 2 111 Fine page table descriptor bit Bits Description deseription 31 12 Forms the base for referencing the second level descriptor the fine page table index for the entry is derived from the MVA 11 9 Always written as 0 8 5 Specifies one of the 16 possible domains held in the Domain Access Control register that contain primary access controls 4 Always written as 1 3 2 Always written as 0 1 0 Must be 11 to indicate a fine page table descriptor Translating This figure illustrates the complete section translation sequence section references www digiembedded com 113 WORKING WITH THE CPU BEES MemoryManagement Unit MMU 31 2019 0 Table index Section index Translation table base 31 14 13 0 Translation base 31 1413 210 Translation base Table index 0 0 Section first level descriptor 31 2019 8 543210 Section base address SBZ 0 Domain 1 0 1 Physical ad
432. s are accessed with zero wait states Register address These are the external DMA control and status registers map Address Description Access Reset value 0xA080_0000 DMA Channel 1 Buffer Descriptor Pointer R W 0x00000000 0 080 0004 Channel 1 Control register R W 0x00000000 0 080 0008 DMA Channel 1 Status and Interrupt Enable R W 0x00000000 0 080 000C DMA Channel 1 Peripheral Chip Select R W 0x00000000 0 080 0010 DMA Channel 2 Buffer Descriptor Pointer R W 0x00000000 0 080 0014 Channel 2 Control register R W 0x00000000 0 080 0018 DMA Channel 2 Status and Interrupt Enable R W 0x00000000 0 080 001C DMA Channel 2 Peripheral Chip Select R W 0x00000000 DMA Buffer Descriptor Pointer Address A080 0000 A080 0010 The DMA Buffer Descriptor Pointer register contains a 32 bit pointer to the first buffer in a contiguous list of buffer descriptors The external DMA module has two of these registers Each buffer descriptor is 16 bytes in length 346 Hardware Reference NS9215 Register 31 30 29 28 27 26 25 15 14 13 12 11 10 9 Register bit assignment Bit s Access Mnemonic D31 00 R W BuffDesc 24 23 22 BuffDesc 8 7 6 BuffDesc Reset 0x0000_0000 EXTERNAL DMA DMA Control register 21 19 18 17 16 Description 32 bit pointer to a buffer descriptor DMA Control register Address A080_0004 A080_0014 The DMA Control register contains the required DMA transfer co
433. s of the multicast address and a separate register that contains the upper 16 bits of the address For an explanation of the synchronization scheme used for these registers see Clock synchronization on page 276 Address A060 0A40 D31 00 R W Default 0x0000 0000 MFILTLO Address A060 0 44 D31 00 R W Default 0x0000 0000 MFILTL1 Address A060 0A48 D31 00 R W Default 0x0000 0000 MFILTL2 Address A060 0A4C D31 00 R W Default 0x0000 0000 MFILTLA Address A060 0A50 D31 00 R W Default 0x0000 0000 MFILTLA Address A060 0 54 D31 0 R W Default 0x0000 0000 MFILTLS 327 ETHERNET COMMUNICATION MODULE Multicast Low Address Filter Register 6 Multicast Low Address Filter Register 7 Multicast High Address Filter Register 0 Multicast High Address Filter Register 1 Multicast High Address Filter Register 2 Multicast High Address Filter Register 3 Multicast High Address Filter Register 4 Multicast High Address Filter Register 5 Address A060 0A58 D31 00 R W Default 0x0000 0000 Address A060 0A5C D31 00 R W Default 0x0000 0000 Address A060 0A60 D31 16 R Default 0x0000 0000 D15 00 R W Default 0x0000 0000 Address A060 0A64 D31 16 R Default 0x0000 0000 D15 00 R W Default 0x0000 0000 Address A060 0A68 D31 16 R Default 0x0000 0000 D15 00 R W Default 0x0000 0000 Address A060 0A6C D31 16 R Default 0x0000 0000 D15 00 R W Defau
434. s place the TLNB entry in the set associative region of the TLB P 1 Subsequent hardware page table walks place the TLB entry in the lockdown region at the entry specified by the victim in the range 0 7 TLB entries in the lockdown region are preserved so invalidate TLB operations only invalidate the unpreserved entries in the TLB that is those entries in the set associative region Invalidate TLB single entry operations invalidate any TLB entry corresponding to the modified virtual address given in Rd regardless of the entry s preserved state that is whether they are in lockdown or set associative TLB regions See R8 TLB Operations register on page 97 for a description of the TLB invalidate operations 101 WORKING WITH THE CPU Programming Use these instructions to program the TLB Lockdown register instructions Read data TLB lockdown victim MRC 5 0 Rd c10 c0 0 Write data TLB lockdown victim MCR p15 0 Rd c10 c0 0 The victim automatically increments after any table walk that results in an entry being written into the lockdown part of the TLB Note t is not possible for a lockdown entry to map entirely either small or large pages unless all subpage access permissions are the same Entries can still be written into the lockdown region but the address range that is mapped covers only the subpage corresponding to the address that was used to perform the page table walk Sample code This
435. s the ICache Lockdown register Use these instructions to access the CacheLockdown register Function Data Instruction Read DCache Lockdown register L bits 5 0 Rd c9 c0 0 Write DCache Lockdown register L bits MCR 15 0 Rd c9 c0 0 Read ICache Lockdown register L bits 15 0 Rd c9 c0 1 Write ICache Lockdown register L bits 5 0 Rd c9 c0 1 You must modify the Cache Lockdown register using a modify read write sequence for example p15 0 Rn c9 c0 1 ORR Rn 0x01 MCR p15 0 Rn c9 c0 1 This sequence sets the L bit to 1 for way 0 of the ICache This is the format for the Cache Lockdown register 31 16 15 4 3 0 L bits cache ways 0103 SBZ UNP SBO This table shows the format of the Cache Lockdown register L bits cache ways are available for allocation from reset Bits 4 way associative Notes 31 16 UNP SBZ Reserved 15 4 OxFFF SBO 99 Lockdown cache Specific loading of addresses into a WORKING WITH THE CPU R9 Cache Lockdown register Bits 4 way associative Notes L bit for way 3 Bits 3 0 are the L bits for each cache way L bit for way 2 0 Allocation to the cache way is determined by the standard replacement algorithm reset state L bit for way 1 1 No allocation is performed to this way L bit for way 0 cache way 100 1 Use this procedure to lockdown cache The
436. s the following Provides control functions to the MAC Buffers and filters the frames received from the Pumps transmit data into the MAC Moves frames between the MAC and the system memory Reports transmit and receive status to the host Common RD Receive read acronyms RX WR Receive write TX RD Transmit read TX WR Transmit write www digiembedded com 261 ETHERNET COMMUNICATION MODULE Ethernet communications module Ethernet PHY TX RX MGMT Ethernet MAC 9 e z 5 9 I Ethernet Front End SYSTEM BUS Ethernet MAC The Ethernet MAC includes a full function 10 100 Mbps Media Access Controller MAC station address filtering logic SAL statistic collection module STAT and MII 262 Hardware Reference NS9215 MAC module block diagram SYSTEM INTERFACE MODULE MAC module features Feature MAC Core ETHERNET COMMUNICATION MODULE Ethernet MAC Tx DATA Tx CONTROL Rx DATA Rx CONTROL CONTROL STATUS CLK amp RESET Description 10 100 megabit Media Access Controller Performs the CSMA CD function m MCS MAC control sublayer m Transmit function m RFUN Receive function HOST Host interface Provides an interface for control and configuration CLK amp Reset Clocks amp resets P
437. s written to system memory F When set indicates the buffer is full The RX RD logic sets this bit after filling a buffer The system software clears this bit as required to free the buffer for future use When a new frame is received pools that have the F bit set in their next buffer descriptor are skipped when deciding in which pool to put the frame Buffer length This is a dual use field m When the buffer descriptor is read from system memory buffer length indicates the maximum sized frame in bytes that can be stored in this buffer ring m When the RD logic writes the descriptor back from the receive status FIFO into system memory at the end of the frame the buffer length is the actual frame length in bytes Only the lower 11 bits of this field are valid since the maximum legal frame size for Ethernet is 1522 bytes Transmit packet processor Transmit frames are transferred from system memory to the transmit packet processor into a 256 byte TX_FIFO Because various parts of the transmit frame can www digiembedded com 269 ETHERNET COMMUNICATION MODULE reside in different buffers in system memory several buffer descriptors can be used to transfer the frame Transmit buffer All buffer descriptors that is up to 64 are found in a local TX buffer descriptor descriptor format RAM This is the transmit buffer descriptor format 31 30 29 28 16 15 0 OFFSET 0 Source Addr
438. scriptor holds the four bit domain field which selects one of the 16 two bit domains in the Domain Access Control register The two bits of the specified domain are then checked for access permissions as described in Interpreting access permission bits on page 121 The domain is checked when the level one descriptor is returned If the specified access is either no access 00 or reserved 10 either a section domain fault or a page domain fault occurs If the two bit domain field returns client 01 access permissions are checked as follows Section If the level one descriptor defines a section mapped access the AP bits of the descriptor define whether the access is allowed per Interpreting access permission bits on page 121 The interpretation depends on the setting of the S and R bits see R1 Control register beginning on page 88 If the access is not allowed a section permission fault is generated Large page or small page If the level one descriptor defines page mapped access and the level two descriptor is for a large or small page four access permission fields AP3 to APO are specified each corresponding to one quarter of the page For small pages AP3 is selected by the top 1 KB of the page and APO is selected by the bottom 1 KB of the page For large pages AP3 is selected by the top 16 KB of the page and APO is selected by the bottom 16 KB of the page The selected AP bits are then 124 Hardware Reference NS92
439. select 1 D11 00 N A Reserved N A N A D31 12 R W CSIM OxF0000 Chip select 1 mask Mask or size for chip select 5 D11 01 N A Reserved N A N A D00 R W CSDI 0 1 Chip select 1disable 0 Disable chip select Enable chip select System Memory Chip Select 2 Dynamic Memory Base and Mask registers 192 Addresses A090 01 0 01 4 These control registers set the base and mask for system memory chip select 2 with a minimum size of 4K The powerup default settings produce a memory range of 0x2000 0000 Ox2FFF FFFF Hardware Reference NS9215 Registers Register bit assignment 31 30 29 28 27 26 SYSTEM CONTROL MODULE System Memory Chip Select 3 Dynamic Memory Base and Mask registers 25 24 23 22 21 20 Chip select 2 base CS2B 0 Disable chip select Enable chip select 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip select 2 base CS2B Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select 2 mask 52 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip select 2 mask 52 Reserved CSD2 Bits Access Mnemonic Reset Description D31 12 R W CS2B 0x20000 Chip select 2 base Base address for chip select 2 D11 00 N A Reserved N A N A D31 12 R W CS2M 0 0000 Chip select 2 mask Mask or size for chip select 2 D11 01 N A Reserved N A N A D00 R W CSD2 0 1 Chip select 2 disable System Memory Chip Select 3 Dynamic Memory Base and Mask registers www digiembedded com
440. served gpio 36 Ethernet MII RX ER PIC 0 GEN IO Sj I O dup Reserved gpio 37 Ethernet MII RXD 0 0 GEN IO 6j I O dup Reserved gpio 38 Ethernet MII RXD 1 0 GEN IO 7 I O dup Reserved gpio 39 Ethernet MII RXD 2 PIC 1 GEN IO 0j I O dup Reserved gpio 40 Ethernet MII RXD 3 PIC 1 GEN IO 1j I O dup Reserved gpio 41 Ethernet MII TX EN PIC 1 GEN IO 2 I O dup Reserved gpio 42 Ethernet MII TX ER PIC 1 GEN IO 3 I O dup Reserved gpio 43 Ethernet MII TXD 0 PIC 1 GEN IO 4 I O dup Reserved gpio 44 Ethernet MII TXD 1 PIC 1 GEN IO Sj I O dup Reserved gpio 45 17 gplo 37 U 2 D13 gpio 38 U VO 2 17 gplo 39 U 2 D16 gpio 40 U 2 0 17 gpio 41 U LO 2 B14 gpio 42 U 2 0 15 gpio 43 U LO 2 gpio 44 U LO 2 em 12 gplo 45 U 2 36 Hardware Reference NS9215 265 General purpose I O GPIO Description D12 gpio 46 U IO Ethernet TXD 2 PIC 1 GEN IO 6 I O dup Reserved gpio 46 A16 gpio 47 U IO Ethernet MII TXD 3 PIC 1 GEN IO 7j I O dup Reserved gpio 47 14 gpio 48 Ethernet Reserved Reserved g
441. ses are remapped from VA to PA depending on the MMU page table entry that is VA translated to MVA MVA remapped to PA If either the DCache or is disabled the contents of that cache are not accessed If the cache subsequently is re enabled the contents will not have changed To guarantee that memory coherency is maintained the DCache must be cleaned of dirty data before it is disabled 90 Hardware Reference NS9215 WORKING WITH THE CPU R2 Translation Table Base register R2 Translation Table Base register Register format Register R2 isthe Translation Table Base register TTBR for the base address of the first level translation table w Reading from R2 returns the pointer to the currently active first level translation table in bits 31 14 and an UNPREDICTABLE value in bits 13 0 wm Writing to R2 updates the pointer to the first level translation table from the value in bits 31 14 of the written value Bits 13 0 SHOULD BE ZERO Use these instructions to access the Translation Table Base register pl5 0 Rd c2 0 read TTBR MCR p15 0 Rd c2 c0 0 write TTBR The CRm and opcode 2 fields SHOULD BE ZERO when writing to R2 31 14 13 0 Translation table base UNP SBZ R3 Domain Access Control register Register format Access permissions and instructions www digiembedded com Register R3 is the Domain Access Control register and consists of 16 two bit fields
442. sitive input timing requirements 482 22 483 Memory Tilt aac tert eee wee Ra Pr a edd 484 SDRAM burst read 16 6 485 SDRAM burst read 16 bit CAS latency 3 486 SDRAM burst write 16 487 SDRAM burst read 32 Dit EIE DUREE 488 SDRAM burst read 32 bit CAS latency 3 489 SDRAM burst write 32 490 SDRAM load Eme erre ttd 491 SDRAM refresh mode 492 Clock enable timing hee Ex 493 Values in SRAM timing 4 494 Static RAM read cycles with 0 wait 5 495 Static RAM asynchronous page mode read WTPG 21 496 Static RAM read cycle with configurable wait states 497 Static RAM sequential write cycles 498 Static RAM write 2 499 Static write cycle with c
443. sk lt 3 0 gt dy_cs_n lt 3 0 gt ras n cas n we n Notes Thisis the bank and RAS address 2 This is the CAS address 488 Hardware Reference NS9215 Memory Timing SDRAM burst read 32 bit CAS latency 2 3 H re ad lat lat data A data B data C out 3 data D data lt 31 0 gt addr Note data lt 3 0 gt dy cs lt 3 0 gt ras n NE cas Notes 1 2 This is the bank and RAS address This is the CAS address www digiembedded com 489 TIMING SDRAM burst write 32 bit t dk out D T T T i Lu 0 12 4 i i 0 T T T T i 1 1 1 1 DL XTT Nowe 30 i i lt 3 0 gt i 1 1 1 1 1 9 1 1 1 I 1 1 Notes Thisis the bank and RAS address 2 This is the CAS address 490 Hardware Reference NS9215 SDRAM load mode dy cs lt 3 0 gt ras n cas n we n www digiembedded com TIMING Memory Timing 491 TIMING SDRAM refresh mode out dy 50 n dy csi n dy cs3 n ras n i 8 _ 492 Hardware Reference NS9215 Memory Timing gt Clock enable timing dk out
444. small page descriptor is included in a fine page table the upper two bits of the page index and low order two bits of the fine page table index overlap Each fine page table entry for a small page must be duplicated four times 117 WORKING WITH THE CPU MemoryManagement Unit MMU Translation sequence for tiny Modified virtual address page references 81 2019 109 0 Level two Table index table index Page index Translation table base 31 14 13 0 Translation base 81 v 1413 210 mm First level descriptor 31 1211 8 543210 eme 31 1211 210 a Second level descriptor 31 109 6543210 TE Physical address 31 109 Page translation involves one additional step beyond that of a section translation The first level descriptor is the fine page table descriptor this points to the first level descriptor Note The domain specified in the first level description and access permissions specified in the first level description together determine whether the access has permissions to proceed See Domain access control on page 121 for more information Subpages You can define access permissions for subpages of small and large pages If duringa 118 page table walk a small or large page has a different subpage permission only the subpage being accessed is written into the TLB For example a 16 KB large page subpage entry is written into the TLB if the subpage permission differs
445. sor Power down mode www digiembedded com As a frame is received from the Ethernet MAC it is stored in the receive data FIFO At the end the frame an accept rej ect decision is made based on several conditions If the packet is rejected it is flushed from the receive data FIFO If a frame is accepted status signals from the MAC including the receive size of the frame are stored in a separate 32 entry receive status FIFO the Rx logic is notified that a good frame is in the FIFO If the RX WR logic tries to write to a full receive data FIFO anytime during the frame it flushes the frame from the receive data FIFO and sets RXOVFL DATA RX data FIFO overflowed in the Ethernet Interrupt Status register For proper operation reset the receive packet processor using the ERX bit in the Ethernet General Control Register 1 when this condition occurs If the WR logic tries to write a full receive status FIFO at the end of the frame the wR logic flushes the frame from the receive data FIFO and sets RXOVFL STAT RX status FIFO overflowed in the Ethernet Interrupt Status register The RX WR logic supports the processor system power down and recovery functionality In this mode the RX clock to the MAC and the WR logic are still active but the clock to the Rx RD and AHB interface is disabled This allows frames to be received and written into the receive FIFO but the frame remains in the FIFO until the system wakes up
446. stem initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode This value normally is found in SDRAM data sheets as Note The Dynamic Memory Self refresh Exit Time register is used for all four dynamic memory chip selects The worst case value for all chip selects must be programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SREX Bits Access Mnemonic Description D31 04 N A Reserved N A do not modify D03 00 R W SREX Self refresh exit time tsp rx 0 0 0 1 clock cycles where the delay is in cycles OxF 16 clock cycles reset value on reset_n Dynamic Memory Last Data Out to Active Time register Address A070 003C The Dynamic Memory Last Data Out to Active Time register allows you to program the last data out to active command time It is recommended that this register be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode This value normally is found in SDRAM datasheets as t ppp Note The Dynamic Memory Last Data Out to Active Time register is used for all four dynamic memory chip selects The worst case value for all chip selects must be programmed 240 Hardware Reference NS9215 Register
447. t Determines the cache size and cache associativity values in conjunction with the size and assoc fields Note This field must be set to 0 for the ARM926EJ S processor Len Determines the line length of the cache m Thelen field is bits 13 12 for the DCache and bits 1 0 for the ICache m Line length encoding Len field Cache line length 10 8 words 32 bytes Other values Reserved R1 Control register 880 06 6 000000000000 00 000000000060 6 60600 0000 Register R1 is the control register for the ARM926E S processor This register specifies the configuration used to enable and disable the caches and MMU memory management unit It is recommended that you access this register using a read modify write sequence For both reading and writing the CRm and opcode 2 fields SHOULD BE ZERO Use these instructions to read and write this register 15 0 Rd 0 read control register 5 Rd c0 0 write control register defined control bits are set to zero on reset except the V bit and B bit m TheV bit is set to zero at reset if the viNITHI signal is low m TheBbit is set to zero at reset if the BIGENDINIT signal is low and set to one if the BIGENDINIT Signal is high 88 Hardware Reference NS9215 Control register 31 WORKING WITH THE CPU RI Control register
448. t 1 Static Memory Base and Mask registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select O base CSOB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip select 0 base 5 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select O mask CSOM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Chip select mask CSOM Reserved CSDO Bits Access Mnemonic Reset Description D31 12 R W CSOB 0x40000 Chip select 0 base Base address for chip select 0 D11 00 N A Reserved N A N A D31 12 R W CSOM 0 0000 Chip select 0 mask Mask or size for chip select 0 D11 01 N A Reserved N A N A D00 R W CSDO 0 1 Chip select 0 disable 0 Disable chip select Enable chip select System Memory Chip Select 1 Static Memory Base and Mask registers www digiembedded com Addresses A09001F8 01 These control registers set the base and mask for system memory chip select 1 with a minimum size of 4K The powerup default settings produce a memory range of 0x5000 0000 Ox5FFF 195 SYSTEM CONTROL MODULE System Memory Chip Select 2 Static Memory Base and Mask registers Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select 1 base CS1B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Chip select 1 base CS1B Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Chip select 1 mask CS1M 15 14 13 12 11 10
449. t incremented when a packet is truncated because it exceeds the MAXF value D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 ROVR Incremented for each frame received that is less than 64 bytes in length and contains an invalid FCS this includes integral and non integral lengths D31 12 R Reserved D11 00 R W Reset 0x000 RFRG 306 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Statistics registers Receive jabber Incremented for frames received that exceed 1518 bytes non VLAN or 1522 bytes counter A060 VLAN and contain an invalid FCS including alignment errors This counter does not 06D8 increment when a packet is truncated to 1518 non VLAN or 1522 VLAN bytes by MAXF D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 RJBR Transmit statistics counters address Address Register Transmit counters R W 060 06 0 Transmit byte counter R W A060 06 4 TPKT Transmit packet counter R W A060 06 8 TMCA Transmit multicast packet counter R W A060 06EC TBCA Transmit broadcast packet counter R W A060 06 0 Reserved N A N A A060 06F4 TDFR Transmit deferral packet counter R W A060 06 8 TEDF Transmit excessive deferral packet counter R W A060 06 TSCL Transmit single collision packet counter R W A060 0700 TMCL Transmit multiple collision packet counter R W A060 0704 TLCL Transmit late collision packet counter R W A060 0708 T
450. t mask D14 R W M2TFG 1 Mask register 2 counter carry bit mask D13 R W M2TBY 1 Mask register 2 TBYT counter carry bit mask D12 R W 2 1 Mask register 2 TPKT counter carry bit mask D11 R W M2TMC 1 Mask register 2 counter carry bit mask D10 R W M2TBC 1 Mask register 2 counter carry bit mask D09 R W Not used 1 Always write as 1 D08 R W M2TDF 1 Mask register 2 TDFR counter carry bit mask D07 R W M2TED 1 Mask register 2 counter carry bit mask D06 R W M2TSC 1 Mask register 2 TSCL counter carry bit mask D05 R W M2TMA 1 Mask register 2 TMCL counter carry bit mask D04 R W M2TLC 1 Mask register 2 TLCL counter carry bit mask D03 R W M2TXC 1 Mask register 2 TXCL counter carry bit mask D02 R W M2TNC 1 Mask register 2 counter carry bit mask D01 00 R W Not used 11 Always write as 11 314 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE A Buffer Descriptor Pointer register RX A Buffer Descriptor Pointer register Address A060 0A00 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXAPTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXAPTR Register bit assignment Bits Access Mnemonic Reset Description D31 00 R W RXAPTR 0x00000000 RX_A Buffer Descriptor Pointer Contains a pointer to the initial receive buffer descriptor for the A pool of buffers RX_B Buffer Descriptor Pointer register Address A060 0A04 Register 31 30 29 28 27 26 25 24 23 22 21
451. t pending Set when the DMA channel encounters a buffer descriptor whose F bit is in the incorrect state The F bit must be set in order for the fetched buffer descriptor to be considered valid If the F bit is not set the descriptor is considered invalid and the NRIP field is set When the NRIP bit is set the DMA channel stops until the field is cleared by firmware The DMA channel does not advance to the next buffer descriptor D28 R WIC CAIP Channel abort interrupt pending Set when the DMA channel detects the CA bit D30 set in the DMA Control register When is set the channel stops until the CAIP bit is cleared by firmware The DMA channel automatically advances to the next buffer descriptor after CAIP 15 cleared The CA bit in the DMA Control register must be cleared through firmware before the CAIP bit is cleared Failure to reset the CA bit cause the next buffer descriptor to abort also D27 D26 25 www digiembedded com R WIC PCIP Not used Premature complete interrupt pending Set when a DMA transfer is terminated by assertion of the dma done signal NCIP is set when PCIP is set for backwards compatibility This field must always be set to 0 351 EXTERNAL DMA Peripheral Chip Select register Bit s Access Mnemonic Reset Description D24 R W NCIE 0 Enable NCIP interrupt generation D23 R W ECIE 0 Enable ECIE interrupt generati
452. t upon terminal count wm Each GPTC has interrupt request connected to the IRQ interrupt controller VIC The priority level and enable disable of each interrupt can be programmed in the VIC The CPU can read the contents of the timer counter m GPTCscan be concatenated to form larger timer counters Include this control field in each of the 32 bit timer counter control registers m Clock frequency selection w Mode of operation Internal timer with or without external terminal count indicator External gated timer with gate active low External gated timer with gate active high External event counter frequency must be less than one half the system memory clock frequency m Timer counter enable Count up or down 143 16 bit mode options SYSTEM CONTROL MODULE Interrupt enable Concatenate to up stream timer counter that is use up stream timer counter s overflow underflow output as clock input Reload enable Basic PWM function Enhanced PWM functionality timers 6 9 Quadrature decoder function timer 5 32 bit or 16 bit operation These options are available in 16 bit mode Capture mode Capture the counter value on the rising or falling edge of an external event and interrupt the CPU Compare mode Interrupt the CPU when the counter value is equal to the Match register Basic PWM function Functional block diagram pulse width control period control Any of the timer counters
453. ta to be sent to the MAC and to allow processor access to the TX buffer descriptor RAM 280 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Ethernet General Control Register 1 Bits Access Mnemonic Reset Description D22 R W ETXDMA 0 Enable transmit DMA 0 Disable transmit DMA data request use to stall transmitter Enable transmit DMA data request Must be set active high to allow the transmit packet processor to issue transmit data requests to the AHB interface Set this bit to 0 to temporarily stall frame transmission which always stalls at the completion of the current frame The 8 bit address of the next buffer descriptor to be read in the TX buffer descriptor RAM is loaded into the TXSPTR register when the transmit process ends If the transmit packet processor already is stalled and waiting for TCLER clearing ETXDMA will not take effect until TCLER has been toggled This bit generally should be set after the Ethernet transmit parameters for example buffer pointer descriptor are programmed into the transmit packet processor D21 R W Not used 1 Always write as 1 D20 R W Not used 0 Always write as 0 D19 R W ERXINIT 0 Enable initialization of RX buffer descriptors 0 Do not initialize 1 Initialize When set causes the RX_RD logic to initialize the internal buffer descriptor registers for each of the four pools from the buffer descriptors pointed to by RXAPTR RXBPTR RXCPTR and RXDPTR This is done
454. tain the primary access controls 4 Should be written as 1 for backwards compatibility 3 2 Indicate if the area of memory mapped by this section is treated as writeback cachable write through cachable noncached buffered or noncached nonbuffered 1 0 Must be 1010 indicate a section descriptor A coarse page table descriptor provides the base address of a page table that contains second level descriptors for either large page or small page accesses Coarse page tables have 256 entries splitting the 1 MB that the table describes into 4 KB blocks Note f a coarse page table descriptor is returned from the first level fetch a second level fetch is initiated 31 109 8 5 4 3 2 1 0 5 Coarse page table base address B Domain 1 SBZ 0 1 7 Bits Description 31 10 Forms the base for referencing the second level descriptor the coarse page table index for the entry derived from the MVA 9 Always written as 0 8 5 Specifies one of the 16 possible domains held in the Domain Access Control registers that contain the primary access controls 4 Always written as 1 3 2 Always written as 0 1 0 Must be 01 to indicate a coarse page descriptor A fine page table descriptor provides the base address of a page table that contains second level descriptors for large page small page or tiny page accesses Fine 112 Hardware Reference NS9215 WORKING WITH THE CPU Memo
455. tains the DMA transfer status and control information used in generating AHB DMA interrupt signals The external DMA module has two of these registers Register 31 30 29 28 27 26 2b 24 23 22 21 20 19 18 17 16 NRIP PCIE LAST FULL DONE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 350 Hardware Reference NS9215 Register bit assignment D31 Access R WIC Mnemonic NCIP Reset 0 EXTERNAL DMA DMA Status and Interrupt Enable register Description Normal completion interrupt pending Set when a buffer descriptor has been closed A normal DMA channel completion occurs when the BLEN count D15 00 expires to zero and the L but in the buffer descriptor is set or when the peripheral device signals completion D30 R WIC ECIP Error completion interrupt pending Set when the DMA channel encounters either a bad buffer descriptor pointer or a bad data buffer pointer When the ECIP bit is set the DMA channel stops until the ECIP bit is cleared by firmware The DMA channel does not advance to the next buffer descriptor When firmware clears the ECIP bit the buffer descriptor is retried from where it left off The CA bit in the DMA Control register can be used to abort the current buffer descriptor and advance to the next descriptor D29 R WIC NRIP Buffer not ready interrup
456. tatic RAM write cycle out data lt 31 0 gt addr lt 27 0 gt st_cs_n lt 3 0 gt we_n byte_lane lt 3 0 gt byte_lane 3 0 as WE a WTWR 0 a WWEN 0 During a 32 bit transfer all four byte lane signals will go low During 16 bit transfer two byte lane signals will go low w During 8 bit transfer only one byte lane signal will go low Note m the PB field is set to 0 the byte lane signals will function as write enable signals and the we n signal will always be high www digiembedded com 499 TIMING Static write cycle with configurable wait states out data lt 31 0 gt addr lt 17 0 gt st_cs_n lt 3 0 gt we_n byte_lane lt 3 0 gt byte_lane 3 0 as Noted m WTWR from 0 to 15 m WWEN from 0 to 15 m The WTWR field determines the length on the write cycle mw During a 32 bit transfer all four byte lane signals will go low m During a 16 bit transfer two byte lane signals will go low a During an 8 bit transfer only one byte lane signal will go low Notes 1 Timing of the st_cs_n signal is determined with a combination of the WTWR and WWEN fields The st cs nsignal will always go low at least one clock before we n goes low and will go high one clock after we n goes high 2 Timing ofthe we n signal is determined with a combination of the WTWR and WWEN fields 3 Timing of the byte lane signals is determined with a combination of the WTWR and WWEN
457. ted and the MAC is not A060 checking the FCS because the frame is reported as having a length of 0 bytes D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 TUND Transmit Incremented for every frame less than 64 bytes with an incorrect FCS value fragment counter A060 072C D31 12 R Reset Read as 0 Reserved D11 00 R W Reset 0x000 TFRG General Statistics These are the General Statistics registers registers address map Address Register General registers R W A060_0730 Carry Register 1 R A060 0734 CAR2 Carry Register 2 R A060 0738 CAMI Carry Register 1 Mask register R W A060 073C 2 Carry Register 2 Mask register R W Carry Register 1 CAR1 and Carry Register 2 CAR2 have carry bits for all of the statistics counters These carry bits are set when the associated counter reaches a rollover condition These carry bits also can cause the STOVFL statistics counter overflow bit in the Ethernet Interrupt Status register to be set Carry Register 1 Mask register 1 and Carry Register 2 Mask register CAM2 have individual mask bits for each of the carry bits When set the mask bit preventsthe associated carry bit from setting the STOVFL bit Carry Register 1 Address A060 0730 310 Hardware Reference NS9215 ETHERNET COMMUNICATION MODULE Statistics registers
458. ted using the CS signal You can configure the master interface to address various slave interfaces using the GPIO pins Simple SPI provides simple parallel serial data conversion to stream serial data between parallel serial memory and a peripheral The SPI port has no protocol associated with it other than data conversion transferring information in multiples of 8 bits Full duplex The SPI port can operate in full duplex mode Information transfer is controlled by a operation single clock signal The clock and chip select signals are chip outputs for a master mode operation and inputs for a slave mode operation 434 Hardware Reference NS9215 SERIAL CONTROL MODULE SPI SPI clocking modes SPI clocking modes Timing modes Clocking mode diagrams www digiembedded com There are four SPI clocking modes Each mode s characteristics are defined by the idle value of the clock which clock edge captures data and which clock edge drives data The MODE field in the SPI Configuration register specifies the timing mode SPI mode SPI CLK Idle SPI DATA IN SPI DATA OUT capture edge drive edge 0 Low Rising Falling 1 High Falling Rising 2 Low Falling Rising 3 High Rising Falling The next two diagrams show the four SPI clocking modes SPI Mode0 and SPI Mode3 are the most commonly used modes SPI Mode0 and Mode3 functional timing CS 0 7 0 Capture Edge
459. tem initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode These registers are not used if the extended wait bit is enabled in the related Static Memory Configuration register 257 MEMORY CONTROLLER StaticMemory Round Delay 0 3 registers Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o Reserved WTWR Register bit assignment Bits Access Mnemonic Description D31 05 N A Reserved N A do not modify D04 00 R W WTWR Write wait states WAITWR 00000 11110 n 2 out cycle write access time The wait state time for write accesses after the first read is WAITWR 0 2 X out 11111 332 out cycle write access time reset value on reset n SRAM wait state time for write accesses after the first read StaticMemory Turn Round Delay 0 3 registers Address A070 0218 0238 0258 0278 The Static Memory Turn Round Delay 0 3 registers allow you to program the number of bus turnaround cycles It is recommended that these registers be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WTTN
460. ter General Status register Address 9006 002C The General Status register determines the status of the RTC configuration If an invalid configuration is found the RTC counters do not start operation Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VCAC VTAC VCC VTC Register bit assignment Access Mnemonic Description D31 04 N A Reserved N A N A D03 R VCAC 0 1 Valid calendar alarm configuration 0 Invalid 1 Valid D02 R VTAC 0 1 Valid time alarm configuration 0 Invalid Valid D01 R VCC Valid calendar configuration 0 Invalid 1 Valid D00 R VTC Valid time configuration 0 Invalid Valid www digiembedded com 471 REAL TIME CLOCK MODULE 472 Hardware Reference NS9215 Analog to Digital Converter ADC Module E 1 5 dos NS9215 ASIC supports a 12 bit successive approximation analog to digital converter ADC To maximize flexibility an input pin is provided to apply an external reference voltage which defines the full scale input range An analog multiplexer is included to enable the selection of up to eight inputs Features The ADC module supports these features 12 bit resolution 1 MHz conversion rate Single ended 8 1 multiplexed inputs Rail to rail input range 12 bit output either DMA or direct CPU access ADC module This diagram shows the ADC module structure structu
461. terminal count to create a clock output 11 Reserved D15 R W TE 0x0 Timer enable 0 Timer disabled 1 Timer enabled D14 12 R W Cap Comp 0x0 Capture and compare mode functions Applicable only when in 16 bit timer mode 000 Normal operation 001 Compare mode toggle output on match 010 Compare mode pulse output on match 011 Capture mode on input falling edge 100 Capture mode on input rising edge 214 rising edge 101 Capture mode on every 110 Capture mode on every 4 rising edge 111 Capture mode on every gu rising edge D11 R W Debug 0x0 Debug mode 0 Timer enabled in CPU debug mode 1 Timer disabled in CPU debug mode D10 R W Int Clr 0x0 Interrupt clear Clears the timer interrupt Software must write a 1 then a 0 to this location to clear the interrupt www digiembedded com 169 SYSTEM CONTROL MODULE Bits Access Mnemonic Reset Description D09 06 R W TCS 0x0 Timer clock select 0000 AHB clock x 2 Not applicable if timer mode 2 is set to PWM mode 01 0001 AHB clock 0010 AHB clock 2 0011 AHB clock 4 0100 AHB clock 8 0101 AHB clock 16 0110 AHB clock 32 0111 AHB clock 64 1000 AHB clock 128 1111 External event D05 04 R W Timer mode 1 0x0 Timer mode 1 00 Internal timer or external event 01 External low level gated timer 10 External high level gated timer 11 Concatenate the lower timer When either external gated option is selected the time clock select bits determine the frequency
462. terrupt condition Description Interrupt RX data FIFO overflow RX data FIFO overflowed RX For proper operation reset the receive packet processor using the ERX bit in the Ethernet General Control Register 1 when this condition occurs RX status FIFO overflow RX status overflowed RX Receive buffer closed I bit set in receive buffer descriptor and buffer closed RX Receive complete Pool Complete receive frame stored in pool A of system memory RX A Receive complete Pool Complete receive frame stored in pool of system memory RX B Receive complete Pool Complete receive frame stored in pool of system memory RX C Receive complete Pool Complete receive frame stored in pool D of system memory RX D www digiembedded com 273 ETHERNET COMMUNICATION MODULE Interrupt condition Description Interrupt No receive buffers No buffer is available for this frame because all 4 buffer rings RX disabled full or no available buffer is big enough for the frame Receive buffers full No buffer is available for this frame because all 4 buffers are RX disabled or full RX buffer ready Frame available in RX_FIFO Used for diagnostics RX Statistics counter One of the statistics counters has overflowed Individual TX overflow counters can be masked using the CAM1 and 2 registers Transmit buffer closed I bit set in Transmit buffer descriptor and buffer closed TX Tra
463. the electrical specifications or timing integral to the operation of the processor Timing includes information about DC and AC characteristics output rise and fall timing and crystal oscillator specifications Electrical characteristics Absolute maximum ratings www digiembedded com The processor operates at a 1 8V core with 3 3V I O ring voltages Permanent device damage can occur if absolute maximum ratings are ever exceeded Absolute maximum ratings are below Parameter Symbol Rating Unit DC supply voltage VDDA 0 3 to 3 9 V DC input voltage VINA 0 3 to 5 0V V DC output voltage VourA 0 3 to Vppa 0 3 V DC input current 10 mA Storage temperature 4010 125 Vma VourA Ratings of I O cells for 3 3V interface Vppc Ratings of internal cell The processor is immune to power supply sequencing problems 479 TIMING Recommended Recommended operating conditions specify voltage and temperature ranges over operating which a circuit s correct logic function is guaranteed The specified DC electrical conditions characteristics are satisfied over these ranges Below are the recommended operating conditions Parameter Symbol Rating Unit DC supply voltage VDDA 3 0 to 3 6 V Vppc core 1 62 to 1 98 V Maximum junction temperature T 125 C Vppa Ratings of I O cells for 3 3V interface Ratings of internal cells Power dissipation The table below sh
464. through and write back copyback cache operations selected by memory region using the C and B bits in the MMU translation tables caches support allocate on read miss The caches perform critical word first cache refilling 127 WORKING WITH THE CPU Write buffer Enabling the caches m Thecachesuse pseudo random or round robin replacement selected by the RR bit in R1 Control register m Cache lockdown registers enable control over which cache ways are used for allocation on a linefill providing a mechanism for both lockdown and controlling cache pollution m The DCache stores the Physical Address Tag PA tag corresponding to each DCache entry in the tag RAM for use during cache line write backs in addition to the virtual address tag stored in the tag RAM This means that the MMU is not involved in DCache write back operations which removes the possibility of TLB misses to the write back address m X Cache maintenance operations provide efficient invalidation of entire DCache or ICache J Regions of the DCache or ICache Regions of virtual memory Cache maintenance operations also provide for efficient cleaning and invalidation of entire DCache Regions of the DCache Regions of virtual memory The latter allows DCache coherency to be efficiently maintained when small code changes occur for example for self modifying code and changes to exception vectors The write buffer is use
465. tic memory default 141 SYSTEM CONTROL MODULE Address range Size System functions 0x7000 0000 Ox7FFF FFFF 256 MB System memory chip select 3 Static memory default 0x8000 0000 Ox8FFF FFFF 256 MB Reserved 0x9000 0000 Ox9FFF FFFF 256 MB IO hub 0xA000 0000 0 05 FFFF 6 MB Reserved 0xA060 0000 OxAO6F FFFF 1 MB Ethernet Communication Module 0xA070 0000 0xA07F FFFF 1 MB Memory controller 0xA080 0000 0 FFFF 1 MB External DMA module 0xA090 0000 0 09 FFFF 1 MB System Control Module 0xA0AO0 0000 OxFFFF FFFF 1526MB Reserved This table shows the hmaster 3 0 assignments for the processor Master Name hmaster 3 0 assignment 926 data 0000 Ethernet Rx 0001 Ethernet Tx 0010 IO hub 0100 ARM 926 instruction 0101 Programmable timers Software watchdog timer The processor provides 11 programmable timers m Software watchdog timer m 10 general purpose timers The software watchdog timer set to specific time intervals handles gross system misbehaviors The watchdog timer can be set to timeout in longer ranges of time intervals typically in seconds The software watchdog timer can be enabled or disabled depending on the operating condition When enabled system software must write to the Software Watchdog Timer register before it expires When the timer does timeout the system is preconfigured to generate an IRQ an FIQ or a RESET to restart the en
466. ties and a 90 degree phase shift Decode these signals to create an algorithm to determine the direction speed and position of a motion wheel Input signals 0 01 1 10 0 0 1 10 0 01 0 10 11 OF OW Counter lockwi 64 se Clockwise Quadrature Legend encoding truth NC No change table CW Clockwise CCW Counter clockwise Err Error 146 Hardware Reference NS9215 Monitors how far the encoder has moved Typical application Digital filter Testing signals Timer support www digiembedded com SYSTEM CONTROL MODULE How the quadrature decoder counter works The counter keeps a running count of how far the encoder has moved wm decoder increments a 32 bit counter when a state change is found the positive direction wm decoder decrements 32 bit counter when a state change is found in the other direction When the programmed number reaches the terminal count the counter is reset and an interrupt is generated to the CPU The CPU can also read the counter directly to sense the direction of the motor This diagram shows a typical application of the quadrature decoder counter Controller Quadrature Decoder Counter To ensure the precision and quality of the quadrature decoder counter a digital filter rejects noise on the incoming quadrature signals using three clock cycle delayed filtering The three clock
467. tion Device Write protect Page mode Buffer ROM Enabled Disabled Disabled 4 Page mode ROM Enabled Enabled Enabled Extended wait ROM Enabled Disabled Disabled SRAM Disabled or enabled 5 Disabled Disabled Page mode SRAM Disabled or enabled Enabled Enabled 4 Extended wait SRAM Disabled or enabled Disabled Disabled 4 Flash Disabled or enabled b Disabled Disabled Page mode flash Disabled or enabled h Enabled Enabled Extended wait flash Disabled or enabled b Disabled Disabled Memory mapped peripheral Disabled or enabled Disabled Disabled a Enabling the buffers means that any access causes the buffer to be used Depending on the application this can provide performance improvements Devices without async page mode support generally work better with the buffer disabled Again depending on the application this can provide performance improvements SRAM and Flash memory devices can be write protected if required Buffering must be disabled when performing Flash memory commands and during writes 207 MEMORY CONTROLLER Write protection Extended wait transfers Notes Buffering enables the transaction order to be rearranged to improve memory performance If the transaction order is important the buffers must be disabled m X Extended wait and page mode cannot be enabled at the same time Each static memory chip select can be configured for write protection SRAM us
468. tion CPU wake interrupt clear Write a 1 followed by a 0 to clear the CPU wake interrupt D19 R W Ext Int 3 0 0 External interrupt 3 interrupt wakeup 0 Do not wake on external 3 interrupt Wake on external 3 wakeup D18 Ext Int 2 0 0 External interrupt 2 interrupt wakeup 0 Do not wake on external 2 interrupt Wake on external 2 wakeup D17 Ext Int 1 0 0 External interrupt 1 interrupt wakeup 0 Do not wake on external 1 interrupt 1 Wake on external wakeup D16 R W Ext Int 0 0 0 External interrupt 0 interrupt wakeup 0 Do not wake on external 0 interrupt 1 Wake on external 0 wakeup D15 13 N A Reserved N A N A D12 RTC 0 0 wakeup 0 Do not wake RTC interrupt Wake on RTC interrupt D11 R W 0 0 DC wakeup 0 Do not wake on C activity 1 Wake on PC activity D10 06 D05 N A Reserved SPI N A 0 0 SPI wakeup 0 Do not wake on SPI activity 1 Wake on SPI activity D04 R W UARTD 0x0 UART D wakeup 0 Do not wake on character match Wake character match D03 R W UART C 0 0 wakeup 0 Do not wake on character match 1 Wake character match D02 www digiembedded com UART B 0x0 UART B wakeup 0 Do not wake on character match 1 Wake character match 189 SYSTEM CONTROL MODULE Bits Access Mnemonic Reset Description
469. tion bit 3 set to 1 and the number of channels but leave bit 31 set to a 0 474 Hardware Reference NS9215 ANALOG TO DIGITAL CONVERTER ADC MODULE ADC control and status registers 2 Set up the ADC DMA control registers and buffer descriptors UART channel D 3 Reset the ADC module by writing a 0 then a 1 to bit 8 in the Module Reset register at address A090 0180 4 Flush the ADC DMA FIFO by writing a 1 then a 0 to bit 17 in UART Channel D Wrapper Configuration register at address 9002 9000 5 Enable the ADC channel by writing 1 then a 0 to bit 31 the UART D DMA RX Control register at address 9002 8004 6 Start the ADC by writing a 1 to bit 31 the ADC Configuration register at address 9003 9000 ADC control and status registers The ADC configuration registers are located at offset 0x9003 9000 Register address map Address Description Access Reset value 9003_ 9000 ADC Configuration register R W 0x00000000 9003 9004 ADC Clock Configuration register R W 0x00000000 9003 9008 ADC Output 0 register R W 0x00000000 9003 900C ADC Output 1 register R W 0x00000000 9003 9010 ADC Output 2 register R W 0x00000000 9003 9014 ADC Output 3 register R W 0x00000000 9003 9018 ADC Output 4 register R W 0x00000000 9003 901C ADC Output 5 register R W 0x00000000 9003 9020 ADC Output 6 register R W 0x00000000 9003 9024 ADC Output 7 register R W 0x00000000 ADC Configuration register Address 9003 9000 The ADC Configuration
470. tion address octet 3 stad 23 16 D07 00 R W 0 Station address octet 4 stad 31 24 Station Address Register 3 D31 16 N A Reserved N A N A D15 08 R W OCTETS 0 Station address octet 5 stad 39 32 D07 00 R W OCTET6 0 Station address octet 46 stad 47 40 Note Octet 6 is the first byte of a frame received from the Octet 1 is the last byte of the station address received from the MAC Station Address Filter register Address A060 0500 The Station Address Filter register contains several filter controls The register is located in the station address logic see Station address logic SAL on page 264 filtering conditions are independent of each other For example the station address logic can be programmed to accept all multicast frames all broadcast frames and frames to the programmed destination address www digiembedded com 301 Register ETHERNET COMMUNICATION MODULE 31 30 29 28 27 26 25 24 23 22 21 17 Reserved 15 10 8 Reserved PRO PRM PRA BROAD Register bit assignment Bits Access Mnemonic Reset Description D31 04 N A Reserved N A N A D03 R W PRO 0 Enable promiscuous mode receive all frames D02 R W PRM 0 Accept all multicast frames 01 0 Accept multicast frames using the hash table D00 R W BROAD 0 Accept all broadcast frames RegisterHash Tables The MAC receiver
471. tire system 142 Hardware Reference NS9215 SYSTEM CONTROL MODULE General purpose timers counters General purpose timers counters Source clock frequency GPTC characteristics Control field www digiembedded com Ten 32 bit general purpose timers counters GPTC provide programmable time intervals to the CPU when used as one or multiple timers There are two 1 0 pins associated with each timer wm When used as a gated timer one 1 0 pin serves as an input qualifier high low programmable When used asa regular timer enabled by software the other I O pin serves as a terminal count indicator output These pins can also be used independently as up down counters to monitor the frequency of certain events events capturing In this situation the I O pin becomes the clock source of the counter Depending on the applications the source clock frequency of the timers counters is selectable among the system memory clock the system memory clock with multiple divisor options or an external pulse event The divisor options are 2 4 6 16 32 62 128 or 256 If an external pulse is used the frequency must be less than one half the system memory clock frequency wm Each GPTC can measure external event lengths up to minutes range and be individually enabled disabled wm Each GPTC can be configured to reload with the value defined in the Initial Timer Count register one for each GPTC and generates an interrup
472. tive Bank A to Active Bank B 0 0 0 n 1 clock cycles where the delay is cycles OxF 16 clock cycles reset on reset n Dynamic Memory Load Mode register to Active Command Time register Address A070 0058 The Dynamic Memory Load Mode register to Active Command Time register allows you to program the Load Mode register to active command time typp It is recommended that this register be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode This value normally is found in SDRAM datasheets as typp Note The Dynamic Memory Load Mode register to Active Command Time register is used for all four chip selects The worst case value for all chip selects must be programmed Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MRD Register bit assignment Bits Access Mnemonic Description D31 045 N A Reserved N A do not modify D03 00 R W MRD Load mode register to Active Command Time 0 0 0 n clock cycles where the delay is out cycles OxF 16 clock cycles reset on reset n 246 Hardware Reference NS9215 MEMORY CONTROLLER Static Memory Extended Wait register Static Memory Extended Wait register Address A070 0080 The Static Memory Extended Wait register times long static memory read and
473. tivity Note that for the 16 bit wide configuration the data bus connects to data 31 16 on the processor 32 bit wide configuration 16M device 64M device 256 512 SDRAM SDRAM device device signal signal SDRAM SDRAM signal signal 228 Hardware Reference NS9215 MEMORY CONTROLLER SDRAM address and data bus interconnect 16M device 64M device 128M 256 512 SDRAM SDRAM device device device signal signal SDRAM SDRAM SDRAM signal signal signal addr 14 12 12 12 addr 15 addr 16 addr 17 addr 18 addr 19 addr 20 addr 21 BA addr 22 BAO BAO BAO BAO addr 23 BAI BAI BAI BAI 10 data 31 0 D 31 0 D 31 0 D 31 0 D 31 0 A12 used only in 4 x 16M x 8 configurations 32 bit wide configuration 16M device 64M device 128M 256M 512M SDRAM SDRAM device device device signal signal SDRAM SDRAM SDRAM signal signal signal addr 2 AI AI AI Al Al addr 3 A2 A2 A2 A2 A2 addr 4 addr 5 4 4 4 4 4 addr 6 AS AS AS AS AS addr 7 A6 A6 A6 A6 A6 addr 8 7 7 7 7 7 addr 9 addr 10 A9 A9 A9 A9 A9 addr 11 addr 12 addr 13 AI2 A12 A12 addr 14 www digiembedded com 229 MEMORY CONTROLLER 16M device 64M device 128M 256 512 SDRAM SDRAM device device device signa
474. tor within the continuous list of descriptors The next buffer descriptor is found using the initial DMA channel buffer descriptor pointer When the W bit is not set the next buffer descriptor is found using an offset of 0 10 from the current buffer descriptor The Interrupt 1 bit when set tells the DMA controller to issue an interrupt to the CPU when the buffer is closed due to a normal channel completion The interruption occurs regardless of the normal completion interrupt enable configuration for the DMA channel The Last L bit when set tells the DMA controller that this buffer descriptor is the last descriptor that completes an entire message frame The DMA controller uses this bit to assert the normal channel completion status when the byte count reaches zero The Full F bit when set indicates that the buffer descriptor is valid and can be processed by the DMA channel The DMA channel clears this bit after completing the transfer s The DMA channel does not try a transfer with the F bit clear The DMA channel enters an idle state upon fetching a buffer descriptor with the F bit cleared Whenever the F bit is modified by the device driver the device driver must also write a 1to the CE bit in the DMA Control register to activate the idle channel Descriptor list processing www digiembedded com Once a DMA controller has completed the operation specified by the current buffer descriptor it clears the F bit and fetches the
475. ts D07 01 otherwise all 10 bits are used Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mstr Reserved Master device address addr mode 452 Hardware Reference NS9215 2 MASTER SLAVE INTERFACE Slave Address register Register bit assignment Bits Access Mnemonic Reset Description D10 01 R W MDA 0x0 Master device address Used for selecting a slave Represents bits 6 0 of the device address if using 7 bit address D10 08 are not used Represents bits 9 0 of device address if using 10 bit address D00 R W MAM 0x0 Master addressing mode 07 bit address mode 110 bit address mode Slave Address register Address 9005 0008 If using 7 bit addressing the slave device address field uses only bits D07 01 otherwise bits 10 01 are used Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Gnrl Slave Reserved call Slave device address addr addr mode Register bit assignment Bits Access Mnemonic Reset Description Dil R W GCA 0x0 General call address s irq Enable the general call address D10 01 R W SDA Ox3FF Slave device address Represents bits 6 0 of device address if using 7 bit address D10 08 are not used Represents bits 9 0 of device address if using 10 bit address D00 R W SAM 0x0 Slave addressing mode 07 bit address mode 110 bit address mode
476. tus field of a buffer descriptor which is not the last buffer descriptor in a frame has a non zero value The TX WR logic stops processing frames until TCLER clear transmit logic in Ethernet General Control Register 2 is toggled from low to high to resume processing The TX WR logic also sets TXERR last frame not transmitted successfully in the Ethernet Interrupt Status register and loads the TX buffer descriptor RAM address of the current buffer descriptor in the TX Error Buffer Descriptor Pointer register see page 320 This allows identification of the frame that was not transmitted successfully As part of the recovery procedure software must read the TX Error Buffer Descriptor Pointer register and then write the 8 bit address of the buffer descriptor to resume transmission into the TX Recover Buffer Descriptor Pointer register The RD logic is responsible for reading data from the TX FIFO and sending it to the Ethernet MAC The logic does not begin reading a new frame until the TX FIFO is full This scheme decouples the data transfer to the Ethernet MAC from the fill rate from the AHB bus For short frames that are less than 256 bytes the transmit process begins when the end of frame signal is received from the TX WR logic When the MAC completes a frame transmission it returns status bits that are stored in the Ethernet Transmit Status register see page 283 and written into the status field of the current buffer descriptor An
477. tween assertion of chip select and write enable reset value on reset n 0001 1111 1 out cycle delay where the delay is WAITWEN 1 x fo out Delay from chip select assertion to write enable Static Memory Output Enable Delay 0 3 registers Address A070 0208 0228 0248 0268 The Static Memory Output Enable Delay 0 3 registers allow you to program the delay from the chip select or address change whichever is later to the output enable assertion The Static Memory Output Enable Delay register is used in conjunction with the Static Memory Read Delay registers to control the width of the output enable signals It is recommended that these registers be modified during system initialization or when there are no current or outstanding transactions Wait until the memory controller is idle then enter low power or disabled mode Register 31 20 28 27 26 25 24 23 2 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WOEN Register bit assignment Bits Access Mnemonic Description D31 04 N A Reserved N A do not modify D03 00 R W WOEN Wait output enable WAITOEN 0000 No delay reset value on reset n 0001 1111n cycle delay where the delay is WAITOEN x teik out Delay from chip select assertion to output enable www digiembedded com 255 MEMORY CONTROLLER Static Memory Read Delay 0 3 registers Static Memory Read Delay 0 3 registers Address
478. ually is unprotected and ROM devices must be write protected to avoid potential bus conflict when performing a write access to ROM but the P field in the Static Memory Configuration register see StaticMemory Configuration 0 3 registers on page 251 can be set to write protect SRAM as well as ROM devices If a write access is made to a write protected memory bank a bus error occurs If a write access is made to a memory bank containing ROM devices and the chip select is not write protected An error is not returned and the write access proceeds as normal Note that this might lead to a bus conflict The static memory controller supports extremely long transfer times In normal use the memory transfers are timed using the Static Memory Read Delay register StaticWaitRd and Static Memory Wait Delay register StaticWaitWr These registers allow transfers with up to 32 wait states If a very slow static memory device has to be accessed however you can enable the static configuration extended wait EW bit When EW is enabled the Static Extended Wait register is used to time both the read and write transfers The Static Extended Wait register allows transfers to have up to 16368 wait states peripheral can at any time signal to the processor that it wants to complete an access early by asserting the ns ta strb signal This allows a slow peripheral with variable access times to signal that it is ready to complete an access The processor nor
479. und robin scheduler 00 100 01 7596 10 50 11 25 D03 00 R W HMSTR 0x0 hmaster Program a particular AHB bus master number here Note that a particular master an be programmed to more than one channel AHB Error Detect Status 1 Address A090 0018 www digiembedded com 159 SYSTEM CONTROL MODULE The AHB Error Detect Status 1 register records the haddr 31 0 value present when any AHB error is found Note that this value is not reset on powerup but is reset when the AHB Error Interrupt Clear bit is set in the AHB Error Monitoring Configuration register Register 31 30 2 28 27 6 2 23 2 2 20 19 18 17 16 EDSI 15 14 13 1 11 10 9 8 7 6 5 4 3 2 1 0 EDSI Register bit assignment Access D31 00 EDS1 Reset Not reset Description haddr 31 0 value recorded during a slave error response AHB Error Detect Status 2 Address A090 001C The AHB Error Detect Status 2 register records AHB master and slave values present when any AHB error is found This register also records which error condition was triggered Note that this value is not reset on powerup but is reset when the AHB Interrupt Clear bit is set in the AHB Error Monitoring Configuration register Register 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 Reserved IE DE ER er 15 14 13 41 111 9 8 7 6 5 4 3 2 1 ne H HMSTR HPR HSZ HBRST bs R 160 Har
480. upt generation whenever the transmitter moves from the active state to the idle state m In master mode this indicates that the transmit FIFO is empty and that the transmitter is not actively shifting out data m In slave mode this indicates that the externally provided chip select has been deasserted D00 R W RX IDLE 0 Enable receive idle Enables interrupt generation whenever the receiver moves from the active state to the idle state In either master or slave mode this indicates that the chip select signal has been deasserted Interrupt Status register Address 9003 1024 The Interrupt Status register provides status about SPI events events are indicated by reading a 1 and are cleared by writing a 1 442 Hardware Reference NS9215 SERIAL CONTROL MODULE SPI SPI timing characteristics Register Register bit assignment Bits Access Mnemonic Reset Description D31 02 R W Not used 0 Write this field to 0 D01 R WITC TX IDLE 0 Transmit idle Indicates that the transmitter has moved from the active state to the idle state The transmitter moves from the active state to the idle state when the transmit FIFO is empty and the transmitter is not actively shifting out data D00 R WITC RX IDLE 0 Receive idle Indicates that the receiver has moved from the active state to the idle state The receiver moves from the active state to the idle state when a start bit has not been received within 4 bit periods of the previo
481. uration register Multicast address filtering Filter entries Multicast address filter registers Multicast address filtering example 1 www digiembedded com The RX WR logic contains a programmable 8 entry multicast address filter that provides more restrictive filtering than that available in the MAC using the SAL Only multicast addresses that match those programmed into the filter will be accepted Each entry in the filter consists of a 48 bit destination address an enable bit and a 48 bit mask The mask contains a 1 in each bit position of the address that is used in the address filter this is used to extend the range of each entry Register Description MFILTL 7 0 Lower 32 bits of multicast address MFILTH 7 0 Upper 16 bits of multicast address MCMSKL Lower 32 bits of multicast address mask MCMSKH 7 0 Upper 16 bits of multicast address MFILTEN Per entry enable bits To accept only multicast packets with destination address 0x01 00 5E 00 00 00 using entry 0 the registers are set as shown Register Function MFILTEN 0 1 Enable entry 0 MFILTLO 0 5 00 00 00 Lower 32 bits of multicast address MFILTHO 0x01 00 Upper 16 bits of multicast address MCMSKLO OxFFFF FFFF Include all of the lower 32 bits of the multicast address in the comparison MCMSKHO OxFFFF Include all of the upper 16 bits of the multicast address in the comparison 275 ETHERNET COMMUNICATION MODULE
482. urth cycle will always be 11 7 Ifthe PB field is set to 0 the byte lane signal will always be high during a read cycle 8 Setting the BMODE Burst mode bit D02 in the static memory configuration register allows the static output enable signal to toggle during bursts Hardware Reference NS9215 Memory Timing Static RAM read cycle with configurable wait states out E data lt 31 0 gt 9 Eg a addr lt 27 0 gt CU M20 St cs lt 3 0 gt N M28 M23 M24 byte_lane lt 3 0 gt Note m WTRD from 1 to 15 m from 0 to 15 m Ifthe PB field is set to 1 all four byte lane signals will go low for 32 bit 16 bit and 8 bit read cycles m Ifthe PB field is set to 0 the byte lane signal will always be high www digiembedded com 497 TIMING Static RAM sequential write cycles out M15 16 data lt 31 0 gt CEDE e St cs n 3 0 M23 to M24 byte_lane lt 3 0 gt M21 M22 byte_lane 3 0 as WE ote a WTWR 0 a WWEN 0 mw During a 32 bit transfer all four byte lane signals will go low m During a 16 bit transfer two byte lane signals will go low a During an 8 bit transfer only one byte lane signal will go low Note m the PB field is set to 0 the byte lane signals will function as write enable signals and the we n signal will always be high 498 Hardware Reference NS9215 TIMING Memory Timing S
483. us bit D16 R GPIO80 Undefined GPIO 80 status bit D17 R GPIO81 Undefined GPIO 81 status bit D18 R GPIO82 Undefined GPIO 82 status bit D19 R GPIO83 Undefined GPIO 83 status bit D20 R GPIO84 Undefined GPIO 84 status bit D21 R GPIO85 Undefined GPIO 85 status bit D22 R GPIO86 Undefined GPIO 86 status bit www digiembedded com I O CONTROL MODULE Bit s Access Mnemonic Reset Description D23 R GPIO87 Undefined GPIO 87 status bit D24 R GPIO88 Undefined GPIO 88 status bit D25 R GPIO89 Undefined GPIO 89 status bit D26 R GPIO90 Undefined GPIO 90 status bit D27 R GPIO91 Undefined GPIO 91 status bit D28 R GPIO92 Undefined GPIO 92 status bit D29 R GPIO93 Undefined GPIO 93 status bit D30 R GPIO94 Undefined GPIO 94 status bit D31 R GPIO95 Undefined GPIO 95 status bit GPIO Status Address A090 2088 Register 3 5 55 Reset Description R GPIO96 Undefined GPIO 96 status bit D01 R GPIO97 Undefined GPIO 97 status bit D02 R GPIO98 Undefined GPIO 98 status bit D03 R GPIO99 Undefined GPIO 99 status bit D04 R GPIO100 Undefined GPIO 100 status bit D05 R GPIO101 Undefined GPIO 101 status bit D06 R 102 Undefined GPIO 102 status bit D07 R GPIO103 Undefined GPIO 103 status bit D08 R GPIO A0 Undefined GPIO A 0 status bit D09 R GPIO 1 Undefined GPIO status bit D10 R GPIO A2 Undefined GPIO A 2 status bit D11 R GPIO_A3 Und
484. us stop bit SPI timing characteristics These are the guaranteed timing parameters for all four SPI clocking modes SPI master timing parameters Parm Description Min Max Unit Notes 51 CS falling to CLK rising 1 clock 1 52 CLK period low time 12 13 ns 2 53 CLK period high time 12 13 ns 2 54 Data output setup to CLK rising 11 ns 3 S5 Data output hold from CLK rising 11 ns 3 S6 Data input setup to CLK rising 10 ns 4 57 Data input hold from CLK rising 0 ns 4 S8 CLK falling to CS rising 1 clock 1 59 CS deassertion time 4 clock 1 www digiembedded com 443 SERIAL CONTROL MODULE SPI SPI master timing diagram SPI slave timing parameters 444 Notes 1 Theunit clock refers to the SPI master clock 2 The SPI master interface clock duty cycle is always at least 52 48 The numbers shown here are for a 40 Mhz clock rate 3 numbers shown here for a 40 Mhz clock rate Usually this parameter is one half the SPI master interface clock period less 1 5ns 4 This parameter does not depend on the SPI master interface clock rate CS oS MDO MDI Parm Description Min Max Unit Notes S11 CS falling to CLK rising 50 ns 3 12 CLK period low time 53 80 ns 1 2 513 CLK period high time 53 80 ns 1 2 S14 Data input setup to CLK rising 10 ns 4 S15 Data input hold from CLK rising 15 ns 3 16 Data output setup to CLK rising 80 ns 2 517 Data
485. us the 4 byte header MII Management Configuration register ss Address A060 0420 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RMIIM Reserved CLKS spre Not used Register bit assignment Bits Access Mnemonic Reset Description D31 16 N A Reserved N A N A 15 RMIIM 0 Reset MII management block Set this bit to 1 to reset the MII Management module D14 05 N A Reserved N A N A www digiembedded com 295 ETHERNET COMMUNICATION MODULE m MII Management Command register Clocks field settings MII Management Command register Bits Access Mnemonic Reset Description D04 02 R W CLKS 0x0 Clock select Used by the clock divide logic in creating the MII management clock which per the IEEE 802 3u standard can be no faster than 2 5 MHz Note Some PHYs support clock rates up to 12 5 MHz The AHB bus clock is used as the input to the clock divide logic See the Clocks field settings table for settings that can be used with AHB clock hclk frequencies 01 R W SPRE 0 Suppress preamble 0 Causes normal cycles to be performed 1 Causes the Management module to perform read write cycles without the 32 bit preamble field Preamble suppression is supported by some PHYs D00 R W Not used 0 Always write to 0 CLKS field Divisor AHB bus clock for 2 5 MHz AHB bus clock for 12 5 MHz max management
486. uxiliary analog comparator input trip point 2 4 V min 2 5 max If not used terminate using a 1M to GND aux comp Note If RTC battery backup is not used the following connection changes can be made N3 M4 bat_vdd_reg tie to 1 8V 32 788kHz crystal load capacitors tie to N3 1 8V N4 bat_vdd tie to 3 3V aux comp tie to ground System mode U D OD Description M13 sys mode 2 I test mode pins M14 sys mode 1 I test mode pins L14 sys mode 0 I test mode pins www digiembedded com 45 265 sys mode 2 sys mode 1 5 5 0 Description 0 0 0 manufacturing test 0 0 1 manufacturing test 0 1 0 manufacturing test 0 1 1 normal operation boundary scan enabled POR disabled 1 0 0 normal operation boundary scan enabled POR enabled 1 0 1 board test mode all outputs tristated 1 1 0 normal operation ARM debug enabled POR disabled 1 1 1 normal operation ARM debug enabled POR enabled 46 Hardware Reference NS9215 System reset PINOUT 265 System reset www digiembedded com UD OD Description E12 reset_n U I System reset 5 reset out n 2 System reset output A13 reset done 2 Reset done D9 sreset n U I Soft system reset RESET n PLL Config Watchdog pin pin Reg Time Out Update Reset SPI YES YES YES YES BootStrapping PL YES NO NO NO Other Strappings YES NO NO NO Endianess
487. vant registers in the memory controller as well as the configuration registers in the external static memory device The data width of each external memory bank must be configured by programming the appropriate bank configuration register Static Memory Configuration 0 3 When the external memory bus is narrower that the transfer initiated from the current main bus master the internal bus transfer takes several external bus transfers to complete For example if bank 0 is configured as 8 bit wide memory and a 32 bit read is initiated the AHB bus stalls while the memory controller reads four consecutive bytes from the memory During these accesses the static memory controller block demultiplexes the four bytes into one 32 bit word on the AHB bus Each bank of the memory controller must be configured for external transfer wait states in read and write accesses Configure the banks by programming the appropriate bank control registers m StaticMemory Configuration 0 3 registers on page 251 StaticConfig n m StaticMemory Write Enable Delay 0 3 registers on page 254 StaticWaitWen n wm Static Memory Output Enable Delay 0 3 registers on 255 StaticWaitOen n m Static Memory Read Delay 0 3 registers on page 256 StaticWaitRd n m Static Memory Write Delay 0 3 registers on page 257 StaticWaitWr n m StaticMemory Page Mode Read Delay 0 3 registers on page 256 StaticWaitPage n wm StaticMemory Tur
488. w digiembedded com Tag Index Word Byte Hit WORKING WITH THE CPU Cache MVA and Set Way formats Read data 131 WORKING WITH THE CPU Cache MVA Set Way formats ARM926EJ S cache format 31 S 5 S 4 5 4 21 Tag Index Word Byte 0 1 2 3 4 5 TAG 6 7 926 7 5 The following points apply to the ARM926EJ S cache associativity ache sou m group of tags of the same index defines a set associativity m number of tags in a set is the associativity m ARM926E S caches are 4 way associative m range of tags addressed by the index defines way m The number of tagsis a way is the number of sets NSETS This table shows values of S and NSETS for an ARM926E S cache 926 5 5 NSETS 4KB 5 32 8 6 64 16 KB 7 128 32 8 256 64 KB 9 512 128 KB 10 1024 Set way word format for 35A ARM926EJ S 81 31A 9 5 9 4 5 4 21 0 caches SBZ Setselet Word 132 Index Hardware Reference NS9215 WORKING WITH THE CPU Noncachable instruction fetches In this figure A log associativity For example with a 4 way cache A 2 S logy NSETS Noncachable instruction fetches Self modifying code www digiembedded com The 926 S processor performs speculative noncachable instruction fetches to increase performance Speculative instructi
489. ware based flow control The UART module provides expanded functionality for hardware based flow control The RTS signal normally indicates the state of the receive FIFO The CTS signal normally halts the transmitter With this UART module the RI CTS DCD or DSR signals can halt the transmitter Program these features using the HWFLOW bits in the Wrapper Configuration register Character based flow control XON XOFF Traditional character based flow control requires the processor to match the flow control characters and control the transmitter accordingly This UART module performs the character matching function in hardware and automatically updates the state of the transmitter which allows character based flow control to achieve the same response time as hardware based flow control Example Configure the character based flow control using at least two Receive Character configuration Match registers and the Receive Character Based Flow Control register This table shows a sample configuration for a system transferring 8 data bits per character Control register Comment Receive Character Match Control ENABLE 1 Enable character match Regist cgister 0 MASK 0x00 Mask bits DATA 0x7e Define character Receive Character Match Control ENABLE 1 Enable character match Register 1 MASK 0x00 Mask bits DATA 0x81 Define character Receive Character Based Flow FLOWO 0 2 when matched trol ist FLOWI 0x3 XOF
490. with FCSE PID 0 A2 Fetched with FCSE PID 0 A3 Fetched with FCSE PID 1 103 WORKING WITH THE CPU A1 A2 and A3 are the three instructions following the fast context switch Context ID The Context ID register provides a mechanism that allows real time trace tools to register identify the currently executing process in multi tasking environments Access Use these instructions to access the Context ID register instructions Function Data ARM instruction Read context ID Context ID MRC p15 0 Rd c13 c0 1 Write context ID Context ID MCR p15 0 Rd c13 c0 1 Register format This is the format of the Context ID register Rd transferred during this operation 31 Context identifier R14 register Accessing reading or writing this register is reserved R15 Test and debug register Register R15 to provides device specific test and debug operations in ARM926EJ S processors Use of this register currently is reserved J azelle j ava es ARM926EJ S processor has ARM s embedded J azelle J acceleration hardware in the core J ava offers rapid application development to software engineers 926 S processor core executes an extended ARMv5TE instruction set which includes support for J ava byte code execution ARMv5TE ARM optimized J ava Virtual Machine J VM software layer has been written to work with the J azelle hardware ava byte code acceleration is accom
491. y During these accesses the memory controller block demultiplexes the two 16 bit words into one 32 bit word and places the result onto the AHB bus Word transfers are the widest transfers supported by the memory controller Any access tried with a size larger than a word generates an error response SDRAM Initialization www digiembedded com These steps show how to initialize an external SDRAM device 1 Wait 100 ms after powerup and clocks have stabilized 2 Setthe SDRAMInit value in the Dynamic Control register to 11 Issue SDRAM NOP command 3 Wait 200 ms 4 Set the SDRAMInit value in the Dynamic Control register to 10 Issue SDRAM PALL precharge all command This precharges all banks and places the SDRAM device into the all banks idle state 5 Force frequent refresh cycles by writing a 1 to the Dynamic Refresh register This provides a memory refresh every 16 memory clock cycles 6 Wait until eight SDRAM refresh cycles have occurred 128 memory clock cycles 7 Program the appropriate operational value to the Dynamic Refresh register 8 Program the appropriate operational value to the Dynamic Ras and Cas N regis ter 9 Program the appropriate operational value to the Dynamic Configuration N regis ter with the exception of the buffer enable bit which must be set to 0 during initialization 225 Left shift value table 32 bit wide data bus SDRAM RBC MEMORY CONTROLLER 10 1 12 13 Set the SDR
492. y configured system bit 2 Parity error bit 1 Framing error bit 0 Break condition Hardware Reference NS9215 3 March 2008 HUB MODULE Transmit DMA example HDLC Bits Description 15 7 Reserved 6 5 01 HDLC frame close bits 3 0 indicate the close condition bit 4 The last byte is less than 8 bits bit 3 Receiver overflow should never occur in a properly configured system bit 2 Invalid CRC found at end of frame bit 1 Valid CRC found at end of frame bit 0 Abort condition found 11 match character found bit 4 Match character 4 bit 3 Match character 3 bit 2 Match character 2 bit 1 Match character 1 bit 0 Match character 0 00 Other close event bit 2 Buffer gap timer expired bit 1 Software initiated buffer close SPI Not applicable Transmit DMA example 000000000000 00 000 0 0000600 0 00000000000 0 0 00000 0 0 00000 0 0 00 0 000 0 00 0 0 00 0 00000 0 0 0 0 0 After the last buffer in the data packet has been placed system memory and the buffer descriptors have been configured the data packet is ready to be transmitted The CPU configures the module DMA TX buffer descriptor pointer TXBDP see Module DMA TX Buffer Descriptor Pointer on page 381 and then sets the channel enable bit in the DMA Control register Process The DMA controller starts the process to read the buffer descriptor and buffer data from system memory using the AHB master The DMA controller foll
493. y one ofthe clk out signals is used 4 Only one of the dy cs n signals is used Hardware Reference NS9215 Memory Timing gt SDRAM burst read 16 bit pre act read lat dB d C d D d E d F out 2 M X 2 data lt 31 16 gt addr Cc 1 N 2 data mask 3 0 ras n cas n M9 we n Notes Thisis the bank and RAS address 2 This is the CAS address www digiembedded com 485 TIMING SDRAM burst read 16 bit CAS latency 2 3 dA B dC dE pre act read lat lat clk_out data lt 31 16 gt addr data_mask lt 3 0 gt dy_cs_n lt 3 0 gt ras n cas n we n Notes Thisis the bank and RAS address 2 This is the CAS address 486 Hardware Reference NS9215 Memory Timing SDRAM burst write 16 bit dk wrda C dB 1 clk out data lt 31 0 gt addr data_mask lt 3 2 gt data_mask lt 1 0 gt dy_cs_n lt 3 0 gt ras n cas n we n Notes Thisis the bank and RAS address 2 This is the CAS address www digiembedded com TIMING SDRAM burst read 32 bit prechg active re ad cas lat data A data B data C data D clk_out data lt 31 0 gt addr data_ma

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