Compaq M-LVDS Network Router User Manual
Contents
1. R13 MAP U S AYX TEXAS INSTRUMENTS Y J17 VCCO1 GNDO1 VCCO1Elo Ws A W NO 6424409B PWA EVM SN65MLVD__ _ SERIAL NO 1L VCCO GNDO1 R3 Board Layout o The top layer of the EVM contains the controlled impedance and matched length traces Figure 3 2 Top Layer Bill of Materials Board Layout and PCB Construction 3 3 Board Layout The second la a of the ipa the separ d iun These are the E s for the controlled impedan In o Figure 3 3 Second Layer The thir Hane of the EVM has the power plan alate Real the gro2. 100 Q termination resistors at each driver output receiver input and transceiver I O These allow the user to evaluate a single driver receiver or transceiver while not having to deal with a transmission line or additional I Os Jumpers are included to allow the two sections of the EVM to either share the same power and ground or be run off of independent supplies Ground shifts or common mode offsets can be introduced by the removal of these jumpers and using separate power supplies 1 2 M LVDS Standard TIA ElA 899 The M LVDS standard was created in response to a demand from the data communications community for a general purpose high speed balanced interface standard for multipoint applications The TIA ElA 644 standard defines the LVDS electrical layer characteristics used for transmitting information in point to point and multidrop architectures TIA EIA 644 does not address data transmission for multipoint architectures therefore the need for development of a new standard The standard Electrical Characteristics of Multipoint Low Voltage Differential Signaling M LVDS TIA ElA 899 specifies low voltage differential signaling drivers and receivers for data interchange across half duplex or multipoint data bus structures M LVDS is capable of operating at signaling rates up to 500 Mbps In other words when the devices are used at the nominal signaling rate the rise and fall times will be within the specified values in the standard
3. J2 The output signal is shown below measured on both J1 Figure 2 4 left picture and TP1 Figure 2 4 right picture The receiver output in both figures shows the offset zero crossing which is due to the Type 2 receiver incorporated into the SN65MLVD207 device The reduced offset from a Type 1 receiver can be seen in Figure 2 6 receiver number 2 output Measuring the output signal on J1 with a 50 Q cable terminated into 50 at the scope will attenuate the signal due to the 453 Q resistor in series with the receiver output The resistor is installed as a current limit for termination into a 50 Q load As can be seen in the traces below the magnitude of trace 2 on the left is one tenth of trace 2 on the right Measuring the signal with a high impedance probe on TP1 requires replacing R2 the 453 Q resistor with a short to reduce signal roll off Measuring the output on TP1 allows the user to see absolute signal levels out of the device Figure 2 4 Point to Point Parallel Simplex Typical Eye Pattern Data 1 2 0 E 1 0 22 V Ch2 200mVO M2 00ns Aux 2 83V C V 0 0 50 Ohm Output Termination Receiver Output Scaled 10 1 Driver Input Receiver Output Differential us Voltage 2 00V Ch2 2 00V M2 00ns Auxf 2 83V 1 00 V High Impedance Output Termination R2 Shorted The eye patterns in Figure 2 5 are parallel terminated point to point simplex data where trace 1 is the input signal applied to J2 and tr
4. LVDS standard allows for any combination of drivers receivers or transceivers up to a total of 32 on the line Figure 1 6 shows a representation of a five node multipoint configuration using transceivers Increased drive current in addition to the wider common mode input allows M LVDS parts to drive multiple receivers over longer line lengths with up to 2 V of ground noise Figure 1 6 Five Node Multipoint Circuit A two node multipoint setup see Figure 1 7 can be configured with the EVM Additional EVMs are needed for more nodes The test setup and schematic for this configuration is shown in Figure 2 3 The M LVDS Evaluation Module Configurations Figure 1 7 Two Node Multipoint Circuit 1 4 4 EVM Operation With Separate Power Supplies The EVM has been designed with independent power planes for the two devices The two devices can be powered with independent supplies or with a single supply Sending and receiving data between backplanes racks or cabinets where separate power sources may exist can have offset ground potentials between nodes Jumpers W7 8 9 and 10 tie the two separate power and ground planes together If two separate supplies are used and jumpers W7 8 9 and 10 are removed care should be taken to ensure the absolute maximum device ratings are not exceeded Keep in mind that if jumpers W7 8 9 and 10 are not removed when using separate power supplies a difference in potential between the supplies cause
5. Page 2 1 Typical Cable Test Configurations ocoooocommmmmmmnnn 2 2 2 21 Test Results ree eene a 2 5 2 1 Typical Cable Test Configurations 2 1 Typical Cable Test Configurations Each of the following test configurations is a transmission line consisting of a twisted pair cable connected on the 2 pin connectors P1 P2 or P3 Table 2 1 shows the possible configurations In addition to the different transmission topologies the EVM can also be configured to run off two or three separate power supplies as described in the previous section This would allow the user to induce a ground shift or offset between the two different drivers and receivers This setup can be used with any transmission line test Table 2 1 EVM Configuration Options Configuration Jumpers In Resistors In Resistors Out Diagram Point to point simplex transmission W1 2 7 8 9 10 R4 R5 6 7 Figure 2 1 Point to point parallel terminated simplex W1 2 7 8 9 10 R4 7 R5 6 Figure 2 2 transmission Two node multipoint transmission W1 2 3 4 7 8 9 10 R5 16 R2 4 6 7 1315 Figure 2 3 2 1 1 Point to Point Simplex Transmission 1 Connect a twisted pair cable from P1 to P2 2 Verify resistor R4 is installed 3 Remove resistors R5 R6 and R7 This properly terminates the transmission line at one end 4 Enable the driver by connecting the jumper on W2 between pin 1 and pin 2 or U1 pin 4 to Voc 5 Enable the receiver by connectin
6. Twisted Pair Cable 50 0 E B Ng 50 Q cable or Gable Ji 12 R4 7 R5 Active Voltage 100 A E 100 Probe into one E TP1 3 11 Channel of Scop Voc Terminated in PNE High Impedance gt re W1 Output Signa Active Voltage P f PUIOper Probe E 2 1 3 Two Node Multipoint Transmission Connect a twisted pair cable between P1 P2 and P3 Verify resistor R5 and R16 are installed Remove resistors R4 R6 R7 and R15 This properly terminates the transmission line at both ends Enabling the driver in a two node multipoint configuration will be a slightly more challenging task The user can either jumper enable a single driver and send all of the data on the bus through a single driver or sync the driver enable to the data and send data from each driver Enable a single driver by connecting the jumper on W4 between pin 1 and pin 2 which connects U2 pin 3 to Voc or by connecting the jumper on W2 between pin 1 and pin 2 which connects U1 pin 4 to Vcc Enable the receivers by connecting the jumpers on W1 and W3 between pin 2 and pin 3 or U1 pin 3 to GND and U2 pin 2 to GND Test Setup 2 3 Typical Cable Test Configurations Figure 2 3 Two Node Multipoint Transmission Input Signal 50 Q n able J2 9 Signal Source i Ute with 50 Q R3 10 Output TP2 0 49 9 50 Q i 50 Q cable or e di 12 Active Voltage Probe into one Channel of Scop Terminated in High Impedance Active Voltage Probe 50 Q cable or Activ
7. the traces should be mini mized to maintain common mode rejection of the receivers Differential transmission works best when both lines of the pair are kept as identical as possible Bill of Materials Board Layout and PCB Construction 3 7 PCB Construction Table 3 2 shows the layer stack up of the EVM with the defined trace widths for the controlled impedance etch runs using microstrip construction Table 3 2 EVM Layer Stack Up Differential Model Single Ended Model Material z Type d pid iro MU Spacing Impedance Impedance FR 406 mils Q x Q i E e p91 pepe 7 L pw s me ome 1 mew 0 EMEN Signal 0 5 oz start 3 8 Bill of Materials Board Layout and PCB Construction Appendix A Schematic This Appendix contains the EVM schematic A 1 wee R2 a f wi f W2 a Ri TPl Rex 499 00 na ie ae be Receiver Input gt vor 4 R4 e R5 i 13 El lt Receiver Enab Voc 100 100 a 2 Ro nu 92 m 4 DE B 4 4 4 e Reckser Nput 5 10 Driver Input D Zz DriverOutput r s R10 GND Y 00 R3 TP2
8. types of devices can be identified using the EVM schematic located in the EVM User s Guide When placing measurement probes near these devices during operation please be aware that these devices may be very warm to the touch Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2004 Texas Instruments Incorporated Preface How to Use This Manual This document contains the following chapters Y Chapter 1 The M LVDS Evaluation Module Chapter 2 Test Setup Chapter 3 Bill of Materials Board Layout and PCB Construction L Appendix A Schematic Related Documentation From Texas Instruments and Others FCC Warning Y Introduction to M LVDS SLLA108 LVDS Designer s Notes SLLAO144 Reducing EMI With Low Voltage Differential Signaling SLLAO30B d d Y Interface Circuits for TIA EIA 644 LVDS SLLAOS38B Y Transmission at 200 Mpbs in VME Card Cage Using LVDM SLLA088 j LVDS Multidrop Connections literature number SLLAO54 d SN65MLVD20x data sheets Multipoint LVDS Line Drivers and Receivers SLLS573 and SLLS558 UY Electromagnetic Compatibility Printed Circuit Board and Electronic Module Design VEC workshop Violette Engineering Corporation This equipment is intended for use in a laboratory test environment only It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pu
9. 8 493 GND xc SN65MIND202 203 205 0R 207 R7 fg P2 bn 100 100 R1 00 Jer GND DriverOutput gt R13 o o 4 453 gt gt RI 00 oe bi Tianseiver LO SE v i 213 7 ReceiverEnabb RE B 7 R15 pa R16 lt DriverEnable DE A 100 100 lt Diver Input E p GND R18 B 00 mo SN 65M LVD200 201 204 OR 206 e 15 R14 TPA 499 m Ja a7 as Y vec vcco ae a inst aie 7 J w 8 J wo W10 vec veco1 veco1 v Va v c7 Loo Les s 10uF 10uF 10uF uF ca c Le x 10uF l0uF 10uF uF M LVDS EVM SCHEMATIC She Nunber Revision T E OPTDNAL 6424409 These partsare for board testzpurmposesoniy and not installed in the final product 27Feb 2002 Sheet of C JU erata Potel database V DM 200 H VDtcsidbBy LownDenes 6
10. E ae Board Material ev A e Mu y D E MICROSTRIP STRIPLINE Stripline construction is the preferred configuration for differential signaling This configuration reduces radiated emissions from circuit board traces due to better control of the lines of flux The additional ground plane also allows for better control of impedance on the traces It can be seen from the functions and physical construction parameters that careful consideration must be given to these parameters for a robust board design For instance it is not uncommon for er to vary 10 across one board affecting skew This is a good reason to keep differential lines close Other factors to keep in mind when doing a printed circuit layout for transmission lines are as follows 1 2 2 Differences in electrical length translate into skew Careful attention to dimensions length and spacing help to insure isola tion between differential pairs Where possible use ideal interconnects point to point with no loads or branches This keeps the impedance more uniform from end to end and reduce reflections on the line Discontinuities on the line vias pads test points will m Reduce characteristic impedance m Increase the prop delay and rise time degradation E Increase signal transition time Prioritize signals and avoid turns in critical signals Turns can cause im pedance discontinuities Within a pair of traces the distance between
11. I The definition of transition time t and tf in M LVDS is the 10 to 90 levels shown in Figure 1 1 Using the maximum transition time for each of the drivers and the 0 5 ty rule results in the signaling rates shown in Table 1 1 This slew rate control differentiates M LVDS devices from LVDS TIA EIA 644A compliant devices The slower transition times available with M LVDS help to reduce higher frequency components in the transmitted signal This reduces EMI and allows longer stubs on the main transmission line For this reason it is generally better to select a driver with a specified signaling rate no greater than is required in the system Figure 1 1 M LVDS Unit Interval Definition Table 1 1 M LVDS Devices Supported by the EVM Pai nae Footprints a a f Status Mbps 100 SN75176 Type 1 SN65MLVD200AD Production 200 SN75176 Type 1 SN65MLVD201D Production 100 SN75ALS180 Type 1 SN65MLVD202AD Production 200 SN75ALS180 Type 1 SN65MLVD203D Production 100 SN75176 Type 2 SN65MLVD204AD Production 100 SN75ALS180 Type 2 SN65MLVD205AD Production 200 SN75176 Type 2 SN65MLVD206D Production 200 SN75ALS180 Type 2 SN65MLVD207D Production The M LVDS Evaluation Module M LVDS Standard TIA EIA 899 The EVM has been designed with the individual driver and receiver section SN75ALS180 footprint U1 on one half of the board and the transceiver section SN75176 footprint U2 on the other half see Figure 3 1 The EVM as delivered incorporates two
12. RU 3 4 Third Layer PME 3 4 Bottom Layet ocio in OA AO oran 3 5 Trace Configurations in Printed Circuit Boards anaana cece eee ees 3 7 Tables viii M LVDS Devices Supported by the EVM o o ococccccccccccc ete 1 2 Receiver Input Voltage Threshold Requirements 00 00 c cece e eee aes 1 4 EVM Configuration Options 000 eect nh 2 2 M LVDS EVM Bill of Materials oooooooccccccccccocconc 3 2 EVM ikayer Stack Up uso stet ratero rl Pelee p ated nie aerea 3 8 Chapter 1 The M LVDS Evaluation Module This document describes the multipoint low voltage differential signaling M LVDS evaluation module EVM used to aid designers in development and analysis of this new signaling technology The Texas Instruments SN65MLVD200A SN65MLVD201 SN65MLVD202A SN65MLVD203 SN65MLVD204A SN65MLVD205A SN65MLVD206 SN65MLVD207 series are low voltage differential line drivers and receivers complying with the M LVDS standard TIA EIA 899 The EVM kit contains the assembled printed circuit board and all of the released devices referred to in Table 1 1 Using the EVM to evaluate these devices should provide insight into the design of low voltage differential circuits The EVM board allows the designer to connect an input to one or both of the drivers and configure a point to point multidrop or multipoint data bus The EVM can be used to evaluate device parameters while acting as a guide for high frequency boar
13. The M LVDS standard defines the transition time t and tj to be 1 ns or slower into a test load Using this information combined with the requirement that the transition time not exceed 0 5 of the unit interval Ul gives a minimum unit interval of 2 ns leading to the 500 Mpbs maximum signaling rate The standard defines Type 1 and Type 2 receivers Type 1 receivers include no provisions for failsafe and have their differential input voltage thresholds near zero volts Type 2 receivers have their differential input voltage thresholds offset from zero volts to detect the absence of a voltage difference Type 1 receivers maximize the differential noise margin and are intended for the maximum signaling rate Type 2 receivers are intended for control signals slower signaling rates or where failsafe provisions are needed The bus voltage logic state definition can be seen in Table 1 2 and Figure 1 2 The M LVDS Evaluation Module 1 3 M LVDS EVM Kit Contents Table 1 2 Receiver Input Voltage Threshold Requirements Receiver Type Low High Type 1 2 4 V lt Vip lt 0 05 V 0 05 V lt Vip lt 24 V Type 2 2 4 V lt Vip lt 0 05 V 0 15 V lt Vip lt 24 V Figure 1 2 Expanded Graph of Receiver Differential Input Voltage Showing Transition Region Type 1 and Type 2 Receiver Differential Input Thresholds Type 1 Type 2 im Em Y p D IMA Transition Region VID V 1 3 M LVDS EVM Kit Contents The M LVDS EVM kit contains
14. ace 2 is the output Test Setup 2 5 Test Results signal on TP1 R2 is shorted Type 2 behavior is again observed on the SN65MLVD207 receiver output Trace three shows the differential voltage on the bus Note that the bus volt ages are nominal M LVDS levels of 1 1 Vpp due to the lower load seen by the current driver Figure 2 5 Parallel Terminated Point to Point Parallel Simplex Typical Eye Pattern Data Driver Input Receiver Output z f Differential oF Ch3 500mV Figure 2 6 represents the two node multipoint transmission eye patterns where trace 1 is the input signal applied to J2 and traces 2 and 3 are the output signals seen at TP1 and TP3 respectively with R2 and R13 shorted The offset zero crossing shows the difference between Type 2 Receiver 1 Output and Type 1 Receiver 2 Output Figure 2 6 Two Node Multipoint Typical Eye Pattern Data Driver Input Receiver 1 Output Receiver 2 Output 500 v Cha 2 00V M2 00ns Aux 4 2 83 V 2 00 V 2 6 Test Setup Chapter 3 Bill of Materials Board Layout and PCB Construction This chapter contains the bill of materials board layout of the M LVDS and describes the printed circuit board Topic Page Al Billl ofiMaterlalst dero E 3 2 3 2 Board layout ae e EISE EE 3 3 SHO E E E E AA A dde 3 6 3 3 PCB Construction 3 1 Bill of Materials 3 1 B
15. age does not exceed absolute maximum ratings of the line circuits Figure 1 3 Point to Point Simplex Circuit This configuration can also have a termination at the source and load parallel terminated thereby keeping normal M LVDS signal levels as shown in Figure 1 4 The schematic for this option is shown in Figure 2 2 Due to the increased drive current double termination can be used to improve transmission line characteristics Figure 1 4 Parallel Termination Simplex Circuit U1 The M LVDS Evaluation Module 1 5 Configurations 1 4 2 Multidrop A multidrop configuration see Figure 1 5 with two receiver nodes can be simulated with the EVM To get additional receiver nodes on the same bus requires additional EVMs M LVDS controlled driver transition times and higher signal levels help to accommodate the multiple stubs and additional loads on the bus This does not exempt good design practices which would keep stubs short to help prevent excessive signal reflections A bus line termination could be placed at both ends of the transmission line improving the signal quality by reducing return reflections to the driver This would allow the use of standard compliant TIA EIA 644A receivers on the bus in addition to M LVDS receivers Figure 1 5 Multidrop or Distributed Simplex Circuit 1 4 8 Multipoint The multipoint configuration is the primary application of the M LVDS devices and the associated standard The M
16. converter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2004 Texas Instruments Incorporated EVM IMPORTANT NOTICE Texas Instruments TI provides the enclosed product s under the following conditions This evaluation kit being sold by Tl is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use As such the goods being provided may not be complete in terms of required design marketing and or manufacturing related protective considerations including product safety measures typically found in the end product incorporating the goods As a prototype this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive Should this evaluation kit not meet the specifications indicated in the EVM User s Guide the kit may be returned within 30 days from the date of delivery for a ful
17. d layout The board allows for the connection of a 100 controlled impedance cable of varying lengths This provides the designer with a tool for evaluation and successful design of an end product Topic Page VAS TO Verve Wa oa 1 2 1 2 M LVDS Standard TIA EIA 899 LLsseue 1 3 TS ME VDS EVM KT Contents T A 1 4 147 Gonfigurations neee eee aces tas 1 5 1 5 Recommended Equipment seeeeeeeeeeeeeee 1 8 Overview 1 1 Overview The EVM comes with all the production devices in Table 1 1 The SN65MLVD201 and SN65MLVD207 are installed on the circuit board and can easily be replaced with the other devices supplied The M LVDS devices evaluated with this EVM are in the SN75ALS180 and SN75176 footprint Use of these industry standard footprints allows the designer to easily configure the parts into a simplex or half duplex data bus These are all TIA ElA 899 M LVDS standard compliant devices While initially intended for half duplex or multipoint applications M LVDS devices are not precluded from being used in a point to point or multidrop configuration In these configurations there can be a distinct advantage to the additional current drive provided by an M LVDS driver The M LVDS devices shown in Table 1 1 all include output slew rate limited drivers thus the need for different nominal signaling rates The M LVDS standard recommends the transition time not exceed 0 5 of the unit interval U
18. e Voltage Probe into one Channel of Scop Terminated in High Impedance Cable 2 4 Active Voltage Probe M S Output Signal R2 e 2 TP1 nput Signal AG E H ij R14 M TP4 e 49 9 0 R8 0 l TP3 Output E W2 Jumper X R7 100 ix Twisted Pair Cables Si P1 100 3 Jumper R6 100 R5 100 Test Setup 2 2 Test Results Test Results The test configurations described in Section 2 1 were used to simulate point to point simplex parallel terminated point to point simplex and two node multipoint The test results are shown in the following figures A Tektronix HFS9003 was used to generate input signals and a Tektronix TDS784D was used to collect the output data The EVM was populated with a SN65MLVD207D and SN65MLVD201D for U1 and U2 respectively The eye patterns were measured with the source Tektronix HFS9003 generating 215 1 PRBS NRZ data In all cases the length of the transmission line is approximately 21 inches 53 cm and adds to the propagation delay in the device This can be seen in the figures below as a time delay from input to output Figure 2 4 shows the point to point simplex transmission eye patterns Trace 1 is the driver input signal applied to
19. e product must have electronics training and observe good laboratory practice standards No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI products or services might be or are used Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2004 Texas Instruments Incorporated EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the supply voltage range of 3 V to 3 6 V Exceeding the specified supply range may cause unexpected operation and or irreversible damage to the EVM If there are questions concerning the supply range please contact a TI field representative prior to connecting the input power Applying loads outside of the specified output range may result in unintended operation and or possible permanent damage to the EVM Please consult the EVM User s Guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 125 C The EVM is designed to operate properly with certain components above 125 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transistors and current sense resistors These
20. g the jumper on W1 between pin 2 and pin 3 or U1 pin 3 to GND Figure 2 1 Point to Point Simplex Transmission Voc pa Jumper Input Signal Le W2 50 Q AN Cable Je 5 9 R7 gt R6 Signal Source 1 ul 100 Eu X with 50 Q LoT e R3 Ut Ri 100 Output TP2 49 9 Twisted Pair Cable 50 2 B a E 50 Q cable or Gable J1 12 De 7 R4 R5 Active Voltage 100 i P1 100 Probe into one 11 Channel of Scope V Terminated in x High Impedance gt e W1 Output Signa Jumper Active Voltage Probe 2 2 Test Setup Typical Cable Test Configurations 2 1 2 Point to Point Parallel Terminated Simplex Transmission 1 Connect a twisted pair cable from P1 to P2 Verify resistor R4 and R7 are installed Remove resistors R5 and R6 This properly terminates the transmission line at both ends Enable the driver by connecting the jumper on W2 between pin 1 and pin 2 or U1 pin 4 to Voc Enable the receiver by connecting the jumper on W1 between pin 2 and pin 3 or U1 pin 3 to GND Figure 2 2 Point to Point Parallel Terminated Simplex Transmission Vec Jumper Input Signal Le W2 50 Q Lad able Je 5 a 9 R7 Signal Source po 100 i ne ie with 50 Q gt R3 10 Pe Output TP2e 49 9
21. ill of Materials Table 3 1 M LVDS EVM Bill of Materials Reference C1 C2 Capacitor SMT1206 50 V 10 NM 0 01 uF C5 C6 C9 Capacitor SMT1206 16 V 10 1206YC105KAT C10 1 uF C3 C4 C7 C8 Capacitor SMT1210 10 V 10 1210ZG106ZAT2A 10 uF J11 J13 J15 Banana jack red Allied ST 351A J11 J15 J17 2 J12 J14 J16 Banana jack black Allied ST 351B J12 J16 J18 IC SMT 14P High speed 50 Q TI TSN65MLVD202AD line driver receiver SN65MLVD205AD SN65MLVD203D SN65MLVD207D IC SMT 8P High speed 50 Q TSN65MLVD200AD line driver receiver SN65MLVD204AD SN65MLVD201D SN65MLVD206D R1 R3 R12 Resistor SMT 1 4 W 1 49 9 Q CRCW121049R9F R1 R12 R14 2 R2 R13 Resistor SMT 1 4 W 1 453 Q Dae CRCW12104530F En 4 R8 R11 R17 Resistor SMT 1 4 W 1 0 0 2 CRCW12100000F R8 Rt R17 R18 R18 R4 R7 R15 Resistor SMT 1 4 W 1 100 Q m CRCW12101000F BEEN R16 DE EALA Ese EGER CAES la ERES AS bie a EA EEA t Only one will be installed 3 2 Bill of Materials Board Layout and PCB Construction 3 2 Board Layout Figure 3 1 Assembly Drawing 2347 J18 RAT GNDO1 TP4W4 W3 TP3 i VCCO1 o GNDO o 2 U2 R15 o P3 R16 R17 J9
22. ki TEXAS INSTRUMENTS Multipoint Low Voltage Differential Signaling M LVDS Evaluation Module User s Guide April 2004 High Performance Analog SLLU039B IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment Tl warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted u
23. l refund THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies TI from all claims arising from the handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES TI currently deals with a variety of customers for products and therefore our arrangement with the user is not exclusive TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Please read the EVM User s Guide and specifically the EVM Warnings and Restrictions notice in the EVM User s Guide prior to handling the product This notice contains important safety information about temperatures and voltages For further safety concerns please contact the TI application engineer Persons handling th
24. nder any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters data
25. of Materials Board Layout and PCB Construction LLuuuuus 3 1 3 1 Billot Materals Die erret a IR ern 3 2 3 2 Board Layo rarr okar GREAR EIA RR ETE I ng la I e DUE 3 3 239 POB GONSTUCUON eutanasia 3 6 A SCHON AU Ca a dd A 1 vii Figures Q Q Q qq CO DO DO DO O ONO dd ao oo OnNKRONHAAMTAWNAANDAARWND M LVDS Unit Interval Definition 0oooooccccocccccococrcnr ees 1 2 Expanded Graph of Receiver Differential Input Voltage Showing Transition Region 1 4 Point to Point Simplex Circuit leise 1 5 Parallel Termination Simplex Circuit 0060 c cece eee eee 1 5 Multidrop or Distributed Simplex Circuit 00 ects 1 6 Five Node Multipoint Circuit 0 0 ro 1 6 Two Node Multipoint Circuit 0 nett eens 1 7 EVM Configuration for Including a Ground Potential Difference Voltage Between Nodes 1 8 Point to Point Simplex Transmission ssssssesessee eee eee 2 2 Point to Point Parallel Terminated Simplex Transmission 000eeeeeeeee 2 3 Two Node Multipoint Transmission ocooocccccccccco eee 2 4 Point to Point Parallel Simplex Typical Eye Pattern Data 00002 ee o 2 5 Parallel Terminated Point to Point Parallel Simplex Typical Eye Pattern Data 2 6 Two Node Multipoint Typical Eye Pattern Data 002 cece 2 6 Assembly Drawing 222 iaa a a ES DERE 3 3 TOP Layer 2s cheats a EEE 3 3 SECOND Layat ssa re
26. on microstrip and stripline Microstrip construction is shown in Figure 3 6 The characteristic impedance of a microstrip trace on a printed circuit board is approximated by gt 4h o TETS 55708 W 0 1 where er is the permeability of the board material h is the distance between the ground plane and the signal trace W is the trace width and t is the thickness of the trace The differential impedance for a two microstrip traces can be approximated as follows with S being the distance between two microstrip traces Z 2x Zo x 1 0 48e 999 DIFF 2 Stripline construction is also shown in Figure 3 6 the signal lines should be centered between the ground planes The characteristic impedance of a stripline trace in a printed circuit board is approximated by 2 4h Oo mx I 5 672 0 8 W 3 1 3 where er is the permeability of the board material h is the distance between the ground plane and the signal trace W is the trace width and t is the thickness of the trace The differential impedance for a two stripline traces can be approximated as follows with S being the distance between two stripline traces Zpier 2 X Zo x 1 0 374e 9 4 Note For edge coupled striplines the term 0 374 may be replaced with 0 748 for lines which are closely coupled S 12 mils or 0 3 mm Bill of Materials Board Layout and PCB Construction PCB Construction Figure 3 6 Trace Configurations in Printed Circuit Boards
27. rsuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications In which case the user at his own expense is required to take the necessary measures to correct this interference Read This First V vi Contents 1 The M LVDS Evaluation Module oooococcccccnn eee eee nn nnn 1 1 VTS QVCWIOW fii ar dade biG Atos intel del ba ha ein a aed Geer 1 2 1 2 M LVDS Standard TIA EIA 899 0 0 nn 1 3 1 38 M LVDS EVM Kit Contents sssssssssssessse e rn 1 4 1 4 Configurations spei an a a a a E E AEE T E A he 1 5 LAT Pointto Polnt eseri te a eb eter a aril etal ste eeu ERENS 1 5 1420 MUI at De enr ER ea RE tad 1 6 1 43 Multipolnt crac rie I SERRE EEEE THEE BER 1 6 1 4 4 EVM Operation With Separate Power Supplies 0ococoooom o o 1 7 1 5 Recommended Equipment vsede sawarsa a R eens 1 8 2 estSetup 2 222 29 1 01 3040210 IA CUL LI Ies 2 1 2 1 Typical Cable Test Configurations 0oocoooccccocncncnnc eh 2 2 2 1 1 Point to Point Simplex Transmission ssslleeelessleeeeees 2 2 2 1 2 Point to Point Parallel Terminated Simplex Transmission 2 3 2 1 8 Two Node Multipoint Transmission 00 0 cee eee ee eee 2 3 2d TESHIROSUNS ceric acs fede ede dae ned lili cle ved at ore pled a Be 2 5 3 Bill
28. s a current to flow between supplies and through the jumpers The EVM can be configured with three power supplies with isolated outputs in such a way as to input a fixed offset between the grounds see Figure 1 8 This induces a ground potential difference voltage between U1 and U2 To demonstrate this capability the following steps should be followed Adjust PS1 and PS3 to the supply voltage 3 3 V and current limit to 50 mA Y Set PS2to0V Induce a ground offset by varying the output of PS2 PS2 Output The PS2 output should not exceed 2 V to remain within the device ratings The M LVDS Evaluation Module 1 7 Recommended Equipment Figure 1 8 EVM Configuration for Including a Ground Potential Difference Voltage Between Nodes Jumpers removed from W7 W8 W9 W10 1 5 Recommended Equipment a a 3 3 Vdc at 0 5 A power supply or multiple power supplies with both devices powered and enabled the board draws about 35 mA A 100 transmission medium from the driver to the receiver twisted pair cable recommended CAT5 cable for example A function or pattern generator capable of supplying 3 3 V signals at the desired signaling rate A multiple channel high bandwidth oscilloscope preferably above the 1 GHz range Differential or single ended oscilloscope probes The M LVDS Evaluation Module Chapter 2 Test Setup This chapter describes how to setup and use the M LVDS EVM Topic
29. the following B M LVDS EVM PWB with SN65MLVD201D and SN65MLVD207D installed 6424409B B Additional devices SN65MLVD200A SN65MLVD202A SN65MLVD203 SN65MLVD204A SN65MLVD205A SN65MLVD206 B M LVDS EVM kit documentation user s guide B SN65MLVD20x data sheets Multipoint LVDS Line Driver and Receiver SLLS573 and SLLS558 1 4 The M LVDS Evaluation Module Configurations 1 4 Configurations The M LVDS EVM board allows the user to construct various bus configurations The two devices on the EVM allow for point to point simplex parallel terminated point to point simplex and two node multipoint operation All of these modes of operation can be configured through onboard jumpers external cabling and different resistor combinations The devices which are delivered with the EVM change output operation but configuration of jumpers to setup the transmission type is independent of the devices installed 1 4 1 Point to Point The point to point simplex configuration is shown in Figure 1 3 The setup schematic for this option is shown in Figure 2 1 Although this is not the intended mode of operation for M LVDS it works well for high noise or long higher loss transmission lines Due to the increased drive current a single 100 Q termination resistor on the EVM will result in a differential bus voltage Vop twice as large as a doubly terminated line This practice is acceptable as long as the combination of input voltage and common mode volt
30. und planes to ses radiated emission ae ssta E while easing di e ibute a citan Figure 3 4 Third Layer YY ER T ON 8 ANO NI N Q v Q S O o O 9 9 O ON o O 9 9 ON 9 o o Q O N o o on y o S Q O OO AO OY A S Q O Q A NS 3 4 Bill of Materials Board Layout and PCB Construction Board Layout The bottom layer of the EVM contains bulk and decoupling capacitors to be placed close to the power and ground pins on the device Figure 3 5 Bottom Layer VCCO1 gt commco Cail GNDO1 00000000 00000000 Oo Bill of Materials Board Layout and PCB Construction 3 5 PCB Construction 3 3 PCB Construction 3 6 Information in this section was obtained from the following source Electromagnetic Compatibility Printed Circuit Board and Electronic Module Design VEC workshop Violette Engineering Corporation Characteristic impedance is the ratio of voltage to current in a transmission line wave traveling in one direction This characteristic impedance is the value that is matched with our termination resistors so as to reduce reflections This reduction in reflections improves signal to noise ratio on the line and reduces EMI caused by common mode voltages and spikes Two typical approaches are used for controlled impedance in printed circuit board constructi
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