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Atmel ATA6264 Power Supply User Manual

1. MSBit LSBit VR1 VR2 VR3 VR4 EXT ISO LIN Parity Lock bit Table 5 2 Initial Programming Settings 0 0 0 0 All regulators deactivated default 0 0 0 1 1 88V 3 3V 7 8V 0 0 1 0 1 88V 3 3V 9 1V 0 0 1 1 1 88V 3 3V 10 4V 0 1 0 0 2 5V 3 3V 7 8V 0 1 0 1 2 5V 3 3V 9 1V 0 1 1 0 2 5V 3 3V 10 4V 0 1 1 1 1 88V 5V 7 8V 1 0 0 0 1 88V 5V 9 1V 1 0 0 1 1 88V 5V 10 4V 1 0 1 0 2 5V 5V 7 8V 1 0 1 1 2 5V 5V 9 1V 1 1 0 0 2 5V 5V 10 4V 1 1 0 1 5V 5V 7 8V 1 1 1 0 5V 5V 9 1V 1 1 1 1 5V 5V 10 4V Set to 0 Set to 1 EXT No external transistor at VPERI default External transistor at VPERI applied Set to 0 Set to 1 ISO LIN 1509141 mode is activated at K1 default LIN mode is activated at K1 ATA6264 Preliminary 4929B AUTO 01 07 E 264 Preliminary The IP data is valid only if the parity is odd If the IP data is not valid or if the lock bit is not set the programming will not be executed Figure 5 2 Programming Sequence Contact pins RESQ RESQ2 TxD1 TxD2 SSQ MOSI SCLK VPERI K15 K30 Apply 12V at K15 K30 and5V at VPERI Set RESQ and TxD1 to GND and RESQ2 and TxD2 to 5V Transmit 5A5A h via SPI to Enable Testmode Wait until VSAT 11 7V Transmit IP command A9xx h via SPI to configure ATA6264 Wait 1 ms Remove all voltages and pinloads to get out of Test mode AMEL i 4929B AUTO 01 07
2. 264 Preliminary 20 UZP Buffer 4929B AUTO 01 07 The pin UZP is an analog output pin of the ATA6264 The UZP buffer is realized as a tristate out put with the ability to drive to VPERI as well as to GNDA The selected measurement result is given to the pin UZP as long as no new measurement is selected or the tristate command has been sent Driver capability is typically 4 mA Figure 20 1 Functional Principle of the UZP Buffer Tristate normal operating ET v 210 8 mA Voltage selected voltage from AMUX 1 Driver circuitry 470 to 20000 Driver circuitry 1 to 47 nF 2 to 8 mA GNDA Necessary for operation Operating conditions of all other supply pins Vevz Vvsar and Vycore are within functional range limits 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 AIMEL es Table 20 1 Electrical Characteristics UZP Buffer No Parameters Test Conditions Pin Symbol Min Max Unit Type Output current high side Vico OV ivi i uzp UV E 19 1 driving current with UZP connected to GND UZP luzp 8 2 mA A measurement activated Output current lovv side i i Vuze Vypeni 19 2 7 with measurement UZP connected to GND UZP luzp 2 8 mA A Measured from rising edge 19 3 Output settling time of SSQ to 90 of V zp no UZP tuzp 10
3. o Because the diagnosis commands are non latching commands any nevv serial interface com mands except watchdog triggering 6A55 and the Kx switching commands 9Cxx interrupt the diagnosis Table 22 8 IASG Commands Description 7161514131211 IASGx switched to 10V mirror factor 10 1 IASGx switched to 10V mirror factor 15 1 IASGx switched to 5V mirror factor 10 1 IASGx switched to 5V mirror factor15 1 6151413121110 Hex Code 111111110la biclO0O Ol11110 0111110 Fx33 111111110la bilclO Ol111 1111010 Fx3C T1111 1110 alblcl1 1101010 011111 FxC3 T11111110la bilcl1 11010 1111010 FxCC Note a b and c represent the IASG number in binary format only 001 IASG1 010 IASG2 011 IASG3 100 IASG4 and 101 IASG5 are valid commands Table 22 9 Example Description T1615 41312 1 IASG1 switched to 10V mirror factor 10 1 IASG5 switched to 5V mirror factor 15 1 61514131211101 Hex Code TI111111010 01110 O l11110 101111 1 F133 T T T T10111001111 11101011111010 F5CC Because the IASG commands are non latching commands any new serial interface command except watchdog triggering 6A55 and the Kx switching commands 9Cxx interrupts the IASG function AIMEL S 4929B AUTO 01 07 T AME
4. AMEL 5 3 Start up and Power down Procedure The ATA6264 is powered via the pin K30 battery voltage and via a diode or a resistor it is con nected to the ignition key line K15 In order to detect an interruption on one of these pins correctly resistors are implemented at these pins Normally the main supply pin of ATA6264 is pin K30 In the case of a missing or a too low voltage at pin K30 the whole IC is supplied from the backup power supply capacitor hooked up to pin EVZ Figure 5 3 Block Diagram Start up and Power down Procedure K15 ei K15GOOD Buz Y Vias 3V to 4 15V 40 mV to 175mV Hysteresis Comp FS K30 Serial interface O KEY LATCH Vcr L IREF lost L r1 signal e K30GOOD V Vigo 3 85V to 5V VK30 50 mV to 150 mV Hysteresis Comp EVZEN GEVZ VEVZ e CORESWAP b driver Vkao 6 1V to 8 1V ON 5V i i C 1 1 0 5V to 1V Hysteresis omp i lt 121 EVZ Vevz Vevz 7 5V to 9V ON Vevz 5 5V to 6 2V OFF EVZGOOD Comp VSAT SVSAT A VSAT Vvsat 0 9 Power sequencing Vsar 6 77V to 7 2V 200 mV to 500 mV Hysteresis ps Comp HL bi SVPER VVPERI 1 T VPERI al IP K30 4 VCP 1 T 1 ta 1 1 VCORE Iz sd K driver SVCORE A O VCP N CORE EN V VCORE VCORE Vpeni 1 25V to 1 7V VCore m 50 mV to 150 mV Hysteresis Comp driver
5. Vevz VVSAT HI Figure 1 1 Block Diagram SVSAT T T I vsar Ae Serial Interface Watchdog CP Logic VSAT Regulator VPERI Regulator 2 Y VCORE Regulator Internal Supply Reference VBATT ATA6264 Preliminary COMCOI COMCOO VvcoRE HI 4929B AUTO 01 07 X A A6264 Preliminary 1 1 Block Description 1 1 1 Integrated Boost Converter EVZ With an external n channel FET the integrated boost converter EVZ provides 3 different volt ages adjustable via the serial interface for the energy reserve and firing capacitors Two voltages are fixed values one voltage can be adjusted using an external resistive divider 1 1 2 Integrated Buck Converter VSAT The integrated buck converter VSAT is a fully integrated step down converter supplied by the boost converter EVZ and providing 7 8V 9 1V or 10 4V The user can program the voltage via an OTP system 1 1 3 Integrated Buck Converter VCORE The integrated buck converter VCORE is a fully integrated step down converter supplied either by the boost converter EVZ or by the battery and providing 1 88V 2 5V or 5V The user can program the voltage via an OTP system 1 1 4 Linear Regulator VPERI The linear regulator VPERI is supplied from the buck converter VSAT and provides an accurate voltage of 3 3V 3 or 5V 4 as a supply for sensitive elements such as sensors and ADC references wi
6. Table 10 1 Electrical Characteristics Continued VSAT Power Supply No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type Time between reaching overcurrent and reaching 9 15 Overcurrent switch on time 90 of Veygar maximum SVSAT sVSAToff 0 0 5 Hs A under on condition 9 16 Leakage current at pin SVSAT Output transistor off SVSAT Isvsat 10 10 HA A Error Amplifier Maximum output current at pin 9 17 COMSATO sinking to low COMSATO lcomsaro 200 3000 HA A Maximum output current at pin 9 18 COMSATO sourcing to high Icomsaro 165 S89 HA 9 19 77 at pin COMSATI Reomsai 9 ka A 9 20 Input offset voltage 10 10 mV D 9 21 DC open loop gain 70 dB D 9 22 Unity gain bandwidth 2 MHz D 9 23 Output voltage low Icousaro 165 HA COMSATO Veomsaro 0 0 3 V A 9 24 Output voltage high covsaro 85 HA COMSATO Vcomsato Ki GC Mur V A 9 25 Leading edge blanking time blank 150 200 ns D 9 26 Slope of artificial ramp for slope dV dt 1500 240 mV us D compensation 9 27 VSAT loss detection threshold lag 0 1 5 mA D Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter Notes 1 Depending on implementation of slope compensation sub harmonics must be prevented 2 The value of the minimum load current must be higher than the internal pull up current at pi
7. Logic and driver Overvoltage The duration of the output transistor conduction depends on the VSAT level and current feed back Conduction is suppressed immediately if the current through the output transistor exceeds 850 mA typically A logic circuit disables in the case of short spikes multiple pulse operation during one oscillating period If pin VSAT is open VSAT loss an internal current source con nected to a higher voltage than VSAT acts as pull up for this pin to prevent the VSAT voltage from rising up to EVZ In order to ensure the gate voltage for the output transistor the driver stage is supplied by the charge pump pin CP 30 ATA6264 Preliminary mmm 4929B AUTO 01 07 mmm A A6264 Preliminary Necessary for operation Operating conditions of all other supply pins Vpeni and Vcore are within functional range limits T 409C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Table 10 1 Electrical Characteristics VSAT Power Supply No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type 9 1 Vevz voltage for the buck EVZ Vevz 75 9 V A converter to start running 92 Vevz voltage for the buck EVZ Ves 55 6 2 V A converter to stop 93 Regulator switch on time via pin SVSAT 0 20 us A EVZ 9 4 Regulator switch off time via pin SVSAT 0 5 us A EVZ 9 5 Regulator switching frequency Vgyz 28V SVSAT
8. 01 07 AMEL AMEL Table 17 1 Electrical Characteristics Continued LIN ISO 9141 Interfaces No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type ISO 9141 Mode 16 23 Maximum baud rate Kx fkx 62 5 kBd A x 1 2 Propadationdela measured from TxD 16 24 Des y H to L to K 0 9 x Vigo K tepi 1 us A SE Ry 5102 to K30 Cy 470 pF to GNDB x 1 2 Propagation dela measured from TxD deeg A e nan Lto H to K x Vi K tens 1 us A x mg mg 5100 to K30 Cy 470 pF to GNDB x 1 2 measured from 0 0 1 x Vkao to 0 9 x Vicgg 16 26 K rise time Ry 5102 to K30 K krise 3 5 470 pF to GNDB x 1 2 measured from 0 9 x Vkao to 0 1 x Vy 16 27 K fall time Ry 5100 to K30 K tian 3 5 Ckx 470 pF to GNDB E x 1 2 measured from 165g RS K n x Vias to K 4 us A to RxD low 2 RxD HtoL NT x 1 2 from 16 29 5 KC high X 0 6 x Mes to K hun 4 us A xD L to H 1 2 Symmefry of transmitter Eech 16 30 deley y tsym Tx tpi fran Ky toym_tx zi 1 us A toot tkrise Symmetry of receiver x 1 2 8 bie propagation delay sym nx ppkL am e LIN Bus Mode Necessary for Operation Van 8V to 18V Measured betvveen high level 0 8 x Vkao and 16 32 7 e meing ang low level 0 2 x Vis K dV dt
9. 1 3 A g erg Ry 1 kQto K30 Dez 3 3 nF to GNDB 16 33 Maximum baud rate ta 20 kBd A Measured from TxD Propagation delay TxD low H L to K 0 9 x Vkao 16 94 to K low Ry 1 kQ to K30 kou 525 3 3 nF to GNDB Measured from TxD Propagation delay TxD high IL to H to K 0 1 x Vkao 16 35 lio K high Ry 1 kQ to K30 Ki ko UE lt A 3 3 nF to GNDB Propagation delay K low to Measured from 16 36 K 0 4 x to Ki tppkL 4 US A Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 56 RxD low RxD H toL ATA6264 Preliminary s A A6264 Preliminary Table 17 1 Electrical Characteristics Continued LIN ISO 9141 Interfaces No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type Propagation delay K high to EE 16 37 K 0 6 x Vk o to K ou 4 Hs A k s RxD LtoH Symmetry of transmitter 16 38 dele sym teow Ky lsvu 1 1 us A Symmetry of receiver 16 39 delay sym pn Ky Lee pm 1 5 LS Driver Mode 1 40 mA 1 7 16 40 K output voltage drop Io 20 mA K Vi 12 V A x 1 2 measured from 16 41 K switch on delay rising edge of SSQ to K tia 50 5 Vig 16 40V Rix 250010 K30 Cy 3 3 nF to GNDB x 1 2 measured from r
10. 5 us SSQ 2 gt 100 ns 1 gt 100 ns SCLK MOSI not defined MISO not defined 22 2 Set Commands After a reset due to the watchdog or undervoltage all internal control registers and decoded sig nals are set to their default values Table 22 2 Set of Serial Interface Commands 7 Command Latch Hex Description NOP No 0000 0 Key latch Yes 3XXX See Table 22 2 un 0 0 1 1 x x X X X X X XIXIX X X page 71 Watchdog No 6xxx Sep Tabie 22 4 an 0 1 1 0 x x X X X X X X X X X X page 71 Switch commands Yes 9xxx See Tabie 22 0n 1101011 1xlxixixixixixixixix xix page 71 nitial programming N A Axxx so Tae ae T1011101xlxixixixixixixixix xix page 72 Diagnosis No Cxxx dal 1111010 1xlxixixixixixixixix xix page 72 IASG No Fxxx SECHS 11111 1 x xixixixixixixixix xix page 73 Test mode 1 No 55AA 011101110111011111011101110110 Test mode 2 No AA55 110111011101110101110 11011011 Test mode 3 No 5500 011101110111011101010101010010 Test mode enable No 5A5A 011101111101110101110111110 110 Serial interface commands other than those listed in Table 22 2 on page 70 lead to an interrup tion of measurements via AMUX cause pin UZP to be switched to tristate and IASG sources to be deactivated The status of the latches does not change 70 ATA6264 Preliminary mmm A A6264 Preliminary Table 22 3 Key Latc
11. MOSI are ignored and do not affect the data in the serial interface register With the falling edge at pin SSQ the ATA6264 response on the previous command is latched in the ATA6264 status register and after a short delay time the signal at pin MISO is valid With the rising edge at pin SCLK the data at pin MOSI is shifted into the serial interface input register and the next bit of the status register is shifted to pin MISO A command received at pin MOSI is valid and will be executed if the number of rising edges at pin SCLK was exactly 16 during data transmission otherwise the received signal will be ignored The slave select pin SSQ allows the individual selection of different slave SPI devices Slave devices that are not selected do not interfere with SPI bus activities To ensure deactivation of the device in case of an open SSQ pin an internal current source is implemented to drive the SSQ pin to high level VPERI All commands independent of their function consist of 16 bits The serial interface includes a 16 bit input shift register 16 bit latches and a decoder logic block for the generation of the SPI command signals To suppress data transfer errors in the case of spikes or glitches on the clock signal a 16 clock cycle counter is provided Only after 16 clock cycles does the rising edge of SSQ cause an internal signal atch enable which transfers the data from the shift register to the 16 bit latch The data word is decod
12. Q100 002 ESD classification at pins connected to devices outside the ECU K1 and K2 Human body model HBM HBM 2500 V AEC Q100 002 General ESD classification for all other pins Human body model HBM HBM 1500 V AEC Q100 002 Charged device model CDM no corner CDM 500 V pins ESD STM5 3 1 1999 Charged device model CDM corner 750 V pins AMEL 7 4929B AUTO 01 07 AMEL 4 Functional Range Within the functional range the ATA6264 works as specified All voltages are referenced to the ideal ground level of an ECU connected to the GNDA GNDB and GNDD pins At the beginning of each specification table supply voltage and temperature conditions are described Table 4 1 Electrical Characteristics Functional Range No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type Voltage on pins K30 K15 E 1 1 USP 0 3 40 V 1 1a Voltage on pins K1 K2 25 40 V Rate of supply voltage rise 12 a0 K15 K1 K2 29 S 1 3 Supply voltage EVZ 0 3 40 V 1 4 Supply voltage VSAT 0 3 14 V Supply voltages VCORE E 1 5 VPERI 0 3 45 5 V 1 6 Supply voltage CP CP OUT 0 3 50 V 1 7 Voltage on digital UO pins 0 3 45 5 V Voltage on pins SVSAT E 1 8 SVCORE 1 0 440 V Voltage on pins UZP ISENS COMCOI 1 9 COMCOO COMSATO 0 3 45 5 V COMSATI COMEVZO FBEVZ IREF VINT Voltage on pins GEVZ E 1 10 OCEVZ 0 3
13. Vyperi 1 25 1 7 V A 1 88V running Vevz voltage for the VCORE Initial programming oe regulator to stop running Vycore 5V or 2 5V Vevz 2m SS ud Hysteresis at VPERI for the nitial brodram mind 11 2a VCORE regulator to stop prog 9 VPERI Vuys 50 150 mV A Vycore 1 88V running 11 3 Switch on time via pin EVZ SVCORE SVCORE 0 20 8 11 4 Switch off time via pin EVZ SVCORE tevconE 0 10 Hs A Regulator svvitching See numbers 8 1 and 8 2 ie frequency of Table 9 1 on page 27 SCORE svcone 2 11 6 Output current limit SVCORE levconE 0 7 0 9 A A 11 7 Roson of output transistor SVCORE Rsvcore 1 2 Q A Vycone Programmed 11 8 Output voltage 1 band gap tolerance VCORE Vycore1 4 5 0 4 V A included Programmed 11 9 Output voltage 2 band gap tolerance VCORE Vucong 4 2 5 4 V A included Vvcore3 Programmed 11 10 Output voltage 3 band gap tolerance VCORE 4 1 88 4 V A included Time between reaching 0 1 x Vkaomax Vvcoremin and 1141 77 transistor switch on 09 X VvcorEmin SVORE NE 150 He A 0 1 x VEyzmax VvconEmin and 0 9 x Veyzmax VvconEmin Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter Notes 1 Depending on implementation of slope compensation sub harmonics have to be prevented 2 The value of the minimum load current must be higher tha
14. are registered trade marks or trademarks of Atmel Corporation or its subsidiaries Other terms and product names may be trademarks of others 4929B AUTO 01 07
15. to 7 2V p 200 mV to 500 mV Hysteresis Comp al n enl VVPER i driver SVPER 1 Q I IP tT p n veri T gt 2 8 SVCORE Vcore Regulator O vcore d VVCORE 4929B AUTO 01 07 ATMEL 19 AMEL 7 Charge Pump To supply the VSAT and VCORE drivers an external charge pump is provided Both FETs are driven by the high charge pump voltage Vcp to ensure that they can be switched to a low ohmic state For correct function of the charge pump an external capacitor of C 47 nF has to be con nected to pin SVSAT and another of C 100 nF to pin CP A double diode has to be implemented for proper function of the charge pump An external series resistor is recom mended to suppress spikes during switching of the SVSAT The CP block is supplied by EVZ and VSAT voltage and starts to operate as soon as the thresholds for VK15 K30 and EVZ are achieved An additional start up circuitry is implemented to support the VSAT driver during the start up phase thus enabling a reliable system startup The charge pump has an output CP OUT to supply the external circuitry and can be switched via the SPI It is capable of 250 pA Figure 7 1 Block Diagram Charge Pump External circuit Status REF Serial d interface Status register Note 1 Connected to the drivers see Figure 5 3 20 ATA6264 Preliminary mmm A A6264 Preliminary Necessary for operation Operating conditions of all
16. twp as set by prescaler 15 6 Programmed watchdog cycle default 16 ms two two A Start of programmed watchdog 75 x 75 x 15 7 A window two two Max programmed window 50 x 50 x 15 8 A duration two twp Time for RESQ low after 100 15 9 watchdog timeout Missing watchdog trigger RESQ t 16 16 p A Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 52 ATA6264 Preliminary 4929B AUTO 01 07 KTAG6264 Preliminary Figure 16 5 Watchdog Trigger RESQ chip internal trigger window Serial interface communication Trg Wdg CMD re configure prescaler Trg Wdg CMD any different serial interface command Trg Wdg CMD Re configure prescaler during 1 st and 2nd trigger watchdog command AMEL 5 4929B AUTO 01 07 AMEL 17 LIN ISO 9141 Interfaces The ATA6264 includes two complete ISO 9141 interfaces Interface 1 is controlled via the pins RxD1 and TxD1 interface 2 is controlled via the pins RxD2 and TxD2 In order to support both 1509141 and LIN bus requirements interface 1 can be configured during initial programming In applications where one or both 1509141 interfaces are not needed the output transistors of K1 and K2 may be used as simple low side transistors switched on or off by the serial interface In this mode a diagnosis of the pins K1 and K2 via
17. with any voltage between the 0 3 56 V CP OUT limits Any combination of one or more pins Voltage at ECU internal pins GEVZ applied with any voltage between the 0 3 10 V OCEVZ a limits Voltage at ECU internal pins COMEVZO 00151 These voltages can be applied in an VCORE COMCOI COMCOO IREF UZP 7 e the 0 3 7 V ISENS RXD1 TXD1 RXD2 TXD2 ae i RESQ RESQ2 MISO MOSI SSQ SCLK VINT Current at logic pins od e 7577 Series si 3 3 mA maximum voltage ratings via resistor ESD classification at pins connected to devices outside the ECU K30 K15 Human body model HBM HBM 4000 V AEC Q100 002 6 ATA6264 Preliminary nIE M M 4929B AUTO 01 07 E A A6264 Preliminary 3 Absolute Maximum Ratings Continued Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability All voltages are referenced to an ideal ground level of an ECU connected to the GNDA GNDB and GNDD pins Parameters Remark Minimum Maximum Unit ESD classification at pins connected to devices outside the ECU IASG1 to IASG5 Human body model HBM HBM 3000 V AEC
18. 01 07 E A6264 Preliminary The trigger watchdog cycle can be set to the following retrigger times e A ms 8 ms 16 ms default e 32 ms 64 ms e 128 ms Cyclic phase Between two trigger commands a different SPI command must be seen by the SPI decoder Figure 16 3 Watchdog Trigger Functional Principle Successful Watchdog Trigger RESQ inactive e 1 l i tretrigger _ chip _ tretrigger ae 1 tretrigger internal p i I 1 trigger mes sien TTT 1 l 1 1 window m i 1 I 1 1 1 1 1 1 1 1 1 1 m Lu T TT i T ur bi 1 i Serial i i 7 P c em A Pn communication Ss Ss so 29 FR ER O ai Sa 3S oi 26 20 20 AIMEL an 4929B AUTO 01 07 x O AIMEL EE 1 Figure 16 4 Watchdog Trigger Functional Principle Unsuccessful Watchdog Trigger RESQ active gger t rem gger t rem GO 5pm pueuiuioo eoepnejur ees jeuonippe CER BM 4 pueululoo BuissilN awo 6pm rz oC oO LEO ooc Oe Serial interface communication o o Li inactive gger t retri gger t rem chip internal trigger window Serial interface communication iminary ATA6264 Preli 50 4929B AUTO 01 07 E A6264 Preliminary Configuration of watchdog trigger For the configuration of the watchd
19. 10 V 1 11 Voltage on pin SVPERI 0 3 6 V Voltage Voltage on pins IASGx necessary to ie x 1 to 5 drive 40 mA 40 Y stored in 20 uH Temperatures Operating ambient 40 90 C temperature range 1 14 Operating junction 40 150 C temperature range Storage ambient junction 55 105 C temperature range 1 15 Thermal resistance junction 60 K W ambient Substrate current which can 1 16 be drawn without E RR disturbances to upper defined blocks functions Type means A 10096 tested B 100 correlation tested C Characterized on samples D Design parameter Note 1 No substrate current occurs at pins K1 K2 down to V4 Vko 25 8 ATA6264 Preliminary mmm A 16264 Preliminary 4 1 Protection Against Substrate Currents Due to the fact that the ATA6264 is connected to the wiring harness and to components outside of the ECU negative voltages at the following pins might occur ASG interface IASG1 IASG2 IASG3 IASG4 IASG5 USP comparator USP If substrate currents occur it is guaranteed by design that no disturbance and malfunction of the following blocks and functions will happen No disturbance of RESET block No voltage changes of any regulators outside of their tolerances No impact on digital circuitry for example changes of latches status register etc No latch up of any circuitry AIMEL 4929B AUTO 01 07 uy 1 AMEL 5 Su
20. 110101 111111 111111 1111 9QCFF K2 interface works as 809144 interface default K2 interface works in LS driver mode 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 9900 T O 101111101011101010101111 1111 990F K2 switched to high ohmic state default K2 switched to low impedance state T OTLO 111111010101010 01010 0010 9 00 T 10101111 1101010101010111111111 9 Because the K1 and 2 interfaces are by default svvitched to ISO LIN mode the commands 9CFO 9CFF 9C00 and 9COF default to invalid commands AMEL n 4929B AUTO 01 07 72 AMEL Table 22 6 Initial Programming IP Command Description Hex Code Write data to IP register T IO 11 101110 0 1 x X X X X X X X A9xx The initial programming command is only available in Test mode For more information about the programming flow and the register contents see Section 5 2 Initial Programming of the ATA6264 on page 11 Table 22 7 Diagnosis Commands MSByte LSByte Description T1615 4 312 11 017 6151413121110 Hex Code Set UZP to tristate mode and switch off all ololo ololololo olol cooo measurements Switch Vez via AMUXto iq ololrlolt olo oltltlololol11 Cast UZP Switch Vysar via AMUX to iilololtloltlololo 1 tlololt 0l case UZP Switch 90 x
21. 18 6 Ratio Vuzp For BV UZP Ratio 2 E 2 3 A 18 6a Vycore Vuzp For Vyper gt Vycore UZP Ratio 0 995 1 A For Vypeni 5V 1 5V to 3V 6 06 3 5 A For Vypni 5V gt 3V to 25V SE 6 06 2 3 A For Vypeni 3 3V 1 5V to 3V 9 16 3 5 A 16 88 Polo Vigri Yuz For Vyperi 3 3V gt 3V to 25v YZP Ratio 9 16 2 3 A i For Vyper SV 1 5V to 3V 6 06 3 5 A 18 9 Ratio Vka Vuze For gt 3V to 25v 227 Ratio 6 06 2 3 A i For Vypeni 3 3V 1 5V to 3V 9 16 3 5 A TELL Mati M Mija For Vypeni 3 3V gt 3V to 25v H 9 16 2 3 A 18 10 Ratio Visga Vuze For Vypeni 5V UZP Ratio 10 3 A 18 10a Ratio Vias Vuzp For Vuen 3 3V UZP Ratio 14 75 3 A e For Vuen BV 1 5V to 3V R 6 04 696 18 11 Ratio 7 Vuze For Vypen 5V gt 3V to 25 227 alle 6 04 2 3 A i For Vyper 3 3V 1 5V to 3V 9 11 6 A ai Dal Vuses Vur For Vupeni 3 3V gt 3V to 25v 927 Ratio 9 11 2 3 A 18 12 RENO Mingga Vuze For Vypeni 5V gt 3V to 25V Raig 6 04 2 3 A 18 152 Ratio Visas Muze For Vyperi 3 3V gt 3V to 25v 927 Ratio 9 112 2 3 A For Vuen SV 1 5V to 3V 6 04 6 A 18 13 Ratio Vigga Vuze For Vypen gt 3V to 25v UZP Ratio 6 04 2 3 A For Vyper 3 3V 1 5V to 3V l 9 11 6 A 18 198 Rati Vissai Vuze For Vypeni 3 3V gt 3V to 25v H aka 9 11 2 3 A 18 14 Rat
22. 30 to Vkao decreasing 11 28 EVZ See number 7 4 of Table A Vycore 1 8V or 2 5V 8 2 on page 23 programmed Voltage level at K30 to switch VCORE supply from EVZ to K30 Vycore 5V programmed 11 29 Vkao increasing K30 V ao 6 1 8 1 V A Hysteresis at K30 to switch VCORE supply from K30 to EVZ Vycore SV programmed Time to switch VCORE 11 31 supply from EVZ to K30 or SVCORE tewitch 0 7 6 us D K30 to EVZ VCORE loss detection threshold Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 11 30 decreasing K30 0 5 1 V A 11 32 VCORE ls 0 1 mA D Notes 1 Depending on implementation of slope compensation sub harmonics have to be prevented 2 The value of the minimum load current must be higher than the internal pull up current at pin VCORE to ensure proper function of the regulator 38 ATA6264 Preliminary A A6264 Preliminary 13 USP Comparator for General Purpose The USP comparator is used for general purposes for example low battery detection An exter nal resistive voltage divider provides the input signal for pin USP A missing USP connection or Vusp lt 2 44V sets the status register bit b7 to low During normal operation Vu p gt 2 44V the status register bit b7 stays high Figure 13 1 Functional Principle o
23. 64 Preliminary Figure 18 1 Functional Principle of the IASG Interface Serial interface Serial interface Current mirror Serial interface Current limit if Visens gt VPERI Analog multiplexer 1 10 or Y 1 15 Risens Resistive sensor il RIASGx Necessary for operation Vycone and Vypeni gt Reset threshold Veyz 9V to 40V for operation with IASGx switched to 5V Vycone and Vyper gt Reset threshold Veyz 15V to 40V for operation with IASGx switched to 10V Co 10 pF Operating conditions of all other supply pins and Vysar are within functional range limits T 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Class 2 10 nF and 8250 Risens 2 5 kO AIMEL m 4929B AUTO 01 07 uy 1 AMEL Table 18 1 Electrical Characteristics Voltage Current Sources IASG Sources No Parameters Test Conditions Pin Symbol Min Max Unit Type x 1 to 5 17 1 Output voltage V1 40 mA las 0 5 mA IASG Viiasex 6 10 6 V A Visens 0 96 x Vyperi x 2 1 to 5 40 mA las 0 5 mA 17 2 Output voltage V2 Visens 0 96 x Vypgni IASG V2iasex 6 5 6 V A IASG switched to 5V Vgyz gt 11V x 2 1 to 5 25 mA lt lt 0 5 mA 17 2a Output voltage V2 Visens 0 96 x V pEni IASG V2usax 6 5 6 V A IASG switched to 5V Vgyz gt 9V to 11V Output v
24. 7V GEVZ Veevz M M R Driving current at pin GEVZ to 8 9 switch through the external Veevz S5V GEVZ laevz 600 80 mA A driver Gate charge delivered to the 8 10 external FET Voevz SV GEVZ Qaevz 10 nC D Gate charge delivered to the _ 8 11 external FET Veevz 10V GEVZ QeeEvz 20 nC D 8 12 Pull down resistor at pin GEVZ GEVZ Reevz 20 50 ko A Deen Of dynamic sinking 8 13 1 ansistor at GEVZ GENE Reevz x M A Voltage between pins OCEVZ 8 15 GND to detect overcurrent OCEVZ Vocevz 0 475 0 525 V A 2 8V or Veyz 28V 8 16 Maximum switch duty cycle after startup GEVZ Deevz 87 5 90 92 5 A 4V lt Vkao lt 8V or 8 17 Maximum switch duty cycle 4V lt Veyz lt 8V GEVZ Deevz 75 90 92 5 A after startup 8 18 Minimum switch duty cycle GEVZ Deevz 0 A Overvoltage at pin EVZ to switch Mouse programmed 8 19 off the regulator via external divider SE Vevz Ts gg Y A Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 27 4929B AUTO 01 07 AMEL AMEL Table 9 1 Electrical Characteristics Continued EVZ Step up Regulator No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type Overvoltage at pin EVZ to switch 8 19a off the regulator Vevzi programmed VEVZ Vevz 25 28 5 V A Overvoltage at pin EVZ to switch 8 19b off the regulator Vevz programmed VEVZ Vevz 35 39 5 V A Time between reaching over
25. ESO Vneso 0 0 4 V A 8 RESQ RESQ2 RESQ2 Visa 14 3 Reset threshold at pin VCORE is set to 5V VCORE 4 5 5 03 V A Voltage difference 14 3a Vycoge reset threshold at Vycore S set to 5V VCORE dVycone 0 17 0 7 V A VCORE see number 14 3 14 4 Reset threshold at pin VCORE is set to 2 5V VCORE 225 2 5 V A Voltage difference 14 4a Vycone reset threshold at Vvcore S set to 2 5V VCORE dVycore 0 1 0 35 V A VCORE see number 14 4 14 5 Reset threshold at pin VCORE Vycore is set to 1 88V VCORE Vvcore 1 68 1 8852 V A Voltage difference 14 5a Vycone reset threshold at Vvcore S set to 1 88V VCORE dVycone 0 07 0 275 V A VCORE see number 14 5 Overvoltage at pin Vcore to 14 6 switch off the regulator and set Vycoge is set to 5V VCORE 4 97 5 5 V A RESQ to low Voltage difference reset 14 6a threshold at VCORE see Vvcore S set to 5V VCORE dVycore 0 17 0 7 V A number 14 6 Vycore Overvoltage at pin Vcore to 14 7 switch off the regulator and set Vycore is set to 2 5V VCORE 2 5 2 8 V A RESQ to low Voltage difference reset 14 7a threshold at VCORE see Vycore S set to 2 5V VCORE dVycore 0 1 0 35 V A number 14 7 Vycore Overvoltage at pin VCORE to 14 8 switch off the regulator and set Vycoge is set to 1 88V VCORE Vvcore 1 8748 2 11 V A RESQ to low Voltage difference reset 14 8a threshold at VCORE see Vvcore S set to 1 88V VCORE
26. Features Maximum Supply Voltage 40V One Programmable Adjustable Boost Converter Two Programmable Buck Converters One Programmable Linear Regulator OTP Customer Mode 16 bit Serial Interface Two 18091441 Interfaces One Interface Programmable to LIN Functionality Watchdog Various Diagnosis Functions 5 Voltage Sources Tailored to Resistor Measurement Charge Pump Small 44 pin Package ESD Protection Against 2kV and 4kV 1 Description With the introduction of the ATA6264 Atmel introduces a new generation of airbag power supplies for future airbag systems tailored to the needs of the automotive industry It is designed in Atmel s 0 8 micron BCDMOS technology ATA6264 contains all the necessary blocks to supply the microcontroller the firing capacitors and peripheral components of the airbag system The power supply specifically fulfills the power requirements of dual voltage microcontrollers used in modern ECUs The inte grated watchdog and diagnosis blocks additionally support the safety aspects The 8 MHz 16 bit SPI enables a high communication speed Despite the high level func tionality ATA6264 comes in a space saving QFP44 package AIMEL E O Airbag Power Supply IC ATA6264 Preliminary 4929B AUTO 01 07 VBATT gt COMEVZO SVSAT COMSATO O COMSATI Q VSAT seen Q VPERI M VVPER Q SVCORE V
27. Hs A load at pin UZP Load 2 kQ 22 nF low pass filter connected to pin UZP 19 4 Output settling time measured from rising edge UZP tuzp 250 US A of SSQ to 90 of Viow pass filter out 19 5 Output resistance UZP Ruze 100 o A 19 6 Linear measurement range UZP Vuzp 0 2 ien V A V switched via AMUX Vuen 19 7 Maximum output voltage asd UZP Vuzp V A to UZP Viases 6V 50 mV 50 mV Vuzp OV to Vyper UZP 2 19 8 Output leakage current buffer in tristate mode UZP luzp 5 5 HA A 19 9 Output capacitance UZP buffer in tristate mode UZP Cuzp 0 10 pF D Measured from rising edge 19 10 Time to switch to tristate mode of SSQ to liga within UZP tuzp 3 Hs A tolerance Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 66 ATA6264 Preliminary s x Tm A 16264 Preliminary 21 Chip Temperature Measurement A serial interface command allows measuring a chip temperature dependent voltage which is generated by two diodes connected in series Three 2 diode sensors are connected in parallel and located in the following blocks VPERI VCORE and VSAT The diodes are supplied by a temperature constant current source the voltage drop of the diodes is switched via AMUX to pin UZP If the overtemperature level is exceeded bit a7 in the status register is set to 1 Necessary for operation Operating condition
28. K V 17 v A SH g P mA to 40 mA x us x 1 2 capacitance 16 8 K output capacitance between Kx and GNDB K C 10 pF D 16 9 K output current limitation 1 x 1 2 K lkx 50 100 mA A x 1 2 output driver E 16 10 K leakage current deactivated K k 10 10 HA A 16 11 RxD voltage drop high side rm RxD V Vuen V V A i x with laypx HA to 500 HA x RxDx 0 8 SE x 1 2 16 12 RxD voltage drop low side laxox mA to 1mA RxD VRxDx 0 0 4 V A RxD high side output 1 2 E z 16 13 een Van V RxD less 1 1 0 2 mA A x 1 2 16 14 RxD low side output current RxD Ipxpx 1 4 mA A Vnxpx VvrERI 16 15 RxD output rise time 7 RxD tRxDx 1 Hs A 16 16 RxD output fall time iie Pics pF SENG RxD eg 1 HS A TxD input voltage high level Vperi 5V 0 5 x Vyperi 16 17 threshold x 1 2 TAL 2221777 0 3v V A TxD input voltage high level Vperi 3 3V 0 6 x Vegni 16 18 threshold x 1 2 Te Vox Veri oav Y 16 19 TxD input voltage low level LP oe TxD Mrt 5 V A x 1 2 Vyperi 16 20 TxD input voltage hysteresis x 1 2 TXD 100 550 mv A 16 21 TxD input capacitance x 1 2 TxD Crypx 5 pF D 16 22 K thermal shutdown x 1 2 Tue 155 185 C B K thermal shutdown 16 228 teresis x 1 2 DT jie 5 25 K B Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 55 4929B AUTO
29. L 22 3 Serial Interface Status Register For all serial interface commands except the test mode commands 55AAh AA55h 5500h the ATA6264 status is available at the MISO line For the status register a 16 bit structure is used one bit for each information Table 22 10 Status Register Byte A Byte B MSBit LSBit MSBit LSBit Table 22 11 Information Provided by the Itemized Bits of the Status Register Bit Set To Information a7 High Chip temperature reports overtemperature Lovv Chip temperature reports normal temperature a6 High Overtemperature at K1 output Lovv Normal temperature at K1 output a5 High Overtemperature at K2 output Lovv Normal temperature at K2 output a4 High Latch for GKEY function is set Lovv Latch for GKEY function is not set a3 High EVZ switched to 33V EVZ switched to external divider Lovv EVZ switched to 23V a2 High CP OUT switch is low impedance Low CP OUT switch is high ohmic al High CP OUT voltage too low Low CP OUT voltage is in correct voltage range a0 High CP voltage too low Low CP voltage is in correct voltage range b7 High Voltage at pin USP above detection threshold Lovv Voltage at pin USP belovv detection threshold b6 High GNDA or GNDB disconnected Lovv GNDA and GNDB connected b5 High Previously sent serial interface command was invalid default after power on reset Low Previously sent serial interfac
30. Measurement EVZ active Autonomous mode OV Vgyz 40V Ven and Vcore gt Reset Threshold Veyz gt Vigo 2 2b Supply current at EVZ Vsar 10V Vigo lt 3 85V EVZ leyz 0 10 mA A lt 3V SVCORE and SVSAT open AMUX Measurement EVZ active OV Vsar 14V SVPERI open 2 3 Supply current at VSAT AMUX measurement VSAT active VSAT lysar 0 1 5 mA A Supply current at OV lt Noen 5 3V AMUX 7 zu VPERI measurement VPERI active VPER vega 0 2 2 2 mA 2 Supply current at OV lt Vcore 5 3V AMUX e VCORE measurement VCORE active VCORE vcore SE 1 mA Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 10 ATA6264 Preliminary E A A6264 Preliminary 5 1 Discharger Circuit Applications using the ATA6264 usually use a reverse polarity protection diode D1 in Figure 5 1 in the power supply to prevent any damage if the wrong polarity is applied to Van Unfortu nately this method includes some risk as can be seen in the following description During Standby mode lt 3V and KEYLATCH OFF the IC consumes only a low current Jean Any peaks on the supply voltage in Figure 5 1 will gradually charge the blocking capacitor C1 D1 prevents the capacitor from being discharged via the power supply and the very small quiescent current via the IC can also be neglected This means that durin
31. NO 49 ES AAA LVSAS o gt Sam IH3dA ses TE AS IH3d IH3dAS T o T T i s OOOINO N T IOOINOO O SS O YSNOO vr owsnoo 8 O Zeg mq 7130 7 b Er ZA4 zaxL d n AEE ZAZ of wq v oe ZA48 Faxi OE DEI ZN3WOO Vd dsn ISOW Shy OSIIN oem do oss oss zosau 108 ys 0538 l iminary ATA6264 Preli 78 4929B AUTO 01 07 u unu KTA6264 Preliminary 25 Ordering information Extended Type Number Package Remarks ATA6264 ALTVV P TQFP44 Tray ATA6264 ALQVV P TQFP44 Taped and reeled 26 Package Information Package P TQFP 44 acc UEDEC OUTLINE No MO 112 Dimensions in mm 12 0 2 10 0 05 0 2 Latt 0 6 0 15 HHH EXE 1 4 0 05 0 08 0 37 0 07 CL _ technical drawings according to DIN Dravving No 6 543 5131 01 4 specifications ssue 1 11 05 06 AIMEL 79 4929B AUTO 01 07 AIMEL 27 Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned not to this document Revision No e Put datasheet in a new template 4929B AUTO 01 07 e Section 23 Test Mode on page 76 changed 80 ATA6264 Preliminary E A6264 Preliminary 28 Table of Contents al a yaba ab 1 1 1000 o 0 0 1 1 1 Block Descripti
32. OO Icomcoo 200 3000 HA A Maximum output current at 11 18 ipin COMCOO sourcing to COMCOO Icomcoo 165 85 HA A high nput impedance at pin Vcore 1 88V 7 5 18 ko 11 19 COMCOL Vcore 2 5V 5V COMCO 13 27 ka 11 20 Input offset voltage 10 10 mv D 11 21 open loop gain 70 dB D 11 22 Unity gain bandwidth 2 MHz D 11 23 7 lowatpin SS COMSATO Veonsaro 0 03 V A Output voltage high at pin VINT 11 24 Gees Icoucoo 85 HA COMSATO Voomsaro 0 6 VINT V A Type means A 10096 tested B 100 correlation tested C Characterized on samples D Design parameter Notes 1 Depending on implementation of slope compensation sub harmonics have to be prevented 2 The value of the minimum load current must be higher than the internal pull up current at pin VCORE to ensure proper function of the regulator 4929B AUTO 01 07 AMEL 37 AMEL Table 12 1 Electrical Characteristics Continued VCORE Power Supply No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type 11 25 Leading edge blanking time tolank 150 200 ns D Slope of artificial ramp for slope compensation Voltage level at K30 to switch Vkao increasing VCORE supply from EVZ to See number 7 3 of Table K30 Vycore 1 8V or 2 5V 18 2 on page 23 programmed 11 26 dV dt 800 1500 mV us D 11 27 Hysteresis at K30 to svvitch VCORE supply from K
33. Reference current IREF IREF lIREF 100 4 HA A Vkao gt Vevz 13 3a Voltage at VINT Vos VK30GOOD to 5V VINT 3 35 5 47 V A 13 3b Voltage at VINT gt Vevz SV to 6V VINT Vvint 3 7 5 47 V A 13 3c Voltage at VINT gt Vevz 6V IREF Meer 4 2 5 47 V A Vevz gt 13 3d Voltage at VINT Vio OV Veyg gt 6V IREF ViREF 4 2 5 47 V A Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 40 ATA6264 Preliminary s x 4929B AUTO 01 07 TTT A6264 Preliminary 15 Reset Function Pin RESQ and Pin RESQ2 Pins RESQ and RESQ2 are low active digital outputs of the ATA6264 which provide a digital low signal in the case of a missing or incorrect watchdog transmission or in the case of improper VEVZ VPERI or VCORE voltage The voltage at pin RESQ depends on the proper voltages at pins EVZ VCORE and VPERI The RESQ signal will be set to high after a 16 ms delay as soon as the VCORE reset threshold and the VPERI reset threshold and the EVZ reset threshold signal EVZGOOD high have been reached If the watchdog circuitry does not detect a valid watchdog trigger the RESQ signal is set to low again If the watchdog was triggered successfully RESQ stays high and RESQ2 is also set to high In the case that an overvoltage at VCORE or VPERI is detected the voltages at pins RESQ and RESQ2 ar
34. SVSAT 5 200 5 kHz A 9 5a Regulator switching frequency 15 5V gt Veyz x 8V SVSAT svsar 1096 200 10 kHz A 9 6 Output current limit SVSAT levsaT 0 8 1 A A 9 7 RbDson Of output transistor SVSAT Rsvsar 1 Q A Output voltage 1 only at Band gap tolerance ET 9 8 Veen 3 3V included VSAT 1 4 7 8 4 A Vysar programmed 9 9 Output voltage 2 Band gap tolerance VSAT Vysar 496 9 1 496 V A included Vysara Programmed 9 10 Output voltage 3 Band gap tolerance VSAT Vvsara 496 10 4 4 V A included Time between reaching 9 11 Output transistor switch on time us d Vevzmax Vsvsarmin 150 ns A 0 9 x Veyzmax Vsvsarmin Time betvveen reaching 9 12 Output transistor switch on time 7 Vevzmax Vsvsarmin 150 ns A 0 1 x Veyzmax Vsvsarmin Overvoltage svvitching off the 1 1x 9 13 regulator VSAT Vysar V A Time between reaching NE overvoltage and reaching 9 14 Overvoltage switch on time 90 of Veysar maximum SVSAT tsvsatott 0 0 4 US A under on condition Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter Notes 1 Depending on implementation of slope compensation sub harmonics must be prevented 2 The value of the minimum load current must be higher than the internal pull up current at pin VSAT to ensure proper func tion of the regulator 4929B AUTO 01 07 AMEL 31 AMEL
35. T Vevz Vsar and Vcore are within functional range limits T 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Table 8 2 Electrical Characteristics GKEY Function No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type Voltage level at K15 to enable 1Vki increasing 7 1 the EVZ regulator Vkao gt BV KIS Vkis 3 Aus Y R Hysteresis at K15 to disable the 2 regulator K15 Vkis 40 175 mV A Voltage level at K30 to enable Vun increasing 73 he EVZ regulator Vias gt 4 15V Vkso 8 Y A Hysteresis at K30 to disable the 7 4 EVZ regulator K30 Vkao 50 150 mV A 7 5 Pull down resistor at K15 K15 70 365 ko A 7 6 Pull down resistor at K30 K30 Rkao 320 1700 kQ A OV Zus 40V 7 7 Current at K15 AMUX measurement K15 las 0 1 1 mA A EVZ active Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 4929B AUTO 01 07 AMEL 23 AMEL 9 EVZ Step up Regulator 24 A boost converter generates the supply voltage for energy reserve and firing capacitors in the system Using a voltage divider at pin FBEVZ this voltage can be adjusted between 15V and 40V Thus high voltage charged capacitors will be used to supply the whole system during the stand alone time for example broken K30 line after a crash The step up regulator has to start
36. Vyper via e Titlo oltlo 1 0 l0 0111110 110101 casa Switch 10 x Vypgg via 7 1 1 0 0 1 0 1 0 0 0 1 1 1 0 0 0 cass Switch Wcoge via AMUXto lolo 1tltl10lololol1l cast UZP Switch Vas via AMUXto lololtlrlolololtlol cas UZP Switch V via AMUXtO 17 lilololeloltlolo 1ltlolol1lolol cass UZP Switch Viner via AMUX to iq ololsloltlololtltloldlololol caes UZP Switch Vasa via AMUX to 4 14 tlolt ololt ololtlol cage UZP Switch Vase via AMUX to ololtlol110101 cas UZP Switch Vasen AMUXto 4 4 lg lolsloldlolt ololtltlololol cass UZP Switch Viassa Via AMUX to 4 1lololololol1l CACt UZP Switch Vlases Via AMUXto 4 o lo 1 o 4 o 4 4lolo o o0 1 0 cac UZP Switch Vyse via AMUXto 4 olo 1 o 4 o t1 1 olo o1 0 O caca UZP Switch Va via AMUXto l lilololslolrlolilslololtlololol cace UZP AN lt ololt 01110 11111 0l01l0 0 11 CAEI Note 1 UZP voltage vvill be influenced by the USP voltage ATA6264 Preliminary m E 264 Preliminary Table 22 7 Diagnosis Commands Continued MSByte LSByte Description 71615 41312 1 6151413121110 HexCode 7 yur via AMUXto Las wg g e od 1 1 0 0 0 1 0 CAE2 Switch voltage at chip temperature sensor via AMUX to UZP Note 1 UZP voltage will be influenced by the USP voltage 11110101 110101 4 o o
37. arameter 28 ATA6264 Preliminary 4929B AUTO 01 07 X A 16264 Preliminary Table 9 1 Electrical Characteristics Continued EVZ Step up Regulator No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type Error Amplifier Output current at pin COMEVZO 8 32 sinking to low COMEVZO Icomevzo 0 4 3 mA A Output current at pin COMEVZO 8 33 driving to high COMEVZO lIcomevzo 1000 150 HA A 8 34 Input offset voltage 10 10 mv D 8 35 DC open loop gain 70 dB D 8 36 Unity gain bandwidth 2 MHz D Output voltage low on pin B z MEVZO P loomevzo 100 HA COMEVZO Voomevzo 0 2 V A Output voltage high on pin VINT loomevzo 100 pA COMEVZO Voowevzo o a VNT v A GNDA GNDB Disconnect 8 40 GNDA lost detection Vanna VGNDD GNDA VGNDA 0 2 0 4 V A 8 41 Delay for GNDA lost detection GNDA td 10 50 us A 8 42 GNDB lost detection VaNpB VGNDD GNDB VaNpB 0 2 0 4 V A Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter AMEL x 4929B AUTO 01 07 AMEL 10 VSAT Power Supply Figure 10 1 A stabilized VSAT supply is realized by a buck converter An external inductance is PWM switched with a frequency of 200 kHz via an internal high side DMOS power transistor The VSAT power su
38. betvveen serial 3 21 10 interface commands nodata m Hs jA 21 11 Clock frequency CLK facik 0 8 MHz AO 21 12 Pull up current VPERI SSQ Hau ssa 95 45 21 13 Pull up current VPERI SCLK Rou sek 95 45 HA A 21 14 SCLK high low time SCLK to 40 ns A9 SSQ SCLK 0 5 x 21 15 Input voltage high level MOSI Vu EE A SSQ SCLK 0 25x 21 16 Input voltage low level MOSI VL A 21 17 Input voltage hysteresis SCLK Vuys 50 250 mv A 21 18 Output voltage high level lugo 7 1 mA to mA MISO Vu Vasen V A 21 19 Output voltage low level Imiso 0 mA to 1 mA MISO VL 0 0 4 V A Output current high level driven _ 8 Output current low level sinking RB 21 21 from VPERI level Vypeni SV MISO luiso 6 45 mA A SSQ SCLK 21 22 Input capacitance MOSI Cin 10 pF D 21 23 Output capacitance Switched off condition MISO Cmiso 10 pF D 21 24 Leakage current Switched off condition MISO IMiso 10 10 HA A Number of clock cycles to be detected betvveen falling and rising edge of 550 to set error SS A signal in status register to 0 Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter Note 1 Voltage levels for serial interface timing measurements High level 0 7 x Vuen low level 0 2 x Vyperi 2 Timing specified with a 100 pF external load at pin MISO 3 System requirement 69 4929B AUTO 01 07 AMEL AMEL Figure 22 1 Timing Serial Interface 10 gt 1
39. ble the ECU via a powerless signal If the voltage at pin K15 is larger than 3V to 4 15V the charge pump and the EVZ regulator for correct EVZ function the K30 pin has to be connected to the battery will start operating If the K15 pin is open an internal pull down resistor of approximately 220 KQ discharges the pin A logical con nection between the voltage at the K15 pin a serial interface driven latch command and the K30 voltage determines the EVZ Enable signal In order to achieve the Switch Function of the GKEY function a transformer has to be used Table 8 1 Overview of the Start up Conditions Serial interface driven Latch Vias Default 0 OFF EVZ Regulator Low x x Disabled High High x Enabled High x 1 Enabled Note 1 Less than the value shown in number 7 3 of Table 8 2 on page 23 2 Greater than the value shown in number 7 3 of Table 8 2 on page 23 3 Greater than the value shown in number 7 1 of Table 8 2 on page 23 Figure 8 1 Application VVith Lovv current Svvitch GKEY Function Used VBATT i o e gt d 4 V OCEVZ EVZ Q 55 121 EVZ Vevz FBEVZ Q COMEVZO 2 ATA6264 Preliminary s 4929B AUTO 01 07 Figure 8 2 Necessary for operation 3V to 40V Veso 3 85V to 40V Operating conditions of all other supply pins ATA6264 Preliminary Application With High Current Switch GKEY Function Not Used VBAT
40. d those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability All voltages are referenced to an ideal ground level of an ECU connected to the GNDA GNDB and GNDD pins Parameters Remark Minimum Maximum Unit Any combination of one or more pins applied with any voltage between the Voltage at pins connected directly or limits indirectly to the car battery 0 3 45 V K30 K15 USP K30 and K15 connected via diode to Vg USP connected via minimum 5 kQ to Vg maximum reverse current 5 mA Any combination of one or more pins Voltage at pins connected directly or 1 E indirectly to the car battery K1 K2 17 with any voltage between the 25 445 V Voltage at pins connected directly or Any combination of one or more pins to indirectly to the car battery IASG1 applied with any voltage between the diie 71 45 V IASG2 IASG3 IASG4 IASG5 limits stored in 20 uH Any combination of one or more pins Voltage at ECU internal pins FBEVZ E EVZ VSAT applied with any voltage between the 0 3 45 V limits Maximum rate of change at pin VSAT 1 V us d Any combination of one or more pins voltage iECU mama po SVSAT applied vvith any voltage betvveen the 1 45 V SVCORE 5 limits Any combination of one or more pins Voltage at ECU internal pins CP applied
41. dVycone 0 07 0 275 V A number 14 8 Vycore 14 9 Reset threshold at pin VPERI Vuen is set to 5V VPERI VVPERI 4 5 4 82 V A 14 10 Reset threshold at pin VPERI Vyperi is set to 3 3V VPERI VVPERI 2 94 3 16 V A Overvoltage at pin VPERI to 14 11 set RESO to low Vupgn S set to 5V VPERI 5 2 5 51 V A Overvoltage at pin VPERI to 14 12 set RESQ to low Vuen S set to 3 3V VPERI Vyperi 3 4 3 63 V A Threshold for signal 14 13 EVZGOOD OK Vevz rising EVZ Vevz 7 5 9 V A Threshold for signal 14 14 EVZGOOD Not OK Vevz falling EVZ Vevz 5 5 6 2 V A Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 45 4929B AUTO 01 07 AMEL AMEL Table 15 2 Electrical Characteristics Continued Reset Function Pin RESQ and Pin RESQ2 No Parameters Test Conditions Pin Symbol Min Max Unit Type Delay time for RESQ and RESQ2 to switch to low after RESQ nESQ reaching the reset threshold of RESQ2 nEsQ d a9 Vevz RESQ is switched to low 14 16 Pull down current at pin RESQ Vkeso 0 4V RESQ leen 1 2 mA A 1V Vypni lt 5 5V RESQ2 is switched to low Vresa 0 4V 2 ices 1 2 mA A 1V Vypni lt 5 5V Pull down resistor at pin RESQ Rresa 14 18 RESQ RESQ2 RESQ2 Race 28 T RESQ RESQ2 are Output current high side md RESQ Lee m 7 14 19 RESQ RESQ2 switched to high RESQ G
42. e command was valid b4 High Error during last serial interface transmission default after power on reset Low No error during last serial interface transmission b3 High IC is in Test mode Low IC is in Normal mode b2 Reflects bit b2 of the watchdog prescaler b1 Reflects bit b1 of the vvatchdog prescaler bO Reflects bit bO of the watchdog prescaler 74 ATA6264 Preliminary 4929B AUTO 01 07 mmm A 16264 Preliminary 4929B AUTO 01 07 The overtemperature bits a5 a6 and a7 are latched when overtemperature is detected These bits will be reset with the next SPI command unless overtemperature still exists In the case of a reset bits b4 and b5 are not set to their default state These bits show the status before reset so that the microcontroller can detect whether or not the ATA6264 is in power up state Table 22 12 Test Command Issued via the MISO line as a Result of the Test Mode Commands Description Command MISO Answer Hex Code Test mode 1 55AA 11001110111011 10011100111011 AA55 Test mode 2 AA55 0111010110 0111011101110 55AA Test mode 3 5500 0101010101010 bicidie 1 01 Note a b d f g h represent the contents of the Initial Programming Register AIMEL AMEL 23 Test Mode For better testability of the ATA6264 a test mode is implemented This mode is activated if the pins RESQ and TxD1 are connect
43. e set to low Figure 15 1 Functional Principle of RESQ RESQ2 Vevz is above reset threshold VCORE is above reset threshold and belovv overvoltage VPERI is above reset threshold and belovv overvoltage WD logic Watchdog is triggered AIMEL e 4929B AUTO 01 07 x r AMEL Figure 15 2 Functional Principle of RESQ RESQ2 Vevzsoop A 1 1 1 1 1 1 1 1 1 t b t l 1 1 1 I 1 RESQ A i 1 16 ms 1 1 chip 1 1 1 1 internal A i trigger window 1 SPI communication S e m 5 3 l liz Es 8 52 z 82 SS pis p E E 1 z 1 1 Re configure prescaler while 1 1 st and 2nd trigger vvatchdog l command RESQ2 p t Watchdog cycle see pages 48 and 49 a ATA6264 Preliminary memm 4929B AUTO 01 07 ATA6264 Preliminary The RESQ signal results from a logical AND of the Reset signal and an OK signal from the watchdog circuitry so RESQ2 will go high after the watchdog triggers correctly RESQ and RESQ2 have to be set to low if Vyperi or Vgyz are below the specified threshold VCORE is designed as an essential supply for a microcontroller core and therefore special supervisor circuits for this regulator will affect the signals at pin RESQ and RESQ2 such that both outputs are set to low if the voltage at pin VCORE spends mo
44. ed to GND the pins RESQ2 and TxD2 are connected to VPERI and the serial interface command 5A5Ah is sent to the ATA6264 Test mode is latched as long as the ATA6264 is powered Vkao gt 4 2V to 5V and Vas gt 3V to AV In Test mode the watchdog is disabled which means that RESQ and RESQ2 depend on the voltage levels of the pins VCORE VPERI and EVZ In order to provide the programming voltage at VSAT for the ini tial programming Vysar is set to 11 7V 0 5V in Test mode if the lock bit is not set After a reset Test mode is disabled default The following serial interface commands are used for the ATA6264 supplier test E6B5 h and EGBA n Figure 23 1 Hovv to Enable Test Mode Enable testmode 5A5A h 76 ATA6264 Preliminary 4929B AUTO 01 07 X A6264 Preliminary 24 Application Circuits Figure 24 1 Overview of a Typical Airbag System K2 IASG1 to 5 K30 K15 USP IREF K1 K2 IASG1to5 RESQ2 GEVZ OCEVZ GNDB EVZ Micro FBEVZ controller COMEVZ SVSAT COMSATO COMSATI VSAT VPERI VPERIFB SVCORE VCORE COMCOI COMCOO Serial interface Firing ASIC Firing loops AMEL 4929B AUTO 01 07 Safety system monitoring TT AIMEL RG Figure 24 2 Typical Application Circuit V V AS AHOOA V 50577 SUND I A6 IVSA 1 L
45. ed to address the correct functional block Table 22 1 Electrical Characteristics Serial Interface Commands No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type 214 1 Po to SCLK rising edge SCLK tiso 100 ns A isolation 21 2 SSQ lag time SSQ tiag 100 ns A9 550 SCLK 3 21 3 Fall time MOSI i 20 ns A 21 3a Fall time 2 MISO t 20 ns A SSQ SCLK 3 21 4 Rise time MOSI 20 ns A 21 4al Rise time 2 MISO t 20 ns A 21 5 Data set up time MOSI teu 20 ns A9 21 6 Data hold time MOSI thoid 20 ns A9 Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter Note 1 Voltage levels for serial interface timing measurements High level 0 7 x Vuen low level 0 2 x Vypgn 2 Timing specified with a 100 pF external load at pin MISO 3 System requirement 68 ATA6264 Preliminary A 16264 Preliminary Table 22 1 Electrical Characteristics Continued Serial Interface Commands No Parameters Test Conditions Pin Symbol Min Typ Unit Type Time from SSQ falling edge to t Time from SCLK rising edge to t 21 8 MISO valid MISO 0 40 ns A Time from SSQ rising edge to t 21 9 MISO tristate condition Mis 2 4 i 2 No data time
46. ees 550 250 HA A Vngso Vresaz OV RESQ RESQ2 are Output current low side RESQ RESQ Lee 14 20 RESQ switched to high RESQ2 4 10 mA A Vresa Vnesae Vypeni 30 pF external capacitive RESQ tesa 14 21 Rise time RESQ RESQ2 load RESQ ee 4 0 5 30 pF external capacitive RESQ nESQ 14 22 Fall time RESQ RESQ2 load RESQ 5 0 5 us A Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 46 ATA6264 Preliminary 4929B AUTO 01 07 mmm A6264 Preliminary 16 Watchdog Function To verify the proper function of the microcontroller watchdog logic is included As the ATA6264 is powered up the RESQ2 signal stays low until the first valid watchdog trigger is detected Features Watchdog trigger has to be done via the serial interface In case of a watchdog trigger mismatch the ATA6264 is set into its default state latches MISO status etc and RESQ is set to low Watchdog has to be triggered cyclically prescaler for repetition time is set via serial interface command Default 16 ms repetition time Figure 16 1 Watchdog Trigger Functional Principle VCORE 4 5 0V 4 8V RESQ chip internal trigger vvindovv Serial interface communication Trg Wdg CMD re configure prescaler Trg Wdg CMD any different SPI CMD Trg VVdg CMD Re configure prescaler during 1 st a
47. er K30 Bandgap reference L ll Sawtooth oscillator AM i GEVZ be and o river HS PWM Error comp amp i EVZ GNDA 1 overvoltage O Q SPI Q SPI bel e o l m D m lt N COMEVZO 0 H A draft formula for calculating the EVZ voltage vvhich is programmed by the external voltage divider netvvork at pin FBEVZ is Vevz VREF X 2 57 VZ2 The pins EVZ and FBEVZ have to be shorted in applications vvithout an external divider in order to ensure a safe operation of the ATA6264 in the case of an EVZ pin fault If the voltage at pin FBEVZ is larger than the voltage at pin EVZ the ATA6264 switches the feedback path automat ically to pin FBEVZ The remaining voltage at FBEVZ causes the regulator to switch off The output of the error amplifier is compared with a periodic linear ramp of a saw tooth genera tor by the PVVM comparator A logic signal with variable pulse width is generated which controls the PVVM frequency of the external FET A maximum duty cycle is determined by the duration of the falling ramp of the savv tooth oscillator The savv tooth generator is controlled by the internal 100 kHz oscillator AIMEL 4929B AUTO 01 07 26 AMEL Figure 9 3 Functional Principle of the EVZ Regulator A Sawtooth 1 7 1 Error amp output f Vgyz on PWM output off m The output transistor conduction is suppressed
48. er than 1 1V to 1 55V the VCORE regulator has to stop working Phase4 When the voltage at the EVZ capacitor is lower than 5 5V to 6 2V VSAT is switched off Figure 5 5 Start up and Power down Procedure if Vycore Programmed to Be 1 88V Vki5 3V to 4 15V 3V to 4 15V 1 1 VaEvz l e o l 1 Vi 17 5V to 9V too low EVZ volt 17 oo low voltage 1 VSAT goes into On Mode e 5 5V to 6 2V 1 charge pump deactivated 1 1 1 t Y VVSAT 1 1 Y 6 77V to 7 2V 7V to 6 27V 1 I 1 1 i oY 1 VVPERI i 1V to 1 55V VVCORE AIMEL AMEL 6 Power Supply Sequencing Only active when initial programming sets Vycore 1 88V and Vuen 3 3V In order to meet the requirements of several dual voltage supply microcontrollers a power sequencing function is implemented The ATA6264 ensures that the voltage difference VPERI VCORE will not exceed 2 8V The voltage difference between VPERI and VCORE is monitored In error cases for example if the VCORE regulator does not start to work the difference may rise above the 2 8V threshold In this case the VPERI regulator is switched off before reaching this level and switched on again if the voltage difference drops below a hysteresis value Figure 6 1 Example for Incorrect Ramp Up VvPERI 3 3V 1 Not allovved area Vupen Vvcore gt 2 8V VVcORE Necessary for
49. est Conditions Pin Symbol Min Max Unit Type lasox gt CRy x Vypeni Risen i S 17 11 7 7 77 x 1 to 5 Y 1 2 ISENSE Visense x S yvy A ISENS V VPERI Visens lt Vvperi regulator VPERI VPERI active 17 12 ISENS leakage current Visens OV to 0 96 x Vuen ISENSE liSENSE 1 6 1 6 HA A x 1 to 5 17 13 lASGx leakage current IASGx channel deactivated IASG liASGx 1 6 1 6 HA A OV lt Vevz Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 61 4929B AUTO 01 07 AMEL AMEL 19 AMUX Analog Multiplexer for Voltage Measurements Various voltages and the chip temperature inside of the ATA6264 can be measured at the ana log measurement output UZP Different voltage dividers ensure that the values of the measured voltages at UZP are in the range of OV to To select a specific measurement a serial inter face command has to be sent to the ATA6264 For the list of measurable voltages and temperatures refer to Section 22 Serial Interface Com mands on page 68 The overall accuracy of the measurement part inside the ATA6264 can be calculated using the following formula V meas V UZPoffset UZP ratio ratio tolerance Figure 19 1 AMUX Tolerances UZP A Vuzp max In order to describe the behavior of the whole measurement properly the tolerance of the volt age divider ratio ratio
50. exter nal resistor at pin IASG can be calculated using the following formulas R m Risens x Vv or IASGx 10 Visenst VisENs2 R Risens x in Vv Cox 15 Visenst x Visensz The current through pin IASG is internally limited to a value between lAsex 150 mA and 50 mA If the voltage at pin ISENS becomes higher than Vuen the voltage at pin IASG and consequently the current at pin IASG is reduced until Visens Vyperi This function can be used to reduce the current limitation of pin IASG to values lower than the internal limit by choos ing an adequate external resistor at pin ISENS In this case the maximum current through pin IASG can be calculated as V VPER lisexim 10x g l ISENS i 15 VVPERI lASGxim XR ISENS For high accuracy the IASGx current needs to be between 0 5 mA and 40 mA and the maxi mum ISENS voltage must be lt Vpgg 4096 Under a clamping condition the voltage at pin ISENS is clamped to Vpgg 5 Calculation of the resistor at pin ISENS CR1 RSENS 0 96 x Vuen x AsGmax In applications with one or more unused IASG channels the IASG pins can be used as mea surement inputs The five IASG pins are connected to the analog multiplexer block via different dividers Voltages applied to these IASG pins can be measured at the UZP pin selected via SPI commands ATA6264 Preliminary 4929B AUTO 01 07 A A62
51. f the USP Comparator to AMUX USP Status register Necessary for operation Vgyz 5 5V to 40V Ven gt reset threshold Vcore gt reset threshold Vi 3 7V to 5 47V Operating conditions of all other supply pins Vsar and Vk o are within functional range limits T 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Table 13 1 Electrical Characteristics USP Comparator for General Purpose No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type 12 1 Input current at pin USP Vusp 2 44V USP lusp 2 5 42 5 HA A 12 2 Input current at pin USP Vusp 0 to 40V USP lusp 2 5 42 5 HA A Trigger voltage for status 12 3 Threshold voltage at pin USP register bit 7 high vvith USP Vusp 2 44 5 V A increasing Vysp 12 4 De glitching time Laeglitch 20 60 us D Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 4929B AUTO 01 07 AIMEL m AMEL 14 Reference Voltage and Reference Current Generation The pin IREF is an output derived directly from the chip s internal reference voltage This refer ence source is a band gap All internally used precise voltages are derived from this band gap voltage At pin IREF a reference resistor of 12 4 KQ has to be applied providing a reference cur rent All internally used precise currents are derived from this cu
52. figuration Figure 2 1 Pinning QFP44 o o N W Q E OO BN 20908 SO zip 0922 OoOZWU0mo502000 OO oO OC Om OO OO co K15 EVZ SVSAT VSAT GNDD VINT COMSATI VCORE GNDA SVPERI VPERI Nr Oo x ANLA TEEEEPRETER Table 2 1 Pin Description Pin Symbol Function 1 USP Comparator input 2 K30 Continuous connection to the car battery 3 Ki Bus line of 1 1509141 interface 4 K2 Bus line of 279 SO9141 interface 5 lASG1 Output of voltage source 1 6 lASG2 Output of voltage source 2 7 IASG3 Output of voltage source 3 8 1 564 Output of voltage source 4 9 IASG5 Output of voltage source 5 10 ISENS Output of the current mirror from the IASGx interface 11 TXD1 Data input of the 1 1SO9141 interface 12 RESQ Reset output 13 RXD2 Data output of the 2 ISO9141 interface 14 RXD1 Data output of the 19 ISO9141 interface 15 TXD2 Data input of the 2 ISO9141 interface 16 MISO Data output of the serial interface 17 SSQ Chip select of the serial interface 18 SCLK Clock input of the serial interface 19 MOSI Data input of the serial Interface 20 RESQ2 Redundant reset output 21 IREF Connection for the external reference resistor 22 UZP Analog measurement output 4 ATA6264 Preliminary umm 4929B AUTO 01 07 Ts A6264 Preliminary Table 2 1 Pin Description Pin Symbol Function 23 VPERI I
53. g long peri ods of Standby mode the IC s supply voltage could increase continuously until finally the maximum supply voltage limit would be exceeded and the IC could be damaged ATA6264 therefore features a discharger circuit which avoids such unwanted effects If Vig exceeds a threshold value of approximately 26 8V the blocking capacitor is discharged via an integrated resistor until Vko again falls below the threshold Figure 5 1 Discharger Circuit D1 K30 8 kQ RI VBatt VPulse 26 8V 5 2 Initial Programming of the ATA6264 4929B AUTO 01 07 The ATA6264 supports different output voltages at the VSAT VPERI and the VCORE regula tors In addition different modes at the I809141 interfaces can be adjusted at the initial programming IP The memory cells are one time programmable OTP and cannot be changed after the IP default values are 0 In general the IP is done after mounting the ATA6264 on the PCB with an in circuit tester The programming voltage of 11 7V has to be applied on pin VSAT It is also possible to use the VSAT regulator as the programming voltage because VSAT is pro grammed to 11 7V x0 5V as long as the Test mode is entered and the lock bit is not set To ensure proper programming of the ATA6264 at least a 10 pF electrolytic cap and a 100 nF ceramic cap have to be applied at pin VSAT AIMEL H 12 AMEL The following settings can be made at the initial programming
54. h Commands MSByte LSByte Description 71615 4131211 6151413121110 HexCode Key latch set 0101111111111 T T 1111111 3FFF Key latch reset default O 1011 11010 OlOl0 101010 10101 010 3000 Table 22 4 VVatchdog Commands MSByte LSByte Description 71615 4131211 6151413121110 HexCode Trigger vvatchdog 01111 0 110 T 01110111011 6A55 Configure prescaler O1l111 001010 01011 1111110la bc 60Fx Table 22 5 Switch Commands MSByte LSByte Description T161514131211 615 41312 110 Hex Code Enable EVZ switching T 01011111011 111101110 9A5A EVZ switched to 33V T101011101011 1101010 0111111111 930F Ere Med In edv 110 0 1 0 0 1 1 1 1 1 1 0 0 0 0 93FO default EvZewichedioememal garbage 6p o T to 4 4 16 9396 divider CP OUT switched to high ohmic state default CP OUT switched to low impedance state 1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 960F 1 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 96F0 K1 interface works as 809141 or LIN interface depending on ISO LIN bit 11010111110101 111 111111111010 Ol0 99FO of initial programming default K1 interface works in LS driver mode T O 1011111010111 11111111 1111111 99FF K1 svvitched to high ohmic state default K1 switched to low impedance state T OTLO T 11110101 111111 111010 2010 9CFO T IO 011111
55. h Low EVZGOOD high Correctly triggered High V au g ow gt hig gt Vyper VCORE Vevz OK trigger occurred 15 time Correctly triggered High High Incorrectly triggered High gt low High gt low EVZGOOD low X Not OK X Lovv Lovv Figure 15 4 Application Example Vevz Vevz s above reset threshold VCORE is above 1 threshold and below overvoltage Microcontroller dual voltage supply 1 88V 3 3V VPERI is above VPERI reset threshold and below overvoltage Safety system monitoring microcontroller 3 3V WD logic Watchdog is triggered Necessary for operation Vevz 5 5V to 40V Ven 1V to 5 5V Vint 3 7V to 5 47V Operating conditions of all other supply pins Vsar and Vcore are within functional range limits T 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 ATA6264 Preliminary 4929B AUTO 01 07 44 X A 1 6264 Preliminary Table 15 2 Electrical Characteristics Reset Function Pin RESQ and Pin RESQ2 No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type kesq RESQ2 RESQ Vaesq Vuen 14 1 RESQ and RESQ2 high level 200 HA to HA RESQ2 Ve 08 VVPER V A 14 2 RESQ and RESQ2 lowlevel l omAto2ma R
56. immediately if the current through the povver FET exceeds a certain level determined by the voltage drop across an external resistor in the range of 0 20 The ATA6264 itself will see a voltage at the OCEVZ pin If this voltage exceeds typically 0 5V the output transistor conduction has to be suppressed The external FET also has to be switched off if a low battery voltage at K30 or overvoltage on pin EVZ is detected Multiple output pulses at pin GEVZ during one oscillator period are suppressed by internal logic In the default state for example before the minimum input voltage for starting the regulator has been reached the external transistor is switched off During startup the voltage on pin EVZ is too low and the PWM comparator requires a duty cycle of more than 90 Due to an increasing inductance current after several periods the overcur rent sensor becomes active and reduces the maximum duty cycle to improve magnetic energy transfer Figure 9 4 Output Current During Start up Output Current limit current A capacitance of 10 mF or more may be applied at pin EVZ The equivalent series resistance ESR should have a value of less than 0 5 After power on the default state of the internal dividers should always be the low EVZ voltage divider The voltage at pin GNDA is compared with the voltage at pin GNDD and if GNDA is not con nected bit b6 of the APACE status register is set Pin GNDB is also compared with p
57. in GNDD Pin GNDB not being connected will also result in bit b6 being set and additionally in the EVZ regulator being switched off ATA6264 Preliminary 4929B AUTO 01 07 mmm A A6264 Preliminary Necessary for operation Operating conditions of all other supply pins Maar Vpeni and Vcore are within functional range limits T 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Table 9 1 Electrical Characteristics EVZ Step up Regulator No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type ui 2 8V or Veyz 2 8V DES S 8 1 Switching frequency after startup GEVZ sevz 5 100 5 kHz A AV lt Vkao lt 8V or 8 2 Switching frequency 4V Vgyz 8V GEVZ sevz 10 100 10 kHz A after startup 83 Voltage level at K15 to start the See number 7 1 of A TEVZ regulator Table 8 2 on page 23 84 Hysteresis at K15 to stop the See number 7 2 of A IEVZ regulator Table 8 2 on page 23 85 Voltage level at K30 to start the See number 7 3 of A 7 EVZ regulator Table 8 2 on page 23 8 6 Hysteresis at K30 to stop the See number 7 4 of A IEVZ regulator Table 8 2 on page 23 Voltage at pin GEVZ to switch Vkao 2 3 85V to 5V Bd through the external driver ON threshold GEVZ Veevz 0 5V Vkso M Voltage at pin GEVZ to switch BB through the external driver Vkao 2
58. intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMELS TERMS AND CONDI TIONS OF SALE LOCATED ON ATMELS WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically provided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life Atmel Corporation 2007 All rights reserved Atmel logo and combinations thereof Everywhere You Are and others
59. io Visas Vuze UZP Ratio 0 995 1 A Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter AMEL 4929B AUTO 01 07 AMEL Table 19 1 Electrical Characteristics Continued AMUX Analog Multiplexer for Voltage Measurements No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type 18 15 Ratio Vusp Vuzp For Vypeni BV gt 3V to 25V ZP Ratio 6 02 2 3 A Talaq Bal Vosa Vuze For Vyperi 3 3V gt 3V to 25v YZP Ratio 9 07 2 3 A Special Measurement For Detection of Band gap Defect 18 16 Ratio Vuzp UZP Ratio 3 99 2 6 A Voltage 0 9 x Vyperi 18 17 switched to Vuzp UZP Ratio 0 9 x Vypgn 2 A Voltage 0 1 x Vyegni A 18 18 switched to Ve UZP Ratio 0 1 x 2 A nput voltage range for 18 19 proper function of 10 or 14 6 Vinpu 6 40 V A divider Input voltage range for 18 20 proper function of 6 or 9 1 Vinpu 15 25 V A divider nput voltage range for 18 21 proper function of 4 and 2 Vinpu 4 6 V A divider nput voltage range for Vuen 2 proper function of 1 buffer Vinpu Ds 0 2 v 18 23 Ratio Vaer Vuzp 296 1 096 Type means A 100 tested 100 correlation tested Characterized on samples Design parameter 64 ATA6264 Preliminary 4929B AUTO 01 07
60. ising edge of SSQ to 16 42 K switch off delay Vy 0 9 X Vigo K ta 10 5 Du 250010 K30 Cy 3 3 nF to GNDB x 1 2 output driver deactivated AMUX measurement activated and 16 43 K leakage current deactivated Kx lkx K30 5 5V to 15V 10 100 HA K30 gt 15V to 25V 10 160 HA K30 gt 25V to 40V 10 260 HA x 1 2 output driver deactivated AMUX 16 44 K leakage current measurement deactivated K k 150 10 HA A K30 5 5V to 40V K 25V Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter gt gt gt Figure 17 2 Timing LIN ISO 9141 Interface 2 Baudrate VTXD 2 ton toff Baudrate I I 1 I bi PD H 777 1 bu v l i RXD i I I Ip 1 AMEL 4929B AUTO 01 07 AMEL 18 Voltage Current Sources IASG Sources 58 For a variable resistance measurement and especially for buckle switch detection five constant voltage sources switchable between two different voltages V1 and V2 are implemented The current delivered by these voltage sources is mirrored by a factor of 1 10 or 1 15 to the pin ISENS and causes a voltage drop at the external resistor connected to this pin This voltage drop can be measured at pin UZP by choosing the corresponding AMUX command The
61. n VSAT to ensure proper func tion of the regulator 322 AT A6264 Preliminary E A A6264 Preliminary 11 VPERI Power Supply With the Vpery regulator a stabilized and ripple free voltage is generated out of the VSAT supply voltage This voltage is intended to be used for sensitive components for example sensors or reference inputs of A D converters from microcontrollers For this reason a linear regulator is implemented to guarantee high ripple rejection and a precise voltage The regulator output is short circuit protected by an overcurrent protection If pin VPERI is disconnected the regulator is switched off and RESQ RESQ2 are set to low Figure 11 1 Functional Principle of the Vperiphera Regulator V Peripheral Linear regulator If a higher current capability of the regulator is requested or if the power dissipation of the linear regulator is too high an external transistor can boost the regulator Figure 11 2 Functional Principle of the VPERI Regulator With External Boost Transistor VsAT SVPERI Q VPeripheral Linear regulator V Peripheral LL The VPERI voltage can be programmed via the serial interface to one of two different voltage values during initial programming AIMEL 33 4929B AUTO 01 07 uy 1 AMEL Necessary for operation Operating conditions of all other supply pins Vkao Vevz and Vcore are within functional range limits T 40 C to 150 C Other pi
62. n the internal pull up current at pin VCORE to ensure proper function of the regulator 36 ATA6264 Preliminary s x X A A6264 Preliminary Table 12 1 Electrical Characteristics Continued VCORE Power Supply No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type Time between reaching 0 1 x Vkaomax VvcoREmin and 1142 77 transistor svvitch off m X Vksomax VvcorEmin SVCORE tsvconcon 150 we A 0 1 x Vevzmax VvcorEmin and 0 9 x Veyzmax Vvcoremin for switching of the regulator 999 Numbers 14 6 and 11 13 77 9 14 6a of Table 15 2 on and setting pin RESQ to low Beer VCORE is set to 5V pag for switching of the regulator S28 Numbers 14 7 and 11 13a b 14 7a of Table 15 2 on and setting pin RESQ to lovv Wee VCORE is set to 2 5V pag for switching of the regulator 999 Numbers 14 8 and 11 13b 14 8a of Table 15 2 on and setting pin RESQ to lovv Beer VCORE is set to 1 8V pag Time between reaching rm overvoltage and reaching 11 14 Overvoltage switch off time 90 of Vacor maximum SVORE svCOREoff 0 0 4 Hs A under on condition Time betvveen reaching overcurrent and reaching 11 15 Overcurrent switch off time 90 of Vecore maximum SVCORE svconEorr 0 0 5 Hs A under on condition 11 16 U arpin Output transistor off SVCORE lsvcoRE 10 10 HA A Error Amplifier Maximum output current at 11 17 pin COMCOO sinking to low COMC
63. nd 2nd trigger vvatchdog command VVatchdog eycle see pages 48 and 49 AIMEL 47 4929B AUTO 01 07 x AMEL Requirements for successful trigger Minimum one valid different serial interface command between two trigger watchdog commands is necessary Exception First trigger watchdog command need not be preceded by a different serial interface command e Cyclic repetition for the trigger watchdog command within 25 tolerance is necessary Incorrect trigger causes RESQ active The prescaler will be set to its default value with RESQ low Initial phase Timing for the first trigger watchdog is fixed to 16 ms after RESQ changes from low to high trig ger window 25 means 4 ms trigger window for first trigger watchdog command After the first watchdog trigger the prescaler can be reconfigured within a specified time window lt 1 ms Only one configuration command is allowed in this time window For watchdog trigger handling the Serial Interface Reconfigure command can be chosen as a different serial interface com mand Any further configuration inside or outside this time window will cause an immediate reset via RESQ Figure 16 2 Reconfiguration Prescaler Functional Principle RESQ chip internal trigger window Serial interface Succesful No succesful reconfiguration reconfiguration inactive active Trg VVdg CMD o 1 1 t 48 ATA6264 Preliminary 4929B AUTO
64. nput for the VPERI regulator internally used VPERI supply 24 SVPERI Output of VPERI regulator power transistor 25 GNDA Analog GND 26 VCORE nput for VCORE regulator 27 COMSATI Input of the VSAT externally compensated error amplifier 28 VINT Output of internal supply voltage 29 GNDD Digital GND 30 VSAT Input for VSAT regulator internally used VSAT supply 31 SVSAT Output of VSAT regulator power transistor 32 EVZ Input for EVZ regulator internally used EVZ supply 33 K15 Connection to car battery via the ignition key 34 COMSATO Output of the VSAT externally compensated error amplifier 35 COMCOI lnput of the VCORE externally compensated error amplifier 36 COMCOO Output of the VCORE externally compensated error amplifier 37 CP OUT Switchable output of charge pump voltage 38 SVCORE Output of VCORE regulator power transistor 39 CP Charge pump output 40 FBEVZ Input for external resistor divider to adjust EVZ voltage 41 OCEVZ Input for overcurrent measurement of the EVZ regulator 42 GEVZ Gate driver output for the external FET of the EVZ regulator 43 GNDB GND connection of all power stages 44 COMEVZO Output of the EVZ externally compensated error amplifier 4929B AUTO 01 07 AMEL s AMEL 3 Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions beyon
65. ns As defined in Section 4 Functional Range on page 8 Table 11 1 Electrical Characteristics VPERI Power Supply No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type Voltage level at VSAT to enable 10 1 VPERI regulator VSAT Vysar 6 77 7 2 V A Hysteresis at VSAT to disable 10 2 VPERI regulator VSAT Vysar 0 2 0 5 V A Vyper Programmed 10 3 Output voltage 1 band gap tolerance VPERI Vyper 3 6 5 4 V A included Vvperi2 programmed 10 4 Output voltage 2 band gap tolerance VPERI Vypeni 4 3 3 3 V A included 10 5 Output current Vysar 7 5V to 12 5V VPERI IVPERI 100 mA A 10 6 Short circuit current VPERI Jusen 200 110 mA A Vysar 8V to 12 5V IPERI 1 to 1 00 10 7 Line regulation een is constant during VPERI Vyperi 10 10 mv A measurement Vaar DV to 12 5V Vysar 10 8 Load regulation is constant during VPERI Vyper 240 410 mv A measurement bERi 71 mA to 100 mA IPERI 00 mA r f 100 kHz 20 MHz 10 10 Supply voltage rejection Coca 47 uF 100 nF 40 dB D ceramic Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 344 ATA6264 Preliminary X A 1 6264 Preliminary 12 VCORE Power Supply The voltage of the VCORE regulator is generated out of the K30 voltage
66. nt MM compensation and leading edge blanking EVZ Q COMCOO CP Q 4929B AUTO 01 07 In order to trim the compensation of the regulation loop and to improve the behavior at load changes pin COMCOO has to be connected to COMCOI via a compensation network Because of the fact that current mode controlled converters exhibit sub harmonic oscillations when oper ating at duty cycles larger than 50 a slope compensation which adds an artificial ramp to the comparator is implemented If the regulator input voltage at pin EVZ or pin K30 is too low the regulator switches to a duty cycle of 100 Permanent on mode Backward feeding of EVZ and K30 is avoided In order to ensure the gate voltage for the output transistors of the regulator the driver stages are supplied by the charge pump pin CP AMEL a AMEL Necessary for operation VPERI gt Vcore Sex 0 3V Vint 3 7V to 5 47V Operating conditions of all other supply pins is within functional range limits T 402 to 150 C Other pins As defined in Section 4 Functional Range on page 8 Table 12 1 Electrical Characteristics VCORE Power Supply No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type Vevz voltage for the VCORE Initial programming regulator to start running Vycore 5V or 2 5V eve Vevz S y A Vypen Voltage for the m rs 11 1a VCORE regulator to start initial programming VPERI
67. og prescaler a special serial interface command is necessary Description Hex Code Configure prescaler 011111010101010111111111 101 60Fx Note a b andc to be set as defined in Table 16 1 Table 16 1 Watchdog Prescaler Command Selection Bits a b c Retrigger Time ms 0 0 0 Set to default 16 ms 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 Set to default 16 ms The status of the vvatchdog prescaler is indicated in the status register AIMEL 4929B AUTO 01 07 uy 1 AMEL Necessary for operation Vpeni gt Reset threshold Vcore gt Reset threshold Operating conditions of all other supply pins Vkao Vevz and Vygar are within functional range limits T 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Table 16 2 Electrical Characteristics Watchdog Function No Parameters Test Conditions Pin Symbol Min Max Unit Type 15 1 Oscillator frequency fs 5 100 5 kHz A 15 2 Power up extension of RESQ RESQ Lee 16 16 100 A signal os Start of first vvatchdog trigger 100 15 3 window after rising edge at t 12 12 m A RESQ 154 Maximum width of first t 8 8 100 A watchdog trigger window 2 Maximum time for prescaler 100 15 5 configuration after first t 1 1 3 A watchdog trigger command os
68. oltage overshoot at x 1 to 5 17 3 IASGx due to regulator when IASG 5V IASG 5 9 V A characteristic when IASG 10V 11 3 V A 1105 iz4 Maxim m duration ef voltage 409 06 1466 hes 30 us A overshoot at IASGx Ri oap lt Vissex 5V 40 mA Linear range for current mirror x 1 to 5 17 5 at IASGx OV Visens IASG 40 0 5 mA A 17 6 nternal current limitation at x 1 to 5 IASG ia 150 en d A IASG x 1 to 5 i CR has lisens 39 o 17 7 Current ratio 1 OV Vigens 0 96 x Wich IASG CR 3 9 9 3 A 40 mA lt liasex lt 0 5mA x 1 to 5 CRox has lisens 17 8 Current ratio 2 OV Visens 0 96 x Viska IASG CR 3 14 9 3 A 40 mA lt 0 5 mA x 1 to 5 17 9 Settling time RlAsex 2500 no capacitive ISENSE tisENSE 0 50 5 load at IASGx x 2 1 to 5 Measured from rising edge 17 10 Switch on delay pees IASG tiasex 0 50 5 Vlasex 0 1 X Viasax Riasex 250Q no capacitive load at IASGx Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 60 ATA6264 Preliminary X A A6264 Preliminary Table 18 1 Electrical Characteristics Continued Voltage Current Sources IASG Sources No Parameters T
69. on sasssa A SS eer dne 3 1 1 1 Integrated Boost Converter EVZ 3 1 1 2 Integrated Buck Converter 5 3 1 1 3 Integrated Buck Converter VCORE sse 3 1 1 4 Linear Regulator VPER AA 3 LLES Blocks Included reote a a DR a SUR 3 2 FinConliguralionmuu nl 4 3 Absolute Maximum Ratings 6 4 E ET E 8 4 1 Protection Against Substrate Currents 9 5 Supply e E 10 5 1 Discharger Citc it iiie ertet P e FR SERAS 11 5 2 Initial Programming of the ATA6264 11 5 3 Start up and Power down Procedure 14 5 3 4 Start up Procedure if VVCORE is Programmed to Be 5V or 2 5V 15 5 3 2 Power down Procedure Takes Place in Different Phases 15 5 3 8 Start up Procedure if VVCORE Programmed to Be 1 88V 16 5 3 4 Power down Procedure for VVCORE is Programmed to be 1 88V 17 6 Power Supply Sequencing 18 AE 87 17 1 6 5 7 o aaa 20 EV 0 r 22 9 EVZ Step up Regulator 24 10 VSAT Power Supply l l 30 11 VPERI Power Supply ai 33 12 VCORE Power Supply aAA 35 13 USP Comparator for General Pu
70. operating Phase3 After VVSAT has reached 6 77V to 7 2V the VPERI regulator starts working Phase4 If VVPERI is higher than 1 25V to 1 7V the VCORE regulator will be enabled 16 ATA6264 Preliminary 4929B AUTO 01 07 X 264 Preliminary 5 3 4 The Power down Procedure for Vycore is Programmed to be 1 88V 4929B AUTO 01 07 Phase1 If the ignition key is switched off the K15 voltage will vanish at pin K15 If the serial interface command KEYLATCH is not set the EVZ regulator stops working The external charge pump is still working because EVZ is above VSAT and the VSAT regulator is not in the Perma nent on mode The charge pump voltage still supplies the VSAT regulator and the VCORE regulator Because the EVZ regulator stops working VCORE will be switched to EVZ Phase2 The EVZ capacitor will be discharged and as soon as the voltage at pin VSAT drops too low the VSAT regulator will go into Permanent on mode If VSAT reaches Permanent on mode the external charge pump stops working and the VSAT voltage falls analog to the EVZ voltage If the voltage at VSAT is below 6 27V to 7V the VPERI regulator will be switched off Depending on the charge pump voltage the VCORE regulator stops working The power sequencing function for the VPERI regulator is still active and guarantees a maximum voltage difference between VPERI and VCORE of 2 8V Phase3 After VVPERI becomes low
71. operation Vevz OV to 40V Vint 3 7V to 5 47V Operating conditions of all other supply pins Vvsat gt Vvpeni and Vycore are within functional range limits T 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Table 6 1 Electrical Characteristics Power Supply Sequencing No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type m reme R s v 52 witch of VPEMI regulator m 28 v 100 mv A Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 18 ATA6264 Preliminary EEE EE EEE 4929B AUTO 01 07 A6264 Preliminary Figure 6 2 Block Diagram Povver Supply Sequencing 15 lt Mo K15GOOD uz V Vias 3V to 4 15V 40 mV to 175mV Hysteresis Comp 1 K30 Serial interface Q e KEY LATCH V CP d CP IREF lost L signal K30GOOD Vkao 3 85V to 5V VK30 50 mV to 150 mV Hysteresis Comp EVZEN GEVZ y Q V VEVZ CORESWAP D driver Vkao 6 1V to 8 1V ON EN E SIE 0 5V to 1V Hysteresis Comp IP O EVZ Vevz Q V 7 5V to 9V ON VCP b ON EVZGOOD a Vevz 5 5V to 6 2V OFF A Comp VSAT j SVSAT driver VSAT Vysar Q VSATGOOD VEVZ Vat 6 77V
72. other supply pins Vysar Vvpeni and Vycore are within functional range limits T 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Table 7 1 Electrical Characteristics Charge Pump No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type CP off supply of 6 11 Supply current at pin CP internal circuitry CP lcp 0 50 HA A Time between wrong CP OUT 6 12 voltage and valid data in status CP OUT ty 0 50 5 register 6 13 a a SS CP OUT kan 08 42 mA A Voltage difference Ve Veyz 1Note Threshold is in 6 14 er detecting vvrong CP the range of 5V to 7V ER Voit y Time between wrong CP 6 15 voltage and valid data in status CP ta 0 50 Hs A register Voltage difference Vco our AR 6 16 Vgyz for detecting wrong CP OUT Von 5 V A CP OUT g Vevz 5 5V to 40V lt Vevz lop ke ou 7100 HA 6 17 Voltage at pin CP current consumption of CP Vcp Vevz 7 Vevz 11 V A Vsar and Vcore have to be added Vevz 5 5V to 40V lt Vevz lop ke ou 7100 HA 6 18 Voltage at pin CP current consumption of CP Vcp 7 11 V A Vsar and Vcore have to be added Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 21 4929B AUTO 01 07 AMEL AMEL 8 GKEY Function The GKEY function is used to enable or disa
73. pin VSAT drops to low the VSAT regulator will go into Permanent on mode If VSAT reaches Permanent on mode the external charge pump stops working and the VSAT voltage falls analog to the EVZ voltage If the voltage at VSAT is below 6 27V to 7V the VPERI regulator will be switched off Depending on the charge pump voltage the VCORE regulator stops working Phase3 When the voltage at the EVZ capacitor gets to be lower than 5 5V to 6 2V VSAT is switched off AIMEL a Figure 5 4 VaEvz Threshold to enable AMEL 1 A VCORE regulator Vevz Threshold to start VCORE regulator Y y 1 Vvsar 6 77V to 7 2V 7V to 6 27V VVPER VVCORE 5 3 3 T T A i7 5V to 9V too low EVZ voltage 5 5V to 6 2V 1 VSAT goes into On Mode 1 charge pump deactivated Start Up and Power Down Procedure if Vycore Programmed to Be 5V or 2 5V t VKis one a t t br t i 1 T r N E Start up Procedure if VVconer Programmed to Be 1 88V Last t t Phase1 After switching on the ignition key the K15 voltage will appear at pin K15 lf in addi tion the voltage at pin K30 is larger than 3 85V to 5V the EVZ regulator will be enabled The signal K15GOOD can be replaced by the serial interface command KEYLATCH which can be set by the serial interface Phase2 If VEVZ is larger than 7 5V to 9V the VSAT regulator starts
74. pply Currents A minimum current has to flow into each pin for proper functioning of the IC Table 5 1 Electrical Characteristics Supply currents No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type Standby mode OV Vkao 18V 2 1 Supply current at K30 Vias 3V and KEYLATCH OFF K30 Ikao 0 50 HA A Standby mode 18V Vun 40V 2 1a Supply current at K30 Vas 3V and KEYLATCH OFF K30 Ikao 0 5 mA A Startup mode OV 18V 2 1b Supply current at K30 V s gt 4 15V or KEYLATCH ON K30 Jean 0 7 mA A OV Cop 47 nF Startup mode 18V lt Vuen 40V 2 1c Supply current at K30 Vias gt 4 15V or KEYLATCH ON K30 Ikao 0 10 mA A Vevz OV Cop 47 nF Normal mode OV lt Vun 18V Vevz gt Vkao Vkis gt 4V or 2 1d Supply current at K30 KEYLATCH ON SVCORE open K30 Ikao 0 6 5 mA A AMUX Measurement K30 active Normal mode 18V lt Va 40V 2 1e Supply current at K30 VEVz gt Vrso Vis gt 4 15V or K30 0 10 mA A KEYLATCH ON SVCORE open AMUX Measurement K30 active Startup mode OV Veyz 40V 2 2 Supply current at EVZ Vsar Vreni Vcore V EVZ 0 5 mA A gt 5V Vas gt 4 15V SVCORE EVZ and SVSAT open Normal mode OV lt Veyz 40V Vpeni and Vcore gt Reset Threshold Veyz gt Vigo 2 2a Supply current at EVZ Vsar 10V Vkao gt 5V EVZ levz 0 6 mA A Vias gt 4 15V SVCORE and SVSAT open AMUX
75. pply is connected to the boost converter output EVZ and uses the stored energy of the boost converter capacitor if the voltage at K30 is missing The regulator uses both current and voltage feedback The basis for the regulation loop is a temperature compensated band gap reference voltage which is compared with the internally divided output voltage VSAT The error amplifier output is applied to the inverting input of a comparator the current feedback is connected with the positive input The PWM flip flop which is set every 5 us by the oscillator is reset if the current feedback reaches the error amplifier level In order to adjust the compensa tion of the regulation loop and therefore improve the behavior in case of load changes in continuous mode operation pin COMSATO has to be connected to COMSATI via a compensa tion network Because of the fact that current mode controlled converters exhibit sub harmonic oscillations when operating at duty cycles higher than 50 a slope compensation which adds an artificial ramp to the comparator is implemented If the regulator input voltage at pin EVZ is too low the regulator switches to a duty cycle of 100 Permanent on mode The VSAT voltage can be programmed via the serial interface to one of three different voltage values during initial programming Functional Principle of the VSAT Regulator Current Slope measurement compensation and leading edge Bandgap blanking reference
76. py HI 14 ATA6264 Preliminary 4929B AUTO 01 07 Tne A A6264 Preliminary Depending on the initial programming of the ATA6264 the start up procedure takes place in dif ferent phases 5 3 1 Start up Procedure if Vycore s Programmed to Be 5V or 2 5V Phase1 After switching on the ignition key K15 voltage will apply at pin K15 If in addition the voltage at pin K30 is larger than 3 85V to 5V the EVZ regulator will be enabled The signal K15GOOD can be replaced by the serial interface command KEYLATCH which can be set via the serial interface Phase2 If Vgyz is larger than 7 5V to 9V the VSAT regulator starts operating and the VCORE regulator will be enabled Phase3 After Vygar has reached 6 77V to 7 2V the VPERI regulator starts working The VCORE regulator starts operating depending on the charge pump voltage 5 3 2 The Power down Procedure Takes Place in Different Phases 4929B AUTO 01 07 Phase1 If the ignition key is switched off K15 voltage will vanish at pin K15 If the serial inter face command KEYLATCH is not set the EVZ regulator stops working The external charge pump is still working because EVZ is above VSAT and the VSAT regulator is not in Perma nent on mode The charge pump voltage still supplies the VSAT regulator and the VCORE regulator Because the EVZ regulator stops working VCORE will be switched to EVZ Phase2 The EVZ capacitor will be discharged and as soon as the voltage at
77. re than 4 regulator cycles in an overvoltage or undervoltage condition at their corresponding switching marks In addition a detected overcurrent signal during switch on gives information about regulator problems and results in a low level signal for RESQ RESQ2 Figure 15 3 Functional Principle of the Supervisor Circuit for VCORE Monitoring Values are Valid for VVcoRE 1 88V and Vvperi 3 3V EVZ HIGH 7 5V to 9V LOW 5 5V to 6V VPERI 3 0V to 3 16V 3 44V to 3 6V VCORE 1 68V to 1 73V RESQ 2 03V to 2 08V Regulator OFF Signal overcurrent VCORE at regulator ON ON FF VCORE Voltage ON ON If the watchdog is triggered incorrectly RESQ and RESQ2 are set to low as well Voltage spikes on EVZ smaller than or equal to 10 us to 20 us do not influence the RESQ or RESQ2 pins If the ATA6264 internal supply voltage VINT is below its proper value RESQ and RESQ2 are also set to low For all voltages at VPERI below the reset threshold pins RESQ and RESQ2 are switched to low Both pins deliver a valid low until VPERI goes lower than 1V AIMEL 4929B AUTO 01 07 uu o AMEL Table 15 1 Reset Truth Table VPERI VCORE VEVZ WATCHDOG RESQ RESQ2 lt 1V X X X Undefined low Undefined low via resistor via resistor 1V to Vyper OK X X Low Low Not OK X X Low Low After startup no trigger has Hig
78. rpose 39 14 Reference Voltage and Reference Current Generation 40 15 Reset Function Pin RESQ and Pin RESQ2 41 16 Watchdog 116101 47 AMEL a 4929B AUTO 01 07 82 17 18 19 20 21 22 23 24 25 26 27 AMEL LIN ISO 9141 near an 54 Voltage Current Sources IASGx Sources 58 AMUX Analog Multiplexer for Voltage Measurements 62 UZP Bur a a 65 Chip Temperature Measurement 67 Serial interface Commands s rana nra aaa erras Fa nk Arana Aa sa an EKAR 68 22 1 V TM M M ai R 68 22 2 Set Commands rr 70 22 3 Serial Interface Status Register 74 Dg dH 76 Application e 77 Ordering Informati n qu a alda 79 PACKAGE information rass 79 Revision ILI EE 80 ATA6264 Preliminary 4929B AUTO 01 07 AlINEL NN o Atmel Corporation 2325 Orchard Parkvvay San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH 1705 Fribourg Switzerland Tel 41 26 426 5555 Fax 41 26 426 5500 Asia Room 1219 Chinachem Golden Pla
79. rrent In case of a missing resistor at IREF the regulators will stop The power sequencing block still operates as specified A defect of the band gap reference source can be detected by a microcontroller by comparing the voltage at IREF with the voltage at pin VINT Internal 5V supply because Vyr is derived from a different band gap Table 14 1 Truth Table for VINT K30GOOD K15GOOD State Vkao gt 4 2V to 5 gt 3V to 4V Vevz Lovv Lovv 0 OFF 2 High Lovv 0 OFF 3 Lovv High 0 OFF 4 High High Vevz ON Supply K30 ON Supply EVZ only valid if VINT was 2 SS SR Vevz gt 5 5V already enabled via state 4 ON Supply EVZ only valid if VINT was S High Low Vevz gt 5 5V already enabled via state 4 ON Supply EVZ only valid if VINT was Low High Vevz gt 5 5V already enabled via state 4 8 High High Vevz gt ON Supply K30 Necessary for operation Vevz 5 5V to 40V or 3 85V to 40V Operating conditions of all other supply pins Veer and Vcore are within functional range limits T 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Table 14 2 Electrical Characteristics Reference Voltage and Reference Current Generation No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type 13 1 Reference voltage Vizer IREF Vingr 1 24 4 V A 13 2
80. running as soon as a certain threshold voltage at the K15 pin is exceeded The regulator has to stop running again if the voltage at the K15 pin falls below a voltage level or voltage at pin K30 is missing see Section 5 3 Start up and Power down Procedure on page 14 An inductor is PWM switched by an external n channel power FET with a fixed frequency of 100 kHz A driver stage for the external FET is integrated into the ATA6264 The current limita tion of the external FET is implemented by using an external resistor in series betvveen the source connection of the external FET and GND sensing the voltage drop at this resistor via the pins OCEVZ and GNDA The reference section provides a reference voltage of 1 24V for the regulation loop An error amplifier compares the reference voltage with the feedback signal which is provided either from two different serial interface programmable internal dividers VEVZ1 22V VEVZ2 31 5V or an external voltage divider netvvork VEVZEXxt These dividers determine the output voltage EVZ Figure 9 1 EVZ Regulator VVith External Divider Bandgap reference Sawtooth oscillator ar Logic and GEVZ Q driver gt PWM comp Overcurrent Q Ryze C I EVE GNDA overvoltage O SPI E d SPI d lt x z FBEVZ 1 COMEVZO Q ATA6264 Preliminary s 4929B AUTO 01 07 ATA6264 Preliminary Figure 9 2 EVZ Regulator With Internal Divid
81. s of all other supply pins Vevz Vvsat gt Vvpeni and Vycogg are within functional range limits T 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 Table 21 1 Electrical Characteristics Chip Temperature Measurement No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type Temperature coefficient of Chip temperature switched chip temperature sensor via AMUX to UZP UZP Vuze 4 1 86 3 2 mV K D Output voltage temperature Chip temperature switched 20 2 sensor via AMUX to UZP T 25 C V zp 1 29 Te y A f overtemperature is 20 3 Threshold overtemperature detected voltage drops by UZP Vuzp 155 185 C B detection 35 mV 20 3a Hysteresis for overtemperature UZP Voss 5 25 K B detection Type means A 100 tested B 100 correlation tested C Characterized on samples D Design parameter 4929B AUTO 01 07 AIMEL AMEL 22 Serial Interface Commands 22 1 Overview All functions of the ATA6264 are triggered by 16 bit serial interface commands Some of these commands are latched because their actions have to continue for a longer time Other com mands have to be executed as long as no other command is received via the serial interface The pin SSQ low active is used to select the ATA6264 If pin SSQ is inactive high the output pin MISO is disabled tristate and the signals at the pins SCLK and
82. th the current capability of 100 mA The user can program the voltage via an OTP system With a sophisticated power sequencing concept of VCORE and VPERI ATA6264 sup ports dual voltage supply microcontrollers so that under all conditions the voltage difference between the two linear regulator voltages never drops below a defined value This measure guarantees the safe operation of the system 1 1 5 Blocks Included e A general purpose comparator USP for for example low battery voltage detection A band gap as reference for all internal voltages and currents e Two 1SO9141 interfaces one of which is configurable via OTP in accordance with the LIN specification Five constant voltage sources with current to voltage mirrors used for resistance measurements such as buckle switch detection in the range from 0 5 mA to 40 mA e An AMUX block with push pull buffer stage provides the output of all analog values such as voltage sources low voltage detection or the chip temperature for continuous diagnosis A 16 bit serial interface for the communication with the microcontroller which includes a 16 bit shift register a 16 bit latch and a decoder logic block A watchdog to monitor the microcontroller and to generate reset signals in the case of failure nternal oscillator generates internal clock signals GKEY function to control the main switch of the ECU via a logic signal AIMEL 4929B AUTO 01 07 AMEL 2 Pin Con
83. the analog multiplexer is possible The K1 and K2 outputs include an internal current limitation and overtemperature protection circuit Figure 17 1 Functional Principle of the LIN ISO 9141 Interfaces UZP uC Analog input Serial interface Analog MUX K30 Mode E select ra K b 5 yx TXD b RXD Rm Necessary for operation Operating conditions of all other supply pins Vysar S within functional range limits T 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 ATA6264 Preliminary X A 1 6264 Preliminary Table 17 1 Electrical Characteristics LIN ISO 9141 Interfaces No Parameters Test Conditions Pin Symbol Min Typ Max Unit Type General Valid for All Modes Pull up current to VPERI at H H E d 16 1 pin TxD x 1 2 TxD ypx 35 50 65 HA A 0 4 16 2 K input receiver low x 1 2 K V 0 V V A K30 0 6 x 16 3 K input receiver high x 1 2 K Vi V V A K30 Vkso 16 4 K input receiver threshold x 1 2 K Vix 5 V A 16 5 K input receiver hysteresis x 1 2 K Vi 277 V A 16 6 output sink current ate K 35 mA A K output voltage 1 5V x Kx 16 7 K output voltage dro Kal
84. tolerance and the offset tolerance of the UZP buffer Vyzpofiset are defined in separate points The UZP buffer is defined in the following section Necessary for operation Operating conditions of all other supply pins Vvsat gt Vvpeni and Vycore are within functional range limits T 40 C to 150 C Other pins As defined in Section 4 Functional Range on page 8 e ATA6264 Preliminary mmm A6264 Preliminary Table 19 1 Electrical Characteristics AMUX Analog Multiplexer for Voltage Measurements Parameters Test Conditions Has to be calculated from the 18 1 Output offset error values of the differential UZP V UzPottset 15 mV A measurement 18 2 Ratio Vis Vuzp For Vypeni 5V gt 3V to 25V Ratio 6 05 2 3 A For Vyper 3 3V 1 5V to 3V 9 12 6 A 18 2a Ratio Vue Vuzp For Vypeni 3 3V gt 3V to 25v H Hala 9 12 2 3 A 18 3 Ratio Vigo Vuze For Vyper 5V gt 3V to 25V UZP Pano 6 04 2 3 A 18 3a Ratio Vkso Vuzp For 3 3V gt 3V to 25v 227 hatio 9 11 2 396 A 18 4 Ratio Vgyz Vuzp For Vypeni SV UZP Ratio 9 9 2 376 A 18 4a Ratio Vevz Vuzp For Vyper 3 3V UZP Ratio 14 78 2 6 A For Vuen SV 1 5V to 3V 6 05 696 165 Muze For Vypni 5V gt 3V to 25V nali 6 05 2 3 A x For Vypeni 3 3V gt 3V to 25v 927 Ratio 9 12 2 3 A
85. using a step down reg ulator as long as the K30 voltage is available During times when K30 is not present power down or stand alone time the VCORE regulator is supplied out of VEVZ Depending on the initial programming the supply switch signal is derived from the CORESWAP comparator or the EVZEN comparator The VCORE voltage can be programmed via the serial interface to 3 different voltage values during initial programming In the case of short spikes a logic circuit dis ables multiple pulse operation during one oscillating period The regulator uses both current and voltage feedback In the following cases the output transistor of the regulator is switched off at once and may be switched on again with the beginning of the next clock period 1 If the current through the transistor exceeds the output current limit value the transistor is switched off immediately 2 If overvoltage is detected at the pin VCORE the transistor is switched off immediately 3 Ifthe feedback voltage at the pin VCORE is missing disconnected pin the regulator is switched off Figure 12 1 Functional Principle of the VCORE Regulator Control signal K30 EVZ 9 K30 Current 9 Slope measurement compensation and leading edge blanking Overcurrent H4 E Overcurrent 4 VCORE VCORE Q SVCORE Bandgap Logic and Q reference driver COMCOI ES Q e 1 AAA m E 1 SPI OTP Current Slope measureme
86. voltage and reaching 90 of the 8 20 Overvoltage switch off time value at numbers 8 7 GEVZ lottov 200 ns D and 8 8 of Table 9 1 on page 27 Time between reaching overcurrent and reaching 90 of the 8 21 Overcurrent switch off time valiie at n rmbers B 7 GEVZ i 500 ns A and 8 8 of Table 9 1 on page 27 Svvitch on delay time for the Med boost converter output stage taon a SH ns A Time betvveen 0 5V and qa anno ma ora REENEN GEVZ Ka 10 200 ns A converier output stage Coevz 2 nF 8 24 Svvitch off delay time for the GEVZ aon 50 150 H A boost converter output stage Time between 4 5V and 8 25 Switch off fall time for the boost 0 5V at GEVZ GEVZ ton 10 100 na A converter output stage 5 Coevz 2 nF 8 26 Leakage current at pin OCEVZ OCEVZ locevz 10 10 HA A 8 27 Leakage current at pin FBEVZ FBEVZ locevz 10 10 HA A 8 28 Switch on threshold via FBEVZ 7 fela FBEVZ Veeew 1 20 1 24 V A 8 29 Switch on threshold via FBEVZ aoe Sen FBEVZ 124 128 V A Veyz programmed 8 30 Vevz voltage 1 set by SPI Band gap tolerance EVZ Vevzi 20 23 V A included voltage 2 Vevz rogrammed 8 31 EVZ Band gap tolerance EVZ Vevz 28 6 33 V A set by SPI included 8 31a Temperature shutdown Tor 155 185 oG B activation Hysteresis for reactivation of 8 31b GEVZ Thys 5 25 K B Type means A 100 tested B 100 correlation tested C Characterized on samples D Design p
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Atmel ATA6264 Power Supply User Manual

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