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Ampro Corporation 5001692A Computer Hardware User Manual

1. e e e e ow Bon m 8 25 se oo eo ai ai eo 3 575 3 431 i EE ER eee 8 OQOOOOQO JP1 3 400 3 375 AN 70000000000 00000000000 e O DIC 3 375 jpg J6 J5 CE jajajaa ajo ab felt 3 190 Od Hey eooo taloa hes 3 281 m a J13 PS 2 890 4e4H OO gt 3 100 foo zole S pc Sos 18 ho 2 500 S ooooogmB 2 580 OO 11 OO OO OO OO J4 e 7 OO 30 OO 59 S OO o 60 CPU E OO 00 S 0 940 i U14 12 2 0 700 1 5 J10 P1C P1D 8 4H 0 394 0 300 OOoOODOODODOOODOOOOGOOGOGOOODOOGOOQOCO OOOOOOOOOOOOOOOOOOOOOOOOC oOOOOO0 oooaliooooooooooooooodgooc 0 000 D Du DOO OOD DODO OOOO OOOO 5 0 000 0 010 J7 JP2 0 200 E T 40 c 9 Figure 2 7 Mechanical Dimensions View All dimensions are given in inches Pin 1 is s
2. Product Overview JP6 JP9 JP7 JP5 JP4 JP1 5 Re al H JPG 65155 4o Bevo J3 co 9665 ajo c EX CES a Jig JPS JP4 5 rs Lk E e SE 5 0 S e
3. 45 Environmental 15 Ethernet CONNECTION 37 controller Lote ee 37 Port LEDS eausa esi 12 port SettiINgS 51 supported feature 37 Flash access BIOS settings 49 flash programming see 55 programming tools esee 55 Floppy disk port ii aec 48 49 supported drive sizes sess 31 48 Hot cable console redirection 42 modified serial cable sss 42 Console rise te Mn sent 42 W O address 20 IDE interface port SEIN GS ecole M esas 51 supported features 27 Interrupt IRQS list 20 Jumpers locations oO GR 12 Sec eer DERE 12 Keyboard connector pin outs 36 SCLIN SS M MEE 50 supported feature sese 36 LEDs Ethernet Port ete 12 62 Reference Manual Lithium Battery real time clock RTC 40 Low voltage limit 43 Memory 64MB SDRAM esee 18 IMB flash memory 18 BIOS settings untere mrt 50 Bytewide socket 18 Mouse connector pin Outs sese 36 Settings eere ende RUE 50 supported feature
4. Disabled or Enabled Disabled or Enabled EM c a d Typically COM2 Typically COM1 Typically Floppy Disk Typically LPT1 Typically unused Typically unused Typically ISA Bridge Native IDE Typically PS 2 Mouse Typically Hard Disk Typically Hard Disk Reference Manual CoreModule 420 Chapter 4 BIOS Setup Splash Screen Customization The CoreModule 420 BIOS supports a graphical splash screen which can be customized by the user and displayed on screen when enabled through the BIOS Setup Utility The graphical image can be a company logo or any custom image the user wants to display during the boot process The custom image can be displayed as the first image displayed on screen during the boot process and remain there depending on the options selected in BIOS Setup while the OS boots Splash Screen Image Requirements The user s image may be customized with any bitmap software editing tool but must be converted into an acceptable format with the tools files and utilities provided by Ampro If the custom image is not converted with the utilities provided then the image will not display properly when this feature is selected in BIOS Setup NOTE Do not use other splash screen conversion tools as these will render an image that is not compatible with the CoreModule 420 BIOS The splash screen image supported by the CoreModule 420 BIOS should be e Bitmap image e Exa
5. CoreModule 420 PC 104 Single Board Computer Reference Manual P N 5001692A Revision A Notice Page NOTICE No part of this document may be reproduced transmitted transcribed stored in a retrieval system or translated into any language or computer language in any form or by any means electronic mechanical magnetic optical chemical manual or otherwise without the prior written permission of Ampro Computers Incorporated DISCLAIMER Ampro Computers Incorporated makes no representations or warranties with respect to the contents of this manual or of the associated Ampro products and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose Ampro shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this product even if it has been notified of the possibility of such damages Ampro reserves the right to revise this publication from time to time without obligation to notify any person of such revisions If errors are found please contact Ampro at the address listed below on the Notice page of this document TRADEMARKS Ampro and the Ampro logo are registered trademarks and CoreModule EnCore Little Board LittleBoard MiniModule and ReadyBoard are trademarks of Ampro Computers Inc All other marks are the property of their respective companies REVISION HISTORY Initial Release Mar 04
6. Pin Signal Description P1 Row C 1 CO GND Ground 2 Cl SBHE System Byte High Enable This signal is driven low to indicate a transfer of data on the high half of the data bus D15 to D8 3 C2 LA23 Lactchable Address 23 This signal must be latched by the resource if the line is required for the entire data cycle 4 LA22 Lactchable Address 22 Refer to LA23 pin C2 for more information 5 C4 LA21 Lactchable Address 21 Refer to LA23 pin C2 for more information Reference Manual CoreModule 420 Chapter 3 Hardware Pin Signal Description P1 Row C 6 C5 LA20 Lactchable Address 20 Refer to LA23 pin C2 for more information 7 C6 LA19 Lactchable Address 19 Refer to LA23 pin C2 for more information 8 C7 LA18 Lactchable Address 18 Refer to LA23 pin C2 for more information 9 C8 LA17 Lactchable Address 17 Refer to LA23 pin C2 for more information 10 C9 MemR Memory Read This signal instructs a selected memory device to drive data onto the data bus It is active on all memory read cycles 11 C10 MemW Memory Write This signal instructs a selected memory device to store data currently on the data bus It is active on all memory write cycles 12 C11 SD8 System Data 8 Refer to SD7 pin A2 for more information 13 C12 SD9 System Data 9 Refer to SD7 pin A2 for more information 14 C13
7. Super I O Standard FDC37B782 Super I O This chip provides serial Floppy Serial Controller U13 Microsystems and Floppy controllers Controllers Corp Ethernet Intel 82551ER Ethernet This chip provides the Ethernet Controller U15 10 100BaseT Ethernet function aree 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 J5 m 0000 EE o o o o m 4o ofa op e La E 9 9 5 5 5 5 mio 08 J13 JP5 JP4 0 a 2 EI n 9 HS Le dm FENS ARE sense O yy BID P8 0 5 5 5 5 2 EL as d Sr Memory U6 U7 U8 09 U10 ue CPU U14 un a o e RM Wa ee e Teese e mm gt 55 gt SPER EN I SDRAM Z5 de E U14 ej Memory U15 2 07 010 Super U13 5 us E wil 20 Ethernet U16 3 Controller U15 gt B 3 s Ethernet 999 a Magnetics U16 BO a CM420RFM_01a Figure 2 3 CoreModule 420 Top View Pin 1 is shown as black square or round black pin in connectors and jumpers in all illustrations 10 Reference Manual CoreModule 420 Chapter 2 Product Overview Connectors Jumpers and LEDs Connector Definitions
8. 45 Bytewide socket Ampro Products DiskOnChip fausse 18 CoreModule 410 2 external BIOS Dee 18 CoreModule 420 6 CAUTION CoreModule 600 2 master slave GPIO pins 40 EnCore Family sese 3 overwriting BIOS settings 55 LittheBoard Family 111111 11112121210 2 CompactFlash MiniModule Family 3 always use CF on Sec Master 48 RM ATA format 1 49 connector pin outs 36 BIOS setup eee 48 CO 36 40 Card IDE drive equivalent 29 Lithium type 40 Socket Type I or Type 29 BIOS recovery 41 Connectors See also Oops jumper manufacture s number 59 BIOS Setup Parts 59 boot device settings 49 in redirection 41 configuration 45 console redirection 41 Min console OP Eee ee A console redirection 51 serial port settings 5 CPU settings 52 Serial port setup sr 46 Enable BIOS 50 Console Enable Config Box 50 Bi pede 1 Enable Splash 50 5 um ne hi enter BIOS prompt not 45 OS Setup p 5 Ethern
9. 36 No bootable device available 49 Null modem serial cable 42 51 Oops jumper BIOS recovery 41 DB9 connector repere 41 S rial port 41 Parallel port ite DR An GRIP 51 supported 31 51 Parallel Floppy interface Shared port xs Saints in ten cs te 31 PC 104 ISA bus clock speed settings sess 52 up to 8 25MHZ 22 Pin 1 locations 10 POST no bootable device available 49 Power interface connector 17 43 pinouts ote eee hien 43 Power Management BIOS settings 50 Power requirements 15 QuickStart Kit COMENTS c once eden et eite reor d 2 CoreModule 420 2 Real Time Clock RTO 40 Reset switch connector pin outs 36 supported feature 36 Serial console accessing BIOS neo een Oe 46 console redirection 41 Hot cable tert ether edes 42 modified serial 42 serial port settings 42 serial port Setup 46 S rlalterminal sister 41 standard null modem serial 42 51 terminal emulation software
10. Keyboard Mouse External Bat etc CM420blkdiag Chapter 2 Product Overview Major Integrated Circuits ICs Table 2 1 lists the major integrated circuits including a brief description of each on the CoreModule 420 and Figure 2 3 shows the location of the major chips Table 2 1 Major Integrated Circuit Descriptions and Function Chip Type Mfg Model Description Function CPU U14 STMicro STPC Embedded CPU The combination of Embedded electronics ATLAS features in the CPU provide more than CPU just a processor It also provides a graphics controller PCI controller EIDE controller I O features and power management capabilities
11. 41 41 Serial ports connector pin Outs sese 34 BIOS settings 51 cn a E 33 RS232 RS485 33 CoreModule 420 Serial terminal real time clock RTC 40 ANSI compatible 41 serial port settings 42 Speaker connector pin Outs sees 36 supported feature 36 Splash screen converting IMAGE 53 CUSTOMIZATION 53 customer defined 53 image conversion tools 54 requirements ect Deeper pente 53 Standard null modem serial cable 42 51 Supported features 64MB eee 18 BIOS T6COVELY ES venen eere D eR 41 BIOS sn ee ae Uy 46 bytewide socket 18 CompactFlash card 29 console redirection 41 sonne Lan De ds RP ne 18 Ethernet ieu mnt tas hee eed 37 flash memory eee 18 floppy disk port 31 48 IDE interface cs venere bop eee CU 27 keyboard saisis 36 Lithium battery 36 MOUSE aset e ote ae ret Bk 36 Oops jumper esee 41 parallel printer port 31 PC 104 DUS tete 22 teset SWiteli 36 RS232 RS485 selection 33 CONSOLES sc i ono vomere mm 41 serial POLS 33 Speaker sss tte
12. Ampro Computers Incorporated 5215 Hellyer Avenue San Jose CA 95138 1007 Tel 408 360 0200 Fax 408 360 0222 www ampro com Copyright 2004 Ampro Computers Incorporated Audience Assumptions This reference manual is for the person who designs computer related equipment including but not limited to hardware and software design and implementation of the same Ampro Computers Inc assumes you are qualified in designing and implementing your hardware designs and its related software into your prototype computer equipment Reference Manual CoreModule 420 Contents CoreModule 420 Reference Manual ili Contents iv Reference Manual CoreModule 420 Contents CoreModule 420 Reference Manual V Contents Vi Reference Manual CoreModule 420 Chapter 1 About This Manual Purpose of this Manual This manual is for designers of systems based on the CoreModule 420 PC 104 single board computer SBC module This manual contains information that permits designers to create an embedded system based on specific design requirements Information provided in this reference manual includes CoreModule 420 SBC Specifications Environmental requirements Major chips and features implemented CoreModule 420 SBC connector pin numbers and definition BIOS Setup information Information not provided in this reference manual includes Detailed chip specifications Internal component operation Inte
13. 36 USB osse nap D 35 video port interface 38 Terminal emulation software senal consolez sescenti ee 41 USB connector pin Outs esee 35 port features esee tem 35 port settings 5 orn eno een 51 Utility Connector battery connection 36 keyboard connection 36 mouse connection ner 36 reset switch connection 36 speaker connection 36 Video port controller features 38 SCLIN SS zs sese ien 51 Watchdog timer WDT 1 to 255 sec interval 42 BIOS settings 50 functions inre certet rete Ree IER 42 machine code 43 source code 43 Weight iei Ico aet e aere t RP bie 14 CoreModule 420 Reference Manual 63 Index 64 Reference Manual CoreModule 420
14. Refer to pin 9 FP2 for more information 26 FP19 Panel Data 19 Refer to pin 9 FP2 for more information 27 FP20 Panel Data 20 Refer to pin 9 FP2 for more information 28 FP21 Panel Data 21 Refer to pin 9 FP2 for more information 29 FP22 Panel Data 22 Refer to pin 9 FP2 for more information 30 FP23 Panel Data 23 Refer to pin 9 FP2 for more information 31 TFTEnVcc TFT Power Vcc This signal is the power to Flat panel displays 32 TFTEnVee TFT Voltage Enable Vee This signal enables power to Flat panel displays 33 PNLVdd Voltage 43 3 or 5 volts 5 depends on setting of JP6 34 12V Out 12 volts 5 35 GND Digital Ground 36 GND Digital Ground 37 HSYNC Horizontal Sync This signal is used for the digital horizontal sync output to the CRT Also used with VSYNC to signal power management state information to the CRT per the VESA DPMS standard CoreModule 420 Reference Manual 39 Chapter 3 Hardware Pin Signal Description 38 VSYNC Vertical Sync This signal is used for the digital vertical sync output to the CRT Also used with HSYNC to signal power management state information to the CRT per the VESA DPMS standard 39 AGNDR Analog Ground for Red 40 RED Red This pin provides the Red analog output to the CRT 41 AGNDG Analog Ground for Green 42 GREEN Green This pin provides the Green analog output to the CRT 43 AGNDB Analog Ground fo
15. SD10 System Data 10 Refer to SD7 pin A2 for more information 15 C14 SD11 System Data 11 Refer to SD7 pin A2 for more information 16 C15 SD12 System Data 12 Refer to SD7 pin A2 for more information 17 C16 SD13 System Data 13 Refer to SD7 pin A2 for more information 18 17 SD14 System Data 14 Refer to SD7 pin A2 for more information 19 C18 8 15 System Data 15 Refer to SD7 pin A2 for more information 20 C19 Key NC Key Pin Not Connected Notes The shaded area denotes power or ground The signals marked with indicate active low Table 3 8 PC 104 Bus Interface Pin Signal Descriptions P1D Pin 4 Signal Description P1 Row D 21 D0 GND Ground 22 D1 MCS16 Memory Chip Select 16 This is signal is driven low by a memory slave device to indicates it is cable of performing a 16 bit memory data transfer This signal is driven from a decode of the LA23 to LA17 address lines 23 D2 IOCS16 I O Chip Select 16 This signal is driven low by an I O slave device to indicate it is capable of performing a 16 bit I O data transfer This signal is driven from a decode of the SA15 to SAO address lines 24 03 IRQIO Interrupt Request 10 Asserted by a device when it has pending interrupt request Only one device may use the request line at a time 25 D4 IRQI1 Interrupt Request 11 Asserted by a device when it has pen
16. 7 Floppy D Z Parallel olojo JO Z RTC Prim IDE D Z Sec IDE D Z USB 7 Ethernet 0000 Z Math x Coprocessor PS 2 Mouse O 7 Legend D Default Optional Fixed Z Disable option Table 3 3 DMA Map DMA Use 0 1 5 6 7 2 Floppy configurable 3 LPT 1 only in ECP mode configurable 4 DMA 1 cascade Address Map Table 3 4 1 0 Address Map Address hex Subsystem 0000 000F Primary DMA Controller 1 0020 0021 Master Interrupt Controller 1 0022 0023 STPC Configuration 20 The devices listed with Z in the Disable column indicate the device can be disabled which will free the IRQ for another device in the list CoreModule 420 Reference Manual Chapter 3 Address hex Subsystem 0040 0043 Programmable Interrupt Timer Clock Timer 0060 0064 Keyboard Controller 0070 0071 RTC NMI enable 0080 008F DMA Page 0094 Motherboard VGA enable 00A0 00A1 Slave Interrupt Controller 2 00C0 00DF Secondary DMA Controller 2 0102 VGA setup register O1F0 01F7 Primary IDE configurable 0170 0177 Secondary IDE configurable 0201 Watchd
17. appropriate PC 104 signals operating at clock speeds up to 8 25MHz This interface connector is located on the both the top and bottom of the module Table 3 5 PC 104 Bus Interface Pin Signal Descriptions P1A Pin Signal Description P1 Row A 1 Al IOCHCHK I O Channel Check This signal may be activated by ISA boards to request that a non maskable interrupt NMI be generated to the system processor It is driven active to indicate an uncorrectable error has been detected 2 A2 SD7 System Data 7 This signal 0 to 19 provides a system data bit 3 A3 SD6 System Data 6 Refer to SD7 pin A2 for more information 4 A4 SD5 System Data 5 Refer to 07 pin A2 for more information 5 A5 SD4 System Data 4 Refer to SD7 pin A2 for more information 6 A6 SD3 System Data 3 Refer to SD7 pin A2 for more information 7 AT SD2 System Data 2 Refer to 07 pin A2 for more information 8 A8 SDI System Data 1 Refer 07 pin A2 for more information 9 A9 SDO System Data 0 Refer to SD7 pin A2 for more information 10 A10 IOCHRDY I O Channel Ready This signal allows slower ISA boards to lengthen I O or memory cycles by inserting wait states This signal s normal state is active high ready ISA boards drive the signal inactive low not ready to insert wait states Devices using this signal to insert wait states should drive it low immediately after det
18. d ect reme O E ps EX Bytewide 3 gt is U7 U8 u9 5 ue Socket U5 a eps Pin 1 rp a B 2 419 gt JSE 55 B ause et LL Link Activity U14 ng zd LED D1 ES FE S E Pep Speed um E sas LED D2 z 016 EL 995599 5599990009 5 m OOOH 00000 RE BY JP2 3 o Figure 2 5 Jumper and LED Locations Top View B 2 CompactFlash eon p 5 T M Socket J12 U19 en TT U1 F HE 000 u21 U20 al S U24 E E LI a H U23 gt TT tn F1 w LT USB Fuse 1 E PC 104 Bus P1 Figure 2 6 Connector Location Bottom View CoreModule 420 Reference Manual 13 Chapter 2 Product Overview Specifications Physical Specifications Table 2 5 gives the physical dimensions of the module and Figure 2 7 gives the mounting dimensions Table 2 5 Weight and Footprint Dimensions Item Dimension Weieht NOTE Height is measured from the 92 5 0 204165 upper surface of the board Height upper surface 10 99 mm 0 43 inches to the highest permanent See also Note on page 15 component on the upper surface of the board Width 90 2 mm 3 6 inches Length 95 9 mm 3 8 inches Mechanical Specifications
19. RS485 mode this pin is TX Data 6 CTS 8 Clear To Send Indicator to the serial port that external serial communication device is ready to receive data Used as hardware handshake with RTS for low level flow control Rx Data Serial Port 1 or 2 If in RS485 mode this pin is RX Data 7 DTR 4 Data Terminal Ready Indicates serial port is powered initialized and ready Used as hardware handshake with DSR for overall readiness to communicate 8 RI 9 Ring Indicator Indicator to serial port that external modem is detecting a ring condition Used by software to initiate operations to answer and open the communications channel 9 GND 2 Digital Ground 10 KEY NC NC Key Pin Not connected Notes The shaded area denotes power or ground The signals marked with indicate active low Table 3 13 Serial 3 amp 4 Interface Pins Signals J13 J14 Pin Signal DB9 Description 1 DCD 1 Data Carrier Detect Indicator to serial port that external modem is detecting a carrier signal i e a communication channel is currently open In direct connect environments this input will be driven by DTR as part of the DTR DSR handshake DSR Data Set Ready Indicator to serial port that external serial communications device is powered initialized and ready Used as hardware handshake with DTR for overall readiness to communicate Receive Data Serial port receive data inp
20. Refer to the software instructions provided with your specific DiskOnChip device for more information concerning booting the device Reference Manual CoreModule 420 Chapter 4 BIOS Setup e Boot Order Boot 1 none Drive A Drive B Drive C Drive D CDROM Alarm Reboot or Flash Boot 2 none Drive A Drive B Drive C Drive D CDROM Alarm Reboot or Flash Boot 3 none Drive A Drive B Drive Drive D CDROM Alarm Reboot or Flash Boot 4 none Drive A Drive B Drive C Drive D CDROM Alarm Reboot or Flash Boot 5 none Drive A Drive B Drive C Drive D CDROM Alarm Reboot or Flash Boot 6 none Drive A Drive B Drive C Drive D CDROM Alarm Reboot or Flash The default Boot order is A C CD ROM and the BIOS will start its search for a bootable device in drive A then C then CD ROM If no bootable device is found the screen will display No Bootable Device Available and the boot process will stop allowing you to select from R for Reboot or S for Setup If you do not choose R or S the boot process stops until you intervene The Alarm or Reboot options can be used as the last boot order option in cases where the BIOS can t boot from any of the selected drives The Alarm option sounds beeps on the speaker e Drive and Boot Options Flo
21. Settings set Boot 17 to Flash to boot from Flash 12 Select Esc to exit to the main menu 13 Exit BIOS Setup using the Exit Saving Changes option 14 After system reboots from the Flash the example application sends a message to the screen Flash Boot API 56 The BIOS implements an API call to assist in booting from Flash This API allows bootloaders to call the BIOS to copy memory anywhere in the 32 bit address range All addresses are treated as linear physical addresses Refer to the Flash directory under Miscellaneous Source Code Examples on the CoreModule 420 Doc amp SW CD ROM cm420 software examples flash for the examples and more information Reference Manual CoreModule 420 Appendix A Technical Support Ampro Computers Inc provides a number of methods for contacting Technical Support listed below in Table A 1 Requests for support through the Virtual Technician are given the highest priority and usually will be addressed within one working day e Ampro Virtual Technician This is a comprehensive support center designed to meet all your technical needs This service is free and available 24 hours a day through the Ampro web site at This includes a searchable database of Frequently Asked Questions which will help you with the common information requested by most customers This is a good source of information to look at first for your technical solutions However you must register online before you can login
22. Table 2 2 describes the connectors shown in Figures 2 4 to 2 6 Refer to Appendix B for part s Table 2 2 Module Connector Descriptions Jack Plug Access Description P1A 1B amp PIC ID Top 104 pin connector used for PC 104 ISA bus PC 104 Bus Bottom J2 Ethernet Top 8 pin 0 1 connector used for the Ethernet interface J3 Serial 1 COM1 Top 10 pin 0 1 connector used for the Serial 1 interface J4 Floppy Parallel Top 26 pin 0 1 connector provides the Floppy Parallel interface J5
23. Unused if Framebuffer is set to 1MB or more 03F0 0000 1MB RAM or Unused if Framebuffer is set to 2MB or more 03E0 0000 1MB RAM or Unused if Framebuffer is set to 3MB or more 03D0 0000 1MB RAM or Unused if Framebuffer is set to 4MB 03C0 0000 44MB RAM Use Address Size Memory hole size selected 8MB 4MB 2MB 1MB OMB 0100 0000 1MB H H H H R 0000 1MB H H H R R 00 0 0000 1MB H H R R R 00D0 0000 1MB H H R R R 0000 1MB H R R R R 00B0 0000 1MB H R R R R 00A0 0000 1MB H R R R R 0090 0000 1MB H R R R R R RAM H Memory Hole forwarded to ISA The board can be configured to have access to the IMB Flash anywhere in the memory hole on 1MB alignment 0080 0000 MB RAM 0010 0000 128kB Shadowed BIOS 000 0000 8kB Unused 000D E000 8kB DiskOnChip if DC000 DDFFF window selected Unused if no DOC present 000D C000 56kB Unused 000C E000 8kB DiskOnChip if CC000 CDFFF window selected Unused if no DOC present 000C C000 48kB Unused 000C 0000 128kB Unused reserved for Video RAM or in SMI mode mapped to RAM 000A 0000 640kB Base memory 0000 0000 CoreModule 420 Reference Manual 19 Chapter 3 Hardware Interrupt Channel Assignments The channel interrupt assignments are shown in Table 3 2 Table 3 2 Interrupt Channel Assignments Device vs D 1 2 3 4 5 6 7 9 10 11 12 13 14 15 Disable IRQ No Timer X Keyboard X Secondary X Cascade COMI D Z COM2 D Z COM3 7 COM4 O
24. Utility Top 10 pin 0 1 connector used for the Utility interface J6 IDE Top 44 pin 2mm connector used for the IDE interface J7 Power Top 10 pin 0 1 connector used for the Power connection J8 GPIO User Top 10 pin 2mm connector used for the User defined GPIO signals J9 Serial 2 COM2 Top 10 pin 0 1 connector used for the Serial 2 interface J10 USB Top 5 pin 0 1 connector used for the USB interface J11 Video Top 44 pin 2mm connector used for the LCD CRT interface J12 CompactFlash Bottom 50 pin connector used for CompactFlash cards Serial 3 COM3 Top 10 pin 0 1 connector used for the Serial 3 interface J14 Serial 4 Top 10 pin 0 1 connector used for the Serial 4 interface Utility J5 inda ies ll eru Serial 4 J14 di JP6 s afa ajo m ofo ofa m 40 8 Serial 1 J3 COM 4 H B E ojojo ao c 5 1 Serial 3 J13 Serial 2 49 lt 5 0 2 AG E 5 5 5 5 LLLLLLLLLI 7 PPM B SEB cL eee oi GPIO J8 u7 ug us unc ue U11 e a okas Floppy Parallel J4 ps mmm e Video J11 le 9 7 22 E Hes e u14 5 2H Ethernet J2 Ho U13 d pr a c U16 2 USB J10 5m em z P1A S MI E HO Pic 8 J7 P1 JP2 P1D Power J7 PC104 Bus Figur
25. down in size until you have reached an acceptable file size If you are doubtful about the conversion process due to the file size Ampro recommends making a copy of your new splash bmp so that you can edit it later if the conversion does not yield a small enough file Otherwise you may have to re create your custom image before you can edit it down to an acceptable file size 6 If your custom image file is not on the conversion PC copy the new splash bmp file to the conversion directory 7 Run the following command from DOS or a Windows DOS pop up screen to convert your new splash bmp file C splash gt convert convert idf This conversion should yield a splash rle file of approximately 55kB in size or less depending on the complexity of your image 8 Ifthe splash rle file size is greater than 55kB go back to the unconverted image file and edit the file You may reduce the file size of the converted image splash rle by reducing the image s complexity 9 Run the following command to merge the converted image with the BIOS binary file C splash gt resplash cm420 bin splash rle cm420n bin This creates a new BIOS named cm420n bin which has the new splash image This new BIOS is ready to be loaded onto the CoreModule 420 10 Copy the files update bat aflash exe and cm420n bin to a DOS boot floppy 11 Boot the CoreModule 420 from the floppy and run update bat 12 Cycle the power to the CoreModule 420 and enter B
26. in a single chip Memory The CoreModule 420 memory consists of the following elements e SDRAM Flash memory e Bytewide socket SDRAM Memory U7 U8 U9 U10 The CoreModule 420 contains four 16 bit SDRAM chips of 16MB each for a total of 64MB memory soldered into place on the module and operating at 100MHz Flash Memory U6 A IMB flash device is used for system BIOS on the module and 768kB is available for user code The Flash memory also stores system parameters CMOS settings for battery less boot capability when no battery is available Bytewide Socket U5 The CoreModule 420 has a 32 pin DIP socket on the module used as a bytewide memory socket This socket supports DiskOnChip devices A memory device installed in the bytewide socket can be used for e DOC2000 M Systems DiskOnChip e External BIOS BIOS recovery Memory Map Table 3 1 Memory Map Address Size Use 1 0000 0000 256kB Flash ROM BIOS FFFC 0000 130 560kB Unused F804 0000 128kB Ethernet F802 0000 120kB Unused F800 2000 4kB Ethernet F800 1000 4kB USB F800 0000 3824MB Unused 0900 0000 16MB STPC Graphics Memory 0800 0000 64MB Unused Memory Map Table continued on next page 18 Reference Manual CoreModule 420 Chapter 3 Table 3 1 Memory Map continued Hardware Address Size Use 0400 0000 1MB RAM or
27. in to access this service Personal Assistance You may also request personal assistance by going to the Ask a Question area in the Virtual Technician Requests can be submitted 24 hours a day 7 days a week You will receive immediate confirmation that your request has been entered Once you have submitted your request you can go to the My Stuff area and log in to check status update your request and access other features e Embedded Design Resource Center This service is also free and available 24 hours a day at the Ampro web site at http www ampro com However you must be registered online before you can login in to access this service The Embedded Design Resource Center was created as a resource for embedded system developers to share Ampro s knowledge insight and expertise gained from years of experience This page contains links to White Papers Specifications and additional technical information Table A 1 USA Technical Support Contact Information Method Contact Information Virtual Technician http ampro custhelp com Web Site http www ampro com Standard Mail Ampro Computers Incorporated 5215 Hellyer Avenue San Jose CA 95138 1007 USA CoreModule 420 Reference Manual 57 Appendix A Technical Support 58 Reference Manual CoreModule 420 Appendix B Connector Part Numbers These connectors are used on the CoreModule 420 and can be used to determine the mating con
28. need for card cages and backplanes The PC 104 expansion modules can be mounted directly to the PC 104 bus connector of the CoreModule 420 PC 104 compliant modules can be stacked with an inter board spacing of 0 66 inches so that a 3 module system fits in a 3 6 inch by 3 8 inch by 2 4 inch space See Figure 2 1 One or more MiniModule products or other PC 104 modules can be installed on the CoreModule expansion connectors When installed on P1 and P2 the expansion modules fit within the CoreModule outline dimensions Most MiniModule products have stack through connectors compatible with the PC 104 Version 2 5 specification Several modules can be stacked on the CoreModule headers Each additional module increases the thickness of the package by 15mm 0 60 See Figure 2 1 PC 104 Module 4 40 nut 4 CoreModule 420 Stackthrough PC 104 Module Expansion 0 6 inch spacer 4 Ul du d PC 104 Module 5 N 4 40 screw 4 gt il Figure 2 1 Stacking PC 104 Modules with the CoreModule 420 CoreModule 420 Reference Manual 5 Chapter 2 Product Overview Product Description The CoreModule 420 SBC is an exceptionally high integration high performance 486 based PC compatible system in the PC 104 form factor This rugged and high quality single board system
29. onto the bus from the CompactFlash card when the card is configured to use the I O interface 35 IOW I O Write Strobe This signal is generated by the host and clocks the I O data on the Card Data bus into the CompactFlash card controller registers when the card is configured to use the I O interface The clock occurs on the negative to positive edge of the signal trailing edge 36 Vcc 5 volts 5 power supply WE 37 RDY Drive Ready IRQ IRQ 14 is asserted by drive CF when it has a pending interrupt request PIO transfer of data to or from the drive to the host 38 Vcc 5 volts 5 power supply 39 GND Grounded CSEL 40 NC Not Connected VS2 41 IDERst IDE Reset This input signal is the active low hardware reset from the host If this pin goes high it is used as the reset signal This pin is driven high at power up causing a reset and if left high will cause another reset 42 IORDY I O Channel Ready When negated extends the host transfer cycle of any host register access when the drive is not ready to respond to a data transfer request High impedance if asserted 43 NC Not Connected INPACK Input Acknowledge 44 REG Registered Common Memory Access Tied High for Common Memory Access 45 ACT Drive Active Slave Present Tied High for Master Slave handshake protocol SLV 46 NC Not Connected PDIAG Passed Diagnostics 47 D
30. set to Hot Cable use the modified serial cable described in Chapter 3 under Hot Serial Cable 2 Turn on the serial console or the PC with serial terminal emulation and the power supply to the CoreModule 420 3 Start Setup by pressing the Ctl c keys when the following message appears on the boot screen Hit C if you want to run SETUP 4 Use the Enter key to access the Setup screen menus listed in the main BIOS screen The serial console port is not hardware protected but is removed from the COM table during BIOS Setup Diagnostic software that probes hardware addresses may cause a loss or failure of the serial console functions Table 4 1 BIOS Setup Menus BIOS Setup Menu Item Topic BIOS and Hardware Settings Date and Time Drive Configuration Boot Order and Drive and Boot Options Keyboard settings User Interface options Memory settings Power management Advanced Features On Board Features Serial Parallel USB Video etc PCI and Plug and Plug Options Reload Initial Settings Resets the BIOS CMOS to the last know settings Load Factory Default Settings Resets BIOS CMOS to factory settings Exit Saving Changes Writes all changes to BIOS CMOS and exits Exit Discarding Changes Closes BIOS without saving changes except time and date 46 Reference Manual CoreModule 420 Chapter 4 Main BIOS Setup Menu BIOS Setup P IPS BED Ampro Setup U
31. 100MHz Video memory up to 4MB selected in BIOS Setup e CRT Controller Integrated 135MHz triple RAMDAC allowing for 1280 x 1024 x 75Hz display Supports 8 16 and 24 bit pixels Interlaced or non interlaced output e TFT Display Controller Conforms with VESA Flat Panel Display Interface FPDI 1B Supports both 4 3 and 16 9 screen size ratio Supports up to 1024 x 768 pixel display resolutions Uses Internal CRTC Controller for display modes settings Supports VGA and SVGA active matrix panels with 9 12 18 bit Interface 1 pixel clock Supports XGA and SXGA active matrix panels with 2x9 bit Interface 2 pixels clock Programmable image position and size Programmable blank space insertion in text mode Programmable horizontal and vertical image expansion in graphic mode Two fully programmable PWM Pulse Width Modulator signals to adjust the flat panel brightness and contrast Supports PanelLinkTM high speed serial transmitter externally for high resolution panel interface The video interface LCD CRT uses a 44 pin 2mm header with pin outs shown in Table 3 17 38 Reference Manual CoreModule 420 Chapter 3 Hardware Table 3 17 Video Interface Pin Signal Descriptions J11 Pin Signal Description 1 TFTDCLK TFT Shift Clock This clock signal provides the timin
32. 16 Ethernet Interface Pin Signal Descriptions J2 Pin Signal Description 1 TX Analog Twisted Pair Ethernet Transmit Differential Pair These pins transmit the 2 TX serial bit stream through the isolation transformer on the Unshielded Twisted Pair Cable UTP 3 RX Analog Twisted Pair Ethernet Receive Differential Pair These pins receive the 6 RX serial bit stream through the isolation transformer 4 NU Not Used RJ45 termination 3 NU Not Used RJ45 termination 7 NU Not Used RJ45 termination 8 NU Not Used RJ45 termination Note NU Not Used CoreModule 420 Reference Manual 37 Chapter 3 Hardware Video LCD CRT Interface J11 The STPC Atlas chip provides the 2D graphics controller for the video signals to a flat panel display and traditional glass CRT monitor The features are listed below e Enhanced 2D Graphics Controller Supports Pixel Depths of 8 16 24 and 32 bit Full BitBLT Implementation for all 256 Raster Operations Defined for Windows Supports 4 Transparent BLT Modes Bitmap Transparency Pattern Transparency e Source Transparency e Destination Transparency Hardware Clipping Fast Line Draw Engine with anti aliasing Fast Triangle Fill Engine Supports 4 bit Alpha Blend Font for anti aliased text display Complete Double Buffered Registers for pipelined operation 64 bit wide Pipelined Architecture running at
33. 25 A25 SA6 System Address 6 Refer to SA19 pin A12 for more information 26 A26 SAS System Address 5 Refer to SA19 pin A12 for more information 22 Reference Manual CoreModule 420 Chapter 3 Hardware Pin Signal Description P1 Row A 27 A27 SA4 System Address 4 Refer to SA19 pin A12 for more information 28 A28 SA3 System Address 3 Refer to SA19 pin A12 for more information 29 A29 SA2 System Address 2 Refer to SA19 pin A12 for more information 30 A30 SAI System Address 1 Refer to SA19 pin A12 for more information 31 A31 SAO System Address 0 Refer to SA19 pin A12 for more information 32 A32 GND Ground Notes The shaded area denotes power or ground The signals marked with indicate active low Table 3 6 PC 104 Bus Interface Pin Signal Descriptions P1B Pin 4 Signal Description P1 Row B 33 B1 GND Ground 34 B2 RstDrv Reset Drive This signal is used to reset or initialize system logic on power up or subsequent system reset 35 B3 5V 5V power 10 36 B4 IRQ9 Interrupt Request 9 Asserted by a device when it has pending interrupt request Only one device may use this request line at a time 37 B5 NC 5V Not connected 5 volts 38 B6 DRQ2 DMA Request 2 Used by I O resources to request DMA service or to request ownership of the bus as a bus master device Must be held high until a
34. 3 Disk Data 13 Refer to pin 3 D7 for more information 15 D1 Disk Data 1 Refer to pin 3 D7 for more information 16 14 Disk Data 14 Refer to pin 3 D7 for more information 17 DO Disk Data 0 Refer to pin 3 D7 for more information 18 D15 Disk Data 15 Refer to pin 3 D7 for more information 19 GND Digital Ground 20 Key GND Key pin plug Ground 21 PDRQ Request Used for DMA transfers between host and drive direction of transfer controlled by PIOR and PIOW Also used in an asynchronous mode with PDACK Drive asserts when ready to transfer or receive data 22 GND Digital Ground 23 PIOW Drive I O Write Strobe signal for write functions Negative edge enables data from a register or data port of the drive onto the host data bus Positive edge latches data at the host 24 GND Digital Ground CorModue420 Reference 27 Chapter 3 28 Hardware Pin Signal Description 25 PIOR Drive I O Read Strobe signal for read functions Negative edge enables data from a register or data port of the drive onto the host data bus Positive edge latches data at the host 26 GND Digital Ground 27 IOChRdy I O Channel Ready When negated extends the host transfer cycle of any host register access when the drive is not ready to respond to a data transfer request High impedance if asserted 28 Reserv
35. 8 Disk Data 8 Refer to pin 2 D3 for more information 48 D9 Disk Data 9 Refer to pin 2 D3 for more information 49 D10 Disk Data 10 Refer to pin 2 D3 for more information 50 NC Not Connected CD2 Notes The shaded area denotes power or ground The signals marked with Negative true logic NC Not connected NU Not used 30 Reference Manual CoreModule 420 Chapter 3 Hardware Floppy Parallel Port J4 Floppy Disk Drive Port The Super I O chip provides the Floppy Disk Controller and the Parallel Port interface J4 The Floppy Drive interface shares the same connector as the Parallel Port and the signals are multiplexed out of the connector However you can only use one of these devices at a time and it must be configured in BIOS Setup Utility The default device in the BIOS Setup Utility is the Floppy Drive The Floppy Disk Controller supports two floppy disk drives from 360kB through 2 88MB and is configured as the floppy interface in the BIOS Due to the multiplexed nature of the signals for the floppy disk and parallel connector you can only connect one of these devices at a time Refer to Chapter 4 BIOS Setup later in this manual when selecting the floppy or Parallel Port The Super I O chip provides the Parallel Port interface and Floppy Disk Controller which share the same output connector J4 The Parallel Port supports the standard parallel Bi directional Standard Printer Port SPP Enh
36. IOS Setup to enable the splash screen 54 Reference Manual CoreModule 420 Chapter 4 BIOS Setup On Board Flash Access and Use This section describes how to use the on board flash memory and load an application in the available lower 768kB region of the 1MB of Flash Memory The application can boot directly from the on board flash memory The Flash memory can be accessed at 128MB intervals above the base address with the exception of 256MB For example if the Flash address is set to 8MB then the Flash memory can be accessed at 136MB 392MB 520MB etc CAUTION To prevent a system crash or unusable BIOS do not overwrite the BIOS The entire 1MB of Flash is accessible but only the lower 768kB region is available for custom applications The higher 256kB region is used for the BIOS and can be overwritten rendering the CoreModule 420 unbootable Flash Programming Requirements To build an example application under DOS or in a Windows DOS pop up screen you need to have one of the following tools e Microsoft Visual C 7 0 This is a commercial product and is available from Microsoft It can be downloaded as part of the Framework from http msdn microsoft com The compiler is part of the Microsoft NET Framework V1 1 Software Development Kit and the NET Framework Redistributable Package V1 1 Both of these need to be downloaded and installed e Open Watcom C C 32 1 1 This is a commercial compiler product availa
37. OS setup and does not attempt to describe the BIOS functions Refer to the appropriate PC reference manuals for information about the software interface of the onboard ROM BIOS If Ampro has added to or modified the standard functions these functions will be described The options provided for the CoreModule 420 are controlled by the BIOS Setup Utility BIOS Setup is used to configure the CoreModule 420 features modify the fields in the Setup screens and save the results in the onboard configuration memory Configuration memory consists of portions of the CMOS RAM in the battery backed real time clock chip and the flash memory The Setup information is retrieved from configuration memory when the module is powered up or when it is rebooted Changes made to the Setup parameters with the exception of the time and date settings do not take effect until the module is rebooted Setup is located in the ROM BIOS and can be accessed when prompted using the lt Del gt key while the module is in the Power On Self Test POST state just before completing the boot process The screen displays a message indicating when you can press lt Del gt The CoreModule 420 Setup is used to configure items in the BIOS using the following menus e BIOS and Hardware Settings Reload Initial Settings Load Factory Default Settings e Exit Saving Changes e Exit Discarding Changes The main BIOS Setup menu offers the menu choices listed above and the related
38. SB Port J10 The CoreModule 420 contains one root USB Universal Serial Bus hub and one functional USB port The USB function is provided by the STPC ATLAS CPU U14 Features implemented in the USB port include the following One root hub with one USB port USB v 1 1 and Universal OHCI v 1 0 compatible Over current detection status is provided by STPC ATLAS CPU pin D21 Supports a fuse F1 1 5A for over current protection Table 3 14 USB Interface Pin and Signal Designations J10 Pin Signal Description 1 USBPWR USB Power power 5 to port through fuse Port is disabled if this input is low 2 USBPN USB Port Data Negative 3 USBPP USB Port Data Positive 4 GND USB Port ground 5 SHIELD USB Port shield Notes The shaded area denotes power or ground CoreModule 420 Reference Manual 35 Chapter 3 Hardware Utility Interface J5 The Utility interface consists of the 10 pin 0 1 header on the module and is used as the interface for various utility signals The Super I O chip drives most of the device interfaces on the Utility interface Table 3 15 shows the meaning of the interface signals for the utility interface Keyboard and PS 2 Mouse e Battery e Reset Switch e Speaker Keyboard The signal lines for an AT or PS 2 keyboard are provided through the Utility interface J5 to the Super I O controller U13 Refer to Table 3 15 for pin signal informati
39. Shadow D800 DBFF Disabled or Enabled Shadow DC00 DFFF Disabled or Enabled e Power Management APM Disabled or Enabled e Advanced features 50 Post Memory Manager Disabled or Enabled Watchdog Timeout sec select whole number between 1 and 255 seconds in 1 second increments or Disabled Reference Manual CoreModule 420 Chapter 4 BIOS Setup This feature if enabled by selecting a timer interval will direct the watchdog timer to reset the system if it fails to boot the OS properly Serial Console Hot Cable or Enabled Hot Cable option only allows console redirection when a Hot Cable is actually connected to Serial 1 or 2 COM 1 or 2 The Hot Cable option can not be used on Serial 3 or 4 COM 3 or 4 Use the modified serial cable described in Chapter 3 under Hot Serial Cable The Enabled option instructs the BIOS to operate in the serial console console redirection mode at all times with the serial port selected in the Serial Console gt Port field listed below This option can be used on any of the Serial ports Serial 1 2 3 or 4 Use a standard null modem serial cable However connecting a Hot Cable to the other port port not selected overrides the setting of this field Enabled and the Serial Console gt Port field Port 3F8h 2F8h 3E8h 2E8h This field selects the COM Serial port address used for conso
40. active low Reference Manual CoreModule 420 Chapter 3 Hardware IDE Interface J6 The IDE device signals are provided through the standard 44 pin 2mm connector J6 The IDE interface supports the following features Master mode PCI supporting Enhanced IDE devices Supports two EIDE devices Full scatter gather capability Supports ATAPI compliant devices including DVD Supports IDE native and ATA compatibility modes Table 3 9 gives the signals for the 44 pins of the IDE 2mm header Table 3 9 IDE Interface Pin Signal Descriptions J6 Pin Signal Description 1 RESET Low active hardware reset RSTDRV inverted 2 GND Digital Ground 3 D7 Disk Data 7 These pins 0 to 15 provide disk data 4 D8 Disk Data 8 Refer to pin 3 D7 for more information 5 D6 Disk Data 6 Refer to pin 3 D7 for more information 6 D9 Disk Data 9 Refer to pin 3 D7 for more information 7 D5 Disk Data 5 Refer to pin 3 D7 for more information 8 D10 Disk Data 10 Refer to pin 3 D7 for more information 9 D4 Disk Data 4 Refer to pin 3 D7 for more information 10 D11 Disk Data 11 Refer to pin 3 D7 for more information 11 D3 Disk Data 3 Refer to pin 3 D7 for more information 12 D12 Disk Data 12 Refer to pin 3 D7 for more information 13 D2 Disk Data 2 Refer to pin 3 D7 for more information 14 D1
41. als Write Protect Senses the diskette is write protected WRPRT CoreModule 420 Reference Manual 31 Chapter 3 Hardware Pin Signal Description 8 SLIN Select In This output signal is used to select the printer I O pin in ECP EPP mode STEP Step Low step pulse for each track to track movement of the head 9 PD3 Parallel Port Data 3 This pin 0 to 7 provides parallel port data signals RDATA Read Data Raw serial bit stream from the drive for read operations 10 GND Digital Ground 11 PD4 Parallel Port Data 4 This pin 0 to 7 provides parallel port data signals DskChg Disk Change Senses the drive door is open or the diskette has been changed since the last drive selection 12 GND Digital Ground 13 PD5 Parallel Port Data 5 This pin 0 to 7 provides parallel port data signals 14 GND Digital Ground 15 PD6 Parallel Port Data 6 This pin 0 to 7 provides parallel port data signals 16 GND Digital Ground 17 PD7 Parallel Port Data 7 This pin 0 to 7 provides parallel port data signals 18 GND Digital Ground 19 Ack Acknowledge This is a status output signal from the printer A Low State indicates it has received the data and is ready to accept new data DS1 Drive Select 1 Selects floppy drive 1 20 GND Digital Ground 21 Busy Busy This is a Status output signal from the printer A High State indicates the printer is not ready to accept d
42. anced Parallel Port EPP and Enhanced Capabilities Port ECP protocols Table 3 11 Parallel Interface SPP Pin Signal Descriptions J4 parallel device in the BIOS Setup Utility Pin Signal Description 1 Strobe Strobe This is an output signal used to strobe data into the printer I O pin in ECP EPP mode 2 AutoFD Auto Feed This is a request signal into the printer to automatically feed one line after each line is printed Floppy Drive Density Select 0 This signal indicates a low 250 300kbps or DRVO high 500kbps data rate has been selected 3 PDO Parallel Port Data 0 This pin 0 to 7 provides parallel port data signals INDEX Index Sense detects the head is positioned over the beginning of a track 4 ERR Error This is a status output signal from the printer A Low State indicates an error condition on the printer HDSEL Head Select Selects the side for Read Write operations 0 side 1 1 side 0 5 PDI Parallel Port Data 1 This pin 0 to 7 provides parallel port data signals TRKO Track 0 Indicates when the head is positioned over track 0 outermost track 6 INIT Initialize This signal is used to Initialize printer Output in standard mode I O in ECP EPP mode DIR Direction This signal determines direction of head movement 0 inward motion outward motion 7 PD2 Parallel Port Data 2 This pin 0 to 7 provides parallel port data sign
43. ata MTRI Motor Control 1 Selects or enables the motor on floppy drive 1 22 GND Digital Ground 23 PE Paper End This is a status output signal from the printer A High State indicates it is out of paper WDATA Write Data Encoded data to the drive for write operations 24 GND Digital Ground 25 Slct Select This is a status output signal from the printer A High State indicates it is selected and powered on WGATE Write Gate Signal to the drive to enable current flow in the write head 26 Key NC Key Pin Not Connected Notes The shaded area denotes power or ground The signals marked with indicate active low 32 Reference Manual CoreModule 420 Chapter 3 Hardware Serial Ports J3 J9 J13 J14 The Atlas CPU and Super I O chips each contain the circuitry for two of the four serial ports The Atlas CPU provides serial port J3 and serial port 2 J9 through the two independent 10 pin connectors The Super I O chip provides serial ports 3 J13 and 4 J14 The serial ports support the following features Programmable word length stop bits and parity 16 bit programmable baud rate generator Interrupt generator Loop back mode 16 bit FIFOs for each port e Ports 1 and 2 are supported by the STPC Atlas processor and are 15540 compatible Serial 1 J3 COMI supports RS232 RS485 and has full modem operation Serial 2 J9 COMO supports RS232 RS485 and has full modem operation Po
44. ble from ttp Www openwatcom org It is also included on the CoreModule 420 Doc amp SW CD ROM in the cm420 software examples flash watcom directory e Other versions of the above tools may also work The following example application is also necessary and is provided by Ampro e Example application This application can be found in the cm420 software examples flash watcom or cm420 software examples flash msvc directory for the Watcom compiler or Visual C compiler respectively This example application will be described in more detail in the following procedures Building the Example Ampro provides an example for flash programming found on the CoreModule 420 Doc amp SW CD ROM under Miscellaneous Source Code Examples in the Support Software directory The example actually consists of two parts e Example application The example application shows how C compiler can be used to generate a 32 bit application which runs without an Operating System First build this application using the make bat file The make bat file will build app exe Bootloader The bootloader can be found in bootsec asm and the final Flash image is built with image asm You can use make bat to build the bootloader and Flash image in the cm420 software examples flash CoreModule 420 Reference Manual 55 Chapter 4 BIOS Setup Example Assumptions The following assumptions have been made concerning the application and certain functio
45. contains all the component subsystems of a PC AT motherboard plus the equivalent of several PC AT expansion boards In addition the CoreModule 420 SBC includes a comprehensive set of system extensions and enhancements that are specifically designed for embedded systems These enhancements ensure fail safe embedded system operation such as a watchdog timer It is designed to meet the size power consumption temperature range quality and reliability demands of embedded applications The CoreModule 420 requires a single 5 V power source The CoreModule 420 SBC is particularly well suited to either embedded or portable applications Its flexibility makes system design quick and easy It can be stacked with Ampro MiniModules or other PC 104 compliant expansion or it can be used as the computing engine in a fully customized application Module Features CPU Supports 133MHz x86 based STPC ATLAS microprocessor Fully PC compatible architecture 8kB Unified Instruction and Data Cache Parallel Processing Integrated Floating Point Unit Low Power and System Management Modes e Memory 64MB standard SDRAM soldered on the board 100MBz Clock Speed 32 pin bytewide memory socket e Supports a DiskOnChip device 1MB Flash memory e Stores system BIOS e Stores system Setup parameters and manufacturing information e Supports battery free boot capability 768kB available for OEM use e PC 104 Bus Interface Clock speeds up to 8 25MH
46. ctive 33 D12 DAck6 DMA Acknowledge 6 Used by DMA controller to select the I O resource requesting the bus or to request ownership of the bus as a bus master device Can also be used by the ISA bus master to gain control of the bus from the DMA controller 34 D13 DRQ6 DMA Request 6 Used by I O resources to request DMA service Must be held high until associated DACK6 line is active 35 D14 DAck7 DMA Acknowledge 7 Used by DMA controller to select the I O resource requesting the bus or to request ownership of the bus as a bus master device Can also be used by the ISA bus master to gain control of the bus from the DMA controller 36 D15 DRQ7 DMA Request 7 Used by I O resources to request DMA service Must be held high until associated DACK7 line is active 37 D16 5 5V Power 10 38 D17 Master Bus Master Assert This signal is used by an ISA board along with a DRQ line to gain ownership of the ISA bus Upon receiving a DACK a device can pull MASTER low which will allow it to control the system address data and control lines After MASTER is low the device should wait one CLK period before driving the address and data lines and two clock periods before issuing a read or write command 39 D18 GND Ground 40 D19 GND Ground Notes The shaded area denotes power or ground The signals marked with indicate
47. ctly 640x480 pixels e Exactly 16 colors Aconverted file size of not greater than 55kB Converting the Splash Screen File The following files are provided by Ampro on the CoreModule 420 Doc amp SW CD ROM and are required for converting a custom splash screen file Refer to the Miscellaneous Source Code Examples subdirectory under the Support Software directory on the CD ROM for the utilities and examples of how to load a customized image in the cm420 software examples splash directory e splash bmp resplash com convert exe cm420 bin convert idf The process of converting and loading a custom image onto the CoreModule 420 involves the following sequence of events e Prepare directory for conversion create directory and copy files into it e Obtain the CoreModule 420 BIOS binary e Prepare the custom image file e Convert the image to an acceptable BIOS format e Merge the image with BIOS binary to create new BIOS binary e Load the new BIOS binary onto the CoreModule 420 board You can use any Windows PC to convert the custom image but your PC must have an internet browser to access view and make selections in the main menu of the CoreModule 420 Doc amp SW CD ROM For example Microsoft Internet Explorer 4 x or greater Netscape Navigator version 4 x or greater or the equivalent CoreModule 420 Reference Manual 53 Chapter 4 BIOS Setup Use the following steps to convert and load your custom image onto the Cor
48. d CoreModule 420 Reference Manual 15 Chapter 2 Product Overview 16 Reference Manual CoreModule 420 Chapter 3 Hardware Overview This chapter discusses the chips and connectors of the module features in the following order CPU U14 Memory SDRAM 07 U8 U9 010 Flash Memory U6 Bytewide socket US PC 104 P1A B C D IDE J6 CompactFlash J12 Serial J3 J9 J13 J14 Floppy Parallel J4 Utility J5 Keyboard Mouse Battery Reset Switch Speaker Ethernet J2 USB J10 Video J11 Miscellaneous Time of Day RTC User GPIO J8 Oops Jumper BIOS Recovery Watchdog timer Power J7 Ampro Computers Inc only supports the features options tested and listed in this manual The main integrated circuits chips used in the CoreModule 420 may provide more features or options than are listed for the CoreModule 420 but some of these features options are not supported on the module and will not function as specified in the chip documentation CoreModule 420 Reference Manual 17 Chapter 3 Hardware CPU U14 The CoreModule 420 uses an embedded microprocessor operating at 133MHz that combines a powerful x86 core and a selection of peripheral interfaces into one chip The STPC Atlas integrates a standard 5th generation x86 core It supports logic including PC 104 UIDE controllers and combines these with standard I O interfaces to provide a PC compatible subsystem
49. d Each EnCore module provides standard peripherals including IDE floppy drive interface PCI bus serial parallel PS 2 keyboard and mouse interfaces 10 100BaseT Ethernet and USB ports Some EnCore modules also provide video and AC97 sound Depending on the model EnCore modules can hold between 16MB and 512MB of SODIMM SDRAM memory CoreModule 420 Reference Manual 3 Chapter 1 About this Manual 4 Reference Manual CoreModule 420 Chapter 2 Product Overview This introduction presents general information about the PC 104 architecture and the CoreModule 420 single board computer SBC After reading this chapter you should understand PC 104 Concept e CoreModule 420 architecture e CoreModule 420 features Major components e Connectors e Specifications PC 104 Architecture The PC 104 architecture affords a great deal of flexibility in system design You can build a simple system using only a CoreModule 420 with input output devices connected to its serial or parallel ports and a solid state disk drive or CompactFlash card in the respective bytewide socket or CompactFlash socket To expand a simple CoreModule system simply add self stacking Ampro MiniModules or 3 party PC 104 expansion boards to provide additional capabilities such as e Additional serial and parallel ports e Analog or digital e PCMCIA interfaces e Sound cards PC 104 expansion modules can be stacked with the CoreModule 420 avoiding the
50. ding interrupt request Only one device may use the request line at a time 26 D5 IRQI2 Interrupt Request 12 Asserted by a device when it has pending interrupt request Only one device may use the request line at a time 27 D6 IRQIS Interrupt Request 15 Asserted by a device when it has pending interrupt request Only one device may use the request line at a time 28 07 IRQ14 Interrupt Request 14 Asserted by a device when it has pending interrupt request Only one device may use the request line at a time 29 D8 DAck0 DMA Acknowledge 0 Used by DMA controller to select the I O resource requesting the bus or to request ownership of the bus as a bus master device Can also be used by the ISA bus master to gain control of the bus from the DMA controller 30 D9 DRQO DMA Request 0 Used by I O resources to request DMA service Must be held high until associated DACKO line is active CoreModule 420 Reference Manual 25 Chapter 3 26 Hardware Pin Signal Description P1 Row D 31 D10 DAck5 DMA Acknowledge 5 Used by DMA controller to select the I O resource requesting the bus or to request ownership of the bus as a bus master device Can also be used by the ISA bus master to gain control of the bus from the DMA controller 32 D11 DRQS DMA Request 5 Used by I O resources to request DMA service Must be held high until associated DACKS line is a
51. e 2 4 Connector Locations Top View CoreModule 420 Reference Manual 11 Chapter 2 Jumper Definitions Table 2 3 Jumper Settings Table 2 3 describes the jumpers shown in Figure 2 5 Product Overview Jumper Installed Removed JP1 Serial Port 1 Enable RS485 Termination Disable RS485 Termination Termination Pins 1 2 No jumper Default setting JP2 Serial Port 2 Enable RS485 Termination Disable RS485 Termination Termination Pins 1 2 No jumper Default setting JP4 amp JP5 Enable Internal BIOS Normal operation Disabled Won t Boot BIOS DCC Select Pins 1 3 on both JP4 amp JP5 See other positions JP5 JP4 Enable External BIOS Used for recovery Disabled Won t Boot HE PE Pins 1 2 on both JP4 amp JP5 See other positions BIOS DOC Select Jumper Setting Shown in Default Enable DOC Boot from DiskOnChip in bytewide socket Pins 1 3 amp 2 4 on both JP4 amp JP5 Default setting Disabled Won t Boot See other positions JP6 3 3 Volts Pins 1 2 5 Volts Pins 2 3 Flat Panel Voltage Selection JP7 Access from DC000h DDFFFh Access from CC000h CDFFFh DiskOnChip Boot Pins 1 2 No jumper Address Select JP8 Serial Port 1 Enable Serial Port 1 Disabled Serial Port 1 Pins 1 2 Default setting Pins 2 3 JP9 Serial Port 2 Enable Serial Port 2 Disabled Serial Port 2 Pins 1 2 Default setting Pins 2 3 LED Definitions Table 2 4 Ethe
52. e 420 QuickStart Guide and the CoreModule 420 Development System Users Guide in PDF format release notes software utilities and drivers Other CoreModule Products CoreModule 410 This PC 104 embedded CPU is a state of the art high integration x86 based computer using STMicroelectronics 133MHz STPC Elite processor which provides a complete embedded PC solution with most of the standard peripheral interfaces In addition to the standard CoreModule features PC 104 form factor PC 104 bus 5 volt power etc it includes 16MB soldered SDRAM memory watchdog timer serial console BIOS extensions for OEM boot customization and Advanced Power Management The CoreModule 410 also offers a Bytewide socket supporting DiskOnChip 2000 devices and a GPIO interface for customer usage CoreModule 600 This PC 104 Plus embedded single board computer SBC is a compact rugged high integration ultra low power 400MHz ULV Celeron processor with 256kB of internal cache and all of the standard peripheral interfaces In addition to the standard CoreModule features PC 104 form factor PC 104 Plus 5 volt power etc the CoreModule 600 includes 10 100BaseT Ethernet AGP 4X video with 32MB video memory for CRT TFT and standard LCD flat panels USB ports RS232C RS485 serial ports and an onboard Type II CompactFlash socket which supports up to 1GB or more of flash memory The CoreModule 600 also supports a watchdog timer serial console batter
53. e is used for the keyboard and determines the typing rate Initialize PS 2 Mouse Disabled or Enabled e User Interface Show Hit lt Del gt Disabled or Enabled This feature if Enabled will place Hit lt Del gt on screen during the boot process to indicate when you may select lt Del gt to enter the BIOS Setup menus F1 Error Wait Disabled or Enabled This feature if Enabled will display an Error message indicating when an error has occurred and wait for you to respond by hitting the F1 key Config Box Disabled or Enabled This feature if Enabled displays the Configuration Summary Box which list all of the configuration information for the system at the completion of POST but before the Operating System is loaded Splash Screen Disabled or Enabled This feature enables the Splash Screen and displays a default or customized splash screen Refer to the Splash Screen Customization topic later in this chapter for instructions on how to customize the splash screen e Memory Memory Test Fast Standard or Exhaustive Memory Hole Disabled 1MB 2MB 4MB or SMB Flash Address Disabled BMB MB 10MB 11MB 12MB 13MB 14MB or 15MB Shadow C800 CBFF Disabled or Enabled Shadow CC00 CFFF Disabled or Enabled Shadow D000 D3FF Disabled or Enabled Shadow D400 D7FF Disabled or Enabled
54. e serial terminal or PC with communications software must be set to the following values e 115k baud e 8 bits One stop bit No parity No hardware handshake Hot Serial Cable The serial console settings in the BIOS can be overridden by connecting a modified serial cable or Hot Cable between either serial port J3 or J9 and the serial terminal or the PC with communications software set to the appropriate values outlined above To convert a standard serial cable to a Hot Cable certain pins must be shorted together at the Serial port connector or at the DB9 connector Short together the RTS 4 and RI 8 pins on either serial port J3 or J9 header As an alternate you can short the equivalent pins pins 7 and 9 on the respective DB9 port connector as shown in Figure 3 3 97531 12345 2 Serial Port 1 J3 Standard DB9 Serial Or Port Connector Female 8 Side View Rear View 3 108642 6789 gt Figure 3 3 Hot Cable Jumper Watchdog Timer 42 The watchdog timer WDT restarts the system if a mishap occurs ensuring proper start up after the interruption Possible problems include failure to boot properly the application software s loss of control failure of an interface device unexpected conditions on the bus or other hardware or software malfunctions The WDT watchdog timer can be used both during the boot process and during normal system operation e During the Boot proces
55. e when it has pending interrupt request Only one device may use the request line at a time 56 B24 IRQ4 Interrupt Request 4 Asserted by a device when it has pending interrupt request Only one device may use the request line at a time 57 B25 Interrupt Request 3 Asserted by a device when it has pending interrupt request Only one device may use the request line at a time 58 B26 DAck2 DMA Acknowledge 2 Used by DMA controller to select the I O resource requesting the bus or to request ownership of the bus as a bus master device Can also be used by the ISA bus master to gain control of the bus from the DMA controller 59 B27 TC Terminal Count This signal is a pulse to indicate a terminal count has been reached on a DMA channel operation 60 B28 BALE Buffered Address Latch Enable This signal is used to latch the LA23 to LA17 signals or decodes of these signals Addresses are latched on the falling edge of BALE It is forced high during DMA cycles When used with it indicates a valid processor or DMA address 61 B29 5V 5V power 10 62 B30 OSC Oscillator This clock signal operates at 14 3MHz This signal is not synchronous with the system clock SYSCLK 63 B31 GND Ground 64 B32 GND Ground Notes The shaded area denotes power or ground The signals marked with indicate active low Table 3 7 PC 104 Bus Interface Pin Signal Descriptions P1C
56. eModule 420 1 Copy the files from the CM420 software examples splash directory on the CD ROM to a new directory conversion directory on your PC This new conversion directory is where you intend to do the conversion and save the file 2 Ensure you remove the read only attributes from all the files as part of the file copying process 3 Copy the CoreModule 420 BIOS binary file cm420 bin to the new conversion directory on your PC where the other files and utilities are located If this file is not on the CoreModule 420 Doc amp SW CD ROM you will have to obtain it from Ampro Ampro recommends keeping a copy of this original cm420 bin file just in case you encounter problems with your new file or have difficulty updating the BIOS with the new image 4 Prepare your custom image file with any Windows bitmap software editing tool For example Corel Photo Paint Adobe Photoshop or the Windows Paint program provided with Windows You can insert a desired graphic image logo text etc into the file The custom image must be a bitmap image in bmp format at 640x480 pixels and it must be 16 colors The file should be about 153 718 bytes Refer to the example file splash bmp 5 Save your custom image file as splash bmp at 640x480 pixels by 16 colors If your custom image file is not approximately 153 718 bytes in size it is probably not in the right format or is too complex to be used in the BIOS You will have to edit it
57. ecting a valid address decode and an active read or write command The signal is released high when the device is ready to complete the cycle 11 A11 AEn Address Enable This signal is reserved for the ISA Bus and is asserted during DMA cycles to prevent I O slaves from misinterpreting DMA cycles as valid I O cycles 12 12 SA19 System Address 19 This signal 0 to 19 provides a system address bit 13 13 SA18 System Address 18 Refer to SA19 pin A12 for more information 14 A14 SA17 System Address 17 Refer to SA19 pin A12 for more information 15 A15 5 16 System Address 16 Refer to SA19 pin A12 for more information 16 A16 SAI5 System Address 15 Refer to SA19 pin A12 for more information 17 17 SA14 System Address 14 Refer to SA19 pin A12 for more information 18 A18 SA13 System Address 13 Refer to SA19 pin A12 for more information 19 A19 SAI2 System Address 12 Refer to SA19 pin A12 for more information 20 20 SA11 System Address 11 Refer to SA19 pin A12 for more information 21 A21 SA10 System Address 10 Refer to SA19 pin A12 for more information 22 22 SA9 System Address 9 Refer to SA19 pin A12 for more information 23 23 SA8 System Address 8 Refer to SA19 pin A12 for more information 24 A24 SA7 System Address 7 Refer to SA19 pin A12 for more information
58. ed Reserved Not used through 470 ohm resistor to ground 29 PDACK DMA Channel Acknowledge Used by the host to acknowledge data has been accepted or data is available Used in response to DMARQ asserted 30 GND Digital Ground 31 PIRQ Interrupt Request Asserted IRQ 14 by drive when it has pending interrupt request PIO transfer of data to or from the drive to the host 32 NC Not connected 33 18 Latch Address 18 Used to indicate which byte the ATA command block or control block is being accessed 34 NC Not connected through 0 047 uf capacitor to ground 35 17 Latch Address 17 Used to indicate which byte the ATA command block or control block is being accessed 36 19 Latch Address 19 Used to indicate which byte in ATA command block or control block is being accessed 37 IDE PCSI IDE Chip Select 1 Used to select the host accessible Command Block Register 38 IDE PCS3 IDE Chip Select 3 Used to select the host accessible Command Block Register 39 Reserved Reserved Not used 40 GND Digital Ground 41 45V 5 volts 5 power supply 42 45V 5 volts 5 power supply 43 GND Digital Ground 44 NC Not connected Notes The shaded area denotes power or ground The signals marked with indicate active low Reference Manual CoreModule 420 Chapter 3 Hardware CompactFlash Socket J12 The board contains a Type II PC card connector which allows for the in
59. ed e On Board Controllers Primary IDE Disabled or Enabled Secondary IDE Disabled or Enabled PS 2 Mouse IRQ none 1 3 4 5 6 7 8 9 10 11 or 12 CoreModule 420 Reference Manual 51 Chapter 4 52 BIOS Setup USB IRQ none 1 3 4 5 6 7 9 10 11 12 14 or 15 Ethernet IRQ none 1 3 4 5 6 7 9 10 11 12 14 or 15 ISA Speed 7 16 MHz or 8 25 MHz CPU 11 Cache Disabled Write Back or Write Through No Lock Cycles Disabled or Enabled Plug and Play PnP BIOS Disabled or Enabled PnP OS Disabled or Enabled Assign IRQ 1 Assign IRQ 3 Assign IRQ 4 Assign IRQ 5 Assign IRQ 6 Assign IRQ 7 Assign IRQ 9 Assign IRQ 10 Assign IRQ 11 Assign IRQ 12 Assign IRQ 14 Assign IRQ 15 Assign DMA 0 Assign DMA 1 Assign DMA 2 Assign DMA 3 Assign DMA 5 Assign DMA 6 Assign DMA 7 Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled Disabled or Enabled J or Disabled or Enabled or or
60. eference Manual CoreModule 420 Chapter 3 Hardware Ethernet Interface J2 The Ethernet solution is provided by the Intel 82551ER PCI controller chip and consists of both the Media Access Controller MAC and the physical layer PHY combined into a single component solution The 82551ER is a 32 bit PCI controller that features enhanced scatter gather bus mastering capabilities which enables the 82551ER to perform high speed data transfers over the internal PCI bus The 82551ER bus master capabilities enable the component to process high level commands and perform multiple operations thereby off loading communication tasks from the system CPU The Ethernet interface offers the following features Full duplex or half duplex support Full duplex support at 10Mbps or 100Mbps In full duplex mode the 82551ER adheres to the IEEE 802 3x Flow Control specification In half duplex mode performance is enhanced by a proprietary collision reduction mechanism IEEE 802 3 10 100BaseT compatible physical layer to wire transformer Two on board LEDs support the speed and the link and activity status 10BaseT auto polarity correction Data transmission with minimum interframe spacing IFS IEEE 802 3x auto negotiation support for speed and duplex operation 3kB transmit and 3kB receive FIFOs helps prevent data underflow and overflow IEEE 802 3x 100BaseTX flow control support Table 3 16 describes the pin outs of the Ethernet connector J2 Table 3
61. el display resolution Supports VGA and SVGA active matrix TFT flat panels Support internal CRT controller for display mode settings Supports 9 12 and 18 bit interface 1 Pixel Clock Supports 2x9 bit interface 2 Pixels Clock Supports programmable image position Supports 3 3V or 5V LCD panels jumper selectable Video BIOS customization tools provided Miscellaneous Battery backed real time clock and CMOS RAM with support for battery free operation General Purpose I O GPIO Oops Jumper BIOS Recovery Serial Console or Console Redirection Watchdog Timer Reference Manual CoreModule 420 Chapter 2 Block Diagram Figure 2 2 shows the functional components of the module Product Overview CoreModule 420 Figure 2 2 CoreModule 420 Block Diagram Reference Manual Internal PCI Bus Memory gt Ethernet SDRAM E Controller STPC Atlas 2 gt Interface Video CRT TFT 4 lt USB Port Speaker gt Host GPIOs 8 Peripheral Serial Ports ys Interface IDE Devices Serial 1 amp 2 4 gt CompactFlash CD ROM etc PC 104 Interface ISA Dus DiskOnChip BIOS Floppy Drive RTC Parallel Port Super 1 0 Controller Serial Ports 4 Utility Interface Serial 3 amp 4
62. elect Load Factory Default Settings which will automatically load and save the defaults and reboot the system Then you can modify the default settings to your desired values Ensure you save the changes before rebooting the system The CoreModule 420 Serial Port 1 J3 is a 10 pin header and uses pin 7 DTR and pin 8 At Serial Port 1 short pin 7 to 8 as shown in Figure 3 2 Alternatively you may short the equivalent pins on the DB9 connector attached to Serial Port 1 as shown in Figure 3 2 97531 12345 Serial Ports J3 9 Standard DB9 Serial COM1 or CON Or Port Connector Female 5 Side View Rear View 5 108642 6789 Figure 3 2 Oops Jumper Serial Console The CM 420 BIOS supports the serial console or console redirection feature These I O functions are provided by an ANSI compatible serial terminal or the equivalent terminal emulation software running on another system This can be very useful when setting up the BIOS on a production line for systems that are not connected to a keyboard and display CoreModule 420 Reference Manual 41 Chapter 3 Hardware Serial Console BIOS Setup The serial console feature may be invoked by entering the appropriate option port selected in the Serial Console field of the BIOS and Hardware Settings screen in BIOS Setup A standard null modem serial cable is used to connect the chosen serial port on the CoreModule 420 J3 or J9 to a serial terminal or PC Th
63. et settings 51 block diagr Bebo unionem 2 noreste ROTEN 49 bytewide socket US 18 floppy drive settings 48 CompactFlash socket 29 Hot Serial Cable 42 Connector location 11 pO SN NN UNE connector part PAM 59 memory settings s 50 CPU features 18 mouse SEINS 51 CPU heatsink requirements T AE T ae 15 no bootable device available 49 eurent 40 43 on board controller settings 51 parallel port settings 51 DLL DIE MEUSE II 2 Plug and Play 52 LA nee 0 Power management 50 environmental requirements 15 PS 2 mouse settings ce 5 Ethernet 37 serial console ruere eter te E 42 LEDS 12 serial port 42 51 c ru cn RAE serial terminal iere res 41 uns ION NUUS MN E UU s special boot options 49 a time month day year settings 48 OPPY port 3 ond poets 51 master slave 40 video port settings 51 height limitatio
64. g for transferring digital pixel data 2 TFTDE TFT Data Enable This signal indicates valid data on any of the FP 23 0 lines 3 TFTLP TFT Line Pulse This signal is the digital monitor equivalent of HSYNC 4 TFTFrame TFT Frame Marker This signal is the TFT monitor equivalent of VSYNC 5 GND Digital Ground 6 GND Digital Ground 7 NC Not connected FPO Panel Data 0 8 NC Not connected FP1 Panel Data 1 9 FP2 Panel Data 2 These pins 0 to 23 provides Digital pixel data output signals 10 FP3 Panel Data 3 Refer to pin 9 FP2 for more information 11 FP4 Panel Data 4 Refer to pin 9 FP2 for more information 12 FPS Panel Data 5 Refer to pin 9 FP2 for more information 13 FP6 Panel Data 6 Refer to pin 9 FP2 for more information 14 FP7 Panel Data 7 Refer to pin 9 FP2 for more information 15 NC Not connected FP8 Panel Data8 16 NC Not connected FP9 Panel Data 9 17 FP10 Panel Data 10 Refer to pin 9 FP2 for more information 18 11 Panel Data 11 Refer to pin 9 FP2 for more information 19 FP12 Panel Data 12 Refer to pin 9 FP2 for more information 20 FP13 Panel Data 13 Refer to pin 9 FP2 for more information 21 FP14 Panel Data 14 Refer to pin 9 FP2 for more information 22 FP15 Panel Data 15 Refer to pin 9 FP2 for more information 23 NC Not connected FP16 Panel Data 16 24 NC Not connected FP17 Panel Data 17 25 FP18 Panel Data 18
65. hown as a black square or black round pin in connectors and jumpers in all illustrations 14 Reference Manual CoreModule 420 Chapter 2 Product Overview NOTE The CoreModule 420 is in violation of the PC 104 height limitations in two places on the bottom of the board The voltage regulator U19 exceeds the allowed height limitation by 0 085 inches and the CompactFlash socket J12 exceeds the height limitation by 0 2 inches See Figure 2 6 Power Specifications Table 2 6 provides the power requirements Table 2 6 Power Supply Requirements Parameter Characteristics Input Type Regulated DC voltages Input Voltage 5 VDC 5 1 35 Amps typical Requirements Operating Power 6 75 Watts typical Note Current readings were taken with all peripheral devices connected or simulated using the Windows 2000 operating system Environmental Specifications Table 2 7 provides the most efficient operating and storage condition ranges required for this module Table 2 7 Environmental Requirements Parameter Conditions Temperature Operating 0 to 70 C 32 to 158 F Extended Optional 40 to 85 C 40 F to 185 Storage 55 to 85 67 185 Humidity Operating 20 to 80 relative humidity non condensing Non operating 5 to 95 relative humidity non condensing Thermal Cooling Requirements The CPU requires a heatsink provide
66. ial Ports Pin Signal Descriptions J3 J9 Pin Signal DB9 Description 1 DCD 1 Data Carrier Detect Indicator to the serial port that external modem is detecting a carrier signal i e a communication channel is currently open In direct connect environments this input will be driven by DTR as part of the DTR DSR handshake 2 DSR 6 Data Set Ready Indicator to the serial port that external serial communications device is powered initialized and ready Used as hardware handshake with DTRI for overall readiness to communicate 3 RXD 2 Receive Data Serial port receive data input is typically held at a logic 1 mark when no data is being transmitted and is held Off for a brief interval after an On to Off transition on the RTS line to allow the transmission to complete erial Port 1 or 2 If in mode this pin is ata RX Data Serial Port 1 or 2 If in RS485 mode this pin is RX D 4 RTS 7 Request To Send Indicates serial port is ready to transmit data Used as hardware handshake with CTS for low level flow control Tx Data Serial Port 1 2 If in RS485 mode this pin is TX Data 5 TXD 3 Transmit Data Serial port transmit data output is typically held to a logic 1 when no data is being sent Typically a logic 0 On must be present on RTS CTS DSR and DTR before data can be transmitted on this line Tx Data Serial Port 1 or 2 If in
67. le redirection when Enabled has been selected in Serial Console Use a standard null modem serial cable However connecting a Hot Cable to the other port port not selected overrides this field setting and activates the connected port Connecting a Hot Cable to one of the serial ports only allows console redirection when a Hot Cable is actually connected to Serial 1 or 2 Use the modified serial cable described in Chapter 3 under Hot Serial Cable e On Board Serial Ports Serial 1 Mode RS 232 or RS 485 Serial 2 Mode RS 232 or RS 485 Serial 3 Disabled 3F8h 2F8h 3E8h 2E8h 260h 2FOh 3E0h 2EOh 200h or 220h e IRQ none 1 3 4 5 6 7 8 9 10 11 or 12 Serial 4 Disabled 3F8h 2F8h 3E8h 2E8h 260h 2FOh 3E0h 2EOh 200h or 220h e IRQ none 1 3 4 5 6 7 8 9 10 11 12 e On Board LPT Port If the Floppy Drive is selected instead of the Parallel port these settings have no effect LPT 1 Disabled 378h 278h 3BCh 370h or 270h e IRQ none 1 3 4 5 6 7 8 9 10 11 12 e DMA 3 2 1 or 0 e Mode Standard SPP bi dir EPP 1 7 SPP EPP 1 9 SPP EPP 1 7 ECP EPP 1 9 ECP or ECP e On Board Video Framebuffer Size Disabled 1 MB 2MB 3MB or 4MB VGA Palette Snoop Disabled or Enabl
68. ls The master GPIO pins can not be used for customer applications The example program can be built by using the make bat file This produces a 16 bit DOS executable application gpio exe which can be run on the CoreModule 420 to demonstrate the use of GPIO pins For more information about the GPIO pin operation refer to the Programming Manual for the STPC Atlas processor at ttp www stmcu com devicedocs Atlas 75 html 40 Reference Manual CoreModule 420 Chapter 3 Hardware Table 3 18 User GPIO Signals Pin Signal Descriptions J8 Pin Signal Description 1 GPIO8 User defined 2 GPIO9 User defined 3 GPIO10 User defined 4 GPIO11 User defined 5 GPIO12 User defined 6 GPIO13 User defined 7 GPIO14 User defined 8 GPIO15 User defined 9 GND Ground 10 GND Ground Notes The shaded area denotes ground Oops Jumper BIOS Recovery The Oops jumper is provided in the event you ve selected BIOS settings that prevent you from booting the system By using the Oops jumper you can stop the current BIOS settings in the CMOS from being loaded allowing you to proceed using the default settings Connect the DTR pin to the RI pin on Serial port 1 COM 1 prior to boot up to prevent the present BIOS settings from loading After booting with the Oops jumper in place remove the Oops jumper and go into BIOS Setup To restore your BIOS setting changes without the errors you must first s
69. me fields will be saved even if you discard changes at exit Use Arrow keys to change menu item use Page Up Down to mofiy Esc to exit C Copyright 2004 Ampro Computers Inc http www ampro com Figure 4 2 BIOS Configuration Screen e Date amp Time DATE dd mmm yyyy This feature sets the numeric entry of the day of the month calendar month and all 4 digits of the year indicating the century plus year 17 Feb 2004 Time hh mm ss This feature sets the 24 hour Clock in hours minutes and seconds e Drive Assignment Drive A none 360 5 25 1 2MB 5 25 720 3 5 1 44 3 5 or 2 88MB 3 5 Drive B none 360 5 25 1 2MB 5 25 720kB 3 5 1 44MB 3 5 2 88MB 3 5 Drive C none HDD on Pri Master CDROM on Pri Master HDD on Pri Slave CDROM on Pri Slave or CF on Sec Master Drive D none HDD on Pri Master CDROM on Pri Master HDD on Pri Slave CDROM on Pri Slave or CF on Sec Master Drive E none HDD on Pri Master CDROM on Pri Master HDD on Pri Slave CDROM on Pri Slave or CF on Sec Master NOTE If a CompactFlash is used to boot the system it is always configured as CF on Sec Master on Drive C or D but not Drive E even though it appears under Drive E options The DiskOnChip DOC is not listed as a drive and is not in the boot order
70. nality has not implemented e The application is located at the fixed address of IMB e The bootloader has to load the application at the fixed address of 1MB e The startup code is incomplete For example early initialization functions and constructors normally called before main are not called at all e In general the standard libraries can NOT be used e C exception handling is not supported e The bootloader makes certain assumptions which are documented in the source code Installing the Example Application To install the example application the generated Flash image needs to be programmed into Flash memory 1 Copy the files aflash exe image and updimg bat to a floppy 2 Turn on power to the CoreModule 420 and enter BIOS Setup 3 Go to Memory settings under the BIOS and Hardware Settings screen and set Flash Address to 8MB 4 Select Esc to exit to the main menu 5 Exit BIOS Setup using the Exit Saving Changes option 6 Reboot the CoreModule 420 from a MS DOS 6 22 floppy diskette without a config sys and autoexec bat and then remove the diskette 7 Insert the floppy diskette into the drive with aflash exe image and updimg bat previously copied to it 8 Change the current directory to the floppy by typing a 9 Run the updimg bat file from the diskette This bat file will program the file image into the Flash memory 10 Reboot the CoreModule 420 and enter BIOS Setup again 11 Go to the BIOS and Hardware
71. nectors if you want to make your own cables Table B 1 Connector and Manufacture s Part Numbers Connector Pin Number Pin Spacing Manufacturer Manufacturer s PN Orientation J2 Ethernet 8 pin 0 1 right angle Molex Housing 10 11 2063 Pins 08 55 0102 J3 Serial 1 10 pin 0 1 right angle Molex 10 89 1106 J4 Floppy 26 pin 0 1 right angle T amp B Ansley or 609 2600M or Parallel Spectra Strip 812 2622 134 JS Utility 10 pin 0 1 right angle AMP or 102387 1 or Molex 22 55 3101 J6 IDE 44 pin 2mm straight TEKA HM222BTIU 191 00 Power 10 pin 0 1 right angle AMP or Housing 87456 5 or Molex 22 55 2101 AMP or Contact 87523 6 or Molex 16 02 0103 J8 GPIO 10 pin 2mm straight Adam Tech or D2PH 2 10 SG 146 118 420 or Samtec TW 05 06 G D 420 110 J9 Serial 2 10 pin 0 1 right angle Molex 10 89 1106 J10 USB 5 pin 0 1 right angle Molex 22 12 2054 J11 Video 44 pin 2mm right angle Adam Tech or 2PH2R44SGA Astron AT PH2 44 2 1 GF J13 Serial 3 10 pin 0 1 straight Molex 15 91 3100 J14 Serial 4 10 pin 0 1 straight Molex 15 91 3100 CoreModule 420 Reference Manual 59 Appendix B Connector Part Numbers 60 Reference Manual CoreModule 420 Index Accessing BIOS Setup Serial Console 46 rebootoption tei 49 Accessing BIOS Setup
72. ns 15 watchdog timer WDT Settings 50 address map 20 21 Bocrdevis IDE features 27 alarm option 49 Jumper settings en 12 BIOS Setup 49 low voltage limit 43 CD ROM LL 48 major integrated Circuits 10 CompactFlash 48 memory features 18 DiskOnChip DOC not listed 48 Oops jumper 41 Floppy drive 49 Parallel p acu 31 floppy drive selection 49 e architecture AG 49 pin 1 locations essen 0 CoreModule 420 Reference Manual 61 Index power requirements 15 QuickStart Kit 2 Real Time Clock RTC 40 RS485 mode une terere 34 serial connectors 34 serial console option 41 serial port features 33 single board computer SBC 5 USB COMMCCIOL ses ach ine vete 35 Utility connector seen 36 Video port connection 39 voltage requirements 43 watchdog timer WDT sess 42 14 features 5e Seo RON ANIME 18 heatsink requirements eese 15 RS 52 Default settings BIOS configuration 47 shown as bold type in 47 Dimensions 14 DiskOnChip DOC see 48 DMA 20 Enter BIOS prompt not seen
73. og trigger configurable disabled by default 02E8 02EF COMA configurable 02F8 02FF configurable 0376 Secondary IDE see 170 0378 037B LPT 1 configurable disabled by default 0378 037F LPT 1 only in EPP modes 03B4 03B5 VGA registers monochrome mode only 03BA VGA registers monochrome mode only 03C0 03CF VGA registers 03D4 03D5 VGA registers color mode only 03DA VGA registers color mode only 03E8 03EF CONG configurable 03F0 03F1 Super I O Configuration 03F0 03F5 Floppy Disk Controller configurable 03F6 Primary IDE see 1F0 03F7 Floppy Disk Controller see 3F0 03F8 03FF COMI configurable 0778 077A LPT 1 only in ECP modes OCF8 PCI Configuration Address OCFC OCFF PCI Configuration Data 46E8 VGA add in mode enable register D000 D007 General Purpose I O for customer use D400 D407 Board control E400 E43F On Board Ethernet E800 E80F IDE Bus Master registers PCI mode Secondary IDE Control PCI mode F000 FO0F Secondary IDE Command PCI mode F400 F40F Primary IDE Control PCI mode F800 F80F Primary IDE Command PCI mode Note Configurable indicates the device s base address can be configured and or the device can be disabled either through BIOS Setup or hardware jumpers CoreModule 420 Reference Manual Hardware 21 Chapter 3 Hardware PC 104 Bus Interface P1A B C D The PC 104 Bus uses a 104 pin 0 1 connector interface This interface connector will carry all of the
74. on Mouse The signal lines for a PS 2 mouse are provided through the Utility interface J5 to the Super I O controller U13 Refer to Table 3 15 for pin signal information Battery An external battery input connection is provided through the Utility interface J5 to support a battery backup for the CMOS RAM and the RTC Real Time Clock Refer to Table 3 15 for pin signal information Reset Switch An external reset switch provides the reset signal through the Utility interface J5 to a reset circuit which drives the STPC ATLAS CPU U14 Refer to Table 3 15 for pin signal information Speaker The speaker signal provides sufficient signal strength to drive a IW 8 Q Beep speaker through the Utility interface J5 at an audible level The speaker signal is driven from an on board amplifier and the STPC ATLAS CPU U14 Refer to Table 3 15 for pin signal information Table 3 15 Utility Interface Pin Signal Descriptions J5 Pin Signal Description 1 SPKR Speaker Output 2 BATV Ground return 3 RESETSW External Reset Switch signal 4 MDATA Mouse Data input 5 KBDATA Keyboard Data input 6 KBCLK Keyboard Clock input 7 GND Digital Ground 8 KMPWR Keyboard Mouse power 5V output 9 BATV Real time battery voltage 3 6V Type 4 0V Max input 10 MCLK Mouse Clock input Notes The shaded area denotes power or ground The signals marked with indicate active low 36 R
75. ppy over Parallel Disabled or Enabled e If Enabled this option selects the Floppy Drive instead of the Parallel port on the shared connector If Disabled this option selects the Parallel port instead of the Floppy Drive on the shared connector Floppy Swap Disabled or Enabled Floppy Seek Disabled or Enabled Hard disk Seek Disabled or Enabled Boot Method Boot Sector or Windows CE CompactFlash ATA mode LBA Physical or Phoenix This option allows you to select between the existing formats used to format your CompactFlash card This feature allows you to use any one of the three common formats available for CompactFlash cards without having to re format the CompactFlash card before you can use it on the CoreModule 420 The LBA Logical Block Address is set as the default format because it can handle larger drives and is the newest format available but may not be the one used to format your CompactFlash card The other common formats that may be encountered are the Physical or Phoenix formats CoreModule 420 Reference Manual 49 Chapter 4 BIOS Setup Keyboard and Mouse Numlock Disabled or Enabled Typematic Disabled or Enabled Delay 250ms 500ms 750ms or 1000ms This feature is used for the keyboard and determines the typing delay e Rate 30cps 24cps 20cps 15cps 12cps 10cps 8cps or 6cps This featur
76. purchase Ampro highly recommends that you purchase and utilize a CoreModule 420 QuickStart Kit simultaneously with the design of your product CoreModule 420 Support Products CoreModule 420 QuickStart Kit QSK The CoreModule 420 QuickStart Kit includes the CoreModule 420 CPU a complete cable kit documentation and drivers for any Ampro supported operating systems with unique devices used on the board CoreModule 420 Development System The CoreModule 420 Development System is a benchtop system which provides a known good environment for your development work The Development System provides an integrated and easy to use self hosted development environment that lets you maximize the benefit of using off the shelf PC compatible modules as the basis of your embedded system design You can install PC 104 expansion modules or ISA bus expansion boards on the Development System chassis The Development System is laid out to make all the components of your system accessible Refer to the CoreModule 420 Development System Users Guide on the CoreModule 420 Documentation and Support Software Doc amp SW CD ROM for more information CoreModule 420 Documentation and Support Software CD ROM The CoreModule 420 Documentation and Support Software Doc amp SW CD ROM is provided with the CoreModule 420 QuickStart Kit and the Development System The CD ROM includes all of the CoreModule documentation including this Reference Manual the CoreModul
77. r Blue 44 BLUE Blue This pin provides the Blue analog output to the CRT Notes The shaded area denotes power or ground The signals marked with indicate active low Miscellaneous Real Time Clock RTC The CoreModule 420 contains a Real Time time of day Clock RTC which can be backed up with a Lithium Battery The CoreModule 420 will function without a battery in those environments which prohibit inclusion of batteries The CoreModule 420 will also continue to operate after the battery life has been exceeded Under these conditions all setup information is restored from the onboard Flash memory during POST along with the default date and time information NOTE Some operating systems require a valid default date and time to function User GPIO Signals The CoreModule 420 provides GPIO pins for customer use and the signals are routed to connector J8 An example of how to use the GPIO pins is provided in the Miscellaneous Source Code Examples subdirectory under the CoreModule 420 Software menu on the CoreModule 420 Doc amp SW CD ROM cm420 software examples GPIO CAUTION To prevent a system crash or render the CoreModule 420 BIOS unusable do not attempt to use the master GPIO pins GPIOs 0 7 The STPC Atlas processor has two GPIO blocks master and slave The slave GPIO pins are reserved for customer applications The master GPIO pins are dedicated for BIOS use to control on board periphera
78. reModule 420 Doc amp SW CD ROM Power Interface J7 The CoreModule 420 requires one 5 volt power source and uses a 10 pin header with 0 1 spacing When the 5 power drops below 4 0V a low voltage reset triggers activating a system interrupt The power input connector J7 supplies the following voltage directly to the module e 5 0VDC 5 1 35 Amps Table 3 19 gives the signals for Power supply pin outs Table 3 19 Power Interface Pins Signals J7 Pin Signal Descriptions 1 GND Ground 2 5V 5 Volts 3 Key GND Key Pin on connector Grounded on board 4 12V 12 volts routed to PC 104 5 GND Ground 6 NC Not connected 7 GND Ground 8 5V 5 Volts 9 GND Ground 10 5V 5 Volts Note The shaded area denotes power or ground Table 3 20 Power Interface Pin Arrangement J7 Pin Signal Pin Signal 1 GND 2 5V 3 GND 4 12V 5 GND 6 Key NC 7 GND 8 5V 9 GND 10 5V Note The shaded area denotes power or ground CoreModule 420 Reference Manual 43 Chapter 3 Hardware 44 Reference Manual CoreModule 420 Chapter 4 BIOS Setup Introduction This chapter describes the BIOS Setup menus and the various screens used for configuring the CoreModule 420 Some features in the Operating System or application software may require configuration in the BIOS Setup screens This section assumes the user is familiar with general BI
79. rnal registers or signal operations Busor signal timing for industry standard busses and signals Reference Material The following list of reference materials may be helpful for you to complete your custom design successfully Most of this reference material is also available on the Ampro web site in the Embedded Design Resource Center The Embedded Design Resource Center was created for embedded system developers to share Ampro s knowledge insight and expertise gained from years of experience Specifications e PC 104 Specifications Revision 2 5 November 2003 For latest revision of the PC 104 specifications contact the PC 104 Consortium at Web site http www pc104 org Chip Specifications The following chip specifications are used in the CoreModule 420 processor module STMicroelectronics and the chip STPC Atlas used for the embedded CPU Web site http us st com stonline books pdf docs 7341 pdf e Standard Microsystems Corp and the chip FDC37B782 used for the Super I O controller Web site http www smsc com main catalog fdc37b78x html Intel Corporation and the chip 82551ER used for the Ethernet controller Web site http www intel com design network products lan controllers 8255 1er html CoreModule 420 Reference Manual Chapter 1 About this Manual Related Ampro Products The following items are directly related to successfully using the Ampro product you have just purchased or plan to
80. rnet Port J2 LED Indicators Note JP8 and JP9 Enable Disable the Serial ports at the STPC Altas CPU U14 Table 2 4 provides the LED color and definitions for the Ethernet Port J2 located on the CoreModule 420 and Figure 2 5 provides the locations Indicator Definition Ethernet Link Activity LED D1 either transmit or receive activity Link Activity LED This yellow LED is the activity link indicator and provides the status of Ethernet port J2 The Link Activity LED indicates an Link is established with Yellow On This indicates a link is present Yellow Flashing This indicates activity is present Yellow Off This indicates no link or activity is present Ethernet Speed D2 Speed LED This green LED is the LAN Speed indictor and indicates the transmit or receive speed of Ethernet port J2 Green On This indicates the operating speed is 100Mbps Green Off This indicates the operating speed is 10Mbps 12 Reference Manual CoreModule 420 Chapter 2
81. rts 3 and 4 are supported by the Super I O Controller and are 16550 compatible Serial 3 713 COM3 supports RS232 with full modem support Serial 4 714 supports RS232 with full modem support The RS232 RS485 mode for Serial Port 1 COM1 and Serial Port 2 COM are selected in BIOS Setup Utility The RS485 terminations for Serial Port 1 COM1 and Serial Port 2 are selected using jumpers JP1 and JP2 on the board instead of the BIOS Setup Utility However the RS232 mode is the default selection for either Serial Port 1 or 2 COMI or COM2 To implement a two wired RS485 mode with either Serial Port 1 or 2 you must tie pins 3 RX Data to 5 TX Data and pins 4 Tx Data to 6 Rx Data at Serial Port 1 or 2 J3 or J9 for the two wire interface Alternatively you may short the equivalent pins on the DB9 connector attached to respective serial port as shown in Figure 3 1 Serial Ports J3 J9 Standard DB9 Serial or COM2 Gee Or Port Connector Female Side View Rear View 97531 12345 CM420RS485jump 108642 6789 Figure 3 1 Serial 1 to RS485 Conversion Table 3 12 provides the signals for the corresponding pins of the two independent serial interface ports Serial 1 amp 2 and Table 3 13 provides the signals for the corresponding pins of two independent serial interface headers Serial 3 amp 4 CoreModule 420 Reference Manual 33 Chapter 3 Hardware Table 3 12 Ser
82. s If the OS fails to boot in the time interval set in the BIOS the system will reset Enable the Watchdog Timer sec field in the BIOS and Hardware Settings screen of BIOS Setup Set the WDT for a time out interval in seconds between and 255 in one second increments Ensure you allow enough time for the boot process to complete and for the OS to boot The OS or application must tickle or turnoff the WDT as soon as it comes up This can be done by accessing the hardware directly or through a BIOS call e During System Operation An application can set up the WDT hardware through a BIOS call or by accessing the hardware directly Some Ampro Board Support Packages provide an API interface to the WDT The application must tickle or turnoff the WDT in the time set when the WDT is initialized or the system will be reset You can use a BIOS call to tickle the WDT or access the hardware directly The BIOS implements interrupt 15 function 0C3h to manipulate the WDT Reference Manual CoreModule 420 Chapter 3 Hardware e Watchdog Code examples Ampro has provided source code examples on the CoreModule 420 Doc amp SW CD ROM illustrating how to control the WDT The code examples can be easily copied to your development environment to compile and test the examples or make any desired changes before compiling Refer to the WDT Readme file in the Miscellaneous Source Code Examples subdirectory under the Support Software menu on the Co
83. sed by the ISA bus master to gain control of the bus from the DMA controller 48 B16 DRQ3 DMA Request 3 Used by I O resources to request DMA service Must be held high until associated DACK3 line is active CoreModule 420 Reference Manual 23 Chapter 3 24 Hardware Pin Signal Description P1 Row B 49 B17 DAck1 DMA Acknowledge 1 Used by DMA controller to select the I O resource requesting the bus or to request ownership of the bus as a bus master device Can also be used by the ISA bus master to gain control of the bus from the DMA controller 50 B18 DRQI DMA Request 1 Used by I O resources to request DMA service Must be held high until associated DACK1 line is active 51 B19 Refresh Memory Refresh This signal is driven low to indicate a memory refresh cycle is in progress Memory is refreshed every 15 6 usec 52 B20 SysClk System Clock This is a free running clock typically in 8MHZ to 10MHz range although its exact frequency is not guaranteed 53 B21 IRQ7 Interrupt Request 7 Asserted by a device when it has pending interrupt request Only one device may use the request line at a time 54 B22 IRQ6 Interrupt Request 6 Asserted by a device when it has pending interrupt request Only one device may use the request line at a time 55 B23 IRQ5 Interrupt Request 5 Asserted by a devic
84. sertion of a CompactFlash card The CompactFlash card acts as a standard IDE Drive and is connected as CF on Sec Master in BIOS NOTE Supports True IDE Mode and Type 1 or Type II PC cards in the CompactFlash socket J12 Table 3 10 CompactFlash Interface Pin Signal Descriptions J12 Pin Signal Description 1 GND Digital Ground 2 D3 Disk Data 3 These signals 20 215 carry the Data Commands and Status between the host and the controller DO is the LSB of the even Byte of the Word D8 is the LSB of the Odd Byte of the Word All Task File operations occur in byte mode on the low order bus DO D7 while all data transfers are 16 bit using DO D15 provide the disk data signals 3 D4 Disk Data 4 Refer to pin 2 D3 for more information 4 D5 Disk Data 5 Refer to pin 2 D3 for more information 5 D6 Disk Data 6 Refer to pin 2 D3 for more information 6 D7 Disk Data 7 Refer to pin 2 D3 for more information 7 CE1 Card Enable 1 This signal along with CE2 is used to select the card and indicate to the card when a byte or word operation is being performed This signal accesses the even byte or odd byte of the word depending on AO and CE2 GND Digital Ground 9 GND Digital Ground 10 GND Digital Ground 11 GND Digital Ground 12 GND Digital Ground 13 5 volts 5 power supply 14 GND Digital Ground 15 GND Digital Gro
85. sly e Supports IEEE 802 3x Flow control in full duplex mode Half duplex mode supports enhanced proprietary collision reduction mode e Utility Interface Keyboard and PS 2 Mouse Interface Supports external battery for Real Time Clock operation Supports standard 8Q speaker interface Supports a Reset switch e USB Ports Supports one root USB hub Supports one USB port Supports USB v1 1 and Universal OHCI v1 1 CoreModule 420 Reference Manual 7 Chapter 2 Product Overview Video LCD CRT Display Enhanced 2D graphics controller Supports BitBLT implementation for all 256 raster operations for Window support Supports all BLT transparency modes e Bitmap transparency Pattern transparency e Source transparency e Destination transparency Supports 8 16 24 and 32 bit pixel depths Supports Hardware Clipping Supports fast line draw engine with Anti aliasing Supports fast triangle fill engine Supports 4 bit Alpha blend font for Anti aliased text display Supports 64 bit wide Pipelined architecture operating at 100MHz Supports complete double buffered registers for pipelined operation Supports video memory up to 4MB selected in BIOS Setup CRT VGA Controller with 135MHz triple RAMDACS for 1280 x 1024 x 75Hz display Supports 24 bit pixel depth Interlaced or non interlaced output LCD TFT Controller Supports VESA Flat Panel Display interface FPDI 1B Supports programmable panel size up to 1024x768 pix
86. ssociated DACK2 line is active 39 B7 NC 12V Not connected 12 volts 40 B8 ZWS Zero Wait State This signal is driven low by a bus slave device to indicate it is capable of performing a bus cycle without inserting any additional wait states To perform a 16 bit memory cycle without wait states this signal is derived from an address decode 41 B9 12V 12 Volts 42 B10 Key NC Key Pin Not connected 43 B11 SMemW System Memory Write This signal is used by bus owner to request a memory device to store data currently on the data bus and only active for the lower IMB Used for legacy compatibility with 8 bit cards 44 812 SMemR System Memory Read This signal is used by bus owner to request a memory device to drive data onto the data bus and only active for lower 1MB Used for legacy compatibility with 8 bit cards 45 B13 IOW I O Write This strobe signal is driven by the owner of the bus ISA bus master or DMA controller and instructs the selected I O device to capture the write data on the data bus 46 B14 IOR Read This strobe signal is driven by the owner of the bus ISA bus 5 y master or DMA controller and instructs the selected I O device to drive read data onto the data bus 47 815 DAck3 DMA Acknowledge 3 Used by DMA controller to select the I O resource requesting the bus or to request ownership of the bus as a bus master device Can also be u
87. tility for CoreModule 420 SWxxxxxx gt BIOS and Hardware Settings lt Reload Initial Settings Load Factory Default Settings Exit Saving Changes Exit Discarding Changes Help for BIOS and Hardware Settings This selection enters the screen with setup parameters These parameters configure the BIOS and the hardware as well as peripheral devices Use Arrow keys to change menu item use Enter to select menu item C Copyright 2004 Ampro Computers Inc http www ampro com Figure 4 1 BIOS Setup Opening Screen The default values or the typical settings are shown highlighted bold text in the list of options Refer to the bottom of the BIOS screens for the navigation instructions when making selections CoreModule 420 Reference Manual 47 Chapter 4 BIOS Configuration Screen 48 BIOS Setup Ampro Setup Utility for CoreModule 420 SWxxxxxx Date amp Time gt Date 16 Feb 2004 lt Time 10 24 34 Drive Assignment Drive A 1 44 MB 3 5 Drive B none Drive C HDD on Pri Master Drive D none Drive E none Boot Order Boot 1st Drive A Boot 2nd Drive C Boot 3rd CDROM Boot 4th none Boot 5th none Boot 6th none Drive and Boot Options Y Help for Date The Date amp Time fields are updated in real time When you make a change the CMOS is updated immediately Any changes made to Date amp Ti
88. topics and screens are described on the following pages Table 4 1 summarizes the list of BIOS menus and some of the features available for CoreModule 420 Accessing BIOS Setup VGA Display To access BIOS Setup using a VGA display for the CoreModule 420 1 Turn on the VGA monitor and the power supply to the CoreModule 420 2 Start Setup by pressing the Del key when the following message appears on the boot screen Hit lt Del gt if you want to run SETUP NOTE If the setting for Memory Test is set to Fast you may not see this prompt appear on screen if the monitor is too slow to display it on start up If this happens use the lt Del gt key early in the boot sequence to enter BIOS Setup 3 Use the lt Enter gt key to access the screen menus listed in the BIOS opening screen 4 Follow the instructions at the bottom of each screen to navigate through the selections and modify any settings CoreModule 420 Reference Manual 45 Chapter 4 BIOS Setup Accessing BIOS Setup Serial Console Entering the BIOS Setup in serial console mode is very similar to the steps you use to enter BIOS Setup with a VGA display input except the actual keys you use 1 Connect the serial console or the PC with serial terminal emulation to Serial Port 1 J3 or Serial Port 2 J9 of the CoreModule 420 Ifthe BIOS option Serial Console is set to Enable use a standard null modem serial cable Ifthe BIOS option Serial Console is
89. und 16 GND Digital Ground 17 GND Digital Ground 18 A2 Address Select 2 One of three signals 0 2 used to select one of eight registers in the Task File The host grounds all remaining address lines 19 Al Address Select 1 Refer to A2 on pin 18 for more information 20 AO Address Select 0 Refer to A2 on pin 18 for more information 21 DO Disk Data 0 Refer to D3 on pin 2 for more information 22 DI Disk Data 1 Refer to D3 on pin 2 for more information 23 D2 Disk Data 2 Refer to D3 on pin 2 for more information CoreModule 420 Reference Manual 29 Chapter 3 Hardware Pin Signal Description 24 NC Not connected IOCS16 I O select 16 bit 25 GND Digital Ground 26 NC Not Connected Card detect 27 D11 Disk Data 11 Refer to pin 2 D3 for more information 28 D12 Disk Data 12 Refer to pin 2 D3 for more information 29 D13 Disk Data 13 Refer to pin 2 D3 for more information 30 D14 Disk Data 14 Refer to pin 2 D3 for more information 31 D15 Disk Data 15 Refer to pin 2 D3 for more information 32 CE2 Card Enable 2 This signal along with CE1 is used to select the CompactFlash card and indicate to the card when a byte or word operation is being performed This signal always accesses the odd byte of the word 33 NC Not Connected VS1 34 IOR Read Strobe This signal is generated by the host and gates the I O data
90. ut is typically held at a logic 1 mark when no data is being transmitted and is held Off for a brief interval after an On to Off transition on the RTS line to allow the transmission to complete 34 Reference Manual CoreModule 420 Chapter 3 Hardware Pin Signal DB9 Description 4 RTS Request To Send Indicates serial port is ready to transmit data Used as hardware handshake with CTS for low level flow control TXD Transmit Data Serial port transmit data output is typically held to a logic 1 when no data is being sent Typically a logic 0 On must be present on RTS CTS DSR and DTR before data can be transmitted on this line CTS Clear To Send Indicator to serial port that external serial communications device is ready to receive data Used as hardware handshake with RTS for low level flow control DTR Data Terminal Ready Indicates serial port is powered initialized and ready Used as hardware handshake with DSR for overall readiness to communicate RI Ring Indicator Indicator to serial port that external modem is detecting a ring condition Used by software to initiate operations to answer and open the communications channel 9 GND 5 Digital Ground 10 Key NC NC Key Pin Not connected Notes The shaded area denotes power or ground The signals marked with indicate active low U
91. y less boot BIOS extensions for OEM boot customization some power management features and up to 256MB of SDRAM memory Other Ampro Products e LittleBoard M Family These high performance highly integrated single board computers use the EBX form factor 5 75x8 00 inches and are available with Pentium MMX Pentium III and Celeron processors The EBX compliant LittleBoard single board computers offer functions equivalent to a complete laptop or desktop PC system plus several expansion cards Built in extras to meet the critical requirements of embedded applications include onboard solid state disk capability watchdog timer smart power monitor and other embedded PC BIOS enhancements Reference Manual CoreModule 420 Chapter 1 About this Manual e MiniModule Family This extensive line of peripheral interface modules compliant with PC 104 and PC 104 Plus standard can be used with Ampro s CoreModule and LittleBoard single board computers to configure embedded system solutions Ampro s highly reliable MiniModule products currently support USB 2 0 IEEE 1394 FireWire CRT and flat panel display interfaces Ethernet PC Card expansion analog data acquisition FPGA additional RS232 RS485 serial ports and general purpose I O GPIO e EnCore Family These high performance compact modular CPU solutions use various processor technologies including Intel x86 MIPS and PowerPC architectures to plug into your custom logic boar
92. z e IDE Interface Supports two enhanced IDE devices Fast ATA capable interface supports high speed PIO modes PIO modes 0 to 4 Supports ATAPI and DVD peripherals Supports IDE native and ATA compatibility modes 6 Reference Manual CoreModule 420 Chapter 2 Product Overview e CompactFlash Socket Supports Type II PC card connector Supports IDE CompactFlash card Utilizes Secondary IDE bus e Floppy Disk Controller Shared connector with parallel port Supports two floppy drives Supports all standard PC AT formats 360kB 1 2MB 720kB 1 44MB 2 88MB e Serial Ports Four buffered RS232 serial ports with full handshaking and modem capability Provides 16550 or 15540 equivalent controllers each with a built in 16 byte FIFO buffer Ports 1 and 2 support RS232 or RS485 operation Supports programmable word length stop bits and parity Supports 16 bit programmable baud rate generator and a interrupt generator e Parallel Port Shared connector with Floppy drive port Supports standard printer port Supports IEEE standard 1284 protocols including EPP ECP modes Bidirectional data lines Supports 16 byte FIFO for ECP mode e Ethernet Controller Intel 82551ER Controller chip Supports IEEE 802 3 10BaseT 100BaseT compatible physical layer Supports Auto negotiation for speed duplex mode and flow control Supports full duplex or half duplex mode e Full duplex mode supports transmit and receive frames simultaneou

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