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COM Express Carrier Development System Design Workbook

1. 5 2 5G 2 5G COM Express Carrier Development System Design Workbook Rev 1 16 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe1 Type Module PCle SRIO Cards PCle SGMII SRIO Cards Aurora Debug Connector COMEXPRS CONN REFCLK_SD1 p n _ 100 MHz Figure 9 P4080 SerDes Bank1 to Carrier Board Cards Debug Connector Configuration COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 17 COM Express Carrier Architecture When Used with COMe1 Type Module Z Z PCle SGMII XAUI O Cards O WY xX A x lt SATA connectors LLI O REFCLK_SD2 3 p n 125 MHz Figure 10 P4080 SerDes Bank 2 and 3 to Carrier Board Cards SATA Connector Configuration NOTE The SD2 and SD3 clocking domains use separate clock generators 2 3 3 Carrier Board Use of P4080 Ethernet Controller EC Interfaces The carrier board uses up to two 10 100 1000baseT triple speed Ethernet controllers ECs of the P4080 in one of the following configurations e EC2 is connected to the on board PHY using the RGMII protocol the remaining ports are unused or e Both ECs are independently connected to a ULPI USB interface for the COMExprsDS EC2 routes via the ULPI to a USB PHY COM Express Carrier Development System Design Workbook Rev 1 18 Freescale Semi
2. 1588 SIGNALS JOJOBUUND WO 9 1S HOIS 819d HIS 810d GIO S 819d DVI I DV ATX CONN ear LVDS A B In DFP CONN Dual FAN HDR RS232 UARTO 1 Figure 20 COM Express Carrier Block Diagram When Used with COMe2 Type Module 3 1 System Reset Performed by FPGA Reset Sequencer in a System with a COMe2 Module The carrier board FPGA contains a reset sequencer that properly manages the orderly bring up of the system this is not the same as the power sequencer which is similar but not specifically related to reset After the system transitions to having fully stable power supplies the reset sequencer does the following 1 Waits for all reset conditions to clear 2 Configures and releases the processor from reset 3 Idles waiting for further reset conditions to occur COM Express Carrier Development System Design Workbook Rev 1 30 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe2 Type Module Table 15 summarizes the reset conditions and actions of the FPGA when used with a COMe2 module Table 15 Reset Conditions and Actions of FPGA Reset Sequencer Term Type Description Notes HOT_RST_B External HOT power stable Restarts all CPLD power sequencing PWRGD External ATX power stable Causes full system reset unless the system is in S3 power down state SYS_RST_B External COP tool reset request Upon power good sys_rst_b is sent from carrier to COMe2 module RE
3. IRQ6_B IRQ7_B Not connected IRQ8_B FPGA TBD IRQ9_B FPGA TBD IRQ10_B IRQ11_B IRQ_OUT_B Not used as Interrupt but as an EVT pin 2 3 11 Carrier Use of P4080 GPIO Signals The I7C1 interface on the P4080 is expanded by routing five P4080 GPIO signals to the carrier board FPGA for general usage and routing three GPIO signals for controlling the IXXAT module In the future the FPGA could alternatively be implemented to use these GPIO signals to support EMI MDIO bus multiplexing as shown in Table 9 Currently switches can be used or the FPGA can automatically detect that I O cards are in slots 2 and 3 and set the EMI value accordingly Table 9 Future Options for Configuring P4080 Dedicated GPIO Signals for EMI MDIO Bus Multiplexing Signal Name System Function GPIO 0 1 EM1 management bus mux control GPIO 2 3 EM2 management bus mux control GPIO 4 7 Spares connected to test points COM Express Carrier Development System Design Workbook Rev 1 24 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe1 Type Module 2 3 12 Carrier Use of P4080 Control Signals The carrier board implements SYS_RESET_B to reset the entire development system and CB_RESET_B in turn sends a reset to the FPGA from the COMe module P4080 COMe1 Module SYS_RESET_B lt _ CB_RESET_B gt FPGA Figure 16 P4080 CO
4. IRQS EXTVBUS MIC2076 CPEN USBPWR overcurrent Figure 15 P4080 USB Connection to Carrier Board USB Interfaces See the COMX P4080 COM Express Module installation and user manual for details about the four PHYs and the two SxHUBs 2 3 9 Carrier Use of P4080 DMA Controllers The P4080 DMA controllers have internal and external controls to initiate and monitor DMA activity The carrier board does not incorporate any specific devices that make use of the external pin controlled DMA controllers The P4080 DMA ports are connected to test points on the carrier board to allow external hardware control as needed COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 23 COM Express Carrier Architecture When Used with COMe1 Type Module 2 3 10 Carrier Use of P4080 eOpenPIC Interrupt Controller The carrier board contains numerous interrupt connections The P4080 eOpenPIC connections to the carrier are shown in Table 8 See the COMX P4080 COM Express Module installation and user manual for more details on all of the interrupt signals implemented by the module Table 8 P4080 eOpenPIC Interrupt Connections to Carrier Board Devices Signal Name Connections IRQ0_B SLOTS sideband connector SGMII riser does not connect must use in band irq IRQ1_B DS3232 real time CLOCK and NVRAM IRQ2_B IRQ3_B IRQ4_B a IRQ5_B MIC2076 USB Power FLAG for over current at USB connector
5. SerDes clock Two clock buffers Sd_refclk1 pair supports PCIe and sd_refclk2_p n supports SGMII and XAUI e Power supplies Power is supplied to carrier board via standard ATX power supply Power is supplied to COMe module via 12 V pins VCC_RTC 3 3 V and VCC_5V_stby 5 V on the COM Express connectors 2 5 V power for RMI Ethernet PHY 1 1 COMExprsDS as a Processor Evaluation System For general hardware and or software development and evaluation purposes the COMExpress development system can be used like an ordinary desktop computer The P4080COMe DS PB and P2020COMe DS PB development systems can also be used to evaluate many features of the P4080 and P2020 processors respectively Table 2 summarizes the processor hardware interfaces that can be evaluated by using the COM Express carrier board note that shaded features apply to only one processor Table 2 COMExprsDS Device Interfaces Device Feature Configuration Options SerDes e Connect to PCI Express slots for use with graphics or other PEX cards e Test via PCI Express card typically graphics or Catalyst PCI Express control monitoring card LVDS Use ports A or B to test single link DFP using LVDS TFT LCD panel and touch screen for applicable modules eSDHC For P2020 only Supports SDMedia cards and MMC cards SPI Supports standard and x4 devices Local bus For P4080 only Internal debug Serial UART supports two 4 wi
6. W EC 2 VILLE 2 aaka mc tk Port 2s A ai To USB2 j x 3 Z Port 3 Wit Q k gr O GTXCLK 125 MHz CLKBUF Figure 25 P2020 Ethernet Connections to the Carrier Board Table 18 summarizes the carrier board EC connections and routing when the COMe2 is populated with a P2020 Table 18 P2020 Ethernet Port Locations on Carrier P2020 EC Connection Port PHY Address Location 1 1 3 0 1 P9 top P11 2 2 2 P9 bottom See Section 3 3 8 Carrier Board Use of P2020 USB Interfaces and the COMX P2020 COM Express Module installation and user manual for more details on the use of these interfaces COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 37 COM Express Carrier Architecture When Used with COMe2 Type Module 3 3 4 Carrier Board Use of P2020 Support for IEEE Std 1588 Protocol The carrier board supports the P2020 IEEE 1588 precision time protocol PTP as shown in Figure 26 This facility works in tandem with the Ethernet controller to time stamp incoming packets P2020 1588 PULSEOUT 1 2 ALARMOUT 1 2 TRIGIN 1 2 STMP_TX RX 1 2 a oO O oO I D J Q oO QO XTALOSC 125 000 MHz CLKIN CLKOUT 25 ppm Figure 26 P2020 IEEE 1588 Interface to Carrier Board P6880 Header 3 3 5 Carrier Board Use of P2020 Local Bus Interface See the COMX P2020 COM Express Module installation and user manual for details on how the P20
7. freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center 1 800 441 2447 or 1 303 675 2140 Fax 1 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number COMEXPRSDS Rev 1 02 2011 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of
8. 19 P4080 COMe1 Module Clock Architecture Conversely the carrier board provides a battery to the RTC clock to keep time while the system is turned off as shown in Table 14 Table 14 P4080 Clock Connections to Carrier Board Pin Count Signal Names Connections 1 RTC Arbitrary timebase frequency 11 Total pins in this group NOTE The SerDes and Ethernet clocks are described in their respective sections 2 3 18 P4080 Power An ATX power supply 600 W is provided in the system to support the P4080 COMe1 module the carrier board and all its I O cards VCC_12 VCC_5V_STBY and VCC_RTC_BAT are provided to the COMe module from the carrier board COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 29 COM Express Carrier Architecture When Used with COMe2 Type Module 3 COM Express Carrier Architecture When Used with COMe2 Type Module COMEXPRESS CARRIER COMe2 GBE0 3 MIDI 3 x RJ 45 4 USB 2 0 ports DUAL USE 4 USB 2 0 ports HDRS PMC conn to PQ MDS QOC3 card UPC Dual DB9 lt gt rsz UART2 3 lt _ __ _______ _ __ gt RS 485 Adapter TDM riser card Line In Out PMC conn to PQ MDS 16T1E1 Dual RMI MII RJ45 PHY 1588 HDR 1588 SIGNALS tor lt VGA gt CLOCKS QE UART SECURITY STM1403A pampo det TDM for SLIC TouchlF SPI SPIFlash SDHC SD MMC conn vs ENET S XN N eu1 x4 pue VWOd4
9. 4 Programming Model for PC implementation information 3 3 15 Carrier Board Use of P2020 EM1 and EM2 Management Buses The carrier board has the following types of buses e SGMII and RGMII PHY management e XAUI PHY management not applicable for P2020 Because one set of buses must span across multiple devices on the carrier board multiplexers are used to route from the P2020 to each PHY and switches are used to control these multiplexers PHY management bus control is summarized in Table 22 and Table 23 Table 22 P2020 PHY Management Bus Map for EMI1 on Carrier Board Bus SWw4 3 4 Device EMI1 00 On board RGMI PHYI EMI1 01 Slot 2 SGMII EMI1 10 Slot 3 SGMII Table 23 P2020 PHY Management Bus Map for EMI2 on Carrier Board Bus SW8 4 5 Device EMI2 00 No Device EMl2 01 No Device EMI2 10 No Device EMI2 11 Slot 3 XAUI not applicable for P2020 COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 45 COM Express Carrier Architecture When Used with COMe2 Type Module 3 3 16 Carrier Board Use of P2020 Debug Features The carrier board provides a JTAG COP header and AURORA test points for debug purpose using the CodeWarrior USBTAP already installed in the system To upgrade the U Boot stored on the COMe module s NOR FLASH use the CodeWarrior USBTAP tool See the COMX P2020 COM Express Module installation and user manual and the
10. P2020 is expanded by routing five P2020 GPIO signals to the carrier board FPGA for general usage and three GPIO signals for controlling the IXXAT module In the future the FPGA could alternatively be implemented to use these GPIO signals to support EMI MDIO bus multiplexing as shown in Table 20 Currently switches can be used or the FPGA can automatically detect that IO cards are in slots 2 and 3 and set the EMI value accordingly Table 20 Future Options for Configuring P2020 Dedicated GPIO Signals for EMI MDIO Bus Multiplexing Signal Names System Function GPIO 0 1 EM1 management bus mux control GPIO 2 3 EM2 management bus mux control GPIO 4 7 Spares connected to test points COM Express Carrier Development System Design Workbook Rev 1 42 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe2 Type Module 3 3 12 Carrier Use of P2020 Control Signals The carrier board implements SYS_RESET_B to reset the entire development system and CB_RESET_B in turn sends a reset to the FPGA from the COMe module P2020 COMe2 Module SYS_RESET_B lt _ CB_RESET_B gt FPGA Figure 30 P2020 COMe2 System Reset Connection with Carrier Board FPGA 3 3 13 Carrier Board Use of P2020 UART Serial Ports The carrier board connects both 4 wire serial ports of the P2020 to serial level transceivers and from there to a stacked dual DB9 male connector placed on the fr
11. include VCC_SVSTBY and VCC_BAT Note that to support the FPGA standby operation video cards or other high power dissipation cards in the PCI Express slot the PSU should support the following minimum specifications e Minimum 450 W overall 500 W recommended e One PCIE 12 V connector TBD e PCIE 12 V supports a minimum of 150 W e Minimum 5 V 2 A standby current COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 9 COMExprsDS Features and Architecture All other power sources are also derived from the ATX PSU Figure 4 shows the principal system power connections in relationship to the CPLD control For more detail about the processor power scheme implemented by this system see Power in Table 3 ATX PSU PWRON lt PWRGD 22 gt 5VSTB 5 V gt 3 3 V _ gt 12 V _ gt 12V_BULK COM Express Carrier Development System Design Workbook Rev 1 3 3VHOT ses 9 gt gt Raptor 1 8VHOT LDO LDO LDO LDO 3 3 V HOT Select Batt J Figure 4 COMExprsDS System Power Supplies gt 412 5V gt 1 8V gt 1 2V gt VSTANDBY Freescale Semiconductor COM Express Carrier Architecture When Used with COMe1 Type Module 2 COM Express Carrier Architecture When Used with COMe1 Type Module As described earlier the architecture and feature set of the carrier board depends
12. of P4080 SPI Interface The P4080 has a serial peripheral interface SPI which is used to communicate with various peripherals The COM Express carrier board connects a conventional 16 Mbyte serial SPI FLASH EEPROM to one chip select of the P4080 SPI interface The remaining three chip selects are unused P4080 SPI_MOSI SPI_MISO SPI_CLK z Z O O N SPI FLASH 7 16 Mbytes Xx LW O SPI_CS0_B Q gt gt SPI_CS1_B gt E SPI_CS2_B gt gt SPI_CS3_B gt gt Y xX m gt cfg_SDX8MUX A gt sw_FLASHWP_B Figure 14 P4080 SPI Interface Connection to Carrier SPI FLASH Slot COM Express Carrier Development System Design Workbook Rev 1 22 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe1 Type Module 2 3 8 Carrier Board Use of P4080 USB Interfaces The P4080 has a USB 2 0 port that uses the UTMI protocol to connect to an external USB PHY and it may be configured for host or device modes of operation The carrier board USB port connector is a female Type A the standard connector for a host to communicate with keyboards mice memory sticks and so on P4080 Four USB PHYs and Two 5xHUB USB_D 0 7 lt gt _ DATA 0 7 e NXT Z USB_NXT ap 5 USB_DIR lt _ DIR S USB USB_STP ______ gt STP DM ce Ports USB_CLK lt _ CLKOUT at x lt W VBUS
13. power supplies based upon the ATX power supply 5 V standby power VCC5STDBY ASLEEP indicates that the processors s have exited the reset state It does not cause a reset because the processor can sleep for any number of reasons after hard reset is completed During power down all I O and output drivers are tristated After power up drivers may be driven Normal operation and or use of the VELA engine may cause some I Os to be tristated occurrence REGFILE must be able to accept or arbitrate for concurrent writes to the same register though this is not a statistically likely Because access to the internal registers may be blocked asynchronous not ready signalling is used In some instances CONFIG maps switch settings into direct configuration outputs while in others such as SYSCLK it maps a 3 position switch into a 16 bit register initialization pattern which is subsequently used to initialize the clock generator 1 4 System Power Connections Between Carrier Board and COMe Module The 12 V 5 V and 3 3 V power requirements of the carrier board are met by the attached ATX 12V compatible power supply unit PSU of the COMExprsDS 5 V and 3 3 V are connected to individual power planes in the COMExprsDS PCB stackup The 12 V power from the standard ATX header is treated as separate from the ATX 12V power which supplies a large amount of current and is referred to as VCC_12V_BULK to the COMe module Other supplies
14. when used with a P4080 COMe module are shown in Figure 6 Switch names exactly match the name on the schematics and on the printed circuit board in most cases except where a spare has been newly assigned and only the FPGA has changed sw4 SW5 lt Default Setting Reserved MSEL 0 3 4 b1011 Reserved W N Ww RMI PHY_MDIO MDC 1 SLOT2 EMI1_MDIO MDC for SGMII mode SLOT3 EMI1_MDIO MDC for SGMIl mode PHYAD3 to 0 gt SPARE PHYAD3 to 1 SPI Flash write protected PHYAD4 to 0 SPI Flash NOT write protected PHYAD4 to 1 Select alternate SDHC flash mode on the carrier Reserved Select alternate SPI flash mode on the carrier Reserved Reserved Reserved sws lt Default Setting 1 RMII PHY AN1_B disable RMII PHY AN1_B enable RMIl PHY ANO_B disable Of Aon lt Default Setting Reserved 1 EMI2_SELO EMI2_SEL1 it 4 Reseved oo SLOT3 EMl4_MDIOMMDC for XAUI mode ay ae RMII PHY AN1_A enable RMII PHY ANO_A disable RMII PHY ANO_A enable Reserved Reserved Reserved Disable backlight Enable LVDS backlight RMII PHY ANO_B enable E Disable SW_AUTO_ON Reserved 5 Enable SW_AUTO_ON Reserved ililReseved Cd Reserved al fe Resevea Cd z lt Disable LVDS VDD Enable LVDS VDD Figure 6 Carrier Board Switch Assignments and Defaults When Used with P4080 COMe Module COM Express Carrier Dev
15. 20 local bus interface is used COM Express Carrier Development System Design Workbook Rev 1 38 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe2 Type Module 3 3 6 Carrier Board Use of P2020 eSDHC Interface The P2020 has an enhanced secure digital host controller eSDHC The carrier board connects the P2020 eSDHC to an SDMedia card slot and uses GPIO signals for sideband signals such as write protect detect and card detect Both x4 and x8 cards are supported the latter using the SPI_CS_B 0 3 signals which can be reassigned as eSHDC_D 4 7 P2020 SDMedia Slot SDHC_CMD CMD SDHC_DAT O 3 DAT O 3 SDHC_CLK CLK SDHC_CD_B SDHC_CD CD_B SDHC_WP_B SDHC_WP WP_B SDHC_DAT 4 7 zZ Z Q O N xX A gt lt Lu O O p DAT 4 7 CFG_SDX8MUX SS Figure 27 P2020 eSDHC Interface to Carrier Board SD Media Card Slot NOTE SDHC_DAT 4 7 are shared with the SPI CS pins the CFG_SDX8MUX switch selects the routing of those pins to either the SDHC devices or the SPI devices but both cannot be used simultaneously COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 39 COM Express Carrier Architecture When Used with COMe2 Type Module 3 3 7 Carrier Board Use of P2020 SPI Interface The serial peripheral interface SPI on the P2020 communicates with various peripherals The COM Express carrier board connects a conventional 16 Mbyte serial SPI FL
16. ASH EEPROM to one chip select of the P2020 SPI interface The remaining three chip selects are unused P2020 SPI_MOSI SPI_MISO SPI_CLK z Z O O N SPI FLASH qi 16 Mbytes Xx Lu O SPI_CS0_B 0 m SPI_CS1_B gt gt SPI_CS2_B gt gt SPI_CS3_B gt gt Y xX m gt cfg_SDX8MUX A gt sw_FLASHWP_B Figure 28 P2020 SPI Interface Connection to Carrier SPI FLASH Slot COM Express Carrier Development System Design Workbook Rev 1 40 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe2 Type Module 3 3 8 Carrier Board Use of P2020 USB Interfaces The P2020 has a USB 2 0 port that uses the UTMI protocol to connect to an external USB PHY and it may be configured for host or device modes of operation The carrier board USB port connector is a female Type A the standard connector for a host to communicate with keyboards mice memory sticks and so on P2020 Four USB PHYs and Two 5xHUB USB_D 0 7 lt _ DATA 0 7 bg NXT USB_NXT 5p 5S USB_DIR lt _ DIR 2 USB USB_STP ______ gt STP DM a Ponts USB_CLK lt _ CLKOUT mE x lt W VBUS IRQS EXTVBUS gt MIC2076 CPEN USBPWR overcurrent Figure 29 P2020 USB Connection to Carrier Board USB Interfaces See the COMX P2020 COM Express Module installation and user manual for details about the four PH
17. Des PCIE CLOCK SOURCE 557G O05ALFT 100MHz Diff 2x 100MHz Diff Crystal 14 31818MHz Figure 33 P2020 COMe1 Module Clock Architecture Conversely the carrier board provides a battery to the RTC clock to keep time while the system is turned off as shown in Table 25 Table 25 P2020 Clock Connections to Carrier Board Pin Count Signal Names Connections 1 RTC Arbitrary timebase frequency 11 Total pins in this group NOTE The SerDes and Ethernet clocks are included in their respective sections COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 47 Programming Model 3 3 18 P2020 Power An ATX power supply 600 W is provided in the system to support the P2020 COMe1 module and all its T O cards VCC_12 VCC_S5V_STBY VCC_RTC_BAT are provided to the COMe module from the carrier board 4 Programming Model For C master reading of the processor ID EEPROM see ProcessorID Format for Power Architecture Development Systems Table 26 describes the EEPROM on the COMe module at address OxA8 supplying the processor ID and other attributes The ProcessorID device is implemented by a 256 byte serial IC EEPROM A typical device is the Atmel AT24C02 or equivalent Table 26 ProcessorID EEPROM Data Requirements Characteristic Value Size 256 bytes Address OxA8 Addressing Non extended IC bus 2021 Write protection Required 1 Maxim
18. FPGA architecture PSU_PWR_GOOD _ _ gt __ CPLD CPU gt RG 7 RESET SW RESET _ i RESETS m SEQ RESETS CONFIG DRIVE REGFILE lt ____ CONFIG lt s CONFIG LOCAL 8 BIT LAD LBUS gt ane 1201 2CEEPROM debug only SLAVE MASTER I2CLOGIC Figure 3 CPLD and FPGA Overview COM Express Carrier Development System Design Workbook Rev 1 8 Freescale Semiconductor COMExprsDS Features and Architecture Table 3 describes the various FPGA modules Table 3 FPGA Module Descriptions ean Function Modules RESETSEQ Collects various reset power good signals and starts the global reset sequencer 2 REGRESETS Copies reset signals from the sequencer but also allows register based software to individually asserted reset to the local bus memory and or compact FLASH interfaces REGFILE A multi ported register file containing status and configuration data LOCALBUS Interface between the processor and REGFILE for internal Freescale debug use only CONFIG Monitors and or sets selected configuration signals I2CLOGIC The 12C1 master reads COMe module EEPROM at address OxA8 to detect processor type and id information and 2C1 An I2C slave is also used to select muxes for QE functions via the 12C1 expander FPGA_IO signals first availability is for P1021 COMe2 module Power Power for FPGA is supplied from dedicated VCC_HOT_3 3 and VCC_HOT_1 5 V
19. Freescale Semiconductor Design Workbook Document Number COMEXPRSDS Rev 1 02 2011 COM Express Carrier Development System Design Workbook This document primarily describes the COM Express carrier board its relationship to the whole COM Express development system and the differences between the carrier board s architected functions depending on the processor module in use The COM Express carrier development system referred to in this document as COMExprsDS is a high performance computing evaluation and development platform supporting a single board computing SBC COM Express module based on Power Architecture processor The COM Express carrier board is a lead free RoHS compliant board that supports various COMe processor module types Each COMe processor module hereafter referred to as COMe module includes a primary processor or one of its derivatives and Figure 1 shows how the various modules plug into the common carrier board 2011 Freescale Semiconductor Inc All rights reserved Contents 1 COMExprsDS Features and Architecture 3 1 2 Difficult to Find COMe Carrier Connections 7 1 1 COMExprsDS as a Processor Evaluation System 5 2 COM Express Carrier Architecture When Used with COMe1 Type Module 00000 11 3 COM Express Carrier Architecture When Used with COMe2 Type Module 0000 30 4 Programming Model 20000 48 5 Re
20. II 100 10 MHz connector for COMe2 only for processors that feature QUICC Engine QE functionality IXXAT 50 pin connector for Industrial Ethernet Module via SPI bus Tamper detect circuitry to test out P5020 P3040 security modes SLIC RJ 11 phone connectors can be added by using a TDM riser card into slot 5 and the TDM riser sideband connector RS 485 can be added by adding an adapter to the DB 9 RS 232 connector Itifunction FPGA Routes low speed and user defined signals from the COMe module board connectors to the appropriate connectors and devices located on the COM Express carrier board Programmed by the processor on the COMe module following a power up or hard reset The FPGA functionality varies depending on the specific processor populated on the COMe module Generally interfaces to the following signal groups on the COMe module connectors Reserved user defined UART2 and UART3 COM Express Carrier Development System Design Workbook Rev 1 Freescale Se miconductor 3 COMExprsDS Features and Architecture TDM SSI GPI GPO Interfaces to the following connectors and devices on the COM Express carrier board for processors that feature QUICC Engine QE functionality Two RS 232 serial ports with corresponding DB9 connectors UART 2 3 Two RS 4 85 serial ports with corresponding DB9 connectors Four CAN ports with corresponding connectors UTOPIA module and connec
21. Me1 System Reset Connection with Carrier Board FPGA 2 3 13 Carrier Board Use of P4080 UART Serial Ports The carrier board connects both 4 wire serial ports of the P4080 to serial level transceivers and from there to a stacked dual DB9 male connector placed on the front panel UART I O board that is located at the front of the chassis The default mode is 4 wire so RTS CTS flow control is supported on these connectors For the P4080DS kit P4080COMe DS PB UART ports 0 and 1 are supported 3 3 V P4080 UART 1 TLL Port 1 Top port 5 z ep x an z x 5 UARTO X N MUX AE z Port 0 Bottom port O O _ gt HOT 3 3 V cfg_pixisuart Figure 17 P4080 UART Serial Port Connection to Carrier Board Serial Port Connector COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 25 COM Express Carrier Architecture When Used with COMe1 Type Module 2 3 14 Carrier Board Use of P4080 IC Interfaces The carrier board uses three of the four available C SMB buses The I C1 master from the FPGA accesses the EEPROM on the COMe module to read 256 bytes of EEPROM processor type data before the carrier system reset is asserted to the module P4080 Z Z FPGA O O 2C1 D 12C1_MAS 12C2 1 12C2_ SLAVE x YZ 1203 W 12C3_SLAVE 2 D 2 O S 3 Zz B Figure 18 IP4080 Ic Connectivity to Carrier Board FPGA The P4080 I7C bus device add
22. Mentor Embedded Linux for Freescale COMe P2020 System Builder Quick Start Guide for more details 3 3 17 Carrier Board Clock Generation from P2020 COMe2 Module Board The carrier board clock signals are generated by the COMe module board in use Table 24 lists the requirements of the carrier board clock signals when the carrier board is populated with a P2020 COMe2 module For more details on the P2020 COMe2 module see the COMX P2020 COM Express Module installation and user manual Table 24 Carrier Board Clock Requirements When Used with P2020 COMe2 Module z A y Clock COMez2 Clock Signal Corresponding Carrier Board Clock Signal Frequency Type SD1 REFCLK P2020 SD_REFCLK1 p n 100 MHz LVDS SLOT1 REFCLK p n SLOT2 REFCLK p n SLOT4 REFCLK p n SLOT5 REFCLK p n SD2 REFCLK P2020 SD_REFCLK2 p n 100 MHz LVDS SLOT1 REFCLK p n COM Express Carrier Development System Design Workbook Rev 1 46 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe2 Type Module Figure 33 shows the principal clock connections from the P2020 COMe2 module to the carrier board SYSCLK 100 MHz 100MHz DDRCLK 100MHz CY23055 output clock buffer OSC 100MHz lt lt DDR2 DDR3 2ranks Slots USB2 0 PHY x2 USB2 0 HUB x2 USB3315 USB2514i 24MHz mw gt oscam P2020 Dual Core 125MHz 25MHz 1 2GHz n oe 5 output clock buffer GEPHY 2 100MHz Diff 4 Lane 3 GHz Ser
23. Not used for P2020 module Reserved Philips PCA9555PW 1 0x34 CODEC Not used for P2020 COMe module Reserved Wolfson WM8776SEFT 1 0x57 I7C slave port Not used for P2020 COMe module Reserved 1 0x58 USB HUB2 On P2020 COMe module 1 OxAO 4 Kbyte EEPROM Boot configuration C EEPROM on P2020 COMe module Atmel AT24C02C or equivalent 1 OxA4 Remote 1 C 1O Expander On carrier Read only See datasheet for programming instructions Philips PCA9672PW Device ID 1 OxA8 4 Kbyte EEPROM Stores 256 bytes of processor type data Atmel AT24C64A or equivalent Write protectable 1 OxEO I C MUX On P2020 COMe module COM Express Carrier Development System Design Workbook Rev 1 44 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe2 Type Module Table 21 P2020 I2C Bus Device Map continued C 2 I C Bus Kddiess Device Notes 2 0x36 DDR3 devices On P2020 COMe module 0x66 OxA6 2 0x58 USBHUB1 On P2020 COMe module 2 0x60 6 bit DAC Not used for P2020 module Reserved Maxim MAX5362LEUK 2 0x90 Thermal sensor On P2020 COMe module National Semiconductor LM75CIM 3 2 OxDO RTC On P2020 COMe module 3 contact VGA chip On P2020 COMe module Contact vendor for datasheet and see vendor VOLARI Z11M P2020 COMe module User Guide for more details Note These addresses do not include the position of the LSB of the transmitted address the read write bit See Section
24. SET_REQ_B External CPU requests reset Full reset 3 2 Carrier Board Configuration Switches in a System with a P2020 COMe2 Module There are different types of COMe configurations A list of these configuration types and their implementation is shown in Table 16 Table 16 Carrier Board Configuration Types Configuration Type Implementation Requires software configuration to Implemented with DIP switches and or software settable options support evaluation Expected to be easily and often changed by the end user or developer COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 31 COM Express Carrier Architecture When Used with COMe2 Type Module The carrier board switches and their default settings when used with a P2020 COMe module are shown in Figure 21 Switch names exactly match the name on the schematics and on the printed circuit board in most cases except where a spare has been newly assigned and only the FPGA has changed sw4 1 2 3 4 5 6 7 38 a tet ttl lt Default Setting MSEL 0 3 4 b1011 EMI1_SELO SLOT2 EMI4_MDIO MDC for SGMII mode 2 SLOT3 EMl1_MDIOMDC for SGMII mode SPI Flash write protected SPI Flash NOT write protected Select alternate SDHC flash mode on the carrier Select alternate SPI flash mode on the carrier lt Default Setting 1 RMII PH
25. Y AN1_B disable RMII PHY AN1_B enable 1 RMII PHY ANO_B disable RMII PHY ANO_B enable Reserved Reserved 1 Reserved Reserved Disable backlight Enable LVDS backlight Disable LVDS VDD Enable LVDS VDD lt Default Setting lea Reserved PHYAD3 to 0 PHYAD3 to 1 PHYAD4 to 0 PHYAD4 to 1 Reserved gt E woun nn ltl t lt Default Setting Reserved Disable SW_AUTO_ON Enable SW_AUTO_ON Pp Reseved S SLOT3 EMI1_MDIO MDC for XAUI mode e EMI2_SEL1 gt gt Em2_seLo f gt AN_EN_A enable 1 RMII PHY ANO_A disable I RMII PHY ANO_A enable COM Express Carrier Development System Design Workbook Rev 1 32 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe2 Type Module pots st ofif s N lt Default setting TOM_ENET1_SEL JEN_TDM_ENET1_B MUX5_ENABLE MUX4_ENABLE MUX3_ENABLE MUX2_ENABLE MUX1_ENABLE BIOS_DIS enable boot from module microSD card a BIOS_DIS enable boot from Carrier SD card Figure 21 Carrier Board Switch Assignments and Defaults When Used with P2020 COMe Module For those signals configured using switches the configuration logic is as shown in Figure 22 EEPROM OVDD ENI FPGA P2020 CFGDR y hH gt gt CONFIG PIN where needed Figure 22 COMe2 Configuration Switch Logic and P2020 The def
26. Y s and the two SxHUBs 3 3 9 Carrier Use of the P2020 DMA Controller The P2020 DMA controllers have internal and external controls to initiate and monitor DMA activity The carrier board does not incorporate any specific devices that make use of the external pin controlled DMA controllers The P2020 DMA ports are connected to test points on the carrier board to allow external hardware control as needed COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 41 COM Express Carrier Architecture When Used with COMe2 Type Module 3 3 10 Carrier Use of P2020 eOpenPIC Interrupt Controller The carrier board contains numerous interrupt connections The P2020 eOpenPIC connections are as shown in Table 19 See the COMX P2020 COM Express Module more details on all of the interrupt signals implemented by the module Table 19 P2020 eOpenPIC Interrupt Connections to Carrier Board Devices Signal Names Connections IRQ0_B SLOT3 Sideband connector SGMII riser does not connect must use in band irq IRQ1_B DS3232 real time CLOCK and NVRAM IRQ2_B IRQ3_B IRQ4_B IRQ5_B MIC2076 USB Power FLAG for over current at USB connector IRQ6_B IRQ7_B Not Connected IRQ8_B FPGA TBD IRQ9_B FPGA TBD IRQ10_B IRQ11_B IRQ_OUT_B Not used as Interrupt but as an EVT pin 3 3 11 Carrier Use of P2020 GPIO Signals The I C1 interface on the
27. ___ gt _10G XAUiy OG XAUi 10G XAUI 1G T lt remii gt piy lt ie1 n Presem 1G T xPO lt RGMIVUSB gt pry 1G T gt ASAIO 8xSERDES pay eUS ha F B2 0 xUSB2 0 i 7 Sees USB ULPI gt ay USI 20 gt kup lt xUSB2 0 lt USB PHY lt USB PHY so iwm lt DDR3 1333 1600 72 bit gt Freescale lt _ 2xUART TwRx CTS RTS gt _ COME lt DDR3 1333 1600 72 bit gt P4080 lt SDIO MMC _ gt 4xl2C a 2xSATA gt SPI 3 CS 4x20 _________ gt Debug SD MMC RTC_CLK gt R TAG COP al lt RTC_BAT WDT gt Debu 2xRGMII 5 Aurora axusea0 0 NOR oe TwRx CTS ATS lt Localus gt Uboot FW Or 4xUART Tx rX NAND Flash Local Bus OS App 2xlIEEE 1588 1588 eg Nermibicdd ulse Stamp uh _ gt eset lt ___ Tamper Detect Figure 8 P4080 COMe Module Block Diagram 2 3 1 Carrier Board Use of P4080 DDR Interface See the COMX P4080 COM Express Module installation and user manual COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 15 COM Express Carrier Architecture When Used with COMe1 Type Module 2 3 2 Carrier Board Use of P4080 SerDes x18 Interface The SerDes block on the P4080 provides high speed serial communications interfaces for several internal devices The SerDes block on the P4080 COMe1 module provides 18 serial lanes for the carrier
28. ane 3 GHz Serbas a S2rdes 2 3 LA PCIE x2 2 Peis le OO COMe Socket dg Hen xe PCle xt 0 GPU DS90C385AMT Vea gt aM n eee 2x l2C 2x 12C lt _________ gt lt _ ___ gt 12C EEPROM 2c 1 AT24C02 2x 12C lt lt _ ____ _ _ gt ka me axic lt gt gt a 12C 2 12C 0 12C EEPROM RTC WARCHDOG AT24C02 M41ST85WMX6TR lt gt SPI 5 SPI FLASH SOCKET 2x 1588 FOR DEBUG ONLY 2x1588 lt _ gt e R 8x GPIO 4x GPI 4xGPO a MICRO SD CARD SOCKET SDHC SHDC somo E ah e lt 2xUART 2xUART 2xUART Figure 23 P2020 COMe Module Block Diagram 3 3 1 Carrier Board Use of P2020 DDR Interface See the COMX P2020COM Express Module installation and user manual COM Express Carrier Development System Design Workbook Rev 1 34 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe2 Type Module 3 3 2 Carrier Board Use of P2020 SerDes x18 Interface The SerDes block on the P2020 provides high speed serial communications interfaces for several internal devices The SerDes block on the P2020 COMe 2 provides 18 serial lanes for the carrier that may be partitioned as shown in Table 17 Note that the term lane is used to describe the minimum number of signals needed to create a bidirectional communications channel in the case of PCI Express or Serial RapidIO a lane consists of two differential pairs one for receive and one for transmit or four in all Table 17
29. ault action is for the FPGA to transfer the switch setting to the processor configuration pin during the CB_RESET_B assertion interval For certain COMe modules the I7C expander FPGA IO signals can select the multiplexer configurations COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 33 COM Express Carrier Architecture When Used with COMe2 Type Module 3 3 COM Express Carrier Board Functionality when Used with a P2020 COMe2 Module This section and its subsections are tailored to the carrier board functionality when used with the P2020 COMe 2 module specifically Figure 23 shows the P2020 COMe module block diagram Note that functional modules that only exist on the COMe module are described in the COMX P4080 COM Express Module installation and user manual 2G 64BIT DDR3 800 ECC DDR2 DDR3 g 42V oprapors 2ranks Slots e 5V standby lt gt JTAG Header COP AP USB ULPI USB 2 0 PH USB 2 0 USB 2 0 HUB 4x USB2 0 4x USB2 0 gt usessis gt UsB25141 lt gt lt gt pee ee zs ae e a a aa O PERRETE ETT m USB ULPI USB 2 0 PH USB 2 0_ USB 2 0 HUB 4x USB2 0 4x USB2 0 I wee pes USB25141 jess lt y nyForP1020 E o a ed a UE mF SRA Sa aa EE E E Ea S a gt oniyrorPio21 2xRGMII 1 3 eTSEC 1 3 cep 2 SE 2xGbE me BCM5482 RGMII 2 _ gt GE PHY 2 1x GbE 1xGbE Dual Core tsec 2 lt a Bomsa82 lt gt 1 2GHz DiM F
30. bug Header 2 3 5 Carrier Board Use of P4080 Local Bus Interface See the COMX P4080 COM Express Module installation and user manual for details Local bus connection to the carrier board is for Freescale internal use only COM Express Carrier Development System Design Workbook Rev 1 20 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe1 Type Module 2 3 6 Carrier Board Use of P4080 eSDHC Interface The P4080 has an enhanced secure digital host controller eSDHC The carrier board connects the P4080 eSDHC to an SDMedia card slot and uses GPIO signals for sideband signals such as write protect detect and card detect Both x4 and x8 cards are supported the latter using the SPI_CS_BJ 0 3 signals which can be reassigned as eSHDC_D 4 7 P4080 SDMedia Slot SDHC_CMD CMD SDHC_DAT 0 3 DAT 0 3 SDHC_CLK CLK SDHC_CD_B SDHC_CD CD_B SDHC_WP_B SDHC_WP WP_B SDHC_DAT 4 7 a DAT 4 7 Z Z Q O N a A gt lt Lu O O a CFG_SDX8MUX S Figure 13 P4080 eSDHC Interface to Carrier Board SD Media Card Slot NOTE SDHC_DAT 4 7 are shared with the SPI CS pins the CFG_SDX8MUX switch selects the routing of those pins to either the SDHC devices or the SPI devices but both cannot be used simultaneously COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 21 COM Express Carrier Architecture When Used with COMe1 Type Module 2 3 7 Carrier Board Use
31. conductor COM Express Carrier Architecture When Used with COMe1 Type Module P4080 ENET PHY M lt Z EC 1 Z A 7 Port 1 O EC 2 VILLE 2 J T Port 2s To USB2 Z U 5 l Port 3 O GTXCLK 125 MHz CLKBUF Figure 11 P4080 Ethernet Connections to the Carrier Board Table 7 summarizes the carrier board EC connections and routing when the COMe 1 is populated with a P4080 Table 7 P4080 Ethernet Port Locations on Carrier P4080 EC Connection Port PHY Address Location 1 1 0 Conn P9 top 2 2 1 Conn P9 bottom See Section 2 3 8 Carrier Board Use of P4080 USB Interfaces and COMX P4080 COM Express Module installation and user manual for more details on the use of these interfaces COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 19 COM Express Carrier Architecture When Used with COMe1 Type Module 2 3 4 Carrier Board Use of P4080 Support for IEEE Std 1588 Protocol The carrier board supports the P4080 IEEE 1588 precision time protocol PTP as shown in Figure 12 This facility works in tandem with an Ethernet controller to time stamp incoming packets P4080 1588 PULSEOUT 1 2 ALARMOUT 1 2 TRIGIN 1 2 STMP_TX RX 1 2 a oO O oO I D J Q oO QO XTALOSC 125 000 MHz CLKIN CLKOUT 25 ppm Figure 12 P4080 IEEE 1588 Interface to Carrier Board P6880 De
32. elopment System Design Workbook Rev 1 Freescale Semiconductor 13 COM Express Carrier Architecture When Used with COMe1 Type Module For those signals configured using switches the configuration logic is as shown in Figure 7 EEPROM where needed Figure 7 COMe1 Configuration Switch Logic and P4080 The default action is for the FPGA to transfer the switch setting to the processor configuration pin during the CB_RESET_B assertion interval For certain COMe modules the I7C expander FPGA IO signals can select the multiplexer configurations COM Express Carrier Development System Design Workbook Rev 1 14 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe1 Type Module 2 3 COM Express Carrier Board Functionality when Used with a P4080 COMe1 Module The ways in which the COMe1 module affects the functionality of the carrier board also depends on the specific processor used in the COMe1 module This section and its subsections are tailored to the carrier board functionality when used with the P4080 COMe1 module specifically Figure 8 shows the P4080 COMe module block diagram Note that functional modules that only exist on the COMe module are described in the COMX P4080 COM Express Module installation and user manual lt 10G XAUI x4PCle 4x1G SGMI gt lt a Cle x4PCle 4xSRIO 4x1G SGMI gt lt __ _____ _ x4PCle 4xSRIO __
33. es first followed by the COMe module type features and then the processor device specifics and how they are used by the carrier board COM Express Carrier Development System Design Workbook Rev 1 2 Freescale Semiconductor COMExprsDS Features and Architecture 1 COMExprsDS Features and Architecture The general features of the COMExprsDS are as follows e Carrier COMe connectors and supported functions that include the following e Mu Standard ATX power supply connector One SD card MMC connector Two dual CAN connectors SerDes PCI Express PCIe connector Five PCle x4 connectors connector A through connector F which can support up to four lanes of PCIe 2 0 1 0 SGMII sRIO and XAUI depending on what processor is used Two PCle x1 connectors used as sideband connectors for the PCIe x4 connectors and one PCIe x1 connector used for a TDM riser to support SLIC functionality Eight USB2 0 connectors Four SATA II connectors One DVI I connector to support either analog VGA via an adapter or digital DVI connector LVDS A and B ports to support two single link DFP TFT panel displays with optional LVDS panel and touchscreen functionality Two UART DB 9 RS 232 connectors UARTO 1 serial ports that operate at up to 115200 Kbps One stereo audio jack Three gigabit Ethernet ports 0 1 3 supporting one dual and one single GMII 1 GHz RJ 45 Ethernet connectors One dual port PHY supporting one dual RM
34. for all reset conditions to clear 2 Configures and releases the processor from reset 3 Idles waiting for further reset conditions to occur Table 4 summarizes the reset conditions and actions of the FPGA when used with a COMe1 module Table 4 Reset Conditions and Actions of FPGA Reset Sequencer Signal Type Description Action HOT_RST_B External HOT power stable Restarts all FPGA internal state machines and registers PWRGD External ATX power stable Causes full system reset unless the system is in S3 power down state SYS_HRST_B_ External COP tool reset request Upon power good sys_rst_b is sent from carrier to COMe1 module RESET_REQ_B External CPU requests reset Full reset 2 2 Carrier Board Configuration Switches When Used with a P4080 COMe1 Module There are different types of carrier board configurations A list of these configuration types and their implementation is shown in Table 5 Table 5 Carrier Board Configuration Types Configuration Type Implementation Requires software configuration to Implemented with DIP switches and or software settable options support evaluation Expected to be easily or often changed by the end user or developer COM Express Carrier Development System Design Workbook Rev 1 12 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe1 Type Module The carrier board switches and their default settings
35. in a System with a P2020 COMe2 Module provides the FPGA and external configuration switch settings used for start up configuration information for U Boot or Linux when the system is used as an embedded platform COM Express Carrier Development System Design Workbook Rev 1 6 Freescale Semiconductor COMExprsDS Features and Areniectur 1 2 Difficult to Find COMe Carrier Connections Figure 2 highlights connections that are difficult to find on the COM Express carrier board L ATX power connector SW3 power on button SW1 local reset CPLD programming header FPGA programming header Figure 2 Difficult to Find Connections COM Express Carrier Top View COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 7 COMExprsDS Features and Architecture 1 3 System Logic CPLD and FPGA Architecture and Functionality The carrier board contains a CPLD used for power sequencing and an FPGA that implements the following functions e Transfers switch settings to processor board configuration signals e Performs reset sequencing e Enables disables functions based on processor type e Implements miscellaneous system logic IC timeout reset TBD The CPLD is implemented with a MAX II and the FPGA is implemented in an Altera Cyclone HI EP3C16F484C8 in a 484 256 pad micro BGA Figure 3 shows the overall
36. lation and user manual and Mentor Embedded Linux For Freescale COMe P2020 System Builder Quick Start Guide for more details 2 3 17 Carrier Board Clock Generation from P4080 COMe1 Module Board The carrier board clock signals are generated by the COMe module board in use Table 13 lists the requirements of the carrier board clock signals when the carrier board is populated with a P4080 COMel module For more details on the P4080 COMe1 module see the COMX P4080 COM Express Module installation and user manual Table 13 Carrier Board Clock Requirements When Used with P4080 COMe1 Module P 3 Clock COMe1 Clock Signal Corresponding Carrier Board Clock Signal Frequency Type SD1 REFCLK SLOT1 REFCLK p n LVDS SD2 REFCLK P4080 SD2_REFCLK p n 156 25 MHz LVDS SLOT2 REFCLK p n or SLOT3 REFCLK p n 125 00 MHz SD3 REFCLK P4080 SD3_REFCLK p n 156 25 MHz LVDS or 125 00 MHz SLOT5 REFCLK p n LVDS COM Express Carrier Development System Design Workbook Rev 1 28 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe1 Type Module Figure 19 shows the principal clock connections from the P4080 COMe1 module to the carrier board OSC 24M USB2 0 HUB USB25141 RTC 32 768K TC P16C557 03LE 100M 125M Ethernet reference clock SERDES bank1 reference clock SERDES bank2 reference clock SERDES banks reference clock X2 Aurora Connector COME Connector Figure
37. on the module type with which it is used Figure 5 depicts the general features and connectivity of the COM Express carrier board when used with a COMe1 type module board COMEXPRESS CARRIER COMe1 GBEO 3 MIDI 4 USB 2 0 ports 4 USB 2 0 ports HDRS QE UART STM1403A Tamper det Dual DB9 gt UART2 3 ser defined SECURITY hdr ee GPIO RS 485 Oniy DART I2C BC NOR Flash LBC 12C 3 12C 2 TouchIF PI spy SPIFlash SDHC SD MMC conn ow soxn euse xXy pue VWOd4 4CAN CAN g CONN 1588 SIGNALS HDR VGA CLOCKS DVI I DV ATX CONN an ad LVDS A B DFP CONN Dual nen xe Figure 5 COM Express Carrier Block Diagram When Used with COMe 1 Type Module a ep O O D O gt D 2 Q Lanes 0 3 HOIS 819d gols 810d e118 10d as 0S 819d Lanes 4 7 Lanes 16 19 Lanes 20 23 Lanes 24 S OIS 819d COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 11 COM Express Carrier Architecture When Used with COMe1 Type Module 2 1 System Reset Performed by FPGA Reset Sequencer in a System with a COMe1 Module The carrier board FPGA contains a reset sequencer that properly manages the orderly bring up of the system this is not the same as the power sequencer which is similar but not specifically related to reset After the system transitions to having fully stable power supplies the reset sequencer does the following 1 Waits
38. ont panel UART I O board that is located at the front of the chassis The default mode is 4 wire so RTS CTS flow control is supported on these connectors For the P2020 DS kit P2020COMe DS PB UART ports 0 and 1 are supported 3 3 V P2020 UART 1 ITLL Port 1 Top port 2 09 x an A 8 UART 0 N MUX wo z Port 0 Bottom port O O gt HOT 3 3 V cfg_pixisuart Figure 31 P2020 UART Serial Port Connection to Carrier Board Serial Port Connector COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 43 COM Express Carrier Architecture When Used with COMe2 Type Module 3 3 14 Carrier Board Use of P2020 IC Interfaces The carrier board uses three of the four available C SMB buses The I C1 master from the FPGA accesses the EEPROM on the COMe module to read 256 bytes of EEPROM processor type data before the carrier system reset is asserted to the module P2020 IS O am m W Q Z FPGA a Z So Y O 12C1 O 12C1_MAS a 12C2 cr 12C2_ SLAVE Oo A 12C3 i 12C3_SLAVE gt O O DVIVGA LVDS Figure 32 P2020 C Connectivity to Carrier Board FPGA I C bus device addresses are summarized in Table 21 Table 21 P2020 I2C Bus Device Map Philips PCA9545APW C 2 I C Bus Address Device Notes 1 0x21 Reserved 1 0x22 Reserved 1 0x23 1O Expander
39. others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off QorlQ is a trademark of Freescale Semiconductor Inc All other product or service names are the property of their respective owners The Power Architecture and Power org word marks and the Power and Power org logos and related marks are trademarks and service marks licensed by Power org 2011 Freescale Semiconductor Inc 2 freescale Power semiconductor
40. re serial ports PG I C bus 1 can be used for the following e Boot initialization code e System EEPROM MAC address storage serial number and so on e Processor EEPROM for COMe module and processor ID from IC master in the carrier FPGA e Expander to interface to C slave in the carrier FPGA TBD I C bus 2 can be used for the following e RTC on the COMe module e interface to LVDS control I C bus 3 can be used for the following e interface to VGA control Clocking e SerDes clock buffers for XAUI SGMII Serial RapidlO and PCI Express slots e RMII clock and buffers GPIO Eight GPIOs come from I C expander COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor COMExprsDS Features and Architecture Table 2 COMExprsDS Device Interfaces continued Device Feature Configuration Options IRQs EVENT switch normally asserts IRQ but can drive SRESETO and or SRESET1 via software setting Power ATX power supply to COMExpress connector VCC_12 VCC_5_STBY VCC_RTC_BAT 1 1 1 Development System Use In the absence of special hardware or software configuration the COMExpress development system operates identically to a development evaluation system such as ArgoNavis 8641DS or other members of the HPC family 1 1 2 Embedded Use Section 2 2 Carrier Board Configuration Switches When Used with a P4080 COMe1 Module and Section 3 2 Carrier Board Configuration Switches
41. resses on the carrier board are summarized in Table 10 Table 10 P4080 I2C Bus Device Map for Carrier Board IC Bus I CAddress Device Notes 1 0x21 Reserved 1 0x22 Reserved 1 0x23 IO Expander Not used for P4080 module Reserved Philips PCA9555PW 1 0x34 CODEC Not used for P4080 module Reserved Wolfson WM8776SEFT 1 0x64 DDR3 DIMM2 On P4080 COMe module 1 0x66 DDR3 DIMM1 On P4080 COMe module 1 0x98 Thermal sensor On P4080 COMe module ON Semiconductor ADT7461ARMZ 1 OxAO 4 Kbyte EEPROM Boot configuration C EEPROM on P4080 COMe module Atmel AT24C02C or equivalent 1 OxA4 Remote IC IO Expander On carrier Read only See datasheet for programming instructions Philips PCA9672PW Device ID 1 OxA8 4 Kbyte EEPROM Stores 256 bytes of processor type data Atmel AT24C64A or equivalent Write protectable 1 OxDO RTC On P4080 COMe module COM Express Carrier Development System Design Workbook Rev 1 26 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe1 Type Module Table 10 P4080 IC Bus Device Map for Carrier Board continued IC Bus I CAddress Device Notes 1 0xDC Clockgen for SD BANK1 On P4080 COMe module IDT 9FG104DGILFT 1 0x57 C slave port Not used for P4080 Reserved 2 0x58 USB HUB2 On P4080 COMe module 2 0x60 6 bit DAC Not used for P4080 module Reserved Maxim MAX5362LEUK Note These addre
42. rogramming P4080 QorlQ Integrated Multicore Communication Processor Family Reference Manual P4080RM P2020 QorlQ Integrated Multicore Communication Processor Family Reference Manual P2020RM Switch configuration P4080DS Configuration Sheet P2020DS Configuration Sheet SystemID format The SystemID Format for Power Architecture Development Systems AN3638 COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 49 How to Reach Us Home Page www freescale com Web Support http Awww freescale com support USA Europe or Locations Not Listed Freescale Semiconductor Inc Technical Information Center EL516 2100 East Elliot Road Tempe Arizona 85284 1 800 521 6274 or 1 480 768 2130 www freescale com support Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French www freescale com support Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor China Ltd Exchange Building 23F No 118 Jianguo Road Chaoyang District Beijing 100022 China 86 10 5879 8000 support asia
43. sses do not include the position of the LSB of the transmitted address the read write bit See Section 4 Programming Model for PC implementation information 2 3 15 Carrier Board Use of P4080 EM1 and EM2 Management Buses The P4080 has the following types of buses e SGMII and RGMII PHY management e XAUIPHY management Because one set of buses must span across multiple devices on the carrier board multiplexers are used to route from the P4080 to each PHY and switches are used to control these multiplexers PHY management bus control is summarized in Table 11 and Table 12 Table 11 P4080 PHY Management Bus Map for EMI1 on Carrier Board Bus SW4 3 4 Device EMI1 00 On board RGMI PHYI EMI1 01 Slot 2 SGMII EMI1 10 Slot 3 SGMII Table 12 P4080 PHY Management Bus Map for EMI2 on Carrier Board Bus SW8 4 5 Device EMl2 00 No Device EMI2 01 No Device EMI2 10 No Device EMI2 11 Slot 3 XAUI 2 3 16 Carrier Board Use of P4080 Debug Features The carrier board provides a JTAG COP header and AURORA test points for debug purpose using the CodeWarrior USBTAP already installed in the system COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 27 COM Express Carrier Architecture When Used with COMe1 Type Module To upgrade the U Boot stored on the COMe module s NOR FLASH use the CodeWarrior USBTAP tool See the COMX P4080 COM Express Module instal
44. that may be partitioned as shown in Table 6 Note that the term lane is used to describe the minimum number of signals needed to create a bidirectional communications channel in the case of PCI Express or Serial RapidIO a lane consists of two differential pairs one for receive and one for transmit or four in all Table 6 top down shows the following clocking banks and how they are configured by the carrier board e Bankl lanes A D go to slot 1 E H to slot 2 and I J to the Aurora debug connector e Bank2 lanes A D go to slot 3 e Bank3 lanes A B go to SATA ports 1 and 2 Table 6 P4080 SerDes Lane Multiplexing Configurations on Carrier Bank 1 Bank 2 Bank 3 A B C D E F G H l J A B C D A B C D 0 11 23 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Aurora Conn on SATA SATA SLOT arene COMe Module ators Porti Port2 PCle1 PCle2 Debug 5 2 5G XAUI FM2 SATA1 SATA2 5 2 5G 5 2 5G PCle1 SGMII SGMII SGMII SGMII Debug 5 2 5G XAUI FM2 SATA1 SATA2 5 2 5G FM2 FM2 FM2 FM2 sRIO2 sRIO1 Debug 5 2 5G XAUI FM2 SATA1 SATA2 2 5G 2 5G sRIO2 sRIO1 Debug 2 5G SGMII SGMII SGMII SGMII SATA1 SATA2 2 5G 2 5G FM2 FM2 FM2 FM2 sRIO2 sRIO1 Debug 5 2 5G PCle3 SATA1 SATA2 2 5G 2 5G 5 2 5G PCle1 sRIO1 Debug 5 2 5G XAUI FM2 SATA1 SATA2
45. top down shows the following clocking banks and how they are configured by the carrier board e Bank1 lanes 0 3 go to slot 1 e Bank2 lanes 4 7 go to slot 2 e Bank3 lanes 16 17 go to slot 3 Table 17 P2020 SerDes Lane Multiplexing Configurations on Carrier Bank 1 Bank 2 Bank 3 A B C D E FIGH C J 0 1 2 3 4 5 6 7 16 17 SLOT 1 SLOT 2 SLOT 3 PCle1 PCle2 PCle3 5 2 5G 5 2 5G 5 2 5G COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor 35 COM Express Carrier Architecture When Used with COMe2 Type Module PCle Cards Z 6 O dp VHA oc PCle Cards A 2 lt LLI 5 O PCle Cards REFCLK_SD1 p n al 100 MHz Figure 24 P2020 SerDes Bank1 to Carrier Board Cards Configuration NOTE The SD2 and SD3 clocking domains use separate clock generators COM Express Carrier Development System Design Workbook Rev 1 36 Freescale Semiconductor COM Express Carrier Architecture When Used with COMe2 Type Module 3 3 3 Carrier Board Use of P2020 Ethernet Controller EC Interfaces The carrier board uses up to two 10 100 1000baseT triple speed Ethernet controllers ECs of the P2020 as follows e EC2 is connected to the on board PHY using the RGMII protocol the remaining ports are unused P2020 ENET PHY M lt Z EC 1 LLL VILL LLL 3 Z Port 1 Z g O g
46. tor using Freescale PQ MDS QOC3 card HDLC module and connector using Freescale PQ MDS 16T1E1 card TDM based SLIC modules Fast Ethernet PHY RMII MII SSI based CODECs 1588 header support is TBD e Other functions routed from the COMe module to carrier board devices are Local bus 128 Mbyte NOR FLASH on COMe1 module for Freescale debug purposes only eSDHC Connects to SDMedia card slot for boot code or mass storage SPI 16 Mbyte EEPROM module for boot code and storage Control interface for LVDS touchscreen rC Three C controllers from COMe module One C2 master implemented in FPGA to read I C2 EEPROM to determine processor type I C1 to PC expander to generate eight GPIOs five to FPGA three to IXXAT module C2 to control LVDS interface and FPGA I C2 slave mux demux for COMe2 P1021 P1012 only C3 to control DVI VGA interface and FPGA C3 slave mux demux for COMe2 P1021 P1012 only Debug features Legacy COP JTAG and USBTAP headers for use with CodeWarrior software e System logic CPLD and FPGA other functions CPLD manages power sequencing Enabling disabling of functions based on processor type Mux demux functions for QE functions based on I C2 or I C3 slave register settings C1 master reads processor type COM Express Carrier Development System Design Workbook Rev 1 Freescale Semiconductor e Clocks COMExprsDS Features and Architecture
47. um size for non extended addressing 4 1 2C Slave Format The I2C1 bus is used to drive the I C expander on the COMe carrier board Figure 34 shows the mapping of FPGA_GPIO and IXATT_GPIO0 signals that are used to select QUICC Engine multiplexers and functions via software Byte 0 Access Read Write 0 7 R Ww Reset All zeros Figure 34 I7C Slave Byte Signal Mapping Table 27 i2C Byte Field Descriptions Bits Signals 0 IXATT_GPIOO 1 FPGA_GPIO4 2 IXXAT_GPIO2 COM Express Carrier Development System Design Workbook Rev 1 48 Freescale Semiconductor Revision History Table 27 i2C Byte Field Descriptions continued Bits Signals IXXAT_GPIO3 FPGA_GPIOO FPGA_GPIO1 FPGA_GPIO2 NIOJ oO AJ FPGA_GPIO3 5 Revision History Table 28 provides a revision history for this design workbook Table 28 Document Revision History Rev Number Date Substantive Change s 1 02 2011 In the second paragraph changed the definition of SBC to be single board computing 0 01 2011 Initial public release Appendix A References Table A 1 lists useful documentation references Table A 1 Useful References Topic Document Title Document ID System design P4080 QorlQ Integrated Processor Hardware Specifications P4080EC P2020 QorlQ Integrated Processor Hardware Specifications P2020EC SoC p
48. vision History 00 0 e eee eee eee 49 Ais REPETENCES fh s in5 sloth sistarbinainaes cetacean Sith dataset 49 lop oe 2 freescale semiconductor Table 1 shows the processors currently supported by each COMe module type and the orderable part number for each kit Table 1 Supported Processors and Kit Ordering Information COMe Module Type Processor Kit Part Number COMe1 P4080 P4080COMe DS PB COMe2 P2020 P2020COMe DS PB P4080 COMe1 P2020 COMe2 a aa P5020 P5010 P2010 P1020 P4040 P 3041 P1011 P1021 1012 Figure 1 How Various Module Types Fit into the Common Carrier Board NOTE In the future the COM Express carrier board will support the P5020 P5010 P4040 P3041 P2010 P1021 P1020 P1011 P1012 and P1013 devices Having a common carrier architecture that supports all of these devices as plug in modules saves development time and money because many devices can be evaluated with only a single investment in the remaining components of the development system the peripheral IO modules chassis and power supply remain unchanged The COME xprsDS feature set is determined primarily by the type of COMe module in use and then by the actual processor on the module Based on this feature set the development system provides typical OS dependent resources disk Ethernet and so on for that configuration Therefore this document describes the general development system featur

COM Express Carrier Development System Design Workbook

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