FPGA SPARTAN 3 an Evaluation Kit
Contents
1. e 50 MHz crystal oscillator clock source e 40 pin I O connector for interface external peripherals modules e JTAG port for download user program through cable e 9V AC DC power input through adapter e On board 5V 3 3V and 1 2V regulators 2 1 General Block Diagram Join the Technical Community Today http www pantechsolutions net 9V Input 5V 3 3V 1 2V anes OR 2 CH UART Serial Comm IN System FLASH 8 Nos LED Digital Outputs XILINX SPI based DAC SPI based ADC 5x1 MATRIX Keyboard i 40 pin I O 8 Slide Switch connector Digital Inputs 2x16 Char n XC3S50AN Buzzer 50MHz Clock SPI based generator Temn Sensor 3 Jumper amp Switch Details ADC External Input JP1 External Input to CH1 External Input to CHO ADC Channel O JP2 Internal Trim Pot Input External Input ADC Channel 1 JP3 Internal Temperature Sensor Input External Input Join the Technical Community Today http www pantechsolutions net Enable Buzzer Disable Buzzer Program Execution Mode Selection EXE MODE JTAG FLASH J3 MODE1 JTAG Programming MODE2 Flash Programming 4 Connector Details 40pin Box Connector J2 1041 1 2 1042 te y 1043 3 4 104 n i045 5 CS 5 Oe O46 1047 So 1047 7 8 TOO Sse HEER ieee l O55 13 14 To8g 1054 ora 2059 15 16 Toads O58 GND 17 18 GN 5V 19 20 5V GND 71 22 GND W3 23 24 3V3 1068 gt 1579 y 38 1078S 10889 1070 gt2. A Lines o pos e 7 3 JTAG Programmer The FPGASP3 Kit includes a JTAG programming and debugging chain Pantech JTAG3 low cost parallel to JTAG cable is included as part of the kit and connects to the JTAG header DB 25 parallel port connector to 6 pin female header connector The JTAG cable connect directly to the parallel port of a PC and to a standard 6 pin JTAG programming header in the kit can program a devices that have a JTAG voltage of 1 8V or greater Join the Technical Community Today http www pantechsolutions net 6 Pin JTAG SPARTAN3 Heade Signals FPGA Lines JTAG Cable III ee a DI P2 T Programmer The Pantech low cost parallel port to JTAG cable fits directly over the header stake pins as shown in above figure When properly fitted the cable is perpendicular to the board Make sure that the signals at the end of the JTAG cable align with the labels listed on the board The other end of the Pantech cable connects to the PC s parallel port The Pantech cable is directly compatible with the Xilinx iMPACT software Join the Technical Community Today http www pantechsolutions net Pantech solutions creates information packed technical documents like this one every month And our website is a rich and trusted resource used by a vibrant online community of more than 1 00 000 members from organization of all shapes and sizes Join the Technical Community Today http www pantechsolutions ne
3. This document is owned by 4 www pantechsolutions net Republishing or redistribution is prohibited CPLD FPGA BOARDS FPGA SPARTAN 3 an Evaluation Kit Contents Mig VR UOC CUO TN eea E ce cues we seeped eee EE EE N E E N eters eae 3 i P Fa ore 2 E a ee ee ee ee ee eee 3 1 2 Technical OF Customer SUpport aesese cease cecen Soanencsscorscanveaneacoucocesus Sosataenieomacavousteaed ntereetousseas 3 2 Key Components and ea CU OS asc cst ctessoncs tusccoeebesenee taboseutectisacu suncesetatiavaus eecaawiedt meas meceaneeteemee 3 2 1 General BIOCK Diagr ii ccc asec seancsu watts acewetanssenmsassesessasecusntacaucesaccatoosseedesdeapasinattareeasiecasenees 4 3 PUMA OTe Wea DCU ING sorsien ien 5 4d CORI CU ON Deta eara EE tecoee oer carate EE EE E arameseeasdeteanssomaen 6 gt POWE S 0 een nen E eee er eee E ee eee 7 o ROA POE Cia Sacer saeco ste E E E ENS 7 6d HUENCEMIUNE DIOdES sesccso nse eact otwacnce caisaeiat aseacabarau dence EENE EARE Ea 8 WAD Fe ere a 9 10 seen eee eee ee eee 9 oo 2X16 Char LED Di 9 serienummer E ee ee eee 10 645S DIV Ted ON a nsn A ens stems seneceuede rues sonetanacenanes 11 Se ean OM MOTO ereerermrnr te E ee ere eee G50 BUZZ er MIL CI OE E creat TE EE ee tome EE E EAEE AE P PE PAD a cc cere E E A EA E TE A N EE E E N BE SAG E A S E E E E A E E E 7 Pernpherals SecHon e Mesmerer 13 7 1 RS 232 Communication USART sesssssesssssssesssessrsssressrensrrnsrensernserssesssses
4. aa KX 1072 073 See 29 30 ore tup o zl 32 COT 1078 079 Se 33 34 COB G82 ioga 4088 35 36 NOB 1084 loas 55 See 37 38 COB 1587 1088 39 40 1090 1088 S i090 i EXTENSION CONN JTAG Connector Join the Technical Community Today http www pantechsolutions net O 1 oN O A 5 Power Supply The external power can be AC or DC with a voltage between 9V 1A output at 230V AC input The SPARTAN3AN board produces 5V using an LM7805 voltage regulator which provides supply to the peripherals Separate On Off Switch SW1 for controlling power to the board ON OFF SW2 Power 5V ON External through Adaptor Power 0V OFF There are multiple voltages supplied on the Spartan 3AN Evaluation Kit 3 3V and 1 2V regulators Similarly the 3 3V regulator feeds all the VCCO voltage supply inputs to the FPGA s I O banks and powers most of the components on the board The FPGA configuration interface on the board is powered by 3 3V Finally a 1 2V regulator supplies power to the FPGA s VCCINT voltage inputs which power the FPGA s core logic The board uses three discrete regulators to generate the necessary voltages 6 On board Peripherals The Development Kit comes with many interfacing options e 8 Nos Slide Switches for digital inputs e 8 nos of Point LEDs for Digital outputs e 2x16 Character LCD interface Join the Technical Community Today http www pantechsolutions net O
5. alog SPI DAC Join the Technical Community Today http www pantechsolutions net SPARTAN3AN DAC SELECTION DAC PIN FPGA Lines P58 s oe Co e 6 9 Buzzer Interface 5V continuous buzzer connected through FPGA s I O pins P5 to enable buzzer place jumper JP7 at E label mark position Buzzer Module Spartan3 FPGA pins Buzzer P5 make port pins to high buzzer will activated J5 Buzzer P64 To Enable Buzzer 7 Peripherals Section Il 7 1 RS 232 Communication USART USART stands for Universal Synchronous Asynchronous Receiver Transmitter FPGASP3AN Kit provides an RS232 port that can be driven by the Spartan 3AN FPGA A subset of the RS232 signals is used on the Spartan 3AN kit to implement this interface RxD and TxD signals Join the Technical Community Today http www pantechsolutions net e RS 232 communication enables point to point data transfer It is commonly used in data acquisition applications for the transfer of data between the microcontroller FPGA and a PC e The voltage levels of a FPGA and PC are not directly compatible with those of RS 232 a level transition buffer such as MAX3232 be used UART SPARTAN3AN Serial Port Section DB 9 Connector FPGA Lines SPARTAN3AN 7 2 Clock Source The FPGASP3 Kit has a dedicated 50 MHz series clock oscillator source and an optional socket for another clock oscillator source SPARTAN3 Crystal Oscillator FPG
6. ave Out 2 MOSI Master Out Slave In 3 SCK Serial Clock 4 CS Chip Select 2 CHANNEL ADC CS SHDNO 1 8 O VoolVeer cH0g 2 z 7 OCLK CHIC 3 rs 6 CO Dan FJ Join the Technical Community Today http www pantechsolutions net SPARTAN3AN ADC PIN EPGA Lines ADC CHANNEL SELECTION MCP3202 CHANNEL 1 As you know in synchronous serial communication their is a clock line SCK in case of SPI which synchronizes the transfer The clock is always controlled by the MASTER In our case the Spartan3AN is the MASTER and the MCP3202 is a slave on the bus SPI is full duplex that means data can be sent and received simultaneously SPI Transfer A SPI transfer is initiated by the MASTER pulling the CS line low The CS line sits at HIGH during idle state Now master can write to the bus in 8bit or 1 byte chunks One most important thing to note about SPI is that for every byte MASTER writes to SLAVE the MASTER receives one byte in return So the only transaction possible is exchange of data Their is no separate Read and Write commands their is only one command and that is Write 6 7 12 Bit SPI DAC The controller designed coverts the digital data into analog where the digital data is transferred using SPI Controller and DAC MCP4921 converts the serial data into the analog SPI Controller controls the speed data transmission DAC selection etc Based on the inputs from the SPI line DAC MCP4921 coverts the 12 bit data to an
7. e 5x1 Matrix Keypad interface Buzzer Interface Clock Source 12 Bit SPI ADC 12 Bit SPI DAC Buzzer JTAG Programmer UART for serial port communication through PC 6 1 Light Emitting Diodes Light Emitting Diodes LEDs are the most commonly used components usually for displaying pin s digital states The FPGASP3 KIT has 8 nos of Point LEDs connected with port pins details tabulated below the cathode of each LED connects to ground via a 3300 resistor To light an individual LED drive the associated FPGA control signal to High p Point LEDs XC3S200 Pins LED Selection N H m A H O lt 2 O eo pt Make Pin High LED ON Make Pin Low LED OFF Join the Technical Community Today http www pantechsolutions net 6 2 Digital Inputs e This is another simple interface of 8 Nos of slide switch mainly used to give an input to the port lines and for some control applications also e The FPGASP3AN KIT slide switches SW7 SW14 directly connected with FPGA 1 0 lines details tabulated below user can give logical inputs high through slide switches The switches are connected to 3 3V in order to detect a switch state by default lines are pull downed through resistors The switches typically exhibit about 2 ms of mechanical bounce and there is no active de bouncing circuitry although such circuitry could easily be added to the FPGA design programmed on the board A 10KQ se
8. eessseesseeseeeseee 13 FD O SOC E a E EE EE E EE E E 14 TE a e Ee Fae E E E E E EE E EE E E 14 Join the Technical Community Today http www pantechsolutions net 1 Introduction The intention of the design is to endorse the engineers and scholars to exercise and explore the capabilities of FPGA architectures with many interfacing modules on board point LEDs Slide switches LCD ADC DAC Buzzer UART and Push Buttons with ease to create a stand alone versatile test platform 1 1 Packages e Spartan 3AN Evaluation Kit XC3S50AN e Serial Port Cable e JTAG Programming Cable e Printed User Manual e CD contains o Software Programmers ISE o Example Programs o User Manual 1 2 Technical or Customer Support Post your questions Pantech forum www pantechsolutions net forum Website www pantechsolutions net 2 Key Components and Features On Chip Features e 50 000 gate Xilinx Spartan 3AN FPGA in a 144 TQG XC3S50 4TQG144C Join the Technical Community Today http www pantechsolutions net 1 584 logic cell equivalents 54K bit block RAMs Three 18x18 hardware multipliers Two Digital Clock Managers DCMs Up to 108 user defined I O signals On Board Features e 8 Nos Slide Switches for digital inputs e 8 nos of Point LEDs for Digital outputs e 2x16 Character LCD interface e 5x1 Matrix Keypad interface e RS 232 Serial Port e 12 Bit SPI ADC e 12 Bit SPI DAC e Buzzer
9. ries resistor provides nominal input protection Slide switch XC3S200 Pins Slide Switch Logic WV H A H lt m Make Switch Close High Make Switch Open Low Join the Technical Community Today http www pantechsolutions net 6 3 2x16 Char LCD Display The 2x16 character LCD interface card with supports both modes 4 bit and 8 bit interface and also facility to adjust contrast through trim pot In 8 bit interface 11 lines needed to create 8 bit interface 8 data bits DO D7 three control lines address bit RS read write bit R W and control signal E The LCD controller is a standard KS0070B or equivalent which is a very well known interface for smaller character based LCDs E LCD MODULE XC3S200 Pins 2x16 LCD Selection CONTRO N LLJ Z lt Jn lt m Join the Technical Community Today http www pantechsolutions net 6 5 5x1 Matrix keypad Keypads arranged by matrix format each row and column section pulled by high all row lines and column lines connected directly by the I O pins PUSH BUTTON SW1 ei pas i D PUSH BUTTON SW2 PUSH sr SW Iam eee PUSH BUTTON SW3 ee P31 ey Krush PUSH BUTTON SW4 a i Keus S PUSH BUTTON SW5 6 6 12 Bit ADC These ADCs are SPI Bus based which is a serial bus So the number of pins in IC is very low Total of 4 lines are required to interface it with FPGA 1 MISO Master In Sl
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