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STM8S007C8T6 Datasheet

1. Address Block Register Label Register Name ueni 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x17 2 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CCR Condition code register 0x28 god SC Reserved area 85 bytes 0x00 7F60 CPU CFG GCR Global configuration register 0x00 0x00 7F70 ITC SPR1 Interrupt software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt software priority register 2 OxFF 0x00 7F72 ITC SPR3 Interrupt software priority register 3 OxFF 0x00 7F73 m ITC SPR4 Interrupt software priority register 4 OxFF 0x00 7F74 ITC SPR5 Interrupt software priority register 5 OxFF 0x00 7F75 ITC SPR6 Interrupt software priority register 6 OxFF 0x00 7F76 ITC SPR7 Interrupt software priority register 7 OxFF 0x00 7F77 ITC SPR8 Interrupt software priority register 8 OxFF peu Reserved area 2 bytes 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 DEAE Reserved area 15 bytes er DoclD022171 Rev 5 35 92 Memory and register map STM8S007C8 Table 9 CPU SWIM debug module interrupt controller registers continued
2. Address Block Register Label Register Name a 0x00 7F90 DM BK1RE DM breakpoint 1 register extended byte OxFF 0x00 7F91 DM BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM BK1RL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM BK2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BK2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM debug module control register 1 0x00 0x00 7F97 DM CR2 DM debug module control register 2 0x00 0x00 7F98 DM CSR1 DM debug module control status register 1 0x10 0x00 7F99 DM CSR2 DM debug module control status register 2 0x00 0x00 7F9A DM ENFCTR DM enable function register OxFF ed Biag Reserved area 5 bytes 1 Accessible by debug module only 2 Product dependent value see Figure 4 Memory map 36 92 DoclD022171 Rev 5 d STM8S007C8 Interrupt vector mapping 7 Interrupt vector mapping Table 10 Interrupt mapping lees Description atau om Wakauputom Vector address RESET _ Reset Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 TLI External top level interrupt 0x00 8008 1 AWU Auto wake up from halt Yes 0x00 800C 2 CLK Clock controller 0x00 8010 3 EXTIO Port A external interrupts Yes Yes 0x00 8014 4 EXTI1 Port
3. 43 9 1 6 Loading capacitor 43 9 1 7 Pin input voltage 43 9 2 Absolute maximum ratings 44 9 3 Operating conditions sus gor RE a x xo Rr dad sawed eek Pew eds 46 9 3 1 VCAP external capacitor 48 9 3 2 Supply current characteristics 48 9 3 3 External clock sources and timing characteristics 56 9 3 4 Internal clock sources and timing characteristics 58 9 3 5 Memory characteristics 60 9 3 6 I O port pin characteristics 61 9 3 7 Reset pin characteristics 70 9 3 8 SPI serial peripheral interface 72 9 3 9 IC interface characteristics 75 9 3 10 10 bit ADC characteristics 77 9 311 EMC characteristics 80 Package information 5 294 dns cen Osos ee nem os cee BK EK dem 83 10 1 LQFP48 package information 83 10 2 Thermal characteristics 86 10 2 1 Reference document 86 10 2 2 Selecting the product temperature range
4. devices with two Vggig pins 160 Total output current sunk sum of all I O and control pins for We 80 devices with one Vssio pin Injected current on NRST pin 4 linsen PP Injected current on OSCIN pin 4 Injected current on any other pin 4 Zlinuem Total injected current sum of all I O and control pins 6 20 Data based on characterization results not tested in production All power Vip Vppio Vppa and ground Vss Vssio Vssa pins must always be connected to the external supply I O pins used simultaneously for high current source sink must be uniformly spaced around the package between the Vppjo Vssio pins IiNj piN must never be exceeded This is implicitly insured if Vy maximum is respected If Vin maximum cannot be respected the injection current must be limited externally to the liy piy value A positive injection is induced by Vin gt Vpp while a negative injection is induced by Vin lt Vss For true open drain pads there is no positive injection current and the corresponding VIN maximum must always be respected Negative injection disturbs the analog performance of the device See note in Section 9 3 10 10 bit ADC characteristics on page 77 When several inputs are submitted to a current injection the maximum Zliny pin is the absolute sum of the positive and negative injected currents instantaneous values These results ar based on characterization with Zliny pin maxi
5. 22 STM8S007C8 pin description 22 Flash Data EEPROM and RAM boundary addresses 27 I O port hardware register map I Ih 27 General hardware register map 29 CPU SWIM debug module interrupt controller registers 35 Interrupt MAPPING aua desk nas eee ae Re x Ra dte a Na ka ua anna QUE ae 37 leen 38 Option byte description n 39 Voltage characteristics 44 Current characteristics 45 Thermal characteristics 45 General operating conditions 46 Operating conditions at power up power down 47 Total current consumption with code execution in run mode at Vpp 25V 49 Total current consumption with code execution in run mode at Vpp 3 8 V 50 Total current consumption in wait mode at Vbp 5V 51 Total current consumption in wait mode at Vpp 3 8 V 51 Total current consumption in active halt mode at Vpp 5 V Ta 40 to 85 C 52 Total current consumption in active halt mode at Vpp 3 3V 52 Total current consumption in halt mode at Vpp 5 V Ta 40 to 85
6. 78 92 Table 43 ADC accuracy with Ran lt 10 KQ Vppa 5 V Symbol Parameter Conditions Typ Max fapc 2 MHz 1 0 2 5 IErl Total unadjusted error 1 fApc 4 MHz 14 3 fane 6 MHz 1 6 3 5 fane 2 MHz 0 6 2 0 IEol Offset error N fApc 4 MHz 1 1 2 5 fapc 6 MHz 1 2 2 5 fapc 2 MHz 0 2 2 IE Gain error N fapc 4 MHz 0 6 2 5 fac 6 MHz 0 8 2 5 fane 2 MHz 0 7 1 5 Ep Differential linearity error 1 fApc 4 MHz 0 7 1 5 fapc 6 MHz 0 8 1 5 fane 2 MHz 0 6 1 5 ELI Integral linearity error 1 fapc 4 MHz 0 6 1 5 fac 6 MHz 0 6 1 5 Unit LSB ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for ling pin and Zlwupmn in Section 9 3 6 does not affect the ADC accuracy Table 44 ADC accuracy with Ran lt 10 KO Ram VppA 3 3 V Symbol Parameter Conditions Typ Max fac 2 MHz 1 1 2 0 Erl Total unadjusted error c fApc 4 MHz 1 6 2 5 f 2 MHz 0 7 15 Eo Offset error ADC fApc 4 MHz 1 8 2 0 f 2 MHz 0 2 15 EG Gain error ADC fapc
7. 128 kHz Operating mode S RC oscillator 68 i Off Power down mode 128 kHz 11 45 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register Table 23 Total current consumption in active halt mode at Vpp 3 3 V Conditions Symbol Parameter Main voltage Typ Unit regulator Flash mode Clock source MVR HSE crystal osc 16 MHz 600 Operating mode 5 LSI RC osc 128 kHz 200 n Supply current in HSE crystal osc 16 MHz 540 Ipp AH ici dide imode Power down mode uA LSI RC osc 128 kHz 140 Operating mode 66 Off k LS RC osc 128 kHz m Power down mode 9 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register d 52 92 DoclD022171 Rev 5 STM8S007C8 Electrical characteristics Total current consumption in halt mode Table 24 Total current consumption in halt mode at Vpp 5 V TA 40 to 85 C Symbol Parameter Conditions Typ Max Unit Flash in operating mode HSI 63 5 i Ge Ba F clock after wakeup upply current in halt mode u an Flash in power down mode HSI 6 5 35 clock a
8. Symbol Parameter Conditions Min Typ Max Unit Operating voltage Von all modes execution write erase fopu lt JONE 2 95 um i Standard programming time including erase for byte word block 6 0 6 6 ms iiis 1 byte 4 bytes 128 bytes Fast programming time for 1 block 128 bytes 30 eee oms torase Erase time for 1 block 128 bytes i 3 0 3 3 ms Erase write cycles 160 i program memory Now Ta 85 C cycles Erase write cycles took i data memory Data retention program memory after 100 erase write cycles at 20 Ta 85 C Tret 55 C tRer Data retention data memory after 20 years 10k erase write cycles at Ta 85 C Data retention data memory after BES 100 k erase write cycles at TA 85 C Teer ng Supply current Flash programming or 20 mA DD erasing for 1 to 128 bytes 1 Data based on characterization results not tested in production 2 The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte d DoclD022171 Rev 5 STM8S007C8 Electrical characteristics 9 3 6 O port pin characteristics General characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resi
9. 3 2 1 0 accuracy 1 2 VDD V ai15067c d 58 92 DoclD022171 Rev 5 STM8S007C8 Electrical characteristics Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Ta Table 32 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fis Frequency 128 kHz Lut sn LSI oscillator wakeup time S 70 us Jop sn LSI oscillator power consumption R 5 5 HA 1 Guaranteed by design not tested in production Figure 15 Typical LSI frequency variation vs Vpp 25 C 396 296 gt 1 g 0 nm S S 1 2 3 2 5 3 3 5 4 4 5 5 5 5 6 Von V ai15070V2 Ly DocID022171 Rev 5 59 92 Electrical characteristics STM8S007C8 9 3 5 60 92 Memory characteristics RAM and hardware registers Table 33 RAM and hardware registers Symbol Parameter Conditions Min Unit VRM Data retention mode Halt mode or reset Vir max V 1 Minimum supply voltage without losing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production 2 Refer to Table 17 on page 47 for the value of Vir may Flash program memory data EEPROM memory General conditions T4 40 to 85 C Table 34 Flash program memory data EEPROM memory
10. For typical current consumption measurements Vpp Vppio and Vppa are connected together in the configuration shown in Figure 5 Figure 5 Supply current measurement conditions 5Vor3 3V Vopa Vppio Vss Vssa Vssio d DoclD022171 Rev 5 STM8S007C8 Electrical characteristics 9 1 5 Pin loading conditions 9 1 6 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6 Figure 6 Pin loading conditions L STM8 pin T WI 9 1 7 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7 Figure 7 Pin input voltage l STM8 pin WW I DoclD022171 Rev 5 43 92 Electrical characteristics STM8S007C8 9 2 44 92 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 13 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage including Vppa and Vppio 0 3 6 5 Input voltage on true open drain pins PE1 PE2 Vss 0 3 6 5 V VN Input voltage on any other pin Vss 0
11. HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a I duplication of the function DoclD022171 Rev 5 21 92 Pinouts and pin descriptions STM8S007C8 22 92 Table 4 Legend abbreviations for STM8S007C8 pin description table Type input O output S power supply floating Input wpu weak pull up Ext interrupt external interrupt HS high sink O1 Slow up to 2 MHz Output Speed O3 Fast slow programmability with slow as default state after reset O4 Fast slow programmability with fast as default state after reset OD open drain PP push pull Reset state Bold X pin state after internal reset release Unless otherwise specified the pin state is the same during the reset phase and after the internal reset release Table 5 STM8S007C8 pin description Input Output c E pa 25 Alternate a E 9 S x e Giele function 3 Pin name Se E E v 3r alternate E Fls 32 0 gjaja 5 function after remap 8 5 oja a5 option bit OI 1 NRST I O X Reset 2 PA1 OSCIN VOL X x O1 X X Port a1 Resonator crystal in 3 PAzOSCOUT vol x XIX for x x PortA2 Resonator crystal out 4 Vssio
12. fe y life augmented STM8S007C8 Value line 24 MHz STM8S 8 bit MCU 64 Kbytes Flash true data EEPROM 10 bit ADC timers 2 UARTs SPI IC Features e Core Max fcpy up to 24 MHz 0 wait states fopu lt 16 MHz Advanced STM8 core with Harvard architecture and 3 stage pipeline Extended instruction set Max 20 MIPS 24 MHz e Memories Program 64 Kbytes Flash data retention 20 years at 55 C after 100 cycles Data 128 bytes true data EEPROM endurance 100 kcycles RAM 6 Kbytes e Clock reset and supply management 2 95 to 5 5 V operating voltage Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC Clock security system with clock monitor Wait active halt amp halt low power modes Beripheral clocks switched off individually Permanently active low consumption power on and power down reset e Interrupt management Nested interrupt controller with 32 interrupts Up to 37 external interrupts on 6 vectors e Timers 2x 16 bit general purpose timers with 2 3 CAPCOM channels IC OC or PWM Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization 8 bit basic timer with 8 bit prescaler Auto wakeup timer Window watchdog independent watchdog Datasheet production data LQFP48 7x7
13. 4 MHz 0 5 2 0 f 2 MHz 0 7 1 0 Ep Differential linearity error ADE fapc 4 MHz 0 7 1 0 fane 2 MHz 0 6 15 Ej Integral linearity error ADG fapc 4 MHz 0 6 1 5 Unit LSB ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for ling pin and Zliny pin in Section 9 3 6 does not affect the ADC accuracy DoclD022171 Rev 5 Ly STM8S007C8 Electrical characteristics Figure 37 ADC accuracy characteristics A i EG i Pai c e 1LSB 7 t 1021 IDEAL 1024 BAe ye Er MM i E uk 7 pt 14 3 i 71 1 A 1 1 64 E dh NN ES E D B Eo d e EL L A AZ 1 1 1 L i 1 1 ra 1 3 L P Ep 25 lt gt 1d 4 ing 1 LSBipgaL i L I l LL l L 0 1 2 3 4 5 6 7 1021102210231024 Vssa VDDA 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line Ey Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual tr
14. C Package pitch No character 0 5 mm Packing TR No character Tray or tube TR Tape and reel For a list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you DoclD022171 Rev 5 2 Refer to Table 1 STM8S007C8 value line features for detailed description I STM8S007C8 STM8 development tools 12 12 1 I STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation system supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STM8 is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STM8 application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in appli
15. NSS SCK MOSI MISO Table 40 SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode 0 10 SCK SPI clock frequency MHz Vtcisck Slave mode 0 6 ec SPI clock rise and fall time Capacitive load C 30 pF 25 tysck Lues NSS setup time Slave mode 4 X tMASTER tss NSS hold time Slave mode 70 1 IMGOKH SCK high and low time Master mode tscx 2 15 tgcK 2 15 w SCKL t 1 Master mode 5 SuMD Data input setup time tsu Sl Slave mode 5 1 Master mode 7 ns thm Data input hold time this Slave mode 10 tao Data output access time Slave mode 3 x MASTER taisoy 9 Data output disable time Slave mode 25 tyso II Data output valid time Slave mode after enable edge 75 tmo Data output valid time Master mode after enable edge 30 inso Slave mode after enable edge 31 G Data output hold time th MO Master mode after enable edge 12 1 Values based on design simulation and or characterization results and not tested in production 2 Mintimeis for the minimum time to drive the output and the max time is for the maximum time to validate the data 3 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z 72 92 DoclD022171 Rev 5 Ly STM8S007C8 Electrical characteristics Figure 33 SPI timing diagram slave mode and CPHA 0
16. manual RM0016 e For information on programming erasing and protection of the internal Flash memory please refer to the PM0051 How to program STM8S and STM8A Flash program memory and data EEPROM e For information on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e For information on the STMB core please refer to the STM8 CPU programming manual PM0044 I DoclD022171 Rev 5 STM8S007C8 Description 2 I Description The STM8S007C8 value line 8 bit microcontrollers offer 64 Kbytes Flash program memory They are referred to as high density devices in the STM8S microcontroller family reference manual RM0016 The STM8S007C8 value line devices provide the following benefits reduced system cost performance robustness short development cycles and product longevity The system cost is reduced thanks to a true data EEPROM for up to 100 k write erase cycles and a high system integration level with internal clock oscillators watchdog and brown out reset Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced characteristics which include robust I O independent watchdogs with a separate clock Source and a clock security system Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout memory map and modular periphera
17. refer to the application note AN1181 Table 47 ESD absolute maximum ratings Symbol Ratings Conditions Class pomi Unit V Electrostatic discharge voltage TA 25 C conforming to A 2000 V ESD HBM Human body model JESD22 A114 V Electrostatic discharge voltage Ta 25 C conforming to IV 1000 V ESD CDM Charge device model JESD22 C101 1 Data based on characterization results not tested in production d DoclD022171 Rev 5 81 92 Electrical characteristics STM8S007C8 82 92 Static latch up Two complementary static tests are required on 10 parts to assess the latch up performance e A supply overvoltage applied to each power supply pin e A current injection applied to each input output and configurable I O pin is performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 48 Electrical sensitivities Symbol Parameter Conditions Class Ta 25 C A LU Static latch up class Ta 85 C A 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard d DoclD022171 Rev 5 STM8S007C8 Package information 10 Package information To meet
18. 1 s I O ground 5 Vss S Digital ground 6 VCAP s 1 8 V regulator capacitor 7 Vpp S Digital power supply 8 Wppio 1 s I O power supply Timer 2 TIM3 CH1 9 PA3 TIM2_CH3 VO X X X O1 X X Port A3 channel3 AFR1 10 RMUARTIRX Lo x x x lus o3 x X Port aa VART receive 11 PAS UART1 TX WO XX HS O3 X X Port A5 CARTI transmit UART1 12 PAG UART1 CK l O X X X HS O3 X X Port A6 synchronous clock DoclD022171 Rev 5 Ly STM8S007C8 Pinouts and pin descriptions Table 5 STM8S007C8 pin description continued Input Output c 5 ge Alternate 2 KH E S x 20 ee function 3 Pin name Ec E E v 3r alternate F s a 9 gjalla T5 function after remap 8 3 E 5 amp oja a5 option bit LL 13 VppA S Analog power supply 14 Vssa Analog ground 15 PB7 AIN7 VO X X X O1 X X Port B7 alog input 7 16 PB6 AING VO X X X O1 X X Port Be alog input 6 Analog DC SDA 17 PB5 AIN5 VOI X X X O1 X X Port B5 input 5 AFRG Analog DC SCL 18 PB4 AIN4 VOI X X X O1 X X Port B4 ud AFR6 Analog TIM1 ETR 19 PB3 AIN3 VOIX X X O1 X X Port B3 Fee AFRS Analo iur 20 PB2 AIN2 V OXIX x O1 X X Port B2 a CH3N P AFR5 Analo OM 21 PB1 AIN1 VOIX X X Ot X X Port B1 Sen CH2N p AFR5 Analo TM 22 PBO AINO V OXIXI x O1 X X Port BO PS CH1N P AFR5 23
19. 3 Vpp 0 3 Vppx Vppl Variations between different power pins 50 mi Vssx Vss Variations between all the different ground pins 50 see Absolute maximum VEsp Electrostatic discharge voltage ratings electrical sensitivity on page 81 1 All power Vip Vppio Vppa and ground Vss Vssio Vssa pins must always be connected to the external power supply 2 lnJ PIN must never be exceeded This is implicitly insured if Vin maximum is respected If Vin maximum cannot be respected the injection current must be limited externally to the liy j piyy value A positive injection is induced by Vin gt Vpp while a negative injection is induced by Viy Vas For true open drain pads there is no positive injection current and the corresponding VIN maximum must always be respected d DoclD022171 Rev 5 STM8S007C8 Electrical characteristics Table 14 Current characteristics Symbol Ratings Max Unit lvpp Total current into Vpp power lines source 2 60 lyss Total current out of Vss ground lines sink 60 is Output current sunk by any I O and control pin 20 Output current source by any I Os and control pin 20 Total output current sourced sum of all I O and control pins for devices with two Vppjo pins 200 Total output current sourced sum of all I O and control pins for devices with one Vppjo pin 100 A li d B Total output current sunk sum of all UO and control pins for
20. Address Block Register label Register name ee 0x00 5250 TIM1 CR1 TIM1 control register 1 0x00 0x00 5251 TIM1 CR2 TIM1 control register 2 0x00 0x00 5252 TIM1 SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1 ETR TIM1 external trigger register 0x00 0x00 5254 TIM1 IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1 SR1 TIM1 status register 1 0x00 0x00 5256 TIM1 SR2 TIM1 status register 2 0x00 0x00 5257 TIM1 EGR TIM1 event generation register 0x00 0x00 5258 TIM1 CCMR1 TIM1 capture compare mode register 1 0x00 0x00 5259 TIM1 CCMR2 TIM1 capture compare mode register 2 0x00 0x00 525A TIM1 CCMR3 TIM1 capture compare mode register 3 0x00 0x00 525B TIM1 CCMR4 TIM1 capture compare mode register 4 0x00 0x00 525C TIM1 CCER1 TIM1 capture compare enable register 1 0x00 0x00 525D TIM1 CCER2 TIM1 capture compare enable register 2 0x00 0x00 525E TIM1 CNTRH TIM1 counter high 0x00 0x00 525F TIM1 CNTRL TIM1 counter low 0x00 0x00 5260 ZER TIM1 PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1 PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1 ARRH TIM1 auto reload register high OxFF 0x00 5263 TIM1 ARRL TIM1 auto reload register low OxFF 0x00 5264 TIM1 RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1 CCR1H TIM1 capture compare register 1 high 0x00 0x00 5266 TIM1 CCR1L TIM1 capture compare register 1 low 0x00 0x00 5267 TIM1 CCR2H TIM1 capture compare register 2 high 0x00 0x00 5268 TIM1 CCR2L TIM1 capture compare register 2 low 0x00 0x00 5269 TIM1
21. B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTIS Port D external interrupts Yes Yes 0x00 8020 7 EXTI4 Port E external interrupts Yes Yes 0x00 8024 8 Reserved 0x00 8028 9 Reserved 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 41 TIM1 Re CU 0x00 8034 12 TIM1 TIM1 capture compare 0x00 8038 13 TIM2 TIM2 update overflow s S 0x00 803C 14 TIM2 TIM2 capture compare 0x00 8040 15 TIM3 Update overflow 5 0x00 8044 16 TIM3 Capture compare 0x00 8048 17 UART1 Tx complete 0x00 804C 18 UART1 Receive register DATA FULL 0x00 8050 19 Ee DC interrupt Yes Yes 0x00 8054 20 UART3 Tx complete s 0x00 8058 21 UART3 Receive register DATA FULL 0x00 805C 22 ADC2 ADC2 end of conversion 0x00 8060 23 TIM4 TIM4 update overflow 0x00 8064 24 Flash EOP WR PG DIS 0x00 8068 Reserved 0x00 806C to 0x00 807C 1 Except PA1 er DoclD022171 Rev 5 37 92 Option bytes STM8S007C8 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one NOPTXx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in Table 11 Option bytes below Option bytes can also be modified o
22. C 53 Total current consumption in halt mode at Vpp 3 3V 53 Wakeup liries AA 53 Total current consumption and timing in forced reset state 54 Peripheral current consumption 54 HSE user external clock characteristics 56 HSE oscillator characteristics 57 HSI oscillator characteristics 58 LSI oscillator characteristics 59 RAM and hardware registers 60 Flash program memory data EEPROM memory 60 I O static characteristics rh 61 Output driving current standard ports 63 Output driving current true open drain ports 63 Output driving current high sink ports 64 NRST pin characteristics 70 SPI characteristics sy sarias ai misie hn 72 IC characteristics PA 75 ADG characteristics exe RE aaa a dass e dtu KENA ed dem de ps 77 ADC accuracy with RA lt 10 KQ Vppa DN 78 ADC accuracy with RAIN lt 10 kQ RAIN Vppa EV 78 EMS data sinusite aa Edle haies Va dete ed GR Ra epa ide 80 SIE ENEE EN ESD absolute ma
23. CCR3H TIM1 capture compare register 3 high 0x00 0x00 526A TIM1 CCR3L TIM1 capture compare register 3 low 0x00 0x00 526B TIM1 CCR4H TIM1 capture compare register 4 high 0x00 0x00 526C TIM1 CCR4L TIM1 capture compare register 4 low 0x00 0x00 526D TIM1 BKR TIM1 break register 0x00 0x00 526E TIM1 DTR TIM1 dead time register 0x00 0x00 526F TIM1 OISR TIM1 output idle state register 0x00 a E Reserved area 147 bytes 32 92 DoclD022171 Rev 5 d STM8S007C8 Memory and register map Table 8 General hardware register map continued Address Block Register label Register name at 0x00 5300 TIM2 CR1 TIM2 control register 1 0x00 0x00 5301 TIM2 IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2 SR1 TIMe status register 1 0x00 0x00 5303 TIM2 SR2 TIMe status register 2 0x00 0x00 5304 TIM2 EGR TIM2 event generation register 0x00 0x00 5305 TIM2 CCMR1 TIM2 capture compare mode register 1 0x00 0x00 5306 TIM2 CCMR2 TIM2 capture compare mode register 2 0x00 0x00 5307 TIM2 CCMR3 TIM2 capture compare mode register 3 0x00 0x00 5308 TIM2 CCER1 TIM2 capture compare enable register 1 0x00 0x00 5309 TIM2 CCER2 TIM2 capture compare enable register 2 0x00 0x00 530A TIM2 TIM2 CNTRH TIM2 counter high 0x00 0x00 530B TIM2 CNTRL TIM2 counter low 0x00 00 530C0x
24. NSS input te SCK 2 cPHA 0 a CPOL 0 x CPHA 0 a CPOL 1 ta SO th SO MISO e OUTP UT BITS OUT MOSI i INBUT BI T1 IN Y semn Y IN ai14134c Figure 34 SPI timing diagram slave mode and CPHA 10 NSS input f ISU NSS ep ie te SCK gt i tnynss i 3 CPHA 1 i Y a CPOL 0 id iN bh n l Slam se MEN H l Ke t i II SO ste t la T SCKp Le ty ta SO gt Le v SO h SO Ft SC dis SO gt i MISO m Wi OUTPUT C MSH OUT BIT6 OUT i LSB OUT su Sl pi n s MOSI EN INPUT MSB IN BITI IN LSB IN ai14135 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp d DoclD022171 Rev 5 73 92 Electrical characteristics STM8S007C8 Figure 35 SPI timing diagram master mode High NSS input fe SOK 3 CPHA 0 8 CPOL 0 i E i 1 1 1 x CPHA 0 I i o D 1 SCK Output OO 32 it O LI l CPHA 1 i i CPOL 1 NO KIN SN Lt i l l l I tw SCKH i A m SCK Isu MI lt gt Awer gt di ME TS 1 w ju p INPUT 1 MSBIN BITS IN LBN l th OUTPUT wear i B 1 OUT isor OU ai14136V2 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp 74 92 DoclD022171 Rev 5 d STM8S007C8 Electrical characteristics 9 3 9 d I C interface characteristics Table 41 I C characteristics faster Must be at least 8 MHz to achi
25. Supply current ih fopu fuasrER 16 MHz HSE user ext clock 16 MHz 2 7 5 8 run mode HSI RC osc 16 MHz 2 5 3 4 code HSE user ext clock 16 MHz 1 2 4 10 exce fopu fMaster 128 125 kHz from RAM HSI RC osc 16 MHz 1 0 1 3 fopu fmasTER 128 15 625 kHz HSI RC osc 16 MHz 8 0 55 fcpu fMASTER 128 kHz LSI RC osc 128 kHz 0 45 ST HSE crystal osc 24 MHZ 11 4 PU IMASTER Z ga S HSE user ext clock 24 MHz 10 8 18 HSE crystal osc 16 MHz 9 0 Supply 7 e q curr nt i fcpu fuasrER 16 MHz HSE user ext clock 16 MHz 8 2 15 2 run mode HSI RC osc 16 MHz 8 1 13 2 0 code executed CPU MAsrER 2 MHz HSI RC osc 16 MHz 8 2 1 5 S from Flash fopu fMASTER 1 28 125 kHz HSI RC osc 16 MHz 1 1 fopu fmasTER 128 en HSI RC osc 16 MHz 8 0 6 fopy fMASTER 128 kHz LSI RC osc 128 kHz 0 55 DoclD022171 Rev 5 Unit mA 49 92 Electrical characteristics STM8S007C8 Table 19 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit t sat HSE crystal osc 24 MHz 4 0 H SE HSE user ext clock 24 MHz 3 7 7 3 HSE crystal osc 16 MHz 2 9 Suppl Get i fopu master 16 MHz HSE user ext clock 16 MHz 2 7 5 8 run mode HSI RC osc 16 MHz 2 5 3 4 Cad d HSE user ext cl
26. TIM2_PSCR TIM2 prescaler register 0x00 0x00 530D TIM2_ARRH TIM2 auto reload register high OxFF 0x00 530E TIM2 ARRL TIM2 auto reload register low OxFF 0x00 530F TIM2 CCR1H TIM2 capture compare register 1 high 0x00 0x00 5310 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5311 TIM2 CCR2H TIM2 capture compare reg 2 high 0x00 0x00 5312 TIM2 CCR2L TIM2 capture compare register 2 low 0x00 0x00 5313 TIM2 CCR3H TIM2 capture compare register 3 high 0x00 0x00 5314 TIM2 CCR3L TIM2 capture compare register 3 low 0x00 E Reserved area 11 bytes 0x00 5320 TIM3 CR1 TIMS control register 1 0x00 0x00 5321 TIM3 IER TIMS interrupt enable register 0x00 0x00 5322 TIM3 SR1 TIMS status register 1 0x00 0x00 5323 TIM3 SR2 TIMS status register 2 0x00 0x00 5324 TIM3 EGR TIM3 event generation register 0x00 0x00 5325 TIM3 TIM3 CCMR1 TIM3 capture compare mode register 1 0x00 0x00 5326 TIM3 CCMR2 TIMS capture compare mode register 2 0x00 0x00 5327 TIM3 CCER1 TIM3 capture compare enable register 1 0x00 0x00 5328 TIM3 CNTRH TIM3 counter high 0x00 0x00 5329 TIM3 CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIM3 prescaler register 0x00 er DoclD022171 Rev 5 33 92 Memory and register map STM8S007C8 Table 8 General hardware register map continued Address Block Register label Register name Wee 0x00 532B TIM3 ARRH TIM
27. Trigger from TIM1 TRGO e End of conversion EOC interrupt 4 14 Communication interfaces The following communication interfaces are implemented e UART1 full feature UART SPI emulation LIN2 1 master capability SmartCard mode IrDA mode single wire mode e UARTS3 full feature UART LIN2 1 master slave capability e SPI full and half duplex 10 Mbit s e lC upto 400 Kbit s d DoclD022171 Rev 5 17 92 Product overview STM8S007C8 4 14 1 UART1 Main features 1 Mbit s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode Asynchronous communication UART mode Full duplex communication NRZ standard format mark space Programmable transmit and receive baud rates up to 1 Mbit s fopy 16 and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes A Address bit MSB Idle line interrupt Transmission error detection with interrupt generation Parity control Synchronous communication Full duplex synchronous transfers SPI master operation 8 bit data communication Maximum speed 1 Mbit s at 16 MHz fcpu 16 LIN master mode Emission generates 13 bit synch break frame Reception detects 11 bit break frame 4 14 2 UART3 Main features 18 92 1 Mbit s full duplex SCI LIN mast
28. V 3 301 1 Data based on characterization results not tested in production Typical output level curves Figure 20 to Figure 27 show typical output level curves measured with output on a single pin Figure 19 Typ Vo Vpp 5 V standard ports e lo mA MS19400V2 64 92 DoclD022171 Rev 5 ky STM8S007C8 Electrical characteristics Figure 20 Typ Vo Vpp 3 3 V standard ports Vol V lo mA MS19401V2 Figure 21 Typ Vo 9 Vpp 5 V true open drain ports 1 25 amp 4 3 0 75 0 5 0 25 0 0 5 10 15 20 25 loL mA MS19402V2 Ly DoclD022171 Rev 5 65 92 Electrical characteristics STM8S007C8 66 92 Figure 22 Typ Vo Vpp 3 3 V true open drain ports 2 p 1 5 1 25 2 1 o gt 0 75 0 5 0 25 0 0 2 4 6 8 10 12 14 lot mA MS19403V2 Figure 23 Typ Vo 9 Vpp 5 V high sink ports 2 o gt 0 5 10 15 20 25 lot mA MS19404V2 d DoclD022171 Rev 5 STM8S007C8 Electrical characteristics Figure 24 Typ Vo 9 Vpp 3 3 V high sink ports lo mA MS19405V2 Figure 25 Typ Vpp Von Vpp 5 V standard ports VoL V loL mA MS19406V2 d DoclD022171 Rev 5 67 92 Electrical characteristics STM8S007C8 Figure 26 Typ Vpp Von Vpp 3 3 V standard ports Vol V lot mA MS19407V2 Figure 27 Typ Vpn Von
29. VcAp parameters is given by the design of the internal regulator To calculate Ppmax Ta use the formula Ppmax Timax Ta Oya see Section 10 2 Thermal characteristics on page 86 with the value for I Jmax given in Table 16 above and the value for O ja given in Table 50 Thermal characteristics 4 Refer to Section 10 2 Thermal characteristics on page 86 for the calculation method d 46 92 DoclD022171 Rev 5 STM8S007C8 Electrical characteristics Figure 8 f pymax Versus Vpp fce u MHz 24 Functionality not guaranteed in 16 this area 12 7 Functionality guaranteed with 0 wait state 8 1 4 0 2 95 4 0 5 0 5 5 Supply voltage V MS19413V1 Table 17 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate 20 5 oo typp us V Vpp fall time rate 20 s oo Reset release A 1 trEMP delay Vpp rising i 1 700 ms Power on reset Vir threshold 2 65 2 8 2 95 V Brown out reset Vi threshold 2 58 2 73 2 88 V Brown out reset VHYS BOR hysteresis i d my 1 Guaranteed by design not tested in production 2 f Vpp is below 2 95 V the code execution is guaranteed above the Vir and vir thresholds RAM content is kept The EEPROM programming sequence must not be initiated d DoclD022171 Rev 5 47 92 Electrical characteristics STM8S007C8 9 3 1 9 3 2 48 92 VCAP external capacit
30. instructions software breakpoints e Two advanced breakpoints 23 predefined configurations Interrupt controller e Nested interrupts with three software priority levels e 32 interrupt vectors with hardware priority e Up to 33 external interrupts on six vectors including TLI e Trap and reset interrupts Flash program and data EEPROM memory e 64 Kbytes of high density Flash program single voltage Flash memory e 128 bytes true data EEPROM e Read while write Writing in data memory possible while executing code in program memory e User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash program memory data EEPROM and option bytes To perform in application programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to Figure 2 DocID022171 Rev 5 Ly STM8S007C8 Product overview d The size of the UBC is prog
31. master features Clock generation A Start and stop generation IC slave features Programmable I2C address detection Stop bit detection Generation and detection of 7 bit 10 bit addressing and general call Supports different communication speeds A Standard speed up to 100 kHz Fast speed up to 400 kHz I DoclD022171 Rev 5 STM8S007C8 Pinouts and pin descriptions 5 Pinouts and pin descriptions Figure 3 LQFP 48 pin pinout Q o i x m 9 oo Zz bp ER lq m ug ZE E TITI To x x en LO ed Ci wNwoZo ono0z lumus mum 11 FEFEEESEOQY I GECHDDDD HESS ESSLILILL R NODIDANTOO NG g Qooonoaao LLI LLI LLI LLI DOO O OO OO oO a NA D 48 47 46 45 44 4342 41 40 39 38 NRST H1 e 36 IPG1 OSCIN PA1 12 350 PGO OSCOUT PA2 13 341 PC7 HS SPI MISO Vssio 1 4 33 I PC6 HS SPI MOSI Vss 5 32 1 Vppio 2 VCAP Oe 31 Vssio 2 Vpp O7 300 PC5 HS SPI SCK Vppio 1 8 299 PC4 HS TIM1_CH4 TIM3 CH1 TIM2 CH3 PA3 g9 28 PC3 HS TIM1_CH3 UART1 RX HS PA4 10 27 D PC2 HS TIM1_CH2 UART1_TX HS PAS 11 267 PC1 HS TIM1 CH1 UART1_CK HS PA6 C12 250 PES SPI_NSS 1314151617 18192021 222324 LI LT LT ET ELT ET ET LT ET ET ET rn O 10 st CO QN TO NG Aa oo m ca c cm ww LILO OL OO ES D ON TO dao 2222222222 LLLLLLLLL lt X DR mo SIE o OU ITI o oz 99 9 Sas EE EE 1
32. uA Vpb V ai15068c 1 The pull up is a pure resistor slope goes through 0 Table 36 Output driving current standard ports Symbol Parameter Conditions Min Max Unit VoL Output low level with 8 pins sunk lio 10 mA Vpp 5V S 2 Output low level with 4 pins sunk lio 24 mA Vpp 3 3 V 100 Von Output high level with 8 pins sourced ez 10 mA Vip 5 V 2 8 s iy Output high level with 4 pins sourced le 4 MA Vpp 3 3 V 2 11 1 Data based on characterization results not tested in production Table 37 Output driving current true open drain ports Symbol Parameter Conditions Max Unit lio 10 mA Vpp 5V Output low level with 2 pins sunk lo 10 MA Vip 3 3 V lio 20 mA Vpp 5V 1 Data based on characterization results not tested in production d DoclD022171 Rev 5 63 92 Electrical characteristics STM8S007C8 Table 38 Output driving current high sink ports Symbol Parameter Conditions Min Max Unit Outputlowlevel with 8pinssunk lo i0mA Vpp 5V 08 Vor Output low level with 4 pins sunk lio 10 mA Vpp 3 3 V 100 Output low level with 4 pins sunk lo 20 mA Vpp 5 V 1 50 Output high level with 8 pins sourced lo 10 mA Vip 5 V 4 0 E Vox Output high level with 4 pins sourced lo 10mA Vpp2 333 V 2140 Output high level with 4 pins sourced lio 20 mA Vpp 5
33. 0F3 BEEP BEEP_CSR BEEP control status register Ox1F Wara Reserved area 12 bytes 0x00 5200 SPI CR1 SPI control register 1 0x00 0x00 5201 SPI CR2 SPI control register 2 0x00 0x00 5202 SPI ICR SPI interrupt control register 0x00 0x00 5203 pa SPI SR SPI status register 0x02 0x00 5204 SPI DR SPI data register 0x00 0x00 5205 SPI CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF pe Reserved area 8 bytes 0x00 5210 I2C CR1 DC control register 1 0x00 0x00 5211 I2C CR2 DC control register 2 0x00 0x00 5212 pA GC FREQR DC frequency register 0x00 0x00 5213 l2C OARL IC own address register low 0x00 0x00 5214 l2C OARH DC own address register high 0x00 0x00 5215 Reserved 30 92 DoclD022171 Rev 5 I STM8S007C8 Memory and register map Table 8 General hardware register map continued Address Block Register label Register name aries 0x00 5216 I2C DR DC data register 0x00 0x00 5217 I2C SR1 DC status register 1 0x00 0x00 5218 I2C SR2 I2C status register 2 0x00 0x00 5219 I2C SR3 IC status register 3 0x00 0x00 521A e l2C ITR I2C interrupt control register 0x00 0x00 521B I2C CCRL I2C clock control register low 0x00 0x00 521C 12C_CCRH DC clock control register high 0
34. 1 0x02 0x00 5013 PD CR2 Port D control register 2 0x00 DoclD022171 Rev 5 27 92 Memory and register map STM8S007C8 Table 7 I O port hardware register map continued Address Block Register label Register name aga 0x00 5014 PE ODR Port E data output latch register 0x00 0x00 5015 PE IDR Port E input pin value register 0x00 0x00 5016 Port E PE DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE CR2 Port E control register 2 0x00 0x00 5019 PF ODR Port F data output latch register 0x00 0x00 501A PF IDR Port F input pin value register 0x00 0x00 501B Port F PF DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 0x00 501E PG ODR Port G data output latch register 0x00 0x00 501F PG IDR Port G input pin value register 0x00 0x00 5020 Port G PG DDR Port G data direction register 0x00 0x00 5021 PG CR1 Port G control register 1 0x00 0x00 5022 PG CR2 Port G control register 2 0x00 0x00 5023 PH ODR Port H data output latch register 0x00 0x00 5024 PH IDR Port H input pin value register 0x00 0x00 5025 Port H PH DDR Port H data direction register 0x00 0x00 5026 PH CR1 Port H control register 1 0x00 0x00 5027 PH CR2 Port H control register 2 0x00 0x00 5028 PI ODR Port data output latch
35. 1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 45 EMS data Symbol Parameter Conditions Level class Voltage limits to be applied on any I O pin to hor gje Ta 25 C VrEsD faster 16 MHz 2B induce a functional disturbance conforming to IEC 61000 4 2 Fast transient voltage burst limits to be Vpp 5 V Ta 25 Verre applied through 100pF
36. 2 Clock controller The clock controller distributes the system clock fuasrer coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safe clock switching Clock sources can be changed safely on the fly in run mode through a configuration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory D Master clock sources Four different clock sources can be used to drive the master clock 1 24 MHz high speed external crystal HSE Upto 24 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected b
37. 2 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details OPT1 UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Pages 0 to 1 defined as UBC memory write protected 0x02 Pages O to 3 defined as UBC memory write protected 0x03 Pages O0 to 4 defined as UBC memory write protected OxFE Pages 0 to 255 defined as UBC memory write protected OxFF Reserved Note Refer to the family reference manual RM0016 section on Flash EEPROM write protection for more details OPT2 AFR7Alternate function remapping option 7 0 Port D4 alternate function TIM2 CH1 1 Port D4 alternate function BEEP AFR6 Alternate function remapping option 6 0 Port B5 alternate function AIN5 port B4 alternate function AIN4 1 Port B5 alternate function I C_SDA port B4 alternate function 12C_SCL AFR5 Alternate function remapping option 5 0 Port B3 alternate function AIN3 port B2 alternate function AIN2 port B1 alternate function AIN1 port BO alternate function AINO 1 Port B3 alternate function TIM1_ETR port B2 alternate function TIM1 CHQ3N port B1 alternate function TIM1 CHAN port BO alternate function TIM1 CHIN AFR4 Alternate function remapping option 4 Reserved A
38. 22171 Rev 5 15 92 Product overview STM8S007C8 4 8 4 9 4 10 4 11 16 92 Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHz LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wakeup counter e Used for auto wakeup from active halt mode e Clock source Internal 128 kHz internal low frequency RC oscillator or external clock e LSI clock can be internally connected to TIM3 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit prescaler e Four independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output e Synchronization module to control the timer with external signals e Break input to force the timer outputs into a defined state e Three comple
39. 87 Part numbering e dee EE NEEN rx LIPAD KARERA Goa AGIT DRA 88 STM8 development tools 89 12 1 Emulation and in circuit debugging tools 89 DoclD022171 Rev 5 3 92 Contents STM8S007C8 12 2 Software 00G aaa data aaa DI KAG Rod pan aos kake decedit ko Roin qd 90 122 11 SIM 1oolset Las ssec ad eam RR xe eS RR RR on 90 12 2 2 Candassembly toolchains 90 12 3 Programming tools tere eoe sre doe nce Pew ad be vea EE 90 13 Revision history aaa xad su kun dos aO AL eta E ACER UR C re 91 4 92 d DoclD022171 Rev 5 STM8S007C8 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Ly STM8S007C8 value line features 9 Peripheral clock gating bit assignments in CLK PCKENR1 2 registers 14 TIM timer features 2 el nn 17 Legend abbreviations for STM8S007C8 pin description table
40. 9 Vpp 5 V high sink ports VDD VoH V loH mA MS19408V3 d 68 92 DoclD022171 Rev 5 STM8S007C8 Electrical characteristics Figure 28 Typ Vpp Von Vpp 3 3 V high sink ports VDD VOH V loH mA MS19409V2 d DoclD022171 Rev 5 69 92 Electrical characteristics STM8S007C8 9 3 7 Reset pin characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 39 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit Viwnrst NRST input low level voltage 1 0 3 V 0 3 x Vpp Vuen NRST input high level voltage 1 0 7 x Vpp Vpp 0 3 V Vounrsrt NRST output low level voltage 1 loL 2 mA 0 5 Reuwrst NRST pull up resistor 2 30 55 80 kQ tep rst NRST input filtered pulse 9 75 ns tinFpinRsT NRST Input not filtered pulse 500 A ns toewasr NRST output pulse 1 15 us 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production 70 92 Figure 29 Typical NRST Vj and Vu vs Vpp 3 temperatures ViL ViH V DoclD022171 Rev 5 MS19410V3 d STM8S007C8 Electrical characteristics Figure 30 Typical NRST pull up resistance vs Vpp 3 temperatures NR
41. ESET pull up resistance kohm MS19411V3 Figure 31 Typical NRST pull up current vs Vpp 3 temperatures NREST pull up current uA Von V ai15069c The reset network shown in Figure 32 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vj max level specified in Table 35 Otherwise the reset is not taken into account internally For power consumption sensitive applications the capacity of the external reset capacitor can be reduced to limit charge discharge current If the NRST signal is used to reset the external circuitry care must be taken of the charge discharge time of the external capacitor to fulfill the external device s reset timing conditions The minimum recommended capacity is 10 nF d DoclD022171 Rev 5 71 92 Electrical characteristics STM8S007C8 Figure 32 Recommended reset pin protection Vpp STM8 Rpy External NRST Internal reset reset Filter circuit ZZ 04gF optional 9 3 8 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 40 are derived from tests performed under ambient temperature fyaster frequency and Vpp supply voltage conditions tMASTER 1 fMASTER Refer to I O port characteristics for more details on the input output alternate function characteristics
42. FR3 Alternate function remapping option 3 0 Port DO alternate function TIM3 CH2 1 Port DO alternate function TIM1 BKIN AFR2 Alternate function remapping option 2 0 Port DO alternate function TIM3 CH2 1 Port DO alternate function CLK CCO Note AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0 Port A3 alternate function TIM2 CH3 port D2 alternate function TIM3 CH1 1 Port A3 alternate function TIM3 CH1 port D2 alternate function TIM2 CH3 AFRO Alternate function remapping option 0 0 Port D3 alternate function TIM2_CH2 1 Port D3 alternate function ADC_ETR d DoclD022171 Rev 5 39 92 Option bytes STM8S007C8 Table 12 Option byte description continued Option byte no OPT3 Description LSI EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active OPT4 EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock sign
43. PE7 AIN8 VOI X X X O1 X X Port E7 Analog input 8 24 PE6 AIN9 VOIX X X O1 X X Port E6 Analog input 9 SPI 25 PE5 SPI NSS lO X X x O1 X X Port E5 master slave select 26 PC1 TIM1 CH1 vol X x X HS O3 X X Port c1 Timer 1 channel 1 27 PC2 TIM1 cH2 vol X X X HSO3 X X Port c2 mer 1 channel 2 28 PC3 TIM1 CH3 vol X x X Hs o3 X X Port ca Timer 1 channel 3 29 PCA TIMi cHa vol x X X HS 03 X X Port ca mer 1 channel 4 30 PC5 SPI SCK VO X X X HS OS X X Port C5 SPI clock 31 Vssio 2 S I O ground 32 Vppio 2 S I O power supply Ky DocID022171 Rev 5 23 92 Pinouts and pin descriptions STM8S007C8 24 92 Table 5 STM8S007C8 pin description continued Input Output c 5 ge Alternate 2 KH E S x 20 ee function 3 Pin name Ec E E v 3r alternate F s a 9 gjalla T5 function after remap 5 5 amp oja a5 option bit LL SPI master 33 PC6 SPI MOSI O X x X HS 03 X X Port C6 lout slave in SPI master in 34 PC7 SPL MISO O X x X HS 03 X X Port C7 slave out 35 PGO VO x X O1 X Port GO 36 PG1 O X O1 X Port G1 37 PE3 TIM1 BKIN VO x x x Of X X Port e3 mer 1 break input 38 PE2 2C SDA O X X O1 T Port E2 2C data 39 PE1 2C SCL O X X O1 T Port E1 I2C clock 40 PEO CLK cco O X x X HS 031 X X Port Eo GConfigurable c
44. S auto reload register high OxFF 0x00 532C TIM3 ARRL TIMS auto reload register low OxFF 0x00 532D TIG TIM3 CCR1H TIMS capture compare register 1 high 0x00 0x00 532bE TIM3 CCR1L TIMS capture compare register 1 low 0x00 0x00 532F TIM3 CCR2H TIMS capture compare register 2 high 0x00 0x00 5330 TIM3 CCR2L TIM3 capture compare register 2 low 0x00 E Reserved area 15 bytes 0x00 5340 TIM4 CR1 TIM4 control register 1 0x00 0x00 5341 TIM4 IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4 SR TIM4 status register 0x00 0x00 5343 TIM4 TIM4 EGR TIM4 event generation register 0x00 0x00 5344 TIM4 CNTR TIM4 counter 0x00 0x00 5345 TIM4 PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4 ARR TIM4 auto reload register OxFF LUE Reserved area 185 bytes 0x00 5400 ADC CSR ADC control status register 0x00 0x00 5401 ADC CR1 ADC configuration register 1 0x00 0x00 5402 ADC CR2 ADC configuration register 2 0x00 0x00 5403 DES ADC CR3 ADC configuration register 3 0x00 0x00 5404 ADC DRH ADC data register high OxXX 0x00 5405 ADC DRL ADC data register low OxXX 0x00 5406 ADC TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 ADC TDRL ADC Schmitt trigger disable register low 0x00 pa gea Reserved area 1016 bytes 1 Depends on the previous reset source 2 Write only register d 34 92 DoclD022171 Rev 5 STM8S007C8 Memory and register map Table 9 CPU SWIM debug module interrupt controller registers
45. SI RC osc 16 MHz 1 0 oe ro Pen HSI RC osc 16 MHz 8 2 0 55 fopu faster 128 kHz LSI RC osc 128 kHz 0 5 3 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Table 21 Total current consumption in wait mode at Vpp z 3 3 V Symbol Parameter Conditions Typ Max Unit Mie HSE crystal osc 24 MHz 2 0 HSE user ext clock 24 MHz 1 8 4 7 HSE crystal osc 16 MHz 1 6 Sibol fcpu fuasrER 16 MHz HSE user ext clock 16 MHz 1 4 4 4 lppqwel current in HSI RC osc 16 MHz 12 16 mA wait mode fopy fyaster 128 125 kHz HSI RC osc 16 MHz 1 0 E MASTER Ipa HSI RC osc 16 MHz 8 2 0 55 pe METER 1285 LSI RC osc 128 kHz 0 5 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Ky DoclD022171 Rev 5 51 92 Electrical characteristics STM8S007C8 Total current consumption in active halt mode Table 22 Total current consumption in active halt mode at Vpp 5 V Ta 40 to 85 C Conditions Symbol Parameter Main voltage Typ Max Unit regulator Flash model Clock source MVR 2 HSE crystal oscillator 16 MHz 1008 Operating mode Rec j oscillator 128 kHz 200 Ca HSE ill Supply current in crystal oscillator 949 IDD H active halt mode 16 MHz pa Power down mode LSI RC oscillator 140
46. UART1 5 gt 8 3 Up to 4 CAPCOM E 16 bit advanced control cS ir UART3 gt timer TIM1 3 complementary outputs ADC2 lt gt GE 16 bit general purpose Ko Up to timers TIM2 TIM3 em 5 CAPCOM channels Beeper lt gt 8 bit basic timer TIM4 AWU timer DoclD022171 Rev 5 d STM8S007C8 Product overview 4 4 1 I Product overview The following section intends to give an overview of the basic features of the STM8S007C8 value line functional modules and peripherals For more detailed information please refer to the corresponding family reference manual RM0016 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance It contains six internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture e 3 stage pipeline e 32 bit wide program memory bus single cycle fetching for most instructions e XandY 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations e 8 bit accumulator e 24 bit program counter 16 Mbyte linear memory space e 16 bit stack pointer access to a 64 K level stack e 8 bit condition code register 7 condition flags for the result of the last instruction Addres
47. ader manual for more details d DoclD022171 Rev 5 41 92 Electrical characteristics STM8S007C8 9 9 1 42 92 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Ves Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at Ta 25 C and Ta Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 X Typical values Unless otherwise specified typical data are based on Ta 25 C Vpp 5 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2 2 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Typical current consumption
48. al on OSCIN CKAWUSEL Auto wakeup unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler 00 24 MHz to 128 kHz prescaler 01 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler OPT5 HSECNT 7 0 HSE crystal oscillator stabilization time This configures the stabilization time 0x00 2048 HSE cycles OxB4 128 HSE cycles OxD2 8 HSE cycles OxE1 0 5 HSE cycles OPT6 Reserved OPT7 WAITSTATE Wait state configuration This option configures the number of wait states inserted when reading from the Flash data EEPROM memory 1 wait state is required if fopy gt 16 MHz 0 No wait state 1 1 wait state 40 92 d DoclD022171 Rev 5 STM8S007C8 Option bytes Table 12 Option byte description continued Option byte no OPTBL Description BL 7 0 Bootloader option byte For STM8S products this option is checked by the boot ROM code after reset Depending on the content of addresses 0x487E 0x487F and 0x8000 reset vector the CPU jumps to the bootloader or to the reset vector Refer to the UM0560 STM8L S bootloader manual for more details For STM8L products the bootloader option bytes are on addresses OxXXXX and OxXXXX 1 2 bytes These option bytes control whether the bootloader is active or not For more details refer to the UM0560 STM8L S bootlo
49. ameter Conditions Typ Max Unit Ipp R Supply current in reset state me E mA Vpp 3 3 V 0 8 eee ee release to bootloader vector 150 US 1 Data guaranteed by design not tested in production Current consumption of on chip peripherals Subject to general operating conditions for Vpp and Ta HSI internal RC fcpy fuAsrER 16 MHz Table 28 Peripheral current consumption Symbol Parameter Typ Unit Ippcrim1 TIM1 supply current 1 220 Ippcrimz TIM2 supply current 1 120 IDD TIM3 TIM3 timer supply current 1 100 IDD TIM4 TIM4 timer supply current 1 25 Ipp uanri UART1 supply current 90 uA IDD UART3 UART3 supply current 110 IDD SPI SPI supply current 40 Ipp i2c I G supply current 2 50 Ipp ADC2 ADC2 supply current when converting 9 1000 1 Data based on a differential Ipp measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no UO pads toggling Not tested in production 2 Data based on a differential Ipp measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production 3 Data based on a differential Ipp measurement between reset configuration and continuous A D conversions Not tested in production 54 92 DoclD022171 Rev 5 d STM8S007C8 Electrical characteristics Current consumption curves F
50. ansition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 38 Typical application with ADC Von STM8 R v qe SINE 10 bit A D AIN conversion TI Capc d DoclD022171 Rev 5 79 92 Electrical characteristics STM8S007C8 9 3 11 80 92 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN
51. by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 A free version that outputs up to 32 Kbytes of code is available STM8 toolset STMB8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com This package includes ST Visual Develop Full featured integrated development environment from ST featuring e Seamless integration of C and ASM toolsets e Full featured debugger e Project management e Syntax highlighting editor e Integrated programming interface e Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer STVP Easy to use unlimited graphical interface allowing read write and verify the user STM8 microcontroller Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of user application directly from an easy to use graphical interface Available toolchains include e Cosmic C compiler for STM8 One free version
52. cation execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers STice key features e Occurrence and time profiling and code coverage new features e Advanced breakpoints with up to 4 levels of conditions e Data breakpoints e Program and data trace recording up to 128 KB records e HRead write on the fly of memory during emulation e In circuit debugging programming via SWIM protocol e 8 bit probe analyzer e 1 input and 2 output triggers e Power supply follower managing application voltages between 1 62 to 5 5 V e Modularity that allows users to specify the components users need to meet their development requirements and adapt to future requirements e Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 DoclD022171 Rev 5 89 92 STM8 development tools STM8S007C8 12 2 12 2 1 12 2 2 12 3 90 92 Software tools STM8 development tools are supported
53. ch case Table 6 Flash Data EEPROM and RAM boundary addresses Memory area Size bytes Start address End address Flash program memory 64K 0x00 8000 0x01 7FFF RAM 6K 0x00 0000 0x00 17FF Data EEPROM 128 0x00 4000 0x00 407F Register map Table 7 I O port hardware register map Address Block Register label Register name kaaa 0x00 5000 PA ODR Port A data output latch register 0x00 0x00 5001 PA IDR Port A input pin value register 0x00 0x00 5002 Port A PA DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control register 1 0x00 0x00 5004 PA CR2 Port A control register 2 0x00 0x00 5005 PB ODR Port B data output latch register 0x00 0x00 5006 PB IDR Port B input pin value register 0x00 0x00 5007 Port B PB DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PB IDR Port C input pin value register 0x00 0x00 500C Port C PC DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD IDR Port D input pin value register 0x00 0x00 5011 Port D PD DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register
54. control Resonator g STM8 OSCOUT HSE oscillator critical gm formula Omerit 2x IT x fyse x Rn 2C0 0 Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification C Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 42C p C Grounded external capacitance Om gt gt Omerit Ly DoclD022171 Rev 5 57 92 Electrical characteristics STM8S007C8 9 3 4 Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and Ta fuse High speed internal RC oscillator HSI Table 31 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fug Frequency 16 MHz Trimmed by the CLK HSITRIMR register for given Vpp and Ta ACC conditions Vpp 5 V Ta 25 C 5 Accuracy of HSI oscillator 1 00 1 0 Accuracy of HSI oscillator factory calibrated Vpp 5 V B S 40 C lt Tas 85 C 9 gt t HSI oscillator wakeup i 1 00 su HS time including calibration j HSI oscillator power 170 2502 uA l DD HSI consumption 1 Guaranteed by design not tested in production 2 Data based on characterization results not tested in production Figure 14 Typical HSI frequency variation vs Vpp at 3 temperatures
55. control timer 16 4 11 TIM2 TIMG 16 bit general purpose timers 16 4 12 TIMA 8 bit basic timer css osse eR RR RR xs 17 4 13 Analog to digital converter ADC2 17 4 14 Communication interfaces 17 4441 VARIT 52 oe ARE kel pak eee KA Roe Ue eeu Re SN ad 18 434 2 UARTS ise oe cce aeter KET a RR e owes i 18 4143 SPM assassins e ut i hm e e aa we gere eb e d e 19 WAS op ANAK oe apa a 20 5 Pinouts and pin descriptions 21 5 1 Alternate function remapping 25 6 Memory and register map 26 6 1 Memory MAP sexes timana aT baec acrem bee genes era vibe KG 26 6 2 Register Map orsi pd Re RUSO rpm p dc GEN RD a ER RON qus 27 2 92 DocID022171 Rev 5 Ly STM8S007C8 Contents 10 11 12 I Interrupt vector mapping 37 Option bytes 25 su dusasmenmsasateesesenesaasspestasses 38 Electrical characteristics 2eusma x ma aise nomme se EEN 42 9 1 Parameter conditions 42 9 1 1 Minimum and maximum values 42 9 1 2 Typical values 42 9 1 3 Typical CUVGS oigo yog e Reda aed baade NEEN edd dad 42 9 1 4 Typical current consumption 42 9 1 5 Pin loading conditions
56. ed by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode In this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Activation of the watchdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout at 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register DoclD0
57. ent points are made at CMOS levels 0 3 x Vpp and 0 7 x Vpp I DoclD022171 Rev 5 STM8S007C8 Electrical characteristics 9 3 10 10 bit ADC characteristics Subject to general operating conditions for Vppa fmasTER and Ta unless otherwise specified Table 42 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit Vppa 3 to 5 5 V 1 S A fapc ADC clock frequency MHz VDDA 4 5 to 5 5 V 1 6 Vppa Analog supply 3 5 5 V Vor Positive reference voltage 2750 VppA V VREr Negative reference voltage Vssa z 0 50 V i Vssa Vopa V Van k tteielouigizgeeper Canc capacitor 2 pF fApc 4 MHz 0 75 te Sampling time us fADC 6 MHz 0 5 tstag Wakeup time from standby 5 7 us fapc 4 MHz 3 5 us Total conversion time including T Iconv sampling time 10 bit resolution fanc 6 MHz se Se 14 l fApc 1 Data guaranteed by design not tested in production 2 During the sample time the input capacitance Cam 8 pF max can be charged discharged by the external Source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock tg depend on programming d DoclD022171 Rev 5 77 92 Electrical characteristics STM8S007C8
58. environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 10 1 LQFP48 package information Figure 39 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline SEATING PLANE RE re GAUGE PLANE y K 5B_ME_V2 1 Drawing is not to scale Ly DoclD022171 Rev 5 83 92 Package information STM8S007C8 84 92 Table 49 LQFP48 48 pin 7 x 7 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 gt E 0 0630 A1 0 050 S 0 150 0 0020 3 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 S 0 2165 S E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 s 5 500 S 0 2165 x e i 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 S S 0 0394 k 0 3 5 7 0 3 5 7 CCC S 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits DoclD022171 Rev 5 Ky STM8S007C8 Package informat
59. er capable High precision baud rate generator d DoclD022171 Rev 5 STM8S007C8 Product overview 4 14 3 d Asynchronous communication UART mode Full duplex communication NRZ standard format mark space Programmable transmit and receive baud rates up to 1 Mbit s fopy 16 and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes A Address bit MSB dle line interrupt Transmission error detection with interrupt generation Parity control LIN master capability Emission Generates 13 bit synch break frame Reception Detects 11 bit break frame LIN slave mode Autonomous header handling one single interrupt per valid message header Automatic baud rate synchronization maximum tolerated initial clock deviation 15 96 Synch delimiter checking 11 bit LIN synch break detection break detection always active Parity check on the LIN identifier field LIN error management Hot plugging support Maximum speed 10 Mbit s fnaster 2 both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave master selection input pin DoclD022171 Rev 5 19 92 Product overview STM8S007C8 4 14 4 20 92 PC PC
60. eve max fast CC speed 400kHz Data based on standard DC protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time Standard mode IZC Fast mode 12C 1 Symbol Parameter Unit Min Max Min Max tw SCLL SCL clock low time 4 7 1 3 ig tw SCLH SCL clock high time 4 0 S 0 6 x tsu sDA SDA setup time 250 100 thspa SDA data hold time o9 o9 9008 hispa SDA and SCL rise time 3 1000 300 ns t SCL tsoa SDA and SCL fall time 300 300 tyscr th sta START condition hold time 4 0 0 6 S us tsu sTA Repeated START condition setup time 4 7 0 6 tsu sTo STOP condition setup time 4 0 0 6 US STOP to START condition time 47 13 lw STO STA bus free j i us Cp Capacitive load for each bus line 400 400 pF 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL DoclD022171 Rev 5 75 92 STM8S007C8 Electrical characteristics 76 92 Figure 36 Typical application with I C bus and timing diagram VDD VDD PC bus I START Dee e EN I I H SDA gt re SDA 9 hels sSDA 77777 IZ i i i STOP 1 47 tsu STA STO I 1 l Li pr th STA 4 tw SCEL th SDA 1 il 1 1 tw SCLH T SCL zua te sc pl tsu STO ai17490V2 1 Measurem
61. f ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved 92 92 DoclD022171 Rev 5 d Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information STMicroelectronics STM8S007C8T6
62. fter wakeup Table 25 Total current consumption in halt mode at Vpp 3 3 V Symbol Parameter Conditions Typ Unit Flash in operating mode HSI clock after 615 I Suppl in hal d nm A DD H upply current in halt mode H m Flash in power down mode HSI clock after 45 wakeup Low power mode wakeup times Table 26 Wakeup times Symbol Parameter Conditions Typ Max Unit 2 t Wakeup time from wait A WU WFI 3 UWF mode to run mode Te faster 16 MHz 0 56 ash o operating 4 2 6 MVR voltage Mode D 1 regulator on Flashin power down 36 5 i Wakeup time active halt mode HSI after ig WU AH mode to run mode 9 Flash in operating Wakeup 180 5 z MVR voltage mode 4 regulator off Flash in power down 6 5 50 mode Wakeup time from halt Flash in operating mode 52 3 WU mode to run mode Flash in power down mode 54 1 Data guaranteed by design not tested in production 2 twu wrn 2 X 1fmaster 7 X 1 fcpu 3 Measured from interrupt event to interrupt vector fetch 4 Configured by the REGAH bit in the CLK_ICKR register 5 Configured by the AHALT bit in the FLASH CR1 register 6 Plus 1 LSI clock depending on synchronization Ly DocID022171 Rev 5 53 92 Electrical characteristics STM8S007C8 Total current consumption and timing in forced reset state Table 27 Total current consumption and timing in forced reset state Symbol Par
63. grees Celsius may be calculated using the following equation Tymax Tamax PDmax X Oga Where e TAmax is the maximum ambient temperature in C e jpis the package junction to ambient thermal resistance in C W e Ppmax is the sum of Pintmax and Pi Omax PDmax Pintmax Pl Omax e Pintmax is the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power e Pyomax represents the maximum power dissipation on output pins where PyOmax No lol Z Vpp VoH oul and taking account of the actual Vo lo and Voylog of the I Os at low and high level in the application Table 50 Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient LQFP 48 7 x 7 mm Thor resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org d DoclD022171 Rev 5 STM8S007C8 Package information 10 2 2 I Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Figure 42 STM8S007C8 value line ordering information scheme 1 The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions Maximum ambient te
64. ied temperature range and ACCHs values in Table 31 HSI oscillator characteristics on page 58 ACCHs parameter Modified Figure 35 SPI timing diagram master mode 1 on page 74 SCK output instead of SCK input 10 Mar 2015 Updated the disclaimer Added Figure 41 LQFP48 marking example package top view 25 Mar 2015 Updated Figure 27 Typ VDD VOH VDD 5 V high sink ports Figure 29 Typical NRST VIL and VIH vs VDD 9 3 temperatures Figure 30 Typical NRST pull up resistance vs VDD 3 temperatures Added a note to Power on reset threshold parameter in Table 17 Operating conditions at power up power down DoclD022171 Rev 5 91 92 STM8S007C8 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale o
65. igure 10 and Figure 11 show typical current consumption measured with code executing in RAM Figure 10 Typ Ipp nuw VS Vpp HSI RC osc fcpy 16 MHz Ipp RUN HSI mA ai18796V2 IDD WFI HS1 mA Vb V ai18797V2 d DoclD022171 Rev 5 55 92 Electrical characteristics STM8S007C8 9 3 3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for Vpp and Ta Table 29 HSE user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit ee ead ian clock source 0 24 MHz Vise SEH EEGEN 7xVpp gt NVpp 08v Vase CO SS input pin low level Ves 0 3 x Vpp ILEAK HSE Mn pU ea age Vss lt Vin lt Vpp i E 1 uA 1 Data based on characterization results not tested in production Figure 12 HSE external clock source Vueent 4 D gt fuse External clock source OSCIN mI H STM8 HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 24 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and sta
66. ion d Figure 40 LQFP48 48 pin 7 x 7 mm low profile quad flat recommended footprint 0 50 1 20 36 25 0 30 p Ls PE oo co o Y o c3 EI al 020 EI co 7 7 5 80 i C ci o o o CU 288 CC co est Yas 13 E 3 1 V 12 III 1 20 ut 5 80 _ _ gt A 9 70 y ai14911d 1 Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 41 LQFP48 marking example package top view Product identification S T M S 0 0 d Standard ST logo Revision code Pin 1 identifier MS37489V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity DoclD022171 Rev 5 85 92 Package information STM8S007C8 10 2 10 2 1 86 92 Thermal characteristics The maximum chip junction temperature T max must never exceed the values given in Table 16 General operating conditions The maximum chip junction temperature T jmax in de
67. lock output TIM1 BKIN Timer 3 AFR3 41 PDO TIM3_CH2 VO X X X HS O3 X X Port DO isen 2 CLK CCO AFR2 42 PD1 SWIM vol x x x HS 041 X X Port p1 WIM data interface Timer 3 TIM2 CH3 43 PD2 TIM3_CH1 I O X X X HS O3 X X Port D2 annal IWERT Timer 2 ADC ETR 44 PD3 TIM2_CH2 I O X X X HS O8 X X Port D3 TE A AFRO PD4 TIM2_CH1 B Timer 2 BEEP output 45 CE VO X X X Hs 03 x X Port D4 P AFR 46 PD5 UART3 TX VO X X X O1 X X Port ps VARTS data transmit PD6 UART3 data 47 luanta gx YO X X X O1 X X Port D6 5 48 PD7 TLI VOIX X x 01 x X Port D7 Op level interrupt The default state of UART1 RX and UART3 RX pins is controlled by the ROM bootloader These pins are pulled up as part of the bootloader activation process and returned to the floating state before a return from the bootloader In the open drain output column T defines a true open drain UO P buffer weak pull up and protection diode to Vpp are not implemented The PD1 pin is in input pull up during the reset phase and after the internal reset release DoclD022171 Rev 5 d STM8S007C8 Pinouts and pin descriptions Note The slope control of true open drain pins cannot be programmed and by default is limited to 2 MHz 5 1 Alternate function remapping As shown in the rightmost column of the pin description table some al
68. ls Full documentation is offered with a wide choice of development tools Product longevity is ensured in the STM8S family thanks to their advanced core which is made in a state of the art technology for applications with 2 95 V to 5 5 V operating supply Table 1 STM8S007C8 value line features Features STM8S007C8 Pin count 48 Max number of GPIOs I O 38 External interrupt pins 35 Timer CAPCOM channels 9 Timer complementary outputs 3 A D converter channels 10 High sink I Os 16 High density Flash program memory 64 Kbytes Data EEPROM 128 bytes RAM 6 Kbytes DoclD022171 Rev 5 9 92 Block diagram STM8S007C8 3 10 92 Block diagram Figure 1 STM8S007C8 value line block diagram Single wire debug interf 400 Kbit s E 10 Mbit s ds LIN master SPI emul AE ARS UE Master slave autosynchro 16 channels 1 2 4 kHz beep um Reset block XTAL 1 24 MHz lt gt Clock controller Reset RC int 16 MHz Detector POR BOR RC int 128 kHz Clock to peripherals and core Window WDG STMB core 2 gt lt gt Independent WDG Debug SWIM on 64 Kbytes high density program Flash 2 Ke gt de 128 bytes data EEPROM e a 2 SPI 5 gt E lt gt 6 Kbytes RAM 5 o E o lt gt Boot ROM
69. mentary outputs with adjustable dead time e Encoder mode e interrupt sources 3 x input capture output compare 1 x overflow update 1 x break TIM2 TIM3 16 bit general purpose timers e 16 bit autoreload AR up counter e 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 e Timers with 3 or 2 individually configurable capture compare channels e PWM mode e Interrupt sources 2 or 3 x input capture output compare 1 x overflow update I DoclD022171 Rev 5 STM8S007C8 Product overview 4 12 TIM4 8 bit basic timer e 8 bit autoreload adjustable prescaler ratio to any power of 2 from 1 to 128 e Clock source CPU clock e Interrupt source 1 x overflow update Table 3 TIM timer features Counter Timer Counting CAPCOM Complem Ext synchr Timer size Prescaler e ne bits mode channels outputs trigger onization chaining TIM1 16 Any integer from 1 to 65536 Up down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No T o TIM3 16 Any power of 2 from 1 to 32768 Up 2 0 No TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No 4 13 Analog to digital converter ADC2 STM8S007C8 value line products contain a 10 bit successive approximation A D converter ADC2 with up to 10 multiplexed input channels and the following main features e Input voltage range 0 to VppA e Conversion time 14 clock cycles e Single and continuous modes e External trigger input e
70. mm Communications interfaces UART with clock output for synchronous operation LIN master mode UART with LIN 2 1 compliant master slave modes and automatic resynchronization SPI interface up to 10 Mbit s I2C interface up to 400 Kbit s 10 bit ADC with up to 16 channels Os 38 I Os including 16 high sink outputs Highly robust I O design immune against current injection Development support Single wire interface module SWIM and debug module DM March 2015 DoclD022171 Rev 5 1 92 This is information on a product in full production www SL Com Contents STM8S007C8 Contents 1 idee e Pre Do Mcr 8 2 Description c aci ica EE dala aci ww ew Re RE ca Aa ng De dr a ee 9 3 Block diagram e EINEN umm AKA c aw n oC KR B e RR Rn a 10 4 Product overview sansene teca aon Qr on OR AA RC QI DN CE sd 11 4 1 Central processing unit STM8 11 4 2 Single wire interface module SWIM and debug module DM 12 4 3 Meru COMEDIE ases sle rade due rego ee Rd Ii NG AT bee 12 4 4 Flash program and data EEPROM memory 12 4 5 Clock controller ue tabs edax ERR PONE pr PP DAE EE Rn 14 4 6 Power management 15 4 7 Watchdog timers esses sx Ree ERA EG GERE RR EE ehre A 15 48 Auto wakeup counter 16 4 9 BEEDET Lie is MAn B Nes mr Roe Sek Meee Beebe Nee ee 16 4 10 TIM1 16 bit advanced
71. mperature Tamax 82 C measured according to JESD51 2 IpDmax 15 mA Vpp 5 5V Maximum eight standard I Os used at the same time in output at low level with lo 10 mA Vo 22V Maximum four high sink I Os used at the same time in output at low level with lo 20 mA Vo 1 5 V Maximum two true open drain I Os used at the same time in output at low level with lot 20 mA Vos 2V PiNTmax 15 MA x 5 5 V 82 5 mW Piomax 10 MA x 2 V x8 20 mA x 2 V x2 20 mA x 1 5 V x 4 360 mW This gives Pintmax 82 5 mW and Pjomax 360 mW Ppmax 82 5 mW 360 mW Thus Ppmax 443 mW Using the values obtained in Table 50 Thermal characteristics on page 86 T jmax is calculated as follows for LQFP64 10 x 10 mm 46 C W TJmax 82 C 46 C W x 443 mW 82 C 20 C 102 C This is within the range of the suffix 6 version parts 40 lt Tj lt 105 C In this case parts must be ordered at least with the temperature range suffix 6 DoclD022171 Rev 5 87 92 Part numbering STM8S007C8 11 88 92 Part numbering Figure 42 STM8S007C8 value line ordering information scheme Example Product class STM8 STM8 microcontroller Family type s S standard Sub family type 007 C 007 peripheral set Pin count C 48 pins Program memory size 8 8 64 Kbytes Package type 1 T LQFP Temperature range 6 6 40 C to 85
72. mum current injection on four I O port pins of the device Table 15 Thermal characteristics I Symbol Ratings Value Unit TsTG Storage temperature range 65 to 150 iB Tj Maximum junction temperature 150 DoclD022171 Rev 5 45 92 Electrical characteristics STM8S007C8 9 3 Operating conditions The device must be used in operating conditions that respect the parameters in Table 16 In addition full account must be taken of all physical capacitor characteristics and tolerances Table 16 General operating conditions Symbol Parameter Conditions Min Max Unit 0 24 fopu Internal CPU clock frequency MHz Vpp Vpp 10 Standard operating voltage 2 95 5 5 V Cgxr capacitance of external 470 3300 nF capacitor 1 Voap ESR of external capacitor i 0 3 ohm At 1 MHz ESL of external capacitor 15 nH 48 pin devices with output 3 Power dissipation at on eight standard ports two i Po Ta 85 C for suffix 6 high sink ports and two open aa iid drain ports simultaneously TA a E SES Maximum power dissipation 40 85 i Tj Junction temperature range 40 105 1 Care should be taken when selecting the capacitor due to its tolerance as well as the parameter dependency on temperature DC bias and frequency in addition to other factors The parameter specifications must be respected for the full application range This frequency of 1 MHz as a condition for
73. n the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 11 Option bytes i Option bits Factory Option Option Addr KHAN B E wak default Meu c7 6 5 4 3 2 1 0 setting Read out 4800h protection OPTO ROP 7 0 00h ROP 4801h User boot code OPT UBC 7 0 00h 4802n UBC NOPT1 NUBC 7 0 FFh 4803h ang OPT2 AFR7 AFR6 AFR5 BS AFR3 AFR2 AER AFRO 00h remapping 4804h AFR NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO FFh LSI IWDG WWDG WWDG 4805h OPT3 Reserved 00h Watchdog EN HW HW HALT option NLSI NIWDG NWWDG NWWDG 4806h NOPT3 Reserved EN HW HW HALT FFh EXT CKAWU PRS PRS 4807h OPT4 Reserved CLK SEL C1 CO 00h Clock option NEXT NCKAW NPR NPR 4808h NOPT4 Reserved CLK USEL SC1 SCO FFh 4809h HSE clock OPT5 HSECNT 7 0 00h 480Ah Startup NOPT5 NHSECNT 7 0 FFh 480Bh OPT6 Reserved 00h L Reserved 480Ch NOPT6 Reserved FFh 480Dh OPT7 Reserved SE 00h Flash wait state states 480Eh NOPT7 Reserved kaa FFh 487Eh OPTBL BL 7 0 00h Bootloader 487Fh NOPTBL NBL 7 0 FFh 38 92 DoclD022171 Rev 5 KYI STM8S007C8 Option bytes Table 1
74. ock 16 MHz 1 2 4 1 execute fopu fmastep 128 125 kHz from RAM HSI RC osc 16 MHz 1 0 1 3 fopu fmasTER 128 15 625 kHz HSI RC osc 16MHz 8 0 55 fopu fMASTER 128 kHz LSI RC osc 128 kHz 0 45 IDD RUN mA e T HSE crystal osc 24 MHz 11 0 fopu fuasTER Z SEE S HSE user ext clock 24 MHz 10 8 18 0 HSE crystal osc 16 MHz 8 4 Supply e Trent fcpu fuasrER 16 MHz HSE user ext clock 16 MHz 8 2 15 2 run mode HSI RC osc 16 MHz 8 1 13 2 code executed fopu fMaster 2 MHz HSI RC osc 16 MHz 8 2 1 5 from Flash fepu MASTER 1 28 125 kHz HSI RC osc 16 MHz 1 1 fopu fmasTER 128 i 15 625 kHz HSI RC osc 16 MHz 8 0 6 fopy fMASTER 128 kHz LSI RC osc 128 kHz 0 55 1 Data based on characterization results not tested in production 2 Default clock configuration 50 92 DoclD022171 Rev 5 Ly STM8S007C8 Electrical characteristics Total current consumption in wait mode Table 20 Total current consumption in wait mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 24 MHz 2 4 fopu wem 24 MHz HSE user ext clock 24 MHz 1 8 4 7 HSE crystal osc 16 MHz 2 0 Supply fcpu faster 16 MHz HSE user ext clock 16 MHz 1 4 4 4 IDowen current in HSI RC osc 16 MHz 12 16 mA wait mode fcpu fmasrer 128 125 kHz H
75. on Vpp and Vss pins fmaster 16 MHz 4A to induce a functional disturbance conforming to IEC 61000 4 4 I DoclD022171 Rev 5 STM8S007C8 Electrical characteristics Electromagnetic interference EMI Emission tests conform to the SAE IEC 61967 2 standard for test software board layout and pin loading Table 46 EMI data Conditions 1 Symbol Parameter Monitored Max fhse fcpu Unit General conditions frequeney band 16MHz 16 MHz 24 MHz 8 MHz 16 MHz 24 MHz 0 1MHz to 30 MHz 14 13 24 Vop 5V Peak level 25 C 30 MHz to 130 MHz 19 23 17 dBuV Semi LQFP48 package 130 MHz to 1 GHz 4 4 7 conforming to SAE IEC Se EMI 61967 2 SAE EMI level 1 5 2 2 5 1 Data based on characterization results not tested in production Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges 3 positive then 3 negative pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin This test conforms to the JESD22 A114A A115A standard For more details
76. or Stabilization for the main regulator is achieved connecting an external capacitor Cer to the Vcap pin CExr is specified in Table 16 Care should be taken to limit the series inductance to less than 15 nH Figure 9 External capacitor CExT ESR C ESL SE Sos T Rleak 1 Legend ESR is the equivalent series resistance and ESL is the equivalent inductance Supply current characteristics The current consumption is measured as described in Figure 5 on page 42 Total current consumption in run mode The MCU is placed under the following conditions e All UO pins in input mode with a static value at Vpp or Vss no load e All peripherals are disabled clock stopped by Peripheral Clock Gating registers except if explicitly mentioned e When the MCU is clocked at 24 MHz Ta x 85 C and the WAITSTATE option bit is set Subject to general operating conditions for Vpp and Ta d DoclD022171 Rev 5 STM8S007C8 Electrical characteristics Table 18 Total current consumption with code execution in run mode at Vpp 5 V Symbol IDD RUN 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off d Parameter Conditions Typ Max uM HSE crystal osc 24 MHz 4 4 PU IMASTER Z SS S HSE user ext clock 24 MHz 3 7 7 30 HSE crystal osc 16 MHz 3 3
77. or CExT I an ken 48 Typ IDD RUN VS Vpp HSI RC OSC fepu 216 MHZ senka mr xy Rs 55 Typ IDD WFI VS Vpp HSI RC OSC fepu s16 MHZ sis ass data audi 55 HSE external clock source 56 HSE oscillator circuit diagram 57 Typical HSI frequency variation vs Vpp at 3 temperatures 58 Typical LSI frequency variation vs Vpp 25 C 59 Typical Vu and Vj vs Vpp 3 temperatures 62 Typical pull up resistance vs Vpp 3 temperatures 62 Typical pull up current vs Vpp 3 temperatures 63 Typ No Vpp 5 V standard ports 64 Typ Voi Vpp 3 3 V standard ports 65 Typ Voi Vpp 5 V true open drain ports 65 Typ Vor Vpp 3 3 V true open drain ports 66 Typ No Vpp 5 V high sink ports 66 Typ VoL Vpp 3 3 V high sink parts Nee Louisiane danse sue Rr Rx ya 67 Typ Vpp Vou O Vpp 5 V standard ports 67 Typ Vpp Vou Vpp 3 3 V standard ports 68 Typ Vpp Vou Vpp 5 V high sink ports 68 Typ Vpp V
78. ou Vpp 3 3 V high sink ports 69 Typical NRST Vj and Vip vs Vpp 3 temperatures 70 Typical NRST pull up resistance vs Vpp 3 temperatures 71 Typical NRST pull up current vs Von 9 3 temperatures 71 Recommended reset pin protection 72 SPI timing diagram slave mode and CPHA 0 73 SPI timing diagram slave mode and CPHA VP 73 SPI timing diagram master mode RR EEE EE EGEN 74 Typical application with DC bus and timing diagram 76 ADC accuracy characteristics nes 79 Typical application with ADC IIR 79 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline 83 LQFP48 48 pin 7 x 7 mm low profile quad flat recommended footprint 85 LQFP48 marking example package top view 85 STM8S007C8 value line ordering information schemelt 88 DoclD022171 Rev 5 7 92 Introduction STM8S007C8 8 92 Introduction This datasheet contains the description of the STM8S007C8 value line features pinout electrical characteristics mechanical data and ordering information e For complete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S and STM8A microcontroller families reference
79. rammable through the UBC option byte Table 12 in increments of 1 page 512 bytes by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory 64 Kbytes minus UBC e User specific boot code UBC Configurable up to 64 Kbytes The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the IAP and communication routines Figure 2 Flash memory organisation Data Data memory area up to 2 Kbytes EEPROM 1 memory Option bytes Programmable area from 1 Kbyte UBC area 2 first pages up to 64 Kbytes Remains write protected during IAP 1 page steps 64 Kbytes Flash program memory Program memory area Write access possible for IAP Read out protection ROP The read out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller DoclD022171 Rev 5 13 92 Product overview STM8S007C8 4 5 14 9
80. register 0x00 0x00 5029 PI IDR Port input pin value register 0x00 0x00 502A Port I PI DDR Port data direction register 0x00 0x00 502B PI CR1 Port control register 1 0x00 0x00 502C PI CR2 Port control register 2 0x00 28 92 DoclD022171 Rev 5 d STM8S007C8 Memory and register map Table 8 General hardware register map Address Block Register label Register name ete AG pay Reserved area 10 bytes 0x00 505A FLASH CR1 Flash control register 1 0x00 0x00 505B FLASH CR2 Flash control register 2 0x00 0x00 505C FLASH NCR2 Flash complementary control register 2 OxFF 0x00 505D Flash FLASH FPR Flash protection register 0x00 0x00 505E FLASH NFPR Flash complementary protection register OxFF 0x00 505F FLASH IAPSR Flash DE status 0x00 pce Reserved area 2 bytes 0x00 5062 Flash FLASH PUKR Flash Aa UNDE on 0x00 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH DUKR Data EEPROM unprotection register 0x00 CE Reserved area 59 bytes 0x00 50A0 EXTI CR1 External interrupt control register 1 0x00 0x00 50A1 SS EXTI CR2 External interrupt control register 2 0x00 SEE Reserved area 17 bytes 0x00 50B3 RST RST SR Reset status register Oxxx EE Reserved area 12 bytes 0x00 50C0 CLK ICKR Internal clock control register 0x01 0x00 50C1 SC CLK ECKR External clock con
81. rt up stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy d 56 92 DoclD022171 Rev 5 STM8S007C8 Electrical characteristics Table 30 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit in External high speed oscillator 1 24 MHz frequency Rr Feedback resistor a 5 220 3 kQ Cc Recommended load capacitance S 20 pF C 20 pF i 6 startup fosc 24 MHz 2 stabilized Ipp HsE HSE oscillator power consumption mA C 10 pF 6 startup fosc 24 MHz 1 5 stabilized 9 Om Oscillator transconductance 5 mA V tsuHse Startup time Vpp is stabilized 1 ms 1 Cis approximately equivalent to 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value Refer to crystal manufacturer for more details 3 Data based on characterization results not tested in production tsu usE is the start up time measured from the moment it is enabled by software to a stabilized 24 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 13 HSE oscillator circuit diagram fuse to core gt Oo rr I 3 3 3 Oo ll Oo Ln OSCIN Resonator p Consumption
82. sing e 20 addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set e 80 instructions with 2 byte average instruction size e Standard data movement and logic arithmetic functions e 8 bit by 8 bit multiplication e 16 bit by 8 bit and 16 bit by 16 bit division e Bit manipulation e Data transfer between stack and accumulator push pop with direct stack access e Data transfer using the X and Y registers or direct memory to memory transfers DoclD022171 Rev 5 11 92 Product overview STM8S007C8 4 2 4 3 4 4 12 92 Single wire interface module SWIM and debug module DM The single wire interface module and debug module permits non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R W to RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory
83. stor Table 35 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit Input low level Vit voltage 0 3 0 3 x Vpp V Input high level Voo 5 V S Vin voltage 0 7 x Vpp Vpp 0 3 V V Vhys Hysteresis 700 mV Rou Pull up resistor Vpp 5 V ViN Vss 30 55 80 kQ Fast I Os 5 20 ns tet Rise and fall time Load 50 pF RF 10 90 Standard and high sink I Os 1250 Ha Load 50 pF Input leakage likg current Vss lt VS Vpp 5 1 HA analog and digital Analog input kg ana eos Ge Vss lt VNS Von 250 9 na likg ini SE oo Injection current 4 mA A 10 HA 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 2 Data guaranteed by design not tested in production 3 Data based on characterization results not tested in production d DoclD022171 Rev 5 61 92 Electrical characteristics STM8S007C8 62 92 Figure 16 Typical Vu and Vi vs Vpp 3 temperatures ViL ViH mA 2 5 3 3 5 4 4 5 5 5 5 6 Vb V ai18798V2 Figure 17 Typical pull up resistance vs Vpp 3 temperatures Pull up resisitance kohm 2 5 3 3 5 4 4 5 5 5 5 6 Vo V ai18799V2 DoclD022171 Rev 5 d STM8S007C8 Electrical characteristics Figure 18 Typical pull up current vs Vpp 3 temperatures 140 120 100 Pull up current
84. ternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits Refer to Section 8 Option bytes When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of the family reference manual RM0016 DoclD022171 Rev 5 25 92 I Memory and register map STM8S007C8 6 6 1 26 92 Memory and register map Memory map Figure 4 Memory map 0x00 0000 RAM 6 Kbytes 0x00 17FF 1024 bytes stack 0x00 1800 Reserved 0x00 3FFF 0x00 4000 128 bytes data EEPROM 0x00 407F 0x00 4080 Reserved 0x00 47FF 0x00 4800 Option bytes 0x00 487F 0x00 4900 Reserved 0x00 4FFF 0x00 5000 2 GPIO and peripheral registers 0x00 57FF see Table 8 and Table 9 0x00 5800 Reserved 0x00 5FFF 0x00 6000 2 Kbytes boot ROM 0x00 67FF 0x00 6800 Reserved 0x00 7EFF 0x00 7F00 CPU SWIM debug ITC 0x00 7FFF register see Table 10 0x00 8000 32 interrupt vectors 0x00 807F 0x00 8080 Flash program memory 64 bytes 0x01 7FFF MS19412V2 DocID022171 Rev 5 Ly STM8S007C8 Memory and register map 6 2 I Table 6 lists the boundary addresses for each memory size The top of the stack is at the RAM end address in ea
85. that outputs up to 32 Kbytes of code is available For more information see www cosmic software com e Haisonance C compiler for STM8 One free version that outputs up to 32 Kbytes of code For more information see www raisonance com e STM8 assembler linker Free assembly toolchain included in the STVD toolset which allows users to assemble and link the user application source code Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on user application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming the user STM8 For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STMB8 family DocID022171 Rev 5 Ly STM8S007C8 Revision history 13 I Revision history Table 51 Document revision history Date 31 Oct 2011 Revision 1 Changes Initial release 06 Jan 2012 Table 34 Flash program memory data EEPROM memory updated Vpp condition updated trer parameters Table 39 NRST pin characteristics updated typ and max values of the NRST Pull up resistor 26 Apr 2012 Added the document status on the cover page datasheet production data Modif
86. trol register 0x00 0x00 50C2 Reserved area 1 byte 0x00 50C3 CLK CMSR Clock master status register OxE1 0x00 50C4 CLK SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register OxXX 0x00 50C6 CLK CKDIVR Clock divider register 0x18 0x00 50C7 ed CLK PCKENR1 Peripheral clock gating register 1 OxFF 0x00 50C8 CLK CSSR Clock security system register 0x00 0x00 50C9 CLK CCOR Configurable clock control register 0x00 0x00 50CA CLK PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB Reserved area 1 byte Ky DoclD022171 Rev 5 29 92 Memory and register map STM8S007C8 Table 8 General hardware register map continued Address Block Register label Register name Wee 0x00 50CC CLK HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CD CLK OLK SWIMCCR SWIM clock control register ps s paang Reserved area 3 bytes 0x00 50D1 EE WWDG CR WWDG control register Ox7F 0x00 50D2 WWDG WR WWDR window register Ox7F UNDE Reserved area 13 bytes 0x00 50E0 IWDG_KR IWDG key register OxXX 2 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF A Reserved area 13 bytes 0x00 50F0 AWU_CSR1 AWU control status register 1 0x00 0x00 50F1 AWU AWU APR AWU asynchronous prescaler buffer register Ox3F 0x00 50F2 AWU_TBR AWU timebase selection register 0x00 0x00 5
87. x00 0x00 521D I2C TRISER DC TRISE register 0x02 E Reserved area 18 bytes 0x00 5230 UART1 SR UART1 status register OxCO 0x00 5231 UART1 DR UART1 data register OxXX 0x00 5232 UART1 BRR1 UART1 baud rate register 1 0x00 0x00 5233 UART1 BRR2 UART1 baud rate register 2 0x00 0x00 5234 UART1 CR1 UART1 control register 1 0x00 0x00 5235 UART1 UART1 CR2 UART1 control register 2 0x00 0x00 5236 UART1 CR3 UART1 control register 3 0x00 0x00 5237 UART1 CR4 UART1 control register 4 0x00 0x00 5238 UART1 CR5 UART1 control register 5 0x00 0x00 5239 UART1 GTR UART1 guard time register 0x00 0x00 523A UART1 PSCR UART1 prescaler register 0x00 UE Reserved area 5 bytes 0x00 5240 UART3 SR UARTS status register COh 0x00 5241 UART3 DR UARTS data register OxXX 0x00 5242 UART3 BRR1 UART3 baud rate register 1 0x00 0x00 5243 UART3 BRR2 UARTS baud rate register 2 0x00 0x00 5244 UART3 CR1 UARTS control register 1 0x00 0x00 5245 PSP UART3 CR2 UARTS control register 2 0x00 0x00 5246 UART3 CR3 UARTS control register 3 0x00 0x00 5247 UART3 CR4 UARTS control register 4 0x00 0x00 5248 Reserved 0x00 5249 UART3 CR6 UARTS control register 6 0x00 pedi Reserved area 6 bytes Ky DoclD022171 Rev 5 31 92 Memory and register map STM8S007C8 Table 8 General hardware register map continued
88. ximum ratings ren 81 Electrical sensitivities 82 DoclD022171 Rev 5 5 92 List of tables STM8S007C8 Table 49 LQFP48 48 pin 7 x 7 mm low profile quad flat package mechanical data 84 Table 50 Thermal characteristics 86 Table 51 Document revision history 91 6 92 DocID022171 Rev 5 Lys STM8S007C8 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 I STM8S007C8 value line block diagram 10 Flash memory organisation 13 LQFP 48 pin pinout 21 Memory map EEE EN 26 Supply current measurement conditions 42 Pin loading conditions 0 beeen tenes 43 Pin Input voltage AA 43 Te puma VEISUS VOD sets Latte a ee FUR eee peke BABA UN Dama oe 47 External capacit
89. y the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Table 2 Peripheral clock gating bit assignments in CLK PCKENR1 2 registers Bit Peripheral Bit Peripheral Bit Peripheral Bit Peripheral clock clock clock clock PCKEN17 TIM1 PCKEN13 UART3 PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM3 PCKEN12 UART1 PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 Ic PCKEN24 Reserved PCKEN20 Reserved DoclD022171 Rev 5 I STM8S007C8 Product overview 4 6 4 7 d Power management For efficent power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode In this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is trigger

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