AD7823 2.7 V to 5.5 V, 5 s, 8-Bit ADC in 8-Lead
Contents
1. 450 mW T4 25 C unless otherwise noted Oja Thermal Impedance 160 C W Vppto GND 0 eee cence cece eee eens 0 3 V to 7 V 6j Thermal Impedance 05 56 C W Digital Input Voltage to GND Lead Temperature Soldering CONVST SCLK 0 3 V Vpp 0 3 V Vapor Phase 60 sec 0 eee eee eee 215 C Digital Output Voltage to GND Infrared 15 86C ine ee eee wed 220 C Dour eee n 0 3 V Vpp 0 3 V MicroSOIC Package Power Dissipation 450 mW Vgge to GND 1 eee eee eee 0 3 V Vpp 0 3 V Oja Thermal Impedance ecce das rtu a 206 C W Analog Inputs 6 Thermal Impedance 05 44 C W Vines Vm o9 omo o9 o9 9 o9 9 9 9 9 9 9 9 9 9 n9 9 n9 5 0 3 V Vpp 0 3 V Lead Temperature Soldering Storage Temperature Range 65 C to 150 C Vapor Phase 60 sec 0 eee e eee eee eee 215 C Junction Temperature 20 2 ce ee eee eee 150 C Infrared 15 sec 2 cece cece ee cc eee ee ec ees 220 C Plastic DIP Package Power Dissipation 450 mW Stresses above those listed under Absolute Maximum Ratings may cause perma Oja Thermal Impedance ee eee 125 C W nent damage to the device This is a stress rating only functional operation of the 1c Thermal Impedance eedem es 50 C W device at these or any other conditions above those listed in the operational Lead Temperature Soldering 10 sec 22. OPEN ACQUISITION PHASE SWITCH CLOSED Figure 7 Equivalent Analog Input Circuit The analog input of the AD7823 is made up of a pseudo dif ferential pair Vy pseudo differential with respect to V The signal is applied to V but in the pseudo differential scheme the sampling capacitor is connected to Vm during conversion see Figure 8 This input scheme can be used to remove offsets that exist in a system For example if a system had an offset of 0 5 V the offset could be applied to Vm and the signal applied to Vin This has the effect of offsetting the input span by 0 5 V It is only possible to offset the input span when the reference volt age Vggg is less than Vpp Voggsgr CHARGE REDISTRIBUTION DAC SAMPLING CAPACITOR wol Nue UY ral CONVERSION Vin Vorrser i V Figure 8 Pseudo Differential Input Scheme us REV C AD7823 When using the pseudo differential input scheme the signal on Vm must not vary by more than a 1 2 LSB during the conver sion process If the signal on Vm varies during conversion the conversion result will be incorrect For single ended operation V is always connected to AGND Figure 9 shows the AD7823 pseudo differential input being used to make a unipolar dc current mea surement A sense resistor is used to convert the current to a voltage and the voltage is applied to the differential input as shown AD7823 Figure 9 DC Current Measurement Scheme DC A
3. Single Supply Operation The AD7823 operates from a single 2 7 V to 5 5 V supply and typically consumes only 9 mW of power The power dissipa tion can be significantly reduced at lower throughput rates by using the automatic power down mode e g at a throughput rate of 10 kSPS the power consumption is only 570 W 3 Automatic Power Down The automatic power down mode whereby the AD7823 powers down at the end of a conversion and wakes up before the next conversion means the AD7823 is ideal for battery powered applications See Power vs Throughput Rate section 4 Serial Interface An easy to use fast serial interface allows connection to most popular microprocessors with no external circuitry One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 2000 AD 1823 SPEC FI CATI 0 NS GND 0 V Vref Von All specifications 40 C to 125 C unless otherwise noted Parameter Y Version Unit Test Conditions Comments DYNAMIC PERFORMANCE fi 30 KHz fsauprg 133 kHz Signal to Noise Distortion Ratio 48 dB min Total Harmonic Distortion 70 dB typ Peak Harmonic or Spurious Noise 70 dB typ Intermodulation Distortion fa 48 kHz fb 48 5 kHz 2nd Order Terms 77 dB typ 3rd Order Terms 77 dB typ DC ACCURACY Resolution 8 Bits Relative Accuracy 0 5 LSB max Differential Non
4. conversion In this case the new data will not be latched into the output shift regis ter until the read has finished If the user waits until the end of the conversion process i e 4 us typ after falling edge of CONVST Point B before initiating a read the current conversion result is shifted out g REV C AD7823 Mode 2 Operation Automatic Power Down When used in this mode of operation the part automatically powers down at the end of a conversion This is achieved by leaving the CONVST signal low until the end of the conversion The timing diagram in Figure 15 shows how to operate the part in this mode If the AD7823 is powered down the rising edge of the CONVST pulse causes the part to power up When the part has powered up 1 5 us after the rising edge of CONVST the CONVST signal is brought low and a conversion is initiated on this falling edge of the CONVST signal The conversion takes 5 us max and after this time the conversion result is latched into the serial shift register and the part powers down Therefore when the part is operated in Mode 2 the effective conversion time is equal to the power up time 1 5 us and the SAR conver sion time 5 Us i e 6 5 Us As in the case of Mode 1 operation the rising edge of the CONVST pulse enables the serial port of the AD7823 see Serial Interface section If a serial read is initiated soon after this rising edge Point A i e before the end of the con
5. down automatically at the end of a conversion and wakes up at the start of a new conversion This feature significantly reduces the power consumption of the part at lower throughput rates The AD7823 can also operate in a high speed mode where the part is not powered down between conversions In this high speed mode of operation the conver sion time of the AD7823 is 4 us typ The maximum throughput rate is dependent on the speed of the serial interface of the microcontroller The part is available in a small 8 lead 0 3 wide plastic dual in line package mini DIP in an 8 lead small outline IC SOIC and in an 8 lead microSOIC package REV C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM Voo AGND VREF Bi Dour O SCLK CONVST PRODUCT HIGHLIGHTS 1 Complete 8 Bit ADC in 8 Lead Package The AD7823 is an 8 bit 4 us typ ADC with inherent track and hold functionality and a high speed serial interface all in an 8 lead microSOIC package Vazr may be connected to Vpp to eliminate the need for an external reference The result is a high speed low power space saving ADC solution 2 Low Power
6. opera tion allows high throughput rates to be achieved The timing diagram in Figure 14 shows how this optimum throughput rate is achieved by bringing the CONVST signal high before the end of the conversion It is recommended that the CONVST signal should go high within 3 us of conversion starting This ensures that the CONVST signal does not go high at the same time the part is attempting to power down The AD7823 leaves its tracking mode and goes into hold on the falling edge of CONVST A conversion is also initiated at this time and takes 4 us typ to complete At this point the result of the current conversion is latched into the serial shift register and the state of the CONVST signal is checked The CONVST signal should be high at the end of the conversion to prevent the part from powering down CONVST D CURRENT CONVERSION QUT RESULT Figure 14 Mode 1 Operation Timing The serial port on the AD7823 is enabled on the rising edge of the CONVST signal see Serial Interface section As explained earlier this rising edge should occur before the end of the con version process if the part is not to be powered down A serial read can take place at any stage after the rising edge of CONVST If a serial read is initiated before the end of the current conver sion process i e at time A then the result of the previous conversion is shifted out on the Dour pin It is possible to allow the serial read to extend beyond the end of a
7. sek ts t4 te Dor Figure 16 Serial Interface Timing REV C AD7823 MICROPROCESSOR INTERFACING The serial interface on the AD7823 allows the parts to be directly connected to a range of many different microprocessors This section explains how to interface the AD7823 with some of the more common microcontroller serial interface protocols AD7823 to PIC16C6x 7x The PIC16C6x Synchronous Serial Port SSP is configured as an SPI Master with the Clock Polarity Bit 0 This is done by writing to the Synchronous Serial Port Control Register SSPCON See PIC16 17 Microcontroller User Manual Figure 17 shows the hardware connections needed to interface to the PIC16 PIC17 In this example I O port RAI is being used to pulse CONVST and enable the serial port of the AD7823 AD7823 PIC16C6x 7x d SDO RC5 ADDITIONAL PINS OMITTED FOR CLARITY Figure 17 Interfacing to the PIC16 PIC17 AD7823 to MC68HC11 The Serial Peripheral Interface SPI on the MC68HCI1 is configured for Master Mode MSTR 0 Clock Polarity Bit CPOL 0 and the Clock Phase Bit CPHA 1 The SPI is configured by writing to the SPI Control Register SPCR see 68HC11 User Manual A connection diagram is shown in Figure 18 AD7823 MC68HC11 ji ERE MISO PD2 ADDITIONAL PINS OMITTED FOR CLARITY Figure 18 Interfacing to the MC68HC11 10 AD7823 to 8051 The AD7823 requires a clock
8. synchronized to the serial data therefore the 8051 serial interface must be operated in Mode 0 In this mode serial data enters and exits through RXD and a serial clock is output on TXD half duplex Figure 19 shows how the 8051 is connected to the AD7823 Here because the AD7823 shifts data out on the rising edge of the serial clock the serial clock must be inverted AD7823 ADDITIONAL PINS OMITTED FOR CLARITY Figure 19 Interfacing to the 8051 Serial Port It is possible to implement a serial interface using the data ports on the 8051 or any microcontroller This would allow direct interfacing between the AD7823 and 8051 to be implemented without the need for any gluing logic The technique involves bit banging an I O port e g P1 0 to generate a serial clock and using another I O port e g P1 1 to read in data see Figure 20 AD7823 ADDITIONAL PINS OMITTED FOR CLARITY Figure 20 Interfacing to the 8051 Using I O Ports REV C AD7823 OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Lead Plastic DIP N 8 0 430 10 92 0 348 8 84 Ie 0 280 7 11 0 240 6 10 0 325 8 25 MBIN1 0 060 1 52 0 210 5 33 0 015 0 38 L 3 Teen 195 4 95 MAX 0 130 0 115 2 93 0 160 4 06 F p NU ii 30 0 115 2 93 Ai ja gt SEATING 0 016 0381 381 0 022 0 558 0 100 0 070 1 77 PLA 0 008 0 204 2 54 0 014 0 356 2 54 0 045 1 15 8 L
9. 16 below The serial inter face is designed to allow easy interfacing to most microcontrollers e g PIC16C PICI7C QSPI and SPI without the need for any gluing logic When interfacing to the 8051 the SCLK must be inverted The Microprocessor Interface section explains how to interface to some popular microcontrollers Figure 16 shows the timing diagram for a serial read from the AD7823 The serial interface works with both a continuous and a noncontinuous serial clock The rising edge of the CONVST signal RESETS a counter which counts the number of serial clocks to ensure the correct number of bits are shifted out of the serial shift registers The SCLK is ignored once the correct number of bits have been shifted out In order for another serial transfer to take place the counter must be reset by the falling edge of the eighth SCLK Data is clocked out from the Dour line on the first rising SCLK edge after the rising edge of the CONVST signal and on subsequent SCLK rising edges The Dour pin goes back into a high impedance state on the falling edge of the eighth SCLK In multipackage applications the CONVST signal can be used as a chip select signal The serial interface will not shift data out until it receives a rising edge on the CONVST pin tPOWER UP ty CONVST SCLK Dour CURRENT CONVERSION RESULT Figure 15 Mode 2 Operation Timing
10. 60 C sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ORDERING GUIDE Linearity Temperature Branding Package Model Error Range Information Option AD7823YN 1 LSB 40 C to 125 C N 8 AD7823YR 1 LSB 40 C to 125 C SO 8 AD7823YRM 1 LSB 40 C to 125 C C2Y RM 8 N plastic DIP RM microSOIC SO small outline IC SOIC 1 6V Figure 1 Load Circuit for Digital Output Timing Specifications REV C 3 AD7823 PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Description 1 CONVST Convert Start Falling edge puts the track and hold into hold mode and initiates a conversion A rising edge on the CONVST pin enables the serial port of the AD7823 This is useful in multipackage applications where a number of devices share the same serial bus The state of this pin at the end of conversion also determines whether the part is powered down or not See Operating Modes section of this data sheet 2 Vis Positive input of the pseudo differential analog input 3 Vw Negative input of the pseudo differential analog input 4 GND Ground reference for analog and digital circuitry 5 VREF External reference is connected here 6 Dour Serial data is shifted out on this pin 7 SCLK Serial Clock An external serial clock is applied here 8 Vopp Positive Supply Voltage 2 7 V to 5 5 V PIN CONFIGURATION DIP SOIC mi
11. ANALOG DEVICES 2 1 V to 5 5 V 5 jus 8 Bit ADC in 8 Lead microSOIC DIP AD7823 FEATURES 8 Bit ADC with 4 ps Conversion Time Small Footprint 8 Lead microSOIC Package Specified Over a 40 C to 125 C Temperature Range Inherent Track and Hold Functionality Operating Supply Range 2 7 V to 5 5 V Specifications at 2 7 V to 5 5 V and 5 V 10 Microcontroller Compatible Serial Interface Optional Automatic Power Down Low Power Operation 570 pW at 10 kSPS Throughput Rate 2 9 mW at 50 kSPS Throughput Rate Analog Input Range 0 V to Vper Reference Input Range 0 V to Vpp Drop In Upgrade to 10 Bits Available AD7810 APPLICATIONS Low Power Hand Held Portable Applications Requiring Analog to Digital Conversion with 8 Bit Accuracy e g Battery Powered Test Equipment Battery Powered Communications Systems GENERAL DESCRIPTION The AD7823 is a high speed low power 8 bit A D converter that operates from a single 2 7 V to 5 5 V supply The part con tains a 4 us typ successive approximation A D converter inherent track and hold functionality with a pseudo differential input and a high speed serial interface that interfaces to most microcon trollers The AD7823 is fully specified over a temperature range of 40 C to 125 C By using a technique that samples the state of the CONVST convert start signal at the end of a conversion the AD7823 may be used in an automatic power down mode When used in this mode the AD7823 powers
12. DE 2 CONVST IDLES LOW nl UE Yoo tpowER uUP_ 1 5ps CONVST J Figure 12 Power Up Times CONVST POWER VS THROUGHPUT RATE By operating the AD7823 in Mode 2 the average power con sumption of the AD7823 decreases at lower throughput rates Figure 13 shows how the automatic power down is implemented using the CONVST signal to achieve the optimum power per formance for the AD7823 The AD7823 is operated in Mode 2 As the throughput rate is reduced the device remains in its power down state for longer and the average power consump tion over time drops accordingly tconvert 5ys tpower uP 1 5us POWER DOWN CONVST ES tcycLe 100ps 10kSPS Figure 13 Automatic Power Down For example if the AD7823 is operated in a continuous sampling mode with a throughput rate of 10 kSPS the power consumption is calculated as follows The power dissipation during normal operation is 10 5 mW Vpp 3 V If the power up time is 1 5 us and the conversion time is 5 us then the AD7823 can be said to dissipate 10 5 mW for 6 5 us worst case during each conver sion cycle If the throughput rate is 10 kSPS the cycle time is 100 us and the average power dissipated during each cycle is 6 5 100 x 10 5 mW 683 uW Figure 2 shows a graph of Power vs Throughput OPERATING MODES Mode 1 Operation High Speed Sampling When the AD7823 is used in this mode of operation the part is not powered down between conversions This mode of
13. analog input signals in the range 0 V to Vpp Figures 4 and 5 below show simplified schematics of the ADC Figure 4 shows the ADC during its acquisition phase SW2 is closed and SW1 is in Position A the comparator is held in a balanced condi tion and the sampling capacitor acquires the signal on Vr REDISTRIBUTION DAC o I gt D 0 m SAMPLING CAPACITOR Vins 0 04 0 A SW1 B ACQUISITION PHASE Vin Vpp 3 Figure 4 ADC Acquisition Phase When the ADC starts a conversion see Figure 5 SW2 will open and SW1 will move to Position B causing the comparator to become unbalanced The control logic and the charge redis tribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor in order to bring the com parator back into a balanced condition When the comparator is rebalanced the conversion is complete The control logic generates the ADC output code Figure 11 shows the ADC transfer function CONTROL LOGIC T COMPARATOR CHARGE REDISTRIBUTION DAC SAMPLING CAPACITOR Vins O O swi CONTROL LOGIC CONVERSION PHASE Vin Vpp 3 Figure 5 ADC Conversion Phase TYPICAL CONNECTION DIAGRAM Figure 6 shows a typical connection diagram for the AD7823 The serial interface is implemented using two wires the rising edge of CONVST enables the serial interface see Serial Interface section for more details Vggg
14. aximum deviation from a straight line passing through the endpoints of the ADC transfer function Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC Offset Error This is the deviation of the first code transition 0000 000 to 0000 001 from the ideal i e AGND 1 LSB Gain Error This is the deviation of the last code transition 1111 110 to 1111 111 from the ideal i e Vpzp 1 LSB after the offset error has been adjusted out Track Hold Acquisition Time Track hold acquisition time is the time required for the output of the track hold amplifier to reach its final value within 1 2 LSB after the end of conversion the point at which the track hold returns to track mode It also applies to situations where there is a step input change on the input voltage applied to the Vm input of the AD7823 It means that the user must wait for the duration of the track hold acquisition time after the end of conversion or after a step input change to Vw before starting another conversion to ensure that the part operates to specification AD7823 2048 POINT FFT SAMPLING 136 054 fin 29 961 7 VET mr UT TT TH Figure 3 AD7823 SNR AD7823 CIRCUIT DESCRIPTION Converter Operation The AD7823 is a successive approximation analog to digital converter based around a charge redistribution DAC The ADC can convert
15. be a noise peak Intermodulation Distortion With inputs consisting of sine waves at two frequencies fa and fb any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m n 0 1 2 3 etc Intermodulation terms are those for which neither m nor n are equal to zero For example the second order terms include fa fb and fa fb while the third order terms include 2fa fb 2fa fb fa 2fb and fa 2fb Typical Performance Characteristics 10 0 z E 1 tr wW z o n 0 1 i 10 20 30 40 50 THROUGHPUT kSPS Figure 2 Power vs Throughput REV C The AD7823 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used In this case the second and third order terms are of different significance The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies As a result the second and third order terms are specified sepa rately The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs Relative Accuracy Relative accuracy or endpoint nonlinearity is the m
16. cquisition Time The ADC starts a new acquisition phase at the end of a conver sion and ends on the falling edge of the CONVST signal At the end of a conversion there is a settling time associated with the sampling circuit This settling time lasts approximately 100 ns The analog signal on Vr is also being acquired during this settling time therefore the minimum acquisition time needed is approximately 100 ns Figure 10 shows the equivalent charging circuit for the sampling capacitor when the ADC is in its acquisition phase R2 represents the source impedance of a buffer amplifier or resistive network R1 is an internal multiplexer resistance and C1 is the sampling capacitor R1 Vine 1250 O o o gt Wore c1 DS Figure 10 Equivalent Sampling Circuit During the acquisition phase the sampling capacitor must be charged to within a 1 2 LSB of its final value The time it takes to charge the sampling capacitor tcuanaz is given by the follow ing formula tcHarGE 6 2 x R2 125 Q x 8 5 pF REV C For small values of source impedance the settling time associated with the sampling circuit 100 ns is in effect the acquisition time of the ADC For example with a source impedance R2 of 10 Q the charge time for the sampling capacitor is approxi mately 2 ns The charge time becomes significant for source impedances of 4 6 kQ and greater AC Acquisition Time In ac applications it is recommended to always buffer analog in
17. croSOIC TOP VIEW D s Not to Scale g OUT ET REV C AD7823 TERMINOLOGY Signal to Noise Distortion Ratio This is the measured ratio of signal to noise distortion at the output of the A D converter The signal is the rms amplitude of the fundamental Noise is the rms sum of all nonfundamental signals up to half the sampling frequency fs 2 excluding dc The ratio is dependent upon the number of quantization levels in the digitization process the more levels the smaller the quantization noise The theoretical signal to noise distortion ratio for an ideal N bit converter with a sine wave input is given by Signal to Noise Distortion 6 02N 1 76 dB Thus for an 8 bit converter this is 50 dB Total Harmonic Distortion Total harmonic distortion THD is the ratio of the rms sum of harmonics to the fundamental For the AD7823 it is defined as Jv THD dB 20 log where V is the rms amplitude of the fundamental and V5 V3 V4 V and Vg are the rms amplitudes of the second through the sixth harmonics Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum up to fs 2 and excluding dc to the rms value of the fundamental Normally the value of this specification is determined by the largest harmonic in the spectrum but for parts where the harmonics are buried in the noise floor it will
18. ead Small Outline Package SO 8 0 1968 5 00 E 1890 4 80 L 8 5 0 1574 4 00 0 2440 6 20 0 1 D 4 10 2284 5 80 ig e 0688 1 75 0 0196 0 50 0532 1 35 al Is 0 0099 0 25 PIN 1 0 0098 0 25 0 0040 0 10 TTL 2 ry gt e gt e 8 f 0 0500 0 0192 0 49 fee lle SEATING 127 o9738 0 35 0 0098 025 0 0500 1 27 PLANE psc 0 0075 0 19 0 0160 0 41 e x 45 e 8 Lead microSOIC Package RM 8 0 122 3 10 Eg em 0 122 3 10 0 114 2 90 0 199 5 05 0 187 4 75 gt we 0 0256 0 65 BSC 0 120 3 05 0 120 3 05 0 112 2 84 0 112 2 84 I 0 043 1 09 0 037 0 94 0 006 0 15 v 0 002 0 05 4 4 F 33 0 018 0 46 F E be SEATING 0 008 0 20 0 011 0 28 0 028 0 71 PLANE 0 003 0 08 0 016 0 41 REV C 11 C01322a 0 10 00 rev C PRINTED IN U S A
19. is connected to a well decoupled Vpp pin to provide an analog input range of 0 V to Vpp When Vpp is first connected the AD7823 powers up in a low current mode i e power down A rising edge on the CONVST input will cause the part to power up see Operating Modes If power consumption is of concern the automatic power down at the end of a conversion should be used to improve power performance See Power vs Throughput Rate section of the data sheet SUPPLY 2 7V TO 5 5V TWO WIRE SERIAL INTERFACE OV TO VREF O INPUT Figure 6 Typical Connection Diagram Analog Input Figure 7 shows an equivalent circuit of the analog input struc ture of the AD7823 The two diodes D1 and D2 provide ESD protection for the analog inputs Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV This will cause these diodes to become forward biased and start conducting current into the substrate The maximum current these diodes can conduct without caus ing irreversible damage to the part is 20 mA The capacitor C2 is typically about 4 pF and can be primarily attributed to pin capacitance The resistor R1 is a lumped component made up of the on resistance of a multiplexer and a switch This resistor is typically about 125 Q The capacitor C1 is the ADC sampling capacitor and has a capacitance of 3 5 pF Vpp R1 C1 1250 3 5pF L o Vpp 3 Vive D2 CONVERT PHASE SWITCH
20. linearity DNL 0 5 LSB max Gain Error LSB max Offset Error 1 LSB max Total Unadjusted Error LSB max Minimum Resolution for Which No Missing Codes Are Guaranteed 8 Bits ANALOG INPUT Input Voltage Range 0 V min VREF V max Input Leakage Current 1 uA max Input Capacitance 15 pF max REFERENCE INPUTS Veer Input Voltage Range 1 2 V min Vpp V max Input Leakage Current 1 uA max Input Capacitance 20 pF max LOGIC INPUTS Vine Input High Voltage 2 0 V min Vwi Input Low Voltage 0 4 V max Input Current In 1 uA max Typically 10 nA Vy 0 V to Vpp Input Capacitance Cr 8 pF max LOGIC OUTPUTS Output High Voltage Voy 2 4 V min Isounce 200 pA Output Low Voltage Vor 0 4 V max Is 200 uA High Impedance Leakage Current 1 uA max High Impedance Capacitance 15 pF max CONVERSION RATE Conversion Time 4 us typ Track Hold Acquisition Time 100 ns max See DC Acquisition Section POWER SUPPLY Vpp 2 1 5 5 Volts For Specified Performance Ipp 3 5 mA max Sampling at 133 kSPS and Logic Inputs Vpp or 0 V Vpp 5 V Power Dissipation 17 5 mW max Nominal Supplies Power Down Mode Ipp 1 uA max Power Dissipation 5 uW max Nominal Supplies Automatic Power Down Vpp 3 V 1 kSPS Throughput 54 uW max 10 kSPS Throughput 540 uW max 50 kSPS Throughput 2 7 mW max NOTES See Terminology Sample tested during initial release and after any redesign or process change that may affect this parameter Specifications subject to change witho
21. put signals The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of the ADC Large values of source impedance will cause the THD to degrade at high throughput rates In addition better perfor mance can generally be achieved by using an external 1 nF capacitor on Vy ADC TRANSFER FUNCTION The output coding of the AD7823 is straight binary The designed code transitions occur at successive integer LSB values i e 1 LSB 2 LSBs etc The LSB size is Vgggp 256 The ideal trans fer characteristic for the AD7823 is shown in Figure 11 below 111 111 111 110 Ww B 111 000 o Q 011 111 d L 1LSB Vngp 256 000 010 000 001 000 000 e gt r 0V 1LSB Vper 1LSB ANALOG INPUT Figure 11 Transfer Characteristic AD7823 POWER UP TIMES The AD7823 has a 1 5 us power up time When Vpp is first connected the AD7823 is in a low current mode of operation In order to carry out a conversion the AD7823 must first be powered up The ADC is powered up by a rising edge on the CONVST pin A conversion is initiated on the falling edge of CONVST Figure 12 shows how to power up the AD7823 when Vpp is first connected or after the AD7823 is powered down using the CONVST pin Care must be taken to ensure that the CONVST pin of the AD7823 is logic low when Vpp is first applied MODE 1 CONVST IDLES HIGH o VoD t lt 1ps Q lPowERuP Sip MO
22. ut notice REV C AD7823 TIMING CHARACTERISTICS 2 40 C to 125 C unless otherwise noted Parameter Vpp 5 V 10 Vpp 3 V 10 Unit Conditions Comments t 5 5 us max Conversion Time Mode 1 Operation High Speed Mode ty 20 20 ns min CONVST Pulsewidth t5 25 25 ns min SCLK High Pulsewidth t4 25 25 ns min SCLK Low Pulsewidth tj 5 5 ns min CONVST Rising Edge to SCLK Rising Edge Set Up Time tg 10 10 ns max SCLK Rising Edge to Dour Data Valid Delay t 5 5 ns max Data Hold Time after Rising Edge SCLK tg 4 20 20 ns max Bus Relinquish Time after Falling Edge of SCLK 10 10 ns min tPOWERUP 1 5 1 5 us max Power Up Time NOTES ISample tested to ensure compliance See Figures 14 15 and 16 3These numbers are measured with the load circuit of Figure 1 They are defined as the time required for the o p to cross 0 8 V or 2 4 V for V pp 5 V 10 and 0 4 V or 2 V for Vpp 3 V 10 Derived from the measured time taken by the data outputs to change 0 5 V when loaded with the circuit of Figure 1 The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor This means that the time quoted in the Timing Characteristics tg is the true bus relinquish time of the part and as such is independent of external bus loading capacitances Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS SOIC Package Power Dissipation
23. version then the result of the previous conversion is shifted out on pin Dour In order to read the result of the current conversion the user must wait at least 5 us max after the falling edge of CONVST before initiating a serial read The serial port of the AD7823 is still functional even though the AD7823 has been powered down Note A serial read should not cross the reset rising edge of CONVST Because it is possible to do a serial read from the part while it is powered down the AD7823 is powered up only to do the conver sion and is immediately powered down at the end of a conversion This significantly improves the power consumption of the part at slower throughput rates see Power vs Throughput Rate section Note Although the AD7823 takes 1 5 us to power up after the rising edge of CONVST it is not necessary to leave CONVST high for 1 5 us after the rising edge before bringing it low to initiate a conversion If the CONVST signal goes low before 1 5 us in time has elapsed the power up time is timed out inter nally and a conversion is initiated Hence the AD7823 is guaran teed to have always powered up before a conversion is initiated even if the CONVST pulsewidth is 1 5 us If the CONVST width is 71 5 us a conversion is initiated on the falling edge SERIAL INTERFACE The serial interface of the AD7823 consists of three wires a serial clock input SCLK serial port enable CONVST and a serial data output Dour see Figure
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