Bubble board User Manual
Contents
1. PUSH T NOE TY TA BUTTON ET re ot A SWITCH SW3 f 00 ts oo PUSH 22 DIP SW BUTTON O0 SWITCH SW1 28 DIP SW BIT3 00 The Bubble has two push button switches and 4 way DIP switch To use these switches it is necessary to set the IO pins connected to the switches to have a pull up resistor in the FPGA This is set in FPGA constraints file Any switches pressed or made will then give a LOW signal at the FPGA otherwise a HIGH is seen The two push button switches are connected to the following IO pins Confidential O 2012 RivieraWaves Page 32 of 58 Release Date 2012 02 06 Title Bubble board User Manual RivieraWaves The four DIP switch bits are connected to the following IO pins M16 L15 M4 B3 Confidential 2012 RivieraWaves Page 33 of 58 Release Date 2012 02 06 Reference in Wireless Title Bubble board User Manual NN 15 16k SERIAL EEPROM LESEITIPITIIITILTI LI a fo i nm 16K SERIAL EEPROM 00 T T The Bubble has Atmel AT24C16 EEPROM device which use simple Parallel address and single serial data line and clock There is also a write protect line which can be used to electronically safeguard the information contained in the device Confidential O 2012 RivieraWaves Page 342. oo oo 000000000 24 000000000 ACCELEROMETER The Bubble board has an MMA7455L 3 axis accelerometer which has 3 sensitivity ranges 2g 4g and 386 Typical applications for this device are tilt and motion sensing freefall detection and shock and vibration detection and these types of devices are used in cell phones anti theft equipment pedometers e compasses and for 3d gaming The datasheet for this accelerometer can be obtained from www freescale com This device has both SPI and I2C interfaces The connections between the accelerometer and the FPGA are shown below Confidential O 2012 RivieraWaves Page 38 of 58 Release Date 2012 02 06 Title Bubble board User Manual RivieraWaves CS 7 11 INT1 DRDY 8 J6 INT2 9 J7 SDO 12 K1 SDA SDI SDO 13 K2 SLC SPC 14 K6 IADDRO 4 FIXED OV Confidential O 2012 RivieraWaves Page 39 of 58 Release Date 2012 02 06 Title Bubble board User Manual 18 52 SAAABRAAZAAALIA en 33 2 1 le TNT 4 000000 50000000000 0000000000 TWO PS2 PORTS 4 14mm 13mm Confidential O 2012 RivieraWaves Page 40 of 58 Release Date 2012 02 06 22 777 Title Bubble board User Manual
3. Confidential O 2012 RivieraWaves Page 22 of 58 Title Bubble board User Manual RivieraWaves Release Date 2012 02 06 NN pom 7 IDC 4 C6 27 IDC 14 AB15 9 IDC 5 Y9 29 IDC 15 AA14 11 IDC 6 AB9 31 IDC 16 AB14 13 IDC 7 D9 33 IDC 17 Y13 15 IDC 8 C8 35 IDC 18 AB13 17 IDC 9 C9 37 IDC 19 W12 19 IDC 10 A9 39 IDC 20 Y12 Confidential 2012 RivieraWaves Page 23 of 58 Release Date 2012 02 06 Title Bubble board User Manual 9 LCD DISPLAY LCD DISPLAY n e 4 UE 00000000000 00000000000 The standard Bubble LCD display is LCM S01602DTR M display which is 16x2 alpha numerical display with a Hitachi 44780 compatible chipset More information on this at http www lumex com specs LCM S01602DTR9620M pdf The IO pins used for the display are shown in the table below Backlight ON V11 Confidential O 2012 RivieraWaves Page 24 of 58 Title Bubble board User Manual Release Date 2012 02 06 RS C14 R W C13 EN D11 DO C17 D1 A17 D2 D17 D3 E16 04 A15 D5 C15 D6 D15 D7 D14 RivieraWaves NN Confidential 2012 RivieraWaves Page 25 of 58 Release Date 2012 02 06 Reference in Wireless Title Bubble board User Manual BiigrgWaves 10 LEDS a
4. LED6 4 MEG 4725 TIT D xw LED13 9j 4 oopa Io LED12 5 LED3 99 aci LED10 LED5 60 oo oo 00 oo HOO oo LED7 Bubble has 13 LEDs There is a single red LED in the lower half of the board just below the Real Time Clock device and 12 LEDs arranged into 4 blocks of three one of each block being red orange and green This is to enable users to simulate a traffic light sequence The LEDS may turn on dimly when power is applied to the unconfigured board The relevant IO pin for an LED needs to be asserted low to ensure the specified LED turns on The exception to this is LED7 for which the relevant IO pin should be asserted high Confidential O 2012 RivieraWaves Page 26 of 58 Title Bubble board User Manual Release Date 2012 02 06 The LEDS are connected to the FPGA as indicated below 5 RyigaWaves 07 1 20 RED 2 A21 ORANGE 3 B22 GREEN 4 F16 GREEN 5 F17 ORANGE 6 C19 RED 7 K7 RED SINGLE 8 P17 RED 9 V20 ORANGE 10 U19 GREEN 11 W22 GREEN 12 w20 ORANGE 13 T20 RED Confidential 2012 RivieraWaves Page 27 of 58 Title Bubble board User Manual Release Date 2012 02 06 11 REAL TIME CLOCK REAL TIME CLOCK DN1306EN RyigaWaves A 2010 Enterpoint Ltd eNter poi
5. The full ISE toolset can also be purchased from the Xilinx website Once you have obtained your ISE tools 1 Connect your programming cable to the board and your PC hosting the Xilinx software 2 Connect the Bubble board to either a USB connector of a PC a USB power supply or a 5V source plugged into the 2 1mm Jack socket Note that some Laptops and desktop computer USB ports have a current limit of 100mA Bubble can exceed this in some circumstances and should you have a problem a powered USB hub or external mains to USB adaptor are recommended solutions Check that the 5V input selection jumper on J11 situated adjacent to the 5V jack socket is set to the correct position left for power from USB right for power into Jack socket Switch the power ON using the small standby switch near J11 3 If using an external power brick switch on your power source Confidential 2012 RivieraWaves Page 9 of 58 Title Bubble board User Manual Release Date 2012 02 06 3 FPGA gt t LEM 4 4 4 SPARTAN 6 00 FPGA T T 60 ivieraWaves Reforence in Wireless Bubble supports Spartan 6 devices in the FGG484 package Bubble is normally available with commercial grade 2 speed devices fitted in the XC6SLX150 size Confidential O 2012 Riviera
6. 00 BUTTON i ETHERNET 46 SWITCHES INTERFACE 60 9 9 i 4 WAY DIP DIL HEADERS SWITCH WITH FORTY 5V 2 TOLERANT IO 26 USB REAL TIME CLOCK MICRO SDCARD DN1306EN HOLDER ON BACK OF BOARD I6KBIT MUI EEPROM i H CLOCK TAG NE GENERATOR CONNECTOR BATTERY HOLDER ACCELEROMETER FOR REAL TIME CLOCK ON RJ45 CONNECTOR 128M MINI USB FLASH TWO PS2 CONNECTOR MEMORY PORTS Figure 2 1 Bubble front View Confidential O 2012 RivieraWaves Page 7 of 58 22 777 Title Bubble board User Manual Release Date 2012 02 06 eee o gt 201 Enterpoint Ltd iaa WW enter Point UK Be LI 4 E j 1 Winn he ue uS WOW iw X f e d EXPANSION HEADER LI BATTERY HOLDER MICRO SDCARD FOR REAL TIME HOLDER CLOCK Figure 2 2 Bubble Back View The Bubble board can be supplied with either a Prog2 parallel port programming cable or a Prog3 USB port programming cable Confidential O 2012 RivieraWaves Page 8 of 58 ff Title Bubble board User Manual QlvieraWaves Release Date 2012 02 06 The full Xilinx toolset is required to build a design on the on board Spartan 6 LX150 FPGA ISE Webpack can be obtained directly from the Xilinx website at http www xilinx com ise Registration will be necessary to complete the download
7. RivieraWaves NN Bubble board User Manual 2012 02 06 RivieraWaves http www rivierawaves com RivieraWaves confidential This document is copyrighted and released under CDA or NDA only Do not copy or distribute without written authorization from RivieraWaves Please check with RivieraWaves that this document is the latest release Title Bubble board User Manual Release Date 2012 02 06 Table of Contents Table of Contents LIST OF Figures List of 1 2 Getting 5 11 REAL TIME CLOCK 12 POWER MONITOR AND MASTER RESET 13 5 14 SWITCHES 15 16k SERIAL EEPROM 16 MICRO SD CARD HOLDER 17 ACCELEROMETER DS o 19 POWER CONNECTIONS 20 POWER REGULATORS 21 CLOCK GENERATOR Confidential O 2012 RivieraWaves RivieraWaves NN Page 2 of 58 Title Bubble board User Manual Release Date 2012 02 06 22 EXPANSION HEADERS ntn tnnt ao aon 48 23 Programming Bubble nonton EN YR PETS ser E Yn op 53 24 MECHANICAL ARRANGEMENT 56 Confidential 2012 RivieraWaves Page 3 of 58 Title Bubble board User Manual Ri i Release Dat
8. 0 B18 3 3V L2P 0 AA21 2 IO L65N 0 A18 3 3V lO L2N 0 21 3 IO L63P 0 B16 3 3V lO 0 Y19 4 lO L63N 0 A16 3 3V lO L5N 0 AB19 5 IO L50P 0 B14 3 3V lO L14P 0 18 6 IO L50N 0 A14 3 3V lO L14N 0 AB18 7 lO L37P 0 B12 3 3V lO L15P 0 Y17 8 lO L37N 0 A12 3 3V lO L15N 0 AB17 9 IO L35N 0 A11 3 3V lO L19P 0 AA16 10 10 C11 3 3V lO 0 AB16 11 IO B10 3 3V lO 0 12 12 10 134 0 10 3 3V lO L31N 0 AB12 13 IO L6P 0 B8 3 3V lO L45P 0 AA8 14 L6N 0 A8 3 3V lO 145 0 AB8 15 IO 3 B6 3 3V lO 149 0 AB6 16 10_L4N 3 A6 3 3V lO 149 0 AAG 17 IO L5P 3 3 3V lO L57P 0 AAA 18 10_L5N 3 A7 3 3V lO L57N 0 ABA 19 10 1327 3 D7 3 3V lO L64P 0 AA2 20 IO L32N 3 D8 3 3V lO 164 0 AB2 Confidential O 2012 RivieraWaves Page 16 of 58 Title Bubble board User Manual Release Date 2012 02 06 The DIL Headers provide a simple mechanical and electrical interface for add on modules There are twenty on each side of the DIL Header giving a total of 40 1 0 available Each of these I O pins is protected bus switch technology to facilitate 5V tolerance on all of these pins Bus switch technology has a minimal effect on I O timing with propagation times of less than 250ps through these devices There are sites on the reverse side of the Bubble where pull up resistors to 5
9. ADBUS7 24 P4 ACBUSO 26 P5 ACBUS1 27 R1 ACBUS2 28 R3 ACBUS3 29 R4 ACBUS4 30 T1 ACBUS5 32 T2 ACBUS6 33 T4 ACBUS7 34 U1 BDBUSO 38 TCK Confidential O 2012 RivieraWaves Page 20 of 58 Title Bubble board User Manual Release Date 2012 02 06 RivieraWaves NN BDBUS1 39 TDI BDBUS2 40 TDO BDBUS3 41 TMS BDBUS4 43 P3 BDBUSS 44 P2 BDBUS6 45 P1 BDBUS7 46 P8 BCBUSO 48 N6 BCBUS1 52 M2 BCBUS2 53 M5 BCBUS3 54 M6 BCBUS4 55 M8 BCBUSS 57 BCBUS6 58 L1 BCBUS7 59 L6 PWREN 60 K4 SUSPEND 36 T3 Confidential 2012 RivieraWaves Page 21 of 58 Title Bubble board User Manual RivieraWaves Release Date 2012 02 06 X f Reference in Wireless 8 TOPIDC HEADER IDC HEADER 00000000000000000 Ie de denn At the top the Bubble there a 40 way IDC connector This has 20 IO connections to the FPGA 20 DGND OV connections The IOs are wired directly to the Spartan 6 FPGA so signal voltage to these pins should not exceed 3 3V The connections between the IDC connector and the FPGA are shown below Pin 1 of the IDC header is defined as the pin on the left of the lower row of pins as viewed from the front of the board The odd numbered pins occupy the lower row of connections on the IDC header 1 IDC 1 C5 21 IDC 11 D10 3 IDC 2 A5 23 IDC 12 C10 5 IDC 3 D6 25 IDC 13 Y15
10. SCLK 53 BCBUS2 SDAT 54 BCBUS3 Confidential 2012 RivieraWaves Page 47 of 58 Release Date 2012 02 06 22 777 Title Bubble board User Manual NN ove 22 EXPANSION HEADERS LIN 7 c2010 Enterpoint Ltd WW eNter Point PIN Al PIN PIN PIN A1 hu gt 25 7 SA gt a EXPANSION 5 7 EXPANSION HEADER J101 gt Ea HEADER J100 PIN B30 dai L5 vd ML m PIN A30 eT o s 8 av FINE PIN B30 Confidential O 2012 RivieraWaves Page 48 of 58 Release Date 2012 02 06 22 777 Title Bubble board User Manual NN ove On the reverse side of Bubble are two CLP 130 02 L D A connectors which provide access to up to 38 LVDS pairs 76 single ended IO on the FPGA These connections are not available for all FPGA sizes but they are all connected for the XC6SLX150 device The connections between these expansion headers and the FPGA are shown below The suffix of the IO function denotes the FPGA Bank into which it connects 1 DGND A4 A5 A6 EXP P7 E14 lO 147 0 7 7 F15 lO 147 0 B7 EXP P6 F14 A8 DGND B8 EXP 6 H14 9 DGND B9 EXP P8 H13 lO 146 0 10 EXP 8 G13 lO 146 0 11 EXP 11 E12 lO L43P 0 12 DGND B12 EXP N11 012 lO L43N O A13 DGND A16 DGND A17 DGND B17 EXP
11. This header can also be used for an external system reset with a remote switch or relay wired across the pins The signal from the voltage monitor is connected to pin C12 of the FPGA p TTTTITTYYTUTY VOLTAGE 2 T MONITOR 7 At 73 ado tn AIL oo ooo oo oo oo oo oo Confidential O 2012 RivieraWaves Page 30 of 58 Release Date 2012 02 06 Reference in Wireless Title Bubble board User Manual 13 OSCILLATOR The main oscillator the Bubble is ASEM 50MHz oscillator The oscillator is situated as shown is connected to the FPGA on PIN AB11 The Bubble board also has a Clock Generator see below fitted with a 25MHz oscillator The Spartan 6 has PLLs and DCMs to produce multiples divisions and phases of the clock for specific application requirements Please consult the Spartan 6 datasheet available from the Xilinx website at http www xilinx com if multiple clock signals are required OSCILLATOR 8 oc i oo oo 00 oo oo oo oo oo IR m Confidential O 2012 RivieraWaves Page 31 of 58 Release Date 2012 02 06 Title Bubble board User Manual 14 SWITCHES
12. 16 CLOCK NOTE C SEL A17 EXP P24 W10 10 44 2 B17 EXP CLOCK NOTE C A18 EXP N24 10 10 L44N 2 818 5V NOTE E A19 EXP P25 W9 10 147 2 819 NOTE E A20 EXP N25 lO 147 2 820 5v NOTE E A21 EXP P26 W8 10 2 B21 5V NOTE E 22 EXP N26 V7 lO L46N 2 822 V5 NOTE E 823 FEED 1 NOTE E 824 FEED 1 NOTE E A25 EXP P28 7 lO L48P 2 825 FEED 1 NOTE E 26 EXP N28 B7 O 148 2 826 FEED 1 NOTE E 827 FEED 2 NOTE E 828 FEED 2 NOTE E A29 EXP P34 U6 lO L63P 2 829 FEED 2 NOTE E A30 EXP N34 V5 lO 163 2 B30 FEED 2 NOTE E AVAILABLE ON LX150 LX100 LX45 LX25 AVAILABLE ON LX150 LX100 LX45 Confidential O 2012 RivieraWaves Page 50 of 58 Release Date 2012 02 06 Title Bubble board User Manual aves AVAILABLE ON LX150 LX45 LX25 AVAILABLE ON Lx150 1 45 AVAILABLE ON ALL DEVICES NOTES A This pin is connected to the main suspend pin of the Spartan6 and is intended for use where the A D FPGA needs to be shut down from an external device e g for power saving Leaving this pin unconnected allows the FPGA to function normally Asserting the pin HIGH 3v3 will shut the FPGA down There is a 100ohm resistor connected between this pin and EXP SCP connects to 4 resistor sites R204 to R207 which connect to
13. 901NLGI clock generator capable of generating four single ended clocks and one differential clock which are all connected to FPGA It can be used to generate clock frequencies in the range 4 9KHz to 500MHz The clock generator is controlled by an I2C serial interface and has an internal EEPROM Confidential O 2012 RivieraWaves Page 46 of 58 Release Date 2012 02 06 22 777 Title Bubble board User Manual ove for storage of configuration data Information and configuration software for this device are available from www idt com The connections between the Clock Generator and the FPGA are shown below 02 IDT5VA9EE901 Function IDTSVISEESO1Pin FPGAPin CLK C 24 K5 P CLK Differential Clock ve 11 JA P CLK Differential Clock ve 10 K3 CLKB 8 M3 CLKA 7 L4 18 WA 19 UA 26 AB3 29 U3 30 J3 Signals shown in yellow are routed via a 4 bit multiplexer which enables these signals if required to be controlled from the USB device In order for this to happen the signal on BCBUSA must be asserted low or a jumper should be fitted to J7 default The legend on the PCB shows the positions for the jumper marked FPGA if the FPGA is to control the clock generator right side of J7 or USB if the control is from the FT2232H device left side of J7 When USB control is selected the signals will be routed as follows SHUTDOWN OE 48 BCBUSO SEL2 SUSPEND 52 BCBUS1
14. Bubble board User Manual Nivigrgviaves AA Release Date 2012 02 06 E There is a choice of power sources for the expansion header 5v supply The supply on pins 18 22 of J101 is either from the Jack socket on Bubble J13 or from the USB connection to Bubble depending upon the setting of jumper J11 Pins B23 to B26 could if required it could be used to supply 5v from the expansion headers to power the Bubble Pins B27 to B30 could be used for a second alternative power supply e g a solar panel or a battery The Supply voltage should not exceed 5 5V as this would cause irreparable damage to the Voltage Regulators on Bubble Confidential 2012 RivieraWaves Page 52 of 58 Release Date 2012 02 06 Title Bubble board User Manual 23 Programming Bubble TES ETERS TT ELT Py HW oo oo oo E 00 oo HEADER programming the FPGA and SPI Flash parts Bubble is achieved using the JTAG interface Principally it is anticipated that a JTAG connection will be used in conjunction with Xilinx ISE software although other alternatives do exist including self re programming The Spartan 6 series needs to be programmed using ISE 11 or higher Versions of ISE prior to 11 do not support Spartan 6 The full version of the Xilinx tools is required to program the XC6SLX150 2FGG484C There is a single J
15. OUCH OR PLACE HIGHLY FLAMABLE MATERIALS NEAR THESE DEVICES WHILST THE BUBBLE BOARD IS IN OPERATION A Micrel MIC22600 regulator supplies 3 3V with a maximum current available of 6A This powers the FPGA general 1 0 DIL Header and other devices such the Real Time Clock A Micrel MIC22600 regulator supplies 1 2V with a maximum current available of 6A This is used for the core voltage of the FPGA Empirion EP53880l regulator supplies 1 5V with a maximum current of 600mA for the DDR3 and related FPGA 1 0 A National Semiconductor LP2996 push pull regulator produces up to 1 5A at 0 75V This supply is used as reference and termination voltage for the DDR3 memory and related FPGA I O There is a small Standby Switch near the Jack socket which disables the voltage regulators A small residual current into the board may be seen when the switch is in the off position and the 5V supply to the board will still be active Confidential 2012 RivieraWaves Page 45 of 58 Title Bubble board User Manual Release Date 2012 02 06 21 CLOCK GENERATOR Se ee ee tm FT 25 7 9 oo oo oo oo oo 00 oo oo oo oo Ll 4 fup BiigrgWaves Reforence in Wireless CLOCK GENERATOR Bubble has an IDT5V19EE
16. P9 F13 lO 145 0 18 EXP CLOCK1 NOTE C B18 EXP 9 D13 lO 145 0 A19 EXP CLOCK1 N NOTE C B19 EXP P4 G8 L15P A20 EXP SUSPEND N15 NOTE A B20 4 A21 EXP SCP NOTE B B21 EXP P33 A22 PB1 Y4 B22 EXP_N33 A23 PB2 F7 B23 EXP P A24 REG1 EN NOTE D A25 REG2 EN NOTE D A26 DGND A27 DGND A28 DGND A29 DGND A30 AVAILABLE ON LX150 LX100 AVAILABLE ON LX150 LX100 LX75 LX25 AVAILABLE ON LX150 LX100 LX25 AVAILABLE ON LX150 LX100 LX75 LX45 Confidential O 2012 RivieraWaves Page 49 of 58 Release Date 2012 02 06 Title Bubble board User Manual RivieraWaves AVAILABLE ON LX150 LX100 LX45 LX25 727777 AVAILABLE ON LX150 LX100 LX45 DI AVAILABLE ON LX150 LX45 LX25 AvAIABLE ON Lx150 LX45 AVAILABLE ON ALL DEVICES DGND B2 EXP 17 W18 L6P 2 B3 N17 18 L6N 2 BA B5 DGND A8 N20 14 10 L20N 2 A9 P18 V13 10 L18P 2 B9 DGND A10 EXP N18 W13 O L18N 2 B10 EXP P38 014 10 L14P 2 A11 EXP P32 T7 IO L60P 2 B11 EXP N38 013 101143 2 12 EXP N32 R7 lO L60N 2 812 EXP SEL1 NOTE C B13 EXP SELO NOTE C B14 EXP P37 AA10 141 2 A15 EXP P23 R11 0 L40P 2 B15 EXP N37 AB10 O 141 2 A16 EXP N23 T11 10 1403 2 B
17. TAG chain on Bubble The JTAG chain allows the programming of the Spartan 6 and SPI Flash device Confidential O 2012 RivieraWaves Page 53 of 58 Title Bubble board User Manual RivieraWaves Release Date 2012 02 06 NN Reference in Wireless The JTAG connector has a layout as follows top view Using iMPACT Boundary Scan the JTAG chain appears like this ISPIJBPI EE pA xcBslx150 bypass TDO 1 Programming the FPGA directly Direct JTAG programming of the Spartan 6 FPGA is volatile and the FPGA will lose its configuration every time the board power is cycled For sustained use of an FPGA design programming the design into the Flash memory is recommended see 2 and 3 below Direct JTAG programming using bit files is useful for fast temporary programming during development of FPGA programs Right click the icon representing the Spartan 6 FPGA and choose Assign New Configuration File Navigate to your bit file and choose OPEN The next dialogue box will offer to add a flash memory and you should decline Right click the icon representing the Spartan 6 FPGA and choose Program On the next dialogue box ensure that the Verify box is not checked If it is you should uncheck it failure to do this will result in error messages being displayed Click OK The Spartan 6 will program This process is very quick typically one second Confidential O 2012 RivieraWaves Page 54 of 58 Title Bubble board Use
18. The Bubble has two PS2 ports which connect the FPGA through bus switches and hence 5 tolerant These can be used to connect to a keyboard and mouse or for other user defined functions The connections to the FPGA are shown below Connector 1 is defined as the connector on the left PIN 1 LEFT G4 PIN 2 G3 PIN 3 Wired to PIN 5 Wired to 5V PIN 6 G7 PIN 8 F2 CONNECTOR2 PIN 1 RIGHT H5 CONNECTOR2 PIN 2 CONNECTOR2 PIN 3 Wired to OV CONNECTOR2 PIN 5 Wired to 5V CONNECTOR2 PIN 6 H6 CONNECTOR PIN 8 G6 Confidential 2012 RivieraWaves Page 41 of 58 Title Bubble board User Manual Release Date 2012 02 06 19 POWER CONNECTIONS 2 1MM JACK CONNECTOR FOR 5V SUPPLY ROW OF 20 0V CONNECTIONS ON IDC HEADER 3 2232 et d at 11137 oo oo oo oo oo oo oo oo oo MINI USB CONNECTOR COLUMN OF 20 0V COLUMN OF 20 3 3V CONNECTIONS ON CONNECTIONS ON LHS DILHEADER RHS DILHEADER Confidential O 2012 RivieraWaves Page 42 of 58 ff Title Bubble board User Manual QlvieraWaves Release Date 2012 02 06 Bubble is powered principally from the 2 1mm Jack socket A limited supply can be provided using the USB connector bu
19. Waves Page 10 of 58 Release Date 2012 02 06 Title Bubble board User Manual 4 SPI FLASH MEMORY Ci 3 P SPI FLASH MEMORY LI oo oo oo oo oo oo Bb The M25P128 SPI flash memory device configures the when it is powered providing suitable bitstream is programmed into the device The M25P128 has a capacity of 128Mbits with a single configuration bitstream for Bubble taking 4 1Mbits LX150 Any remaining space can be used for alternative configurations or code and data storage Confidential O 2012 RivieraWaves Page 11 of 58 Title Bubble board User Manual Release Date 2012 02 06 After configuration the SPI Flash can be accessed via the following pins of the FPGA CCLK Y21 MOSI AB20 WRITE V15 DIN AA20 CSO B T5 The HOLD pin of this memory device is permanently connected to 3 3V RiyigaWaves A The flash memory can be programmed using direct SPI programming from the 7x2 programming connector 78 To achieve this the jumper J14 must be connected between pins 1 and 2 left position Otherwise the jumper J14 should be connected between pins 2 and 3 right position so that normal JTAG programming can be achieved The connections to the SPI flash ca
20. e 2012 02 06 List of Figures Fig re 2 1 B bble front VIEW iecore te 7 Figure 2 2 Bubble Back View Confidential 2012 RivieraWaves Page 4 of 58 Title Bubble board User Manual Release Date 2012 02 06 List of Tables No table of figures entries found Confidential 2012 RivieraWaves RivieraWaves NN Page 5 of 58 Title Bubble board User Manual RivieraWaves Release Date 2012 02 06 NN Reference in Wireless 1 Introduction Welcome to your Bubble board Bubble is a Spartan 6 based FPGA development board offering a highly powerful flexible and low cost approach to prototyping FPGA and System designs The aim of this manual is to assist in using the main features of Bubble There are features that are beyond the scope of the manual Should you need to use these features then please contact RivieraWaves for detailed instructions Bubble currently comes with a XC6SLX150 2FGG484C or XC6SLX75 2FGG484C Spartan 6 Bubble is supported by the Ripple RF daughter board which contains a radio chip compliant with Bluetooth 4 0 Confidential 2012 RivieraWaves Page 6 of 58 Release Date 2012 02 06 Title Bubble board User Manual 2 Getting Started POWER SWITCH 2 1MM JACK 20 IO s on IDC FOR 5V HEADER SUPPLY 2X16 LCD DISPLAY TETTTTTTTYTTTTTUT OM 13 LEDs IGBIT DDR3 a MEMORY SPARTAN6 T v Scc FPGA 2 PUSH
21. n also be accessed via the USB interface This option requires the jumper J14 to be connected between pins 2 and 3 left position The connections between the USB interface and the SPI flash memory are shown below CCLK BDBUSO 38 MOSI BDBUS1 39 DIN BDBUS2 40 CSO B BDBUS3 41 Confidential O 2012 RivieraWaves Page 12 of 58 Release Date 2012 02 06 Reference in Wireless Title Bubble board User Manual NN 5 DDR3 MEMORY Li IGBIT DDR3 00000 Kw ae 6 6 6 a o o gt o o no Lo Bubble has 1GBIT DDR3 Micron 4 1064 16 device as standard This device is organised as 8 Meg x 16 x 8 banks This device is supported by the hard core memory controller that is in the Spartan 6 FPGA To add this core to your design the COREGEN tool part of the ISE suite will generate implementation templates in VHDL or Verilog for the configuration that you want to use More details on the memory controller can be found in the user guide http www xilinx com support documentation user guides ug388 pdf Confidential O 2012 RivieraWaves Page 13 of 58 Release Date 2012 02 06 u Title Bubble board User Manual The DDR3 has 12 address lines and 16 data lines to address all the available memory which be accessed a
22. nfiguration Rate The default setting is 2 Increase this number The maximum value we suggest is 22 Choose Apply and 4 Generate the program file as normal Confidential O 2012 RivieraWaves Page 55 of 58 Title Bubble board User Manual Ri Release Date 2012 02 06 24 MECHANICAL ARRANGEMENT The Dimensions on the drawings below are millimetres mm All sizes quoted are subject to manufacturing tolerances and should only be used as a general guide 34mm JAN D 3 25 TYTTYTITTTTTITIITITIT 71 65mm Confidential O 2012 RivieraWaves Page 56 of 58 Title Bubble board User Manual Release Date 2012 02 06 Locations of mounting holes and headers The socket pins on the DIL headers are arranged on a 2 45mm 0 1inch pitch LITT 94 45 45mm N Location of Expansion headers measured to holes for locating pegs Confidential 2012 RivieraWaves Page 57 of 58 22 777 Title Bubble board User Manual QlvigraWavee AA Release Date 2012 02 06 The heights of the components measured from the lower surface of the board are as follows Upper surface of LCD display 12 5mm Ethernet connector 15 3mm USB connector 5 5mm PS2 connectors 14 7mm Micro SD card holder measured from top surface of PCB to bottom of SD card holder 2 6mm The PCB is 1 6mm thick Confidential 2012 RivieraWaves Page 58 of 58
23. nt UK n BATTERY HOLDER FOR REAL TIME CLOCK The Bubble has a Maxim DS1306EN Serial Alarm Real time clock device with a 32 768KHz crystal Further information and datasheets for this device can be found on http ww maxim ic com The DS1306EN can provide a 32 768KHz clock timed interrupts and data storage features Please consult the device datasheet for more details The DS1306EN is supported by a battery holder that can take CR1220 1225 battery types We do not normally supply the battery to avoid shipping issues with batteries Confidential O 2012 RivieraWaves Page 28 of 58 Title Bubble board User Manual Release Date 2012 02 06 Ryig Waves W The connections between the Real Time Clock device and the FPGA are shown below 1HZ 9 F1 SDI 15 01 8 F5 INTO 7 F3 32KHZ 18 E1 SDO 16 E3 SCLK 14 C4 CE 12 B1 Confidential O 2012 RivieraWaves Page 29 of 58 Release Date 2012 02 06 Title Bubble board User Manual 12 POWER MONITOR AND MASTER RESET The Bubble has a voltage monitor which monitors the 3 3V 1 2V and 0 75V supplies within the board If any of these voltages are missing the reset signal is held active Connector J2 found at the very top left of the board provides a manual reset facility Placing a jumper between the centre pin of J2 and the leftmost pin pin 1 OV will cause an active reset signal
24. oard User Manual 7 USB aa 2232 DEVICE MINI B USB SOCKET The USB interface on the Bubble board is achieved using an FT2232H USB 2 0 High Speed 480Mb s to UART FIFO device which can operate as a USB to dual serial parallel ports with a variety of configurations The datasheet and drivers for this device are available from http www ftdichip com When appropriate drivers are installed the Bubble USB port should be detected as a serial port Alternative data optimized drivers are also available from FTDI Confidential O 2012 RivieraWaves Page 19 of 58 MM Title Bubble board User Manual QivieraWaves Release Date 2012 02 06 The FT2232H is connected to the Spartan 6 and has the capability of being configured in a variety of industry standard serial or parallel interfaces It is supported by an AT93CA6E 1Kbit serial EEPROM which is used for configuration data The FT2232H device is also connected into the JTAG chain for the FPGA so that reconfiguration of the FPGA over USB is possible Jumper J14 will need to be set to the right position between pins 2 and 3 for this to be possible The connections between the USB device and the FPGA are shown below SIGNAL FT2232H PIN FPGA PIN ADBUSO 16 M7 ADBUS1 17 7 ADBUS2 18 N1 ADBUS3 19 N4 ADBUS4 21 N3 ADBUS5 22 P7 ADBUS6 23 P6
25. of 58 Release Date 2012 02 06 22 777 Title Bubble board User Manual NN ove This serial memory has 2048 words of 8 bits and employs a byte or page programming system It can run at speeds up to 400 kHz The EEPROM has the following connections to the FPGA SDA H1 SCL H2 WP G1 The address pins on this device are wired to Confidential 2012 RivieraWaves Page 35 of 58 Title Bubble board User Manual Release Date 2012 02 06 V f Reference in Wireless 16 MICRO SD CARD HOLDER SD CARD HOLDER Further access to data can be achieved using the Micro SD Card Socket which is situated on the back of the Bubble board To use this socket in a design you may need to obtain a license from the SD Association at http www sdcard org home Confidential 2012 RivieraWaves Page 36 of 58 Release Date 2012 02 06 22 777 Title Bubble board User Manual The connections between the Micro SD Card Socket and the are shown below DATA 0 Y2 DATA 1 w3 DATA 2 V1 DATA 3 v2 CMD w1 CLK POWER M1 The POWER ON N pin must be set LOW for power to be supplied to the SDCARD Reader Confidential O 2012 RivieraWaves Page 37 of 58 Release Date 2012 02 06 Reference in Wireless Title Bubble board User Manual 17 ACCELEROMETER v s
26. r Manual RivieraWaves Release Date 2012 02 06 NN Reference in Wireless 2 Programming the SPI flash memory using Boundary Scan Once the SPI Flash memory has been programmed the Spartan 6 device will automatically load from the Flash memory at power up Generation of suitable Flash memory files mcs can be achieved using ISE iMPACT s Prom File Formatter Right click on the icon representing the Spartan 6 and choose Add SPI BPI Flash Navigate to your programming file mcs and click OPEN Use the next dialogue box to select SPI flash and M25P128 Data width should be set to 1 The flash memory should appear as shown below xcb5slx150 bypass Right click on the icon representing the flash memory and choose Program to load your program into the device It is recommended that options to Verify and Erase before programming are chosen Otherwise all defaults can be accepted The programming operation will take some time at least 3 or 4 minutes Depending upon the settings used when generating the bitfile using ISE it will take up to 20 seconds for the XC6LX150 to configure upon power up In order to decrease this time the following process can be followed 1 In the main ISE menu right click Generate Programming file Choose Properties On the left hand side of the Process Properties Dialogue box choose Configuration Options 3 The first item on the menu which appears on the right hand side of the dialogue box is Co
27. t since the current available from a USB port be as low as 100mA this should be avoided unless you know that your design does not consume more current than this A powered USB hub or a USB power supply can also be used Whatever power supply is used care should be taken not to exceed 5 5V input as this can cause damage to the Bubble The power from the jack connector is limited by a 2 6A resettable fuse and the power from the USB connector is limited by a 1 1A resettable fuse OV and 3 3V are available on the DIL headers to power add on modules or the user s hardware The maximum current available from the 3 3v regulator is 6 amps however the actual maximum current available will be limited by the fuse on the 5v supply Confidential 2012 RivieraWaves Page 43 of 58 Release Date 2012 02 06 Reference in Wireless Title Bubble board User Manual 20 POWER REGULATORS EE LUN 4 0 75V rn EH PH TR REGULATOR ptm wie 92 1 2 2219 3 0679 REGULATOR 1 5 00 12 gt 3 T Bubble has four regulators supplying 3 3V 1 5V 1 2V and 0 75V power rails Confidential O 2012 RivieraWaves Page 44 of 58 ff Title Bubble board User Manual QlvieraWaves NY Release Date 2012 02 06 WARNING REGULATORS CAN BECOME HOT IN NORMAL OPERATION ALONG WITH THE BOARDS THERMAL RELIEF PLEASE DO NOT T
28. t speeds of 1 87ns More details of the DDR3 can be found in http download micron com pdf datasheets dram ddr3 1Gb DDR3 SDRAM pdf For OEM applications we can fit bigger DDR3 parts subject to limitations of the memory controller The DDR3 site has the following connections to the FPGA DDR3 FUNCTION FPGA PIN DDR3 FUNCTION FPGA PIN F21 DDR M22 F22 DDR 004 J20 E22 DDR 5 J22 DDR K21 DDR 007 K22 DDR_DQ8 P21 DDR DQ9 P22 DDR 0010 R20 DDR 0011 R22 DDR 0012 U20 DDR 0013 U22 DDR 0014 V21 DDR_DQ15 V22 DDR_LDM DDR LDOS DDR 1095 DDR UDM DDR UDOS DDR 0095 Confidential O 2012 RivieraWaves Page 14 of 58 Release Date 2012 02 06 Title Bubble board User Manual NN DDR CS N DDR RESET N DDR DQO DDR 1 DDR 2 The signals shown shaded in yellow are terminated using suitable arrangements of resistors A timing loop has been implemented on the PCB and connected to the FPGA between pins R19 and P18 to facilitate compensation for temperature and timing delays where necessary Confidential O 2012 RivieraWaves Page 15 of 58 Release Date 2012 02 06 Title Bubble board User Manual RivieraWaves 6 DIL HEADERS 1 IO L65P
29. the top 4 Left hand side DIL Header pins This is to allow an external device connected to J100 to connect with a user s module plugged into the DIL Headers Bubble boards are normally shipped with these resistors not fitted If customer requires any of these resistors to be fitted it is advised that they specify which are required so that they can be fitted before the board is shipped Enterpoint Ltd cannot be responsible for damage to the Bubble board by poor soldering There are 6 connections between the expansion headers and the Clock Generator This is to allow an external device connected to the expansion headers to provide an alternative clock source to the 25MHz oscillator provided on Bubble to select the clock source and to access clock signals from the Clock Generator The connections between the Expansion headers and the Clock Generator are shown below SIGNAL NAME EXPANSION HEADER PIN CLOCK GENERATOR PIN EXP CLOCK B17 5 EXP CLOCK SRC SEL B16 20 EXP CLOCK SELO B13 28 EXP CLOCK SEL1 B12 27 EXP CLK1 P A18 14 EXP CLK1 N A19 15 There are two signals on the expansion header which allow the main regulators on the DN4 to be shut down for purposes of power saving REG1 EN controls the 1 2V regulator and REG2 EN controls the 3 3V regulator These signals should be asserted LOW to shut down a regulator leaving them unconnected allows the regulators to function normally Confidential O 2012 RivieraWaves Page 51 of 58 22 777 Title
30. v may be fitted Bubble is normally shipped with these resistors not fitted The DIL Headers can also support up 20 pairs of LVDS signaling when not used for add on modules The Spartan 6 FPGA can terminate any of these pairs LVDS termination on individual signal pairs is a programmable option that can be set in build constraints for the FPGA when using the ISE toolset The LVDS pairs are shown in the table above along with Spartan 6 pin numbers AA s LEFT DIL HEADER Confidential O 2012 RivieraWaves Ngora Waves W oo Ei 00 oo 06 1 22 777 Title Bubble board User Manual QlvigraWavee AA Release Date 2012 02 06 The DIL Headers can support the use of add on modules enhancing the capabilities of your Bubble board The DIL Header connectors are arranged on a standard 0 1inch 2 54mm pitch The horizontal pitch of the DIL Headers is 1 6 inches between the outer rows of the headers The inner pins of the header form continuous power strips allowing a range of modules to be used together in one header subject to sufficient pins being available The right hand side header has an inner column of 3 3V pins The LHS header has an inner column of DGND 0 Confidential 2012 RivieraWaves Page 18 of 58 Release Date 2012 02 06 Reference in Wireless Title Bubble b
Download Pdf Manuals
Related Search